revert to vlynq bus clock divisor guessing
authorNicolas Thill <nico@openwrt.org>
Mon, 1 Oct 2007 10:16:14 +0000 (10:16 +0000)
committerNicolas Thill <nico@openwrt.org>
Mon, 1 Oct 2007 10:16:14 +0000 (10:16 +0000)
SVN-Revision: 9086


No differences found