-+#define AR5312_RESETTMR (AR5312_APBBASE + 0x3000)
-+#define AR5312_TIMER (AR5312_RESETTMR + 0x0000) /* countdown timer */
-+#define AR5312_WD_CTRL (AR5312_RESETTMR + 0x0008) /* watchdog cntrl */
-+#define AR5312_WD_TIMER (AR5312_RESETTMR + 0x000c) /* watchdog timer */
-+#define AR5312_ISR (AR5312_RESETTMR + 0x0010) /* Intr Status Reg */
-+#define AR5312_IMR (AR5312_RESETTMR + 0x0014) /* Intr Mask Reg */
-+#define AR5312_RESET (AR5312_RESETTMR + 0x0020)
-+#define AR5312_CLOCKCTL1 (AR5312_RESETTMR + 0x0064)
-+#define AR5312_SCRATCH (AR5312_RESETTMR + 0x006c)
-+#define AR5312_PROCADDR (AR5312_RESETTMR + 0x0070)
-+#define AR5312_PROC1 (AR5312_RESETTMR + 0x0074)
-+#define AR5312_DMAADDR (AR5312_RESETTMR + 0x0078)
-+#define AR5312_DMA1 (AR5312_RESETTMR + 0x007c)
-+#define AR5312_ENABLE (AR5312_RESETTMR + 0x0080) /* interface enb */
-+#define AR5312_REV (AR5312_RESETTMR + 0x0090) /* revision */
++#define AR5312_TIMER 0x0000 /* countdown timer */
++#define AR5312_RELOAD 0x0004 /* timer reload value */
++#define AR5312_WD_CTRL 0x0008 /* watchdog cntrl */
++#define AR5312_WD_TIMER 0x000c /* watchdog timer */
++#define AR5312_ISR 0x0010 /* Intr Status Reg */
++#define AR5312_IMR 0x0014 /* Intr Mask Reg */
++#define AR5312_RESET 0x0020
++#define AR5312_CLOCKCTL1 0x0064
++#define AR5312_SCRATCH 0x006c
++#define AR5312_PROCADDR 0x0070
++#define AR5312_PROC1 0x0074
++#define AR5312_DMAADDR 0x0078
++#define AR5312_DMA1 0x007c
++#define AR5312_ENABLE 0x0080 /* interface enb */
++#define AR5312_REV 0x0090 /* revision */