brcm63xx: register interrupt-controllers through DT when possible
authorJonas Gorski <jogo@openwrt.org>
Mon, 1 Dec 2014 00:52:07 +0000 (00:52 +0000)
committerJonas Gorski <jogo@openwrt.org>
Mon, 1 Dec 2014 00:52:07 +0000 (00:52 +0000)
Add the required nodes for the interrupt controllers and register
them through DT when a DTB is present.

Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 43457

target/linux/brcm63xx/dts/bcm6318.dtsi
target/linux/brcm63xx/dts/bcm63268.dtsi
target/linux/brcm63xx/dts/bcm6328.dtsi
target/linux/brcm63xx/dts/bcm6338.dtsi
target/linux/brcm63xx/dts/bcm6345.dtsi
target/linux/brcm63xx/dts/bcm6348.dtsi
target/linux/brcm63xx/dts/bcm6358.dtsi
target/linux/brcm63xx/dts/bcm6362.dtsi
target/linux/brcm63xx/dts/bcm6368.dtsi
target/linux/brcm63xx/patches-3.14/373-MIPS-BCM63XX-register-interrupt-controllers-through-.patch [new file with mode: 0644]

index 370183e..723c488 100644 (file)
                };
        };
 
+       cpu_intc: interrupt-controller {
+               #address-cells = <0>;
+               compatible = "mti,cpu-interrupt-controller";
+
+               interrupt-controller;
+               #interrupt-cells = <1>;
+       };
+
        memory { device_type = "memory"; reg = <0 0>; };
 
        ubus@10000000 {
                #size-cells = <1>;
                ranges;
                compatible = "simple-bus";
+
+               ext_intc: interrupt-controller@10000018 {
+                       compatible = "brcm,bcm6345-ext-intc";
+                       reg = <0x10000018 0x4>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+
+                       interrupt-parent = <&periph_intc>;
+                       interrupts = <24>, <25>, <26>, <27>;
+               };
+
+               periph_intc: interrupt-controller@10000020 {
+                       compatible = "brcm,bcm6345-l2-intc";
+                       reg = <0x10000020 0x20>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+
+                       interrupt-parent = <&cpu_intc>;
+                       interrupts = <2>;
+               };
        };
 };
index eafa74b..214cd62 100644 (file)
                };
        };
 
+       cpu_intc: interrupt-controller {
+               #address-cells = <0>;
+               compatible = "mti,cpu-interrupt-controller";
+
+               interrupt-controller;
+               #interrupt-cells = <1>;
+       };
+
        memory { device_type = "memory"; reg = <0 0>; };
 
        ubus@10000000 {
                #size-cells = <1>;
                ranges;
                compatible = "simple-bus";
+
+               ext_intc: interrupt-controller@10000018 {
+                       compatible = "brcm,bcm6345-ext-intc";
+                       reg = <0x10000018 0x4>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+
+                       interrupt-parent = <&periph_intc>;
+                       interrupts = <44>, <45>, <46>, <47>;
+               };
+
+               periph_intc: interrupt-controller@10000020 {
+                       compatible = "brcm,bcm6345-l2-intc";
+                       reg = <0x10000020 0x20>,
+                             <0x10000040 0x20>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+
+                       interrupt-parent = <&cpu_intc>;
+                       interrupts = <2>, <3>;
+               };
        };
 };
index c9940c1..0ed186e 100644 (file)
                };
        };
 
+       cpu_intc: interrupt-controller {
+               #address-cells = <0>;
+               compatible = "mti,cpu-interrupt-controller";
+
+               interrupt-controller;
+               #interrupt-cells = <1>;
+       };
+
        memory { device_type = "memory"; reg = <0 0>; };
 
        ubus@10000000 {
                #size-cells = <1>;
                ranges;
                compatible = "simple-bus";
+
+               ext_intc: interrupt-controller@10000018 {
+                       compatible = "brcm,bcm6345-ext-intc";
+                       reg = <0x10000018 0x4>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+
+                       interrupt-parent = <&periph_intc>;
+                       interrupts = <24>, <25>, <26>, <27>;
+               };
+
+               periph_intc: interrupt-controller@10000020 {
+                       compatible = "brcm,bcm6345-l2-intc";
+                       reg = <0x10000020 0x10>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+
+                       interrupt-parent = <&cpu_intc>;
+                       interrupts = <2>;
+               };
        };
 };
index 9746e7a..b527781 100644 (file)
                };
        };
 
+       cpu_intc: interrupt-controller {
+               #address-cells = <0>;
+               compatible = "mti,cpu-interrupt-controller";
+
+               interrupt-controller;
+               #interrupt-cells = <1>;
+       };
+
        memory { device_type = "memory"; reg = <0 0>; };
 
        pflash: nor@1fc00000 {
                #size-cells = <1>;
                ranges;
                compatible = "simple-bus";
+
+               periph_intc: interrupt-controller@fffe000c {
+                       compatible = "brcm,bcm6345-l2-intc";
+                       reg = <0xfffe000c 0x8>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+
+                       interrupt-parent = <&cpu_intc>;
+                       interrupts = <2>;
+               };
+
+               ext_intc: interrupt-controller@fffe0014 {
+                       compatible = "brcm,bcm6345-ext-intc";
+                       reg = <0xfffe0014 0x4>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+
+                       interrupt-parent = <&cpu_intc>;
+                       interrupts = <3>, <4>, <5>, <6>;
+               };
        };
 };
index 03e742b..16ba8bd 100644 (file)
                };
        };
 
+       cpu_intc: interrupt-controller {
+               #address-cells = <0>;
+               compatible = "mti,cpu-interrupt-controller";
+
+               interrupt-controller;
+               #interrupt-cells = <1>;
+       };
+
        memory { device_type = "memory"; reg = <0 0>; };
 
        pflash: nor@1fc00000 {
                #size-cells = <1>;
                ranges;
                compatible = "simple-bus";
+
+               periph_intc: interrupt-controller@fffe000c {
+                       compatible = "brcm,bcm6345-l2-intc";
+                       reg = <0xfffe000c 0x9>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+
+                       interrupt-parent = <&cpu_intc>;
+                       interrupts = <2>;
+               };
+
+               ext_intc: interrupt-controller@fffe0014 {
+                       compatible = "brcm,bcm6345-ext-intc";
+                       reg = <0xfffe0014 0x4>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+
+                       interrupt-parent = <&cpu_intc>;
+                       interrupts = <3>, <4>, <5>, <6>;
+               };
        };
 };
index 404ed33..06ecbaa 100644 (file)
                };
        };
 
+       cpu_intc: interrupt-controller {
+               #address-cells = <0>;
+               compatible = "mti,cpu-interrupt-controller";
+
+               interrupt-controller;
+               #interrupt-cells = <1>;
+       };
+
        memory { device_type = "memory"; reg = <0 0>; };
 
        pflash: nor@1fc00000 {
                #size-cells = <1>;
                ranges;
                compatible = "simple-bus";
+
+               periph_intc: interrupt-controller@fffe000c {
+                       compatible = "brcm,bcm6345-l2-intc";
+                       reg = <0xfffe000c 0x8>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+
+                       interrupt-parent = <&cpu_intc>;
+                       interrupts = <2>;
+               };
+
+               ext_intc: interrupt-controller@fffe0014 {
+                       compatible = "brcm,bcm6348-ext-intc";
+                       reg = <0xfffe0014 0x4>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+
+                       interrupt-parent = <&cpu_intc>;
+                       interrupts = <3>, <4>, <5>, <6>;
+               };
        };
 };
index b376cf0..a4af214 100644 (file)
                };
        };
 
+       cpu_intc: interrupt-controller {
+               #address-cells = <0>;
+               compatible = "mti,cpu-interrupt-controller";
+
+               interrupt-controller;
+               #interrupt-cells = <1>;
+       };
+
        memory { device_type = "memory"; reg = <0 0>; };
 
        pflash: nor@1e000000 {
                #size-cells = <1>;
                ranges;
                compatible = "simple-bus";
+
+               periph_intc: interrupt-controller@fffe000c {
+                       compatible = "brcm,bcm6345-l2-intc";
+                       reg = <0xfffe000c 0x8>,
+                             <0xfffe0038 0x8>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+
+                       interrupt-parent = <&cpu_intc>;
+                       interrupts = <2>, <3>;
+               };
+
+               ext_intc0: interrupt-controller@fffe0014 {
+                       compatible = "brcm,bcm6345-ext-intc";
+                       reg = <0xfffe0014 0x4>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+
+                       interrupt-parent = <&periph_intc>;
+                       interrupts = <25>, <26>, <27>, <28>;
+               };
+
+               ext_intc1: interrupt-controller@fffe001c {
+                       compatible = "brcm,bcm6345-ext-intc";
+                       reg = <0xfffe001c 0x4>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+
+                       interrupt-parent = <&periph_intc>;
+                       interrupts = <20>, <21>;
+               };
        };
 };
index 543d24e..36765b0 100644 (file)
                };
        };
 
+       cpu_intc: interrupt-controller {
+               #address-cells = <0>;
+               compatible = "mti,cpu-interrupt-controller";
+
+               interrupt-controller;
+               #interrupt-cells = <1>;
+       };
+
        memory { device_type = "memory"; reg = <0 0>; };
 
        ubus@10000000 {
                #size-cells = <1>;
                ranges;
                compatible = "simple-bus";
+
+               ext_intc: interrupt-controller@10000018 {
+                       compatible = "brcm,bcm6345-ext-intc";
+                       reg = <0x10000018 0x4>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+
+                       interrupt-parent = <&periph_intc>;
+                       interrupts = <40>, <41>, <42>, <43>;
+               };
+
+               periph_intc: interrupt-controller@10000020 {
+                       compatible = "brcm,bcm6345-l2-intc";
+                       reg = <0x10000020 0x10>,
+                             <0x10000030 0x10>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+
+                       interrupt-parent = <&cpu_intc>;
+                       interrupts = <2>, <3>;
+               };
        };
 };
index 378f4fb..dcbbdbf 100644 (file)
                };
        };
 
+       cpu_intc: interrupt-controller {
+               #address-cells = <0>;
+               compatible = "mti,cpu-interrupt-controller";
+
+               interrupt-controller;
+               #interrupt-cells = <1>;
+       };
+
        memory { device_type = "memory"; reg = <0 0>; };
 
        ubus@10000000 {
                #size-cells = <1>;
                ranges;
                compatible = "simple-bus";
+
+               ext_intc0: interrupt-controller@10000018 {
+                       compatible = "brcm,bcm6345-ext-intc";
+                       reg = <0x10000018 0x4>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+
+                       interrupt-parent = <&periph_intc>;
+                       interrupts = <20>, <21>, <22>, <23>;
+               };
+
+               ext_intc1: interrupt-controller@1000001c {
+                       compatible = "brcm,bcm6345-ext-intc";
+                       reg = <0x1000001c 0x4>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+
+                       interrupt-parent = <&periph_intc>;
+                       interrupts = <24>, <25>;
+               };
+
+               periph_intc: interrupt-controller@10000020 {
+                       compatible = "brcm,bcm6345-l2-intc";
+                       reg = <0x10000020 0x10>,
+                             <0x10000030 0x10>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+
+                       interrupt-parent = <&cpu_intc>;
+                       interrupts = <2>, <3>;
+               };
        };
 
        pflash: nor@18000000 {
diff --git a/target/linux/brcm63xx/patches-3.14/373-MIPS-BCM63XX-register-interrupt-controllers-through-.patch b/target/linux/brcm63xx/patches-3.14/373-MIPS-BCM63XX-register-interrupt-controllers-through-.patch
new file mode 100644 (file)
index 0000000..5a74ddb
--- /dev/null
@@ -0,0 +1,38 @@
+From 7c22b08baba941a8c83072047b0d2b55a6b952aa Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Mon, 1 Dec 2014 00:20:07 +0100
+Subject: [PATCH] MIPS: BCM63XX: register interrupt controllers through DT
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/irq.c |   10 +++++++++-
+ 1 file changed, 9 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/bcm63xx/irq.c
++++ b/arch/mips/bcm63xx/irq.c
+@@ -15,6 +15,8 @@
+ #include <linux/irqchip.h>
+ #include <linux/irqchip/irq-bcm6345-ext-intc.h>
+ #include <linux/irqchip/irq-bcm6345-l2-intc.h>
++#include <linux/of.h>
++#include <linux/of_fdt.h>
+ #include <asm/irq_cpu.h>
+ #include <asm/mipsregs.h>
+ #include <bcm63xx_cpu.h>
+@@ -189,7 +191,15 @@ static void bcm63xx_init_irq(void)
+                                     ext_shift);
+ }
++static const struct of_device_id irqchip_of_match_mips_cpu_intc __used __section(__irqchip_of_table) = {
++      .compatible = "mti,cpu-interrupt-controller",
++      .data = mips_cpu_irq_of_init,
++};
++
+ void __init arch_init_irq(void)
+ {
+-      bcm63xx_init_irq();
++      if (initial_boot_params)
++              irqchip_init();
++      else
++              bcm63xx_init_irq();
+ }