[boot] move boot related packages to their own folder
authorJohn Crispin <john@openwrt.org>
Tue, 16 Oct 2012 13:44:25 +0000 (13:44 +0000)
committerJohn Crispin <john@openwrt.org>
Tue, 16 Oct 2012 13:44:25 +0000 (13:44 +0000)
SVN-Revision: 33781

208 files changed:
package/boot/fconfig/Makefile [new file with mode: 0644]
package/boot/grub2/Makefile [new file with mode: 0644]
package/boot/grub2/patches/100-grub_setup_root.patch [new file with mode: 0644]
package/boot/kexec-tools/Config.in [new file with mode: 0644]
package/boot/kexec-tools/Makefile [new file with mode: 0644]
package/boot/kexec-tools/patches/0004-mips_regdefs.patch [new file with mode: 0644]
package/boot/uboot-ar71xx/Makefile [new file with mode: 0644]
package/boot/uboot-ar71xx/files/board/zyxel/nbg460n/Makefile [new file with mode: 0644]
package/boot/uboot-ar71xx/files/board/zyxel/nbg460n/config.mk [new file with mode: 0644]
package/boot/uboot-ar71xx/files/board/zyxel/nbg460n/lowlevel_init.S [new file with mode: 0644]
package/boot/uboot-ar71xx/files/board/zyxel/nbg460n/nbg460n.c [new file with mode: 0644]
package/boot/uboot-ar71xx/files/board/zyxel/nbg460n/u-boot.lds [new file with mode: 0644]
package/boot/uboot-ar71xx/files/cpu/mips/ar71xx_serial.c [new file with mode: 0644]
package/boot/uboot-ar71xx/files/drivers/net/ag71xx.c [new file with mode: 0644]
package/boot/uboot-ar71xx/files/drivers/net/ag71xx.h [new file with mode: 0644]
package/boot/uboot-ar71xx/files/drivers/net/phy/rtl8366.h [new file with mode: 0644]
package/boot/uboot-ar71xx/files/drivers/net/phy/rtl8366_mii.c [new file with mode: 0644]
package/boot/uboot-ar71xx/files/drivers/spi/ar71xx_spi.c [new file with mode: 0644]
package/boot/uboot-ar71xx/files/include/asm-mips/ar71xx.h [new file with mode: 0644]
package/boot/uboot-ar71xx/files/include/asm-mips/ar71xx_gpio.h [new file with mode: 0644]
package/boot/uboot-ar71xx/files/include/configs/nbg460n.h [new file with mode: 0644]
package/boot/uboot-ar71xx/patches/001-ar71xx.patch [new file with mode: 0644]
package/boot/uboot-ar71xx/patches/002-ar71xx-spi.patch [new file with mode: 0644]
package/boot/uboot-ar71xx/patches/010-enet-ag71xx.patch [new file with mode: 0644]
package/boot/uboot-ar71xx/patches/011-switch-rtl8366sr.patch [new file with mode: 0644]
package/boot/uboot-ar71xx/patches/020-freebsd-compat.patch [new file with mode: 0644]
package/boot/uboot-ar71xx/patches/021-darwin_compat.patch [new file with mode: 0644]
package/boot/uboot-ar71xx/patches/022-getline_backport.patch [new file with mode: 0644]
package/boot/uboot-envtools/Makefile [new file with mode: 0644]
package/boot/uboot-envtools/files/ar71xx [new file with mode: 0644]
package/boot/uboot-envtools/files/kirkwood [new file with mode: 0644]
package/boot/uboot-envtools/files/lantiq [new file with mode: 0644]
package/boot/uboot-envtools/files/ramips [new file with mode: 0644]
package/boot/uboot-envtools/files/uboot-envtools.sh [new file with mode: 0644]
package/boot/uboot-envtools/patches/001-crc32_func_signature.patch [new file with mode: 0644]
package/boot/uboot-envtools/patches/002-makefile.patch [new file with mode: 0644]
package/boot/uboot-envtools/patches/003-nor-eraselen.patch [new file with mode: 0644]
package/boot/uboot-envtools/patches/004-allow_mac_change.patch [new file with mode: 0644]
package/boot/uboot-kirkwood/Makefile [new file with mode: 0644]
package/boot/uboot-kirkwood/files/board/iomega/iconnect/Makefile [new file with mode: 0644]
package/boot/uboot-kirkwood/files/board/iomega/iconnect/iconnect.c [new file with mode: 0644]
package/boot/uboot-kirkwood/files/board/iomega/iconnect/iconnect.h [new file with mode: 0644]
package/boot/uboot-kirkwood/files/board/iomega/iconnect/kwbimage.cfg [new file with mode: 0644]
package/boot/uboot-kirkwood/files/include/configs/iconnect.h [new file with mode: 0644]
package/boot/uboot-kirkwood/patches/0001-ib62x0.patch [new file with mode: 0644]
package/boot/uboot-kirkwood/patches/0002-kwboot.patch [new file with mode: 0644]
package/boot/uboot-kirkwood/patches/0003-ide_bus.patch [new file with mode: 0644]
package/boot/uboot-kirkwood/patches/100-iconnect.patch [new file with mode: 0644]
package/boot/uboot-kirkwood/patches/110-dockstar.patch [new file with mode: 0644]
package/boot/uboot-omap35xx/Makefile [new file with mode: 0644]
package/boot/uboot-omap35xx/files/include/configs/omap3_overo.h [new file with mode: 0644]
package/boot/uboot-omap4/Makefile [new file with mode: 0644]
package/boot/uboot-pxa/Makefile [new file with mode: 0644]
package/boot/uboot-pxa/patches/001-squashfs_rootfstype_cmdline.patch [new file with mode: 0644]
package/boot/uboot-xburst/Makefile [new file with mode: 0644]
package/boot/uboot-xburst/files/board/n516/Makefile [new file with mode: 0644]
package/boot/uboot-xburst/files/board/n516/config.mk [new file with mode: 0644]
package/boot/uboot-xburst/files/board/n516/flash.c [new file with mode: 0644]
package/boot/uboot-xburst/files/board/n516/n516.c [new file with mode: 0644]
package/boot/uboot-xburst/files/board/n516/u-boot-nand.lds [new file with mode: 0644]
package/boot/uboot-xburst/files/board/n516/u-boot.lds [new file with mode: 0644]
package/boot/uboot-xburst/files/board/nanonote/Makefile [new file with mode: 0644]
package/boot/uboot-xburst/files/board/nanonote/config.mk [new file with mode: 0644]
package/boot/uboot-xburst/files/board/nanonote/nanonote.c [new file with mode: 0644]
package/boot/uboot-xburst/files/board/nanonote/u-boot-nand.lds [new file with mode: 0644]
package/boot/uboot-xburst/files/board/nanonote/u-boot.lds [new file with mode: 0644]
package/boot/uboot-xburst/files/board/sakc/Makefile [new file with mode: 0644]
package/boot/uboot-xburst/files/board/sakc/config.mk [new file with mode: 0644]
package/boot/uboot-xburst/files/board/sakc/sakc.c [new file with mode: 0644]
package/boot/uboot-xburst/files/board/sakc/u-boot-nand.lds [new file with mode: 0644]
package/boot/uboot-xburst/files/board/sakc/u-boot.lds [new file with mode: 0644]
package/boot/uboot-xburst/files/cpu/mips/jz4740.c [new file with mode: 0644]
package/boot/uboot-xburst/files/cpu/mips/jz4740_nand.c [new file with mode: 0644]
package/boot/uboot-xburst/files/cpu/mips/jz_lcd.c [new file with mode: 0644]
package/boot/uboot-xburst/files/cpu/mips/jz_lcd.h [new file with mode: 0644]
package/boot/uboot-xburst/files/cpu/mips/jz_mmc.c [new file with mode: 0644]
package/boot/uboot-xburst/files/cpu/mips/jz_mmc.h [new file with mode: 0644]
package/boot/uboot-xburst/files/cpu/mips/jz_serial.c [new file with mode: 0644]
package/boot/uboot-xburst/files/cpu/mips/mmc_protocol.h [new file with mode: 0644]
package/boot/uboot-xburst/files/cpu/mips/nanonote_gpm940b0.c [new file with mode: 0644]
package/boot/uboot-xburst/files/cpu/mips/nanonote_gpm940b0.h [new file with mode: 0644]
package/boot/uboot-xburst/files/cpu/mips/usb_boot.S [new file with mode: 0644]
package/boot/uboot-xburst/files/include/asm-mips/jz4740.h [new file with mode: 0644]
package/boot/uboot-xburst/files/include/configs/avt2.h [new file with mode: 0644]
package/boot/uboot-xburst/files/include/configs/n516.h [new file with mode: 0644]
package/boot/uboot-xburst/files/include/configs/nanonote.h [new file with mode: 0644]
package/boot/uboot-xburst/files/include/configs/qi_lb60.h [new file with mode: 0644]
package/boot/uboot-xburst/files/include/configs/sakc.h [new file with mode: 0644]
package/boot/uboot-xburst/files/nand_spl/board/n516/Makefile [new file with mode: 0644]
package/boot/uboot-xburst/files/nand_spl/board/n516/config.mk [new file with mode: 0644]
package/boot/uboot-xburst/files/nand_spl/board/n516/u-boot.lds [new file with mode: 0644]
package/boot/uboot-xburst/files/nand_spl/board/nanonote/Makefile [new file with mode: 0644]
package/boot/uboot-xburst/files/nand_spl/board/nanonote/config.mk [new file with mode: 0644]
package/boot/uboot-xburst/files/nand_spl/board/nanonote/u-boot.lds [new file with mode: 0644]
package/boot/uboot-xburst/files/nand_spl/board/sakc/Makefile [new file with mode: 0644]
package/boot/uboot-xburst/files/nand_spl/board/sakc/config.mk [new file with mode: 0644]
package/boot/uboot-xburst/files/nand_spl/board/sakc/u-boot.lds [new file with mode: 0644]
package/boot/uboot-xburst/files/nand_spl/nand_boot_jz4740.c [new file with mode: 0644]
package/boot/uboot-xburst/patches/001-xburst.patch [new file with mode: 0644]
package/boot/uboot-xburst/patches/005-i2c.patch [new file with mode: 0644]
package/boot/uboot-xburst/patches/009-n516.patch [new file with mode: 0644]
package/boot/uboot-xburst/patches/010-sakc.patch [new file with mode: 0644]
package/boot/yamonenv/Makefile [new file with mode: 0644]
package/boot/yamonenv/patches/001-yamonenv_mtd_partition.patch [new file with mode: 0644]
package/fconfig/Makefile [deleted file]
package/grub2/Makefile [deleted file]
package/grub2/patches/100-grub_setup_root.patch [deleted file]
package/kexec-tools/Config.in [deleted file]
package/kexec-tools/Makefile [deleted file]
package/kexec-tools/patches/0004-mips_regdefs.patch [deleted file]
package/uboot-ar71xx/Makefile [deleted file]
package/uboot-ar71xx/files/board/zyxel/nbg460n/Makefile [deleted file]
package/uboot-ar71xx/files/board/zyxel/nbg460n/config.mk [deleted file]
package/uboot-ar71xx/files/board/zyxel/nbg460n/lowlevel_init.S [deleted file]
package/uboot-ar71xx/files/board/zyxel/nbg460n/nbg460n.c [deleted file]
package/uboot-ar71xx/files/board/zyxel/nbg460n/u-boot.lds [deleted file]
package/uboot-ar71xx/files/cpu/mips/ar71xx_serial.c [deleted file]
package/uboot-ar71xx/files/drivers/net/ag71xx.c [deleted file]
package/uboot-ar71xx/files/drivers/net/ag71xx.h [deleted file]
package/uboot-ar71xx/files/drivers/net/phy/rtl8366.h [deleted file]
package/uboot-ar71xx/files/drivers/net/phy/rtl8366_mii.c [deleted file]
package/uboot-ar71xx/files/drivers/spi/ar71xx_spi.c [deleted file]
package/uboot-ar71xx/files/include/asm-mips/ar71xx.h [deleted file]
package/uboot-ar71xx/files/include/asm-mips/ar71xx_gpio.h [deleted file]
package/uboot-ar71xx/files/include/configs/nbg460n.h [deleted file]
package/uboot-ar71xx/patches/001-ar71xx.patch [deleted file]
package/uboot-ar71xx/patches/002-ar71xx-spi.patch [deleted file]
package/uboot-ar71xx/patches/010-enet-ag71xx.patch [deleted file]
package/uboot-ar71xx/patches/011-switch-rtl8366sr.patch [deleted file]
package/uboot-ar71xx/patches/020-freebsd-compat.patch [deleted file]
package/uboot-ar71xx/patches/021-darwin_compat.patch [deleted file]
package/uboot-ar71xx/patches/022-getline_backport.patch [deleted file]
package/uboot-envtools/Makefile [deleted file]
package/uboot-envtools/files/ar71xx [deleted file]
package/uboot-envtools/files/kirkwood [deleted file]
package/uboot-envtools/files/lantiq [deleted file]
package/uboot-envtools/files/ramips [deleted file]
package/uboot-envtools/files/uboot-envtools.sh [deleted file]
package/uboot-envtools/patches/001-crc32_func_signature.patch [deleted file]
package/uboot-envtools/patches/002-makefile.patch [deleted file]
package/uboot-envtools/patches/003-nor-eraselen.patch [deleted file]
package/uboot-envtools/patches/004-allow_mac_change.patch [deleted file]
package/uboot-kirkwood/Makefile [deleted file]
package/uboot-kirkwood/files/board/iomega/iconnect/Makefile [deleted file]
package/uboot-kirkwood/files/board/iomega/iconnect/iconnect.c [deleted file]
package/uboot-kirkwood/files/board/iomega/iconnect/iconnect.h [deleted file]
package/uboot-kirkwood/files/board/iomega/iconnect/kwbimage.cfg [deleted file]
package/uboot-kirkwood/files/include/configs/iconnect.h [deleted file]
package/uboot-kirkwood/patches/0001-ib62x0.patch [deleted file]
package/uboot-kirkwood/patches/0002-kwboot.patch [deleted file]
package/uboot-kirkwood/patches/0003-ide_bus.patch [deleted file]
package/uboot-kirkwood/patches/100-iconnect.patch [deleted file]
package/uboot-kirkwood/patches/110-dockstar.patch [deleted file]
package/uboot-omap35xx/Makefile [deleted file]
package/uboot-omap35xx/files/include/configs/omap3_overo.h [deleted file]
package/uboot-omap4/Makefile [deleted file]
package/uboot-pxa/Makefile [deleted file]
package/uboot-pxa/patches/001-squashfs_rootfstype_cmdline.patch [deleted file]
package/uboot-xburst/Makefile [deleted file]
package/uboot-xburst/files/board/n516/Makefile [deleted file]
package/uboot-xburst/files/board/n516/config.mk [deleted file]
package/uboot-xburst/files/board/n516/flash.c [deleted file]
package/uboot-xburst/files/board/n516/n516.c [deleted file]
package/uboot-xburst/files/board/n516/u-boot-nand.lds [deleted file]
package/uboot-xburst/files/board/n516/u-boot.lds [deleted file]
package/uboot-xburst/files/board/nanonote/Makefile [deleted file]
package/uboot-xburst/files/board/nanonote/config.mk [deleted file]
package/uboot-xburst/files/board/nanonote/nanonote.c [deleted file]
package/uboot-xburst/files/board/nanonote/u-boot-nand.lds [deleted file]
package/uboot-xburst/files/board/nanonote/u-boot.lds [deleted file]
package/uboot-xburst/files/board/sakc/Makefile [deleted file]
package/uboot-xburst/files/board/sakc/config.mk [deleted file]
package/uboot-xburst/files/board/sakc/sakc.c [deleted file]
package/uboot-xburst/files/board/sakc/u-boot-nand.lds [deleted file]
package/uboot-xburst/files/board/sakc/u-boot.lds [deleted file]
package/uboot-xburst/files/cpu/mips/jz4740.c [deleted file]
package/uboot-xburst/files/cpu/mips/jz4740_nand.c [deleted file]
package/uboot-xburst/files/cpu/mips/jz_lcd.c [deleted file]
package/uboot-xburst/files/cpu/mips/jz_lcd.h [deleted file]
package/uboot-xburst/files/cpu/mips/jz_mmc.c [deleted file]
package/uboot-xburst/files/cpu/mips/jz_mmc.h [deleted file]
package/uboot-xburst/files/cpu/mips/jz_serial.c [deleted file]
package/uboot-xburst/files/cpu/mips/mmc_protocol.h [deleted file]
package/uboot-xburst/files/cpu/mips/nanonote_gpm940b0.c [deleted file]
package/uboot-xburst/files/cpu/mips/nanonote_gpm940b0.h [deleted file]
package/uboot-xburst/files/cpu/mips/usb_boot.S [deleted file]
package/uboot-xburst/files/include/asm-mips/jz4740.h [deleted file]
package/uboot-xburst/files/include/configs/avt2.h [deleted file]
package/uboot-xburst/files/include/configs/n516.h [deleted file]
package/uboot-xburst/files/include/configs/nanonote.h [deleted file]
package/uboot-xburst/files/include/configs/qi_lb60.h [deleted file]
package/uboot-xburst/files/include/configs/sakc.h [deleted file]
package/uboot-xburst/files/nand_spl/board/n516/Makefile [deleted file]
package/uboot-xburst/files/nand_spl/board/n516/config.mk [deleted file]
package/uboot-xburst/files/nand_spl/board/n516/u-boot.lds [deleted file]
package/uboot-xburst/files/nand_spl/board/nanonote/Makefile [deleted file]
package/uboot-xburst/files/nand_spl/board/nanonote/config.mk [deleted file]
package/uboot-xburst/files/nand_spl/board/nanonote/u-boot.lds [deleted file]
package/uboot-xburst/files/nand_spl/board/sakc/Makefile [deleted file]
package/uboot-xburst/files/nand_spl/board/sakc/config.mk [deleted file]
package/uboot-xburst/files/nand_spl/board/sakc/u-boot.lds [deleted file]
package/uboot-xburst/files/nand_spl/nand_boot_jz4740.c [deleted file]
package/uboot-xburst/patches/001-xburst.patch [deleted file]
package/uboot-xburst/patches/005-i2c.patch [deleted file]
package/uboot-xburst/patches/009-n516.patch [deleted file]
package/uboot-xburst/patches/010-sakc.patch [deleted file]
package/yamonenv/Makefile [deleted file]
package/yamonenv/patches/001-yamonenv_mtd_partition.patch [deleted file]

diff --git a/package/boot/fconfig/Makefile b/package/boot/fconfig/Makefile
new file mode 100644 (file)
index 0000000..14bbec5
--- /dev/null
@@ -0,0 +1,45 @@
+#
+# Copyright (C) 2006-2008 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+include $(TOPDIR)/rules.mk
+
+PKG_NAME:=fconfig
+PKG_VERSION:=20080329
+PKG_RELEASE:=1
+
+PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
+PKG_SOURCE_URL:=http://andrzejekiert.ovh.org/software/fconfig/
+PKG_MD5SUM:=dac355e9f2a0f48c414c52e2034b6346
+
+PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)
+
+include $(INCLUDE_DIR)/package.mk
+
+define Package/fconfig
+  SECTION:=utils
+  CATEGORY:=Utilities
+  TITLE:=RedBoot configuration editor
+  URL:=http://andrzejekiert.ovh.org/software.html.en
+endef
+
+define Package/fconfig/description
+       displays and (if writable) also edits the RedBoot configuration.
+endef
+
+define Build/Configure
+endef
+
+define Build/Compile
+       $(call Build/Compile/Default)
+endef
+
+define Package/fconfig/install
+       $(INSTALL_DIR) $(1)/usr/sbin
+       $(INSTALL_BIN) $(PKG_BUILD_DIR)/fconfig $(1)/usr/sbin/
+endef
+
+$(eval $(call BuildPackage,fconfig))
diff --git a/package/boot/grub2/Makefile b/package/boot/grub2/Makefile
new file mode 100644 (file)
index 0000000..b606f54
--- /dev/null
@@ -0,0 +1,51 @@
+#
+# Copyright (C) 2006-2010 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/kernel.mk
+
+PKG_NAME:=grub
+PKG_VERSION:=2.00
+PKG_RELEASE:=1
+
+PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
+PKG_SOURCE_URL:=@GNU/grub
+PKG_MD5SUM:=e927540b6eda8b024fb0391eeaa4091c
+
+PKG_HOST_ONLY:=1
+HOST_BUILD_PARALLEL:=1
+PKG_BUILD_DEPENDS:=grub2/host
+
+include $(INCLUDE_DIR)/host-build.mk
+include $(INCLUDE_DIR)/package.mk
+
+define Package/grub2
+  SUBMENU:=Boot Loaders
+  CATEGORY:=Utilities
+  SECTION:=utils
+  TITLE:=GRand Unified Bootloader
+  URL:=http://www.gnu.org/software/grub/
+  DEPENDS:=@TARGET_x86
+endef
+
+HOST_CONFIGURE_ARGS += \
+       --target=$(REAL_GNU_TARGET_NAME) \
+       --sbindir="$(STAGING_DIR_HOST)/bin" \
+       --disable-werror \
+       --disable-nls
+
+HOST_MAKE_FLAGS += \
+       TARGET_RANLIB=$(TARGET_RANLIB) \
+       LIBLZMA=$(STAGING_DIR_HOST)/lib/liblzma.a
+
+define Host/Configure
+       $(SED) 's,(RANLIB),(TARGET_RANLIB),' $(HOST_BUILD_DIR)/grub-core/Makefile.in
+       $(Host/Configure/Default)
+endef
+
+$(eval $(call HostBuild))
+$(eval $(call BuildPackage,grub2))
diff --git a/package/boot/grub2/patches/100-grub_setup_root.patch b/package/boot/grub2/patches/100-grub_setup_root.patch
new file mode 100644 (file)
index 0000000..7775b2a
--- /dev/null
@@ -0,0 +1,77 @@
+--- a/util/grub-setup.c
++++ b/util/grub-setup.c
+@@ -141,12 +141,11 @@ write_rootdev (char *core_img, grub_devi
+ static void
+ setup (const char *dir,
+        const char *boot_file, const char *core_file,
+-       const char *dest, int force,
++       const char *root, const char *dest, int force,
+        int fs_probe, int allow_floppy)
+ {
+   char *boot_path, *core_path, *core_path_dev, *core_path_dev_full;
+   char *boot_img, *core_img;
+-  char *root = 0;
+   size_t boot_size, core_size;
+   grub_uint16_t core_sectors;
+   grub_device_t root_dev = 0, dest_dev, core_dev;
+@@ -253,7 +252,10 @@ setup (const char *dir,
+   core_dev = dest_dev;
+-  {
++  if (root)
++    root_dev = grub_device_open(root);
++
++  if (!root_dev) {
+     char **root_devices = grub_guess_root_devices (dir);
+     char **cur;
+     int found = 0;
+@@ -263,6 +265,8 @@ setup (const char *dir,
+       char *drive;
+       grub_device_t try_dev;
++      if (root_dev)
++        break;
+       drive = grub_util_get_grub_dev (*cur);
+       if (!drive)
+         continue;
+@@ -956,6 +960,8 @@ static struct argp_option options[] = {
+    N_("install even if problems are detected"), 0},
+   {"skip-fs-probe",'s',0,      0,
+    N_("do not probe for filesystems in DEVICE"), 0},
++  {"root-device", 'r', N_("DEVICE"), 0,
++   N_("use DEVICE as the root device"), 0},
+   {"verbose",     'v', 0,      0, N_("print verbose messages."), 0},
+   {"allow-floppy", 'a', 0,      0,
+    /* TRANSLATORS: The potential breakage isn't limited to floppies but it's
+@@ -993,6 +999,7 @@ struct arguments
+   char *core_file;
+   char *dir;
+   char *dev_map;
++  char *root_dev;
+   int  force;
+   int  fs_probe;
+   int allow_floppy;
+@@ -1040,6 +1047,13 @@ argp_parser (int key, char *arg, struct 
+         arguments->dev_map = xstrdup (arg);
+         break;
++      case 'r':
++        if (arguments->root_dev)
++          free (arguments->root_dev);
++
++        arguments->root_dev = xstrdup (arg);
++        break;
++
+       case 'f':
+         arguments->force = 1;
+         break;
+@@ -1172,7 +1186,7 @@ main (int argc, char *argv[])
+   setup (arguments.dir ? : DEFAULT_DIRECTORY,
+        arguments.boot_file ? : DEFAULT_BOOT_FILE,
+        arguments.core_file ? : DEFAULT_CORE_FILE,
+-       dest_dev, arguments.force,
++       arguments.root_dev, dest_dev, arguments.force,
+        arguments.fs_probe, arguments.allow_floppy);
+   /* Free resources.  */
diff --git a/package/boot/kexec-tools/Config.in b/package/boot/kexec-tools/Config.in
new file mode 100644 (file)
index 0000000..60c819d
--- /dev/null
@@ -0,0 +1,21 @@
+menu "Configuration"
+       depends on PACKAGE_kexec-tools
+
+config KEXEC_TOOLS_TARGET_NAME
+       string
+       prompt "Target name for kexec kernel"
+       default EXTRA_TARGET_ARCH_NAME  if powerpc64
+       default ARCH
+       help
+         Defines the target type of the kernels that kexec deals
+         with. This should be the target specification of
+         the kernel you're booting.
+
+config KEXEC_TOOLS_kdump
+       bool
+       prompt "kdump support"
+       default n
+       help
+         Include the kdump utility.
+
+endmenu
diff --git a/package/boot/kexec-tools/Makefile b/package/boot/kexec-tools/Makefile
new file mode 100644 (file)
index 0000000..fa4f4d8
--- /dev/null
@@ -0,0 +1,80 @@
+#
+# Copyright (C) 2006-2012 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+include $(TOPDIR)/rules.mk
+
+PKG_NAME:=kexec-tools
+PKG_VERSION:=2.0.3
+PKG_RELEASE:=1
+
+PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
+PKG_SOURCE_URL:=@KERNEL/linux/utils/kernel/kexec
+PKG_MD5SUM:=b3ced2097ce3981abba38ceedc84f939
+
+PKG_FIXUP:=autoreconf
+
+include $(INCLUDE_DIR)/package.mk
+
+define Package/kexec-tools
+  SECTION:=utils
+  CATEGORY:=Utilities
+  DEPENDS:=@armeb||@arm||@i386||@powerpc64||@mipsel||@mips +zlib
+  TITLE:=Kernel boots kernel
+  URL:=http://kernel.org/pub/linux/kernel/people/horms/kexec-tools/
+  MAINTAINER:=Florian Fainelli <florian@openwrt.org>
+  MENU:=1
+endef
+
+define Package/kexec-tools/description
+ kexec is a set of systems call that allows you to load
+ another kernel from the currently executing Linux kernel.
+endef
+
+define Package/kexec-tools/config
+       source "$(SOURCE)/Config.in"
+endef
+
+KEXEC_TARGET_NAME:=$(call qstrip,$(CONFIG_KEXEC_TOOLS_TARGET_NAME))-linux-$(TARGET_SUFFIX)
+
+CONFIGURE_ARGS = \
+               --target=$(KEXEC_TARGET_NAME) \
+               --host=$(REAL_GNU_TARGET_NAME) \
+               --build=$(GNU_HOST_NAME) \
+               --program-prefix="" \
+               --program-suffix="" \
+               --prefix=/usr \
+               --exec-prefix=/usr \
+               --bindir=/usr/bin \
+               --sbindir=/usr/sbin \
+               --libexecdir=/usr/lib \
+               --sysconfdir=/etc
+
+CONFIGURE_VARS += \
+       BUILD_CC="$(HOSTCC)" \
+       TARGET_CC="$(TARGET_CC)"
+
+kexec-extra-sbin-$(CONFIG_KEXEC_TOOLS_kdump) += kdump
+
+define Build/Compile
+       $(MAKE) -C $(PKG_BUILD_DIR) DESTDIR="$(PKG_INSTALL_DIR)" all install
+endef
+
+define Package/kexec-tools/install
+       $(INSTALL_DIR) $(1)/usr/sbin
+       $(INSTALL_BIN) \
+               $(addprefix $(PKG_INSTALL_DIR)/usr/sbin/, \
+                       $(kexec-extra-sbin-y)) \
+               $(kexec-extra-bin-y) \
+               $(PKG_INSTALL_DIR)/usr/sbin/kexec \
+               $(1)/usr/sbin
+
+# make a link for compatability with other distros
+       $(INSTALL_DIR) $(1)/sbin
+       ln -s /usr/sbin/kexec $(1)/sbin/kexec
+endef
+
+$(eval $(call BuildPackage,kexec-tools))
diff --git a/package/boot/kexec-tools/patches/0004-mips_regdefs.patch b/package/boot/kexec-tools/patches/0004-mips_regdefs.patch
new file mode 100644 (file)
index 0000000..7e21349
--- /dev/null
@@ -0,0 +1,103 @@
+--- /dev/null
++++ b/kexec/arch/mips/regdef.h
+@@ -0,0 +1,100 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 1985 MIPS Computer Systems, Inc.
++ * Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle
++ * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
++ */
++#ifndef _ASM_REGDEF_H
++#define _ASM_REGDEF_H
++
++#include <asm/sgidefs.h>
++
++#if _MIPS_SIM == _MIPS_SIM_ABI32
++
++/*
++ * Symbolic register names for 32 bit ABI
++ */
++#define zero    $0      /* wired zero */
++#define AT      $1      /* assembler temp  - uppercase because of ".set at" */
++#define v0      $2      /* return value */
++#define v1      $3
++#define a0      $4      /* argument registers */
++#define a1      $5
++#define a2      $6
++#define a3      $7
++#define t0      $8      /* caller saved */
++#define t1      $9
++#define t2      $10
++#define t3      $11
++#define t4      $12
++#define t5      $13
++#define t6      $14
++#define t7      $15
++#define s0      $16     /* callee saved */
++#define s1      $17
++#define s2      $18
++#define s3      $19
++#define s4      $20
++#define s5      $21
++#define s6      $22
++#define s7      $23
++#define t8      $24     /* caller saved */
++#define t9      $25
++#define jp      $25     /* PIC jump register */
++#define k0      $26     /* kernel scratch */
++#define k1      $27
++#define gp      $28     /* global pointer */
++#define sp      $29     /* stack pointer */
++#define fp      $30     /* frame pointer */
++#define s8    $30     /* same like fp! */
++#define ra      $31     /* return address */
++
++#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
++
++#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
++
++#define zero  $0      /* wired zero */
++#define AT    $at     /* assembler temp - uppercase because of ".set at" */
++#define v0    $2      /* return value - caller saved */
++#define v1    $3
++#define a0    $4      /* argument registers */
++#define a1    $5
++#define a2    $6
++#define a3    $7
++#define a4    $8      /* arg reg 64 bit; caller saved in 32 bit */
++#define ta0   $8
++#define a5    $9
++#define ta1   $9
++#define a6    $10
++#define ta2   $10
++#define a7    $11
++#define ta3   $11
++#define t0    $12     /* caller saved */
++#define t1    $13
++#define t2    $14
++#define t3    $15
++#define s0    $16     /* callee saved */
++#define s1    $17
++#define s2    $18
++#define s3    $19
++#define s4    $20
++#define s5    $21
++#define s6    $22
++#define s7    $23
++#define t8    $24     /* caller saved */
++#define t9    $25     /* callee address for PIC/temp */
++#define jp    $25     /* PIC jump register */
++#define k0    $26     /* kernel temporary */
++#define k1    $27
++#define gp    $28     /* global pointer - caller saved for PIC */
++#define sp    $29     /* stack pointer */
++#define fp    $30     /* frame pointer */
++#define s8    $30     /* callee saved */
++#define ra    $31     /* return address */
++
++#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
++
++#endif /* _ASM_REGDEF_H */
diff --git a/package/boot/uboot-ar71xx/Makefile b/package/boot/uboot-ar71xx/Makefile
new file mode 100644 (file)
index 0000000..ab692d5
--- /dev/null
@@ -0,0 +1,90 @@
+#
+# Copyright (C) 2010 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/kernel.mk
+
+PKG_NAME:=u-boot
+PKG_VERSION:=2010.03
+PKG_RELEASE:=1
+
+PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
+PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
+PKG_SOURCE_URL:=ftp://ftp.denx.de/pub/u-boot
+PKG_MD5SUM:=
+PKG_TARGETS:=bin
+
+include $(INCLUDE_DIR)/package.mk
+
+define uboot/Default
+  TITLE:=
+  CONFIG:=
+  IMAGE:=
+endef
+
+define uboot/nbg460n_550n_550nh
+  TITLE:=U-boot for the NBG460N/550N/550NH routers
+endef
+
+UBOOTS:=nbg460n_550n_550nh
+
+define Package/uboot/template
+define Package/uboot-ar71xx-$(1)
+  SECTION:=boot
+  CATEGORY:=Boot Loaders
+  TITLE:=$(2)
+  DEPENDS:=@TARGET_ar71xx
+  URL:=http://www.denx.de/wiki/U-Boot
+  DEFAULT:=y if (TARGET_ar71xx_generic_NBG_460N_550N_550NH || TARGET_ar71xx_generic_Default || CONFIG_TARGET_ar71xx_generic_Minimal)
+  VARIANT:=$(1)
+endef
+endef
+
+define BuildUbootPackage
+       $(eval $(uboot/Default))
+       $(eval $(uboot/$(1)))
+       $(call Package/uboot/template,$(1),$(TITLE))
+endef
+
+
+ifdef BUILD_VARIANT
+$(eval $(call uboot/$(BUILD_VARIANT)))
+UBOOT_CONFIG:=$(if $(CONFIG),$(CONFIG),$(BUILD_VARIANT))
+UBOOT_IMAGE:=$(if $(IMAGE),$(IMAGE),openwrt-$(BOARD)-$(BUILD_VARIANT)-u-boot.bin)
+endif
+
+define Build/Prepare
+       $(call Build/Prepare/Default)
+       $(CP) ./files/* $(PKG_BUILD_DIR)
+       find $(PKG_BUILD_DIR) -name .svn | $(XARGS) rm -rf
+endef
+
+define Build/Configure
+       $(MAKE) -C $(PKG_BUILD_DIR) \
+               $(UBOOT_CONFIG)_config
+endef
+
+define Build/Compile
+       $(MAKE) -C $(PKG_BUILD_DIR) \
+               CROSS_COMPILE=$(TARGET_CROSS)
+endef
+
+define Package/uboot/install/template
+define Package/uboot-ar71xx-$(1)/install
+       $(INSTALL_DIR) $$(1)
+       $(CP) $(PKG_BUILD_DIR)/u-boot.bin $(BIN_DIR)/$(2)
+endef
+endef
+
+$(foreach u,$(UBOOTS), \
+       $(eval $(call Package/uboot/install/template,$(u),openwrt-$(BOARD)-$(SUBTARGET)-$(u)-u-boot.bin)) \
+)
+
+$(foreach u,$(UBOOTS), \
+       $(eval $(call BuildUbootPackage,$(u))) \
+       $(eval $(call BuildPackage,uboot-ar71xx-$(u))) \
+)
diff --git a/package/boot/uboot-ar71xx/files/board/zyxel/nbg460n/Makefile b/package/boot/uboot-ar71xx/files/board/zyxel/nbg460n/Makefile
new file mode 100644 (file)
index 0000000..b0a385b
--- /dev/null
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).a
+
+COBJS-y += $(BOARD).o
+SOBJS-y += lowlevel_init.o
+
+SRCS   := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS-y))
+SOBJS  := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):        $(obj).depend $(OBJS) $(SOBJS)
+       $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/package/boot/uboot-ar71xx/files/board/zyxel/nbg460n/config.mk b/package/boot/uboot-ar71xx/files/board/zyxel/nbg460n/config.mk
new file mode 100644 (file)
index 0000000..e042e78
--- /dev/null
@@ -0,0 +1 @@
+TEXT_BASE = 0x81E00000
diff --git a/package/boot/uboot-ar71xx/files/board/zyxel/nbg460n/lowlevel_init.S b/package/boot/uboot-ar71xx/files/board/zyxel/nbg460n/lowlevel_init.S
new file mode 100644 (file)
index 0000000..83084c8
--- /dev/null
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2010
+ * Michael Kurz <michi.kurz@googlemail.com>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+
+
+
+.globl lowlevel_init
+/*
+       All done by Bootbase, nothing to do
+*/
+lowlevel_init:
+    jr ra
+    nop
+
diff --git a/package/boot/uboot-ar71xx/files/board/zyxel/nbg460n/nbg460n.c b/package/boot/uboot-ar71xx/files/board/zyxel/nbg460n/nbg460n.c
new file mode 100644 (file)
index 0000000..03a479d
--- /dev/null
@@ -0,0 +1,96 @@
+/*
+ * (C) Copyright 2010
+ * Michael Kurz <michi.kurz@googlemail.com>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/reboot.h>
+#include <asm/ar71xx.h>
+#include <asm/ar71xx_gpio.h>
+
+#define NBG460N_WAN_LED                        19
+
+phys_size_t initdram(int board_type)
+{
+    return (32*1024*1024);
+}
+
+int checkboard(void)
+{
+       // Set pin 19 to 1, to stop WAN LED blinking
+    ar71xx_setpindir(NBG460N_WAN_LED, 1);
+    ar71xx_setpin(NBG460N_WAN_LED, 1);
+
+    printf("U-boot on Zyxel NBG460N\n");
+    return 0;
+}
+
+void _machine_restart(void)
+{
+       for (;;) {
+               writel((RESET_MODULE_FULL_CHIP | RESET_MODULE_DDR),
+                       KSEG1ADDR(AR71XX_RESET_BASE + AR91XX_RESET_REG_RESET_MODULE));
+        readl(KSEG1ADDR(AR71XX_RESET_BASE + AR91XX_RESET_REG_RESET_MODULE));
+       }
+}
+
+int board_eth_init(bd_t *bis)
+{
+    char *phynames[] = {RTL8366_DEVNAME, RTL8366_DEVNAME};
+    u16 phyids[] = {RTL8366_LANPHY_ID, RTL8366_WANPHY_ID};
+    u16 phyfixed[] = {1, 0};
+
+    if (ag71xx_register(bis, phynames, phyids, phyfixed) <= 0)
+        return -1;
+
+       if (rtl8366s_initialize())
+        return -1;
+
+    if (rtl8366_mii_register(bis))
+        return -1;
+               
+    return 0;
+}
+
+int misc_init_r(void) {
+    uint8_t macaddr[6];
+    uint8_t enetaddr[6];
+
+       debug("Testing mac addresses\n");
+       
+    memcpy(macaddr, (uint8_t *) CONFIG_ETHADDR_ADDR, 6);
+
+    if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
+        debug("Setting eth0 mac addr to %pM\n", macaddr);
+        eth_setenv_enetaddr("ethaddr", macaddr);
+    }
+
+    if (!eth_getenv_enetaddr("eth1addr", enetaddr)) {
+               macaddr[5] += 1;
+        debug("Setting eth1 mac addr to %pM\n", macaddr);
+        eth_setenv_enetaddr("eth1addr", macaddr);
+    }
+
+    return 0;
+}
diff --git a/package/boot/uboot-ar71xx/files/board/zyxel/nbg460n/u-boot.lds b/package/boot/uboot-ar71xx/files/board/zyxel/nbg460n/u-boot.lds
new file mode 100644 (file)
index 0000000..8dc2b76
--- /dev/null
@@ -0,0 +1,42 @@
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+       . = 0x00000000;
+
+       . = ALIGN(4);
+       .text       :
+       {
+         *(.text)
+       }
+
+       . = ALIGN(4);
+       .rodata  : { *(.rodata) }
+
+       . = ALIGN(4);
+       .data  : { *(.data) }
+
+       . = ALIGN(4);
+       .sdata  : { *(.sdata) }
+
+       _gp = ALIGN(16);
+
+       __got_start = .;
+       .got  : { *(.got) }
+       __got_end = .;
+
+       .sdata  : { *(.sdata) }
+
+       __u_boot_cmd_start = .;
+       .u_boot_cmd : { *(.u_boot_cmd) }
+       __u_boot_cmd_end = .;
+
+       uboot_end_data = .;
+       num_got_entries = (__got_end - __got_start) >> 2;
+
+       . = ALIGN(4);
+       .sbss  : { *(.sbss) }
+       .bss  : { *(.bss) }
+       uboot_end = .;
+}
diff --git a/package/boot/uboot-ar71xx/files/cpu/mips/ar71xx_serial.c b/package/boot/uboot-ar71xx/files/cpu/mips/ar71xx_serial.c
new file mode 100644 (file)
index 0000000..f093318
--- /dev/null
@@ -0,0 +1,177 @@
+/*
+ * (C) Copyright 2010
+ * Michael Kurz <michi.kurz@googlemail.com>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <config.h>
+#include <asm/ar71xx.h>
+
+#define                REG_SIZE                4
+
+/* === END OF CONFIG === */
+
+/* register offset */
+#define         OFS_RCV_BUFFER          (0*REG_SIZE)
+#define         OFS_TRANS_HOLD          (0*REG_SIZE)
+#define         OFS_SEND_BUFFER         (0*REG_SIZE)
+#define         OFS_INTR_ENABLE         (1*REG_SIZE)
+#define         OFS_INTR_ID             (2*REG_SIZE)
+#define         OFS_DATA_FORMAT         (3*REG_SIZE)
+#define         OFS_LINE_CONTROL        (3*REG_SIZE)
+#define         OFS_MODEM_CONTROL       (4*REG_SIZE)
+#define         OFS_RS232_OUTPUT        (4*REG_SIZE)
+#define         OFS_LINE_STATUS         (5*REG_SIZE)
+#define         OFS_MODEM_STATUS        (6*REG_SIZE)
+#define         OFS_RS232_INPUT         (6*REG_SIZE)
+#define         OFS_SCRATCH_PAD         (7*REG_SIZE)
+
+#define         OFS_DIVISOR_LSB         (0*REG_SIZE)
+#define         OFS_DIVISOR_MSB         (1*REG_SIZE)
+
+#define         UART16550_READ(y)   readl(KSEG1ADDR(AR71XX_UART_BASE+y))
+#define         UART16550_WRITE(x, z)  writel(z, KSEG1ADDR((AR71XX_UART_BASE+x)))
+
+void 
+ar71xx_sys_frequency(u32 *cpu_freq, u32 *ddr_freq, u32 *ahb_freq)
+{
+#ifndef CONFIG_AR91XX
+    u32 pll, pll_div, cpu_div, ahb_div, ddr_div, freq;
+
+    pll = readl(KSEG1ADDR(AR71XX_PLL_REG_CPU_CONFIG + AR71XX_PLL_BASE));
+
+    pll_div = 
+        ((pll & AR71XX_PLL_DIV_MASK) >> AR71XX_PLL_DIV_SHIFT) + 1;
+
+    cpu_div = 
+        ((pll & AR71XX_CPU_DIV_MASK) >> AR71XX_CPU_DIV_SHIFT) + 1;
+
+    ddr_div = 
+        ((pll & AR71XX_DDR_DIV_MASK) >> AR71XX_DDR_DIV_SHIFT) + 1;
+
+    ahb_div = 
+       (((pll & AR71XX_AHB_DIV_MASK) >> AR71XX_AHB_DIV_SHIFT) + 1)*2;
+
+    freq = pll_div * 40000000; 
+
+    if (cpu_freq)
+        *cpu_freq = freq/cpu_div;
+
+    if (ddr_freq)
+        *ddr_freq = freq/ddr_div;
+
+    if (ahb_freq)
+        *ahb_freq = (freq/cpu_div)/ahb_div;
+
+#else
+    u32 pll, pll_div, ahb_div, ddr_div, freq;
+
+    pll = readl(KSEG1ADDR(AR91XX_PLL_REG_CPU_CONFIG + AR71XX_PLL_BASE));
+
+    pll_div = 
+        ((pll & AR91XX_PLL_DIV_MASK) >> AR91XX_PLL_DIV_SHIFT);
+
+    ddr_div = 
+        ((pll & AR91XX_DDR_DIV_MASK) >> AR91XX_DDR_DIV_SHIFT) + 1;
+
+    ahb_div = 
+       (((pll & AR91XX_AHB_DIV_MASK) >> AR91XX_AHB_DIV_SHIFT) + 1)*2;
+
+    freq = pll_div * 5000000; 
+
+    if (cpu_freq)
+        *cpu_freq = freq;
+
+    if (ddr_freq)
+        *ddr_freq = freq/ddr_div;
+
+    if (ahb_freq)
+        *ahb_freq = freq/ahb_div;
+#endif
+}
+
+
+int serial_init(void)
+{
+    u32 div;
+    u32 ahb_freq = 100000000;
+
+    ar71xx_sys_frequency  (0, 0, &ahb_freq);  
+    div  = ahb_freq/(16 * CONFIG_BAUDRATE);  
+
+       // enable uart pins
+#ifndef CONFIG_AR91XX
+    writel(AR71XX_GPIO_FUNC_UART_EN, KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_FUNC));
+#else
+       writel(AR91XX_GPIO_FUNC_UART_EN, KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_FUNC));
+#endif
+
+    /* set DIAB bit */
+    UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
+
+    /* set divisor */
+    UART16550_WRITE(OFS_DIVISOR_LSB, (div & 0xff));
+    UART16550_WRITE(OFS_DIVISOR_MSB, ((div >> 8) & 0xff));
+
+    /* clear DIAB bit*/ 
+    UART16550_WRITE(OFS_LINE_CONTROL, 0x00);
+
+    /* set data format */
+    UART16550_WRITE(OFS_DATA_FORMAT, 0x3);
+
+    UART16550_WRITE(OFS_INTR_ENABLE, 0);
+
+       return 0;
+}
+
+int serial_tstc (void)
+{
+    return(UART16550_READ(OFS_LINE_STATUS) & 0x1);
+}
+
+int serial_getc(void)
+{
+    while(!serial_tstc());
+
+    return UART16550_READ(OFS_RCV_BUFFER);
+}
+
+
+void serial_putc(const char byte)
+{
+    if (byte == '\n') serial_putc ('\r');
+
+    while (((UART16550_READ(OFS_LINE_STATUS)) & 0x20) == 0x0);
+    UART16550_WRITE(OFS_SEND_BUFFER, byte);
+}
+
+void serial_setbrg (void)
+{
+}
+
+void serial_puts (const char *s)
+{
+       while (*s)
+       {
+               serial_putc (*s++);
+       }
+}
diff --git a/package/boot/uboot-ar71xx/files/drivers/net/ag71xx.c b/package/boot/uboot-ar71xx/files/drivers/net/ag71xx.c
new file mode 100644 (file)
index 0000000..b3324c0
--- /dev/null
@@ -0,0 +1,809 @@
+/*
+ *  Atheros AR71xx built-in ethernet mac driver
+ *
+ *  Copyright (C) 2010 Michael Kurz <michi.kurz@googlemail.com>
+ *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  Based on Atheros' AG7100 driver
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+#include <miiphy.h>
+
+#include <asm/ar71xx.h>
+
+#include "ag71xx.h"
+
+#ifdef AG71XX_DEBUG
+#define DBG(fmt,args...)               printf(fmt ,##args)
+#else
+#define DBG(fmt,args...)
+#endif
+
+
+static struct ag71xx agtable[] = {
+       {
+               .mac_base = KSEG1ADDR(AR71XX_GE0_BASE),
+               .mii_ctrl = KSEG1ADDR(AR71XX_MII_BASE + MII_REG_MII0_CTRL),
+               .mii_if = CONFIG_AG71XX_MII0_IIF,
+       } , {
+               .mac_base = KSEG1ADDR(AR71XX_GE1_BASE),
+               .mii_ctrl = KSEG1ADDR(AR71XX_MII_BASE + MII_REG_MII1_CTRL),
+               .mii_if = CONFIG_AG71XX_MII1_IIF,
+       }
+};
+
+static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
+{
+       int err;
+       int i;
+       int rsize;
+
+       ring->desc_size = sizeof(struct ag71xx_desc);
+       if (ring->desc_size % (CONFIG_SYS_CACHELINE_SIZE)) {
+               rsize = roundup(ring->desc_size, CONFIG_SYS_CACHELINE_SIZE);
+               DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
+                       ring, ring->desc_size,
+                       rsize);
+               ring->desc_size = rsize;
+       }
+
+       ring->descs_cpu = (u8 *) malloc((size * ring->desc_size)
+               + CONFIG_SYS_CACHELINE_SIZE - 1);
+       if (!ring->descs_cpu) {
+               err = -1;
+               goto err;
+       }
+       ring->descs_cpu = (u8 *) UNCACHED_SDRAM((((u32) ring->descs_cpu + 
+               CONFIG_SYS_CACHELINE_SIZE - 1) & ~(CONFIG_SYS_CACHELINE_SIZE - 1)));
+    ring->descs_dma = (u8 *) virt_to_phys(ring->descs_cpu);
+
+       ring->size = size;
+
+       ring->buf = malloc(size * sizeof(*ring->buf));
+       if (!ring->buf) {
+               err = -1;
+               goto err;
+       }
+    memset(ring->buf, 0, size * sizeof(*ring->buf));
+
+       for (i = 0; i < size; i++) {
+               ring->buf[i].desc =
+                       (struct ag71xx_desc *)&ring->descs_cpu[i * ring->desc_size];
+               DBG("ag71xx: ring %p, desc %d at %p\n",
+                       ring, i, ring->buf[i].desc);
+       }
+
+       flush_cache( (u32) ring->buf, size * sizeof(*ring->buf));
+       
+       return 0;
+
+ err:
+       return err;
+}
+
+static void ag71xx_ring_tx_init(struct ag71xx *ag)
+{
+       struct ag71xx_ring *ring = &ag->tx_ring;
+       int i;
+
+       for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
+               ring->buf[i].desc->next = (u32) virt_to_phys((ring->descs_dma +
+                       ring->desc_size * ((i + 1) % AG71XX_TX_RING_SIZE)));
+
+               ring->buf[i].desc->ctrl = DESC_EMPTY;
+               ring->buf[i].skb = NULL;
+       }
+
+       ring->curr = 0;
+}
+
+static void ag71xx_ring_rx_clean(struct ag71xx *ag)
+{
+       struct ag71xx_ring *ring = &ag->rx_ring;
+       int i;
+
+       if (!ring->buf)
+               return;
+
+       for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
+           ring->buf[i].desc->data = (u32) virt_to_phys(NetRxPackets[i]);
+           flush_cache((u32) NetRxPackets[i], PKTSIZE_ALIGN);
+        ring->buf[i].desc->ctrl = DESC_EMPTY;
+    }
+
+       ring->curr = 0;
+}
+
+static int ag71xx_ring_rx_init(struct ag71xx *ag)
+{
+       struct ag71xx_ring *ring = &ag->rx_ring;
+       unsigned int i;
+
+       for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
+               ring->buf[i].desc->next = (u32) virt_to_phys((ring->descs_dma +
+                       ring->desc_size * ((i + 1) % AG71XX_RX_RING_SIZE)));
+
+               DBG("ag71xx: RX desc at %p, next is %08x\n",
+                       ring->buf[i].desc,
+                       ring->buf[i].desc->next);
+       }
+
+       for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
+               ring->buf[i].desc->data = (u32) virt_to_phys(NetRxPackets[i]);
+               ring->buf[i].desc->ctrl = DESC_EMPTY;
+       }
+
+       ring->curr = 0;
+
+       return 0;
+}
+
+static int ag71xx_rings_init(struct ag71xx *ag)
+{
+       int ret;
+
+       ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE);
+       if (ret)
+               return ret;
+
+       ag71xx_ring_tx_init(ag);
+
+       ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE);
+       if (ret)
+               return ret;
+
+       ret = ag71xx_ring_rx_init(ag);
+       return ret;
+}
+
+static void ar71xx_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
+{
+       uint32_t base = KSEG1ADDR(AR71XX_PLL_BASE);
+       u32 t;
+
+       t = readl(base + cfg_reg);
+       t &= ~(3 << shift);
+       t |=  (2 << shift);
+       writel(t, base + cfg_reg);
+       udelay(100);
+
+       writel(pll_val, base + pll_reg);
+
+       t |= (3 << shift);
+       writel(t, base + cfg_reg);
+       udelay(100);
+
+       t &= ~(3 << shift);
+       writel(t, base + cfg_reg);
+       udelay(100);
+
+       debug("ar71xx: pll_reg %#x: %#x\n", (unsigned int)(base + pll_reg),
+       readl(base + pll_reg));
+}
+
+static void ar91xx_set_pll_ge0(int speed)
+{
+       //u32 val = ar71xx_get_eth_pll(0, speed);
+       u32 pll_val;
+
+       switch (speed) {
+       case SPEED_10:
+               pll_val = 0x00441099;
+               break;
+       case SPEED_100:
+               pll_val = 0x13000a44;
+               break;
+       case SPEED_1000:
+               pll_val = 0x1a000000;
+               break;
+       default:
+               BUG();
+       }
+
+       ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK,
+                        pll_val, AR91XX_ETH0_PLL_SHIFT);
+}
+
+static void ar91xx_set_pll_ge1(int speed)
+{
+       //u32 val = ar71xx_get_eth_pll(1, speed);
+    u32 pll_val;
+
+       switch (speed) {
+       case SPEED_10:
+               pll_val = 0x00441099;
+               break;
+       case SPEED_100:
+               pll_val = 0x13000a44;
+               break;
+       case SPEED_1000:
+               pll_val = 0x1a000000;
+               break;
+       default:
+               BUG();
+       }
+
+       ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK,
+                        pll_val, AR91XX_ETH1_PLL_SHIFT);
+}
+
+static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
+{
+       u32 t;
+
+       t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
+         | (((u32) mac[3]) << 8) | ((u32) mac[2]);
+
+       ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
+
+       t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
+       ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
+}
+
+static void ag71xx_dma_reset(struct ag71xx *ag)
+{
+       u32 val;
+       int i;
+
+       DBG("%s: txdesc reg: 0x%08x rxdesc reg: 0x%08x\n",
+                       ag->dev->name,
+                       ag71xx_rr(ag, AG71XX_REG_TX_DESC),
+                       ag71xx_rr(ag, AG71XX_REG_RX_DESC));
+       
+       /* stop RX and TX */
+       ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
+       ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
+
+       /* clear descriptor addresses */
+       ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0);
+       ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0);
+
+       /* clear pending RX/TX interrupts */
+       for (i = 0; i < 256; i++) {
+               ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
+               ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
+       }
+
+       /* clear pending errors */
+       ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
+       ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
+
+       val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
+       if (val)
+               printf("%s: unable to clear DMA Rx status: %08x\n",
+                       ag->dev->name, val);
+
+       val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
+
+       /* mask out reserved bits */
+       val &= ~0xff000000;
+
+       if (val)
+               printf("%s: unable to clear DMA Tx status: %08x\n",
+                       ag->dev->name, val);
+}
+
+static void ag71xx_halt(struct eth_device *dev)
+{
+    struct ag71xx *ag = (struct ag71xx *) dev->priv;
+
+    /* stop RX engine */
+       ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
+
+       ag71xx_dma_reset(ag);
+}
+
+#define MAX_WAIT        1000
+
+static int ag71xx_send(struct eth_device *dev, volatile void *packet,
+                       int length)
+{
+    struct ag71xx *ag = (struct ag71xx *) dev->priv;
+       struct ag71xx_ring *ring = &ag->tx_ring;
+       struct ag71xx_desc *desc;
+       int i;
+
+       i = ring->curr % AG71XX_TX_RING_SIZE;
+       desc = ring->buf[i].desc;
+
+       if (!ag71xx_desc_empty(desc)) {
+               printf("%s: tx buffer full\n", ag->dev->name);
+               return 1;
+       }
+
+       flush_cache((u32) packet, length);
+    desc->data = (u32) virt_to_phys(packet);
+    desc->ctrl = (length & DESC_PKTLEN_M);
+       
+       DBG("%s: sending %#08x length %#08x\n",
+               ag->dev->name, desc->data, desc->ctrl);
+       
+       ring->curr++;
+       if (ring->curr >= AG71XX_TX_RING_SIZE){
+               ring->curr = 0;
+       }
+       
+       /* enable TX engine */
+       ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
+
+    for (i = 0; i < MAX_WAIT; i++)
+    {
+        if (ag71xx_desc_empty(desc))
+            break;
+        udelay(10);
+    }
+    if (i == MAX_WAIT) {
+        printf("%s: tx timed out!\n", ag->dev->name);
+               return -1;
+       }
+       
+       /* disable TX engine */
+       ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
+       desc->data = 0;
+       desc->ctrl = DESC_EMPTY;
+       
+       return 0;
+}
+
+static int ag71xx_recv(struct eth_device *dev)
+{
+    struct ag71xx *ag = (struct ag71xx *) dev->priv;
+       struct ag71xx_ring *ring = &ag->rx_ring;
+
+    for (;;) {
+               unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
+               struct ag71xx_desc *desc = ring->buf[i].desc;
+               int pktlen;
+               
+               if (ag71xx_desc_empty(desc))
+                       break;
+
+               DBG("%s: rx packets, curr=%u\n", dev->name, ring->curr);
+
+        pktlen = ag71xx_desc_pktlen(desc);
+               pktlen -= ETH_FCS_LEN;
+
+
+               NetReceive(NetRxPackets[i] , pktlen);
+               flush_cache( (u32) NetRxPackets[i], PKTSIZE_ALIGN);
+
+        ring->buf[i].desc->ctrl = DESC_EMPTY;
+               ring->curr++;
+               if (ring->curr >= AG71XX_RX_RING_SIZE){
+                       ring->curr = 0;
+               }
+
+    }
+
+       if ((ag71xx_rr(ag, AG71XX_REG_RX_CTRL) & RX_CTRL_RXE) == 0) {
+               /* start RX engine */
+               ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
+       }
+       
+       return 0;
+}
+
+#ifdef AG71XX_DEBUG
+static char *ag71xx_speed_str(struct ag71xx *ag)
+{
+       switch (ag->speed) {
+       case SPEED_1000:
+               return "1000";
+       case SPEED_100:
+               return "100";
+       case SPEED_10:
+               return "10";
+       }
+
+       return "?";
+}
+#endif
+
+void ag71xx_link_adjust(struct ag71xx *ag)
+{
+       u32 cfg2;
+       u32 ifctl;
+       u32 fifo5;
+       u32 mii_speed;
+
+       if (!ag->link) {
+               DBG("%s: link down\n", ag->dev->name);
+               return;
+       }
+
+       cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
+       cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
+       cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
+
+       ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
+       ifctl &= ~(MAC_IFCTL_SPEED);
+
+       fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
+       fifo5 &= ~FIFO_CFG5_BM;
+
+       switch (ag->speed) {
+       case SPEED_1000:
+               mii_speed =  MII_CTRL_SPEED_1000;
+               cfg2 |= MAC_CFG2_IF_1000;
+               fifo5 |= FIFO_CFG5_BM;
+               break;
+       case SPEED_100:
+               mii_speed = MII_CTRL_SPEED_100;
+               cfg2 |= MAC_CFG2_IF_10_100;
+               ifctl |= MAC_IFCTL_SPEED;
+               break;
+       case SPEED_10:
+               mii_speed = MII_CTRL_SPEED_10;
+               cfg2 |= MAC_CFG2_IF_10_100;
+               break;
+       default:
+               BUG();
+               return;
+       }
+
+    ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff);
+
+    if (ag->macNum == 0)
+        ar91xx_set_pll_ge0(ag->speed);
+    else
+        ar91xx_set_pll_ge1(ag->speed);
+
+       ag71xx_mii_ctrl_set_speed(ag, mii_speed);
+
+       ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
+       ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
+       ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
+
+    DBG("%s: link up (%sMbps/%s duplex)\n",
+        ag->dev->name,
+        ag71xx_speed_str(ag),
+        (1 == ag->duplex) ? "Full" : "Half");
+
+       DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
+               ag->dev->name,
+               ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
+               ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
+               ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
+
+       DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
+               ag->dev->name,
+               ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
+               ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
+               ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
+
+       DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x, mii_ctrl=%#x\n",
+               ag->dev->name,
+               ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
+               ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
+               ag71xx_mii_ctrl_rr(ag));
+}
+
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+static int ag71xx_getMiiSpeed(struct ag71xx *ag) 
+{
+    uint16_t phyreg, cap;
+
+    if (miiphy_read(ag->phyname, ag->phyid,
+                    PHY_BMSR, &phyreg)) {
+        puts("PHY_BMSR read failed, assuming no link\n");
+        return -1;
+    }
+
+    if ((phyreg & PHY_BMSR_LS) == 0) {
+        return -1;
+    }
+
+    if (miiphy_read(ag->phyname, ag->phyid,
+                PHY_1000BTSR, &phyreg))
+        return -1;
+
+    if (phyreg & PHY_1000BTSR_1000FD) {
+        ag->speed = SPEED_1000;
+        ag->duplex = 1;
+    } else if (phyreg & PHY_1000BTSR_1000HD) {
+        ag->speed = SPEED_1000;
+        ag->duplex = 0;
+    } else {
+        if (miiphy_read(ag->phyname, ag->phyid,
+                PHY_ANAR, &cap))
+            return -1;
+
+        if (miiphy_read(ag->phyname, ag->phyid,
+                PHY_ANLPAR, &phyreg))
+            return -1;
+
+        cap &= phyreg;
+        if (cap & PHY_ANLPAR_TXFD) {
+            ag->speed = SPEED_100;
+            ag->duplex = 1;
+        } else if (cap & PHY_ANLPAR_TX) {
+            ag->speed = SPEED_100;
+            ag->duplex = 0;
+        } else if (cap & PHY_ANLPAR_10FD) {
+            ag->speed = SPEED_10;
+            ag->duplex = 1;
+        } else {
+            ag->speed = SPEED_10;
+            ag->duplex = 0;
+        }
+    }
+       
+       ag->link = 1;
+       
+       return 0;
+}
+#endif
+
+static int ag71xx_hw_start(struct eth_device *dev, bd_t * bd)
+{
+       struct ag71xx *ag = (struct ag71xx *) dev->priv;
+
+       ag71xx_dma_reset(ag);
+
+    ag71xx_ring_rx_clean(ag);
+       ag71xx_ring_tx_init(ag);
+       
+       ag71xx_wr(ag, AG71XX_REG_TX_DESC, 
+                               (u32) virt_to_phys(ag->tx_ring.descs_dma));
+       ag71xx_wr(ag, AG71XX_REG_RX_DESC,
+                               (u32) virt_to_phys(ag->rx_ring.descs_dma));
+
+       ag71xx_hw_set_macaddr(ag, ag->dev->enetaddr);
+
+    if (ag->phyfixed) {
+        ag->link = 1;
+        ag->duplex = 1;
+        ag->speed = SPEED_1000;
+    } else {
+
+#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
+               if (ag71xx_getMiiSpeed(ag))
+                       return -1;
+#else
+               /* only fixed, without mii */
+               return -1;
+#endif
+
+    }
+    ag71xx_link_adjust(ag);
+       
+       DBG("%s: txdesc reg: %#08x rxdesc reg: %#08x\n",
+               ag->dev->name,
+               ag71xx_rr(ag, AG71XX_REG_TX_DESC),
+               ag71xx_rr(ag, AG71XX_REG_RX_DESC));
+       
+       /* start RX engine */
+       ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
+       
+       return 0;
+}
+
+#define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
+
+#define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
+                        FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
+                        FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
+                        FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
+                        FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
+                        FIFO_CFG4_VT)
+
+#define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
+                        FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
+                        FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
+                        FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
+                        FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
+                        FIFO_CFG5_17 | FIFO_CFG5_SF)
+
+static int ag71xx_hw_init(struct ag71xx *ag)
+{
+    int ret = 0;
+       uint32_t reg;
+       uint32_t mask, mii_type;
+
+    if (ag->macNum == 0) {
+        mask = (RESET_MODULE_GE0_MAC | RESET_MODULE_GE0_PHY);
+        mii_type = 0x13;
+    } else {
+        mask = (RESET_MODULE_GE1_MAC | RESET_MODULE_GE1_PHY);
+        mii_type = 0x11;
+    }
+
+    // mac soft reset
+    ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
+    udelay(20);
+       
+       // device stop
+       reg = ar71xx_reset_rr(AR91XX_RESET_REG_RESET_MODULE);
+       ar71xx_reset_wr(AR91XX_RESET_REG_RESET_MODULE, reg | mask);
+       udelay(100 * 1000);
+       
+    // device start
+    reg = ar71xx_reset_rr(AR91XX_RESET_REG_RESET_MODULE);
+    ar71xx_reset_wr(AR91XX_RESET_REG_RESET_MODULE, reg & ~mask);
+    udelay(100 * 1000);
+
+    /* setup MAC configuration registers */
+    ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, (MAC_CFG1_RXE | MAC_CFG1_TXE));
+
+    ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
+          MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
+
+    /* setup FIFO configuration register 0 */
+    ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
+
+    /* setup MII interface type */
+    ag71xx_mii_ctrl_set_if(ag, ag->mii_if);
+
+    /* setup mdio clock divisor */
+    ag71xx_wr(ag, AG71XX_REG_MII_CFG, MII_CFG_CLK_DIV_20);
+       
+       /* setup FIFO configuration registers */
+       ag71xx_sb(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
+    ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
+    ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
+    ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
+
+    ag71xx_dma_reset(ag);
+
+    ret = ag71xx_rings_init(ag);
+    if (ret)
+        return -1;
+
+       ag71xx_wr(ag, AG71XX_REG_TX_DESC, 
+                               (u32) virt_to_phys(ag->tx_ring.descs_dma));
+       ag71xx_wr(ag, AG71XX_REG_RX_DESC,
+                               (u32) virt_to_phys(ag->rx_ring.descs_dma));
+               
+       ag71xx_hw_set_macaddr(ag, ag->dev->enetaddr);
+       
+    return 0;
+}
+
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+#define AG71XX_MDIO_RETRY      1000
+#define AG71XX_MDIO_DELAY      5
+
+static inline struct ag71xx *ag71xx_name2mac(char *devname)
+{
+    if (strcmp(devname, agtable[0].dev->name) == 0)
+        return &agtable[0];
+    else if (strcmp(devname, agtable[1].dev->name) == 0)
+        return &agtable[1];
+    else
+        return NULL;
+}
+
+static inline void ag71xx_mdio_wr(struct ag71xx *ag, unsigned reg,
+                                 u32 value)
+{
+       uint32_t r;
+
+       r = ag->mac_base + reg;
+       writel(value, r);
+
+       /* flush write */
+       (void) readl(r);
+}
+
+static inline u32 ag71xx_mdio_rr(struct ag71xx *ag, unsigned reg)
+{
+       return readl(ag->mac_base + reg);
+}
+
+static int ag71xx_mdio_read(char *devname, unsigned char addr,
+                            unsigned char reg, unsigned short *val)
+{
+       struct ag71xx *ag = ag71xx_name2mac(devname);
+       uint16_t regData;
+       int i;
+
+       ag71xx_mdio_wr(ag, AG71XX_REG_MII_CMD, MII_CMD_WRITE);
+       ag71xx_mdio_wr(ag, AG71XX_REG_MII_ADDR,
+                       ((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff));
+       ag71xx_mdio_wr(ag, AG71XX_REG_MII_CMD, MII_CMD_READ);
+
+       i = AG71XX_MDIO_RETRY;
+       while (ag71xx_mdio_rr(ag, AG71XX_REG_MII_IND) & MII_IND_BUSY) {
+               if (i-- == 0) {
+                       printf("%s: mii_read timed out\n",
+                               ag->dev->name);
+                       return -1;
+               }
+               udelay(AG71XX_MDIO_DELAY);
+       }
+
+       regData = (uint16_t) ag71xx_mdio_rr(ag, AG71XX_REG_MII_STATUS) & 0xffff;
+       ag71xx_mdio_wr(ag, AG71XX_REG_MII_CMD, MII_CMD_WRITE);
+
+       DBG("mii_read: addr=%04x, reg=%04x, value=%04x\n", addr, reg, regData);
+
+    if (val)
+        *val = regData;
+
+       return 0;
+}
+
+static int ag71xx_mdio_write(char *devname, unsigned char addr,
+                            unsigned char reg, unsigned short val)
+{
+       struct ag71xx *ag = ag71xx_name2mac(devname);
+       int i;
+
+    if (ag == NULL)
+        return 1;
+
+       DBG("mii_write: addr=%04x, reg=%04x, value=%04x\n", addr, reg, val);
+
+       ag71xx_mdio_wr(ag, AG71XX_REG_MII_ADDR,
+                       ((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff));
+       ag71xx_mdio_wr(ag, AG71XX_REG_MII_CTRL, val);
+
+       i = AG71XX_MDIO_RETRY;
+       while (ag71xx_mdio_rr(ag, AG71XX_REG_MII_IND) & MII_IND_BUSY) {
+               if (i-- == 0) {
+                       printf("%s: mii_write timed out\n",
+                               ag->dev->name);
+                       break;
+               }
+               udelay(AG71XX_MDIO_DELAY);
+       }
+
+       return 0;
+}
+#endif
+
+int ag71xx_register(bd_t * bis, char *phyname[], uint16_t phyid[], uint16_t phyfixed[])
+{
+    int i, num = 0;
+    u8 used_ports[MAX_AG71XX_DEVS] = CONFIG_AG71XX_PORTS;
+
+       for (i = 0; i < MAX_AG71XX_DEVS; i++) {
+               /*skip if port is configured not to use */
+               if (used_ports[i] == 0)
+                       continue;
+
+               agtable[i].dev = malloc(sizeof(struct eth_device));
+               if (agtable[i].dev == NULL) {
+                       puts("malloc failed\n");
+                       return 0;
+        }
+               memset(agtable[i].dev, 0, sizeof(struct eth_device));
+               sprintf(agtable[i].dev->name, "eth%d", i);
+
+               agtable[i].dev->iobase = 0;
+               agtable[i].dev->init = ag71xx_hw_start;
+               agtable[i].dev->halt = ag71xx_halt;
+               agtable[i].dev->send = ag71xx_send;
+               agtable[i].dev->recv = ag71xx_recv;
+               agtable[i].dev->priv = (void *) (&agtable[i]);
+               agtable[i].macNum = i;
+               eth_register(agtable[i].dev);
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+
+        if ((phyname == NULL) || (phyid == NULL) || (phyfixed == NULL))
+            return -1;
+
+        agtable[i].phyname = strdup(phyname[i]);
+        agtable[i].phyid = phyid[i];
+        agtable[i].phyfixed = phyfixed[i];
+
+        miiphy_register(agtable[i].dev->name, ag71xx_mdio_read,
+                       ag71xx_mdio_write);
+#endif
+
+               if (ag71xx_hw_init(&agtable[i]))
+                       continue;
+
+        num++;
+       }
+
+    return num;
+}
diff --git a/package/boot/uboot-ar71xx/files/drivers/net/ag71xx.h b/package/boot/uboot-ar71xx/files/drivers/net/ag71xx.h
new file mode 100644 (file)
index 0000000..edce429
--- /dev/null
@@ -0,0 +1,374 @@
+/*
+ *  Atheros AR71xx built-in ethernet mac driver
+ *
+ *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  Based on Atheros' AG7100 driver
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef __AG71XX_H
+#define __AG71XX_H
+
+#include <linux/types.h>
+#include <linux/bitops.h>
+
+#include <asm/ar71xx.h>
+
+// controller has 2 ports
+#define MAX_AG71XX_DEVS 2
+
+#define ETH_FCS_LEN    4
+
+#define SPEED_10        10
+#define SPEED_100       100
+#define SPEED_1000      1000
+
+
+#define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
+#define AG71XX_INT_TX  (AG71XX_INT_TX_PS)
+#define AG71XX_INT_RX  (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
+
+#define AG71XX_INT_POLL        (AG71XX_INT_RX | AG71XX_INT_TX)
+#define AG71XX_INT_INIT        (AG71XX_INT_ERR | AG71XX_INT_POLL)
+
+#define AG71XX_TX_FIFO_LEN     2048
+#define AG71XX_TX_MTU_LEN      1536
+#define AG71XX_RX_PKT_RESERVE  64
+#define AG71XX_RX_PKT_SIZE     \
+       (AG71XX_RX_PKT_RESERVE + ETH_HLEN + ETH_FRAME_LEN + ETH_FCS_LEN)
+
+#ifndef CONFIG_SYS_RX_ETH_BUFFER
+#define AG71XX_TX_RING_SIZE    4
+#define AG71XX_RX_RING_SIZE    4
+#else
+#define AG71XX_TX_RING_SIZE    CONFIG_SYS_RX_ETH_BUFFER
+#define AG71XX_RX_RING_SIZE    CONFIG_SYS_RX_ETH_BUFFER
+#endif
+
+#define AG71XX_TX_THRES_STOP   (AG71XX_TX_RING_SIZE - 4)
+#define AG71XX_TX_THRES_WAKEUP \
+               (AG71XX_TX_RING_SIZE - (AG71XX_TX_RING_SIZE / 4))
+
+
+
+
+struct ag71xx_desc {
+       u32     data;
+       u32     ctrl;
+#define DESC_EMPTY     BIT(31)
+#define DESC_MORE      BIT(24)
+#define DESC_PKTLEN_M  0xfff
+       u32     next;
+       u32     pad;
+} __attribute__((aligned(4)));
+
+struct ag71xx_buf {
+       struct sk_buff          *skb;
+       struct ag71xx_desc      *desc;
+       dma_addr_t              dma_addr;
+       u32                     pad;
+};
+
+struct ag71xx_ring {
+       struct ag71xx_buf       *buf;
+       u8                      *descs_cpu;
+       u8                  *descs_dma;
+       unsigned int            desc_size;
+       unsigned int            curr;
+       unsigned int            size;
+};
+
+struct ag71xx {
+       uint32_t                    mac_base;
+       uint32_t                    mii_ctrl;
+
+       struct eth_device       *dev;
+
+       struct ag71xx_ring      rx_ring;
+       struct ag71xx_ring      tx_ring;
+
+    char               *phyname;
+    u16                 phyid;
+    u16                 phyfixed;
+       uint32_t                link;
+       uint32_t                speed;
+       int32_t                     duplex;
+    uint32_t            macNum;
+    uint32_t            mii_if;
+};
+
+void ag71xx_link_adjust(struct ag71xx *ag);
+
+int ag71xx_phy_connect(struct ag71xx *ag);
+void ag71xx_phy_disconnect(struct ag71xx *ag);
+void ag71xx_phy_start(struct ag71xx *ag);
+void ag71xx_phy_stop(struct ag71xx *ag);
+
+static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
+{
+       return ((desc->ctrl & DESC_EMPTY) != 0);
+}
+
+static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
+{
+       return (desc->ctrl & DESC_PKTLEN_M);
+}
+
+/* Register offsets */
+#define AG71XX_REG_MAC_CFG1    0x0000
+#define AG71XX_REG_MAC_CFG2    0x0004
+#define AG71XX_REG_MAC_IPG     0x0008
+#define AG71XX_REG_MAC_HDX     0x000c
+#define AG71XX_REG_MAC_MFL     0x0010
+#define AG71XX_REG_MII_CFG     0x0020
+#define AG71XX_REG_MII_CMD     0x0024
+#define AG71XX_REG_MII_ADDR    0x0028
+#define AG71XX_REG_MII_CTRL    0x002c
+#define AG71XX_REG_MII_STATUS  0x0030
+#define AG71XX_REG_MII_IND     0x0034
+#define AG71XX_REG_MAC_IFCTL   0x0038
+#define AG71XX_REG_MAC_ADDR1   0x0040
+#define AG71XX_REG_MAC_ADDR2   0x0044
+#define AG71XX_REG_FIFO_CFG0   0x0048
+#define AG71XX_REG_FIFO_CFG1   0x004c
+#define AG71XX_REG_FIFO_CFG2   0x0050
+#define AG71XX_REG_FIFO_CFG3   0x0054
+#define AG71XX_REG_FIFO_CFG4   0x0058
+#define AG71XX_REG_FIFO_CFG5   0x005c
+#define AG71XX_REG_FIFO_RAM0   0x0060
+#define AG71XX_REG_FIFO_RAM1   0x0064
+#define AG71XX_REG_FIFO_RAM2   0x0068
+#define AG71XX_REG_FIFO_RAM3   0x006c
+#define AG71XX_REG_FIFO_RAM4   0x0070
+#define AG71XX_REG_FIFO_RAM5   0x0074
+#define AG71XX_REG_FIFO_RAM6   0x0078
+#define AG71XX_REG_FIFO_RAM7   0x007c
+
+#define AG71XX_REG_TX_CTRL     0x0180
+#define AG71XX_REG_TX_DESC     0x0184
+#define AG71XX_REG_TX_STATUS   0x0188
+#define AG71XX_REG_RX_CTRL     0x018c
+#define AG71XX_REG_RX_DESC     0x0190
+#define AG71XX_REG_RX_STATUS   0x0194
+#define AG71XX_REG_INT_ENABLE  0x0198
+#define AG71XX_REG_INT_STATUS  0x019c
+
+#define MAC_CFG1_TXE           BIT(0)  /* Tx Enable */
+#define MAC_CFG1_STX           BIT(1)  /* Synchronize Tx Enable */
+#define MAC_CFG1_RXE           BIT(2)  /* Rx Enable */
+#define MAC_CFG1_SRX           BIT(3)  /* Synchronize Rx Enable */
+#define MAC_CFG1_TFC           BIT(4)  /* Tx Flow Control Enable */
+#define MAC_CFG1_RFC           BIT(5)  /* Rx Flow Control Enable */
+#define MAC_CFG1_LB            BIT(8)  /* Loopback mode */
+#define MAC_CFG1_SR            BIT(31) /* Soft Reset */
+
+#define MAC_CFG2_FDX           BIT(0)
+#define MAC_CFG2_CRC_EN                BIT(1)
+#define MAC_CFG2_PAD_CRC_EN    BIT(2)
+#define MAC_CFG2_LEN_CHECK     BIT(4)
+#define MAC_CFG2_HUGE_FRAME_EN BIT(5)
+#define MAC_CFG2_IF_1000       BIT(9)
+#define MAC_CFG2_IF_10_100     BIT(8)
+
+#define FIFO_CFG0_WTM          BIT(0)  /* Watermark Module */
+#define FIFO_CFG0_RXS          BIT(1)  /* Rx System Module */
+#define FIFO_CFG0_RXF          BIT(2)  /* Rx Fabric Module */
+#define FIFO_CFG0_TXS          BIT(3)  /* Tx System Module */
+#define FIFO_CFG0_TXF          BIT(4)  /* Tx Fabric Module */
+#define FIFO_CFG0_ALL  (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
+                       | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
+
+#define FIFO_CFG0_ENABLE_SHIFT 8
+
+#define FIFO_CFG4_DE           BIT(0)  /* Drop Event */
+#define FIFO_CFG4_DV           BIT(1)  /* RX_DV Event */
+#define FIFO_CFG4_FC           BIT(2)  /* False Carrier */
+#define FIFO_CFG4_CE           BIT(3)  /* Code Error */
+#define FIFO_CFG4_CR           BIT(4)  /* CRC error */
+#define FIFO_CFG4_LM           BIT(5)  /* Length Mismatch */
+#define FIFO_CFG4_LO           BIT(6)  /* Length out of range */
+#define FIFO_CFG4_OK           BIT(7)  /* Packet is OK */
+#define FIFO_CFG4_MC           BIT(8)  /* Multicast Packet */
+#define FIFO_CFG4_BC           BIT(9)  /* Broadcast Packet */
+#define FIFO_CFG4_DR           BIT(10) /* Dribble */
+#define FIFO_CFG4_LE           BIT(11) /* Long Event */
+#define FIFO_CFG4_CF           BIT(12) /* Control Frame */
+#define FIFO_CFG4_PF           BIT(13) /* Pause Frame */
+#define FIFO_CFG4_UO           BIT(14) /* Unsupported Opcode */
+#define FIFO_CFG4_VT           BIT(15) /* VLAN tag detected */
+#define FIFO_CFG4_FT           BIT(16) /* Frame Truncated */
+#define FIFO_CFG4_UC           BIT(17) /* Unicast Packet */
+
+#define FIFO_CFG5_DE           BIT(0)  /* Drop Event */
+#define FIFO_CFG5_DV           BIT(1)  /* RX_DV Event */
+#define FIFO_CFG5_FC           BIT(2)  /* False Carrier */
+#define FIFO_CFG5_CE           BIT(3)  /* Code Error */
+#define FIFO_CFG5_LM           BIT(4)  /* Length Mismatch */
+#define FIFO_CFG5_LO           BIT(5)  /* Length Out of Range */
+#define FIFO_CFG5_OK           BIT(6)  /* Packet is OK */
+#define FIFO_CFG5_MC           BIT(7)  /* Multicast Packet */
+#define FIFO_CFG5_BC           BIT(8)  /* Broadcast Packet */
+#define FIFO_CFG5_DR           BIT(9)  /* Dribble */
+#define FIFO_CFG5_CF           BIT(10) /* Control Frame */
+#define FIFO_CFG5_PF           BIT(11) /* Pause Frame */
+#define FIFO_CFG5_UO           BIT(12) /* Unsupported Opcode */
+#define FIFO_CFG5_VT           BIT(13) /* VLAN tag detected */
+#define FIFO_CFG5_LE           BIT(14) /* Long Event */
+#define FIFO_CFG5_FT           BIT(15) /* Frame Truncated */
+#define FIFO_CFG5_16           BIT(16) /* unknown */
+#define FIFO_CFG5_17           BIT(17) /* unknown */
+#define FIFO_CFG5_SF           BIT(18) /* Short Frame */
+#define FIFO_CFG5_BM           BIT(19) /* Byte Mode */
+
+#define AG71XX_INT_TX_PS       BIT(0)
+#define AG71XX_INT_TX_UR       BIT(1)
+#define AG71XX_INT_TX_BE       BIT(3)
+#define AG71XX_INT_RX_PR       BIT(4)
+#define AG71XX_INT_RX_OF       BIT(6)
+#define AG71XX_INT_RX_BE       BIT(7)
+
+#define MAC_IFCTL_SPEED                BIT(16)
+
+#define MII_CFG_CLK_DIV_4      0
+#define MII_CFG_CLK_DIV_6      2
+#define MII_CFG_CLK_DIV_8      3
+#define MII_CFG_CLK_DIV_10     4
+#define MII_CFG_CLK_DIV_14     5
+#define MII_CFG_CLK_DIV_20     6
+#define MII_CFG_CLK_DIV_28     7
+#define MII_CFG_RESET          BIT(31)
+
+#define MII_CMD_WRITE          0x0
+#define MII_CMD_READ           0x1
+#define MII_ADDR_SHIFT         8
+#define MII_IND_BUSY           BIT(0)
+#define MII_IND_INVALID                BIT(2)
+
+#define TX_CTRL_TXE            BIT(0)  /* Tx Enable */
+
+#define TX_STATUS_PS           BIT(0)  /* Packet Sent */
+#define TX_STATUS_UR           BIT(1)  /* Tx Underrun */
+#define TX_STATUS_BE           BIT(3)  /* Bus Error */
+
+#define RX_CTRL_RXE            BIT(0)  /* Rx Enable */
+
+#define RX_STATUS_PR           BIT(0)  /* Packet Received */
+#define RX_STATUS_OF           BIT(2)  /* Rx Overflow */
+#define RX_STATUS_BE           BIT(3)  /* Bus Error */
+
+#define MII_CTRL_IF_MASK       3
+#define MII_CTRL_SPEED_SHIFT   4
+#define MII_CTRL_SPEED_MASK    3
+#define MII_CTRL_SPEED_10      0
+#define MII_CTRL_SPEED_100     1
+#define MII_CTRL_SPEED_1000    2
+
+static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
+{
+       __raw_writel(value, ag->mac_base + reg);
+       /* flush write */
+       (void) __raw_readl(ag->mac_base + reg);
+}
+
+static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
+{
+       return __raw_readl(ag->mac_base + reg);
+}
+
+static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
+{
+       uint32_t r;
+
+       r = ag->mac_base + reg;
+       __raw_writel(__raw_readl(r) | mask, r);
+       /* flush write */
+       (void)__raw_readl(r);
+}
+
+static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
+{
+       uint32_t r;
+
+       r = ag->mac_base + reg;
+       __raw_writel(__raw_readl(r) & ~mask, r);
+       /* flush write */
+       (void) __raw_readl(r);
+}
+
+static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
+{
+       ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
+}
+
+static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
+{
+       ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
+}
+
+static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value)
+{
+       __raw_writel(value, ag->mii_ctrl);
+
+       /* flush write */
+       __raw_readl(ag->mii_ctrl);
+}
+
+static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag)
+{
+       return __raw_readl(ag->mii_ctrl);
+}
+
+static void inline ag71xx_mii_ctrl_set_if(struct ag71xx *ag,
+                                         unsigned int mii_if)
+{
+       u32 t;
+
+       t = ag71xx_mii_ctrl_rr(ag);
+       t &= ~(MII_CTRL_IF_MASK);
+       t |= (mii_if & MII_CTRL_IF_MASK);
+       ag71xx_mii_ctrl_wr(ag, t);
+}
+
+static void inline ag71xx_mii_ctrl_set_speed(struct ag71xx *ag,
+                                            unsigned int speed)
+{
+       u32 t;
+
+       t = ag71xx_mii_ctrl_rr(ag);
+       t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
+       t |= (speed & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT;
+       ag71xx_mii_ctrl_wr(ag, t);
+}
+
+#ifdef CONFIG_AG71XX_AR8216_SUPPORT
+void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb);
+int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb,
+                               int pktlen);
+static inline int ag71xx_has_ar8216(struct ag71xx *ag)
+{
+       return ag71xx_get_pdata(ag)->has_ar8216;
+}
+#else
+static inline void ag71xx_add_ar8216_header(struct ag71xx *ag,
+                                          struct sk_buff *skb)
+{
+}
+
+static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag,
+                                             struct sk_buff *skb,
+                                             int pktlen)
+{
+       return 0;
+}
+static inline int ag71xx_has_ar8216(struct ag71xx *ag)
+{
+       return 0;
+}
+#endif
+
+#endif /* _AG71XX_H */
diff --git a/package/boot/uboot-ar71xx/files/drivers/net/phy/rtl8366.h b/package/boot/uboot-ar71xx/files/drivers/net/phy/rtl8366.h
new file mode 100644 (file)
index 0000000..f0567dd
--- /dev/null
@@ -0,0 +1,188 @@
+/*
+ * (C) Copyright 2010
+ * Michael Kurz <michi.kurz@googlemail.com>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef RTL8366_MII_H
+#define RTL8366_MII_H
+
+#define        MII_CONTROL_REG             0
+#define        MII_STATUS_REG          1
+#define        MII_PHY_ID0                     2
+#define        MII_PHY_ID1                     3
+#define        MII_LOCAL_CAP           4
+#define        MII_REMOTE_CAP              5
+#define        MII_EXT_AUTONEG             6
+#define        MII_LOCAL_NEXT_PAGE         7
+#define        MII_REMOTE_NEXT_PAGE    8
+#define        MII_GIGA_CONTROL            9
+#define        MII_GIGA_STATUS             10
+#define        MII_EXT_STATUS_REG          15
+
+/* Control register */
+#define        MII_CONTROL_1000MBPS    6
+#define        MII_CONTROL_COLL_TEST   7
+#define        MII_CONTROL_FULLDUPLEX  8
+#define        MII_CONTROL_RENEG           9
+#define        MII_CONTROL_ISOLATE         10
+#define        MII_CONTROL_POWERDOWN   11
+#define        MII_CONTROL_AUTONEG         12
+#define        MII_CONTROL_100MBPS         13
+#define        MII_CONTROL_LOOPBACK    14
+#define        MII_CONTROL_RESET           15
+
+/* Status/Extended status register */
+/* Basic status */
+#define        MII_STATUS_CAPABILITY   0
+#define        MII_STATUS_JABBER           1
+#define        MII_STATUS_LINK_UP          2
+#define        MII_STATUS_AUTONEG_ABLE 3
+#define        MII_STATUS_REMOTE_FAULT 4
+#define        MII_STATUS_AUTONEG_DONE 5
+#define        MII_STATUS_NO_PREAMBLE  6
+#define        MII_STATUS_RESERVED         7
+#define        MII_STATUS_EXTENDED         8
+#define        MII_STATUS_100_T2_HALF  9
+#define        MII_STATUS_100_T2_FULL  10
+#define        MII_STATUS_10_TX_HALF   11
+#define        MII_STATUS_10_TX_FULL   12
+#define        MII_STATUS_100_TX_HALF  13
+#define        MII_STATUS_100_TX_FULL  14
+#define        MII_STATUS_100_T4           15
+
+#define        MII_GIGA_CONTROL_HALF   8
+#define        MII_GIGA_CONTROL_FULL   9
+#define        MII_GIGA_STATUS_HALF    10
+#define        MII_GIGA_STATUS_FULL    11
+
+/* Extended status */
+#define        MII_STATUS_1000_T_HALF  12
+#define        MII_STATUS_1000_T_FULL  13
+#define        MII_STATUS_1000_X_HALF  14
+#define        MII_STATUS_1000_X_FULL  15
+
+/* Local/Remmote capability register */
+#define        MII_CAP_10BASE_TX           5
+#define        MII_CAP_10BASE_TX_FULL  6
+#define        MII_CAP_100BASE_TX          7
+#define        MII_CAP_100BASE_TX_FULL 8
+#define        MII_CAP_100BASE_T4          9
+#define        MII_CAP_SYMM_PAUSE          10
+#define        MII_CAP_ASYMM_PAUSE         11
+#define        MII_CAP_RESERVED            12
+#define        MII_CAP_REMOTE_FAULT    13
+#define        MII_CAP_ACKNOWLEDGE         14
+#define        MII_CAP_NEXT_PAGE           15
+#define        MII_CAP_IEEE_802_3          0x0001
+
+#define        MII_LINK_MODE_MASK          0x1f
+
+#define REALTEK_RTL8366_CHIP_ID0    0x001C
+#define REALTEK_RTL8366_CHIP_ID1    0xC940
+#define REALTEK_RTL8366_CHIP_ID1_MP 0xC960
+
+#define REALTEK_MIN_PORT_ID     0
+#define REALTEK_MAX_PORT_ID     5
+#define REALTEK_MIN_PHY_ID      REALTEK_MIN_PORT_ID
+#define REALTEK_MAX_PHY_ID      4
+#define REALTEK_CPU_PORT_ID     REALTEK_MAX_PORT_ID
+#define REALTEK_PHY_PORT_MASK   ((1<<(REALTEK_MAX_PHY_ID+1)) - (1<<REALTEK_MIN_PHY_ID))
+#define REALTEK_CPU_PORT_MASK   (1<<REALTEK_CPU_PORT_ID)
+#define REALTEK_ALL_PORT_MASK   (REALTEK_PHY_PORT_MASK | REALTEK_CPU_PORT_MASK)
+
+/* port ability */
+#define RTL8366S_PORT_ABILITY_BASE                     0x0011
+
+/* port vlan control register */
+#define RTL8366S_PORT_VLAN_CTRL_BASE                   0x0058
+
+/* port linking status */
+#define RTL8366S_PORT_LINK_STATUS_BASE                 0x0060
+#define RTL8366S_PORT_STATUS_SPEED_BIT                 0
+#define RTL8366S_PORT_STATUS_SPEED_MSK                 0x0003
+#define RTL8366S_PORT_STATUS_DUPLEX_BIT                        2
+#define RTL8366S_PORT_STATUS_DUPLEX_MSK                        0x0004
+#define RTL8366S_PORT_STATUS_LINK_BIT                  4
+#define RTL8366S_PORT_STATUS_LINK_MSK                  0x0010
+#define RTL8366S_PORT_STATUS_TXPAUSE_BIT               5
+#define RTL8366S_PORT_STATUS_TXPAUSE_MSK               0x0020
+#define RTL8366S_PORT_STATUS_RXPAUSE_BIT               6
+#define RTL8366S_PORT_STATUS_RXPAUSE_MSK               0x0040
+#define RTL8366S_PORT_STATUS_AN_BIT                    7
+#define RTL8366S_PORT_STATUS_AN_MSK                    0x0080
+
+/* internal control */
+#define RTL8366S_RESET_CONTROL_REG                     0x0100
+#define RTL8366S_RESET_QUEUE_BIT                       2
+
+#define RTL8366S_CHIP_ID_REG                           0x0105
+
+/* MAC control */
+#define RTL8366S_MAC_FORCE_CTRL0_REG                   0x0F04
+#define RTL8366S_MAC_FORCE_CTRL1_REG                   0x0F05
+
+
+/* PHY registers control */
+#define RTL8366S_PHY_ACCESS_CTRL_REG                   0x8028
+#define RTL8366S_PHY_ACCESS_DATA_REG                   0x8029
+
+#define RTL8366S_PHY_CTRL_READ                         1
+#define RTL8366S_PHY_CTRL_WRITE                                0
+
+#define RTL8366S_PHY_REG_MASK                          0x1F
+#define RTL8366S_PHY_PAGE_OFFSET                       5
+#define RTL8366S_PHY_PAGE_MASK                         (0x7<<5)
+#define RTL8366S_PHY_NO_OFFSET                         9
+#define RTL8366S_PHY_NO_MASK                           (0x1F<<9)
+
+#define RTL8366S_PHY_NO_MAX                            4
+#define RTL8366S_PHY_PAGE_MAX                          7
+#define RTL8366S_PHY_ADDR_MAX                          31
+
+/* cpu port control reg */
+#define RTL8366S_CPU_CTRL_REG                          0x004F
+#define RTL8366S_CPU_DRP_BIT                           14
+#define RTL8366S_CPU_DRP_MSK                           0x4000
+#define RTL8366S_CPU_INSTAG_BIT                                15
+#define RTL8366S_CPU_INSTAG_MSK                                0x8000
+
+/* LED registers*/
+#define RTL8366S_LED_BLINK_REG                         0x420
+#define RTL8366S_LED_BLINKRATE_BIT                     0
+#define RTL8366S_LED_BLINKRATE_MSK                     0x0007
+#define RTL8366S_LED_INDICATED_CONF_REG                        0x421
+#define RTL8366S_LED_0_1_FORCE_REG                     0x422
+#define RTL8366S_LED_2_3_FORCE_REG                     0x423
+#define RTL8366S_LEDCONF_LEDFORCE                      0x1F
+#define RTL8366S_LED_GROUP_MAX                         4
+
+#define RTL8366S_GREEN_FEATURE_REG                     0x000A
+#define RTL8366S_GREEN_FEATURE_TX_BIT                  3
+#define RTL8366S_GREEN_FEATURE_TX_MSK                  0x0008
+#define RTL8366S_GREEN_FEATURE_RX_BIT                  4
+#define RTL8366S_GREEN_FEATURE_RX_MSK                  0x0010
+
+#define        RTL8366S_MODEL_ID_REG   0x5C
+#define        RTL8366S_REV_ID_REG     0x5D
+#define        RTL8366S_MODEL_8366SR   0x6027
+#define        RTL8366S_MODEL_8366RB   0x5937
+
+#endif
diff --git a/package/boot/uboot-ar71xx/files/drivers/net/phy/rtl8366_mii.c b/package/boot/uboot-ar71xx/files/drivers/net/phy/rtl8366_mii.c
new file mode 100644 (file)
index 0000000..e3c5316
--- /dev/null
@@ -0,0 +1,786 @@
+/*
+ * (C) Copyright 2010
+ * Michael Kurz <michi.kurz@googlemail.com>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <net.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include MII_GPIOINCLUDE
+
+#include "rtl8366.h"
+
+#ifdef DEBUG_RTL8366
+       #define DBG(fmt,args...)        printf (fmt ,##args)
+#else
+       #define DBG(fmt,args...)
+#endif
+
+
+//-------------------------------------------------------------------
+// Soft SMI functions
+//-------------------------------------------------------------------
+
+#define DELAY 2
+
+static void smi_init(void)
+{
+    MII_SDAINPUT;
+    MII_SCKINPUT;
+
+       MII_SETSDA(1);
+       MII_SETSCK(1);
+
+    udelay(20);
+}
+
+static void smi_start(void)
+{
+/*
+ * rtl8366 chip needs a extra clock with
+ * SDA high before start condition
+ */
+
+    /* set gpio pins output */
+    MII_SDAOUTPUT;
+    MII_SCKOUTPUT;
+    udelay(DELAY);
+
+    /* set initial state: SCK:0, SDA:1 */
+    MII_SETSCK(0);
+    MII_SETSDA(1);
+    udelay(DELAY);
+
+    /* toggle clock */
+    MII_SETSCK(1);
+    udelay(DELAY);
+    MII_SETSCK(0);
+    udelay(DELAY);
+
+    /* start condition */
+    MII_SETSCK(1);
+    udelay(DELAY);
+    MII_SETSDA(0);
+    udelay(DELAY);
+    MII_SETSCK(0);
+    udelay(DELAY);
+    MII_SETSDA(1);
+}
+
+static void smi_stop(void)
+{
+/*
+ * rtl8366 chip needs a extra clock with
+ * SDA high after stop condition
+ */
+
+    /* stop condition */
+       udelay(DELAY);
+    MII_SETSDA(0);
+    MII_SETSCK(1);
+    udelay(DELAY);
+    MII_SETSDA(1);
+    udelay(DELAY);
+    MII_SETSCK(1);
+    udelay(DELAY);
+    MII_SETSCK(0);
+    udelay(DELAY);
+
+    /* toggle clock */
+    MII_SETSCK(1);
+    udelay(DELAY);
+    MII_SETSCK(0);
+    udelay(DELAY);
+    MII_SETSCK(1);
+
+    /* set gpio pins input */
+    MII_SDAINPUT;
+    MII_SCKINPUT;
+}
+
+static void smi_writeBits(uint32_t data, uint8_t length)
+{
+    uint8_t test;
+
+    for( ; length > 0; length--) {
+        udelay(DELAY);
+
+        /* output data */
+        test = (((data & (1 << (length - 1))) != 0) ? 1 : 0);
+        MII_SETSDA(test);
+        udelay(DELAY);
+
+        /* toogle clock */
+        MII_SETSCK(1);
+        udelay(DELAY);
+        MII_SETSCK(0);
+    }
+}
+
+static uint32_t smi_readBits(uint8_t length)
+{
+    uint32_t ret;
+
+    MII_SDAINPUT;
+
+    for(ret = 0 ; length > 0; length--) {
+        udelay(DELAY);
+
+        ret <<= 1;
+
+        /* toogle clock */
+        MII_SETSCK(1);
+        udelay(DELAY);
+        ret |= MII_GETSDA;
+        MII_SETSCK(0);
+    }
+
+    MII_SDAOUTPUT;
+
+    return ret;
+}
+
+static int smi_waitAck(void)
+{
+    uint32_t retry = 0;
+
+       while (smi_readBits(1)) {
+               if (retry++ == 5)
+                       return -1;
+       }
+
+       return 0;
+
+}
+
+static int smi_read(uint32_t reg, uint32_t *data)
+{
+    uint32_t rawData;
+
+    /* send start condition */
+    smi_start();
+    /* send CTRL1 code: 0b1010*/
+    smi_writeBits(0x0a, 4);
+    /* send CTRL2 code: 0b100 */
+    smi_writeBits(0x04, 3);
+    /* send READ command */
+    smi_writeBits(0x01, 1);
+
+    /* wait for ACK */
+    if (smi_waitAck())
+        return -1;
+
+    /* send address low */
+    smi_writeBits(reg & 0xFF, 8);
+    /* wait for ACK */
+    if (smi_waitAck())
+        return -1;
+    /* send address high */
+    smi_writeBits((reg & 0xFF00) >> 8, 8);
+    /* wait for ACK */
+    if (smi_waitAck())
+        return -1;
+
+    /* read data low */
+    rawData = (smi_readBits(8) & 0xFF);
+    /* send ACK */
+    smi_writeBits(0, 1);
+    /* read data high */
+    rawData |= (smi_readBits(8) & 0xFF) << 8;
+    /* send NACK */
+    smi_writeBits(1, 1);
+
+    /* send stop condition */
+    smi_stop();
+
+    if (data)
+        *data = rawData;
+
+    return 0;
+}
+
+static int smi_write(uint32_t reg, uint32_t data)
+{
+    /* send start condition */
+    smi_start();
+    /* send CTRL1 code: 0b1010*/
+    smi_writeBits(0x0a, 4);
+    /* send CTRL2 code: 0b100 */
+    smi_writeBits(0x04, 3);
+    /* send WRITE command */
+    smi_writeBits(0x00, 1);
+
+    /* wait for ACK */
+    if (smi_waitAck())
+        return -1;
+
+    /* send address low */
+    smi_writeBits(reg & 0xFF, 8);
+    /* wait for ACK */
+    if (smi_waitAck())
+        return -1;
+    /* send address high */
+    smi_writeBits((reg & 0xFF00) >> 8, 8);
+    /* wait for ACK */
+    if (smi_waitAck())
+        return -1;
+
+    /* send data low */
+    smi_writeBits(data & 0xFF, 8);
+    /* wait for ACK */
+    if (smi_waitAck())
+        return -1;
+    /* send data high */
+    smi_writeBits((data & 0xFF00) >> 8, 8);
+    /* wait for ACK */
+    if (smi_waitAck())
+        return -1;
+
+    /* send stop condition */
+    smi_stop();
+
+    return 0;
+}
+
+
+//-------------------------------------------------------------------
+// Switch register read / write functions
+//-------------------------------------------------------------------
+static int rtl8366_readRegister(uint32_t reg, uint16_t *data)
+{
+    uint32_t regData;
+
+    DBG("rtl8366: read register=%#04x, data=", reg);
+
+    if (smi_read(reg, &regData)) {
+        printf("\nrtl8366 smi read failed!\n");
+        return -1;
+    }
+
+    if (data)
+        *data = regData;
+
+    DBG("%#04x\n", regData);
+
+    return 0;
+}
+
+static int rtl8366_writeRegister(uint32_t reg, uint16_t data)
+{
+    DBG("rtl8366: write register=%#04x, data=%#04x\n", reg, data);
+
+    if (smi_write(reg, data)) {
+        printf("rtl8366 smi write failed!\n");
+        return -1;
+    }
+
+    return 0;
+}
+
+static int rtl8366_setRegisterBit(uint32_t reg, uint32_t bitNum, uint32_t value)
+{
+    uint16_t regData;
+
+    if (bitNum >= 16)
+        return -1;
+
+    if (rtl8366_readRegister(reg, &regData))
+        return -1;
+
+    if (value)
+        regData |= (1 << bitNum);
+    else
+        regData &= ~(1 << bitNum);
+
+    if (rtl8366_writeRegister(reg, regData))
+        return -1;
+
+    return 0;
+}
+
+//-------------------------------------------------------------------
+// MII PHY read / write functions
+//-------------------------------------------------------------------
+static int rtl8366_getPhyReg(uint32_t phyNum, uint32_t reg, uint16_t *data)
+{
+    uint16_t phyAddr, regData;
+
+    if (phyNum > RTL8366S_PHY_NO_MAX) {
+               printf("rtl8366s: invalid phy number!\n");
+               return -1;
+       }
+
+    if (phyNum > RTL8366S_PHY_ADDR_MAX) {
+               printf("rtl8366s: invalid phy register number!\n");
+               return -1;
+       }
+
+       if (rtl8366_writeRegister(RTL8366S_PHY_ACCESS_CTRL_REG,
+                           RTL8366S_PHY_CTRL_READ))
+        return -1;
+
+    phyAddr = 0x8000 | (1 << (phyNum + RTL8366S_PHY_NO_OFFSET))
+                     | (reg & RTL8366S_PHY_REG_MASK);
+    if (rtl8366_writeRegister(phyAddr, 0))
+        return -1;
+
+    if (rtl8366_readRegister(RTL8366S_PHY_ACCESS_DATA_REG, &regData))
+        return -1;
+
+    if (data)
+        *data = regData;
+
+    return 0;
+}
+
+static int rtl8366_setPhyReg(uint32_t phyNum, uint32_t reg, uint16_t data)
+{
+    uint16_t phyAddr;
+
+    if (phyNum > RTL8366S_PHY_NO_MAX) {
+               printf("rtl8366s: invalid phy number!\n");
+               return -1;
+       }
+
+    if (phyNum > RTL8366S_PHY_ADDR_MAX) {
+               printf("rtl8366s: invalid phy register number!\n");
+               return -1;
+       }
+
+       if (rtl8366_writeRegister(RTL8366S_PHY_ACCESS_CTRL_REG,
+                           RTL8366S_PHY_CTRL_WRITE))
+        return -1;
+
+    phyAddr = 0x8000 | (1 << (phyNum + RTL8366S_PHY_NO_OFFSET))
+                     | (reg & RTL8366S_PHY_REG_MASK);
+    if (rtl8366_writeRegister(phyAddr, data))
+        return -1;
+
+    return 0;
+}
+
+static int rtl8366_miiread(char *devname, uchar phy_adr, uchar reg, ushort *data)
+{
+    uint16_t regData;
+
+    DBG("rtl8366_miiread: devname=%s, addr=%#02x, reg=%#02x\n",
+          devname, phy_adr, reg);
+
+    if (strcmp(devname, RTL8366_DEVNAME) != 0)
+        return -1;
+
+    if (rtl8366_getPhyReg(phy_adr, reg, &regData)) {
+        printf("rtl8366_miiread: write failed!\n");
+        return -1;
+    }
+
+    if (data)
+        *data = regData;
+
+    return 0;
+}
+
+static int rtl8366_miiwrite(char *devname, uchar phy_adr, uchar reg, ushort data)
+{
+    DBG("rtl8366_miiwrite: devname=%s, addr=%#02x, reg=%#02x, data=%#04x\n",
+          devname, phy_adr, reg, data);
+
+    if (strcmp(devname, RTL8366_DEVNAME) != 0)
+        return -1;
+
+    if (rtl8366_setPhyReg(phy_adr, reg, data)) {
+        printf("rtl8366_miiwrite: write failed!\n");
+        return -1;
+    }
+
+    return 0;
+}
+
+int rtl8366_mii_register(bd_t *bis)
+{
+    miiphy_register(strdup(RTL8366_DEVNAME), rtl8366_miiread,
+                       rtl8366_miiwrite);
+
+    return 0;
+}
+
+
+//-------------------------------------------------------------------
+// Switch management functions
+//-------------------------------------------------------------------
+
+int rtl8366s_setGreenFeature(uint32_t tx, uint32_t rx)
+{
+    if (rtl8366_setRegisterBit(RTL8366S_GREEN_FEATURE_REG,
+                               RTL8366S_GREEN_FEATURE_TX_BIT, tx))
+        return -1;
+
+    if (rtl8366_setRegisterBit(RTL8366S_GREEN_FEATURE_REG,
+                               RTL8366S_GREEN_FEATURE_RX_BIT, rx))
+        return -1;
+
+    return 0;
+}
+
+int rtl8366s_setPowerSaving(uint32_t phyNum, uint32_t enabled)
+{
+    uint16_t regData;
+
+    if (phyNum > RTL8366S_PHY_NO_MAX)
+        return -1;
+
+    if (rtl8366_getPhyReg(phyNum, 12, &regData))
+        return -1;
+
+    if (enabled)
+        regData |= (1 << 12);
+    else
+        regData &= ~(1 << 12);
+
+    if (rtl8366_setPhyReg(phyNum, 12, regData))
+        return -1;
+
+    return 0;
+}
+
+int rtl8366s_setGreenEthernet(uint32_t greenFeature, uint32_t powerSaving)
+{
+    uint32_t phyNum, i;
+    uint16_t regData;
+
+       const uint16_t greenSettings[][2] =
+       {
+               {0xBE5B,0x3500},
+               {0xBE5C,0xB975},
+               {0xBE5D,0xB9B9},
+               {0xBE77,0xA500},
+               {0xBE78,0x5A78},
+               {0xBE79,0x6478}
+       };
+
+    if (rtl8366_readRegister(RTL8366S_MODEL_ID_REG, &regData))
+        return -1;
+
+       switch (regData)
+       {
+               case 0x0000:
+                       for (i = 0; i < 6; i++) {
+                               if (rtl8366_writeRegister(RTL8366S_PHY_ACCESS_CTRL_REG, RTL8366S_PHY_CTRL_WRITE))
+                                       return -1;
+                               if (rtl8366_writeRegister(greenSettings[i][0], greenSettings[i][1]))
+                                       return -1;
+                       }
+                       break;
+
+               case RTL8366S_MODEL_8366SR:
+                       if (rtl8366_writeRegister(RTL8366S_PHY_ACCESS_CTRL_REG, RTL8366S_PHY_CTRL_WRITE))
+                               return -1;
+                       if (rtl8366_writeRegister(greenSettings[0][0], greenSettings[0][1]))
+                               return -1;
+                       break;
+
+               default:
+                       printf("rtl8366s_initChip: unsupported chip found!\n");
+                       return -1;
+       }
+
+    if (rtl8366s_setGreenFeature(greenFeature, powerSaving))
+        return -1;
+
+    for (phyNum = 0; phyNum <= RTL8366S_PHY_NO_MAX; phyNum++) {
+        if (rtl8366s_setPowerSaving(phyNum, powerSaving))
+            return -1;
+    }
+
+    return 0;
+}
+
+int rtl8366s_setCPUPortMask(uint8_t port, uint32_t enabled)
+{
+       if(port >= 6){
+               printf("rtl8366s_setCPUPortMask: invalid port number\n");
+               return -1;
+       }
+
+       return rtl8366_setRegisterBit(RTL8366S_CPU_CTRL_REG, port, enabled);
+}
+
+int rtl8366s_setCPUDisableInsTag(uint32_t enable)
+{
+       return rtl8366_setRegisterBit(RTL8366S_CPU_CTRL_REG,
+               RTL8366S_CPU_INSTAG_BIT, enable);
+}
+
+int rtl8366s_setCPUDropUnda(uint32_t enable)
+{
+       return rtl8366_setRegisterBit(RTL8366S_CPU_CTRL_REG,
+               RTL8366S_CPU_DRP_BIT, enable);
+}
+
+int rtl8366s_setCPUPort(uint8_t port, uint32_t noTag, uint32_t dropUnda)
+{
+       uint32_t i;
+
+       if(port >= 6){
+               printf("rtl8366s_setCPUPort: invalid port number\n");
+               return -1;
+       }
+
+       /* reset register */
+       for(i = 0; i < 6; i++)
+       {
+               if(rtl8366s_setCPUPortMask(i, 0)){
+                       printf("rtl8366s_setCPUPort: rtl8366s_setCPUPortMask failed\n");
+                       return -1;
+               }
+       }
+
+       if(rtl8366s_setCPUPortMask(port, 1)){
+               printf("rtl8366s_setCPUPort: rtl8366s_setCPUPortMask failed\n");
+               return -1;
+       }
+
+       if(rtl8366s_setCPUDisableInsTag(noTag)){
+               printf("rtl8366s_setCPUPort: rtl8366s_setCPUDisableInsTag fail\n");
+               return -1;
+       }
+
+       if(rtl8366s_setCPUDropUnda(dropUnda)){
+               printf("rtl8366s_setCPUPort: rtl8366s_setCPUDropUnda fail\n");
+               return -1;
+       }
+
+       return 0;
+}
+
+int rtl8366s_setLedConfig(uint32_t ledNum, uint8_t config)
+{
+    uint16_t regData;
+
+       if(ledNum >= RTL8366S_LED_GROUP_MAX) {
+               DBG("rtl8366s_setLedConfig: invalid led group\n");
+               return -1;
+       }
+
+    if(config > RTL8366S_LEDCONF_LEDFORCE) {
+               DBG("rtl8366s_setLedConfig: invalid led config\n");
+               return -1;
+       }
+
+       if (rtl8366_readRegister(RTL8366S_LED_INDICATED_CONF_REG, &regData)) {
+        printf("rtl8366s_setLedConfig: failed to get led register!\n");
+        return -1;
+       }
+
+       regData &= ~(0xF << (ledNum * 4));
+       regData |= config << (ledNum * 4);
+
+       if (rtl8366_writeRegister(RTL8366S_LED_INDICATED_CONF_REG, regData)) {
+        printf("rtl8366s_setLedConfig: failed to set led register!\n");
+        return -1;
+       }
+
+       return 0;
+}
+
+int rtl8366s_getLedConfig(uint32_t ledNum, uint8_t *config)
+{
+    uint16_t regData;
+
+       if(ledNum >= RTL8366S_LED_GROUP_MAX) {
+               DBG("rtl8366s_getLedConfig: invalid led group\n");
+               return -1;
+       }
+
+    if (rtl8366_readRegister(RTL8366S_LED_INDICATED_CONF_REG, &regData)) {
+        printf("rtl8366s_getLedConfig: failed to get led register!\n");
+        return -1;
+       }
+
+       if (config)
+        *config = (regData >> (ledNum * 4)) & 0xF;
+
+    return 0;
+}
+
+int rtl8366s_setLedForceValue(uint32_t group0, uint32_t group1,
+                              uint32_t group2, uint32_t group3)
+{
+    uint16_t regData;
+
+    regData = (group0 & 0x3F) | ((group1 & 0x3F) << 6);
+       if (rtl8366_writeRegister(RTL8366S_LED_0_1_FORCE_REG, regData)) {
+        printf("rtl8366s_setLedForceValue: failed to set led register!\n");
+        return -1;
+       }
+
+    regData = (group2 & 0x3F) | ((group3 & 0x3F) << 6);
+       if (rtl8366_writeRegister(RTL8366S_LED_2_3_FORCE_REG, regData)) {
+        printf("rtl8366s_setLedForceValue: failed to set led register!\n");
+        return -1;
+       }
+
+       return 0;
+}
+
+int rtl8366s_initChip(void)
+{
+    uint32_t ledGroup, i = 0;
+    uint16_t regData;
+    uint8_t ledData[RTL8366S_LED_GROUP_MAX];
+       const uint16_t (*chipData)[2];
+
+       const uint16_t chipB[][2] =
+       {
+               {0x0000,        0x0038},{0x8100,        0x1B37},{0xBE2E,        0x7B9F},{0xBE2B,        0xA4C8},
+               {0xBE74,        0xAD14},{0xBE2C,        0xDC00},{0xBE69,        0xD20F},{0xBE3B,        0xB414},
+               {0xBE24,        0x0000},{0xBE23,        0x00A1},{0xBE22,        0x0008},{0xBE21,        0x0120},
+               {0xBE20,        0x1000},{0xBE24,        0x0800},{0xBE24,        0x0000},{0xBE24,        0xF000},
+               {0xBE23,        0xDF01},{0xBE22,        0xDF20},{0xBE21,        0x101A},{0xBE20,        0xA0FF},
+               {0xBE24,        0xF800},{0xBE24,        0xF000},{0x0242,        0x02BF},{0x0245,        0x02BF},
+               {0x0248,        0x02BF},{0x024B,        0x02BF},{0x024E,        0x02BF},{0x0251,        0x02BF},
+               {0x0230,        0x0A32},{0x0233,        0x0A32},{0x0236,        0x0A32},{0x0239,        0x0A32},
+               {0x023C,        0x0A32},{0x023F,        0x0A32},{0x0254,        0x0A3F},{0x0255,        0x0064},
+               {0x0256,        0x0A3F},{0x0257,        0x0064},{0x0258,        0x0A3F},{0x0259,        0x0064},
+               {0x025A,        0x0A3F},{0x025B,        0x0064},{0x025C,        0x0A3F},{0x025D,        0x0064},
+               {0x025E,        0x0A3F},{0x025F,        0x0064},{0x0260,        0x0178},{0x0261,        0x01F4},
+               {0x0262,        0x0320},{0x0263,        0x0014},{0x021D,        0x9249},{0x021E,        0x0000},
+               {0x0100,        0x0004},{0xBE4A,        0xA0B4},{0xBE40,        0x9C00},{0xBE41,        0x501D},
+               {0xBE48,        0x3602},{0xBE47,        0x8051},{0xBE4C,        0x6465},{0x8000,        0x1F00},
+               {0x8001,        0x000C},{0x8008,        0x0000},{0x8007,        0x0000},{0x800C,        0x00A5},
+               {0x8101,        0x02BC},{0xBE53,        0x0005},{0x8E45,        0xAFE8},{0x8013,        0x0005},
+               {0xBE4B,        0x6700},{0x800B,        0x7000},{0xBE09,        0x0E00},
+               {0xFFFF, 0xABCD}
+       };
+
+    const uint16_t chipDefault[][2] =
+    {
+        {0x0242, 0x02BF},{0x0245, 0x02BF},{0x0248, 0x02BF},{0x024B, 0x02BF},
+               {0x024E, 0x02BF},{0x0251, 0x02BF},
+               {0x0254, 0x0A3F},{0x0256, 0x0A3F},{0x0258, 0x0A3F},{0x025A, 0x0A3F},
+               {0x025C, 0x0A3F},{0x025E, 0x0A3F},
+               {0x0263, 0x007C},{0x0100, 0x0004},
+               {0xBE5B, 0x3500},{0x800E, 0x200F},{0xBE1D, 0x0F00},{0x8001, 0x5011},
+               {0x800A, 0xA2F4},{0x800B, 0x17A3},{0xBE4B, 0x17A3},{0xBE41, 0x5011},
+               {0xBE17, 0x2100},{0x8000, 0x8304},{0xBE40, 0x8304},{0xBE4A, 0xA2F4},
+               {0x800C, 0xA8D5},{0x8014, 0x5500},{0x8015, 0x0004},{0xBE4C, 0xA8D5},
+               {0xBE59, 0x0008},{0xBE09, 0x0E00},{0xBE36, 0x1036},{0xBE37, 0x1036},
+               {0x800D, 0x00FF},{0xBE4D, 0x00FF},
+               {0xFFFF, 0xABCD}
+    };
+
+       DBG("rtl8366s_initChip\n");
+
+    /* save current led config and set to led force */
+    for (ledGroup = 0; ledGroup < RTL8366S_LED_GROUP_MAX; ledGroup++) {
+        if (rtl8366s_getLedConfig(ledGroup, &ledData[ledGroup]))
+            return -1;
+
+        if (rtl8366s_setLedConfig(ledGroup, RTL8366S_LEDCONF_LEDFORCE))
+            return -1;
+    }
+
+    if (rtl8366s_setLedForceValue(0,0,0,0))
+        return -1;
+
+    if (rtl8366_readRegister(RTL8366S_MODEL_ID_REG, &regData))
+        return -1;
+
+       switch (regData)
+       {
+               case 0x0000:
+                       chipData = chipB;
+                       break;
+
+               case RTL8366S_MODEL_8366SR:
+                       chipData = chipDefault;
+                       break;
+
+               default:
+                       printf("rtl8366s_initChip: unsupported chip found!\n");
+                       return -1;
+       }
+
+    DBG("rtl8366s_initChip: found %x chip\n", regData);
+
+    while ((chipData[i][0] != 0xFFFF) && (chipData[i][1] != 0xABCD)) {
+
+        /* phy settings*/
+        if ((chipData[i][0] & 0xBE00) == 0xBE00) {
+            if (rtl8366_writeRegister(RTL8366S_PHY_ACCESS_CTRL_REG,
+                                      RTL8366S_PHY_CTRL_WRITE))
+                return -1;
+        }
+
+        if (rtl8366_writeRegister(chipData[i][0], chipData[i][1]))
+            return -1;
+
+        i++;
+    }
+
+    /* chip needs some time */
+    udelay(100 * 1000);
+
+    /* restore led config */
+    for (ledGroup = 0; ledGroup < RTL8366S_LED_GROUP_MAX; ledGroup++) {
+        if (rtl8366s_setLedConfig(ledGroup, ledData[ledGroup]))
+            return -1;
+    }
+
+    return 0;
+}
+
+int rtl8366s_initialize(void)
+{
+       uint16_t regData;
+
+    DBG("rtl8366s_initialize: start setup\n");
+
+    smi_init();
+
+       rtl8366_readRegister(RTL8366S_CHIP_ID_REG, &regData);
+       DBG("Realtek 8366SR switch ID %#04x\n", regData);
+
+       if (regData != 0x8366) {
+               printf("rtl8366s_initialize: found unsupported switch\n");
+               return -1;
+       }
+
+    if (rtl8366s_initChip()) {
+        printf("rtl8366s_initialize: init chip failed\n");
+        return -1;
+    }
+
+       if (rtl8366s_setGreenEthernet(1, 1)) {
+       printf("rtl8366s_initialize: set green ethernet failed\n");
+       return -1;
+   }
+
+       /* Set port 5 noTag and don't dropUnda */
+       if (rtl8366s_setCPUPort(5, 1, 0)) {
+               printf("rtl8366s_initialize: set CPU port failed\n");
+               return -1;
+       }
+
+    return 0;
+}
diff --git a/package/boot/uboot-ar71xx/files/drivers/spi/ar71xx_spi.c b/package/boot/uboot-ar71xx/files/drivers/spi/ar71xx_spi.c
new file mode 100644 (file)
index 0000000..bbe27b1
--- /dev/null
@@ -0,0 +1,191 @@
+/*
+ * (C) Copyright 2010
+ * Michael Kurz <michi.kurz@googlemail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <spi.h>
+
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <asm/ar71xx.h>
+
+/*-----------------------------------------------------------------------
+ * Definitions
+ */
+
+#ifdef DEBUG_SPI
+#define PRINTD(fmt,args...)    printf (fmt ,##args)
+#else
+#define PRINTD(fmt,args...)
+#endif
+
+struct ar71xx_spi_slave {
+       struct spi_slave slave;
+       unsigned int mode;
+};
+
+static inline struct ar71xx_spi_slave *to_ar71xx_spi(struct spi_slave *slave)
+{
+       return container_of(slave, struct ar71xx_spi_slave, slave);
+}
+
+/*=====================================================================*/
+/*                         Public Functions                            */
+/*=====================================================================*/
+
+/*-----------------------------------------------------------------------
+ * Initialization
+ */
+void spi_init()
+{
+       PRINTD("ar71xx_spi: spi_init");
+
+       // Init SPI Hardware, disable remap, set clock
+       __raw_writel(0x43, KSEG1ADDR(AR71XX_SPI_BASE + SPI_REG_CTRL));
+       
+       PRINTD(" ---> out\n");
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+               unsigned int max_hz, unsigned int mode)
+{
+       struct ar71xx_spi_slave *ss;
+
+       PRINTD("ar71xx_spi: spi_setup_slave");
+       
+       if ((bus != 0) || (cs > 2))
+               return NULL;
+
+       ss = malloc(sizeof(struct ar71xx_spi_slave));
+       if (!ss)
+               return NULL;
+
+       ss->slave.bus = bus;
+       ss->slave.cs = cs;
+       ss->mode = mode;
+
+       /* TODO: Use max_hz to limit the SCK rate */
+
+       PRINTD(" ---> out\n");
+       
+       return &ss->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+       struct ar71xx_spi_slave *ss = to_ar71xx_spi(slave);
+
+       free(ss);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+
+       return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+               void *din, unsigned long flags)
+{
+       struct ar71xx_spi_slave *ss = to_ar71xx_spi(slave);
+       uint8_t *rx = din;
+       const uint8_t *tx = dout;
+       uint8_t curbyte, curbitlen, restbits;
+       uint32_t bytes = bitlen / 8;
+       uint32_t out;
+       uint32_t in;
+       
+       PRINTD("ar71xx_spi: spi_xfer: slave:%p bitlen:%08x dout:%p din:%p flags:%08x\n", slave, bitlen, dout, din, flags);
+       
+       if (flags & SPI_XFER_BEGIN) {
+               __raw_writel(SPI_FS_GPIO, KSEG1ADDR(AR71XX_SPI_BASE + SPI_REG_FS));
+               __raw_writel(SPI_IOC_CS_ALL, KSEG1ADDR(AR71XX_SPI_BASE + SPI_REG_IOC));
+       }
+       
+       restbits = (bitlen % 8);
+       if (restbits != 0)
+               bytes++;
+
+       // enable chip select
+       out = SPI_IOC_CS_ALL & ~(SPI_IOC_CS(slave->cs));
+
+       while (bytes--) {
+               
+               curbyte = 0;
+               if (tx) {
+                       curbyte = *tx++;
+               }
+               
+               if (restbits != 0) {
+                       curbitlen = restbits;
+                       curbyte <<= 8 - restbits;
+               } else {
+                       curbitlen = 8;
+               }
+               
+               PRINTD("ar71xx_spi: sending: data:%02x length:%d\n", curbyte, curbitlen);
+               
+               /* clock starts at inactive polarity */
+               for (curbyte <<= (8 - curbitlen); curbitlen; curbitlen--) {
+
+                       if (curbyte & (1 << 7))
+                               out |= SPI_IOC_DO;
+                       else
+                               out &= ~(SPI_IOC_DO);
+
+                       /* setup MSB (to slave) on trailing edge */
+                       __raw_writel(out, KSEG1ADDR(AR71XX_SPI_BASE + SPI_REG_IOC));
+
+                       __raw_writel(out | SPI_IOC_CLK, KSEG1ADDR(AR71XX_SPI_BASE + SPI_REG_IOC));
+
+                       curbyte <<= 1;
+               }
+               
+               in = __raw_readl(KSEG1ADDR(AR71XX_SPI_BASE + SPI_REG_RDS));
+               PRINTD("ar71xx_spi: received:%02x\n", in);
+               
+               if (rx) {
+                       if (restbits == 0) {
+                               *rx++ = in;
+                       } else {
+                               *rx++ = (in << (8 - restbits));
+                       }
+               }
+       }
+       
+       if (flags & SPI_XFER_END) {
+               __raw_writel(SPI_IOC_CS(slave->cs), KSEG1ADDR(AR71XX_SPI_BASE + SPI_REG_IOC));
+               __raw_writel(SPI_IOC_CS_ALL, KSEG1ADDR(AR71XX_SPI_BASE + SPI_REG_IOC));
+               __raw_writel(0, KSEG1ADDR(AR71XX_SPI_BASE + SPI_REG_FS));
+       }
+
+       PRINTD(" ---> out\n");
+       
+       return 0;
+}
diff --git a/package/boot/uboot-ar71xx/files/include/asm-mips/ar71xx.h b/package/boot/uboot-ar71xx/files/include/asm-mips/ar71xx.h
new file mode 100644 (file)
index 0000000..e8f3f61
--- /dev/null
@@ -0,0 +1,515 @@
+/*
+ *  Atheros AR71xx SoC specific definitions
+ *
+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  Parts of this file are based on Atheros' 2.6.15 BSP
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_AR71XX_H
+#define __ASM_MACH_AR71XX_H
+
+#include <linux/types.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+
+#ifndef __ASSEMBLER__
+
+#define BIT(x) (1<<(x))
+
+#define AR71XX_PCI_MEM_BASE    0x10000000
+#define AR71XX_PCI_MEM_SIZE    0x08000000
+#define AR71XX_APB_BASE                0x18000000
+#define AR71XX_GE0_BASE                0x19000000
+#define AR71XX_GE0_SIZE                0x01000000
+#define AR71XX_GE1_BASE                0x1a000000
+#define AR71XX_GE1_SIZE                0x01000000
+#define AR71XX_EHCI_BASE       0x1b000000
+#define AR71XX_EHCI_SIZE       0x01000000
+#define AR71XX_OHCI_BASE       0x1c000000
+#define AR71XX_OHCI_SIZE       0x01000000
+#define AR7240_OHCI_BASE       0x1b000000
+#define AR7240_OHCI_SIZE       0x01000000
+#define AR71XX_SPI_BASE                0x1f000000
+#define AR71XX_SPI_SIZE                0x01000000
+
+#define AR71XX_DDR_CTRL_BASE   (AR71XX_APB_BASE + 0x00000000)
+#define AR71XX_DDR_CTRL_SIZE   0x10000
+#define AR71XX_CPU_BASE                (AR71XX_APB_BASE + 0x00010000)
+#define AR71XX_UART_BASE       (AR71XX_APB_BASE + 0x00020000)
+#define AR71XX_UART_SIZE       0x10000
+#define AR71XX_USB_CTRL_BASE   (AR71XX_APB_BASE + 0x00030000)
+#define AR71XX_USB_CTRL_SIZE   0x10000
+#define AR71XX_GPIO_BASE       (AR71XX_APB_BASE + 0x00040000)
+#define AR71XX_GPIO_SIZE       0x10000
+#define AR71XX_PLL_BASE                (AR71XX_APB_BASE + 0x00050000)
+#define AR71XX_PLL_SIZE                0x10000
+#define AR71XX_RESET_BASE      (AR71XX_APB_BASE + 0x00060000)
+#define AR71XX_RESET_SIZE      0x10000
+#define AR71XX_MII_BASE                (AR71XX_APB_BASE + 0x00070000)
+#define AR71XX_MII_SIZE                0x10000
+#define AR71XX_SLIC_BASE       (AR71XX_APB_BASE + 0x00090000)
+#define AR71XX_SLIC_SIZE       0x10000
+#define AR71XX_DMA_BASE                (AR71XX_APB_BASE + 0x000A0000)
+#define AR71XX_DMA_SIZE                0x10000
+#define AR71XX_STEREO_BASE     (AR71XX_APB_BASE + 0x000B0000)
+#define AR71XX_STEREO_SIZE     0x10000
+
+#define AR724X_PCI_CRP_BASE    (AR71XX_APB_BASE + 0x000C0000)
+#define AR724X_PCI_CRP_SIZE    0x100
+
+#define AR724X_PCI_CTRL_BASE   (AR71XX_APB_BASE + 0x000F0000)
+#define AR724X_PCI_CTRL_SIZE   0x100
+
+#define AR91XX_WMAC_BASE       (AR71XX_APB_BASE + 0x000C0000)
+#define AR91XX_WMAC_SIZE       0x30000
+
+#define AR71XX_MEM_SIZE_MIN    0x0200000
+#define AR71XX_MEM_SIZE_MAX    0x10000000
+
+#define AR71XX_CPU_IRQ_BASE    0
+#define AR71XX_MISC_IRQ_BASE   8
+#define AR71XX_MISC_IRQ_COUNT  8
+#define AR71XX_GPIO_IRQ_BASE   16
+#define AR71XX_GPIO_IRQ_COUNT  32
+#define AR71XX_PCI_IRQ_BASE     48
+#define AR71XX_PCI_IRQ_COUNT   8
+
+#define AR71XX_CPU_IRQ_IP2     (AR71XX_CPU_IRQ_BASE + 2)
+#define AR71XX_CPU_IRQ_USB     (AR71XX_CPU_IRQ_BASE + 3)
+#define AR71XX_CPU_IRQ_GE0     (AR71XX_CPU_IRQ_BASE + 4)
+#define AR71XX_CPU_IRQ_GE1     (AR71XX_CPU_IRQ_BASE + 5)
+#define AR71XX_CPU_IRQ_MISC    (AR71XX_CPU_IRQ_BASE + 6)
+#define AR71XX_CPU_IRQ_TIMER   (AR71XX_CPU_IRQ_BASE + 7)
+
+#define AR71XX_MISC_IRQ_TIMER  (AR71XX_MISC_IRQ_BASE + 0)
+#define AR71XX_MISC_IRQ_ERROR  (AR71XX_MISC_IRQ_BASE + 1)
+#define AR71XX_MISC_IRQ_GPIO   (AR71XX_MISC_IRQ_BASE + 2)
+#define AR71XX_MISC_IRQ_UART   (AR71XX_MISC_IRQ_BASE + 3)
+#define AR71XX_MISC_IRQ_WDOG   (AR71XX_MISC_IRQ_BASE + 4)
+#define AR71XX_MISC_IRQ_PERFC  (AR71XX_MISC_IRQ_BASE + 5)
+#define AR71XX_MISC_IRQ_OHCI   (AR71XX_MISC_IRQ_BASE + 6)
+#define AR71XX_MISC_IRQ_DMA    (AR71XX_MISC_IRQ_BASE + 7)
+
+#define AR71XX_GPIO_IRQ(_x)    (AR71XX_GPIO_IRQ_BASE + (_x))
+
+#define AR71XX_PCI_IRQ_DEV0    (AR71XX_PCI_IRQ_BASE + 0)
+#define AR71XX_PCI_IRQ_DEV1    (AR71XX_PCI_IRQ_BASE + 1)
+#define AR71XX_PCI_IRQ_DEV2    (AR71XX_PCI_IRQ_BASE + 2)
+#define AR71XX_PCI_IRQ_CORE    (AR71XX_PCI_IRQ_BASE + 4)
+
+extern u32 ar71xx_ahb_freq;
+extern u32 ar71xx_cpu_freq;
+extern u32 ar71xx_ddr_freq;
+
+enum ar71xx_soc_type {
+       AR71XX_SOC_UNKNOWN,
+       AR71XX_SOC_AR7130,
+       AR71XX_SOC_AR7141,
+       AR71XX_SOC_AR7161,
+       AR71XX_SOC_AR7240,
+       AR71XX_SOC_AR7241,
+       AR71XX_SOC_AR7242,
+       AR71XX_SOC_AR9130,
+       AR71XX_SOC_AR9132
+};
+
+extern enum ar71xx_soc_type ar71xx_soc;
+
+/*
+ * PLL block
+ */
+#define AR71XX_PLL_REG_CPU_CONFIG      0x00
+#define AR71XX_PLL_REG_SEC_CONFIG      0x04
+#define AR71XX_PLL_REG_ETH0_INT_CLOCK  0x10
+#define AR71XX_PLL_REG_ETH1_INT_CLOCK  0x14
+
+#define AR71XX_PLL_DIV_SHIFT           3
+#define AR71XX_PLL_DIV_MASK            0x1f
+#define AR71XX_CPU_DIV_SHIFT           16
+#define AR71XX_CPU_DIV_MASK            0x3
+#define AR71XX_DDR_DIV_SHIFT           18
+#define AR71XX_DDR_DIV_MASK            0x3
+#define AR71XX_AHB_DIV_SHIFT           20
+#define AR71XX_AHB_DIV_MASK            0x7
+
+#define AR71XX_ETH0_PLL_SHIFT          17
+#define AR71XX_ETH1_PLL_SHIFT          19
+
+#define AR724X_PLL_REG_CPU_CONFIG      0x00
+#define AR724X_PLL_REG_PCIE_CONFIG     0x18
+
+#define AR724X_PLL_DIV_SHIFT           0
+#define AR724X_PLL_DIV_MASK            0x3ff
+#define AR724X_PLL_REF_DIV_SHIFT       10
+#define AR724X_PLL_REF_DIV_MASK                0xf
+#define AR724X_AHB_DIV_SHIFT           19
+#define AR724X_AHB_DIV_MASK            0x1
+#define AR724X_DDR_DIV_SHIFT           22
+#define AR724X_DDR_DIV_MASK            0x3
+
+#define AR91XX_PLL_REG_CPU_CONFIG      0x00
+#define AR91XX_PLL_REG_ETH_CONFIG      0x04
+#define AR91XX_PLL_REG_ETH0_INT_CLOCK  0x14
+#define AR91XX_PLL_REG_ETH1_INT_CLOCK  0x18
+
+#define AR91XX_PLL_DIV_SHIFT           0
+#define AR91XX_PLL_DIV_MASK            0x3ff
+#define AR91XX_DDR_DIV_SHIFT           22
+#define AR91XX_DDR_DIV_MASK            0x3
+#define AR91XX_AHB_DIV_SHIFT           19
+#define AR91XX_AHB_DIV_MASK            0x1
+
+#define AR91XX_ETH0_PLL_SHIFT          20
+#define AR91XX_ETH1_PLL_SHIFT          22
+
+// extern void __iomem *ar71xx_pll_base;
+
+// static inline void ar71xx_pll_wr(unsigned reg, u32 val)
+// {
+       // __raw_writel(val, ar71xx_pll_base + reg);
+// }
+
+// static inline u32 ar71xx_pll_rr(unsigned reg)
+// {
+       // return __raw_readl(ar71xx_pll_base + reg);
+// }
+
+/*
+ * USB_CONFIG block
+ */
+#define USB_CTRL_REG_FLADJ     0x00
+#define USB_CTRL_REG_CONFIG    0x04
+
+// extern void __iomem *ar71xx_usb_ctrl_base;
+
+// static inline void ar71xx_usb_ctrl_wr(unsigned reg, u32 val)
+// {
+       // __raw_writel(val, ar71xx_usb_ctrl_base + reg);
+// }
+
+// static inline u32 ar71xx_usb_ctrl_rr(unsigned reg)
+// {
+       // return __raw_readl(ar71xx_usb_ctrl_base + reg);
+// }
+
+/*
+ * GPIO block
+ */
+#define GPIO_REG_OE            0x00
+#define GPIO_REG_IN            0x04
+#define GPIO_REG_OUT           0x08
+#define GPIO_REG_SET           0x0c
+#define GPIO_REG_CLEAR         0x10
+#define GPIO_REG_INT_MODE      0x14
+#define GPIO_REG_INT_TYPE      0x18
+#define GPIO_REG_INT_POLARITY  0x1c
+#define GPIO_REG_INT_PENDING   0x20
+#define GPIO_REG_INT_ENABLE    0x24
+#define GPIO_REG_FUNC          0x28
+
+#define AR71XX_GPIO_FUNC_STEREO_EN     BIT(17)
+#define AR71XX_GPIO_FUNC_SLIC_EN       BIT(16)
+#define AR71XX_GPIO_FUNC_SPI_CS2_EN    BIT(13)
+#define AR71XX_GPIO_FUNC_SPI_CS1_EN    BIT(12)
+#define AR71XX_GPIO_FUNC_UART_EN       BIT(8)
+#define AR71XX_GPIO_FUNC_USB_OC_EN     BIT(4)
+#define AR71XX_GPIO_FUNC_USB_CLK_EN    BIT(0)
+
+#define AR71XX_GPIO_COUNT      16
+
+#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN                BIT(19)
+#define AR724X_GPIO_FUNC_SPI_EN                        BIT(18)
+#define AR724X_GPIO_FUNC_SPI_CS_EN2            BIT(14)
+#define AR724X_GPIO_FUNC_SPI_CS_EN1            BIT(13)
+#define AR724X_GPIO_FUNC_CLK_OBS5_EN           BIT(12)
+#define AR724X_GPIO_FUNC_CLK_OBS4_EN           BIT(11)
+#define AR724X_GPIO_FUNC_CLK_OBS3_EN           BIT(10)
+#define AR724X_GPIO_FUNC_CLK_OBS2_EN           BIT(9)
+#define AR724X_GPIO_FUNC_CLK_OBS1_EN           BIT(8)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN    BIT(7)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN    BIT(6)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN    BIT(5)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN    BIT(4)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN    BIT(3)
+#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN       BIT(2)
+#define AR724X_GPIO_FUNC_UART_EN               BIT(1)
+#define AR724X_GPIO_FUNC_JTAG_DISABLE          BIT(0)
+
+#define AR724X_GPIO_COUNT      18
+
+#define AR91XX_GPIO_FUNC_WMAC_LED_EN   BIT(22)
+#define AR91XX_GPIO_FUNC_EXP_PORT_CS_EN        BIT(21)
+#define AR91XX_GPIO_FUNC_I2S_REFCLKEN  BIT(20)
+#define AR91XX_GPIO_FUNC_I2S_MCKEN     BIT(19)
+#define AR91XX_GPIO_FUNC_I2S1_EN       BIT(18)
+#define AR91XX_GPIO_FUNC_I2S0_EN       BIT(17)
+#define AR91XX_GPIO_FUNC_SLIC_EN       BIT(16)
+#define AR91XX_GPIO_FUNC_UART_RTSCTS_EN        BIT(9)
+#define AR91XX_GPIO_FUNC_UART_EN       BIT(8)
+#define AR91XX_GPIO_FUNC_USB_CLK_EN    BIT(4)
+
+#define AR91XX_GPIO_COUNT      22
+
+// extern void __iomem *ar71xx_gpio_base;
+
+// static inline void ar71xx_gpio_wr(unsigned reg, u32 value)
+// {
+       // __raw_writel(value, ar71xx_gpio_base + reg);
+// }
+
+// static inline u32 ar71xx_gpio_rr(unsigned reg)
+// {
+       // return __raw_readl(ar71xx_gpio_base + reg);
+// }
+
+// void ar71xx_gpio_init(void) __init;
+// void ar71xx_gpio_function_enable(u32 mask);
+// void ar71xx_gpio_function_disable(u32 mask);
+// void ar71xx_gpio_function_setup(u32 set, u32 clear);
+
+/*
+ * DDR_CTRL block
+ */
+#define AR71XX_DDR_REG_PCI_WIN0                0x7c
+#define AR71XX_DDR_REG_PCI_WIN1                0x80
+#define AR71XX_DDR_REG_PCI_WIN2                0x84
+#define AR71XX_DDR_REG_PCI_WIN3                0x88
+#define AR71XX_DDR_REG_PCI_WIN4                0x8c
+#define AR71XX_DDR_REG_PCI_WIN5                0x90
+#define AR71XX_DDR_REG_PCI_WIN6                0x94
+#define AR71XX_DDR_REG_PCI_WIN7                0x98
+#define AR71XX_DDR_REG_FLUSH_GE0       0x9c
+#define AR71XX_DDR_REG_FLUSH_GE1       0xa0
+#define AR71XX_DDR_REG_FLUSH_USB       0xa4
+#define AR71XX_DDR_REG_FLUSH_PCI       0xa8
+
+#define AR724X_DDR_REG_FLUSH_GE0       0x7c
+#define AR724X_DDR_REG_FLUSH_GE1       0x80
+#define AR724X_DDR_REG_FLUSH_USB       0x84
+#define AR724X_DDR_REG_FLUSH_PCIE      0x88
+
+#define AR91XX_DDR_REG_FLUSH_GE0       0x7c
+#define AR91XX_DDR_REG_FLUSH_GE1       0x80
+#define AR91XX_DDR_REG_FLUSH_USB       0x84
+#define AR91XX_DDR_REG_FLUSH_WMAC      0x88
+
+#define PCI_WIN0_OFFS  0x10000000
+#define PCI_WIN1_OFFS  0x11000000
+#define PCI_WIN2_OFFS  0x12000000
+#define PCI_WIN3_OFFS  0x13000000
+#define PCI_WIN4_OFFS  0x14000000
+#define PCI_WIN5_OFFS  0x15000000
+#define PCI_WIN6_OFFS  0x16000000
+#define PCI_WIN7_OFFS  0x07000000
+
+// extern void __iomem *ar71xx_ddr_base;
+
+// static inline void ar71xx_ddr_wr(unsigned reg, u32 val)
+// {
+       // __raw_writel(val, ar71xx_ddr_base + reg);
+// }
+
+// static inline u32 ar71xx_ddr_rr(unsigned reg)
+// {
+       // return __raw_readl(ar71xx_ddr_base + reg);
+// }
+
+// void ar71xx_ddr_flush(u32 reg);
+
+/*
+ * PCI block
+ */
+#define AR71XX_PCI_CFG_BASE    (AR71XX_PCI_MEM_BASE + PCI_WIN7_OFFS + 0x10000)
+#define AR71XX_PCI_CFG_SIZE    0x100
+
+#define PCI_REG_CRP_AD_CBE     0x00
+#define PCI_REG_CRP_WRDATA     0x04
+#define PCI_REG_CRP_RDDATA     0x08
+#define PCI_REG_CFG_AD         0x0c
+#define PCI_REG_CFG_CBE                0x10
+#define PCI_REG_CFG_WRDATA     0x14
+#define PCI_REG_CFG_RDDATA     0x18
+#define PCI_REG_PCI_ERR                0x1c
+#define PCI_REG_PCI_ERR_ADDR   0x20
+#define PCI_REG_AHB_ERR                0x24
+#define PCI_REG_AHB_ERR_ADDR   0x28
+
+#define PCI_CRP_CMD_WRITE      0x00010000
+#define PCI_CRP_CMD_READ       0x00000000
+#define PCI_CFG_CMD_READ       0x0000000a
+#define PCI_CFG_CMD_WRITE      0x0000000b
+
+#define PCI_IDSEL_ADL_START    17
+
+#define AR724X_PCI_CFG_BASE    (AR71XX_PCI_MEM_BASE + 0x4000000)
+#define AR724X_PCI_CFG_SIZE    0x1000
+
+#define AR724X_PCI_REG_APP             0x00
+#define AR724X_PCI_REG_RESET           0x18
+#define AR724X_PCI_REG_INT_STATUS      0x4c
+#define AR724X_PCI_REG_INT_MASK                0x50
+
+#define AR724X_PCI_APP_LTSSM_ENABLE    BIT(0)
+#define AR724X_PCI_RESET_LINK_UP       BIT(0)
+
+#define AR724X_PCI_INT_DEV0            BIT(14)
+
+/*
+ * RESET block
+ */
+#define AR71XX_RESET_REG_TIMER                 0x00
+#define AR71XX_RESET_REG_TIMER_RELOAD          0x04
+#define AR71XX_RESET_REG_WDOG_CTRL             0x08
+#define AR71XX_RESET_REG_WDOG                  0x0c
+#define AR71XX_RESET_REG_MISC_INT_STATUS       0x10
+#define AR71XX_RESET_REG_MISC_INT_ENABLE       0x14
+#define AR71XX_RESET_REG_PCI_INT_STATUS                0x18
+#define AR71XX_RESET_REG_PCI_INT_ENABLE                0x1c
+#define AR71XX_RESET_REG_GLOBAL_INT_STATUS     0x20
+#define AR71XX_RESET_REG_RESET_MODULE          0x24
+#define AR71XX_RESET_REG_PERFC_CTRL            0x2c
+#define AR71XX_RESET_REG_PERFC0                        0x30
+#define AR71XX_RESET_REG_PERFC1                        0x34
+#define AR71XX_RESET_REG_REV_ID                        0x90
+
+#define AR91XX_RESET_REG_GLOBAL_INT_STATUS     0x18
+#define AR91XX_RESET_REG_RESET_MODULE          0x1c
+#define AR91XX_RESET_REG_PERF_CTRL             0x20
+#define AR91XX_RESET_REG_PERFC0                        0x24
+#define AR91XX_RESET_REG_PERFC1                        0x28
+
+#define AR724X_RESET_REG_RESET_MODULE          0x1c
+
+#define WDOG_CTRL_LAST_RESET           BIT(31)
+#define WDOG_CTRL_ACTION_MASK          3
+#define WDOG_CTRL_ACTION_NONE          0       /* no action */
+#define WDOG_CTRL_ACTION_GPI           1       /* general purpose interrupt */
+#define WDOG_CTRL_ACTION_NMI           2       /* NMI */
+#define WDOG_CTRL_ACTION_FCR           3       /* full chip reset */
+
+#define MISC_INT_DMA                   BIT(7)
+#define MISC_INT_OHCI                  BIT(6)
+#define MISC_INT_PERFC                 BIT(5)
+#define MISC_INT_WDOG                  BIT(4)
+#define MISC_INT_UART                  BIT(3)
+#define MISC_INT_GPIO                  BIT(2)
+#define MISC_INT_ERROR                 BIT(1)
+#define MISC_INT_TIMER                 BIT(0)
+
+#define PCI_INT_CORE                   BIT(4)
+#define PCI_INT_DEV2                   BIT(2)
+#define PCI_INT_DEV1                   BIT(1)
+#define PCI_INT_DEV0                   BIT(0)
+
+#define RESET_MODULE_EXTERNAL          BIT(28)
+#define RESET_MODULE_FULL_CHIP         BIT(24)
+#define RESET_MODULE_AMBA2WMAC         BIT(22)
+#define RESET_MODULE_CPU_NMI           BIT(21)
+#define RESET_MODULE_CPU_COLD          BIT(20)
+#define RESET_MODULE_DMA               BIT(19)
+#define RESET_MODULE_SLIC              BIT(18)
+#define RESET_MODULE_STEREO            BIT(17)
+#define RESET_MODULE_DDR               BIT(16)
+#define RESET_MODULE_GE1_MAC           BIT(13)
+#define RESET_MODULE_GE1_PHY           BIT(12)
+#define RESET_MODULE_USBSUS_OVERRIDE   BIT(10)
+#define RESET_MODULE_GE0_MAC           BIT(9)
+#define RESET_MODULE_GE0_PHY           BIT(8)
+#define RESET_MODULE_USB_OHCI_DLL      BIT(6)
+#define RESET_MODULE_USB_HOST          BIT(5)
+#define RESET_MODULE_USB_PHY           BIT(4)
+#define RESET_MODULE_USB_OHCI_DLL_7240 BIT(3)
+#define RESET_MODULE_PCI_BUS           BIT(1)
+#define RESET_MODULE_PCI_CORE          BIT(0)
+
+#define AR724X_RESET_GE1_MDIO          BIT(23)
+#define AR724X_RESET_GE0_MDIO          BIT(22)
+#define AR724X_RESET_PCIE_PHY_SERIAL   BIT(10)
+#define AR724X_RESET_PCIE_PHY          BIT(7)
+#define AR724X_RESET_PCIE              BIT(6)
+
+#define REV_ID_MAJOR_MASK      0xfff0
+#define REV_ID_MAJOR_AR71XX    0x00a0
+#define REV_ID_MAJOR_AR913X    0x00b0
+#define REV_ID_MAJOR_AR7240    0x00c0
+#define REV_ID_MAJOR_AR7241    0x0100
+#define REV_ID_MAJOR_AR7242    0x1100
+
+#define AR71XX_REV_ID_MINOR_MASK       0x3
+#define AR71XX_REV_ID_MINOR_AR7130     0x0
+#define AR71XX_REV_ID_MINOR_AR7141     0x1
+#define AR71XX_REV_ID_MINOR_AR7161     0x2
+#define AR71XX_REV_ID_REVISION_MASK    0x3
+#define AR71XX_REV_ID_REVISION_SHIFT   2
+
+#define AR91XX_REV_ID_MINOR_MASK       0x3
+#define AR91XX_REV_ID_MINOR_AR9130     0x0
+#define AR91XX_REV_ID_MINOR_AR9132     0x1
+#define AR91XX_REV_ID_REVISION_MASK    0x3
+#define AR91XX_REV_ID_REVISION_SHIFT   2
+
+#define AR724X_REV_ID_REVISION_MASK    0x3
+
+// extern void __iomem *ar71xx_reset_base;
+
+static inline void ar71xx_reset_wr(unsigned reg, u32 val)
+{
+       __raw_writel(val, KSEG1ADDR(AR71XX_RESET_BASE) + reg);
+}
+
+static inline u32 ar71xx_reset_rr(unsigned reg)
+{
+       return __raw_readl(KSEG1ADDR(AR71XX_RESET_BASE) + reg);
+}
+
+// void ar71xx_device_stop(u32 mask);
+// void ar71xx_device_start(u32 mask);
+// int ar71xx_device_stopped(u32 mask);
+
+/*
+ * SPI block
+ */
+#define SPI_REG_FS             0x00    /* Function Select */
+#define SPI_REG_CTRL           0x04    /* SPI Control */
+#define SPI_REG_IOC            0x08    /* SPI I/O Control */
+#define SPI_REG_RDS            0x0c    /* Read Data Shift */
+
+#define SPI_FS_GPIO            BIT(0)  /* Enable GPIO mode */
+
+#define SPI_CTRL_RD            BIT(6)  /* Remap Disable */
+#define SPI_CTRL_DIV_MASK      0x3f
+
+#define SPI_IOC_DO             BIT(0)  /* Data Out pin */
+#define SPI_IOC_CLK            BIT(8)  /* CLK pin */
+#define SPI_IOC_CS(n)          BIT(16 + (n))
+#define SPI_IOC_CS0            SPI_IOC_CS(0)
+#define SPI_IOC_CS1            SPI_IOC_CS(1)
+#define SPI_IOC_CS2            SPI_IOC_CS(2)
+#define SPI_IOC_CS_ALL         (SPI_IOC_CS0 | SPI_IOC_CS1 | SPI_IOC_CS2)
+
+// void ar71xx_flash_acquire(void);
+// void ar71xx_flash_release(void);
+
+/*
+ * MII_CTRL block
+ */
+#define MII_REG_MII0_CTRL      0x00
+#define MII_REG_MII1_CTRL      0x04
+
+#define MII0_CTRL_IF_GMII      0
+#define MII0_CTRL_IF_MII       1
+#define MII0_CTRL_IF_RGMII     2
+#define MII0_CTRL_IF_RMII      3
+
+#define MII1_CTRL_IF_RGMII     0
+#define MII1_CTRL_IF_RMII      1
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* __ASM_MACH_AR71XX_H */
diff --git a/package/boot/uboot-ar71xx/files/include/asm-mips/ar71xx_gpio.h b/package/boot/uboot-ar71xx/files/include/asm-mips/ar71xx_gpio.h
new file mode 100644 (file)
index 0000000..c92364b
--- /dev/null
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2010
+ * Michael Kurz <michi.kurz@googlemail.com>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _AR71XX_GPIO_H
+#define _AR71XX_GPIO_H
+
+#include <common.h>
+#include <asm/ar71xx.h>
+
+static inline void ar71xx_setpin(uint8_t pin, uint8_t state)
+{
+       uint32_t reg = readl(KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_OUT));
+
+       if (state != 0) {
+       reg |= (1 << pin);
+   } else {
+       reg &= ~(1 << pin);
+   }
+
+       writel(reg, KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_OUT));
+       readl(KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_OUT));
+}
+
+static inline uint32_t ar71xx_getpin(uint8_t pin)
+{
+    uint32_t reg = readl(KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_IN));
+    return (((reg & (1 << pin)) != 0) ? 1 : 0);
+}
+
+static inline void ar71xx_setpindir(uint8_t pin, uint8_t direction)
+{
+       uint32_t reg = readl(KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_OE));
+
+       if (direction != 0) {
+        reg |= (1 << pin);
+    } else {
+        reg &= ~(1 << pin);
+    }
+
+       writel(reg, KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_OE));
+       readl(KSEG1ADDR(AR71XX_GPIO_BASE + GPIO_REG_OE));
+}
+
+
+#endif /* AR71XX_GPIO_H */
diff --git a/package/boot/uboot-ar71xx/files/include/configs/nbg460n.h b/package/boot/uboot-ar71xx/files/include/configs/nbg460n.h
new file mode 100644 (file)
index 0000000..dd9b4c3
--- /dev/null
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2010
+ * Michael Kurz <michi.kurz@googlemail.com>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* This file contains the configuration parameters for the zyxel nbg460n board. */
+
+#ifndef _NBG460N_CONFIG_H
+#define _NBG460N_CONFIG_H
+
+#define CONFIG_MIPS32          1  /* MIPS32 CPU core */
+#define CONFIG_AR71XX          1
+#define CONFIG_AR91XX          1
+#define CONFIG_SYS_HZ          1000
+#define CONFIG_SYS_MIPS_TIMER_FREQ (400000000/2)
+
+/* Cache Configuration */
+#define CONFIG_SYS_DCACHE_SIZE         32768
+#define CONFIG_SYS_ICACHE_SIZE         65536
+#define CONFIG_SYS_CACHELINE_SIZE      32
+/* Cache lock for stack */
+#define CONFIG_SYS_INIT_SP_OFFSET      0x1000
+
+#define CONFIG_SYS_MONITOR_BASE        (TEXT_BASE)
+
+#define CONFIG_BAUDRATE                115200
+#define CONFIG_SYS_BAUDRATE_TABLE  {115200}
+
+#define CONFIG_MISC_INIT_R
+
+/* SPI-Flash support */
+#define CONFIG_SPI_FLASH
+#define CONFIG_AR71XX_SPI
+#define CONFIG_SPI_FLASH_MACRONIX
+#define CONFIG_SF_DEFAULT_HZ   25000000
+
+#define CONFIG_ENV_SPI_MAX_HZ  25000000
+#define CONFIG_ENV_SPI_BUS             0
+#define CONFIG_ENV_SPI_CS              0
+
+#define        CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_ADDR                        0xbfc20000
+#define CONFIG_ENV_OFFSET              0x20000
+#define CONFIG_ENV_SIZE                        0x01000
+#define CONFIG_ENV_SECT_SIZE   0x10000
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 64
+#define CONFIG_SYS_FLASH_BASE  0xbfc00000
+
+/* Net support */
+#define CONFIG_ETHADDR_ADDR     0xbfc0fff8
+#define CONFIG_SYS_RX_ETH_BUFFER       16
+#define CONFIG_AG71XX
+#define CONFIG_AG71XX_PORTS     { 1, 1 }
+#define CONFIG_AG71XX_MII0_IIF  MII0_CTRL_IF_RGMII
+#define CONFIG_AG71XX_MII1_IIF  MII1_CTRL_IF_RGMII
+#define CONFIG_NET_MULTI
+#define CONFIG_IPADDR                  192.168.1.254
+#define CONFIG_SERVERIP                        192.168.1.42
+
+/* Switch support */
+#define CONFIG_MII
+#define CONFIG_RTL8366_MII
+#define RTL8366_PIN_SDA 16
+#define RTL8366_PIN_SCK 18
+#define MII_GPIOINCLUDE <asm/ar71xx_gpio.h>
+#define MII_SETSDA(x)   ar71xx_setpin(RTL8366_PIN_SDA, x)
+#define MII_GETSDA      ar71xx_getpin(RTL8366_PIN_SDA)
+#define MII_SETSCK(x)   ar71xx_setpin(RTL8366_PIN_SCK, x)
+#define MII_SDAINPUT    ar71xx_setpindir(RTL8366_PIN_SDA, 0)
+#define MII_SDAOUTPUT   ar71xx_setpindir(RTL8366_PIN_SDA, 1)
+#define MII_SCKINPUT    ar71xx_setpindir(RTL8366_PIN_SCK, 0)
+#define MII_SCKOUTPUT   ar71xx_setpindir(RTL8366_PIN_SCK, 1)
+
+#define CONFIG_BOOTDELAY       3
+#define        CONFIG_BOOTARGS         "console=ttyS0,115200 rootfstype==squashfs,jffs2 noinitrd machtype=NBG460N"
+#define CONFIG_BOOTCOMMAND     "bootm 0xbfc70000"
+#define CONFIG_LZMA
+
+
+/* Commands */
+#define CONFIG_SYS_NO_FLASH
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADS
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_SPI
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_PROMPT              "U-Boot> "
+#define CONFIG_SYS_CBSIZE              256
+#define CONFIG_SYS_MAXARGS             16
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP            1
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN          ROUND(3 * 0x10000 + 128*1024, 0x1000)
+#define CONFIG_SYS_GBL_DATA_SIZE       128     /* 128 bytes for initial data */
+
+#define CONFIG_SYS_BOOTPARAMS_LEN      128*1024
+
+#define CONFIG_SYS_SDRAM_BASE          0x80000000     /* Cached addr */
+#define        CONFIG_SYS_LOAD_ADDR            0x80060000     /* default load address  */
+
+#define CONFIG_SYS_MEMTEST_START       0x80000800
+#define CONFIG_SYS_MEMTEST_END         0x81E00000
+
+#endif /* _NBG460N_CONFIG_H */
diff --git a/package/boot/uboot-ar71xx/patches/001-ar71xx.patch b/package/boot/uboot-ar71xx/patches/001-ar71xx.patch
new file mode 100644 (file)
index 0000000..409f67a
--- /dev/null
@@ -0,0 +1,28 @@
+diff -ur u-boot-2010.03/cpu/mips/Makefile u-boot-nbg/cpu/mips/Makefile
+--- u-boot-2010.03/cpu/mips/Makefile   2010-03-31 23:54:39.000000000 +0200
++++ u-boot-nbg/cpu/mips/Makefile       2010-04-15 18:58:01.000000000 +0200
+@@ -33,6 +33,7 @@
+ COBJS-$(CONFIG_INCA_IP)       += asc_serial.o incaip_clock.o
+ COBJS-$(CONFIG_PURPLE)        += asc_serial.o
+ COBJS-$(CONFIG_SOC_AU1X00) += au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o
++COBJS-$(CONFIG_AR71XX)        += ar71xx_serial.o
+ SRCS  := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+ OBJS  := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+diff -ur u-boot-2010.03/Makefile u-boot-nbg/Makefile
+--- u-boot-2010.03/Makefile    2010-03-31 23:54:39.000000000 +0200
++++ u-boot-nbg/Makefile        2010-04-11 23:31:29.000000000 +0200
+@@ -3455,6 +3455,13 @@
+       @$(MKCONFIG) -a qemu-mips mips mips qemu-mips
+ #########################################################################
++## MIPS32 AR71XX (24K)
++#########################################################################
++
++nbg460n_550n_550nh_config :   unconfig
++      @$(MKCONFIG) -a nbg460n mips mips nbg460n zyxel
++
++#########################################################################
+ ## MIPS64 5Kc
+ #########################################################################
diff --git a/package/boot/uboot-ar71xx/patches/002-ar71xx-spi.patch b/package/boot/uboot-ar71xx/patches/002-ar71xx-spi.patch
new file mode 100644 (file)
index 0000000..2bb1ba2
--- /dev/null
@@ -0,0 +1,11 @@
+diff -ur u-boot-2010.03/drivers/spi/Makefile u-boot-nbg/drivers/spi/Makefile
+--- u-boot-2010.03/drivers/spi/Makefile        2010-03-31 23:54:39.000000000 +0200
++++ u-boot-nbg/drivers/spi/Makefile    2010-04-15 19:31:27.000000000 +0200
+@@ -25,6 +25,7 @@
+ LIB   := $(obj)libspi.a
++COBJS-$(CONFIG_AR71XX_SPI) += ar71xx_spi.o
+ COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
+ COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o
+ COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o
diff --git a/package/boot/uboot-ar71xx/patches/010-enet-ag71xx.patch b/package/boot/uboot-ar71xx/patches/010-enet-ag71xx.patch
new file mode 100644 (file)
index 0000000..ee90e32
--- /dev/null
@@ -0,0 +1,22 @@
+diff -ur u-boot-2010.03/drivers/net/Makefile u-boot-nbg/drivers/net/Makefile
+--- u-boot-2010.03/drivers/net/Makefile        2010-03-31 23:54:39.000000000 +0200
++++ u-boot-nbg/drivers/net/Makefile    2010-04-19 23:30:01.000000000 +0200
+@@ -27,6 +27,7 @@
+ COBJS-$(CONFIG_DRIVER_3C589) += 3c589.o
+ COBJS-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o
++COBJS-$(CONFIG_AG71XX) += ag71xx.o
+ COBJS-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o
+ COBJS-$(CONFIG_DRIVER_AX88180) += ax88180.o
+ COBJS-$(CONFIG_BCM570x) += bcm570x.o bcm570x_autoneg.o 5701rls.o
+diff -ur u-boot-2010.03/include/netdev.h u-boot-nbg/include/netdev.h
+--- u-boot-2010.03/include/netdev.h    2010-03-31 23:54:39.000000000 +0200
++++ u-boot-nbg/include/netdev.h        2010-05-02 11:30:58.000000000 +0200
+@@ -42,6 +42,7 @@
+ /* Driver initialization prototypes */
+ int au1x00_enet_initialize(bd_t*);
++int ag71xx_register(bd_t * bis, char *phyname[], u16 phyid[], u16 phyfixed[]);
+ int at91emac_register(bd_t *bis, unsigned long iobase);
+ int bfin_EMAC_initialize(bd_t *bis);
+ int cs8900_initialize(u8 dev_num, int base_addr);
diff --git a/package/boot/uboot-ar71xx/patches/011-switch-rtl8366sr.patch b/package/boot/uboot-ar71xx/patches/011-switch-rtl8366sr.patch
new file mode 100644 (file)
index 0000000..5d2ba41
--- /dev/null
@@ -0,0 +1,28 @@
+diff -ur u-boot-2010.03/drivers/net/Makefile u-boot-nbg/drivers/net/Makefile
+--- u-boot-2010.03/drivers/net/Makefile        2010-03-31 23:54:39.000000000 +0200
++++ u-boot-nbg/drivers/net/Makefile    2010-04-19 23:30:01.000000000 +0200
+@@ -65,6 +65,7 @@
+ COBJS-$(CONFIG_DRIVER_RTL8019) += rtl8019.o
+ COBJS-$(CONFIG_RTL8139) += rtl8139.o
+ COBJS-$(CONFIG_RTL8169) += rtl8169.o
++COBJS-$(CONFIG_RTL8366_MII) += phy/rtl8366_mii.o
+ COBJS-$(CONFIG_DRIVER_S3C4510_ETH) += s3c4510b_eth.o
+ COBJS-$(CONFIG_SH_ETHER) += sh_eth.o
+ COBJS-$(CONFIG_SMC91111) += smc91111.o
+diff -ur u-boot-2010.03/include/netdev.h u-boot-nbg/include/netdev.h
+--- u-boot-2010.03/include/netdev.h    2010-03-31 23:54:39.000000000 +0200
++++ u-boot-nbg/include/netdev.h        2010-05-02 11:30:58.000000000 +0200
+@@ -175,5 +175,13 @@
+ int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig);
+ #endif /* CONFIG_MV88E61XX_SWITCH */
++
++#if defined(CONFIG_RTL8366_MII)
++#define RTL8366_DEVNAME         "rtl8366"
++#define RTL8366_WANPHY_ID       4
++#define RTL8366_LANPHY_ID       -1
++int rtl8366_mii_register(bd_t *bis);
++int rtl8366s_initialize(void);
++#endif
+ #endif /* _NETDEV_H_ */
diff --git a/package/boot/uboot-ar71xx/patches/020-freebsd-compat.patch b/package/boot/uboot-ar71xx/patches/020-freebsd-compat.patch
new file mode 100644 (file)
index 0000000..fee0669
--- /dev/null
@@ -0,0 +1,11 @@
+--- a/include/compiler.h
++++ b/include/compiler.h
+@@ -46,7 +46,7 @@ extern int errno;
+ #ifdef __linux__
+ # include <endian.h>
+ # include <byteswap.h>
+-#elif defined(__MACH__)
++#elif defined(__MACH__) || defined(__FreeBSD__)
+ # include <machine/endian.h>
+ typedef unsigned long ulong;
+ typedef unsigned int  uint;
diff --git a/package/boot/uboot-ar71xx/patches/021-darwin_compat.patch b/package/boot/uboot-ar71xx/patches/021-darwin_compat.patch
new file mode 100644 (file)
index 0000000..dde83d4
--- /dev/null
@@ -0,0 +1,23 @@
+--- a/config.mk
++++ b/config.mk
+@@ -64,9 +64,17 @@ HOSTSTRIP   = strip
+ #
+ ifeq ($(HOSTOS),darwin)
+-HOSTCC                = cc
+-HOSTCFLAGS    += -traditional-cpp
+-HOSTLDFLAGS   += -multiply_defined suppress
++#get the major and minor product version (e.g. '10' and '6' for Snow Leopard)
++DARWIN_MAJOR_VERSION   = $(shell sw_vers -productVersion | cut -f 1 -d '.')
++DARWIN_MINOR_VERSION   = $(shell sw_vers -productVersion | cut -f 2 -d '.')
++
++before-snow-leopard    = $(shell if [ $(DARWIN_MAJOR_VERSION) -le 10 -a \
++   $(DARWIN_MINOR_VERSION) -le 5 ] ; then echo "$(1)"; else echo "$(2)"; fi ;)
++
++# Snow Leopards build environment has no longer restrictions as described above
++HOSTCC  = $(call before-snow-leopard, "cc", "gcc")
++HOSTCFLAGS += $(call before-snow-leopard, "-traditional-cpp")
++HOSTLDFLAGS    += $(call before-snow-leopard, "-multiply_defined suppress")
+ else
+ HOSTCC                = gcc
+ endif
diff --git a/package/boot/uboot-ar71xx/patches/022-getline_backport.patch b/package/boot/uboot-ar71xx/patches/022-getline_backport.patch
new file mode 100644 (file)
index 0000000..2ce2b61
--- /dev/null
@@ -0,0 +1,21 @@
+--- a/tools/os_support.c
++++ b/tools/os_support.c
+@@ -23,6 +23,6 @@
+ #ifdef __MINGW32__
+ #include "mingw_support.c"
+ #endif
+-#ifdef __APPLE__
++#if defined(__APPLE__) && __DARWIN_C_LEVEL < 200809L
+ #include "getline.c"
+ #endif
+--- a/tools/os_support.h
++++ b/tools/os_support.h
+@@ -28,7 +28,7 @@
+ #include "mingw_support.h"
+ #endif
+-#ifdef __APPLE__
++#if defined(__APPLE__) && __DARWIN_C_LEVEL < 200809L
+ #include "getline.h"
+ #endif
diff --git a/package/boot/uboot-envtools/Makefile b/package/boot/uboot-envtools/Makefile
new file mode 100644 (file)
index 0000000..74da5ea
--- /dev/null
@@ -0,0 +1,70 @@
+#
+# Copyright (C) 2006-2012 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+include $(TOPDIR)/rules.mk
+
+PKG_NAME:=uboot-envtools
+PKG_DISTNAME:=u-boot
+PKG_VERSION:=2012.04.01
+PKG_RELEASE:=1
+
+PKG_SOURCE:=$(PKG_DISTNAME)-$(PKG_VERSION).tar.bz2
+PKG_SOURCE_URL:=ftp://ftp.denx.de/pub/u-boot
+PKG_MD5SUM:=192bb231082d9159fb6e16de3039b6b2
+PKG_BUILD_DEPENDS:=zlib
+
+include $(INCLUDE_DIR)/package.mk
+
+TAR_OPTIONS+= --strip-components=3 -C $(PKG_BUILD_DIR) $(PKG_DISTNAME)-$(PKG_VERSION)/tools/env
+
+define Package/uboot-envtools
+  SECTION:=utils
+  CATEGORY:=Utilities
+  TITLE:=read/modify U-Boot bootloader environment
+  URL:=http://www.denx.de/wiki/U-Boot
+endef
+
+define Package/uboot-envtools/description
+ This package includes tools to read and modify U-Boot bootloader environment.
+endef
+
+define Build/Prepare
+       mkdir -p $(PKG_BUILD_DIR)
+       tar xvjf $(DL_DIR)/$(PKG_SOURCE) --strip-components=2 -C $(PKG_BUILD_DIR) $(PKG_DISTNAME)-$(PKG_VERSION)/lib/crc32.c
+       $(call Build/Prepare/Default)
+endef
+
+define Package/uboot-envtools/conffiles
+/etc/config/ubootenv
+/etc/fw_env.config
+endef
+
+define Package/uboot-envtools/install
+       $(INSTALL_DIR) $(1)/usr/sbin
+       $(INSTALL_BIN) $(PKG_BUILD_DIR)/fw_printenv $(1)/usr/sbin
+       ln -s fw_printenv $(1)/usr/sbin/fw_setenv
+       $(INSTALL_DIR) $(1)/lib
+       $(INSTALL_DATA) ./files/uboot-envtools.sh $(1)/lib
+ifneq ($(CONFIG_TARGET_ar71xx),)
+       $(INSTALL_DIR) $(1)/etc/uci-defaults
+       $(INSTALL_BIN) ./files/ar71xx $(1)/etc/uci-defaults/uboot-envtools
+endif
+ifneq ($(CONFIG_TARGET_kirkwood),)
+       $(INSTALL_DIR) $(1)/etc/uci-defaults
+       $(INSTALL_BIN) ./files/kirkwood $(1)/etc/uci-defaults/uboot-envtools
+endif
+ifneq ($(CONFIG_TARGET_lantiq),)
+       $(INSTALL_DIR) $(1)/etc/uci-defaults
+       $(INSTALL_BIN) ./files/lantiq $(1)/etc/uci-defaults/uboot-envtools
+endif
+ifneq ($(CONFIG_TARGET_ramips),)
+       $(INSTALL_DIR) $(1)/etc/uci-defaults
+       $(INSTALL_BIN) ./files/ramips $(1)/etc/uci-defaults/uboot-envtools
+endif
+endef
+
+$(eval $(call BuildPackage,uboot-envtools))
diff --git a/package/boot/uboot-envtools/files/ar71xx b/package/boot/uboot-envtools/files/ar71xx
new file mode 100644 (file)
index 0000000..ad0d921
--- /dev/null
@@ -0,0 +1,31 @@
+#!/bin/sh
+#
+# Copyright (C) 2011-2012 OpenWrt.org
+#
+
+[ -e /etc/config/ubootenv ] && exit 0
+
+touch /etc/config/ubootenv
+
+. /lib/ar71xx.sh
+. /lib/uboot-envtools.sh
+. /lib/functions.sh
+
+board=$(ar71xx_board_name)
+
+case "$board" in
+all0258n)
+       ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x10000" "0x10000"
+       ;;
+alfa-ap96 | \
+all0315n | \
+om2p | \
+om2p-lc)
+       ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x40000" "0x40000"
+       ;;
+esac
+
+config_load ubootenv
+config_foreach ubootenv_add_app_config ubootenv
+
+exit 0
diff --git a/package/boot/uboot-envtools/files/kirkwood b/package/boot/uboot-envtools/files/kirkwood
new file mode 100644 (file)
index 0000000..cad53aa
--- /dev/null
@@ -0,0 +1,25 @@
+#!/bin/sh
+#
+# Copyright (C) 2012 OpenWrt.org
+#
+
+[ -e /etc/config/ubootenv ] && exit 0
+
+touch /etc/config/ubootenv
+
+. /lib/kirkwood.sh
+. /lib/uboot-envtools.sh
+. /lib/functions.sh
+
+hardware=$(kirkwood_hardware_name)
+
+case "$hardware" in
+"RaidSonic ICY BOX IB-NAS6210")
+       ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x20000" "0x20000"
+       ;;
+esac
+
+config_load ubootenv
+config_foreach ubootenv_add_app_config ubootenv
+
+exit 0
diff --git a/package/boot/uboot-envtools/files/lantiq b/package/boot/uboot-envtools/files/lantiq
new file mode 100644 (file)
index 0000000..40befc3
--- /dev/null
@@ -0,0 +1,25 @@
+#!/bin/sh
+#
+# Copyright (C) 2012 OpenWrt.org
+#
+
+[ -e /etc/config/ubootenv ] && exit 0
+
+touch /etc/config/ubootenv
+
+. /lib/lantiq.sh
+. /lib/uboot-envtools.sh
+. /lib/functions.sh
+
+board=$(lantiq_board_name)
+
+case "$board" in
+GIGASX76X)
+       ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x10000" "0x10000" "1"
+       ;;
+esac
+
+config_load ubootenv
+config_foreach ubootenv_add_app_config ubootenv
+
+exit 0
diff --git a/package/boot/uboot-envtools/files/ramips b/package/boot/uboot-envtools/files/ramips
new file mode 100644 (file)
index 0000000..65cd49c
--- /dev/null
@@ -0,0 +1,27 @@
+#!/bin/sh
+#
+# Copyright (C) 2011-2012 OpenWrt.org
+#
+
+[ -e /etc/config/ubootenv ] && exit 0
+
+touch /etc/config/ubootenv
+
+. /lib/ramips.sh
+. /lib/uboot-envtools.sh
+. /lib/functions.sh
+
+board=$(ramips_board_name)
+
+case "$board" in
+all0239-3g | \
+all0256n | \
+all5002)
+       ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x10000" "0x10000"
+       ;;
+esac
+
+config_load ubootenv
+config_foreach ubootenv_add_app_config ubootenv
+
+exit 0
diff --git a/package/boot/uboot-envtools/files/uboot-envtools.sh b/package/boot/uboot-envtools/files/uboot-envtools.sh
new file mode 100644 (file)
index 0000000..e21b283
--- /dev/null
@@ -0,0 +1,36 @@
+#!/bin/sh
+#
+# Copyright (C) 2011-2012 OpenWrt.org
+#
+
+ubootenv_add_uci_config() {
+       local dev=$1
+       local offset=$2
+       local envsize=$3
+       local secsize=$4
+       local numsec=$5
+       uci batch <<EOF
+add ubootenv ubootenv
+set ubootenv.@ubootenv[-1].dev='$dev'
+set ubootenv.@ubootenv[-1].offset='$offset'
+set ubootenv.@ubootenv[-1].envsize='$envsize'
+set ubootenv.@ubootenv[-1].secsize='$secsize'
+set ubootenv.@ubootenv[-1].numsec='$numsec'
+EOF
+       uci commit ubootenv
+}
+
+ubootenv_add_app_config() {
+       local dev
+       local offset
+       local envsize
+       local secsize
+       local numsec
+       config_get dev "$1" dev
+       config_get offset "$1" offset
+       config_get envsize "$1" envsize
+       config_get secsize "$1" secsize
+       config_get numsec "$1" numsec
+       echo "$dev $offset $envsize $secsize $numsec" >>/etc/fw_env.config
+}
+
diff --git a/package/boot/uboot-envtools/patches/001-crc32_func_signature.patch b/package/boot/uboot-envtools/patches/001-crc32_func_signature.patch
new file mode 100644 (file)
index 0000000..f68f29e
--- /dev/null
@@ -0,0 +1,130 @@
+--- a/crc32.c
++++ b/crc32.c
+@@ -8,21 +8,16 @@
+  * For conditions of distribution and use, see copyright notice in zlib.h
+  */
+-#ifndef USE_HOSTCC
+-#include <common.h>
+-#endif
+-#include <compiler.h>
+-#include <u-boot/crc.h>
++#include <stdint.h>
++#include <asm/byteorder.h>
++
++#include "zlib.h"
+-#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+-#include <watchdog.h>
+-#endif
+-#include "u-boot/zlib.h"
+ #define local static
+ #define ZEXPORT       /* empty */
+-#define tole(x) cpu_to_le32(x)
++#define tole(x) __constant_cpu_to_le32(x)
+ #ifdef DYNAMIC_CRC_TABLE
+@@ -151,7 +146,7 @@ tole(0xb40bbe37L), tole(0xc30c8ea1L), to
+ #if 0
+ /* =========================================================================
+- * This function can be used by asm versions of crc32()
++ * This function can be used by asm versions of uboot_crc32()
+  */
+ const uint32_t * ZEXPORT get_crc_table()
+ {
+@@ -183,7 +178,7 @@ uint32_t ZEXPORT crc32_no_comp(uint32_t
+     if (crc_table_empty)
+       make_crc_table();
+ #endif
+-    crc = cpu_to_le32(crc);
++    crc = __cpu_to_le32(crc);
+     /* Align it */
+     if (((long)b) & 3 && len) {
+        uint8_t *p = (uint8_t *)b;
+@@ -212,11 +207,11 @@ uint32_t ZEXPORT crc32_no_comp(uint32_t
+        } while (--len);
+     }
+-    return le32_to_cpu(crc);
++    return __le32_to_cpu(crc);
+ }
+ #undef DO_CRC
+-uint32_t ZEXPORT crc32 (uint32_t crc, const Bytef *p, uInt len)
++uint32_t ZEXPORT uboot_crc32 (uint32_t crc, const Bytef *p, uInt len)
+ {
+      return crc32_no_comp(crc ^ 0xffffffffL, p, len) ^ 0xffffffffL;
+ }
+@@ -239,12 +234,12 @@ uint32_t ZEXPORT crc32_wd (uint32_t crc,
+               chunk = end - curr;
+               if (chunk > chunk_sz)
+                       chunk = chunk_sz;
+-              crc = crc32 (crc, curr, chunk);
++              crc = uboot_crc32 (crc, curr, chunk);
+               curr += chunk;
+               WATCHDOG_RESET ();
+       }
+ #else
+-      crc = crc32 (crc, buf, len);
++      crc = uboot_crc32 (crc, buf, len);
+ #endif
+       return crc;
+--- a/fw_env.c
++++ b/fw_env.c
+@@ -34,6 +34,7 @@
+ #include <sys/ioctl.h>
+ #include <sys/stat.h>
+ #include <unistd.h>
++#include <zlib.h>
+ #ifdef MTD_OLD
+ # include <stdint.h>
+@@ -212,13 +213,14 @@ static char default_environment[] = {
+ static int flash_io (int mode);
+ static char *envmatch (char * s1, char * s2);
+ static int parse_config (void);
++uint32_t uboot_crc32 (uint32_t crc, const Bytef *p, uInt len);
+ #if defined(CONFIG_FILE)
+ static int get_config (char *);
+ #endif
+-static inline ulong getenvsize (void)
++static inline uint32_t getenvsize (void)
+ {
+-      ulong rc = CONFIG_ENV_SIZE - sizeof (long);
++      uint32_t rc = CONFIG_ENV_SIZE - sizeof (uint32_t);
+       if (HaveRedundEnv)
+               rc -= sizeof (char);
+@@ -348,7 +350,7 @@ int fw_env_close(void)
+       /*
+        * Update CRC
+        */
+-      *environment.crc = crc32(0, (uint8_t *) environment.data, ENV_SIZE);
++      *environment.crc = uboot_crc32(0, (uint8_t *) environment.data, ENV_SIZE);
+       /* write environment back to flash */
+       if (flash_io(O_RDWR)) {
+@@ -1116,7 +1118,7 @@ int fw_env_open(void)
+       if (flash_io (O_RDONLY))
+               return -1;
+-      crc0 = crc32 (0, (uint8_t *) environment.data, ENV_SIZE);
++      crc0 = uboot_crc32 (0, (uint8_t *) environment.data, ENV_SIZE);
+       crc0_ok = (crc0 == *environment.crc);
+       if (!HaveRedundEnv) {
+               if (!crc0_ok) {
+@@ -1160,7 +1162,7 @@ int fw_env_open(void)
+                       return -1;
+               }
+-              crc1 = crc32 (0, (uint8_t *) redundant->data, ENV_SIZE);
++              crc1 = uboot_crc32 (0, (uint8_t *) redundant->data, ENV_SIZE);
+               crc1_ok = (crc1 == redundant->crc);
+               flag1 = redundant->flags;
diff --git a/package/boot/uboot-envtools/patches/002-makefile.patch b/package/boot/uboot-envtools/patches/002-makefile.patch
new file mode 100644 (file)
index 0000000..b18bff6
--- /dev/null
@@ -0,0 +1,44 @@
+--- a/Makefile
++++ b/Makefile
+@@ -21,34 +21,17 @@
+ # MA 02111-1307 USA
+ #
+-include $(TOPDIR)/config.mk
+-
+-HOSTSRCS := $(SRCTREE)/lib/crc32.c  fw_env.c  fw_env_main.c
++SRCS := crc32.c fw_env.c fw_env_main.c
+ HEADERS       := fw_env.h
+-# Compile for a hosted environment on the target
+-HOSTCPPFLAGS  = -idirafter $(SRCTREE)/include \
+-              -idirafter $(OBJTREE)/include2 \
+-              -idirafter $(OBJTREE)/include \
+-              -DUSE_HOSTCC
+-
+-ifeq ($(MTD_VERSION),old)
+-HOSTCPPFLAGS += -DMTD_OLD
+-endif
+-
+-all:  $(obj)fw_printenv
+-
+-# Some files complain if compiled with -pedantic, use HOSTCFLAGS_NOPED
+-$(obj)fw_printenv:    $(HOSTSRCS) $(HEADERS)
+-      $(HOSTCC) $(HOSTCFLAGS_NOPED) $(HOSTLDFLAGS) -o $@ $(HOSTSRCS)
++CPPFLAGS := -Wall $(CFLAGS)
+-clean:
+-      rm -f $(obj)fw_printenv
++all: fw_printenv
+-#########################################################################
++fw_printenv: $(SRCS) $(HEADERS)
++      $(CC) $(CPPFLAGS) $(SRCS) -o fw_printenv
+-include $(TOPDIR)/rules.mk
+-
+-sinclude $(obj).depend
++clean:
++      rm -f fw_printenv
+ #########################################################################
diff --git a/package/boot/uboot-envtools/patches/003-nor-eraselen.patch b/package/boot/uboot-envtools/patches/003-nor-eraselen.patch
new file mode 100644 (file)
index 0000000..c6eb59a
--- /dev/null
@@ -0,0 +1,14 @@
+--- a/fw_env.c
++++ b/fw_env.c
+@@ -790,7 +790,10 @@ static int flash_write_buf (int dev, int
+       erase_offset = (offset / blocklen) * blocklen;
+       /* Maximum area we may use */
+-      erase_len = top_of_range - erase_offset;
++      if (mtd_type == MTD_NANDFLASH)
++              erase_len = top_of_range - erase_offset;
++      else
++              erase_len = blocklen;
+       blockstart = erase_offset;
+       /* Offset inside a block */
diff --git a/package/boot/uboot-envtools/patches/004-allow_mac_change.patch b/package/boot/uboot-envtools/patches/004-allow_mac_change.patch
new file mode 100644 (file)
index 0000000..b7d600b
--- /dev/null
@@ -0,0 +1,21 @@
+--- a/fw_env.c
++++ b/fw_env.c
+@@ -46,8 +46,6 @@
+ #include "fw_env.h"
+-#include <config.h>
+-
+ #define WHITESPACE(c) ((c == '\t') || (c == ' '))
+ #define min(x, y) ({                          \
+@@ -401,9 +399,7 @@ int fw_env_write(char *name, char *value
+               if (
+                   (strcmp(name, "serial#") == 0) ||
+                   ((strcmp(name, "ethaddr") == 0)
+-#if defined(CONFIG_OVERWRITE_ETHADDR_ONCE) && defined(CONFIG_ETHADDR)
+                   && (strcmp(oldval, MK_STR(CONFIG_ETHADDR)) != 0)
+-#endif /* CONFIG_OVERWRITE_ETHADDR_ONCE && CONFIG_ETHADDR */
+                  ) ) {
+                       fprintf (stderr, "Can't overwrite \"%s\"\n", name);
+                       errno = EROFS;
diff --git a/package/boot/uboot-kirkwood/Makefile b/package/boot/uboot-kirkwood/Makefile
new file mode 100644 (file)
index 0000000..48bcf99
--- /dev/null
@@ -0,0 +1,110 @@
+#
+# Copyright (C) 2010-2012 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/kernel.mk
+
+PKG_NAME:=u-boot
+PKG_VERSION:=2012.04.01
+PKG_RELEASE:=1
+
+PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
+PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
+PKG_SOURCE_URL:=ftp://ftp.denx.de/pub/u-boot
+PKG_MD5SUM:=192bb231082d9159fb6e16de3039b6b2
+PKG_TARGETS:=bin
+
+include $(INCLUDE_DIR)/package.mk
+
+define uboot/Default
+  TITLE:=
+  CONFIG:=
+  IMAGE:=
+endef
+
+define uboot/sheevaplug
+  TITLE:=U-Boot for the SheevaPlug
+endef
+
+define uboot/dockstar
+  TITLE:=U-Boot for the Seagate DockStar
+endef
+
+define uboot/iconnect
+  TITLE:=U-Boot for the Iomega iConnect Wireless
+endef
+
+define uboot/ib62x0
+  TITLE:=U-Boot for the RaidSonic ICY BOX NAS6210 and NAS6220
+endef
+
+UBOOTS:=sheevaplug dockstar iconnect ib62x0
+
+define Package/uboot/template
+define Package/uboot-kirkwood-$(1)
+  SECTION:=boot
+  CATEGORY:=Boot Loaders
+  DEPENDS:=@TARGET_kirkwood
+  TITLE:=$(2)
+  URL:=http://www.denx.de/wiki/U-Boot
+  VARIANT:=$(1)
+endef
+endef
+
+define BuildUBootPackage
+       $(eval $(uboot/Default))
+       $(eval $(uboot/$(1)))
+       $(call Package/uboot/template,$(1),$(TITLE))
+endef
+
+ifdef BUILD_VARIANT
+$(eval $(call uboot/$(BUILD_VARIANT)))
+UBOOT_CONFIG:=$(if $(CONFIG),$(CONFIG),$(BUILD_VARIANT))
+UBOOT_IMAGE:=$(if $(IMAGE),$(IMAGE),openwrt-$(BOARD)-$(BUILD_VARIANT)-u-boot.bin)
+endif
+
+define Build/Prepare
+       $(call Build/Prepare/Default)
+       $(CP) ./files/* $(PKG_BUILD_DIR)
+endef
+
+define Build/Configure
+       $(MAKE) -C $(PKG_BUILD_DIR) \
+               $(UBOOT_CONFIG)_config
+endef
+
+define Build/Compile
+       $(MAKE) -C $(PKG_BUILD_DIR) \
+               u-boot.kwb \
+               CROSS_COMPILE=$(TARGET_CROSS)
+endef
+
+define Package/uboot/install/default
+       $(INSTALL_DIR) $(BIN_DIR)
+       $(CP) $(PKG_BUILD_DIR)/u-boot.bin \
+               $(BIN_DIR)/openwrt-$(BOARD)-$(1)-u-boot.bin
+       $(CP) $(PKG_BUILD_DIR)/u-boot.kwb \
+               $(BIN_DIR)/openwrt-$(BOARD)-$(1)-u-boot.kwb
+       $(INSTALL_DIR) $(BIN_DIR)/u-boot-kwboot/
+       $(CP) $(PKG_BUILD_DIR)/tools/kwboot \
+               $(BIN_DIR)/u-boot-kwboot/
+endef
+
+define Package/uboot/install/template
+define Package/uboot-kirkwood-$(1)/install
+       $(call Package/uboot/install/default,$(2))
+endef
+endef
+
+$(foreach u,$(UBOOTS), \
+       $(eval $(call Package/uboot/install/template,$(u),$(u))) \
+)
+
+$(foreach u,$(UBOOTS), \
+       $(eval $(call BuildUBootPackage,$(u))) \
+       $(eval $(call BuildPackage,uboot-kirkwood-$(u))) \
+)
diff --git a/package/boot/uboot-kirkwood/files/board/iomega/iconnect/Makefile b/package/boot/uboot-kirkwood/files/board/iomega/iconnect/Makefile
new file mode 100644 (file)
index 0000000..f77fcfb
--- /dev/null
@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).o
+
+COBJS  := iconnect.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):        $(obj).depend $(OBJS) $(SOBJS)
+       $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/package/boot/uboot-kirkwood/files/board/iomega/iconnect/iconnect.c b/package/boot/uboot-kirkwood/files/board/iomega/iconnect/iconnect.c
new file mode 100644 (file)
index 0000000..34ddadf
--- /dev/null
@@ -0,0 +1,141 @@
+/*
+ * Copyright (C) 2009-2012
+ * Wojciech Dubowik <wojciech.dubowik@neratec.com>
+ * Luka Perkov <uboot@lukaperkov.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+#include "iconnect.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+       /*
+        * default gpio configuration
+        * There are maximum 64 gpios controlled through 2 sets of registers
+        * the below configuration configures mainly initial LED status
+        */
+       kw_config_gpio(ICONNECT_OE_VAL_LOW,
+                       ICONNECT_OE_VAL_HIGH,
+                       ICONNECT_OE_LOW, ICONNECT_OE_HIGH);
+
+       /* Multi-Purpose Pins Functionality configuration */
+       u32 kwmpp_config[] = {
+               MPP0_NF_IO2,
+               MPP1_NF_IO3,
+               MPP2_NF_IO4,
+               MPP3_NF_IO5,
+               MPP4_NF_IO6,
+               MPP5_NF_IO7,
+               MPP6_SYSRST_OUTn,
+               MPP7_GPO,
+               MPP8_TW_SDA,
+               MPP9_TW_SCK,
+               MPP10_UART0_TXD,
+               MPP11_UART0_RXD,
+               MPP12_GPO,
+               MPP13_SD_CMD,
+               MPP14_SD_D0,
+               MPP15_SD_D1,
+               MPP16_SD_D2,
+               MPP17_SD_D3,
+               MPP18_NF_IO0,
+               MPP19_NF_IO1,
+               MPP20_GE1_0,
+               MPP21_GE1_1,
+               MPP22_GE1_2,
+               MPP23_GE1_3,
+               MPP24_GE1_4,
+               MPP25_GE1_5,
+               MPP26_GE1_6,
+               MPP27_GE1_7,
+               MPP28_GPIO,
+               MPP29_GPIO,
+               MPP30_GE1_10,
+               MPP31_GE1_11,
+               MPP32_GE1_12,
+               MPP33_GE1_13,
+               MPP34_GE1_14,
+               MPP35_GPIO,
+               MPP36_AUDIO_SPDIFI,
+               MPP37_AUDIO_SPDIFO,
+               MPP38_GPIO,
+               MPP39_TDM_SPI_CS0,
+               MPP40_TDM_SPI_SCK,
+               MPP41_GPIO,
+               MPP42_GPIO,
+               MPP43_GPIO,
+               MPP44_GPIO,
+               MPP45_GPIO,
+               MPP46_GPIO,
+               MPP47_GPIO,
+               MPP48_GPIO,
+               MPP49_GPIO,
+               0
+       };
+       kirkwood_mpp_conf(kwmpp_config);
+       return 0;
+}
+
+int board_init(void)
+{
+       /* Boot parameters address */
+       gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+       return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and initialize PHY */
+void reset_phy(void)
+{
+       u16 reg;
+       u16 devadr;
+       char *name = "egiga0";
+
+       if (miiphy_set_current_dev(name))
+               return;
+
+       /* command to read PHY dev address */
+       if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+               printf("Err..(%s) could not read PHY dev address\n", __func__);
+               return;
+       }
+
+       /*
+        * Enable RGMII delay on Tx and Rx for CPU port
+        * Ref: sec 4.7.2 of chip datasheet
+        */
+       miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+       miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
+       reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+       miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+       miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+       /* reset the phy */
+       miiphy_reset(name, devadr);
+
+       debug("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/package/boot/uboot-kirkwood/files/board/iomega/iconnect/iconnect.h b/package/boot/uboot-kirkwood/files/board/iomega/iconnect/iconnect.h
new file mode 100644 (file)
index 0000000..2fb3e5e
--- /dev/null
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2009-2012
+ * Wojciech Dubowik <wojciech.dubowik@neratec.com>
+ * Luka Perkov <uboot@lukaperkov.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ICONNECT_H
+#define __ICONNECT_H
+
+#define ICONNECT_OE_LOW                        (~(1 << 7))
+#define ICONNECT_OE_HIGH               (~(1 << 10))
+#define ICONNECT_OE_VAL_LOW            (0)
+#define ICONNECT_OE_VAL_HIGH           (1 << 10)
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG                10
+#define MV88E1116_CPRSP_CR3_REG                21
+#define MV88E1116_MAC_CTRL_REG         21
+#define MV88E1116_PGADR_REG            22
+#define MV88E1116_RGMII_TXTM_CTRL      (1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL      (1 << 5)
+
+#endif /* __ICONNECT_H */
diff --git a/package/boot/uboot-kirkwood/files/board/iomega/iconnect/kwbimage.cfg b/package/boot/uboot-kirkwood/files/board/iomega/iconnect/kwbimage.cfg
new file mode 100644 (file)
index 0000000..dee546a
--- /dev/null
@@ -0,0 +1,165 @@
+#
+# (C) Copyright 2009-2012
+# Wojciech Dubowik <wojciech.dubowik@neratec.com>
+# Luka Perkov <uboot@lukaperkov.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM      nand
+NAND_ECC_MODE  default
+NAND_PAGE_SIZE 0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xffd100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xffd01400 0x43000c30     # DDR Configuration register
+# bit13-0:  0xc30, (3120 DDR2 clks refresh rate)
+# bit23-14: 0x0,
+# bit24:    0x1,   enable exit self refresh mode on DDR access
+# bit25:    0x1,   required
+# bit29-26: 0x0,
+# bit31-30: 0x1,
+
+DATA 0xffd01404 0x37543000     # DDR Controller Control Low
+# bit4:     0x0, addr/cmd in smame cycle
+# bit5:     0x0, clk is driven during self refresh, we don't care for APX
+# bit6:     0x0, use recommended falling edge of clk for addr/cmd
+# bit14:    0x0, input buffer always powered up
+# bit18:    0x1, cpu lock transaction enabled
+# bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 0x3, required
+# bit31:    0x0, no additional STARTBURST delay
+
+DATA 0xffd01408 0x22125451     # DDR Timing (Low) (active cycles value +1)
+# bit3-0:   TRAS lsbs
+# bit7-4:   TRCD
+# bit11-8:  TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xffd0140c 0x00000a33     # DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: 0x0, required
+
+DATA 0xffd01410 0x000000cc     # DDR Address Control
+# bit1-0:   00,  Cs0width (x8)
+# bit3-2:   11,  Cs0size (1Gb)
+# bit5-4:   00,  Cs1width (x8)
+# bit7-6:   11,  Cs1size (1Gb)
+# bit9-8:   00,  Cs2width (nonexistent)
+# bit11-10: 00,  Cs2size (nonexistent)
+# bit13-12: 00,  Cs3width (nonexistent)
+# bit15-14: 00,  Cs3size (nonexistent)
+# bit16:    0,   Cs0AddrSel
+# bit17:    0,   Cs1AddrSel
+# bit18:    0,   Cs2AddrSel
+# bit19:    0,   Cs3AddrSel
+# bit31-20: 0x0, required
+
+DATA 0xffd01414 0x00000000     # DDR Open Pages Control
+# bit0:    0,   OpenPage enabled
+# bit31-1: 0x0, required
+
+DATA 0xffd01418 0x00000000     # DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0x0, required
+
+DATA 0xffd0141c 0x00000c52     # DDR Mode
+# bit2-0:   0x2, BurstLen=2 required
+# bit3:     0x0, BurstType=0 required
+# bit6-4:   0x4, CL=5
+# bit7:     0x0, TestMode=0 normal
+# bit8:     0x0, DLL reset=0 normal
+# bit11-9:  0x6, auto-precharge write recovery ????????????
+# bit12:    0x0, PD must be zero
+# bit31-13: 0x0, required
+
+DATA 0xffd01420 0x00000040     # DDR Extended Mode
+# bit0:     0,   DDR DLL enabled
+# bit1:     0,   DDR drive strenght normal
+# bit2:     0,   DDR ODT control lsd (disabled)
+# bit5-3:   0x0, required
+# bit6:     1,   DDR ODT control msb, (disabled)
+# bit9-7:   0x0, required
+# bit10:    0,   differential DQS enabled
+# bit11:    0,   required
+# bit12:    0,   DDR output buffer enabled
+# bit31-13: 0x0, required
+
+DATA 0xffd01424 0x0000f17f     # DDR Controller Control High
+# bit2-0:   0x7, required
+# bit3:     0x1, MBUS Burst Chop disabled
+# bit6-4:   0x7, required
+# bit7:     0x0,
+# bit8:     0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9:     0x0, no half clock cycle addition to dataout
+# bit10:    0x0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11:    0x0, 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 0xf, required
+# bit31-16: 0x0, required
+
+DATA 0xffd01428 0x00085520     # DDR2 ODT Read Timing (default values)
+DATA 0xffd0147c 0x00008552     # DDR2 ODT Write Timing (default values)
+
+DATA 0xffd01500 0x00000000     # CS[0]n Base address to 0x0
+DATA 0xffd01504 0x0ffffff1     # CS[0]n Size
+# bit0:     0x1,     Window enabled
+# bit1:     0x0,     Write Protect disabled
+# bit3-2:   0x0,     CS0 hit selected
+# bit23-4:  0xfffff, required
+# bit31-24: 0x0f,    Size (i.e. 256MB)
+
+DATA 0xffd01508 0x00000000     # CS[1]n Base address to 256Mb
+DATA 0xffd0150c 0x00000000     # CS[1]n Size 256Mb Window enabled for CS1
+
+DATA 0xffd01514 0x00000000     # CS[2]n Size, window disabled
+DATA 0xffd0151c 0x00000000     # CS[3]n Size, window disabled
+
+DATA 0xffd01494 0x00030000     # DDR ODT Control (Low)
+# bit3-0:     ODT0Rd, MODT[0] asserted during read from DRAM CS1
+# bit7-4:     ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
+# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xffd01498 0x00000000     # DDR ODT Control (High)
+# bit1-0:  0x0, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  0x1, ODT1 active NEVER!
+# bit31-4: 0x0, required
+
+DATA 0xffd0149c 0x0000e803     # CPU ODT Control
+DATA 0xffd01480 0x00000001     # DDR Initialization Control
+# bit0: 0x1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/package/boot/uboot-kirkwood/files/include/configs/iconnect.h b/package/boot/uboot-kirkwood/files/include/configs/iconnect.h
new file mode 100644 (file)
index 0000000..59432f1
--- /dev/null
@@ -0,0 +1,124 @@
+/*
+ * (C) Copyright 2009-2012
+ * Wojciech Dubowik <wojciech.dubowik@neratec.com>
+ * Luka Perkov <uboot@lukaperkov.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _CONFIG_ICONNECT_H
+#define _CONFIG_ICONNECT_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING    " Iomega iConnect Wireless"
+
+/*
+ * High level configuration options
+ */
+#define CONFIG_FEROCEON_88FR131                /* CPU Core subversion */
+#define CONFIG_KIRKWOOD                        /* SOC Family Name */
+#define CONFIG_KW88F6281               /* SOC Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT      /* disable board lowlevel_init */
+#define CONFIG_KIRKWOOD_EGIGA_INIT     /* Enable GbePort0/1 for kernel */
+
+/*
+ * Machine type
+ */
+#define CONFIG_MACH_TYPE       MACH_TYPE_ICONNECT
+
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH            /* declare no flash (NOR/SPI) */
+#define CONFIG_SYS_MVFS
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+#undef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT      "iconnect => "
+
+/*
+ * Environment variables configuration
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SECT_SIZE   0x20000
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+#define CONFIG_ENV_SIZE                        0x20000
+#define CONFIG_ENV_OFFSET              0xc0000
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND     "${x_bootcmd_kernel}; "         \
+       "setenv bootargs ${x_bootargs} ${x_bootargs_root}; "    \
+       "${x_bootcmd_usb}; bootm 0x6400000;"
+
+#define CONFIG_MTDPARTS                "orion_nand:1M(u-boot),"        \
+       "3M@1M(kernel),32M@4M(rootfs),475M@36M(data)\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS      "x_bootargs=console"    \
+       "=ttyS0,115200 mtdparts="CONFIG_MTDPARTS                \
+       "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \
+       "x_bootcmd_usb=usb start\0" \
+       "x_bootargs_root=root=/dev/mtdblock2 rw rootfstype=jffs2\0"
+
+/*
+ * Ethernet driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS     {1, 0}  /* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR    11
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * SATA driver configuration
+ */
+#ifdef CONFIG_CMD_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET     MV_SATA_PORT0_OFFSET
+#define CONFIG_SYS_ATA_IDE1_OFFSET     MV_SATA_PORT1_OFFSET
+#endif /* CONFIG_CMD_IDE */
+
+/*
+ * File system
+ */
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+
+#endif /* _CONFIG_ICONNECT_H */
diff --git a/package/boot/uboot-kirkwood/patches/0001-ib62x0.patch b/package/boot/uboot-kirkwood/patches/0001-ib62x0.patch
new file mode 100644 (file)
index 0000000..0a7dc47
--- /dev/null
@@ -0,0 +1,542 @@
+http://lists.denx.de/pipermail/u-boot/2012-April/122597.html
+http://patchwork.ozlabs.org/patch/153293/
+---
+
+diff --git a/MAINTAINERS b/MAINTAINERS
+index 708ded7..9d2aba7 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -777,6 +777,10 @@ Linus Walleij <linus.walleij@linaro.org>
+       integratorap    various
+       integratorcp    various
++Luka Perkov <uboot@lukaperkov.net>
++
++      ib62x0          ARM926EJS
++
+ Dave Peverley <dpeverley@mpc-data.co.uk>
+       omap730p2       ARM926EJS
+diff --git a/board/raidsonic/ib62x0/Makefile b/board/raidsonic/ib62x0/Makefile
+new file mode 100644
+index 0000000..d450f8d
+--- /dev/null
++++ b/board/raidsonic/ib62x0/Makefile
+@@ -0,0 +1,43 @@
++#
++# (C) Copyright 2009
++# Marvell Semiconductor <www.marvell.com>
++# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program. If not, see <http://www.gnu.org/licenses/>.
++#
++
++include $(TOPDIR)/config.mk
++
++LIB   = $(obj)lib$(BOARD).o
++
++COBJS := ib62x0.o
++
++SRCS  := $(SOBJS:.o=.S) $(COBJS:.o=.c)
++OBJS  := $(addprefix $(obj),$(COBJS))
++SOBJS := $(addprefix $(obj),$(SOBJS))
++
++$(LIB):       $(obj).depend $(OBJS) $(SOBJS)
++      $(call cmd_link_o_target, $(OBJS) $(SOBJS))
++
++#########################################################################
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+diff --git a/board/raidsonic/ib62x0/ib62x0.c b/board/raidsonic/ib62x0/ib62x0.c
+new file mode 100644
+index 0000000..65f2c2e
+--- /dev/null
++++ b/board/raidsonic/ib62x0/ib62x0.c
+@@ -0,0 +1,79 @@
++/*
++ * Copyright (C) 2011-2012
++ * Gerald Kerma <dreagle@doukki.net>
++ * Luka Perkov <uboot@lukaperkov.net>
++ * Simon Baatz <gmbnomis@gmail.com>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <common.h>
++#include <miiphy.h>
++#include <asm/arch/cpu.h>
++#include <asm/arch/kirkwood.h>
++#include <asm/arch/mpp.h>
++#include "ib62x0.h"
++
++DECLARE_GLOBAL_DATA_PTR;
++
++int board_early_init_f(void)
++{
++      /*
++       * default gpio configuration
++       * There are maximum 64 gpios controlled through 2 sets of registers
++       * the below configuration configures mainly initial LED status
++       */
++      kw_config_gpio(IB62x0_OE_VAL_LOW,
++                      IB62x0_OE_VAL_HIGH,
++                      IB62x0_OE_LOW, IB62x0_OE_HIGH);
++
++      /* Multi-Purpose Pins Functionality configuration */
++      u32 kwmpp_config[] = {
++              MPP0_NF_IO2,
++              MPP1_NF_IO3,
++              MPP2_NF_IO4,
++              MPP3_NF_IO5,
++              MPP4_NF_IO6,
++              MPP5_NF_IO7,
++              MPP6_SYSRST_OUTn,
++              MPP8_TW_SDA,
++              MPP9_TW_SCK,
++              MPP10_UART0_TXD,
++              MPP11_UART0_RXD,
++              MPP18_NF_IO0,
++              MPP19_NF_IO1,
++              MPP20_SATA1_ACTn,
++              MPP21_SATA0_ACTn,
++              MPP22_GPIO,     /* Power LED red */
++              MPP24_GPIO,     /* Power off device */
++              MPP25_GPIO,     /* Power LED green */
++              MPP27_GPIO,     /* USB transfer LED */
++              MPP28_GPIO,     /* Reset button */
++              MPP29_GPIO,     /* USB Copy button */
++              0
++      };
++      kirkwood_mpp_conf(kwmpp_config);
++      return 0;
++}
++
++int board_init(void)
++{
++      /* adress of boot parameters */
++      gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
++
++      return 0;
++}
+diff --git a/board/raidsonic/ib62x0/ib62x0.h b/board/raidsonic/ib62x0/ib62x0.h
+new file mode 100644
+index 0000000..0c30690
+--- /dev/null
++++ b/board/raidsonic/ib62x0/ib62x0.h
+@@ -0,0 +1,40 @@
++/*
++ * Copyright (C) 2011-2012
++ * Gerald Kerma <dreagle@doukki.net>
++ * Simon Baatz <gmbnomis@gmail.com>
++ * Luka Perkov <uboot@lukaperkov.net>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef __IB62x0_H
++#define __IB62x0_H
++
++#define IB62x0_OE_LOW         (~(1 << 22 | 1 << 24 | 1 << 25 | 1 << 27))
++#define IB62x0_OE_HIGH                (~(0))
++#define IB62x0_OE_VAL_LOW     0
++#define IB62x0_OE_VAL_HIGH    0
++
++/* PHY related */
++#define MV88E1116_LED_FCTRL_REG               10
++#define MV88E1116_CPRSP_CR3_REG               21
++#define MV88E1116_MAC_CTRL_REG                21
++#define MV88E1116_PGADR_REG           22
++#define MV88E1116_RGMII_TXTM_CTRL     (1 << 4)
++#define MV88E1116_RGMII_RXTM_CTRL     (1 << 5)
++
++#endif /* __IB62x0_H */
+diff --git a/board/raidsonic/ib62x0/kwbimage.cfg b/board/raidsonic/ib62x0/kwbimage.cfg
+new file mode 100644
+index 0000000..bd594eb
+--- /dev/null
++++ b/board/raidsonic/ib62x0/kwbimage.cfg
+@@ -0,0 +1,169 @@
++#
++# Copyright (C) 2011-2012
++# Gerald Kerma <dreagle@doukki.net>
++# Simon Baatz <gmbnomis@gmail.com>
++# Luka Perkov <uboot@lukaperkov.net>
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program. If not, see <http://www.gnu.org/licenses/>.
++#
++# Refer docs/README.kwimage for more details about how-to configure
++# and create kirkwood boot image
++#
++
++# Boot Media configurations
++BOOT_FROM     nand    # change from nand to uart if building UART image
++NAND_ECC_MODE default
++NAND_PAGE_SIZE        0x0800
++
++# SOC registers configuration using bootrom header extension
++# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
++
++# Configure RGMII-0 interface pad voltage to 1.8V
++DATA 0xffd100e0 0x1b1b1b9b
++
++#Dram initalization for SINGLE x16 CL=5 @ 400MHz
++DATA 0xffd01400 0x43000c30    # DDR Configuration register
++# bit13-0:  0xc30, (3120 DDR2 clks refresh rate)
++# bit23-14: 0x0,
++# bit24:    0x1,     enable exit self refresh mode on DDR access
++# bit25:    0x1,     required
++# bit29-26: 0x0,
++# bit31-30: 0x1,
++
++DATA 0xffd01404 0x37543000    # DDR Controller Control Low
++# bit4:     0x0, addr/cmd in smame cycle
++# bit5:     0x0, clk is driven during self refresh, we don't care for APX
++# bit6:     0x0, use recommended falling edge of clk for addr/cmd
++# bit14:    0x0, input buffer always powered up
++# bit18:    0x1, cpu lock transaction enabled
++# bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
++# bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
++# bit30-28: 0x3, required
++# bit31:    0x0, no additional STARTBURST delay
++
++DATA 0xffd01408 0x22125451    # DDR Timing (Low) (active cycles value +1)
++# bit3-0:   TRAS lsbs
++# bit7-4:   TRCD
++# bit11-8:  TRP
++# bit15-12: TWR
++# bit19-16: TWTR
++# bit20:    TRAS msb
++# bit23-21: 0x0
++# bit27-24: TRRD
++# bit31-28: TRTP
++
++DATA 0xffd0140c 0x00000a33    # DDR Timing (High)
++# bit6-0:   TRFC
++# bit8-7:   TR2R
++# bit10-9:  TR2W
++# bit12-11: TW2W
++# bit31-13: 0x0, required
++
++DATA 0xffd01410 0x0000000c    # DDR Address Control
++# bit1-0:   00,  Cs0width (x8)
++# bit3-2:   11,  Cs0size (1Gb)
++# bit5-4:   00,  Cs1width (x8)
++# bit7-6:   11,  Cs1size (1Gb)
++# bit9-8:   00,  Cs2width (nonexistent
++# bit11-10: 00,  Cs2size  (nonexistent
++# bit13-12: 00,  Cs3width (nonexistent
++# bit15-14: 00,  Cs3size  (nonexistent
++# bit16:    0,   Cs0AddrSel
++# bit17:    0,   Cs1AddrSel
++# bit18:    0,   Cs2AddrSel
++# bit19:    0,   Cs3AddrSel
++# bit31-20: 0x0, required
++
++DATA 0xffd01414 0x00000000    # DDR Open Pages Control
++# bit0:    0,   OpenPage enabled
++# bit31-1: 0x0, required
++
++DATA 0xffd01418 0x00000000    # DDR Operation
++# bit3-0:   0x0, DDR cmd
++# bit31-4:  0x0, required
++
++DATA 0xffd0141c 0x00000c52    # DDR Mode
++# bit2-0:   0x2, BurstLen=2 required
++# bit3:     0x0, BurstType=0 required
++# bit6-4:   0x4, CL=5
++# bit7:     0x0, TestMode=0 normal
++# bit8:     0x0, DLL reset=0 normal
++# bit11-9:  0x6, auto-precharge write recovery ????????????
++# bit12:    0x0, PD must be zero
++# bit31-13: 0x0, required
++
++DATA 0xffd01420 0x00000040    # DDR Extended Mode
++# bit0:     0,   DDR DLL enabled
++# bit1:     0,   DDR drive strenght normal
++# bit2:     1,   DDR ODT control lsd (disabled)
++# bit5-3:   0x0, required
++# bit6:     0,   DDR ODT control msb, (disabled)
++# bit9-7:   0x0, required
++# bit10:    0,   differential DQS enabled
++# bit11:    0,   required
++# bit12:    0,   DDR output buffer enabled
++# bit31-13: 0x0, required
++
++DATA 0xffd01424 0x0000f17f    # DDR Controller Control High
++# bit2-0:   0x7, required
++# bit3:     0x1, MBUS Burst Chop disabled
++# bit6-4:   0x7, required
++# bit7:     0x0,
++# bit8:     0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
++# bit9:     0x0, no half clock cycle addition to dataout
++# bit10:    0x0, 1/4 clock cycle skew enabled for addr/ctl signals
++# bit11:    0x0, 1/4 clock cycle skew disabled for write mesh
++# bit15-12: 0xf, required
++# bit31-16: 0,   required
++
++DATA 0xffd01428 0x00085520    # DDR2 ODT Read Timing (default values)
++DATA 0xffd0147c 0x00008552    # DDR2 ODT Write Timing (default values)
++
++DATA 0xffd01500 0x00000000    # CS[0]n Base address to 0x0
++DATA 0xffd01504 0x0ffffff1    # CS[0]n Size
++# bit0:     0x1,     Window enabled
++# bit1:     0x0,     Write Protect disabled
++# bit3-2:   0x0,     CS0 hit selected
++# bit23-4:  0xfffff, required
++# bit31-24: 0x0f,    Size (i.e. 256MB)
++
++DATA 0xffd01508 0x10000000    # CS[1]n Base address to 256Mb
++DATA 0xffd0150c 0x00000000    # CS[1]n Size, window disabled
++
++DATA 0xffd01514 0x00000000    # CS[2]n Size, window disabled
++DATA 0xffd0151c 0x00000000    # CS[3]n Size, window disabled
++
++DATA 0xffd01494 0x00030000    # DDR ODT Control (Low)
++# bit3-0:     ODT0Rd, MODT[0] asserted during read from DRAM CS1
++# bit7-4:     ODT0Rd, MODT[0] asserted during read from DRAM CS0
++# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
++# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
++
++DATA 0xffd01498 0x00000000    # DDR ODT Control (High)
++# bit1-0:  0x0, ODT0 controlled by ODT Control (low) register above
++# bit3-2:  0x1, ODT1 active NEVER!
++# bit31-4: 0x0, required
++
++DATA 0xffd0149c 0x0000e803    # CPU ODT Control
++DATA 0xffd01480 0x00000001    # DDR Initialization Control
++# bit0: 0x1, enable DDR init upon this register write
++
++DATA 0xFFD20134 0x66666666      # L2 RAM Timing 0 Register
++DATA 0xFFD20138 0x66666666      # L2 RAM Timing 1 Register
++
++# End of Header extension
++DATA 0x0 0x0
+diff --git a/boards.cfg b/boards.cfg
+index 3cf75c3..23f84e8 100644
+--- a/boards.cfg
++++ b/boards.cfg
+@@ -153,6 +153,7 @@ openrd_client                arm         arm926ejs   openrd              Marvell
+ openrd_ultimate              arm         arm926ejs   openrd              Marvell        kirkwood        openrd:BOARD_IS_OPENRD_ULTIMATE
+ rd6281a                      arm         arm926ejs   -                   Marvell        kirkwood
+ sheevaplug                   arm         arm926ejs   -                   Marvell        kirkwood
++ib62x0                       arm         arm926ejs   ib62x0              raidsonic      kirkwood
+ dockstar                     arm         arm926ejs   -                   Seagate        kirkwood
+ jadecpu                      arm         arm926ejs   jadecpu             syteco         mb86r0x
+ mx25pdk                      arm         arm926ejs   mx25pdk             freescale      mx25          mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg
+diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h
+new file mode 100644
+index 0000000..85856f2
+--- /dev/null
++++ b/include/configs/ib62x0.h
+@@ -0,0 +1,150 @@
++/*
++ * Copyright (C) 2011-2012
++ * Gerald Kerma <dreagle@doukki.net>
++ * Luka Perkov <uboot@lukaperkov.net>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _CONFIG_IB62x0_H
++#define _CONFIG_IB62x0_H
++
++/*
++ * Version number information
++ */
++#define CONFIG_IDENT_STRING   " RaidSonic ICY BOX IB-NAS62x0"
++
++/*
++ * High level configuration options
++ */
++#define CONFIG_FEROCEON_88FR131               /* CPU Core subversion */
++#define CONFIG_KIRKWOOD                       /* SOC Family Name */
++#define CONFIG_KW88F6281              /* SOC Name */
++#define CONFIG_SKIP_LOWLEVEL_INIT     /* disable board lowlevel_init */
++
++/*
++ * Machine type
++ */
++#define CONFIG_MACH_TYPE      MACH_TYPE_NAS6210
++
++/*
++ * Compression configuration
++ */
++#define CONFIG_BZIP2
++#define CONFIG_LZMA
++#define CONFIG_LZO
++
++/*
++ * Commands configuration
++ */
++#define CONFIG_SYS_NO_FLASH           /* declare no flash (NOR/SPI) */
++#define CONFIG_SYS_MVFS
++#include <config_cmd_default.h>
++#define CONFIG_CMD_ENV
++#define CONFIG_CMD_IDE
++#define CONFIG_CMD_MII
++#define CONFIG_CMD_NAND
++#define CONFIG_CMD_PING
++#define CONFIG_CMD_USB
++
++/*
++ * mv-common.h should be defined after CMD configs since it used them
++ * to enable certain macros
++ */
++#include "mv-common.h"
++
++#undef CONFIG_SYS_PROMPT
++#define CONFIG_SYS_PROMPT     "ib62x0 => "
++
++/*
++ * Environment variables configuration
++ */
++#ifdef CONFIG_CMD_NAND
++#define CONFIG_ENV_IS_IN_NAND
++#define CONFIG_ENV_SECT_SIZE  0x20000
++#else
++#define CONFIG_ENV_IS_NOWHERE
++#endif
++#define CONFIG_ENV_SIZE               0x20000
++#define CONFIG_ENV_OFFSET     0x80000
++
++/*
++ * Default environment variables
++ */
++#define CONFIG_BOOTCOMMAND \
++      "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; "     \
++      "ubi part rootfs; "                                             \
++      "ubifsmount rootfs; "                                           \
++      "ubifsload 0x800000 ${kernel}; "                                \
++      "bootm 0x800000"
++
++#define CONFIG_MTDPARTS                               \
++      "mtdparts=orion_nand:"                  \
++      "0x80000@0x0(uboot),"                   \
++      "0x20000@0x80000(uboot_env),"           \
++      "-@0xa0000(rootfs)\0"
++
++#define CONFIG_EXTRA_ENV_SETTINGS                                     \
++      "console=console=ttyS0,115200\0"                                \
++      "mtdids=nand0=orion_nand\0"                                     \
++      "mtdparts="CONFIG_MTDPARTS                                      \
++      "kernel=/boot/uImage\0"                                         \
++      "bootargs_root=noinitrd ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0"
++
++/*
++ * Ethernet driver configuration
++ */
++#ifdef CONFIG_CMD_NET
++#define CONFIG_MVGBE_PORTS    {1, 0}  /* enable port 0 only */
++#define CONFIG_PHY_BASE_ADR   0
++#undef CONFIG_RESET_PHY_R
++#endif /* CONFIG_CMD_NET */
++
++/*
++ * SATA driver configuration
++ */
++#ifdef CONFIG_CMD_IDE
++#define __io
++#define CONFIG_IDE_PREINIT
++#define CONFIG_DOS_PARTITION
++#define CONFIG_MVSATA_IDE_USE_PORT0
++#define CONFIG_MVSATA_IDE_USE_PORT1
++#define CONFIG_SYS_ATA_IDE0_OFFSET    MV_SATA_PORT0_OFFSET
++#define CONFIG_SYS_ATA_IDE1_OFFSET    MV_SATA_PORT1_OFFSET
++#endif /* CONFIG_CMD_IDE */
++
++/*
++ * RTC driver configuration
++ */
++#ifdef CONFIG_CMD_DATE
++#define CONFIG_RTC_MV
++#endif /* CONFIG_CMD_DATE */
++
++/*
++ * File system
++ */
++#define CONFIG_CMD_EXT2
++#define CONFIG_CMD_FAT
++#define CONFIG_CMD_JFFS2
++#define CONFIG_CMD_UBI
++#define CONFIG_CMD_UBIFS
++#define CONFIG_RBTREE
++#define CONFIG_MTD_DEVICE
++#define CONFIG_MTD_PARTITIONS
++#define CONFIG_CMD_MTDPARTS
++
++#endif /* _CONFIG_IB62x0_H */
diff --git a/package/boot/uboot-kirkwood/patches/0002-kwboot.patch b/package/boot/uboot-kirkwood/patches/0002-kwboot.patch
new file mode 100644 (file)
index 0000000..091d6a1
--- /dev/null
@@ -0,0 +1,873 @@
+http://lists.denx.de/pipermail/u-boot/2012-May/125296.html
+http://patchwork.ozlabs.org/patch/161566/
+---
+
+diff --git a/doc/kwboot.1 b/doc/kwboot.1
+new file mode 100644
+index 0000000..ed08398
+--- /dev/null
++++ b/doc/kwboot.1
+@@ -0,0 +1,84 @@
++.TH KWBOOT 1 "2012-05-19"
++
++.SH NAME
++kwboot \- Boot Marvell Kirkwood SoCs over a serial link.
++.SH SYNOPSIS
++.B kwboot
++.RB [ "-b \fIimage\fP" ]
++.RB [ "-p" ]
++.RB [ "-t" ]
++.RB [ "-B \fIbaudrate\fP" ]
++.RB \fITTY\fP
++.SH "DESCRIPTION"
++
++The \fBmkimage\fP program boots boards based on Marvell's Kirkwood
++platform over their integrated UART. Boot image files will typically
++contain a second stage boot loader, such as U-Boot. The image file
++must conform to Marvell's BootROM firmware image format
++(\fIkwbimage\fP), created using a tool such as \fBmkimage\fP.
++
++Following power-up or a system reset, system BootROM code polls the
++UART for a brief period of time, sensing a handshake message which
++initiates an image upload. This program sends this boot message until
++it receives a positive acknowledgement. The image is transfered using
++Xmodem.
++
++Additionally, this program implements a minimal terminal mode, which
++can be used either standalone, or entered immediately following boot
++image transfer completion. This is often useful to catch early boot
++messages, or to manually interrupt a default boot procedure performed
++by the second-stage loader.
++
++.SH "OPTIONS"
++
++.TP
++.BI "\-b \fIimage\fP"
++Handshake; then upload file \fIimage\fP over \fITTY\fP.
++
++Note that for the encapsulated boot code to be executed, \fIimage\fP
++must be of type "UART boot" (0x69). Boot images of different types,
++such as backup images of vendor firmware downloaded from flash memory
++(type 0x8B), will not work (or not as expected). See \fB-p\fP for a
++workaround.
++
++This mode writes handshake status and upload progress indication to
++stdout.
++
++.TP
++.BI "\-p"
++In combination with \fB-b\fP, patches the header in \fIimage\fP prior
++to upload, to "UART boot" type.
++
++This option attempts on-the-fly conversion of some none-UART image
++types, such as images which were originally formatted to be stored in
++flash memory.
++
++Conversion is performed in memory. The contents of \fIimage\fP will
++not be altered.
++
++.TP
++.BI "\-t"
++Run a terminal program, connecting standard input and output to
++.RB \fITTY\fP.
++
++If used in combination with \fB-b\fP, terminal mode is entered
++immediately following a successful image upload.
++
++If standard I/O streams connect to a console, this mode will terminate
++after receiving 'ctrl-\\' followed by 'c' from console input.
++
++.TP
++.BI "\-B \fIbaudrate\fP"
++Adjust the baud rate on \fITTY\fP. Default rate is 115200.
++
++.SH "SEE ALSO"
++.PP
++\fBmkimage\fP(1)
++
++.SH "AUTHORS"
++
++Daniel Stodden <daniel.stodden@gmail.com>
++.br
++Luka Perkov <uboot@lukaperkov.net>
++.br
++David Purdy <david.c.purdy@gmail.com>
+diff --git a/tools/Makefile b/tools/Makefile
+index 8993fdd..8097d95 100644
+--- a/tools/Makefile
++++ b/tools/Makefile
+@@ -72,6 +72,7 @@ BIN_FILES-$(CONFIG_SMDK5250) += mksmdk5250spl$(SFX)
+ BIN_FILES-$(CONFIG_MX28) += mxsboot$(SFX)
+ BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX)
+ BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX)
++BIN_FILES-$(CONFIG_KIRKWOOD) += kwboot$(SFX)
+ # Source files which exist outside the tools directory
+ EXT_OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += common/env_embedded.o
+@@ -101,6 +102,7 @@ OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o
+ NOPED_OBJ_FILES-y += os_support.o
+ OBJ_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1.o
+ NOPED_OBJ_FILES-y += ublimage.o
++OBJ_FILES-$(CONFIG_KIRKWOOD) += kwboot.o
+ # Don't build by default
+ #ifeq ($(ARCH),ppc)
+@@ -234,6 +236,10 @@ $(obj)ncb$(SFX):  $(obj)ncb.o
+ $(obj)ubsha1$(SFX):   $(obj)os_support.o $(obj)sha1.o $(obj)ubsha1.o
+       $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
++$(obj)kwboot$(SFX): $(obj)kwboot.o
++      $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
++      $(HOSTSTRIP) $@
++
+ # Some of the tool objects need to be accessed from outside the tools directory
+ $(obj)%.o: $(SRCTREE)/common/%.c
+       $(HOSTCC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $<
+diff --git a/tools/kwboot.c b/tools/kwboot.c
+new file mode 100644
+index 0000000..e773f01
+--- /dev/null
++++ b/tools/kwboot.c
+@@ -0,0 +1,742 @@
++/*
++ * Boot a Marvell Kirkwood SoC, with Xmodem over UART0.
++ *
++ * (c) 2012 Daniel Stodden <daniel.stodden@gmail.com>
++ *
++ * References: marvell.com, "88F6180, 88F6190, 88F6192, and 88F6281
++ *   Integrated Controller: Functional Specifications" December 2,
++ *   2008. Chapter 24.2 "BootROM Firmware".
++ */
++
++#include <stdlib.h>
++#include <stdio.h>
++#include <string.h>
++#include <stdarg.h>
++#include <libgen.h>
++#include <fcntl.h>
++#include <errno.h>
++#include <unistd.h>
++#include <stdint.h>
++#include <termios.h>
++#include <sys/mman.h>
++#include <sys/stat.h>
++
++#include "kwbimage.h"
++
++#ifdef __GNUC__
++#define PACKED __attribute((packed))
++#else
++#define PACKED
++#endif
++
++/*
++ * Marvell BootROM UART Sensing
++ */
++
++static unsigned char kwboot_msg_boot[] = {
++      0xBB, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77
++};
++
++#define KWBOOT_MSG_REQ_DELAY  10 /* ms */
++#define KWBOOT_MSG_RSP_TIMEO  50 /* ms */
++
++/*
++ * Xmodem Transfers
++ */
++
++#define SOH   1       /* sender start of block header */
++#define EOT   4       /* sender end of block transfer */
++#define ACK   6       /* target block ack */
++#define NAK   21      /* target block negative ack */
++#define CAN   24      /* target/sender transfer cancellation */
++
++struct kwboot_block {
++      uint8_t soh;
++      uint8_t pnum;
++      uint8_t _pnum;
++      uint8_t data[128];
++      uint8_t csum;
++} PACKED;
++
++#define KWBOOT_BLK_RSP_TIMEO 1000 /* ms */
++
++static int kwboot_verbose;
++
++static void
++kwboot_printv(const char *fmt, ...)
++{
++      va_list ap;
++
++      if (kwboot_verbose) {
++              va_start(ap, fmt);
++              vprintf(fmt, ap);
++              va_end(ap);
++              fflush(stdout);
++      }
++}
++
++static void
++__spinner(void)
++{
++      const char seq[] = { '-', '\\', '|', '/' };
++      const int div = 8;
++      static int state, bs;
++
++      if (state % div == 0) {
++              fputc(bs, stdout);
++              fputc(seq[state / div % sizeof(seq)], stdout);
++              fflush(stdout);
++      }
++
++      bs = '\b';
++      state++;
++}
++
++static void
++kwboot_spinner(void)
++{
++      if (kwboot_verbose)
++              __spinner();
++}
++
++static void
++__progress(int pct, char c)
++{
++      const int width = 70;
++      static const char *nl = "";
++      static int pos;
++
++      if (pos % width == 0)
++              printf("%s%3d %% [", nl, pct);
++
++      fputc(c, stdout);
++
++      nl = "]\n";
++      pos++;
++
++      if (pct == 100) {
++              while (pos++ < width)
++                      fputc(' ', stdout);
++              fputs(nl, stdout);
++      }
++
++      fflush(stdout);
++
++}
++
++static void
++kwboot_progress(int _pct, char c)
++{
++      static int pct;
++
++      if (_pct != -1)
++              pct = _pct;
++
++      if (kwboot_verbose)
++              __progress(pct, c);
++}
++
++static int
++kwboot_tty_recv(int fd, void *buf, size_t len, int timeo)
++{
++      int rc, nfds;
++      fd_set rfds;
++      struct timeval tv;
++      ssize_t n;
++
++      rc = -1;
++
++      FD_ZERO(&rfds);
++      FD_SET(fd, &rfds);
++
++      tv.tv_sec = 0;
++      tv.tv_usec = timeo * 1000;
++      if (tv.tv_usec > 1000000) {
++              tv.tv_sec += tv.tv_usec / 1000000;
++              tv.tv_usec %= 1000000;
++      }
++
++      do {
++              nfds = select(fd + 1, &rfds, NULL, NULL, &tv);
++              if (nfds < 0)
++                      goto out;
++              if (!nfds) {
++                      errno = ETIMEDOUT;
++                      goto out;
++              }
++
++              n = read(fd, buf, len);
++              if (n < 0)
++                      goto out;
++
++              buf = (char *)buf + n;
++              len -= n;
++      } while (len > 0);
++
++      rc = 0;
++out:
++      return rc;
++}
++
++static int
++kwboot_tty_send(int fd, const void *buf, size_t len)
++{
++      int rc;
++      ssize_t n;
++
++      rc = -1;
++
++      do {
++              n = write(fd, buf, len);
++              if (n < 0)
++                      goto out;
++
++              buf = (char *)buf + n;
++              len -= n;
++      } while (len > 0);
++
++      rc = tcdrain(fd);
++out:
++      return rc;
++}
++
++static int
++kwboot_tty_send_char(int fd, unsigned char c)
++{
++      return kwboot_tty_send(fd, &c, 1);
++}
++
++static speed_t
++kwboot_tty_speed(int baudrate)
++{
++      switch (baudrate) {
++      case 115200:
++              return B115200;
++      case 57600:
++              return B57600;
++      case 38400:
++              return B38400;
++      case 19200:
++              return B19200;
++      case 9600:
++              return B9600;
++      }
++
++      return -1;
++}
++
++static int
++kwboot_open_tty(const char *path, speed_t speed)
++{
++      int rc, fd;
++      struct termios tio;
++
++      rc = -1;
++
++      fd = open(path, O_RDWR|O_NOCTTY|O_NDELAY);
++      if (fd < 0)
++              goto out;
++
++      memset(&tio, 0, sizeof(tio));
++
++      tio.c_iflag = 0;
++      tio.c_cflag = CREAD|CLOCAL|CS8;
++
++      tio.c_cc[VMIN] = 1;
++      tio.c_cc[VTIME] = 10;
++
++      cfsetospeed(&tio, speed);
++      cfsetispeed(&tio, speed);
++
++      rc = tcsetattr(fd, TCSANOW, &tio);
++      if (rc)
++              goto out;
++
++      rc = fd;
++out:
++      if (rc < 0) {
++              if (fd >= 0)
++                      close(fd);
++      }
++
++      return rc;
++}
++
++static int
++kwboot_bootmsg(int tty, void *msg)
++{
++      int rc;
++      char c;
++
++      kwboot_printv("Sending boot message. Please reboot the target...");
++
++      do {
++              rc = tcflush(tty, TCIOFLUSH);
++              if (rc)
++                      break;
++
++              rc = kwboot_tty_send(tty, msg, 8);
++              if (rc) {
++                      usleep(KWBOOT_MSG_REQ_DELAY * 1000);
++                      continue;
++              }
++
++              rc = kwboot_tty_recv(tty, &c, 1, KWBOOT_MSG_RSP_TIMEO);
++
++              kwboot_spinner();
++
++      } while (rc || c != NAK);
++
++      kwboot_printv("\n");
++
++      return rc;
++}
++
++static int
++kwboot_xm_makeblock(struct kwboot_block *block, const void *data,
++                  size_t size, int pnum)
++{
++      const size_t blksz = sizeof(block->data);
++      size_t n;
++      int i;
++
++      block->pnum = pnum;
++      block->_pnum = ~block->pnum;
++
++      n = size < blksz ? size : blksz;
++      memcpy(&block->data[0], data, n);
++      memset(&block->data[n], 0, blksz - n);
++
++      block->csum = 0;
++      for (i = 0; i < n; i++)
++              block->csum += block->data[i];
++
++      return n;
++}
++
++static int
++kwboot_xm_sendblock(int fd, struct kwboot_block *block)
++{
++      int rc, retries;
++      char c;
++
++      retries = 16;
++      do {
++              rc = kwboot_tty_send(fd, block, sizeof(*block));
++              if (rc)
++                      break;
++
++              rc = kwboot_tty_recv(fd, &c, 1, KWBOOT_BLK_RSP_TIMEO);
++              if (rc)
++                      break;
++
++              if (c != ACK)
++                      kwboot_progress(-1, '+');
++
++      } while (c == NAK && retries-- > 0);
++
++      rc = -1;
++
++      switch (c) {
++      case ACK:
++              rc = 0;
++              break;
++      case NAK:
++              errno = EBADMSG;
++              break;
++      case CAN:
++              errno = ECANCELED;
++              break;
++      default:
++              errno = EPROTO;
++              break;
++      }
++
++      return rc;
++}
++
++static int
++kwboot_xmodem(int tty, const void *_data, size_t size)
++{
++      const uint8_t *data = _data;
++      int rc, pnum, N, err;
++
++      pnum = 1;
++      N = 0;
++
++      kwboot_printv("Sending boot image...\n");
++
++      do {
++              struct kwboot_block block;
++              int n;
++
++              n = kwboot_xm_makeblock(&block,
++                                      data + N, size - N,
++                                      pnum++);
++              if (n < 0)
++                      goto can;
++
++              if (!n)
++                      break;
++
++              rc = kwboot_xm_sendblock(tty, &block);
++              if (rc)
++                      goto out;
++
++              N += n;
++              kwboot_progress(N * 100 / size, '.');
++      } while (1);
++
++      rc = kwboot_tty_send_char(tty, EOT);
++
++out:
++      return rc;
++
++can:
++      err = errno;
++      kwboot_tty_send_char(tty, CAN);
++      errno = err;
++      goto out;
++}
++
++static int
++kwboot_term_pipe(int in, int out, char *quit, int *s)
++{
++      ssize_t nin, nout;
++      char _buf[128], *buf = _buf;
++
++      nin = read(in, buf, sizeof(buf));
++      if (nin < 0)
++              return -1;
++
++      if (quit) {
++              int i;
++
++              for (i = 0; i < nin; i++) {
++                      if (*buf == quit[*s]) {
++                              (*s)++;
++                              if (!quit[*s])
++                                      return 0;
++                              buf++;
++                              nin--;
++                      } else
++                              while (*s > 0) {
++                                      nout = write(out, quit, *s);
++                                      if (nout <= 0)
++                                              return -1;
++                                      (*s) -= nout;
++                              }
++              }
++      }
++
++      while (nin > 0) {
++              nout = write(out, buf, nin);
++              if (nout <= 0)
++                      return -1;
++              nin -= nout;
++      }
++
++      return 0;
++}
++
++static int
++kwboot_terminal(int tty)
++{
++      int rc, in, s;
++      char *quit = "\34c";
++      struct termios otio, tio;
++
++      rc = -1;
++
++      in = STDIN_FILENO;
++      if (isatty(in)) {
++              rc = tcgetattr(in, &otio);
++              if (!rc) {
++                      tio = otio;
++                      cfmakeraw(&tio);
++                      rc = tcsetattr(in, TCSANOW, &tio);
++              }
++              if (rc) {
++                      perror("tcsetattr");
++                      goto out;
++              }
++
++              kwboot_printv("[Type Ctrl-%c + %c to quit]\r\n",
++                            quit[0]|0100, quit[1]);
++      } else
++              in = -1;
++
++      rc = 0;
++      s = 0;
++
++      do {
++              fd_set rfds;
++              int nfds = 0;
++
++              FD_SET(tty, &rfds);
++              nfds = nfds < tty ? tty : nfds;
++
++              if (in >= 0) {
++                      FD_SET(in, &rfds);
++                      nfds = nfds < in ? in : nfds;
++              }
++
++              nfds = select(nfds + 1, &rfds, NULL, NULL, NULL);
++              if (nfds < 0)
++                      break;
++
++              if (FD_ISSET(tty, &rfds)) {
++                      rc = kwboot_term_pipe(tty, STDOUT_FILENO, NULL, NULL);
++                      if (rc)
++                              break;
++              }
++
++              if (FD_ISSET(in, &rfds)) {
++                      rc = kwboot_term_pipe(in, tty, quit, &s);
++                      if (rc)
++                              break;
++              }
++      } while (quit[s] != 0);
++
++      tcsetattr(in, TCSANOW, &otio);
++out:
++      return rc;
++}
++
++static void *
++kwboot_mmap_image(const char *path, size_t *size, int prot)
++{
++      int rc, fd, flags;
++      struct stat st;
++      void *img;
++
++      rc = -1;
++      fd = -1;
++      img = NULL;
++
++      fd = open(path, O_RDONLY);
++      if (fd < 0)
++              goto out;
++
++      rc = fstat(fd, &st);
++      if (rc)
++              goto out;
++
++      flags = (prot & PROT_WRITE) ? MAP_PRIVATE : MAP_SHARED;
++
++      img = mmap(NULL, st.st_size, prot, flags, fd, 0);
++      if (img == MAP_FAILED) {
++              img = NULL;
++              goto out;
++      }
++
++      rc = 0;
++      *size = st.st_size;
++out:
++      if (rc && img) {
++              munmap(img, st.st_size);
++              img = NULL;
++      }
++      if (fd >= 0)
++              close(fd);
++
++      return img;
++}
++
++static uint8_t
++kwboot_img_csum8(void *_data, size_t size)
++{
++      uint8_t *data = _data, csum;
++
++      for (csum = 0; size-- > 0; data++)
++              csum += *data;
++
++      return csum;
++}
++
++static int
++kwboot_img_patch_hdr(void *img, size_t size)
++{
++      int rc;
++      bhr_t *hdr;
++      uint8_t csum;
++      const size_t hdrsz = sizeof(*hdr);
++
++      rc = -1;
++      hdr = img;
++
++      if (size < hdrsz) {
++              errno = EINVAL;
++              goto out;
++      }
++
++      csum = kwboot_img_csum8(hdr, hdrsz) - hdr->checkSum;
++      if (csum != hdr->checkSum) {
++              errno = EINVAL;
++              goto out;
++      }
++
++      if (hdr->blockid == IBR_HDR_UART_ID) {
++              rc = 0;
++              goto out;
++      }
++
++      hdr->blockid = IBR_HDR_UART_ID;
++
++      hdr->nandeccmode = IBR_HDR_ECC_DISABLED;
++      hdr->nandpagesize = 0;
++
++      hdr->srcaddr = hdr->ext
++              ? sizeof(struct kwb_header)
++              : sizeof(*hdr);
++
++      hdr->checkSum = kwboot_img_csum8(hdr, hdrsz) - csum;
++
++      rc = 0;
++out:
++      return rc;
++}
++
++static void
++kwboot_usage(FILE *stream, char *progname)
++{
++      fprintf(stream,
++              "Usage: %s -b <image> [ -p ] [ -t ] "
++              "[-B <baud> ] <TTY>\n", progname);
++      fprintf(stream, "\n");
++      fprintf(stream, "  -b <image>: boot <image>\n");
++      fprintf(stream, "  -p: patch <image> to type 0x69 (uart boot)\n");
++      fprintf(stream, "\n");
++      fprintf(stream, "  -t: mini terminal\n");
++      fprintf(stream, "\n");
++      fprintf(stream, "  -B <baud>: set baud rate\n");
++      fprintf(stream, "\n");
++}
++
++int
++main(int argc, char **argv)
++{
++      const char *ttypath, *imgpath;
++      int rv, rc, tty, term, prot, patch;
++      void *bootmsg;
++      void *img;
++      size_t size;
++      speed_t speed;
++
++      rv = 1;
++      tty = -1;
++      bootmsg = NULL;
++      imgpath = NULL;
++      img = NULL;
++      term = 0;
++      patch = 0;
++      size = 0;
++      speed = B115200;
++
++      kwboot_verbose = isatty(STDOUT_FILENO);
++
++      do {
++              int c = getopt(argc, argv, "hb:ptB:");
++              if (c < 0)
++                      break;
++
++              switch (c) {
++              case 'b':
++                      bootmsg = kwboot_msg_boot;
++                      imgpath = optarg;
++                      break;
++
++              case 'p':
++                      patch = 1;
++                      break;
++
++              case 't':
++                      term = 1;
++                      break;
++
++              case 'B':
++                      speed = kwboot_tty_speed(atoi(optarg));
++                      if (speed == -1)
++                              goto usage;
++                      break;
++
++              case 'h':
++                      rv = 0;
++              default:
++                      goto usage;
++              }
++      } while (1);
++
++      if (!bootmsg && !term)
++              goto usage;
++
++      if (patch && !imgpath)
++              goto usage;
++
++      if (argc - optind < 1)
++              goto usage;
++
++      ttypath = argv[optind++];
++
++      tty = kwboot_open_tty(ttypath, speed);
++      if (tty < 0) {
++              perror(ttypath);
++              goto out;
++      }
++
++      if (imgpath) {
++              prot = PROT_READ | (patch ? PROT_WRITE : 0);
++
++              img = kwboot_mmap_image(imgpath, &size, prot);
++              if (!img) {
++                      perror(imgpath);
++                      goto out;
++              }
++      }
++
++      if (patch) {
++              rc = kwboot_img_patch_hdr(img, size);
++              if (rc) {
++                      fprintf(stderr, "%s: Invalid image.\n", imgpath);
++                      goto out;
++              }
++      }
++
++      if (bootmsg) {
++              rc = kwboot_bootmsg(tty, bootmsg);
++              if (rc) {
++                      perror("bootmsg");
++                      goto out;
++              }
++      }
++
++      if (img) {
++              rc = kwboot_xmodem(tty, img, size);
++              if (rc) {
++                      perror("xmodem");
++                      goto out;
++              }
++      }
++
++      if (term) {
++              rc = kwboot_terminal(tty);
++              if (rc && !(errno == EINTR)) {
++                      perror("terminal");
++                      goto out;
++              }
++      }
++
++      rv = 0;
++out:
++      if (tty >= 0)
++              close(tty);
++
++      if (img)
++              munmap(img, size);
++
++      return rv;
++
++usage:
++      kwboot_usage(rv ? stderr : stdout, basename(argv[0]));
++      goto out;
++}
diff --git a/package/boot/uboot-kirkwood/patches/0003-ide_bus.patch b/package/boot/uboot-kirkwood/patches/0003-ide_bus.patch
new file mode 100644 (file)
index 0000000..c94d63d
--- /dev/null
@@ -0,0 +1,17 @@
+http://lists.denx.de/pipermail/u-boot/2012-April/122594.html
+http://patchwork.ozlabs.org/patch/159129/
+---
+
+diff --git a/include/ide.h b/include/ide.h
+index 8ecc9dd..385e909 100644
+--- a/include/ide.h
++++ b/include/ide.h
+@@ -24,7 +24,7 @@
+ #ifndef       _IDE_H
+ #define _IDE_H
+-#define       IDE_BUS(dev)    (dev >> 1)
++#define IDE_BUS(dev)  (dev / (CONFIG_SYS_IDE_MAXDEVICE / CONFIG_SYS_IDE_MAXBUS))
+ #define       ATA_CURR_BASE(dev)      (CONFIG_SYS_ATA_BASE_ADDR+ide_bus_offset[IDE_BUS(dev)])
diff --git a/package/boot/uboot-kirkwood/patches/100-iconnect.patch b/package/boot/uboot-kirkwood/patches/100-iconnect.patch
new file mode 100644 (file)
index 0000000..d2f35ad
--- /dev/null
@@ -0,0 +1,10 @@
+--- a/boards.cfg
++++ b/boards.cfg
+@@ -137,6 +137,7 @@ hawkboard_uart               arm
+ enbw_cmc                     arm         arm926ejs   enbw_cmc            enbw           davinci
+ calimain                     arm         arm926ejs   calimain            omicron        davinci
+ dns325                       arm         arm926ejs   -                   d-link         kirkwood
++iconnect                     arm         arm926ejs   -                   iomega         kirkwood
+ km_kirkwood                  arm         arm926ejs   km_arm              keymile        kirkwood      km_kirkwood:KM_DISABLE_PCI
+ km_kirkwood_pci              arm         arm926ejs   km_arm              keymile        kirkwood      km_kirkwood:KM_RECONFIG_XLX
+ mgcoge3un                    arm         arm926ejs   km_arm              keymile        kirkwood
diff --git a/package/boot/uboot-kirkwood/patches/110-dockstar.patch b/package/boot/uboot-kirkwood/patches/110-dockstar.patch
new file mode 100644 (file)
index 0000000..4ff7e57
--- /dev/null
@@ -0,0 +1,35 @@
+--- a/include/configs/dockstar.h
++++ b/include/configs/dockstar.h
+@@ -83,22 +83,19 @@
+  * Default environment variables
+  */
+ #define CONFIG_BOOTCOMMAND \
+-      "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; "     \
+-      "ubi part root; " \
+-      "ubifsmount root; " \
+-      "ubifsload 0x800000 ${kernel}; " \
+-      "ubifsload 0x1100000 ${initrd}; " \
+-      "bootm 0x800000 0x1100000"
++      "${x_bootcmd_kernel}; "                                 \
++      "setenv bootargs ${x_bootargs} ${x_bootargs_root}; "    \
++      "${x_bootcmd_usb}; bootm 0x6400000;"
+-#define CONFIG_MTDPARTS               "mtdparts=orion_nand:1m(uboot),-(root)\0"
++#define CONFIG_MTDPARTS \
++      "orion_nand:1M(u-boot),1M@1M(second_stage_u-boot),"     \
++      "3M@2M(kernel),32M@5M(rootfs),219M@37M(data) rw\0"
+ #define CONFIG_EXTRA_ENV_SETTINGS \
+-      "console=console=ttyS0,115200\0" \
+-      "mtdids=nand0=orion_nand\0" \
+-      "mtdparts="CONFIG_MTDPARTS \
+-      "kernel=/boot/uImage\0" \
+-      "initrd=/boot/uInitrd\0" \
+-      "bootargs_root=ubi.mtd=1 root=ubi0:root rootfstype=ubifs ro\0"
++      "x_bootargs=console=ttyS0,115200 mtdparts="CONFIG_MTDPARTS      \
++      "x_bootcmd_kernel=nand read 0x6400000 0x200000 0x300000\0"      \
++      "x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0"     \
++      "x_bootcmd_usb=usb start\0"
+ /*
+  * Ethernet Driver configuration
diff --git a/package/boot/uboot-omap35xx/Makefile b/package/boot/uboot-omap35xx/Makefile
new file mode 100644 (file)
index 0000000..928acc7
--- /dev/null
@@ -0,0 +1,89 @@
+#
+# Copyright (C) 2011 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/kernel.mk
+
+PKG_NAME:=u-boot
+PKG_VERSION:=2010.12
+PKG_RELEASE:=1
+
+PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
+PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
+PKG_SOURCE_URL:=ftp://ftp.denx.de/pub/u-boot
+PKG_MD5SUM:=
+PKG_TARGETS:=bin
+
+include $(INCLUDE_DIR)/package.mk
+
+define uboot/Default
+  TITLE:=
+  CONFIG:=
+  IMAGE:=
+endef
+
+define uboot/omap3_overo
+  TITLE:=U-boot for the gumstix board
+endef
+
+UBOOTS:=omap3_overo
+
+define Package/uboot/template
+define Package/uboot-omap35xx-$(1)
+  SECTION:=boot
+  CATEGORY:=Boot Loaders
+  DEPENDS:=@TARGET_omap35xx
+  TITLE:=$(2)
+  URL:=http://www.denx.de/wiki/U-Boot
+  VARIANT:=$(1)
+endef
+endef
+
+define BuildUbootPackage
+       $(eval $(uboot/Default))
+       $(eval $(uboot/$(1)))
+       $(call Package/uboot/template,$(1),$(TITLE))
+endef
+
+
+ifdef BUILD_VARIANT
+$(eval $(call uboot/$(BUILD_VARIANT)))
+UBOOT_CONFIG:=$(if $(CONFIG),$(CONFIG),$(BUILD_VARIANT))
+UBOOT_IMAGE:=$(if $(IMAGE),$(IMAGE),openwrt-$(BOARD)-$(BUILD_VARIANT)-u-boot.bin)
+endif
+
+define Build/Prepare
+       $(call Build/Prepare/Default)
+       $(CP) ./files/* $(PKG_BUILD_DIR)
+       find $(PKG_BUILD_DIR) -name .svn | $(XARGS) rm -rf
+endef
+
+define Build/Configure
+       $(MAKE) -C $(PKG_BUILD_DIR) \
+               $(UBOOT_CONFIG)_config
+endef
+
+define Build/Compile
+       $(MAKE) -C $(PKG_BUILD_DIR) \
+               CROSS_COMPILE=$(TARGET_CROSS)
+endef
+
+define Package/uboot/install/template
+define Package/uboot-omap35xx-$(1)/install
+       $(INSTALL_DIR) $$(1)
+       $(CP) $(PKG_BUILD_DIR)/u-boot.bin $(BIN_DIR)/$(2)
+endef
+endef
+
+$(foreach u,$(UBOOTS), \
+       $(eval $(call Package/uboot/install/template,$(u),openwrt-$(BOARD)-$(u)-u-boot.bin)) \
+)
+
+$(foreach u,$(UBOOTS), \
+       $(eval $(call BuildUbootPackage,$(u))) \
+       $(eval $(call BuildPackage,uboot-omap35xx-$(u))) \
+)
diff --git a/package/boot/uboot-omap35xx/files/include/configs/omap3_overo.h b/package/boot/uboot-omap35xx/files/include/configs/omap3_overo.h
new file mode 100644 (file)
index 0000000..e1c930d
--- /dev/null
@@ -0,0 +1,316 @@
+/*
+ * Configuration settings for the Gumstix Overo board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7           1       /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP            1       /* in a TI OMAP core */
+#define CONFIG_OMAP34XX                1       /* which is a 34XX */
+#define CONFIG_OMAP3430                1       /* which is in a 3430 */
+#define CONFIG_OMAP3_OVERO     1       /* working with overo */
+
+#define CONFIG_SDRC    /* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h>      /* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO         1
+#define CONFIG_DISPLAY_BOARDINFO       1
+
+/* Clock Defines */
+#define V_OSCK                 26000000        /* Clock output from T2 */
+#define V_SCLK                 (V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ          /* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG             1       /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS       1
+#define CONFIG_INITRD_TAG              1
+#define CONFIG_REVISION_TAG            1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE                        (128 << 10)     /* 128 KiB */
+                                               /* Sector */
+#define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + (128 << 10))
+                                               /* initial data */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK                  48000000        /* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    (-4)
+#define CONFIG_SYS_NS16550_CLK         V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX              3
+#define CONFIG_SYS_NS16550_COM3                OMAP34XX_UART3
+#define CONFIG_SERIAL3                 3
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE                        115200
+#define CONFIG_SYS_BAUDRATE_TABLE      {4800, 9600, 19200, 38400, 57600, \
+                                       115200}
+#define CONFIG_GENERIC_MMC             1
+#define CONFIG_MMC                     1
+#define CONFIG_OMAP_HSMMC              1
+#define CONFIG_DOS_PARTITION           1
+
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR                1
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2                /* EXT2 Support                 */
+#define CONFIG_CMD_FAT         /* FAT support                  */
+#define CONFIG_CMD_JFFS2       /* JFFS2 Support                */
+
+#define CONFIG_CMD_I2C         /* I2C serial bus support       */
+#define CONFIG_CMD_MMC         /* MMC support                  */
+#define CONFIG_CMD_NAND                /* NAND support                 */
+
+#undef CONFIG_CMD_FLASH                /* flinfo, erase, protect       */
+#undef CONFIG_CMD_FPGA         /* FPGA configuration Support   */
+#undef CONFIG_CMD_IMI          /* iminfo                       */
+#undef CONFIG_CMD_IMLS         /* List all found images        */
+#undef CONFIG_CMD_NFS          /* NFS support                  */
+#define CONFIG_CMD_NET         /* bootp, tftpboot, rarpboot    */
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_HARD_I2C                        1
+#define CONFIG_SYS_I2C_SPEED           100000
+#define CONFIG_SYS_I2C_SLAVE           1
+#define CONFIG_SYS_I2C_BUS             0
+#define CONFIG_SYS_I2C_BUS_SELECT      1
+#define CONFIG_I2C_MULTI_BUS           1
+#define CONFIG_DRIVER_OMAP34XX_I2C     1
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER           1
+#define CONFIG_TWL4030_LED             1
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_QUIET_TEST     1
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_ADDR           NAND_BASE       /* physical address */
+                                                       /* to access nand */
+#define CONFIG_SYS_NAND_BASE           NAND_BASE       /* physical address */
+                                                       /* to access nand */
+                                                       /* at CS0 */
+#define GPMC_NAND_ECC_LP_x16_LAYOUT    1
+
+#define CONFIG_SYS_MAX_NAND_DEVICE     1       /* Max number of NAND */
+                                               /* devices */
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV               "nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET       0x680000
+#define CONFIG_JFFS2_PART_SIZE         0xf980000       /* size of jffs2 */
+                                                       /* partition */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY               5
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+       "loadaddr=0x82000000\0" \
+       "console=ttyO2,115200n8\0" \
+       "mpurate=500\0" \
+       "vram=12M\0" \
+       "dvimode=1024x768MR-16@60\0" \
+       "defaultdisplay=dvi\0" \
+       "mmcdev=0\0" \
+       "mmcroot=/dev/mmcblk0p2 rw\0" \
+       "mmcrootfstype=ext3 rootwait\0" \
+       "nandroot='ubi0:rootfs ubi.mtd=5 ubi.mtd=6 ubi.mtd=7'\0" \
+       "nandrootfstype=ubifs\0" \
+       "mmcargs=setenv bootargs console=${console} " \
+               "mpurate=${mpurate} " \
+               "vram=${vram} " \
+               "omapfb.mode=dvi:${dvimode} " \
+               "omapfb.debug=y " \
+               "omapdss.def_disp=${defaultdisplay} " \
+               "root=${mmcroot} " \
+               "rootfstype=${mmcrootfstype}\0" \
+       "nandargs=setenv bootargs console=${console} " \
+               "mpurate=${mpurate} " \
+               "vram=${vram} " \
+               "omapfb.mode=dvi:${dvimode} " \
+               "omapfb.debug=y " \
+               "omapdss.def_disp=${defaultdisplay} " \
+               "root=${nandroot} " \
+               "rootfstype=${nandrootfstype}\0" \
+       "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+       "bootscript=echo Running bootscript from mmc ...; " \
+               "source ${loadaddr}\0" \
+       "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+       "mmcboot=echo Booting from mmc ...; " \
+               "run mmcargs; " \
+               "bootm ${loadaddr}\0" \
+       "nandboot=echo Booting from nand ...; " \
+               "run nandargs; " \
+               "nand read ${loadaddr} 280000 200000; " \
+               "bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+       "if mmc rescan ${mmcdev}; then " \
+               "if run loadbootscript; then " \
+                       "run bootscript; " \
+               "else " \
+                       "if run loaduimage; then " \
+                               "run mmcboot; " \
+                       "else run nandboot; " \
+                       "fi; " \
+               "fi; " \
+       "else run nandboot; fi"
+
+#define CONFIG_AUTO_COMPLETE   1
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP            /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER         /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
+#define CONFIG_SYS_PROMPT              "Overo # "
+#define CONFIG_SYS_CBSIZE              256     /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + \
+                                       sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS             16      /* max number of command */
+                                               /* args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START       (OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END         (OMAP34XX_SDRC_CS0 + \
+                                       0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR           (OMAP34XX_SDRC_CS0) /* default load */
+                                                               /* address */
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE           OMAP34XX_GPT2
+#define CONFIG_SYS_PTV                 2       /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ                  1000
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE       (128 << 10)     /* regular stack 128 KiB */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ   (4 << 10)       /* IRQ stack 4 KiB */
+#define CONFIG_STACKSIZE_FIQ   (4 << 10)       /* FIQ stack 4 KiB */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS   2       /* CS1 may or may not be populated */
+#define PHYS_SDRAM_1           OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE      (32 << 20)      /* at least 32 MiB */
+#define PHYS_SDRAM_2           OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C             1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE               GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE               GPMC_SIZE_128M
+
+#define CONFIG_SYS_MONITOR_LEN         (256 << 10)     /* Reserve 2 sectors */
+
+#define CONFIG_SYS_FLASH_BASE          boot_flash_base
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE                CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_ONENAND_BASE                ONENAND_MAP
+
+#define CONFIG_ENV_IS_IN_NAND          1
+#define ONENAND_ENV_OFFSET             0x240000 /* environment starts here */
+#define SMNAND_ENV_OFFSET              0x240000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE       boot_flash_sec
+#define CONFIG_ENV_OFFSET              boot_flash_off
+#define CONFIG_ENV_ADDR                        SMNAND_ENV_OFFSET
+
+#ifndef __ASSEMBLY__
+extern unsigned int boot_flash_base;
+extern volatile unsigned int boot_flash_env_addr;
+extern unsigned int boot_flash_off;
+extern unsigned int boot_flash_sec;
+extern unsigned int boot_flash_type;
+#endif
+
+#if defined(CONFIG_CMD_NET)
+/*----------------------------------------------------------------------------
+ * SMSC9211 Ethernet from SMSC9118 family
+ *----------------------------------------------------------------------------
+ */
+
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X         1
+#define CONFIG_SMC911X_32_BIT
+#define CONFIG_SMC911X_BASE     0x2C000000
+
+#endif /* (CONFIG_CMD_NET) */
+
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR       0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE       0x800
+#define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_SIZE - \
+                                        GENERATED_GBL_DATA_SIZE)
+
+#endif                         /* __CONFIG_H */
diff --git a/package/boot/uboot-omap4/Makefile b/package/boot/uboot-omap4/Makefile
new file mode 100644 (file)
index 0000000..d128e16
--- /dev/null
@@ -0,0 +1,90 @@
+#
+# Copyright (C) 2012 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/kernel.mk
+
+PKG_NAME:=u-boot
+PKG_VERSION:=2011.12
+PKG_RELEASE:=1
+
+PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
+PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
+PKG_SOURCE_URL:=ftp://ftp.denx.de/pub/u-boot
+PKG_MD5SUM:=7f29b9f6da44d6e46e988e7561fd1d5f
+PKG_TARGETS:=bin
+
+include $(INCLUDE_DIR)/package.mk
+
+define uboot/Default
+  TITLE:=
+  CONFIG:=
+  IMAGE:=
+endef
+
+define uboot/omap4_panda
+  TITLE:=U-Boot for the Pandaboard
+endef
+
+UBOOTS:=omap4_panda
+
+define Package/uboot/template
+define Package/uboot-omap4-$(1)
+  SECTION:=boot
+  CATEGORY:=Boot Loaders
+  DEPENDS:=@TARGET_omap4
+  TITLE:=$(2)
+  URL:=http://www.denx.de/wiki/U-Boot
+  VARIANT:=$(1)
+endef
+endef
+
+define BuildUbootPackage
+       $(eval $(uboot/Default))
+       $(eval $(uboot/$(1)))
+       $(call Package/uboot/template,$(1),$(TITLE))
+endef
+
+
+ifdef BUILD_VARIANT
+$(eval $(call uboot/$(BUILD_VARIANT)))
+UBOOT_CONFIG:=$(if $(CONFIG),$(CONFIG),$(BUILD_VARIANT))
+UBOOT_IMAGE:=$(if $(IMAGE),$(IMAGE),openwrt-$(BOARD)-$(BUILD_VARIANT)-u-boot.bin)
+endif
+
+define Build/Prepare
+       $(call Build/Prepare/Default)
+#      $(CP) ./files/* $(PKG_BUILD_DIR)
+       find $(PKG_BUILD_DIR) -name .svn | $(XARGS) rm -rf
+endef
+
+define Build/Configure
+       $(MAKE) -C $(PKG_BUILD_DIR) \
+               $(UBOOT_CONFIG)_config
+endef
+
+define Build/Compile
+       $(MAKE) -C $(PKG_BUILD_DIR) \
+               CROSS_COMPILE=$(TARGET_CROSS)
+endef
+
+define Package/uboot/install/template
+define Package/uboot-omap4-$(1)/install
+       $(INSTALL_DIR) $$(1)
+       $(CP) $(PKG_BUILD_DIR)/MLO $(BIN_DIR)/MLO-$(BOARD)
+       $(CP) $(PKG_BUILD_DIR)/u-boot.img $(BIN_DIR)/$(2)
+endef
+endef
+
+$(foreach u,$(UBOOTS), \
+       $(eval $(call Package/uboot/install/template,$(u),openwrt-$(BOARD)-$(u)-u-boot.img)) \
+)
+
+$(foreach u,$(UBOOTS), \
+       $(eval $(call BuildUbootPackage,$(u))) \
+       $(eval $(call BuildPackage,uboot-omap4-$(u))) \
+)
diff --git a/package/boot/uboot-pxa/Makefile b/package/boot/uboot-pxa/Makefile
new file mode 100644 (file)
index 0000000..7fe747c
--- /dev/null
@@ -0,0 +1,89 @@
+#
+# Copyright (C) 2012 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/kernel.mk
+
+PKG_NAME:=u-boot
+PKG_VERSION:=2011.08.25
+PKG_RELEASE:=1
+
+PKG_SOURCE_PROTO:=git
+PKG_SOURCE_URL:=git://github.com/ashcharles/verdex-uboot.git
+PKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_VERSION)
+PKG_SOURCE_VERSION:=ca6bf3ef6ac5f5132a359b43dfa31e07076b74b7
+PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION)-$(PKG_SOURCE_VERSION).tar.gz
+
+include $(INCLUDE_DIR)/package.mk
+
+define uboot/Default
+  TITLE:=
+  CONFIG:=
+  IMAGE:=
+endef
+
+define uboot/gumstix
+  TITLE:=U-Boot for the Gumstix Verdex
+endef
+
+UBOOTS:=gumstix
+
+define Package/uboot/template
+define Package/uboot-pxa-$(1)
+  SECTION:=boot
+  CATEGORY:=Boot Loaders
+  DEPENDS:=@TARGET_pxa
+  TITLE:=$(2)
+  URL:=http://www.denx.de/wiki/U-Boot
+  VARIANT:=$(1)
+  MAINTAINER:=Florian Fainelli <florian@openwrt.org>
+endef
+endef
+
+define BuildUBootPackage
+       $(eval $(uboot/Default))
+       $(eval $(uboot/$(1)))
+       $(call Package/uboot/template,$(1),$(TITLE))
+endef
+
+ifdef BUILD_VARIANT
+$(eval $(call uboot/$(BUILD_VARIANT)))
+UBOOT_CONFIG:=$(if $(CONFIG),$(CONFIG),$(BUILD_VARIANT))
+UBOOT_IMAGE:=$(if $(IMAGE),$(IMAGE),openwrt-$(BOARD)-$(BUILD_VARIANT)-u-boot.bin)
+endif
+
+define Build/Configure
+       $(MAKE) -C $(PKG_BUILD_DIR) \
+               $(UBOOT_CONFIG)_config
+endef
+
+define Build/Compile
+       $(MAKE) -C $(PKG_BUILD_DIR) \
+               u-boot.bin \
+               CROSS_COMPILE=$(TARGET_CROSS)
+endef
+
+define Package/uboot/install/default
+       $(INSTALL_DIR) $(BIN_DIR)
+       $(CP) $(PKG_BUILD_DIR)/u-boot.bin \
+               $(BIN_DIR)/openwrt-$(BOARD)-$(1)-u-boot.bin
+endef
+
+define Package/uboot/install/template
+define Package/uboot-pxa-$(1)/install
+       $(call Package/uboot/install/default,$(2))
+endef
+endef
+
+$(foreach u,$(UBOOTS), \
+       $(eval $(call Package/uboot/install/template,$(u),$(u))) \
+)
+
+$(foreach u,$(UBOOTS), \
+       $(eval $(call BuildUBootPackage,$(u))) \
+       $(eval $(call BuildPackage,uboot-pxa-$(u))) \
+)
diff --git a/package/boot/uboot-pxa/patches/001-squashfs_rootfstype_cmdline.patch b/package/boot/uboot-pxa/patches/001-squashfs_rootfstype_cmdline.patch
new file mode 100644 (file)
index 0000000..cfef66b
--- /dev/null
@@ -0,0 +1,13 @@
+diff --git a/include/configs/gumstix.h b/include/configs/gumstix.h
+index 319da63..5483993 100644
+--- a/include/configs/gumstix.h
++++ b/include/configs/gumstix.h
+@@ -136,7 +136,7 @@
+ #define CONFIG_MISC_INIT_R    /* misc_init_r function in gumstix sets board serial number */
+ #define CONFIG_BOOTFILE               boot/uImage
+-#define CONFIG_BOOTARGS               "console=ttyS0,115200n8 root=1f01 rootfstype=jffs2 reboot=cold,hard"
++#define CONFIG_BOOTARGS               "console=ttyS0,115200n8 root=1f01 rootfstype=squashfs,jffs2 reboot=cold,hard"
+ #define CONFIG_BOOTCOMMAND    "icache on; setenv stderr nulldev; setenv stdout nulldev; if pinit on && fatload ide 0 a2000000 gumstix-factory.script; then setenv stdout serial; setenv stderr serial; echo Found gumstix-factory.script on CF...; autoscr; else if mmcinit && fatload mmc 0 a2000000 gumstix-factory.script; then setenv stdout serial; setenv stderr serial; echo Found gumstix-factory.script on MMC...; autoscr; else setenv stdout serial; setenv stderr serial; katload 100000 && bootm; fi; fi"
+ #define CONFIG_BOOTDELAY      2               /* in seconds */
+ #define CONFIG_EXTRA_ENV_SETTINGS     "verify=no"
diff --git a/package/boot/uboot-xburst/Makefile b/package/boot/uboot-xburst/Makefile
new file mode 100644 (file)
index 0000000..1d340fd
--- /dev/null
@@ -0,0 +1,102 @@
+#
+# Copyright (C) 2010 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/kernel.mk
+
+PKG_NAME:=u-boot
+PKG_VERSION:=2009.11
+PKG_RELEASE:=1
+
+PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
+PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
+PKG_SOURCE_URL:=ftp://ftp.denx.de/pub/u-boot
+PKG_MD5SUM:=
+PKG_TARGETS:=bin
+
+include $(INCLUDE_DIR)/package.mk
+
+define uboot/Default
+  TITLE:=
+  CONFIG:=
+  IMAGE:=
+endef
+
+define uboot/qi_lb60
+  TITLE:=U-boot for the qi_lb60 board
+endef
+
+define uboot/avt2
+  TITLE:=U-boot for the avt2 board
+endef
+
+define uboot/sakc
+  TITLE:=U-boot for the sakc board
+endef
+
+define uboot/n516
+  TITLE:=U-boot for the N516 e-book reader
+  CONFIG:=n516_nand
+endef
+
+UBOOTS:=qi_lb60 n516 avt2 sakc
+
+define Package/uboot/template
+define Package/uboot-xburst-$(1)
+  SECTION:=boot
+  CATEGORY:=Boot Loaders
+  DEPENDS:=@TARGET_xburst
+  TITLE:=$(2)
+  URL:=http://www.denx.de/wiki/U-Boot
+  VARIANT:=$(1)
+endef
+endef
+
+define BuildUbootPackage
+       $(eval $(uboot/Default))
+       $(eval $(uboot/$(1)))
+       $(call Package/uboot/template,$(1),$(TITLE))
+endef
+
+
+ifdef BUILD_VARIANT
+$(eval $(call uboot/$(BUILD_VARIANT)))
+UBOOT_CONFIG:=$(if $(CONFIG),$(CONFIG),$(BUILD_VARIANT))
+UBOOT_IMAGE:=$(if $(IMAGE),$(IMAGE),openwrt-$(BOARD)-$(BUILD_VARIANT)-u-boot.bin)
+endif
+
+define Build/Prepare
+       $(call Build/Prepare/Default)
+       $(CP) ./files/* $(PKG_BUILD_DIR)
+       find $(PKG_BUILD_DIR) -name .svn | $(XARGS) rm -rf
+endef
+
+define Build/Configure
+       $(MAKE) -C $(PKG_BUILD_DIR) \
+               $(UBOOT_CONFIG)_config
+endef
+
+define Build/Compile
+       $(MAKE) -C $(PKG_BUILD_DIR) \
+               CROSS_COMPILE=$(TARGET_CROSS)
+endef
+
+define Package/uboot/install/template
+define Package/uboot-xburst-$(1)/install
+       $(INSTALL_DIR) $$(1)
+       $(CP) $(PKG_BUILD_DIR)/u-boot-nand.bin $(BIN_DIR)/$(2)
+endef
+endef
+
+$(foreach u,$(UBOOTS), \
+       $(eval $(call Package/uboot/install/template,$(u),openwrt-$(BOARD)-$(u)-u-boot.bin)) \
+)
+
+$(foreach u,$(UBOOTS), \
+       $(eval $(call BuildUbootPackage,$(u))) \
+       $(eval $(call BuildPackage,uboot-xburst-$(u))) \
+)
diff --git a/package/boot/uboot-xburst/files/board/n516/Makefile b/package/boot/uboot-xburst/files/board/n516/Makefile
new file mode 100644 (file)
index 0000000..da3bb4c
--- /dev/null
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2006
+# Ingenic Semiconductor, <jlwei@ingenic.cn>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).a
+
+COBJS  = $(BOARD).o flash.o
+
+OBJS   = $(addprefix $(obj),$(COBJS))
+SOBJS  = 
+
+$(LIB):        $(obj).depend $(OBJS) $(SOBJS)
+       $(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+$(obj).depend: Makefile $(SOBJS:.o=.S) $(COBJS:.o=.c)
+               $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(COBJS:.o=.c) > $@
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/package/boot/uboot-xburst/files/board/n516/config.mk b/package/boot/uboot-xburst/files/board/n516/config.mk
new file mode 100644 (file)
index 0000000..4bfe680
--- /dev/null
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2006
+# Ingenic Semiconductor, <jlwei@ingenic.cn>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Hanvon n516 e-book, MIPS32 core
+#
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+# ROM version
+TEXT_BASE = 0x88000000
+
+# RAM version
+#TEXT_BASE = 0x80100000
+endif
diff --git a/package/boot/uboot-xburst/files/board/n516/flash.c b/package/boot/uboot-xburst/files/board/n516/flash.c
new file mode 100644 (file)
index 0000000..fd5f815
--- /dev/null
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2006
+ * Ingenic Semiconductor, <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];   /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+       return (0);
+}
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+       printf ("flash_erase not implemented\n");
+       return 0;
+}
+
+void flash_print_info (flash_info_t * info)
+{
+       printf ("flash_print_info not implemented\n");
+}
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+       printf ("write_buff not implemented\n");
+       return (-1);
+}
diff --git a/package/boot/uboot-xburst/files/board/n516/n516.c b/package/boot/uboot-xburst/files/board/n516/n516.c
new file mode 100644 (file)
index 0000000..d788596
--- /dev/null
@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2006
+ * Ingenic Semiconductor, <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/mipsregs.h>
+#include <asm/jz4740.h>
+#include <asm/addrspace.h>
+#include <asm/cacheops.h>
+
+void _machine_restart(void)
+{
+       __wdt_select_extalclk();
+       __wdt_select_clk_div64();
+       __wdt_set_data(100);
+       __wdt_set_count(0);
+       __tcu_start_wdt_clock();
+       __wdt_start();
+       while(1);
+
+}
+
+static void gpio_init(void)
+{
+
+       REG_GPIO_PXPES(0) = 0xffffffff;
+       REG_GPIO_PXPES(1) = 0xffffffff;
+       REG_GPIO_PXPES(2) = 0xffffffff;
+       REG_GPIO_PXPES(3) = 0xffffffff;
+
+       /*
+        * Initialize NAND Flash Pins
+        */
+       __gpio_as_nand();
+
+       /*
+        * Initialize SDRAM pins
+        */
+       __gpio_as_sdram_32bit();
+
+       /*
+        * Initialize UART0 pins
+        */
+       __gpio_as_uart0();
+
+       /*
+        * Initialize MSC pins
+        */
+       __gpio_as_msc();
+
+       /*
+        * Initialize LCD pins
+        */
+       __gpio_as_lcd_16bit();
+
+       /*
+        * Initialize Other pins
+        */
+       __gpio_as_output(GPIO_SD_VCC_EN_N);
+       __gpio_clear_pin(GPIO_SD_VCC_EN_N);
+
+       __gpio_as_input(GPIO_SD_CD_N);
+       __gpio_disable_pull(GPIO_SD_CD_N);
+
+       __gpio_as_output(GPIO_DISP_OFF_N);
+
+       __gpio_as_output(GPIO_LED_EN);
+       __gpio_set_pin(GPIO_LED_EN);
+
+       __gpio_as_input(127);
+}
+
+static void cpm_init(void)
+{
+       __cpm_stop_ipu();
+       __cpm_stop_cim();
+       __cpm_stop_i2c();
+       __cpm_stop_ssi();
+       __cpm_stop_uart1();
+       __cpm_stop_sadc();
+       __cpm_stop_uhc();
+       __cpm_stop_udc();
+       __cpm_stop_aic1();
+       __cpm_stop_aic2();
+       __cpm_suspend_udcphy();
+       __cpm_suspend_usbphy();
+}
+
+//----------------------------------------------------------------------
+// board early init routine
+
+void board_early_init(void)
+{
+       gpio_init();
+       cpm_init();
+}
+
+//----------------------------------------------------------------------
+// U-Boot common routines
+
+int checkboard (void)
+{
+       DECLARE_GLOBAL_DATA_PTR;
+
+       printf("Board: Hanvon n516 e-book (CPU Speed %d MHz)\n",
+              gd->cpu_clk/1000000);
+
+       return 0; /* success */
+}
diff --git a/package/boot/uboot-xburst/files/board/n516/u-boot-nand.lds b/package/boot/uboot-xburst/files/board/n516/u-boot-nand.lds
new file mode 100644 (file)
index 0000000..a15a96e
--- /dev/null
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2006
+ * Ingenic Semiconductor, <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
+
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+       . = 0x00000000;
+
+       . = ALIGN(4);
+       .text       :
+       {
+         *(.text)
+       }
+
+       . = ALIGN(4);
+       .rodata  : { *(.rodata) }
+
+       . = ALIGN(4);
+       .data  : { *(.data) }
+
+       . = ALIGN(4);
+       .sdata  : { *(.sdata) }
+
+       _gp = ALIGN(16);
+
+       __got_start = .;
+       .got  : { *(.got) }
+       __got_end = .;
+
+       .sdata  : { *(.sdata) }
+
+       __u_boot_cmd_start = .;
+       .u_boot_cmd : { *(.u_boot_cmd) }
+       __u_boot_cmd_end = .;
+
+       uboot_end_data = .;
+       num_got_entries = (__got_end - __got_start) >> 2;
+
+       . = ALIGN(4);
+       .sbss  : { *(.sbss) }
+       .bss  : { *(.bss) }
+       uboot_end = .;
+}
diff --git a/package/boot/uboot-xburst/files/board/n516/u-boot.lds b/package/boot/uboot-xburst/files/board/n516/u-boot.lds
new file mode 100644 (file)
index 0000000..a15a96e
--- /dev/null
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2006
+ * Ingenic Semiconductor, <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
+
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+       . = 0x00000000;
+
+       . = ALIGN(4);
+       .text       :
+       {
+         *(.text)
+       }
+
+       . = ALIGN(4);
+       .rodata  : { *(.rodata) }
+
+       . = ALIGN(4);
+       .data  : { *(.data) }
+
+       . = ALIGN(4);
+       .sdata  : { *(.sdata) }
+
+       _gp = ALIGN(16);
+
+       __got_start = .;
+       .got  : { *(.got) }
+       __got_end = .;
+
+       .sdata  : { *(.sdata) }
+
+       __u_boot_cmd_start = .;
+       .u_boot_cmd : { *(.u_boot_cmd) }
+       __u_boot_cmd_end = .;
+
+       uboot_end_data = .;
+       num_got_entries = (__got_end - __got_start) >> 2;
+
+       . = ALIGN(4);
+       .sbss  : { *(.sbss) }
+       .bss  : { *(.bss) }
+       uboot_end = .;
+}
diff --git a/package/boot/uboot-xburst/files/board/nanonote/Makefile b/package/boot/uboot-xburst/files/board/nanonote/Makefile
new file mode 100644 (file)
index 0000000..2c726a7
--- /dev/null
@@ -0,0 +1,38 @@
+#
+# (C) Copyright 2006
+# Ingenic Semiconductor, <jlwei@ingenic.cn>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = lib$(BOARD).a
+
+OBJS   = $(BOARD).o
+SOBJS  =
+
+$(LIB):        .depend $(OBJS) $(SOBJS)
+       $(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend:       Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+               $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/package/boot/uboot-xburst/files/board/nanonote/config.mk b/package/boot/uboot-xburst/files/board/nanonote/config.mk
new file mode 100644 (file)
index 0000000..858e6a2
--- /dev/null
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2006 Qi Hardware, Inc.
+# Author: Xiangfu Liu <xiangfu.z@gmail.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Qi Hardware, Inc. Ben NanoNote (QI_LB60)
+#
+
+ifndef TEXT_BASE
+# ROM version
+# TEXT_BASE = 0x88000000
+
+# RAM version
+TEXT_BASE = 0x80100000
+endif
diff --git a/package/boot/uboot-xburst/files/board/nanonote/nanonote.c b/package/boot/uboot-xburst/files/board/nanonote/nanonote.c
new file mode 100644 (file)
index 0000000..96a3c7d
--- /dev/null
@@ -0,0 +1,123 @@
+/*
+ * Authors: Xiangfu Liu <xiangfu.z@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 3 of the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/mipsregs.h>
+#include <asm/jz4740.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void gpio_init(void)
+{
+       /*
+        * Initialize NAND Flash Pins
+        */
+       __gpio_as_nand();
+
+       /*
+        * Initialize SDRAM pins
+        */
+       __gpio_as_sdram_32bit();
+
+       /*
+        * Initialize LCD pins
+        */
+       __gpio_as_lcd_8bit();
+
+       /*
+        * Initialize MSC pins
+        */
+       __gpio_as_msc();
+
+       /*
+        * Initialize Other pins
+        */
+       unsigned int i;
+       for (i = 0; i < 7; i++){
+               __gpio_as_input(GPIO_KEYIN_BASE + i);
+               __gpio_enable_pull(GPIO_KEYIN_BASE + i);
+       }
+
+       for (i = 0; i < 8; i++) {
+               __gpio_as_output(GPIO_KEYOUT_BASE + i);
+               __gpio_clear_pin(GPIO_KEYOUT_BASE + i);
+       }
+
+       /*
+        * Initialize UART0 pins, in Ben NanoNote uart0 and keyin8 use the
+        * same gpio, init the gpio as uart0 cause a keyboard bug. so for
+        * end user we disable the uart0
+        */
+       if (__gpio_get_pin(GPIO_KEYIN_BASE + 2) == 0){
+               /* if pressed [S] */
+               printf("[S] pressed, enable UART0\n");
+               gd->boot_option = 5;
+               __gpio_as_uart0();
+       } else {
+               printf("[S] not pressed, disable UART0\n");
+               __gpio_as_input(GPIO_KEYIN_8);
+               __gpio_enable_pull(GPIO_KEYIN_8);
+       }
+
+       __gpio_as_output(GPIO_AUDIO_POP);
+       __gpio_set_pin(GPIO_AUDIO_POP);
+
+       __gpio_as_output(GPIO_LCD_CS);
+       __gpio_clear_pin(GPIO_LCD_CS);
+
+       __gpio_as_output(GPIO_AMP_EN);
+       __gpio_clear_pin(GPIO_AMP_EN);
+
+       __gpio_as_output(GPIO_SDPW_EN);
+       __gpio_disable_pull(GPIO_SDPW_EN);
+       __gpio_clear_pin(GPIO_SDPW_EN);
+
+       __gpio_as_input(GPIO_SD_DETECT);
+       __gpio_disable_pull(GPIO_SD_DETECT);
+
+       __gpio_as_input(GPIO_USB_DETECT);
+       __gpio_enable_pull(GPIO_USB_DETECT);
+
+       if (__gpio_get_pin(GPIO_KEYIN_BASE + 3) == 0) {
+               printf("[M] pressed, boot from sd card\n");
+               gd->boot_option = 1;
+       }
+}
+
+static void cpm_init(void)
+{
+       __cpm_stop_ipu();
+       __cpm_stop_cim();
+       __cpm_stop_i2c();
+       __cpm_stop_ssi();
+       __cpm_stop_uart1();
+       __cpm_stop_sadc();
+       __cpm_stop_uhc();
+       __cpm_stop_udc();
+       __cpm_stop_aic1();
+/*     __cpm_stop_aic2();*/
+}
+
+void board_early_init(void)
+{
+       gpio_init();
+       cpm_init();
+}
+
+/* U-Boot common routines */
+
+int checkboard (void)
+{
+
+       printf("Board: Qi LB60 (Ingenic XBurst Jz4740 SoC, Speed %d MHz)\n",
+              gd->cpu_clk/1000000);
+
+       return 0; /* success */
+}
diff --git a/package/boot/uboot-xburst/files/board/nanonote/u-boot-nand.lds b/package/boot/uboot-xburst/files/board/nanonote/u-boot-nand.lds
new file mode 100644 (file)
index 0000000..a15a96e
--- /dev/null
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2006
+ * Ingenic Semiconductor, <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
+
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+       . = 0x00000000;
+
+       . = ALIGN(4);
+       .text       :
+       {
+         *(.text)
+       }
+
+       . = ALIGN(4);
+       .rodata  : { *(.rodata) }
+
+       . = ALIGN(4);
+       .data  : { *(.data) }
+
+       . = ALIGN(4);
+       .sdata  : { *(.sdata) }
+
+       _gp = ALIGN(16);
+
+       __got_start = .;
+       .got  : { *(.got) }
+       __got_end = .;
+
+       .sdata  : { *(.sdata) }
+
+       __u_boot_cmd_start = .;
+       .u_boot_cmd : { *(.u_boot_cmd) }
+       __u_boot_cmd_end = .;
+
+       uboot_end_data = .;
+       num_got_entries = (__got_end - __got_start) >> 2;
+
+       . = ALIGN(4);
+       .sbss  : { *(.sbss) }
+       .bss  : { *(.bss) }
+       uboot_end = .;
+}
diff --git a/package/boot/uboot-xburst/files/board/nanonote/u-boot.lds b/package/boot/uboot-xburst/files/board/nanonote/u-boot.lds
new file mode 100644 (file)
index 0000000..a15a96e
--- /dev/null
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2006
+ * Ingenic Semiconductor, <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
+
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+       . = 0x00000000;
+
+       . = ALIGN(4);
+       .text       :
+       {
+         *(.text)
+       }
+
+       . = ALIGN(4);
+       .rodata  : { *(.rodata) }
+
+       . = ALIGN(4);
+       .data  : { *(.data) }
+
+       . = ALIGN(4);
+       .sdata  : { *(.sdata) }
+
+       _gp = ALIGN(16);
+
+       __got_start = .;
+       .got  : { *(.got) }
+       __got_end = .;
+
+       .sdata  : { *(.sdata) }
+
+       __u_boot_cmd_start = .;
+       .u_boot_cmd : { *(.u_boot_cmd) }
+       __u_boot_cmd_end = .;
+
+       uboot_end_data = .;
+       num_got_entries = (__got_end - __got_start) >> 2;
+
+       . = ALIGN(4);
+       .sbss  : { *(.sbss) }
+       .bss  : { *(.bss) }
+       uboot_end = .;
+}
diff --git a/package/boot/uboot-xburst/files/board/sakc/Makefile b/package/boot/uboot-xburst/files/board/sakc/Makefile
new file mode 100644 (file)
index 0000000..470447d
--- /dev/null
@@ -0,0 +1,38 @@
+#
+# (C) Copyright 2006
+# Ingenic Semiconductor, <jlwei@ingenic.cn>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = lib$(BOARD).a
+
+OBJS   = $(BOARD).o 
+SOBJS  = 
+
+$(LIB):        .depend $(OBJS) $(SOBJS)
+       $(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend:       Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+               $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/package/boot/uboot-xburst/files/board/sakc/config.mk b/package/boot/uboot-xburst/files/board/sakc/config.mk
new file mode 100644 (file)
index 0000000..b254958
--- /dev/null
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2006 Qi Hardware, Inc.
+# Author: Xiangfu Liu <xiangfu.z@gmail.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# SAKC Board
+#
+
+ifndef TEXT_BASE
+# ROM version
+# TEXT_BASE = 0x88000000
+
+# RAM version
+TEXT_BASE = 0x80100000
+endif
diff --git a/package/boot/uboot-xburst/files/board/sakc/sakc.c b/package/boot/uboot-xburst/files/board/sakc/sakc.c
new file mode 100644 (file)
index 0000000..85763c7
--- /dev/null
@@ -0,0 +1,94 @@
+/*
+ * Authors: Xiangfu Liu <xiangfu.z@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 3 of the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/mipsregs.h>
+#include <asm/jz4740.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void gpio_init(void)
+{
+       /*
+        * Initialize NAND Flash Pins
+        */
+       __gpio_as_nand();
+
+       /*
+        * Initialize SDRAM pins
+        */     
+       __gpio_as_sdram_16bit_4725();
+
+       /*
+        * Initialize UART0 pins
+        */
+       __gpio_as_uart0();
+
+       /*
+        * Initialize LCD pins
+        */
+       __gpio_as_lcd_18bit();
+
+       /*
+        * Initialize MSC pins
+        */
+       __gpio_as_msc();
+
+       /*
+        * Initialize SSI pins
+        */
+       __gpio_as_ssi();
+
+       /*
+        * Initialize I2C pins
+        */
+       __gpio_as_i2c();
+
+       /*
+        * Initialize MSC pins
+        */
+       __gpio_as_msc();
+
+       /*
+        * Initialize Other pins
+        */
+       __gpio_as_input(GPIO_SD_DETECT);
+       __gpio_disable_pull(GPIO_SD_DETECT);
+}
+/* TODO SAKC
+static void cpm_init(void)
+{
+       __cpm_stop_ipu();
+       __cpm_stop_cim();
+       __cpm_stop_i2c();
+       __cpm_stop_ssi();
+       __cpm_stop_uart1();
+       __cpm_stop_sadc();
+       __cpm_stop_uhc();
+       __cpm_stop_aic1();
+       __cpm_stop_aic2();
+}*/
+
+void board_early_init(void)
+{
+       gpio_init();
+       //cpm_init(); //TODO SAKC
+}
+
+/* U-Boot common routines */
+
+int checkboard (void)
+{
+
+       printf("Board: SAKC (Ingenic XBurst Jz4725 SoC, Speed %d MHz)\n",
+              gd->cpu_clk/1000000);
+
+       return 0; /* success */
+}
diff --git a/package/boot/uboot-xburst/files/board/sakc/u-boot-nand.lds b/package/boot/uboot-xburst/files/board/sakc/u-boot-nand.lds
new file mode 100644 (file)
index 0000000..a15a96e
--- /dev/null
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2006
+ * Ingenic Semiconductor, <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
+
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+       . = 0x00000000;
+
+       . = ALIGN(4);
+       .text       :
+       {
+         *(.text)
+       }
+
+       . = ALIGN(4);
+       .rodata  : { *(.rodata) }
+
+       . = ALIGN(4);
+       .data  : { *(.data) }
+
+       . = ALIGN(4);
+       .sdata  : { *(.sdata) }
+
+       _gp = ALIGN(16);
+
+       __got_start = .;
+       .got  : { *(.got) }
+       __got_end = .;
+
+       .sdata  : { *(.sdata) }
+
+       __u_boot_cmd_start = .;
+       .u_boot_cmd : { *(.u_boot_cmd) }
+       __u_boot_cmd_end = .;
+
+       uboot_end_data = .;
+       num_got_entries = (__got_end - __got_start) >> 2;
+
+       . = ALIGN(4);
+       .sbss  : { *(.sbss) }
+       .bss  : { *(.bss) }
+       uboot_end = .;
+}
diff --git a/package/boot/uboot-xburst/files/board/sakc/u-boot.lds b/package/boot/uboot-xburst/files/board/sakc/u-boot.lds
new file mode 100644 (file)
index 0000000..a15a96e
--- /dev/null
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2006
+ * Ingenic Semiconductor, <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
+
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+       . = 0x00000000;
+
+       . = ALIGN(4);
+       .text       :
+       {
+         *(.text)
+       }
+
+       . = ALIGN(4);
+       .rodata  : { *(.rodata) }
+
+       . = ALIGN(4);
+       .data  : { *(.data) }
+
+       . = ALIGN(4);
+       .sdata  : { *(.sdata) }
+
+       _gp = ALIGN(16);
+
+       __got_start = .;
+       .got  : { *(.got) }
+       __got_end = .;
+
+       .sdata  : { *(.sdata) }
+
+       __u_boot_cmd_start = .;
+       .u_boot_cmd : { *(.u_boot_cmd) }
+       __u_boot_cmd_end = .;
+
+       uboot_end_data = .;
+       num_got_entries = (__got_end - __got_start) >> 2;
+
+       . = ALIGN(4);
+       .sbss  : { *(.sbss) }
+       .bss  : { *(.bss) }
+       uboot_end = .;
+}
diff --git a/package/boot/uboot-xburst/files/cpu/mips/jz4740.c b/package/boot/uboot-xburst/files/cpu/mips/jz4740.c
new file mode 100644 (file)
index 0000000..5ae5797
--- /dev/null
@@ -0,0 +1,559 @@
+/*
+ * Jz4740 common routines
+ *
+ *  Copyright (c) 2006
+ *  Ingenic Semiconductor, <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the&n