ifxmips: move header files, split up patches, rename some files
authorJohn Crispin <john@openwrt.org>
Thu, 8 Oct 2009 22:24:49 +0000 (22:24 +0000)
committerJohn Crispin <john@openwrt.org>
Thu, 8 Oct 2009 22:24:49 +0000 (22:24 +0000)
SVN-Revision: 18010

51 files changed:
target/linux/ifxmips/files/arch/mips/ifxmips/Kconfig
target/linux/ifxmips/files/arch/mips/ifxmips/Makefile
target/linux/ifxmips/files/arch/mips/ifxmips/board.c
target/linux/ifxmips/files/arch/mips/ifxmips/clock.c
target/linux/ifxmips/files/arch/mips/ifxmips/dma-core.c
target/linux/ifxmips/files/arch/mips/ifxmips/gpio.c
target/linux/ifxmips/files/arch/mips/ifxmips/interrupt.c [deleted file]
target/linux/ifxmips/files/arch/mips/ifxmips/irq.c [new file with mode: 0644]
target/linux/ifxmips/files/arch/mips/ifxmips/pmu.c
target/linux/ifxmips/files/arch/mips/ifxmips/prom.c
target/linux/ifxmips/files/arch/mips/ifxmips/reset.c
target/linux/ifxmips/files/arch/mips/ifxmips/setup.c
target/linux/ifxmips/files/arch/mips/include/asm/ifxmips/ifxmips.h [deleted file]
target/linux/ifxmips/files/arch/mips/include/asm/ifxmips/ifxmips_dma.h [deleted file]
target/linux/ifxmips/files/arch/mips/include/asm/ifxmips/ifxmips_ebu.h [deleted file]
target/linux/ifxmips/files/arch/mips/include/asm/ifxmips/ifxmips_gpio.h [deleted file]
target/linux/ifxmips/files/arch/mips/include/asm/ifxmips/ifxmips_gptu.h [deleted file]
target/linux/ifxmips/files/arch/mips/include/asm/ifxmips/ifxmips_irq.h [deleted file]
target/linux/ifxmips/files/arch/mips/include/asm/ifxmips/ifxmips_led.h [deleted file]
target/linux/ifxmips/files/arch/mips/include/asm/ifxmips/ifxmips_pmu.h [deleted file]
target/linux/ifxmips/files/arch/mips/include/asm/ifxmips/ifxmips_prom.h [deleted file]
target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/cgu.h [deleted file]
target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/gpio.h
target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips.h [new file with mode: 0644]
target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_cgu.h [new file with mode: 0644]
target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_dma.h [new file with mode: 0644]
target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_ebu.h [new file with mode: 0644]
target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_gpio.h [new file with mode: 0644]
target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_gptu.h [new file with mode: 0644]
target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_irq.h [new file with mode: 0644]
target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_led.h [new file with mode: 0644]
target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_pmu.h [new file with mode: 0644]
target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_prom.h [new file with mode: 0644]
target/linux/ifxmips/files/arch/mips/pci/ops-ifxmips.c
target/linux/ifxmips/files/arch/mips/pci/pci-ifxmips.c
target/linux/ifxmips/files/drivers/leds/leds-ifxmips.c
target/linux/ifxmips/files/drivers/mtd/maps/ifxmips.c
target/linux/ifxmips/files/drivers/net/ifxmips_mii0.c
target/linux/ifxmips/files/drivers/serial/ifxmips_asc.c
target/linux/ifxmips/files/drivers/watchdog/ifxmips_wdt.c
target/linux/ifxmips/patches-2.6.30/100-board.patch
target/linux/ifxmips/patches-2.6.30/110-drivers.patch [deleted file]
target/linux/ifxmips/patches-2.6.30/110-pci.patch [new file with mode: 0644]
target/linux/ifxmips/patches-2.6.30/120-serial.patch [new file with mode: 0644]
target/linux/ifxmips/patches-2.6.30/130-ethernet.patch [new file with mode: 0644]
target/linux/ifxmips/patches-2.6.30/140-mtd.patch [new file with mode: 0644]
target/linux/ifxmips/patches-2.6.30/150-wdt.patch [new file with mode: 0644]
target/linux/ifxmips/patches-2.6.30/160-cfi-swap.patch [deleted file]
target/linux/ifxmips/patches-2.6.30/160-led.patch [new file with mode: 0644]
target/linux/ifxmips/patches-2.6.30/170-dma_hack.patch [deleted file]
target/linux/ifxmips/patches-2.6.30/300-cfi-swap.patch [new file with mode: 0644]

index 621020f..549ffe2 100644 (file)
@@ -6,18 +6,6 @@ config MTD_IFXMIPS
        bool "IFXMips flash map"
        default y
 
-config IFXMIPS_SSC
-       bool "IFXMips ssc"
-       default y
-
-config IFXMIPS_EEPROM
-       bool "IFXMips eeprom"
-       default y
-
-config IFXMIPS_MEI
-       bool "IFXMips mei"
-       default y
-
 config IFXMIPS_GPIO_RST_BTN
        bool "Reset Button"
        default y
index a2cc69d..9710645 100644 (file)
@@ -1 +1 @@
-obj-y := reset.o prom.o setup.o interrupt.o dma-core.o pmu.o board.o clock.o gpio.o
+obj-y := reset.o prom.o setup.o irq.o dma-core.o pmu.o board.o clock.o gpio.o
index 364d33b..7d77e9c 100644 (file)
 #include <linux/time.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
+
 #include <asm/bootinfo.h>
 #include <asm/irq.h>
-#include <asm/ifxmips/ifxmips.h>
-#include <asm/ifxmips/ifxmips_irq.h>
+
+#include <ifxmips.h>
+#include <ifxmips_irq.h>
 
 #define MAX_BOARD_NAME_LEN             32
 #define MAX_IFXMIPS_DEVS               9
index a8d1984..d951be8 100644 (file)
 #include <linux/init.h>
 #include <linux/uaccess.h>
 #include <linux/unistd.h>
+#include <linux/errno.h>
+
 #include <asm/irq.h>
 #include <asm/div64.h>
-#include <linux/errno.h>
-#include <asm/ifxmips/ifxmips.h>
-#include <asm/mach-ifxmips/cgu.h>
+
+#include <ifxmips.h>
+#include <ifxmips_cgu.h>
 
 static unsigned int cgu_get_pll0_fdiv(void);
 unsigned int ifxmips_clocks[] = {CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
index 5271e6b..084b283 100644 (file)
 #include <linux/errno.h>
 #include <linux/io.h>
 
-#include <asm/ifxmips/ifxmips.h>
-#include <asm/ifxmips/ifxmips_irq.h>
-#include <asm/ifxmips/ifxmips_dma.h>
-#include <asm/ifxmips/ifxmips_pmu.h>
+#include <ifxmips.h>
+#include <ifxmips_irq.h>
+#include <ifxmips_dma.h>
+#include <ifxmips_pmu.h>
 
 /*25 descriptors for each dma channel,4096/8/20=25.xx*/
 #define IFXMIPS_DMA_DESCRIPTOR_OFFSET 25
index 2100ebb..3ef5100 100644 (file)
 #include <linux/skbuff.h>
 #include <linux/netlink.h>
 #include <linux/platform_device.h>
-#include <net/sock.h>
 #include <linux/uaccess.h>
 #include <linux/semaphore.h>
-#include <asm/ifxmips/ifxmips.h>
+
+#include <net/sock.h>
+
+#include <ifxmips.h>
 
 #define MAX_PORTS                      2
 #define PINS_PER_PORT          16
diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/interrupt.c b/target/linux/ifxmips/files/arch/mips/ifxmips/interrupt.c
deleted file mode 100644 (file)
index 0552a13..0000000
+++ /dev/null
@@ -1,234 +0,0 @@
-/*
- *   This program is free software; you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation; either version 2 of the License, or
- *   (at your option) any later version.
- *
- *   This program is distributed in the hope that it will be useful,
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *   GNU General Public License for more details.
- *
- *   You should have received a copy of the GNU General Public License
- *   along with this program; if not, write to the Free Software
- *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- *   Copyright (C) 2005 Wu Qi Ming infineon
- *   Copyright (C) 2007 John Crispin <blogic@openwrt.org>
- */
-
-#include <linux/init.h>
-#include <linux/sched.h>
-#include <linux/slab.h>
-#include <linux/interrupt.h>
-#include <linux/kernel_stat.h>
-#include <linux/module.h>
-
-#include <asm/bootinfo.h>
-#include <asm/irq.h>
-#include <asm/ifxmips/ifxmips.h>
-#include <asm/ifxmips/ifxmips_irq.h>
-#include <asm/irq_cpu.h>
-
-void ifxmips_disable_irq(unsigned int irq_nr)
-{
-       int i;
-       u32 *ifxmips_ier = IFXMIPS_ICU_IM0_IER;
-
-       irq_nr -= INT_NUM_IRQ0;
-       for (i = 0; i <= 4; i++) {
-               if (irq_nr < INT_NUM_IM_OFFSET) {
-                       ifxmips_w32(ifxmips_r32(ifxmips_ier) & ~(1 << irq_nr),
-                               ifxmips_ier);
-                       return;
-               }
-               ifxmips_ier += IFXMIPS_ICU_OFFSET;
-               irq_nr -= INT_NUM_IM_OFFSET;
-       }
-}
-EXPORT_SYMBOL(ifxmips_disable_irq);
-
-void ifxmips_mask_and_ack_irq(unsigned int irq_nr)
-{
-       int i;
-       u32 *ifxmips_ier = IFXMIPS_ICU_IM0_IER;
-       u32 *ifxmips_isr = IFXMIPS_ICU_IM0_ISR;
-
-       irq_nr -= INT_NUM_IRQ0;
-       for (i = 0; i <= 4; i++) {
-               if (irq_nr < INT_NUM_IM_OFFSET) {
-                       ifxmips_w32(ifxmips_r32(ifxmips_ier) & ~(1 << irq_nr),
-                               ifxmips_ier);
-                       ifxmips_w32((1 << irq_nr), ifxmips_isr);
-                       return;
-               }
-               ifxmips_ier += IFXMIPS_ICU_OFFSET;
-               ifxmips_isr += IFXMIPS_ICU_OFFSET;
-               irq_nr -= INT_NUM_IM_OFFSET;
-       }
-}
-EXPORT_SYMBOL(ifxmips_mask_and_ack_irq);
-
-void ifxmips_enable_irq(unsigned int irq_nr)
-{
-       int i;
-       u32 *ifxmips_ier = IFXMIPS_ICU_IM0_IER;
-
-       irq_nr -= INT_NUM_IRQ0;
-       for (i = 0; i <= 4; i++) {
-               if (irq_nr < INT_NUM_IM_OFFSET) {
-                       ifxmips_w32(ifxmips_r32(ifxmips_ier) | (1 << irq_nr),
-                               ifxmips_ier);
-                       return;
-               }
-               ifxmips_ier += IFXMIPS_ICU_OFFSET;
-               irq_nr -= INT_NUM_IM_OFFSET;
-       }
-}
-EXPORT_SYMBOL(ifxmips_enable_irq);
-
-static unsigned int ifxmips_startup_irq(unsigned int irq)
-{
-       ifxmips_enable_irq(irq);
-       return 0;
-}
-
-static void ifxmips_end_irq(unsigned int irq)
-{
-       if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
-               ifxmips_enable_irq(irq);
-}
-
-static struct hw_interrupt_type ifxmips_irq_type = {
-       "IFXMIPS",
-       .startup = ifxmips_startup_irq,
-       .enable = ifxmips_enable_irq,
-       .disable = ifxmips_disable_irq,
-       .unmask = ifxmips_enable_irq,
-       .ack = ifxmips_end_irq,
-       .mask = ifxmips_disable_irq,
-       .mask_ack = ifxmips_mask_and_ack_irq,
-       .end = ifxmips_end_irq,
-};
-
-/* silicon bug causes only the msb set to 1 to be valid. all
-   other bits might be bogus */
-static inline int ls1bit32(unsigned long x)
-{
-       __asm__ (
-               ".set push \n"
-               ".set mips32 \n"
-               "clz %0, %1 \n"
-               ".set pop \n"
-               : "=r" (x)
-               : "r" (x));
-       return 31 - x;
-}
-
-void ifxmips_hw_irqdispatch(int module)
-{
-       u32 irq;
-
-       irq = ifxmips_r32(IFXMIPS_ICU_IM0_IOSR + (module * IFXMIPS_ICU_OFFSET));
-       if (irq == 0)
-               return;
-
-       /* we need to do this due to a silicon bug */
-       irq = ls1bit32(irq);
-       do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
-
-       if ((irq == 22) && (module == 0))
-               ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_ISTAT) | 0x10,
-                       IFXMIPS_EBU_PCC_ISTAT);
-}
-
-#ifdef CONFIG_CPU_MIPSR2_IRQ_VI
-#define DEFINE_HWx_IRQDISPATCH(x) \
-static void ifxmips_hw ## x ## _irqdispatch(void)\
-{\
-       ifxmips_hw_irqdispatch(x); \
-}
-static void ifxmips_hw5_irqdispatch(void)
-{
-       do_IRQ(MIPS_CPU_TIMER_IRQ);
-}
-DEFINE_HWx_IRQDISPATCH(0)
-DEFINE_HWx_IRQDISPATCH(1)
-DEFINE_HWx_IRQDISPATCH(2)
-DEFINE_HWx_IRQDISPATCH(3)
-DEFINE_HWx_IRQDISPATCH(4)
-/*DEFINE_HWx_IRQDISPATCH(5)*/
-#endif /* #ifdef CONFIG_CPU_MIPSR2_IRQ_VI */
-
-asmlinkage void plat_irq_dispatch(void)
-{
-       unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
-       unsigned int i;
-
-       if (pending & CAUSEF_IP7) {
-               do_IRQ(MIPS_CPU_TIMER_IRQ);
-               goto out;
-       } else {
-               for (i = 0; i < 5; i++) {
-                       if (pending & (CAUSEF_IP2 << i)) {
-                               ifxmips_hw_irqdispatch(i);
-                               goto out;
-                       }
-               }
-       }
-       printk(KERN_ALERT "Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
-
-out:
-       return;
-}
-
-static struct irqaction cascade = {
-       .handler = no_action,
-       .flags = IRQF_DISABLED,
-       .name = "cascade",
-};
-
-void __init arch_init_irq(void)
-{
-       int i;
-
-       for (i = 0; i < 5; i++)
-               ifxmips_w32(0, IFXMIPS_ICU_IM0_IER + (i * IFXMIPS_ICU_OFFSET));
-
-       mips_cpu_irq_init();
-
-       for (i = 2; i <= 6; i++)
-               setup_irq(i, &cascade);
-
-#ifdef CONFIG_CPU_MIPSR2_IRQ_VI
-       if (cpu_has_vint) {
-               printk(KERN_INFO "Setting up vectored interrupts\n");
-               set_vi_handler(2, ifxmips_hw0_irqdispatch);
-               set_vi_handler(3, ifxmips_hw1_irqdispatch);
-               set_vi_handler(4, ifxmips_hw2_irqdispatch);
-               set_vi_handler(5, ifxmips_hw3_irqdispatch);
-               set_vi_handler(6, ifxmips_hw4_irqdispatch);
-               set_vi_handler(7, ifxmips_hw5_irqdispatch);
-       }
-#endif /* CONFIG_CPU_MIPSR2_IRQ_VI */
-
-       for (i = INT_NUM_IRQ0; i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET));
-               i++)
-               set_irq_chip_and_handler(i, &ifxmips_irq_type,
-                       handle_level_irq);
-
-       #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
-       set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
-               IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
-       #else
-       set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
-               IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
-       #endif
-}
-
-void __cpuinit arch_fixup_c0_irqs(void)
-{
-       /* FIXME: check for CPUID and only do fix for specific chips/versions */
-       cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
-       cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ;
-}
diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/irq.c b/target/linux/ifxmips/files/arch/mips/ifxmips/irq.c
new file mode 100644 (file)
index 0000000..b7326c7
--- /dev/null
@@ -0,0 +1,235 @@
+/*
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   Copyright (C) 2005 Wu Qi Ming infineon
+ *   Copyright (C) 2007 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/kernel_stat.h>
+#include <linux/module.h>
+
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+#include <asm/irq_cpu.h>
+
+#include <ifxmips.h>
+#include <ifxmips_irq.h>
+
+void ifxmips_disable_irq(unsigned int irq_nr)
+{
+       int i;
+       u32 *ifxmips_ier = IFXMIPS_ICU_IM0_IER;
+
+       irq_nr -= INT_NUM_IRQ0;
+       for (i = 0; i <= 4; i++) {
+               if (irq_nr < INT_NUM_IM_OFFSET) {
+                       ifxmips_w32(ifxmips_r32(ifxmips_ier) & ~(1 << irq_nr),
+                               ifxmips_ier);
+                       return;
+               }
+               ifxmips_ier += IFXMIPS_ICU_OFFSET;
+               irq_nr -= INT_NUM_IM_OFFSET;
+       }
+}
+EXPORT_SYMBOL(ifxmips_disable_irq);
+
+void ifxmips_mask_and_ack_irq(unsigned int irq_nr)
+{
+       int i;
+       u32 *ifxmips_ier = IFXMIPS_ICU_IM0_IER;
+       u32 *ifxmips_isr = IFXMIPS_ICU_IM0_ISR;
+
+       irq_nr -= INT_NUM_IRQ0;
+       for (i = 0; i <= 4; i++) {
+               if (irq_nr < INT_NUM_IM_OFFSET) {
+                       ifxmips_w32(ifxmips_r32(ifxmips_ier) & ~(1 << irq_nr),
+                               ifxmips_ier);
+                       ifxmips_w32((1 << irq_nr), ifxmips_isr);
+                       return;
+               }
+               ifxmips_ier += IFXMIPS_ICU_OFFSET;
+               ifxmips_isr += IFXMIPS_ICU_OFFSET;
+               irq_nr -= INT_NUM_IM_OFFSET;
+       }
+}
+EXPORT_SYMBOL(ifxmips_mask_and_ack_irq);
+
+void ifxmips_enable_irq(unsigned int irq_nr)
+{
+       int i;
+       u32 *ifxmips_ier = IFXMIPS_ICU_IM0_IER;
+
+       irq_nr -= INT_NUM_IRQ0;
+       for (i = 0; i <= 4; i++) {
+               if (irq_nr < INT_NUM_IM_OFFSET) {
+                       ifxmips_w32(ifxmips_r32(ifxmips_ier) | (1 << irq_nr),
+                               ifxmips_ier);
+                       return;
+               }
+               ifxmips_ier += IFXMIPS_ICU_OFFSET;
+               irq_nr -= INT_NUM_IM_OFFSET;
+       }
+}
+EXPORT_SYMBOL(ifxmips_enable_irq);
+
+static unsigned int ifxmips_startup_irq(unsigned int irq)
+{
+       ifxmips_enable_irq(irq);
+       return 0;
+}
+
+static void ifxmips_end_irq(unsigned int irq)
+{
+       if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
+               ifxmips_enable_irq(irq);
+}
+
+static struct hw_interrupt_type ifxmips_irq_type = {
+       "IFXMIPS",
+       .startup = ifxmips_startup_irq,
+       .enable = ifxmips_enable_irq,
+       .disable = ifxmips_disable_irq,
+       .unmask = ifxmips_enable_irq,
+       .ack = ifxmips_end_irq,
+       .mask = ifxmips_disable_irq,
+       .mask_ack = ifxmips_mask_and_ack_irq,
+       .end = ifxmips_end_irq,
+};
+
+/* silicon bug causes only the msb set to 1 to be valid. all
+   other bits might be bogus */
+static inline int ls1bit32(unsigned long x)
+{
+       __asm__ (
+               ".set push \n"
+               ".set mips32 \n"
+               "clz %0, %1 \n"
+               ".set pop \n"
+               : "=r" (x)
+               : "r" (x));
+       return 31 - x;
+}
+
+void ifxmips_hw_irqdispatch(int module)
+{
+       u32 irq;
+
+       irq = ifxmips_r32(IFXMIPS_ICU_IM0_IOSR + (module * IFXMIPS_ICU_OFFSET));
+       if (irq == 0)
+               return;
+
+       /* we need to do this due to a silicon bug */
+       irq = ls1bit32(irq);
+       do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
+
+       if ((irq == 22) && (module == 0))
+               ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_ISTAT) | 0x10,
+                       IFXMIPS_EBU_PCC_ISTAT);
+}
+
+#ifdef CONFIG_CPU_MIPSR2_IRQ_VI
+#define DEFINE_HWx_IRQDISPATCH(x) \
+static void ifxmips_hw ## x ## _irqdispatch(void)\
+{\
+       ifxmips_hw_irqdispatch(x); \
+}
+static void ifxmips_hw5_irqdispatch(void)
+{
+       do_IRQ(MIPS_CPU_TIMER_IRQ);
+}
+DEFINE_HWx_IRQDISPATCH(0)
+DEFINE_HWx_IRQDISPATCH(1)
+DEFINE_HWx_IRQDISPATCH(2)
+DEFINE_HWx_IRQDISPATCH(3)
+DEFINE_HWx_IRQDISPATCH(4)
+/*DEFINE_HWx_IRQDISPATCH(5)*/
+#endif /* #ifdef CONFIG_CPU_MIPSR2_IRQ_VI */
+
+asmlinkage void plat_irq_dispatch(void)
+{
+       unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
+       unsigned int i;
+
+       if (pending & CAUSEF_IP7) {
+               do_IRQ(MIPS_CPU_TIMER_IRQ);
+               goto out;
+       } else {
+               for (i = 0; i < 5; i++) {
+                       if (pending & (CAUSEF_IP2 << i)) {
+                               ifxmips_hw_irqdispatch(i);
+                               goto out;
+                       }
+               }
+       }
+       printk(KERN_ALERT "Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
+
+out:
+       return;
+}
+
+static struct irqaction cascade = {
+       .handler = no_action,
+       .flags = IRQF_DISABLED,
+       .name = "cascade",
+};
+
+void __init arch_init_irq(void)
+{
+       int i;
+
+       for (i = 0; i < 5; i++)
+               ifxmips_w32(0, IFXMIPS_ICU_IM0_IER + (i * IFXMIPS_ICU_OFFSET));
+
+       mips_cpu_irq_init();
+
+       for (i = 2; i <= 6; i++)
+               setup_irq(i, &cascade);
+
+#ifdef CONFIG_CPU_MIPSR2_IRQ_VI
+       if (cpu_has_vint) {
+               printk(KERN_INFO "Setting up vectored interrupts\n");
+               set_vi_handler(2, ifxmips_hw0_irqdispatch);
+               set_vi_handler(3, ifxmips_hw1_irqdispatch);
+               set_vi_handler(4, ifxmips_hw2_irqdispatch);
+               set_vi_handler(5, ifxmips_hw3_irqdispatch);
+               set_vi_handler(6, ifxmips_hw4_irqdispatch);
+               set_vi_handler(7, ifxmips_hw5_irqdispatch);
+       }
+#endif /* CONFIG_CPU_MIPSR2_IRQ_VI */
+
+       for (i = INT_NUM_IRQ0; i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET));
+               i++)
+               set_irq_chip_and_handler(i, &ifxmips_irq_type,
+                       handle_level_irq);
+
+       #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
+       set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
+               IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
+       #else
+       set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
+               IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
+       #endif
+}
+
+void __cpuinit arch_fixup_c0_irqs(void)
+{
+       /* FIXME: check for CPUID and only do fix for specific chips/versions */
+       cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
+       cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ;
+}
index d78ed4d..29d7104 100644 (file)
@@ -22,7 +22,8 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/version.h>
-#include <asm/ifxmips/ifxmips.h>
+
+#include <ifxmips.h>
 
 void ifxmips_pmu_enable(unsigned int module)
 {
index 1a27f1a..ef5a68a 100644 (file)
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/bootmem.h>
+
 #include <asm/bootinfo.h>
-#include <asm/ifxmips/ifxmips.h>
+
+#include <ifxmips.h>
 
 static char buf[1024]; /* for prom_printf() */
 
index 0446b97..c3119bc 100644 (file)
 #include <linux/kernel.h>
 #include <linux/pm.h>
 #include <linux/io.h>
+
 #include <asm/reboot.h>
 #include <asm/system.h>
-#include <asm/ifxmips/ifxmips.h>
+#include <ifxmips.h>
 
 static void ifxmips_machine_restart(char *command)
 {
index 2ba0592..06fa2f0 100644 (file)
@@ -18,8 +18,6 @@
  */
 
 #include <linux/init.h>
-
-
 #include <linux/cpu.h>
 
 #include <asm/time.h>
 #include <asm/irq.h>
 #include <asm/bootinfo.h>
 
-#include <asm/ifxmips/ifxmips.h>
-#include <asm/ifxmips/ifxmips_irq.h>
-#include <asm/ifxmips/ifxmips_pmu.h>
-#include <asm/mach-ifxmips/cgu.h>
-#include <asm/ifxmips/ifxmips_prom.h>
+#include <ifxmips.h>
+#include <ifxmips_irq.h>
+#include <ifxmips_pmu.h>
+#include <ifxmips_cgu.h>
+#include <ifxmips_prom.h>
 
 static unsigned int r4k_offset;
 static unsigned int r4k_cur;
diff --git a/target/linux/ifxmips/files/arch/mips/include/asm/ifxmips/ifxmips.h b/target/linux/ifxmips/files/arch/mips/include/asm/ifxmips/ifxmips.h
deleted file mode 100644 (file)
index c8cf0ae..0000000
+++ /dev/null
@@ -1,516 +0,0 @@
-/*
- *   This program is free software; you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation; either version 2 of the License, or
- *   (at your option) any later version.
- *
- *   This program is distributed in the hope that it will be useful,
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *   GNU General Public License for more details.
- *
- *   You should have received a copy of the GNU General Public License
- *   along with this program; if not, write to the Free Software
- *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- *   Copyright (C) 2005 infineon
- *   Copyright (C) 2007 John Crispin <blogic@openwrt.org>
- */
-#ifndef _IFXMIPS_H__
-#define _IFXMIPS_H__
-
-#define ifxmips_r32(reg)                       __raw_readl(reg)
-#define ifxmips_w32(val, reg)                  __raw_writel(val, reg)
-#define ifxmips_w32_mask(clear, set, reg)      ifxmips_w32((ifxmips_r32(reg) & ~clear) | set, reg)
-
-/*------------ GENERAL */
-
-#define BOARD_SYSTEM_TYPE              "IFXMIPS"
-
-#define IOPORT_RESOURCE_START          0x10000000
-#define IOPORT_RESOURCE_END            0xffffffff
-#define IOMEM_RESOURCE_START           0x10000000
-#define IOMEM_RESOURCE_END             0xffffffff
-
-#define IFXMIPS_FLASH_START            0x10000000
-#define IFXMIPS_FLASH_MAX              0x02000000
-
-/*------------ ASC0/1 */
-
-#define IFXMIPS_ASC_BASE_ADDR          (KSEG1 + 0x1E100400)
-#define IFXMIPS_ASC_BASE_DIFF          (0x1E100C00 - 0x1E100400)
-
-#define IFXMIPS_ASC_FSTAT              0x0048
-#define IFXMIPS_ASC_TBUF               0x0020
-#define IFXMIPS_ASC_WHBSTATE           0x0018
-#define IFXMIPS_ASC_RBUF               0x0024
-#define IFXMIPS_ASC_STATE              0x0014
-#define IFXMIPS_ASC_IRNCR              0x00F8
-#define IFXMIPS_ASC_CLC                        0x0000
-#define IFXMIPS_ASC_PISEL              0x0004
-#define IFXMIPS_ASC_TXFCON             0x0044
-#define IFXMIPS_ASC_RXFCON             0x0040
-#define IFXMIPS_ASC_CON                        0x0010
-#define IFXMIPS_ASC_BG                 0x0050
-#define IFXMIPS_ASC_IRNREN             0x00F4
-
-#define IFXMIPS_ASC_CLC_DISS           0x2
-#define ASC_IRNREN_RX_BUF              0x8
-#define ASC_IRNREN_TX_BUF              0x4
-#define ASC_IRNREN_ERR                 0x2
-#define ASC_IRNREN_TX                  0x1
-#define ASC_IRNCR_TIR                  0x4
-#define ASC_IRNCR_RIR                  0x2
-#define ASC_IRNCR_EIR                  0x4
-#define ASCOPT_CSIZE                   0x3
-#define ASCOPT_CS7                     0x1
-#define ASCOPT_CS8                     0x2
-#define ASCOPT_PARENB                  0x4
-#define ASCOPT_STOPB                   0x8
-#define ASCOPT_PARODD                  0x0
-#define ASCOPT_CREAD                   0x20
-#define TXFIFO_FL                      1
-#define RXFIFO_FL                      1
-#define TXFIFO_FULL                    16
-#define ASCCLC_RMCMASK                 0x0000FF00
-#define ASCCLC_RMCOFFSET               8
-#define ASCCON_M_8ASYNC                        0x0
-#define ASCCON_M_7ASYNC                        0x2
-#define ASCCON_ODD                     0x00000020
-#define ASCCON_STP                     0x00000080
-#define ASCCON_BRS                     0x00000100
-#define ASCCON_FDE                     0x00000200
-#define ASCCON_R                       0x00008000
-#define ASCCON_FEN                     0x00020000
-#define ASCCON_ROEN                    0x00080000
-#define ASCCON_TOEN                    0x00100000
-#define ASCSTATE_PE                    0x00010000
-#define ASCSTATE_FE                    0x00020000
-#define ASCSTATE_ROE                   0x00080000
-#define ASCSTATE_ANY                   (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
-#define ASCWHBSTATE_CLRREN             0x00000001
-#define ASCWHBSTATE_SETREN             0x00000002
-#define ASCWHBSTATE_CLRPE              0x00000004
-#define ASCWHBSTATE_CLRFE              0x00000008
-#define ASCWHBSTATE_CLRROE             0x00000020
-#define ASCTXFCON_TXFEN                        0x0001
-#define ASCTXFCON_TXFFLU               0x0002
-#define ASCTXFCON_TXFITLMASK           0x3F00
-#define ASCTXFCON_TXFITLOFF            8
-#define ASCRXFCON_RXFEN                        0x0001
-#define ASCRXFCON_RXFFLU               0x0002
-#define ASCRXFCON_RXFITLMASK           0x3F00
-#define ASCRXFCON_RXFITLOFF            8
-#define ASCFSTAT_RXFFLMASK             0x003F
-#define ASCFSTAT_TXFFLMASK             0x3F00
-#define ASCFSTAT_TXFFLOFF              8
-
-
-
-/*------------ RCU */
-#define IFXMIPS_RCU_BASE_ADDR          0xBF203000
-
-/* reset request */
-#define IFXMIPS_RCU_RST                        ((u32 *)(IFXMIPS_RCU_BASE_ADDR + 0x0010))
-#define IFXMIPS_RCU_RST_CPU1           (1 << 3)
-#define IFXMIPS_RCU_RST_ALL            0x40000000
-
-#define IFXMIPS_RCU_RST_REQ_DFE                (1 << 7)
-#define IFXMIPS_RCU_RST_REQ_AFE                (1 << 11)
-#define IFXMIPS_RCU_RST_REQ_ARC_JTAG   (1 << 20)
-
-
-/*------------ GPTU */
-
-#define IFXMIPS_GPTU_BASE_ADDR         0xB8000300
-
-/* clock control register */
-#define IFXMIPS_GPTU_GPT_CLC           ((u32 *)(IFXMIPS_GPTU_BASE_ADDR + 0x0000))
-
-/* captur reload register */
-#define IFXMIPS_GPTU_GPT_CAPREL                ((u32 *)(IFXMIPS_GPTU_BASE_ADDR + 0x0030))
-
-/* timer 6 control register */
-#define IFXMIPS_GPTU_GPT_T6CON         ((u32 *)(IFXMIPS_GPTU_BASE_ADDR + 0x0020))
-
-
-/*------------ EBU */
-
-#define IFXMIPS_EBU_BASE_ADDR          0xBE105300
-
-/* bus configuration register */
-#define IFXMIPS_EBU_BUSCON0            ((u32 *)(IFXMIPS_EBU_BASE_ADDR + 0x0060))
-#define IFXMIPS_EBU_PCC_CON            ((u32 *)(IFXMIPS_EBU_BASE_ADDR + 0x0090))
-#define IFXMIPS_EBU_PCC_IEN            ((u32 *)(IFXMIPS_EBU_BASE_ADDR + 0x00A4))
-#define IFXMIPS_EBU_PCC_ISTAT          ((u32 *)(IFXMIPS_EBU_BASE_ADDR + 0x00A0))
-
-
-/*------------ CGU */
-#define IFXMIPS_CGU_BASE_ADDR          (KSEG1 + 0x1F103000)
-#define IFXMIPS_CGU_PLL0_CFG           ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0004))
-#define IFXMIPS_CGU_PLL1_CFG           ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0008))
-#define IFXMIPS_CGU_PLL2_CFG           ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x000C))
-#define IFXMIPS_CGU_SYS                        ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0010))
-#define IFXMIPS_CGU_UPDATE             ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0014))
-#define IFXMIPS_CGU_IF_CLK             ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0018))
-#define IFXMIPS_CGU_OSC_CON            ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x001C))
-#define IFXMIPS_CGU_SMD                        ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0020))
-#define IFXMIPS_CGU_CT1SR              ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0028))
-#define IFXMIPS_CGU_CT2SR              ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x002C))
-#define IFXMIPS_CGU_PCMCR              ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0030))
-#define IFXMIPS_CGU_PCI_CR             ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0034))
-#define IFXMIPS_CGU_PD_PC              ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0038))
-#define IFXMIPS_CGU_FMR                        ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x003C))
-
-/* clock mux */
-#define IFXMIPS_CGU_SYS                        ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0010))
-#define IFXMIPS_CGU_IFCCR              ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0018))
-#define IFXMIPS_CGU_PCICR              ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0034))
-
-#define CLOCK_60M                      60000000
-#define CLOCK_83M                      83333333
-#define CLOCK_111M                     111111111
-#define CLOCK_133M                     133333333
-#define CLOCK_167M                     166666667
-#define CLOCK_333M                     333333333
-
-
-/*------------ CGU */
-
-#define IFXMIPS_PMU_BASE_ADDR          (KSEG1 + 0x1F102000)
-
-#define IFXMIPS_PMU_PWDCR              ((u32 *)(IFXMIPS_PMU_BASE_ADDR + 0x001C))
-#define IFXMIPS_PMU_PWDSR              ((u32 *)(IFXMIPS_PMU_BASE_ADDR + 0x0020))
-
-
-/*------------ ICU */
-
-#define IFXMIPS_ICU_BASE_ADDR          0xBF880200
-
-
-#define IFXMIPS_ICU_IM0_ISR            ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0000))
-#define IFXMIPS_ICU_IM0_IER            ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0008))
-#define IFXMIPS_ICU_IM0_IOSR           ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0010))
-#define IFXMIPS_ICU_IM0_IRSR           ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0018))
-#define IFXMIPS_ICU_IM0_IMR            ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0020))
-
-#define IFXMIPS_ICU_IM1_ISR            ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0028))
-#define IFXMIPS_ICU_IM2_IER            ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0058))
-#define IFXMIPS_ICU_IM3_IER            ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0080))
-#define IFXMIPS_ICU_IM4_IER            ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x00A8))
-#define IFXMIPS_ICU_IM5_IER            ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x00D0))
-
-#define IFXMIPS_ICU_OFFSET             (IFXMIPS_ICU_IM1_ISR - IFXMIPS_ICU_IM0_ISR)
-
-
-/*------------ ETOP */
-
-#define IFXMIPS_PPE32_BASE_ADDR                0xBE180000
-
-#define ETHERNET_PACKET_DMA_BUFFER_SIZE                0x600
-
-#define IFXMIPS_PPE32_MEM_MAP          ((u32 *)(IFXMIPS_PPE32_BASE_ADDR + 0x10000))
-#define IFXMIPS_PPE32_SRST             ((u32 *)(IFXMIPS_PPE32_BASE_ADDR + 0x10080))
-
-#define MII_MODE                       1
-#define REV_MII_MODE                   2
-
-/* mdio access */
-#define IFXMIPS_PPE32_MDIO_CFG         ((u32 *)(IFXMIPS_PPE32_BASE_ADDR + 0x11800))
-#define IFXMIPS_PPE32_MDIO_ACC         ((u32 *)(IFXMIPS_PPE32_BASE_ADDR + 0x11804))
-
-#define MDIO_ACC_REQUEST               0x80000000
-#define MDIO_ACC_READ                  0x40000000
-#define MDIO_ACC_ADDR_MASK             0x1f
-#define MDIO_ACC_ADDR_OFFSET           0x15
-#define MDIO_ACC_REG_MASK              0xff
-#define MDIO_ACC_REG_OFFSET            0x10
-#define MDIO_ACC_VAL_MASK              0xffff
-
-/* configuration */
-#define IFXMIPS_PPE32_CFG              ((u32 *)(IFXMIPS_PPE32_MEM_MAP + 0x1808))
-
-#define PPE32_MII_MASK                 0xfffffffc
-#define PPE32_MII_NORMAL               0x8
-#define PPE32_MII_REVERSE              0xe
-
-/* packet length */
-#define IFXMIPS_PPE32_IG_PLEN_CTRL     ((u32 *)(IFXMIPS_PPE32_MEM_MAP + 0x1820))
-
-#define PPE32_PLEN_OVER                        0x5ee
-#define PPE32_PLEN_UNDER               0x400000
-
-/* enet */
-#define IFXMIPS_PPE32_ENET_MAC_CFG     ((u32 *)(IFXMIPS_PPE32_MEM_MAP + 0x1840))
-
-#define PPE32_CGEN                     0x800
-
-
-/*------------ DMA */
-#define IFXMIPS_DMA_BASE_ADDR  0xBE104100
-
-#define IFXMIPS_DMA_CS                 ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x18))
-#define IFXMIPS_DMA_CIE                        ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x2C))
-#define IFXMIPS_DMA_IRNEN              ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0xf4))
-#define IFXMIPS_DMA_CCTRL              ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x1C))
-#define IFXMIPS_DMA_CIS                        ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x28))
-#define IFXMIPS_DMA_CDLEN              ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x24))
-#define IFXMIPS_DMA_PS                 ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x40))
-#define IFXMIPS_DMA_PCTRL              ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x44))
-#define IFXMIPS_DMA_CTRL               ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x10))
-#define IFXMIPS_DMA_CPOLL              ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x14))
-#define IFXMIPS_DMA_CDBA               ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x20))
-
-
-/*------------ PCI */
-#define PCI_CR_PR_BASE_ADDR            (KSEG1 + 0x1E105400)
-
-#define PCI_CR_FCI_ADDR_MAP0           ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00C0))
-#define PCI_CR_FCI_ADDR_MAP1           ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00C4))
-#define PCI_CR_FCI_ADDR_MAP2           ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00C8))
-#define PCI_CR_FCI_ADDR_MAP3           ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00CC))
-#define PCI_CR_FCI_ADDR_MAP4           ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D0))
-#define PCI_CR_FCI_ADDR_MAP5           ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D4))
-#define PCI_CR_FCI_ADDR_MAP6           ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D8))
-#define PCI_CR_FCI_ADDR_MAP7           ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00DC))
-#define PCI_CR_CLK_CTRL                        ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0000))
-#define PCI_CR_PCI_MOD                 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0030))
-#define PCI_CR_PC_ARB                  ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0080))
-#define PCI_CR_FCI_ADDR_MAP11hg                ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00E4))
-#define PCI_CR_BAR11MASK               ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0044))
-#define PCI_CR_BAR12MASK               ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0048))
-#define PCI_CR_BAR13MASK               ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x004C))
-#define PCI_CS_BASE_ADDR1              ((u32 *)(PCI_CS_PR_BASE_ADDR + 0x0010))
-#define PCI_CR_PCI_ADDR_MAP11          ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0064))
-#define PCI_CR_FCI_BURST_LENGTH                ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00E8))
-#define PCI_CR_PCI_EOI                 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x002C))
-
-#define PCI_CS_PR_BASE_ADDR            (KSEG1 + 0x17000000)
-
-#define PCI_CS_STS_CMD                 ((u32 *)(PCI_CS_PR_BASE_ADDR + 0x0004))
-
-#define PCI_MASTER0_REQ_MASK_2BITS     8
-#define PCI_MASTER1_REQ_MASK_2BITS     10
-#define PCI_MASTER2_REQ_MASK_2BITS     12
-#define INTERNAL_ARB_ENABLE_BIT                0
-
-
-/*------------ WDT */
-
-#define IFXMIPS_WDT_BASE_ADDR          (KSEG1 + 0x1F880000)
-
-#define IFXMIPS_BIU_WDT_CR             ((u32 *)(IFXMIPS_WDT_BASE_ADDR + 0x03F0))
-#define IFXMIPS_BIU_WDT_SR             ((u32 *)(IFXMIPS_WDT_BASE_ADDR + 0x03F8))
-
-
-/*------------ LED */
-
-#define IFXMIPS_LED_BASE_ADDR          (KSEG1 + 0x1E100BB0)
-#define IFXMIPS_LED_CON0               ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x0000))
-#define IFXMIPS_LED_CON1               ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x0004))
-#define IFXMIPS_LED_CPU0               ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x0008))
-#define IFXMIPS_LED_CPU1               ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x000C))
-#define IFXMIPS_LED_AR                 ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x0010))
-
-#define LED_CON0_SWU                   (1 << 31)
-#define LED_CON0_AD1                   (1 << 25)
-#define LED_CON0_AD0                   (1 << 24)
-
-#define IFXMIPS_LED_2HZ                        (0)
-#define IFXMIPS_LED_4HZ                        (1 << 23)
-#define IFXMIPS_LED_8HZ                        (2 << 23)
-#define IFXMIPS_LED_10HZ               (3 << 23)
-#define IFXMIPS_LED_MASK               (0xf << 23)
-
-#define IFXMIPS_LED_UPD_SRC_FPI        (1 << 31)
-#define IFXMIPS_LED_UPD_MASK           (3 << 30)
-#define IFXMIPS_LED_ADSL_SRC           (3 << 24)
-
-#define IFXMIPS_LED_GROUP0             (1 << 0)
-#define IFXMIPS_LED_GROUP1             (1 << 1)
-#define IFXMIPS_LED_GROUP2             (1 << 2)
-
-#define IFXMIPS_LED_RISING             0
-#define IFXMIPS_LED_FALLING            (1 << 26)
-#define IFXMIPS_LED_EDGE_MASK          (1 << 26)
-
-
-/*------------ GPIO */
-
-#define IFXMIPS_GPIO_BASE_ADDR (0xBE100B00)
-
-#define IFXMIPS_GPIO_P0_OUT            ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0010))
-#define IFXMIPS_GPIO_P1_OUT            ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0040))
-#define IFXMIPS_GPIO_P0_IN             ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0014))
-#define IFXMIPS_GPIO_P1_IN             ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0044))
-#define IFXMIPS_GPIO_P0_DIR            ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0018))
-#define IFXMIPS_GPIO_P1_DIR            ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0048))
-#define IFXMIPS_GPIO_P0_ALTSEL0                ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x001C))
-#define IFXMIPS_GPIO_P1_ALTSEL0                ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x004C))
-#define IFXMIPS_GPIO_P0_ALTSEL1                ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0020))
-#define IFXMIPS_GPIO_P1_ALTSEL1                ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0050))
-#define IFXMIPS_GPIO_P0_OD             ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0024))
-#define IFXMIPS_GPIO_P1_OD             ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0054))
-#define IFXMIPS_GPIO_P0_STOFF          ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0028))
-#define IFXMIPS_GPIO_P1_STOFF          ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0058))
-#define IFXMIPS_GPIO_P0_PUDSEL         ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x002C))
-#define IFXMIPS_GPIO_P1_PUDSEL         ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x005C))
-#define IFXMIPS_GPIO_P0_PUDEN          ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0030))
-#define IFXMIPS_GPIO_P1_PUDEN          ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0060))
-
-
-/*------------ SSC */
-
-#define IFXMIPS_SSC_BASE_ADDR          (KSEG1 + 0x1e100800)
-
-
-#define IFXMIPS_SSC_CLC                        ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0000))
-#define IFXMIPS_SSC_IRN                        ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x00F4))
-#define IFXMIPS_SSC_SFCON              ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0060))
-#define IFXMIPS_SSC_WHBGPOSTAT         ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0078))
-#define IFXMIPS_SSC_STATE              ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0014))
-#define IFXMIPS_SSC_WHBSTATE           ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0018))
-#define IFXMIPS_SSC_FSTAT              ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0038))
-#define IFXMIPS_SSC_ID                 ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0008))
-#define IFXMIPS_SSC_TB                 ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0020))
-#define IFXMIPS_SSC_RXFCON             ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0030))
-#define IFXMIPS_SSC_TXFCON             ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0034))
-#define IFXMIPS_SSC_CON                        ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0010))
-#define IFXMIPS_SSC_GPOSTAT            ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0074))
-#define IFXMIPS_SSC_RB                 ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0024))
-#define IFXMIPS_SSC_RXCNT              ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0084))
-#define IFXMIPS_SSC_GPOCON             ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0070))
-#define IFXMIPS_SSC_BR                 ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0040))
-#define IFXMIPS_SSC_RXREQ              ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0080))
-#define IFXMIPS_SSC_SFSTAT             ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0064))
-#define IFXMIPS_SSC_RXCNT              ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0084))
-
-
-/*------------ MEI */
-
-#define IFXMIPS_MEI_BASE_ADDR          (KSEG1 + 0x1E116000)
-
-#define MEI_DATA_XFR                   ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0000))
-#define MEI_VERSION                    ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0004))
-#define MEI_ARC_GP_STAT                        ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0008))
-#define MEI_DATA_XFR_STAT              ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x000C))
-#define MEI_XFR_ADDR                   ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0010))
-#define MEI_MAX_WAIT                   ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0014))
-#define MEI_TO_ARC_INT                 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0018))
-#define ARC_TO_MEI_INT                 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x001C))
-#define ARC_TO_MEI_INT_MASK            ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0020))
-#define MEI_DEBUG_WAD                  ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0024))
-#define MEI_DEBUG_RAD                  ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0028))
-#define MEI_DEBUG_DATA                 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x002C))
-#define MEI_DEBUG_DEC                  ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0030))
-#define MEI_CONFIG                     ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0034))
-#define MEI_RST_CONTROL                        ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0038))
-#define MEI_DBG_MASTER                 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x003C))
-#define MEI_CLK_CONTROL                        ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0040))
-#define MEI_BIST_CONTROL               ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0044))
-#define MEI_BIST_STAT                  ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0048))
-#define MEI_XDATA_BASE_SH              ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x004c))
-#define MEI_XDATA_BASE                 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0050))
-#define MEI_XMEM_BAR_BASE              ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0054))
-#define MEI_XMEM_BAR0                  ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0054))
-#define MEI_XMEM_BAR1                  ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0058))
-#define MEI_XMEM_BAR2                  ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x005C))
-#define MEI_XMEM_BAR3                  ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0060))
-#define MEI_XMEM_BAR4                  ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0064))
-#define MEI_XMEM_BAR5                  ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0068))
-#define MEI_XMEM_BAR6                  ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x006C))
-#define MEI_XMEM_BAR7                  ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0070))
-#define MEI_XMEM_BAR8                  ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0074))
-#define MEI_XMEM_BAR9                  ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0078))
-#define MEI_XMEM_BAR10                 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x007C))
-#define MEI_XMEM_BAR11                 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0080))
-#define MEI_XMEM_BAR12                 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0084))
-#define MEI_XMEM_BAR13                 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0088))
-#define MEI_XMEM_BAR14                 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x008C))
-#define MEI_XMEM_BAR15                 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0090))
-#define MEI_XMEM_BAR16                 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0094))
-
-
-/*------------ DEU */
-
-#define IFXMIPS_DEU_BASE               (KSEG1 + 0x1E103100)
-#define IFXMIPS_DEU_CLK                        ((u32 *)(IFXMIPS_DEU_BASE + 0x0000))
-#define IFXMIPS_DEU_ID                 ((u32 *)(IFXMIPS_DEU_BASE + 0x0008))
-
-#define IFXMIPS_DES_CON                        ((u32 *)(IFXMIPS_DEU_BASE + 0x0010))
-#define IFXMIPS_DES_IHR                        ((u32 *)(IFXMIPS_DEU_BASE + 0x0014))
-#define IFXMIPS_DES_ILR                        ((u32 *)(IFXMIPS_DEU_BASE + 0x0018))
-#define IFXMIPS_DES_K1HR               ((u32 *)(IFXMIPS_DEU_BASE + 0x001C))
-#define IFXMIPS_DES_K1LR               ((u32 *)(IFXMIPS_DEU_BASE + 0x0020))
-#define IFXMIPS_DES_K3HR               ((u32 *)(IFXMIPS_DEU_BASE + 0x0024))
-#define IFXMIPS_DES_K3LR               ((u32 *)(IFXMIPS_DEU_BASE + 0x0028))
-#define IFXMIPS_DES_IVHR               ((u32 *)(IFXMIPS_DEU_BASE + 0x002C))
-#define IFXMIPS_DES_IVLR               ((u32 *)(IFXMIPS_DEU_BASE + 0x0030))
-#define IFXMIPS_DES_OHR                        ((u32 *)(IFXMIPS_DEU_BASE + 0x0040))
-#define IFXMIPS_DES_OLR                        ((u32 *)(IFXMIPS_DEU_BASE + 0x0050))
-#define IFXMIPS_AES_CON                        ((u32 *)(IFXMIPS_DEU_BASE + 0x0050))
-#define IFXMIPS_AES_ID3R               ((u32 *)(IFXMIPS_DEU_BASE + 0x0054))
-#define IFXMIPS_AES_ID2R               ((u32 *)(IFXMIPS_DEU_BASE + 0x0058))
-#define IFXMIPS_AES_ID1R               ((u32 *)(IFXMIPS_DEU_BASE + 0x005C))
-#define IFXMIPS_AES_ID0R               ((u32 *)(IFXMIPS_DEU_BASE + 0x0060))
-#define IFXMIPS_AES_K7R                        ((u32 *)(IFXMIPS_DEU_BASE + 0x0064))
-#define IFXMIPS_AES_K6R                        ((u32 *)(IFXMIPS_DEU_BASE + 0x0068))
-#define IFXMIPS_AES_K5R                        ((u32 *)(IFXMIPS_DEU_BASE + 0x006C))
-#define IFXMIPS_AES_K4R                        ((u32 *)(IFXMIPS_DEU_BASE + 0x0070))
-#define IFXMIPS_AES_K3R                        ((u32 *)(IFXMIPS_DEU_BASE + 0x0074))
-#define IFXMIPS_AES_K2R                        ((u32 *)(IFXMIPS_DEU_BASE + 0x0078))
-#define IFXMIPS_AES_K1R                        ((u32 *)(IFXMIPS_DEU_BASE + 0x007C))
-#define IFXMIPS_AES_K0R                        ((u32 *)(IFXMIPS_DEU_BASE + 0x0080))
-#define IFXMIPS_AES_IV3R               ((u32 *)(IFXMIPS_DEU_BASE + 0x0084))
-#define IFXMIPS_AES_IV2R               ((u32 *)(IFXMIPS_DEU_BASE + 0x0088))
-#define IFXMIPS_AES_IV1R               ((u32 *)(IFXMIPS_DEU_BASE + 0x008C))
-#define IFXMIPS_AES_IV0R               ((u32 *)(IFXMIPS_DEU_BASE + 0x0090))
-#define IFXMIPS_AES_0D3R               ((u32 *)(IFXMIPS_DEU_BASE + 0x0094))
-#define IFXMIPS_AES_0D2R               ((u32 *)(IFXMIPS_DEU_BASE + 0x0098))
-#define IFXMIPS_AES_OD1R               ((u32 *)(IFXMIPS_DEU_BASE + 0x009C))
-#define IFXMIPS_AES_OD0R               ((u32 *)(IFXMIPS_DEU_BASE + 0x00A0))
-
-/*------------ FUSE */
-
-#define IFXMIPS_FUSE_BASE_ADDR         (KSEG1 + 0x1F107354)
-
-
-/*------------ MPS */
-
-#define IFXMIPS_MPS_BASE_ADDR          (KSEG1 + 0x1F107000)
-#define IFXMIPS_MPS_SRAM               ((u32 *)(KSEG1 + 0x1F200000))
-
-#define IFXMIPS_MPS_CHIPID             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0344))
-#define IFXMIPS_MPS_VC0ENR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0000))
-#define IFXMIPS_MPS_VC1ENR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0004))
-#define IFXMIPS_MPS_VC2ENR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0008))
-#define IFXMIPS_MPS_VC3ENR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x000C))
-#define IFXMIPS_MPS_RVC0SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0010))
-#define IFXMIPS_MPS_RVC1SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0014))
-#define IFXMIPS_MPS_RVC2SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0018))
-#define IFXMIPS_MPS_RVC3SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x001C))
-#define IFXMIPS_MPS_SVC0SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0020))
-#define IFXMIPS_MPS_SVC1SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0024))
-#define IFXMIPS_MPS_SVC2SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0028))
-#define IFXMIPS_MPS_SVC3SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x002C))
-#define IFXMIPS_MPS_CVC0SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0030))
-#define IFXMIPS_MPS_CVC1SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0034))
-#define IFXMIPS_MPS_CVC2SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0038))
-#define IFXMIPS_MPS_CVC3SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x003C))
-#define IFXMIPS_MPS_RAD0SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0040))
-#define IFXMIPS_MPS_RAD1SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0044))
-#define IFXMIPS_MPS_SAD0SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0048))
-#define IFXMIPS_MPS_SAD1SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x004C))
-#define IFXMIPS_MPS_CAD0SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0050))
-#define IFXMIPS_MPS_CAD1SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0054))
-#define IFXMIPS_MPS_AD0ENR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0058))
-#define IFXMIPS_MPS_AD1ENR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x005C))
-
-#define IFXMIPS_MPS_CHIPID_VERSION_GET(value)  (((value) >> 28) & ((1 << 4) - 1))
-#define IFXMIPS_MPS_CHIPID_VERSION_SET(value)  ((((1 << 4) - 1) & (value)) << 28)
-#define IFXMIPS_MPS_CHIPID_PARTNUM_GET(value)  (((value) >> 12) & ((1 << 16) - 1))
-#define IFXMIPS_MPS_CHIPID_PARTNUM_SET(value)  ((((1 << 16) - 1) & (value)) << 12)
-#define IFXMIPS_MPS_CHIPID_MANID_GET(value)    (((value) >> 1) & ((1 << 10) - 1))
-#define IFXMIPS_MPS_CHIPID_MANID_SET(value)    ((((1 << 10) - 1) & (value)) << 1)
-
-#endif
diff --git a/target/linux/ifxmips/files/arch/mips/include/asm/ifxmips/ifxmips_dma.h b/target/linux/ifxmips/files/arch/mips/include/asm/ifxmips/ifxmips_dma.h
deleted file mode 100644 (file)
index 8ba852a..0000000
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- *   This program is free software; you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation; either version 2 of the License, or
- *   (at your option) any later version.
- *
- *   This program is distributed in the hope that it will be useful,
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *   GNU General Public License for more details.
- *
- *   You should have received a copy of the GNU General Public License
- *   along with this program; if not, write to the Free Software
- *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- *   Copyright (C) 2005 infineon
- *   Copyright (C) 2007 John Crispin <blogic@openwrt.org>
- *
- */
-#ifndef _IFXMIPS_DMA_H__
-#define _IFXMIPS_DMA_H__
-
-#define RCV_INT                                                1
-#define TX_BUF_FULL_INT                                        2
-#define TRANSMIT_CPT_INT                               4
-#define IFXMIPS_DMA_CH_ON                              1
-#define IFXMIPS_DMA_CH_OFF                             0
-#define IFXMIPS_DMA_CH_DEFAULT_WEIGHT                  100
-
-enum attr_t{
-       TX = 0,
-       RX = 1,
-       RESERVED = 2,
-       DEFAULT = 3,
-};
-
-#define DMA_OWN                                                1
-#define CPU_OWN                                                0
-#define DMA_MAJOR                                      250
-
-#define DMA_DESC_OWN_CPU                               0x0
-#define DMA_DESC_OWN_DMA                               0x80000000
-#define DMA_DESC_CPT_SET                               0x40000000
-#define DMA_DESC_SOP_SET                               0x20000000
-#define DMA_DESC_EOP_SET                               0x10000000
-
-#define MISCFG_MASK                                    0x40
-#define RDERR_MASK                                     0x20
-#define CHOFF_MASK                                     0x10
-#define DESCPT_MASK                                    0x8
-#define DUR_MASK                                       0x4
-#define EOP_MASK                                       0x2
-
-#define DMA_DROP_MASK                                  (1<<31)
-
-#define IFXMIPS_DMA_RX                                 -1
-#define IFXMIPS_DMA_TX                                 1
-
-struct dma_chan_map {
-       const char *dev_name;
-       enum attr_t dir;
-       int pri;
-       int irq;
-       int rel_chan_no;
-};
-
-#ifdef CONFIG_CPU_LITTLE_ENDIAN
-struct rx_desc {
-       u32 data_length:16;
-       volatile u32 reserved:7;
-       volatile u32 byte_offset:2;
-       volatile u32 Burst_length_offset:3;
-       volatile u32 EoP:1;
-       volatile u32 Res:1;
-       volatile u32 C:1;
-       volatile u32 OWN:1;
-       volatile u32 Data_Pointer; /* fixme: should be 28 bits here */
-};
-
-struct tx_desc {
-       volatile u32 data_length:16;
-       volatile u32 reserved1:7;
-       volatile u32 byte_offset:5;
-       volatile u32 EoP:1;
-       volatile u32 SoP:1;
-       volatile u32 C:1;
-       volatile u32 OWN:1;
-       volatile u32 Data_Pointer; /* fixme: should be 28 bits here */
-};
-#else /* BIG */
-struct rx_desc {
-       union {
-               struct {
-                       volatile u32 OWN:1;
-                       volatile u32 C:1;
-                       volatile u32 SoP:1;
-                       volatile u32 EoP:1;
-                       volatile u32 Burst_length_offset:3;
-                       volatile u32 byte_offset:2;
-                       volatile u32 reserve:7;
-                       volatile u32 data_length:16;
-               } field;
-               volatile u32 word;
-       } status;
-       volatile u32 Data_Pointer;
-};
-
-struct tx_desc {
-       union {
-               struct {
-                       volatile u32 OWN:1;
-                       volatile u32 C:1;
-                       volatile u32 SoP:1;
-                       volatile u32 EoP:1;
-                       volatile u32 byte_offset:5;
-                       volatile u32 reserved:7;
-                       volatile u32 data_length:16;
-               } field;
-               volatile u32 word;
-       } status;
-       volatile u32 Data_Pointer;
-};
-#endif /* ENDIAN */
-
-struct dma_channel_info {
-       /* relative channel number */
-       int rel_chan_no;
-       /* class for this channel for QoS */
-       int pri;
-       /* specify byte_offset */
-       int byte_offset;
-       /* direction */
-       int dir;
-       /* irq number */
-       int irq;
-       /* descriptor parameter */
-       int desc_base;
-       int desc_len;
-       int curr_desc;
-       int prev_desc; /* only used if it is a tx channel*/
-       /* weight setting for WFQ algorithm*/
-       int weight;
-       int default_weight;
-       int packet_size;
-       int burst_len;
-       /* on or off of this channel */
-       int control;
-       /* optional information for the upper layer devices */
-#if defined(CONFIG_IFXMIPS_ETHERNET_D2) || defined(CONFIG_IFXMIPS_PPA)
-       void *opt[64];
-#else
-       void *opt[25];
-#endif
-       /* Pointer to the peripheral device who is using this channel */
-       void *dma_dev;
-       /* channel operations */
-       void (*open)(struct dma_channel_info *pCh);
-       void (*close)(struct dma_channel_info *pCh);
-       void (*reset)(struct dma_channel_info *pCh);
-       void (*enable_irq)(struct dma_channel_info *pCh);
-       void (*disable_irq)(struct dma_channel_info *pCh);
-};
-
-struct dma_device_info {
-       /* device name of this peripheral */
-       char device_name[15];
-       int reserved;
-       int tx_burst_len;
-       int rx_burst_len;
-       int default_weight;
-       int current_tx_chan;
-       int current_rx_chan;
-       int num_tx_chan;
-       int num_rx_chan;
-       int max_rx_chan_num;
-       int max_tx_chan_num;
-       struct dma_channel_info *tx_chan[20];
-       struct dma_channel_info *rx_chan[20];
-       /*functions, optional*/
-       u8 *(*buffer_alloc)(int len, int *offset, void **opt);
-       void (*buffer_free)(u8 *dataptr, void *opt);
-       int (*intr_handler)(struct dma_device_info *info, int status);
-       void *priv;             /* used by peripheral driver only */
-};
-
-struct dma_device_info *dma_device_reserve(char *dev_name);
-void dma_device_release(struct dma_device_info *dev);
-void dma_device_register(struct dma_device_info *info);
-void dma_device_unregister(struct dma_device_info *info);
-int dma_device_read(struct dma_device_info *info, u8 **dataptr, void **opt);
-int dma_device_write(struct dma_device_info *info, u8 *dataptr, int len,
-       void *opt);
-
-#endif
-
diff --git a/target/linux/ifxmips/files/arch/mips/include/asm/ifxmips/ifxmips_ebu.h b/target/linux/ifxmips/files/arch/mips/include/asm/ifxmips/ifxmips_ebu.h
deleted file mode 100644 (file)
index 4c9396a..0000000
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- *   This program is free software; you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation; either version 2 of the License, or
- *   (at your option) any later version.
- *
- *   This program is distributed in the hope that it will be useful,
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *   GNU General Public License for more details.
- *
- *   You should have received a copy of the GNU General Public License
- *   along with this program; if not, write to the Free Software
- *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- *   Copyright (C) 2007 John Crispin <blogic@openwrt.org>
- */
-#ifndef _IFXMIPS_EBU_H__
-#define _IFXMIPS_EBU_H__
-
-extern spinlock_t ebu_lock;
-
-#endif
diff --git a/target/linux/ifxmips/files/arch/mips/include/asm/ifxmips/ifxmips_gpio.h b/target/linux/ifxmips/files/arch/mips/include/asm/ifxmips/ifxmips_gpio.h
deleted file mode 100644 (file)
index a4c8c3f..0000000
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- *   This program is free software; you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation; either version 2 of the License, or
- *   (at your option) any later version.
- *
- *   This program is distributed in the hope that it will be useful,
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *   GNU General Public License for more details.
- *
- *   You should have received a copy of the GNU General Public License
- *   along with this program; if not, write to the Free Software
- *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *   Copyright (C) 2007 John Crispin <blogic@openwrt.org>
- */
-#ifndef _IFXMIPS_GPIO_H__
-#define _IFXMIPS_GPIO_H__
-
-extern int ifxmips_port_reserve_pin(unsigned int port, unsigned int pin);
-extern int ifxmips_port_free_pin(unsigned int port, unsigned int pin);
-extern int ifxmips_port_set_open_drain(unsigned int port, unsigned int pin);
-extern int ifxmips_port_clear_open_drain(unsigned int port, unsigned int pin);
-extern int ifxmips_port_set_pudsel(unsigned int port, unsigned int pin);
-extern int ifxmips_port_clear_pudsel(unsigned int port, unsigned int pin);
-extern int ifxmips_port_set_puden(unsigned int port, unsigned int pin);
-extern int ifxmips_port_clear_puden(unsigned int port, unsigned int pin);
-extern int ifxmips_port_set_stoff(unsigned int port, unsigned int pin);
-extern int ifxmips_port_clear_stoff(unsigned int port, unsigned int pin);
-extern int ifxmips_port_set_dir_out(unsigned int port, unsigned int pin);
-extern int ifxmips_port_set_dir_in(unsigned int port, unsigned int pin);
-extern int ifxmips_port_set_output(unsigned int port, unsigned int pin);
-extern int ifxmips_port_clear_output(unsigned int port, unsigned int pin);
-extern int ifxmips_port_get_input(unsigned int port, unsigned int pin);
-extern int ifxmips_port_set_altsel0(unsigned int port, unsigned int pin);
-extern int ifxmips_port_clear_altsel0(unsigned int port, unsigned int pin);
-extern int ifxmips_port_set_altsel1(unsigned int port, unsigned int pin);
-extern int ifxmips_port_clear_altsel1(unsigned int port, unsigned int pin);
-
-#endif
diff --git a/target/linux/ifxmips/files/arch/mips/include/asm/ifxmips/ifxmips_gptu.h b/target/linux/ifxmips/files/arch/mips/include/asm/ifxmips/ifxmips_gptu.h
deleted file mode 100644 (file)
index 330c3cf..0000000
+++ /dev/null
@@ -1,155 +0,0 @@
-#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
-#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
-
-
-/******************************************************************************
-       Copyright (c) 2002, Infineon Technologies.  All rights reserved.
-
-                               No Warranty
-   Because the program is licensed free of charge, there is no warranty for
-   the program, to the extent permitted by applicable law.  Except when
-   otherwise stated in writing the copyright holders and/or other parties
-   provide the program "as is" without warranty of any kind, either
-   expressed or implied, including, but not limited to, the implied
-   warranties of merchantability and fitness for a particular purpose. The
-   entire risk as to the quality and performance of the program is with
-   you.  should the program prove defective, you assume the cost of all
-   necessary servicing, repair or correction.
-
-   In no event unless required by applicable law or agreed to in writing
-   will any copyright holder, or any other party who may modify and/or
-   redistribute the program as permitted above, be liable to you for
-   damages, including any general, special, incidental or consequential
-   damages arising out of the use or inability to use the program
-   (including but not limited to loss of data or data being rendered
-   inaccurate or losses sustained by you or third parties or a failure of
-   the program to operate with any other programs), even if such holder or
-   other party has been advised of the possibility of such damages.
-******************************************************************************/
-
-
-/*
- * ####################################
- *              Definition
- * ####################################
- */
-
-/*
- *  Available Timer/Counter Index
- */
-#define TIMER(n, X)                     (n * 2 + (X ? 1 : 0))
-#define TIMER_ANY                       0x00
-#define TIMER1A                         TIMER(1, 0)
-#define TIMER1B                         TIMER(1, 1)
-#define TIMER2A                         TIMER(2, 0)
-#define TIMER2B                         TIMER(2, 1)
-#define TIMER3A                         TIMER(3, 0)
-#define TIMER3B                         TIMER(3, 1)
-
-/*
- *  Flag of Timer/Counter
- *  These flags specify the way in which timer is configured.
- */
-/*  Bit size of timer/counter.                      */
-#define TIMER_FLAG_16BIT                0x0000
-#define TIMER_FLAG_32BIT                0x0001
-/*  Switch between timer and counter.               */
-#define TIMER_FLAG_TIMER                0x0000
-#define TIMER_FLAG_COUNTER              0x0002
-/*  Stop or continue when overflowing/underflowing. */
-#define TIMER_FLAG_ONCE                 0x0000
-#define TIMER_FLAG_CYCLIC               0x0004
-/*  Count up or counter down.                       */
-#define TIMER_FLAG_UP                   0x0000
-#define TIMER_FLAG_DOWN                 0x0008
-/*  Count on specific level or edge.                */
-#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000
-#define TIMER_FLAG_LOW_LEVEL_SENSITIVE  0x0040
-#define TIMER_FLAG_RISE_EDGE            0x0010
-#define TIMER_FLAG_FALL_EDGE            0x0020
-#define TIMER_FLAG_ANY_EDGE             0x0030
-/*  Signal is syncronous to module clock or not.    */
-#define TIMER_FLAG_UNSYNC               0x0000
-#define TIMER_FLAG_SYNC                 0x0080
-/*  Different interrupt handle type.                */
-#define TIMER_FLAG_NO_HANDLE            0x0000
-#if defined(__KERNEL__)
-    #define TIMER_FLAG_CALLBACK_IN_IRQ  0x0100
-#endif  //  defined(__KERNEL__)
-#define TIMER_FLAG_SIGNAL               0x0300
-/*  Internal clock source or external clock source  */
-#define TIMER_FLAG_INT_SRC              0x0000
-#define TIMER_FLAG_EXT_SRC              0x1000
-
-
-/*
- *  ioctl Command
- */
-#define GPTU_REQUEST_TIMER              0x01    /*  General method to setup timer/counter.  */
-#define GPTU_FREE_TIMER                 0x02    /*  Free timer/counter.                     */
-#define GPTU_START_TIMER                0x03    /*  Start or resume timer/counter.          */
-#define GPTU_STOP_TIMER                 0x04    /*  Suspend timer/counter.                  */
-#define GPTU_GET_COUNT_VALUE            0x05    /*  Get current count value.                */
-#define GPTU_CALCULATE_DIVIDER          0x06    /*  Calculate timer divider from given freq.*/
-#define GPTU_SET_TIMER                  0x07    /*  Simplified method to setup timer.       */
-#define GPTU_SET_COUNTER                0x08    /*  Simplified method to setup counter.     */
-
-/*
- *  Data Type Used to Call ioctl
- */
-struct gptu_ioctl_param {
-    unsigned int                        timer;  /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
-                                                 *  GPTU_SET_COUNTER, this field is ID of expected      *
-                                                 *  timer/counter. If it's zero, a timer/counter would  *
-                                                 *  be dynamically allocated and ID would be stored in  *
-                                                 *  this field.                                         *
-                                                 *  In command GPTU_GET_COUNT_VALUE, this field is      *
-                                                 *  ignored.                                            *
-                                                 *  In other command, this field is ID of timer/counter *
-                                                 *  allocated.                                          */
-    unsigned int                        flag;   /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
-                                                 *  GPTU_SET_COUNTER, this field contains flags to      *
-                                                 *  specify how to configure timer/counter.             *
-                                                 *  In command GPTU_START_TIMER, zero indicate start    *
-                                                 *  and non-zero indicate resume timer/counter.         *
-                                                 *  In other command, this field is ignored.            */
-    unsigned long                       value;  /*  In command GPTU_REQUEST_TIMER, this field contains  *
-                                                 *  init/reload value.                                  *
-                                                 *  In command GPTU_SET_TIMER, this field contains      *
-                                                 *  frequency (0.001Hz) of timer.                       *
-                                                 *  In command GPTU_GET_COUNT_VALUE, current count      *
-                                                 *  value would be stored in this field.                *
-                                                 *  In command GPTU_CALCULATE_DIVIDER, this field       *
-                                                 *  contains frequency wanted, and after calculation,   *
-                                                 *  divider would be stored in this field to overwrite  *
-                                                 *  the frequency.                                      *
-                                                 *  In other command, this field is ignored.            */
-    int                                 pid;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
-                                                 *  if signal is required, this field contains process  *
-                                                 *  ID to which signal would be sent.                   *
-                                                 *  In other command, this field is ignored.            */
-    int                                 sig;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
-                                                 *  if signal is required, this field contains signal   *
-                                                 *  number which would be sent.                         *
-                                                 *  In other command, this field is ignored.            */
-};
-
-/*
- * ####################################
- *              Data Type
- * ####################################
- */
-typedef void (*timer_callback)(unsigned long arg);
-
-extern int ifxmips_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
-extern int ifxmips_free_timer(unsigned int);
-extern int ifxmips_start_timer(unsigned int, int);
-extern int ifxmips_stop_timer(unsigned int);
-extern int ifxmips_reset_counter_flags(u32 timer, u32 flags);
-extern int ifxmips_get_count_value(unsigned int, unsigned long *);
-extern u32 ifxmips_cal_divider(unsigned long);
-extern int ifxmips_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
-extern int ifxmips_set_counter(unsigned int timer, unsigned int flag,
-       u32 reload, unsigned long arg1, unsigned long arg2);
-
-#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */
diff --git a/target/linux/ifxmips/files/arch/mips/include/asm/ifxmips/ifxmips_irq.h b/target/linux/ifxmips/files/arch/mips/include/asm/ifxmips/ifxmips_irq.h
deleted file mode 100644 (file)
index f84fdcb..0000000
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- *   This program is free software; you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation; either version 2 of the License, or
- *   (at your option) any later version.
- *
- *   This program is distributed in the hope that it will be useful,
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *   GNU General Public License for more details.
- *
- *   You should have received a copy of the GNU General Public License
- *   along with this program; if not, write to the Free Software
- *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- *   Copyright (C) 2005 infineon
- *   Copyright (C) 2007 John Crispin <blogic@openwrt.org>
- */
-#ifndef _IFXMIPS_IRQ__
-#define _IFXMIPS_IRQ__
-
-#define INT_NUM_IRQ0                   8
-#define INT_NUM_IM0_IRL0               (INT_NUM_IRQ0 + 0)
-#define INT_NUM_IM1_IRL0               (INT_NUM_IRQ0 + 32)
-#define INT_NUM_IM2_IRL0               (INT_NUM_IRQ0 + 64)
-#define INT_NUM_IM3_IRL0               (INT_NUM_IRQ0 + 96)
-#define INT_NUM_IM4_IRL0               (INT_NUM_IRQ0 + 128)
-#define INT_NUM_IM_OFFSET              (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
-
-#define IFXMIPSASC_TIR(x)              (INT_NUM_IM3_IRL0 + (x * 7))
-#define IFXMIPSASC_RIR(x)              (INT_NUM_IM3_IRL0 + (x * 7) + 2)
-#define IFXMIPSASC_EIR(x)              (INT_NUM_IM3_IRL0 + (x * 7) + 3)
-
-#define IFXMIPS_SSC_TIR                        (INT_NUM_IM0_IRL0 + 15)
-#define IFXMIPS_SSC_RIR                        (INT_NUM_IM0_IRL0 + 14)
-#define IFXMIPS_SSC_EIR                        (INT_NUM_IM0_IRL0 + 16)
-
-#define IFXMIPS_MEI_INT                        (INT_NUM_IM1_IRL0 + 23)
-
-#define IFXMIPS_TIMER6_INT             (INT_NUM_IM1_IRL0 + 23)
-#define IFXMIPS_USB_OC_INT             (INT_NUM_IM4_IRL0 + 23)
-
-#define MIPS_CPU_TIMER_IRQ             7
-
-#define IFXMIPS_DMA_CH0_INT            (INT_NUM_IM2_IRL0)
-#define IFXMIPS_DMA_CH1_INT            (INT_NUM_IM2_IRL0 + 1)
-#define IFXMIPS_DMA_CH2_INT            (INT_NUM_IM2_IRL0 + 2)
-#define IFXMIPS_DMA_CH3_INT            (INT_NUM_IM2_IRL0 + 3)
-#define IFXMIPS_DMA_CH4_INT            (INT_NUM_IM2_IRL0 + 4)
-#define IFXMIPS_DMA_CH5_INT            (INT_NUM_IM2_IRL0 + 5)
-#define IFXMIPS_DMA_CH6_INT            (INT_NUM_IM2_IRL0 + 6)
-#define IFXMIPS_DMA_CH7_INT            (INT_NUM_IM2_IRL0 + 7)
-#define IFXMIPS_DMA_CH8_INT            (INT_NUM_IM2_IRL0 + 8)
-#define IFXMIPS_DMA_CH9_INT            (INT_NUM_IM2_IRL0 + 9)
-#define IFXMIPS_DMA_CH10_INT           (INT_NUM_IM2_IRL0 + 10)
-#define IFXMIPS_DMA_CH11_INT           (INT_NUM_IM2_IRL0 + 11)
-#define IFXMIPS_DMA_CH12_INT           (INT_NUM_IM2_IRL0 + 25)
-#define IFXMIPS_DMA_CH13_INT           (INT_NUM_IM2_IRL0 + 26)
-#define IFXMIPS_DMA_CH14_INT           (INT_NUM_IM2_IRL0 + 27)
-#define IFXMIPS_DMA_CH15_INT           (INT_NUM_IM2_IRL0 + 28)
-#define IFXMIPS_DMA_CH16_INT           (INT_NUM_IM2_IRL0 + 29)
-#define IFXMIPS_DMA_CH17_INT           (INT_NUM_IM2_IRL0 + 30)
-#define IFXMIPS_DMA_CH18_INT           (INT_NUM_IM2_IRL0 + 16)
-#define IFXMIPS_DMA_CH19_INT           (INT_NUM_IM2_IRL0 + 21)
-
-#define IFXMIPS_PPE_MBOX_INT           (INT_NUM_IM2_IRL0 + 24)
-
-#define IFXMIPS_USB_INT                        (INT_NUM_IM4_IRL0 + 22)
-#define IFXMIPS_USB_OC_INT             (INT_NUM_IM4_IRL0 + 23)
-
-
-extern void ifxmips_mask_and_ack_irq(unsigned int irq_nr);
-
-#endif
diff --git a/target/linux/ifxmips/files/arch/mips/include/asm/ifxmips/ifxmips_led.h b/target/linux/ifxmips/files/arch/mips/include/asm/ifxmips/ifxmips_led.h
deleted file mode 100644 (file)
index c97657a..0000000
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- *   This program is free software; you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation; either version 2 of the License, or
- *   (at your option) any later version.
- *
- *   This program is distributed in the hope that it will be useful,
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *   GNU General Public License for more details.
- *
- *   You should have received a copy of the GNU General Public License
- *   along with this program; if not, write to the Free Software
- *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- *   Copyright (C) 2007 John Crispin <blogic@openwrt.org>
- */
-#ifndef _IFXMIPS_LED_H__
-#define _IFXMIPS_LED_H__
-
-extern void ifxmips_led_set(unsigned int led);
-extern void ifxmips_led_clear(unsigned int led);
-extern void ifxmips_led_blink_set(unsigned int led);
-extern void ifxmips_led_blink_clear(unsigned int led);
-
-#endif
diff --git a/target/linux/ifxmips/files/arch/mips/include/asm/ifxmips/ifxmips_pmu.h b/target/linux/ifxmips/files/arch/mips/include/asm/ifxmips/ifxmips_pmu.h
deleted file mode 100644 (file)
index dd1f0d6..0000000
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- *   This program is free software; you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation; either version 2 of the License, or
- *   (at your option) any later version.
- *
- *   This program is distributed in the hope that it will be useful,
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *   GNU General Public License for more details.
- *
- *   You should have received a copy of the GNU General Public License
- *   along with this program; if not, write to the Free Software
- *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- *   Copyright (C) 2007 John Crispin <blogic@openwrt.org>
- */
-#ifndef _IFXMIPS_PMU_H__
-#define _IFXMIPS_PMU_H__
-
-
-#define IFXMIPS_PMU_PWDCR_DMA          0x0020
-#define IFXMIPS_PMU_PWDCR_USB          0x8041
-#define IFXMIPS_PMU_PWDCR_LED          0x0800
-#define IFXMIPS_PMU_PWDCR_GPT          0x1000
-#define IFXMIPS_PMU_PWDCR_PPE          0x2000
-#define IFXMIPS_PMU_PWDCR_FPI          0x4000
-
-void ifxmips_pmu_enable(unsigned int module);
-void ifxmips_pmu_disable(unsigned int module);
-
-#endif
diff --git a/target/linux/ifxmips/files/arch/mips/include/asm/ifxmips/ifxmips_prom.h b/target/linux/ifxmips/files/arch/mips/include/asm/ifxmips/ifxmips_prom.h
deleted file mode 100644 (file)
index e640ad7..0000000
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- *   This program is free software; you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation; either version 2 of the License, or
- *   (at your option) any later version.
- *
- *   This program is distributed in the hope that it will be useful,
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *   GNU General Public License for more details.
- *
- *   You should have received a copy of the GNU General Public License
- *   along with this program; if not, write to the Free Software
- *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- *   Copyright (C) 2008 John Crispin <blogic@openwrt.org>
- */
-#ifndef _IFXPROM_H__
-#define _IFXPROM_H__
-
-extern void prom_printf(const char *fmt, ...);
-extern u32 *prom_get_cp1_base(void);
-extern u32 prom_get_cp1_size(void);
-extern int ifxmips_has_brn_block(void);
-
-#endif
diff --git a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/cgu.h b/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/cgu.h
deleted file mode 100644 (file)
index 9ee287b..0000000
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- *   This program is free software; you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation; either version 2 of the License, or
- *   (at your option) any later version.
- *
- *   This program is distributed in the hope that it will be useful,
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *   GNU General Public License for more details.
- *
- *   You should have received a copy of the GNU General Public License
- *   along with this program; if not, write to the Free Software
- *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
- *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
- */
-
-#ifndef _IFXMIPS_CGU_H__
-#define _IFXMIPS_CGU_H__
-
-#define BASIC_INPUT_CLOCK_FREQUENCY_1   35328000
-#define BASIC_INPUT_CLOCK_FREQUENCY_2   36000000
-
-#define BASIS_INPUT_CRYSTAL_USB         12000000
-
-#define GET_BITS(x, msb, lsb)           (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
-
-#define CGU_PLL0_PHASE_DIVIDER_ENABLE   (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 31))
-#define CGU_PLL0_BYPASS                 (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 30))
-#define CGU_PLL0_CFG_DSMSEL             (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 28))
-#define CGU_PLL0_CFG_FRAC_EN            (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 27))
-#define CGU_PLL1_SRC                    (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 31))
-#define CGU_PLL1_BYPASS                 (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 30))
-#define CGU_PLL1_CFG_DSMSEL             (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 28))
-#define CGU_PLL1_CFG_FRAC_EN            (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 27))
-#define CGU_PLL2_PHASE_DIVIDER_ENABLE   (ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & (1 << 20))
-#define CGU_PLL2_BYPASS                 (ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & (1 << 19))
-#define CGU_SYS_FPI_SEL                 (1 << 6)
-#define CGU_SYS_DDR_SEL                 0x3
-#define CGU_PLL0_SRC                    (1 << 29)
-
-#define CGU_PLL0_CFG_PLLK               GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 26, 17)
-#define CGU_PLL0_CFG_PLLN               GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 12, 6)
-#define CGU_PLL0_CFG_PLLM               GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 5, 2)
-#define CGU_PLL1_CFG_PLLK               GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 26, 17)
-#define CGU_PLL1_CFG_PLLN               GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 12, 6)
-#define CGU_PLL1_CFG_PLLM               GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 5, 2)
-#define CGU_PLL2_SRC                    GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 18, 17)
-#define CGU_PLL2_CFG_INPUT_DIV          GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 16, 13)
-#define CGU_PLL2_CFG_PLLN               GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 12, 6)
-#define CGU_PLL2_CFG_PLLM               GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 5, 2)
-#define CGU_IF_CLK_PCI_CLK              GET_BITS(*IFXMIPS_CGU_IF_CLK, 23, 20)
-
-
-unsigned int cgu_get_mips_clock(int cpu);
-unsigned int cgu_get_io_region_clock(void);
-unsigned int cgu_get_fpi_bus_clock(int fpi);
-void cgu_setup_pci_clk(int internal_clock);
-unsigned int ifxmips_get_ddr_hz(void);
-unsigned int ifxmips_get_fpi_hz(void);
-unsigned int ifxmips_get_cpu_hz(void);
-
-#endif
index fa70ebc..6f05e38 100644 (file)
@@ -22,8 +22,8 @@
 #ifndef _IFXMIPS_GPIO_H_
 #define _IFXMIPS_GPIO_H_
 
-#include <asm/ifxmips/ifxmips.h>
-#include <asm/ifxmips/ifxmips_gpio.h>
+#include <ifxmips.h>
+#include <ifxmips_gpio.h>
 
 #define GPIO_TO_PORT(x) ((x > 15) ? (1) : (0))
 #define GPIO_TO_GPIO(x) ((x > 15) ? (x-16) : (x))
diff --git a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips.h b/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips.h
new file mode 100644 (file)
index 0000000..c8cf0ae
--- /dev/null
@@ -0,0 +1,516 @@
+/*
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   Copyright (C) 2005 infineon
+ *   Copyright (C) 2007 John Crispin <blogic@openwrt.org>
+ */
+#ifndef _IFXMIPS_H__
+#define _IFXMIPS_H__
+
+#define ifxmips_r32(reg)                       __raw_readl(reg)
+#define ifxmips_w32(val, reg)                  __raw_writel(val, reg)
+#define ifxmips_w32_mask(clear, set, reg)      ifxmips_w32((ifxmips_r32(reg) & ~clear) | set, reg)
+
+/*------------ GENERAL */
+
+#define BOARD_SYSTEM_TYPE              "IFXMIPS"
+
+#define IOPORT_RESOURCE_START          0x10000000
+#define IOPORT_RESOURCE_END            0xffffffff
+#define IOMEM_RESOURCE_START           0x10000000
+#define IOMEM_RESOURCE_END             0xffffffff
+
+#define IFXMIPS_FLASH_START            0x10000000
+#define IFXMIPS_FLASH_MAX              0x02000000
+
+/*------------ ASC0/1 */
+
+#define IFXMIPS_ASC_BASE_ADDR          (KSEG1 + 0x1E100400)
+#define IFXMIPS_ASC_BASE_DIFF          (0x1E100C00 - 0x1E100400)
+
+#define IFXMIPS_ASC_FSTAT              0x0048
+#define IFXMIPS_ASC_TBUF               0x0020
+#define IFXMIPS_ASC_WHBSTATE           0x0018
+#define IFXMIPS_ASC_RBUF               0x0024
+#define IFXMIPS_ASC_STATE              0x0014
+#define IFXMIPS_ASC_IRNCR              0x00F8
+#define IFXMIPS_ASC_CLC                        0x0000
+#define IFXMIPS_ASC_PISEL              0x0004
+#define IFXMIPS_ASC_TXFCON             0x0044
+#define IFXMIPS_ASC_RXFCON             0x0040
+#define IFXMIPS_ASC_CON                        0x0010
+#define IFXMIPS_ASC_BG                 0x0050
+#define IFXMIPS_ASC_IRNREN             0x00F4
+
+#define IFXMIPS_ASC_CLC_DISS           0x2
+#define ASC_IRNREN_RX_BUF              0x8
+#define ASC_IRNREN_TX_BUF              0x4
+#define ASC_IRNREN_ERR                 0x2
+#define ASC_IRNREN_TX                  0x1
+#define ASC_IRNCR_TIR                  0x4
+#define ASC_IRNCR_RIR                  0x2
+#define ASC_IRNCR_EIR                  0x4
+#define ASCOPT_CSIZE                   0x3
+#define ASCOPT_CS7                     0x1
+#define ASCOPT_CS8                     0x2
+#define ASCOPT_PARENB                  0x4
+#define ASCOPT_STOPB                   0x8
+#define ASCOPT_PARODD                  0x0
+#define ASCOPT_CREAD                   0x20
+#define TXFIFO_FL                      1
+#define RXFIFO_FL                      1
+#define TXFIFO_FULL                    16
+#define ASCCLC_RMCMASK                 0x0000FF00
+#define ASCCLC_RMCOFFSET               8
+#define ASCCON_M_8ASYNC                        0x0
+#define ASCCON_M_7ASYNC                        0x2
+#define ASCCON_ODD                     0x00000020
+#define ASCCON_STP                     0x00000080
+#define ASCCON_BRS                     0x00000100
+#define ASCCON_FDE                     0x00000200
+#define ASCCON_R                       0x00008000
+#define ASCCON_FEN                     0x00020000
+#define ASCCON_ROEN                    0x00080000
+#define ASCCON_TOEN                    0x00100000
+#define ASCSTATE_PE                    0x00010000
+#define ASCSTATE_FE                    0x00020000
+#define ASCSTATE_ROE                   0x00080000
+#define ASCSTATE_ANY                   (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
+#define ASCWHBSTATE_CLRREN             0x00000001
+#define ASCWHBSTATE_SETREN             0x00000002
+#define ASCWHBSTATE_CLRPE              0x00000004
+#define ASCWHBSTATE_CLRFE              0x00000008
+#define ASCWHBSTATE_CLRROE             0x00000020
+#define ASCTXFCON_TXFEN                        0x0001
+#define ASCTXFCON_TXFFLU               0x0002
+#define ASCTXFCON_TXFITLMASK           0x3F00
+#define ASCTXFCON_TXFITLOFF            8
+#define ASCRXFCON_RXFEN                        0x0001
+#define ASCRXFCON_RXFFLU               0x0002
+#define ASCRXFCON_RXFITLMASK           0x3F00
+#define ASCRXFCON_RXFITLOFF            8
+#define ASCFSTAT_RXFFLMASK             0x003F
+#define ASCFSTAT_TXFFLMASK             0x3F00
+#define ASCFSTAT_TXFFLOFF              8
+
+
+
+/*------------ RCU */
+#define IFXMIPS_RCU_BASE_ADDR          0xBF203000
+
+/* reset request */
+#define IFXMIPS_RCU_RST                        ((u32 *)(IFXMIPS_RCU_BASE_ADDR + 0x0010))
+#define IFXMIPS_RCU_RST_CPU1           (1 << 3)
+#define IFXMIPS_RCU_RST_ALL            0x40000000
+
+#define IFXMIPS_RCU_RST_REQ_DFE                (1 << 7)
+#define IFXMIPS_RCU_RST_REQ_AFE                (1 << 11)
+#define IFXMIPS_RCU_RST_REQ_ARC_JTAG   (1 << 20)
+
+
+/*------------ GPTU */
+
+#define IFXMIPS_GPTU_BASE_ADDR         0xB8000300
+
+/* clock control register */
+#define IFXMIPS_GPTU_GPT_CLC           ((u32 *)(IFXMIPS_GPTU_BASE_ADDR + 0x0000))
+
+/* captur reload register */
+#define IFXMIPS_GPTU_GPT_CAPREL                ((u32 *)(IFXMIPS_GPTU_BASE_ADDR + 0x0030))
+
+/* timer 6 control register */
+#define IFXMIPS_GPTU_GPT_T6CON         ((u32 *)(IFXMIPS_GPTU_BASE_ADDR + 0x0020))
+
+
+/*------------ EBU */
+
+#define IFXMIPS_EBU_BASE_ADDR          0xBE105300
+
+/* bus configuration register */
+#define IFXMIPS_EBU_BUSCON0            ((u32 *)(IFXMIPS_EBU_BASE_ADDR + 0x0060))
+#define IFXMIPS_EBU_PCC_CON            ((u32 *)(IFXMIPS_EBU_BASE_ADDR + 0x0090))
+#define IFXMIPS_EBU_PCC_IEN            ((u32 *)(IFXMIPS_EBU_BASE_ADDR + 0x00A4))
+#define IFXMIPS_EBU_PCC_ISTAT          ((u32 *)(IFXMIPS_EBU_BASE_ADDR + 0x00A0))
+
+
+/*------------ CGU */
+#define IFXMIPS_CGU_BASE_ADDR          (KSEG1 + 0x1F103000)
+#define IFXMIPS_CGU_PLL0_CFG           ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0004))
+#define IFXMIPS_CGU_PLL1_CFG           ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0008))
+#define IFXMIPS_CGU_PLL2_CFG           ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x000C))
+#define IFXMIPS_CGU_SYS                        ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0010))
+#define IFXMIPS_CGU_UPDATE             ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0014))
+#define IFXMIPS_CGU_IF_CLK             ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0018))
+#define IFXMIPS_CGU_OSC_CON            ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x001C))
+#define IFXMIPS_CGU_SMD                        ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0020))
+#define IFXMIPS_CGU_CT1SR              ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0028))
+#define IFXMIPS_CGU_CT2SR              ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x002C))
+#define IFXMIPS_CGU_PCMCR              ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0030))
+#define IFXMIPS_CGU_PCI_CR             ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0034))
+#define IFXMIPS_CGU_PD_PC              ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0038))
+#define IFXMIPS_CGU_FMR                        ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x003C))
+
+/* clock mux */
+#define IFXMIPS_CGU_SYS                        ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0010))
+#define IFXMIPS_CGU_IFCCR              ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0018))
+#define IFXMIPS_CGU_PCICR              ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0034))
+
+#define CLOCK_60M                      60000000
+#define CLOCK_83M                      83333333
+#define CLOCK_111M                     111111111
+#define CLOCK_133M                     133333333
+#define CLOCK_167M                     166666667
+#define CLOCK_333M                     333333333
+
+
+/*------------ CGU */
+
+#define IFXMIPS_PMU_BASE_ADDR          (KSEG1 + 0x1F102000)
+
+#define IFXMIPS_PMU_PWDCR              ((u32 *)(IFXMIPS_PMU_BASE_ADDR + 0x001C))
+#define IFXMIPS_PMU_PWDSR              ((u32 *)(IFXMIPS_PMU_BASE_ADDR + 0x0020))
+
+
+/*------------ ICU */
+
+#define IFXMIPS_ICU_BASE_ADDR          0xBF880200
+
+
+#define IFXMIPS_ICU_IM0_ISR            ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0000))
+#define IFXMIPS_ICU_IM0_IER            ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0008))
+#define IFXMIPS_ICU_IM0_IOSR           ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0010))
+#define IFXMIPS_ICU_IM0_IRSR           ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0018))
+#define IFXMIPS_ICU_IM0_IMR            ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0020))
+
+#define IFXMIPS_ICU_IM1_ISR            ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0028))
+#define IFXMIPS_ICU_IM2_IER            ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0058))
+#define IFXMIPS_ICU_IM3_IER            ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0080))
+#define IFXMIPS_ICU_IM4_IER            ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x00A8))
+#define IFXMIPS_ICU_IM5_IER            ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x00D0))
+
+#define IFXMIPS_ICU_OFFSET             (IFXMIPS_ICU_IM1_ISR - IFXMIPS_ICU_IM0_ISR)
+
+
+/*------------ ETOP */
+
+#define IFXMIPS_PPE32_BASE_ADDR                0xBE180000
+
+#define ETHERNET_PACKET_DMA_BUFFER_SIZE                0x600
+
+#define IFXMIPS_PPE32_MEM_MAP          ((u32 *)(IFXMIPS_PPE32_BASE_ADDR + 0x10000))
+#define IFXMIPS_PPE32_SRST             ((u32 *)(IFXMIPS_PPE32_BASE_ADDR + 0x10080))
+
+#define MII_MODE                       1
+#define REV_MII_MODE                   2
+
+/* mdio access */
+#define IFXMIPS_PPE32_MDIO_CFG         ((u32 *)(IFXMIPS_PPE32_BASE_ADDR + 0x11800))
+#define IFXMIPS_PPE32_MDIO_ACC         ((u32 *)(IFXMIPS_PPE32_BASE_ADDR + 0x11804))
+
+#define MDIO_ACC_REQUEST               0x80000000
+#define MDIO_ACC_READ                  0x40000000
+#define MDIO_ACC_ADDR_MASK             0x1f
+#define MDIO_ACC_ADDR_OFFSET           0x15
+#define MDIO_ACC_REG_MASK              0xff
+#define MDIO_ACC_REG_OFFSET            0x10
+#define MDIO_ACC_VAL_MASK              0xffff
+
+/* configuration */
+#define IFXMIPS_PPE32_CFG              ((u32 *)(IFXMIPS_PPE32_MEM_MAP + 0x1808))
+
+#define PPE32_MII_MASK                 0xfffffffc
+#define PPE32_MII_NORMAL               0x8
+#define PPE32_MII_REVERSE              0xe
+
+/* packet length */
+#define IFXMIPS_PPE32_IG_PLEN_CTRL     ((u32 *)(IFXMIPS_PPE32_MEM_MAP + 0x1820))
+
+#define PPE32_PLEN_OVER                        0x5ee
+#define PPE32_PLEN_UNDER               0x400000
+
+/* enet */
+#define IFXMIPS_PPE32_ENET_MAC_CFG     ((u32 *)(IFXMIPS_PPE32_MEM_MAP + 0x1840))
+
+#define PPE32_CGEN                     0x800
+
+
+/*------------ DMA */
+#define IFXMIPS_DMA_BASE_ADDR  0xBE104100
+
+#define IFXMIPS_DMA_CS                 ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x18))
+#define IFXMIPS_DMA_CIE                        ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x2C))
+#define IFXMIPS_DMA_IRNEN              ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0xf4))
+#define IFXMIPS_DMA_CCTRL              ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x1C))
+#define IFXMIPS_DMA_CIS                        ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x28))
+#define IFXMIPS_DMA_CDLEN              ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x24))
+#define IFXMIPS_DMA_PS                 ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x40))
+#define IFXMIPS_DMA_PCTRL              ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x44))
+#define IFXMIPS_DMA_CTRL               ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x10))
+#define IFXMIPS_DMA_CPOLL              ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x14))
+#define IFXMIPS_DMA_CDBA               ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x20))
+
+
+/*------------ PCI */
+#define PCI_CR_PR_BASE_ADDR            (KSEG1 + 0x1E105400)
+
+#define PCI_CR_FCI_ADDR_MAP0           ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00C0))
+#define PCI_CR_FCI_ADDR_MAP1           ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00C4))
+#define PCI_CR_FCI_ADDR_MAP2           ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00C8))
+#define PCI_CR_FCI_ADDR_MAP3           ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00CC))
+#define PCI_CR_FCI_ADDR_MAP4           ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D0))
+#define PCI_CR_FCI_ADDR_MAP5           ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D4))
+#define PCI_CR_FCI_ADDR_MAP6           ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D8))
+#define PCI_CR_FCI_ADDR_MAP7           ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00DC))
+#define PCI_CR_CLK_CTRL                        ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0000))
+#define PCI_CR_PCI_MOD                 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0030))
+#define PCI_CR_PC_ARB                  ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0080))
+#define PCI_CR_FCI_ADDR_MAP11hg                ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00E4))
+#define PCI_CR_BAR11MASK               ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0044))
+#define PCI_CR_BAR12MASK               ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0048))
+#define PCI_CR_BAR13MASK               ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x004C))
+#define PCI_CS_BASE_ADDR1              ((u32 *)(PCI_CS_PR_BASE_ADDR + 0x0010))
+#define PCI_CR_PCI_ADDR_MAP11          ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0064))
+#define PCI_CR_FCI_BURST_LENGTH                ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00E8))
+#define PCI_CR_PCI_EOI                 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x002C))
+
+#define PCI_CS_PR_BASE_ADDR            (KSEG1 + 0x17000000)
+
+#define PCI_CS_STS_CMD                 ((u32 *)(PCI_CS_PR_BASE_ADDR + 0x0004))
+
+#define PCI_MASTER0_REQ_MASK_2BITS     8
+#define PCI_MASTER1_REQ_MASK_2BITS     10
+#define PCI_MASTER2_REQ_MASK_2BITS     12
+#define INTERNAL_ARB_ENABLE_BIT                0
+
+
+/*------------ WDT */
+
+#define IFXMIPS_WDT_BASE_ADDR          (KSEG1 + 0x1F880000)
+
+#define IFXMIPS_BIU_WDT_CR             ((u32 *)(IFXMIPS_WDT_BASE_ADDR + 0x03F0))
+#define IFXMIPS_BIU_WDT_SR             ((u32 *)(IFXMIPS_WDT_BASE_ADDR + 0x03F8))
+
+
+/*------------ LED */
+
+#define IFXMIPS_LED_BASE_ADDR          (KSEG1 + 0x1E100BB0)
+#define IFXMIPS_LED_CON0               ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x0000))
+#define IFXMIPS_LED_CON1               ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x0004))
+#define IFXMIPS_LED_CPU0               ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x0008))
+#define IFXMIPS_LED_CPU1               ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x000C))
+#define IFXMIPS_LED_AR                 ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x0010))
+
+#define LED_CON0_SWU                   (1 << 31)
+#define LED_CON0_AD1                   (1 << 25)
+#define LED_CON0_AD0                   (1 << 24)
+
+#define IFXMIPS_LED_2HZ                        (0)
+#define IFXMIPS_LED_4HZ                        (1 << 23)
+#define IFXMIPS_LED_8HZ                        (2 << 23)
+#define IFXMIPS_LED_10HZ               (3 << 23)
+#define IFXMIPS_LED_MASK               (0xf << 23)
+
+#define IFXMIPS_LED_UPD_SRC_FPI        (1 << 31)
+#define IFXMIPS_LED_UPD_MASK           (3 << 30)
+#define IFXMIPS_LED_ADSL_SRC           (3 << 24)
+
+#define IFXMIPS_LED_GROUP0             (1 << 0)
+#define IFXMIPS_LED_GROUP1             (1 << 1)
+#define IFXMIPS_LED_GROUP2             (1 << 2)
+
+#define IFXMIPS_LED_RISING             0
+#define IFXMIPS_LED_FALLING            (1 << 26)
+#define IFXMIPS_LED_EDGE_MASK          (1 << 26)
+
+
+/*------------ GPIO */
+
+#define IFXMIPS_GPIO_BASE_ADDR (0xBE100B00)
+
+#define IFXMIPS_GPIO_P0_OUT            ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0010))
+#define IFXMIPS_GPIO_P1_OUT            ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0040))
+#define IFXMIPS_GPIO_P0_IN             ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0014))
+#define IFXMIPS_GPIO_P1_IN             ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0044))
+#define IFXMIPS_GPIO_P0_DIR            ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0018))
+#define IFXMIPS_GPIO_P1_DIR            ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0048))
+#define IFXMIPS_GPIO_P0_ALTSEL0                ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x001C))
+#define IFXMIPS_GPIO_P1_ALTSEL0                ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x004C))
+#define IFXMIPS_GPIO_P0_ALTSEL1                ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0020))
+#define IFXMIPS_GPIO_P1_ALTSEL1                ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0050))
+#define IFXMIPS_GPIO_P0_OD             ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0024))
+#define IFXMIPS_GPIO_P1_OD             ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0054))
+#define IFXMIPS_GPIO_P0_STOFF          ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0028))
+#define IFXMIPS_GPIO_P1_STOFF          ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0058))
+#define IFXMIPS_GPIO_P0_PUDSEL         ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x002C))
+#define IFXMIPS_GPIO_P1_PUDSEL         ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x005C))
+#define IFXMIPS_GPIO_P0_PUDEN          ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0030))
+#define IFXMIPS_GPIO_P1_PUDEN          ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0060))
+
+
+/*------------ SSC */
+
+#define IFXMIPS_SSC_BASE_ADDR          (KSEG1 + 0x1e100800)
+
+
+#define IFXMIPS_SSC_CLC                        ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0000))
+#define IFXMIPS_SSC_IRN                        ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x00F4))
+#define IFXMIPS_SSC_SFCON              ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0060))
+#define IFXMIPS_SSC_WHBGPOSTAT         ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0078))
+#define IFXMIPS_SSC_STATE              ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0014))
+#define IFXMIPS_SSC_WHBSTATE           ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0018))
+#define IFXMIPS_SSC_FSTAT              ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0038))
+#define IFXMIPS_SSC_ID                 ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0008))
+#define IFXMIPS_SSC_TB                 ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0020))
+#define IFXMIPS_SSC_RXFCON             ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0030))
+#define IFXMIPS_SSC_TXFCON             ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0034))
+#define IFXMIPS_SSC_CON                        ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0010))
+#define IFXMIPS_SSC_GPOSTAT            ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0074))
+#define IFXMIPS_SSC_RB                 ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0024))
+#define IFXMIPS_SSC_RXCNT              ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0084))
+#define IFXMIPS_SSC_GPOCON             ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0070))
+#define IFXMIPS_SSC_BR                 ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0040))
+#define IFXMIPS_SSC_RXREQ              ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0080))
+#define IFXMIPS_SSC_SFSTAT             ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0064))
+#define IFXMIPS_SSC_RXCNT              ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0084))
+
+
+/*------------ MEI */
+
+#define IFXMIPS_MEI_BASE_ADDR          (KSEG1 + 0x1E116000)
+
+#define MEI_DATA_XFR                   ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0000))
+#define MEI_VERSION                    ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0004))
+#define MEI_ARC_GP_STAT                        ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0008))
+#define MEI_DATA_XFR_STAT              ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x000C))
+#define MEI_XFR_ADDR                   ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0010))
+#define MEI_MAX_WAIT                   ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0014))
+#define MEI_TO_ARC_INT                 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0018))
+#define ARC_TO_MEI_INT                 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x001C))
+#define ARC_TO_MEI_INT_MASK            ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0020))
+#define MEI_DEBUG_WAD                  ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0024))
+#define MEI_DEBUG_RAD                  ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0028))
+#define MEI_DEBUG_DATA                 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x002C))
+#define MEI_DEBUG_DEC                  ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0030))
+#define MEI_CONFIG                     ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0034))
+#define MEI_RST_CONTROL                        ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0038))
+#define MEI_DBG_MASTER                 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x003C))
+#define MEI_CLK_CONTROL                        ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0040))
+#define MEI_BIST_CONTROL               ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0044))
+#define MEI_BIST_STAT                  ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0048))
+#define MEI_XDATA_BASE_SH              ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x004c))
+#define MEI_XDATA_BASE                 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0050))
+#define MEI_XMEM_BAR_BASE              ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0054))
+#define MEI_XMEM_BAR0                  ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0054))
+#define MEI_XMEM_BAR1                  ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0058))
+#define MEI_XMEM_BAR2                  ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x005C))
+#define MEI_XMEM_BAR3                  ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0060))
+#define MEI_XMEM_BAR4                  ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0064))
+#define MEI_XMEM_BAR5                  ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0068))
+#define MEI_XMEM_BAR6                  ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x006C))
+#define MEI_XMEM_BAR7                  ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0070))
+#define MEI_XMEM_BAR8                  ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0074))
+#define MEI_XMEM_BAR9                  ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0078))
+#define MEI_XMEM_BAR10                 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x007C))
+#define MEI_XMEM_BAR11                 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0080))
+#define MEI_XMEM_BAR12                 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0084))
+#define MEI_XMEM_BAR13                 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0088))
+#define MEI_XMEM_BAR14                 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x008C))
+#define MEI_XMEM_BAR15                 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0090))
+#define MEI_XMEM_BAR16                 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0094))
+
+
+/*------------ DEU */
+
+#define IFXMIPS_DEU_BASE               (KSEG1 + 0x1E103100)
+#define IFXMIPS_DEU_CLK                        ((u32 *)(IFXMIPS_DEU_BASE + 0x0000))
+#define IFXMIPS_DEU_ID                 ((u32 *)(IFXMIPS_DEU_BASE + 0x0008))
+
+#define IFXMIPS_DES_CON                        ((u32 *)(IFXMIPS_DEU_BASE + 0x0010))
+#define IFXMIPS_DES_IHR                        ((u32 *)(IFXMIPS_DEU_BASE + 0x0014))
+#define IFXMIPS_DES_ILR                        ((u32 *)(IFXMIPS_DEU_BASE + 0x0018))
+#define IFXMIPS_DES_K1HR               ((u32 *)(IFXMIPS_DEU_BASE + 0x001C))
+#define IFXMIPS_DES_K1LR               ((u32 *)(IFXMIPS_DEU_BASE + 0x0020))
+#define IFXMIPS_DES_K3HR               ((u32 *)(IFXMIPS_DEU_BASE + 0x0024))
+#define IFXMIPS_DES_K3LR               ((u32 *)(IFXMIPS_DEU_BASE + 0x0028))
+#define IFXMIPS_DES_IVHR               ((u32 *)(IFXMIPS_DEU_BASE + 0x002C))
+#define IFXMIPS_DES_IVLR               ((u32 *)(IFXMIPS_DEU_BASE + 0x0030))
+#define IFXMIPS_DES_OHR                        ((u32 *)(IFXMIPS_DEU_BASE + 0x0040))
+#define IFXMIPS_DES_OLR                        ((u32 *)(IFXMIPS_DEU_BASE + 0x0050))
+#define IFXMIPS_AES_CON                        ((u32 *)(IFXMIPS_DEU_BASE + 0x0050))
+#define IFXMIPS_AES_ID3R               ((u32 *)(IFXMIPS_DEU_BASE + 0x0054))
+#define IFXMIPS_AES_ID2R               ((u32 *)(IFXMIPS_DEU_BASE + 0x0058))
+#define IFXMIPS_AES_ID1R               ((u32 *)(IFXMIPS_DEU_BASE + 0x005C))
+#define IFXMIPS_AES_ID0R               ((u32 *)(IFXMIPS_DEU_BASE + 0x0060))
+#define IFXMIPS_AES_K7R                        ((u32 *)(IFXMIPS_DEU_BASE + 0x0064))
+#define IFXMIPS_AES_K6R                        ((u32 *)(IFXMIPS_DEU_BASE + 0x0068))
+#define IFXMIPS_AES_K5R                        ((u32 *)(IFXMIPS_DEU_BASE + 0x006C))
+#define IFXMIPS_AES_K4R                        ((u32 *)(IFXMIPS_DEU_BASE + 0x0070))
+#define IFXMIPS_AES_K3R                        ((u32 *)(IFXMIPS_DEU_BASE + 0x0074))
+#define IFXMIPS_AES_K2R                        ((u32 *)(IFXMIPS_DEU_BASE + 0x0078))
+#define IFXMIPS_AES_K1R                        ((u32 *)(IFXMIPS_DEU_BASE + 0x007C))
+#define IFXMIPS_AES_K0R                        ((u32 *)(IFXMIPS_DEU_BASE + 0x0080))
+#define IFXMIPS_AES_IV3R               ((u32 *)(IFXMIPS_DEU_BASE + 0x0084))
+#define IFXMIPS_AES_IV2R               ((u32 *)(IFXMIPS_DEU_BASE + 0x0088))
+#define IFXMIPS_AES_IV1R               ((u32 *)(IFXMIPS_DEU_BASE + 0x008C))
+#define IFXMIPS_AES_IV0R               ((u32 *)(IFXMIPS_DEU_BASE + 0x0090))
+#define IFXMIPS_AES_0D3R               ((u32 *)(IFXMIPS_DEU_BASE + 0x0094))
+#define IFXMIPS_AES_0D2R               ((u32 *)(IFXMIPS_DEU_BASE + 0x0098))
+#define IFXMIPS_AES_OD1R               ((u32 *)(IFXMIPS_DEU_BASE + 0x009C))
+#define IFXMIPS_AES_OD0R               ((u32 *)(IFXMIPS_DEU_BASE + 0x00A0))
+
+/*------------ FUSE */
+
+#define IFXMIPS_FUSE_BASE_ADDR         (KSEG1 + 0x1F107354)
+
+
+/*------------ MPS */
+
+#define IFXMIPS_MPS_BASE_ADDR          (KSEG1 + 0x1F107000)
+#define IFXMIPS_MPS_SRAM               ((u32 *)(KSEG1 + 0x1F200000))
+
+#define IFXMIPS_MPS_CHIPID             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0344))
+#define IFXMIPS_MPS_VC0ENR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0000))
+#define IFXMIPS_MPS_VC1ENR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0004))
+#define IFXMIPS_MPS_VC2ENR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0008))
+#define IFXMIPS_MPS_VC3ENR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x000C))
+#define IFXMIPS_MPS_RVC0SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0010))
+#define IFXMIPS_MPS_RVC1SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0014))
+#define IFXMIPS_MPS_RVC2SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0018))
+#define IFXMIPS_MPS_RVC3SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x001C))
+#define IFXMIPS_MPS_SVC0SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0020))
+#define IFXMIPS_MPS_SVC1SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0024))
+#define IFXMIPS_MPS_SVC2SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0028))
+#define IFXMIPS_MPS_SVC3SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x002C))
+#define IFXMIPS_MPS_CVC0SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0030))
+#define IFXMIPS_MPS_CVC1SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0034))
+#define IFXMIPS_MPS_CVC2SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0038))
+#define IFXMIPS_MPS_CVC3SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x003C))
+#define IFXMIPS_MPS_RAD0SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0040))
+#define IFXMIPS_MPS_RAD1SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0044))
+#define IFXMIPS_MPS_SAD0SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0048))
+#define IFXMIPS_MPS_SAD1SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x004C))
+#define IFXMIPS_MPS_CAD0SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0050))
+#define IFXMIPS_MPS_CAD1SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0054))
+#define IFXMIPS_MPS_AD0ENR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0058))
+#define IFXMIPS_MPS_AD1ENR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x005C))
+
+#define IFXMIPS_MPS_CHIPID_VERSION_GET(value)  (((value) >> 28) & ((1 << 4) - 1))
+#define IFXMIPS_MPS_CHIPID_VERSION_SET(value)  ((((1 << 4) - 1) & (value)) << 28)
+#define IFXMIPS_MPS_CHIPID_PARTNUM_GET(value)  (((value) >> 12) & ((1 << 16) - 1))
+#define IFXMIPS_MPS_CHIPID_PARTNUM_SET(value)  ((((1 << 16) - 1) & (value)) << 12)
+#define IFXMIPS_MPS_CHIPID_MANID_GET(value)    (((value) >> 1) & ((1 << 10) - 1))
+#define IFXMIPS_MPS_CHIPID_MANID_SET(value)    ((((1 << 10) - 1) & (value)) << 1)
+
+#endif
diff --git a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_cgu.h b/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_cgu.h
new file mode 100644 (file)
index 0000000..9ee287b
--- /dev/null
@@ -0,0 +1,64 @@
+/*
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
+ */
+
+#ifndef _IFXMIPS_CGU_H__
+#define _IFXMIPS_CGU_H__
+
+#define BASIC_INPUT_CLOCK_FREQUENCY_1   35328000
+#define BASIC_INPUT_CLOCK_FREQUENCY_2   36000000
+
+#define BASIS_INPUT_CRYSTAL_USB         12000000
+
+#define GET_BITS(x, msb, lsb)           (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
+
+#define CGU_PLL0_PHASE_DIVIDER_ENABLE   (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 31))
+#define CGU_PLL0_BYPASS                 (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 30))
+#define CGU_PLL0_CFG_DSMSEL             (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 28))
+#define CGU_PLL0_CFG_FRAC_EN            (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 27))
+#define CGU_PLL1_SRC                    (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 31))
+#define CGU_PLL1_BYPASS                 (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 30))
+#define CGU_PLL1_CFG_DSMSEL             (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 28))
+#define CGU_PLL1_CFG_FRAC_EN            (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 27))
+#define CGU_PLL2_PHASE_DIVIDER_ENABLE   (ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & (1 << 20))
+#define CGU_PLL2_BYPASS                 (ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & (1 << 19))
+#define CGU_SYS_FPI_SEL                 (1 << 6)
+#define CGU_SYS_DDR_SEL                 0x3
+#define CGU_PLL0_SRC                    (1 << 29)
+
+#define CGU_PLL0_CFG_PLLK               GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 26, 17)
+#define CGU_PLL0_CFG_PLLN               GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 12, 6)
+#define CGU_PLL0_CFG_PLLM               GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 5, 2)
+#define CGU_PLL1_CFG_PLLK               GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 26, 17)
+#define CGU_PLL1_CFG_PLLN               GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 12, 6)
+#define CGU_PLL1_CFG_PLLM               GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 5, 2)
+#define CGU_PLL2_SRC                    GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 18, 17)
+#define CGU_PLL2_CFG_INPUT_DIV          GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 16, 13)
+#define CGU_PLL2_CFG_PLLN               GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 12, 6)
+#define CGU_PLL2_CFG_PLLM               GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 5, 2)
+#define CGU_IF_CLK_PCI_CLK              GET_BITS(*IFXMIPS_CGU_IF_CLK, 23, 20)
+
+
+unsigned int cgu_get_mips_clock(int cpu);
+unsigned int cgu_get_io_region_clock(void);
+unsigned int cgu_get_fpi_bus_clock(int fpi);
+void cgu_setup_pci_clk(int internal_clock);
+unsigned int ifxmips_get_ddr_hz(void);
+unsigned int ifxmips_get_fpi_hz(void);
+unsigned int ifxmips_get_cpu_hz(void);
+
+#endif
diff --git a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_dma.h b/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_dma.h
new file mode 100644 (file)
index 0000000..8ba852a
--- /dev/null
@@ -0,0 +1,195 @@
+/*
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   Copyright (C) 2005 infineon
+ *   Copyright (C) 2007 John Crispin <blogic@openwrt.org>
+ *
+ */
+#ifndef _IFXMIPS_DMA_H__
+#define _IFXMIPS_DMA_H__
+
+#define RCV_INT                                                1
+#define TX_BUF_FULL_INT                                        2
+#define TRANSMIT_CPT_INT                               4
+#define IFXMIPS_DMA_CH_ON                              1
+#define IFXMIPS_DMA_CH_OFF                             0
+#define IFXMIPS_DMA_CH_DEFAULT_WEIGHT                  100
+
+enum attr_t{
+       TX = 0,
+       RX = 1,
+       RESERVED = 2,
+       DEFAULT = 3,
+};
+
+#define DMA_OWN                                                1
+#define CPU_OWN                                                0
+#define DMA_MAJOR                                      250
+
+#define DMA_DESC_OWN_CPU                               0x0
+#define DMA_DESC_OWN_DMA                               0x80000000
+#define DMA_DESC_CPT_SET                               0x40000000
+#define DMA_DESC_SOP_SET                               0x20000000
+#define DMA_DESC_EOP_SET                               0x10000000
+
+#define MISCFG_MASK                                    0x40
+#define RDERR_MASK                                     0x20
+#define CHOFF_MASK                                     0x10
+#define DESCPT_MASK                                    0x8
+#define DUR_MASK                                       0x4
+#define EOP_MASK                                       0x2
+
+#define DMA_DROP_MASK                                  (1<<31)
+
+#define IFXMIPS_DMA_RX                                 -1
+#define IFXMIPS_DMA_TX                                 1
+
+struct dma_chan_map {
+       const char *dev_name;
+       enum attr_t dir;
+       int pri;
+       int irq;
+       int rel_chan_no;
+};
+
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+struct rx_desc {
+       u32 data_length:16;
+       volatile u32 reserved:7;
+       volatile u32 byte_offset:2;
+       volatile u32 Burst_length_offset:3;
+       volatile u32 EoP:1;
+       volatile u32 Res:1;
+       volatile u32 C:1;
+       volatile u32 OWN:1;
+       volatile u32 Data_Pointer; /* fixme: should be 28 bits here */
+};
+
+struct tx_desc {
+       volatile u32 data_length:16;
+       volatile u32 reserved1:7;
+       volatile u32 byte_offset:5;
+       volatile u32 EoP:1;
+       volatile u32 SoP:1;
+       volatile u32 C:1;
+       volatile u32 OWN:1;
+       volatile u32 Data_Pointer; /* fixme: should be 28 bits here */
+};
+#else /* BIG */
+struct rx_desc {
+       union {
+               struct {
+                       volatile u32 OWN:1;
+                       volatile u32 C:1;
+                       volatile u32 SoP:1;
+                       volatile u32 EoP:1;
+                       volatile u32 Burst_length_offset:3;
+                       volatile u32 byte_offset:2;
+                       volatile u32 reserve:7;
+                       volatile u32 data_length:16;
+               } field;
+               volatile u32 word;
+       } status;
+       volatile u32 Data_Pointer;
+};
+
+struct tx_desc {
+       union {
+               struct {
+                       volatile u32 OWN:1;
+                       volatile u32 C:1;
+                       volatile u32 SoP:1;
+                       volatile u32 EoP:1;
+                       volatile u32 byte_offset:5;
+                       volatile u32 reserved:7;
+                       volatile u32 data_length:16;
+               } field;
+               volatile u32 word;
+       } status;
+       volatile u32 Data_Pointer;
+};
+#endif /* ENDIAN */
+
+struct dma_channel_info {
+       /* relative channel number */
+       int rel_chan_no;
+       /* class for this channel for QoS */
+       int pri;
+       /* specify byte_offset */
+       int byte_offset;
+       /* direction */
+       int dir;
+       /* irq number */
+       int irq;
+       /* descriptor parameter */
+       int desc_base;
+       int desc_len;
+       int curr_desc;
+       int prev_desc; /* only used if it is a tx channel*/
+       /* weight setting for WFQ algorithm*/
+       int weight;
+       int default_weight;
+       int packet_size;
+       int burst_len;
+       /* on or off of this channel */
+       int control;
+       /* optional information for the upper layer devices */
+#if defined(CONFIG_IFXMIPS_ETHERNET_D2) || defined(CONFIG_IFXMIPS_PPA)
+       void *opt[64];
+#else
+       void *opt[25];
+#endif
+       /* Pointer to the peripheral device who is using this channel */
+       void *dma_dev;
+       /* channel operations */
+       void (*open)(struct dma_channel_info *pCh);
+       void (*close)(struct dma_channel_info *pCh);
+       void (*reset)(struct dma_channel_info *pCh);
+       void (*enable_irq)(struct dma_channel_info *pCh);
+       void (*disable_irq)(struct dma_channel_info *pCh);
+};
+
+struct dma_device_info {
+       /* device name of this peripheral */
+       char device_name[15];
+       int reserved;
+       int tx_burst_len;
+       int rx_burst_len;
+       int default_weight;
+       int current_tx_chan;
+       int current_rx_chan;
+       int num_tx_chan;
+       int num_rx_chan;
+       int max_rx_chan_num;
+       int max_tx_chan_num;
+       struct dma_channel_info *tx_chan[20];
+       struct dma_channel_info *rx_chan[20];
+       /*functions, optional*/
+       u8 *(*buffer_alloc)(int len, int *offset, void **opt);
+       void (*buffer_free)(u8 *dataptr, void *opt);
+       int (*intr_handler)(struct dma_device_info *info, int status);
+       void *priv;             /* used by peripheral driver only */
+};
+
+struct dma_device_info *dma_device_reserve(char *dev_name);
+void dma_device_release(struct dma_device_info *dev);
+void dma_device_register(struct dma_device_info *info);
+void dma_device_unregister(struct dma_device_info *info);
+int dma_device_read(struct dma_device_info *info, u8 **dataptr, void **opt);
+int dma_device_write(struct dma_device_info *info, u8 *dataptr, int len,
+       void *opt);
+
+#endif
+
diff --git a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_ebu.h b/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_ebu.h
new file mode 100644 (file)
index 0000000..4c9396a
--- /dev/null
@@ -0,0 +1,23 @@
+/*
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   Copyright (C) 2007 John Crispin <blogic@openwrt.org>
+ */
+#ifndef _IFXMIPS_EBU_H__
+#define _IFXMIPS_EBU_H__
+
+extern spinlock_t ebu_lock;
+
+#endif
diff --git a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_gpio.h b/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_gpio.h
new file mode 100644 (file)
index 0000000..a4c8c3f
--- /dev/null
@@ -0,0 +1,40 @@
+/*
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *   Copyright (C) 2007 John Crispin <blogic@openwrt.org>
+ */
+#ifndef _IFXMIPS_GPIO_H__
+#define _IFXMIPS_GPIO_H__
+
+extern int ifxmips_port_reserve_pin(unsigned int port, unsigned int pin);
+extern int ifxmips_port_free_pin(unsigned int port, unsigned int pin);
+extern int ifxmips_port_set_open_drain(unsigned int port, unsigned int pin);
+extern int ifxmips_port_clear_open_drain(unsigned int port, unsigned int pin);
+extern int ifxmips_port_set_pudsel(unsigned int port, unsigned int pin);
+extern int ifxmips_port_clear_pudsel(unsigned int port, unsigned int pin);
+extern int ifxmips_port_set_puden(unsigned int port, unsigned int pin);
+extern int ifxmips_port_clear_puden(unsigned int port, unsigned int pin);
+extern int ifxmips_port_set_stoff(unsigned int port, unsigned int pin);
+extern int ifxmips_port_clear_stoff(unsigned int port, unsigned int pin);
+extern int ifxmips_port_set_dir_out(unsigned int port, unsigned int pin);
+extern int ifxmips_port_set_dir_in(unsigned int port, unsigned int pin);
+extern int ifxmips_port_set_output(unsigned int port, unsigned int pin);
+extern int ifxmips_port_clear_output(unsigned int port, unsigned int pin);
+extern int ifxmips_port_get_input(unsigned int port, unsigned int pin);
+extern int ifxmips_port_set_altsel0(unsigned int port, unsigned int pin);
+extern int ifxmips_port_clear_altsel0(unsigned int port, unsigned int pin);
+extern int ifxmips_port_set_altsel1(unsigned int port, unsigned int pin);
+extern int ifxmips_port_clear_altsel1(unsigned int port, unsigned int pin);
+
+#endif
diff --git a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_gptu.h b/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_gptu.h
new file mode 100644 (file)
index 0000000..330c3cf
--- /dev/null
@@ -0,0 +1,155 @@
+#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
+#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
+
+
+/******************************************************************************
+       Copyright (c) 2002, Infineon Technologies.  All rights reserved.
+
+                               No Warranty
+   Because the program is licensed free of charge, there is no warranty for
+   the program, to the extent permitted by applicable law.  Except when
+   otherwise stated in writing the copyright holders and/or other parties
+   provide the program "as is" without warranty of any kind, either
+   expressed or implied, including, but not limited to, the implied
+   warranties of merchantability and fitness for a particular purpose. The
+   entire risk as to the quality and performance of the program is with
+   you.  should the program prove defective, you assume the cost of all
+   necessary servicing, repair or correction.
+
+   In no event unless required by applicable law or agreed to in writing
+   will any copyright holder, or any other party who may modify and/or
+   redistribute the program as permitted above, be liable to you for
+   damages, including any general, special, incidental or consequential
+   damages arising out of the use or inability to use the program
+   (including but not limited to loss of data or data being rendered
+   inaccurate or losses sustained by you or third parties or a failure of
+   the program to operate with any other programs), even if such holder or
+   other party has been advised of the possibility of such damages.
+******************************************************************************/
+
+
+/*
+ * ####################################
+ *              Definition
+ * ####################################
+ */
+
+/*
+ *  Available Timer/Counter Index
+ */
+#define TIMER(n, X)                     (n * 2 + (X ? 1 : 0))
+#define TIMER_ANY                       0x00
+#define TIMER1A                         TIMER(1, 0)
+#define TIMER1B                         TIMER(1, 1)
+#define TIMER2A                         TIMER(2, 0)
+#define TIMER2B                         TIMER(2, 1)
+#define TIMER3A                         TIMER(3, 0)
+#define TIMER3B                         TIMER(3, 1)
+
+/*
+ *  Flag of Timer/Counter
+ *  These flags specify the way in which timer is configured.
+ */
+/*  Bit size of timer/counter.                      */
+#define TIMER_FLAG_16BIT                0x0000
+#define TIMER_FLAG_32BIT                0x0001
+/*  Switch between timer and counter.               */
+#define TIMER_FLAG_TIMER                0x0000
+#define TIMER_FLAG_COUNTER              0x0002
+/*  Stop or continue when overflowing/underflowing. */
+#define TIMER_FLAG_ONCE                 0x0000
+#define TIMER_FLAG_CYCLIC               0x0004
+/*  Count up or counter down.                       */
+#define TIMER_FLAG_UP                   0x0000
+#define TIMER_FLAG_DOWN                 0x0008
+/*  Count on specific level or edge.                */
+#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000
+#define TIMER_FLAG_LOW_LEVEL_SENSITIVE  0x0040
+#define TIMER_FLAG_RISE_EDGE            0x0010
+#define TIMER_FLAG_FALL_EDGE            0x0020
+#define TIMER_FLAG_ANY_EDGE             0x0030
+/*  Signal is syncronous to module clock or not.    */
+#define TIMER_FLAG_UNSYNC               0x0000
+#define TIMER_FLAG_SYNC                 0x0080
+/*  Different interrupt handle type.                */
+#define TIMER_FLAG_NO_HANDLE            0x0000
+#if defined(__KERNEL__)
+    #define TIMER_FLAG_CALLBACK_IN_IRQ  0x0100
+#endif  //  defined(__KERNEL__)
+#define TIMER_FLAG_SIGNAL               0x0300
+/*  Internal clock source or external clock source  */
+#define TIMER_FLAG_INT_SRC              0x0000
+#define TIMER_FLAG_EXT_SRC              0x1000
+
+
+/*
+ *  ioctl Command
+ */
+#define GPTU_REQUEST_TIMER              0x01    /*  General method to setup timer/counter.  */
+#define GPTU_FREE_TIMER                 0x02    /*  Free timer/counter.                     */
+#define GPTU_START_TIMER                0x03    /*  Start or resume timer/counter.          */
+#define GPTU_STOP_TIMER                 0x04    /*  Suspend timer/counter.                  */
+#define GPTU_GET_COUNT_VALUE            0x05    /*  Get current count value.                */
+#define GPTU_CALCULATE_DIVIDER          0x06    /*  Calculate timer divider from given freq.*/
+#define GPTU_SET_TIMER                  0x07    /*  Simplified method to setup timer.       */
+#define GPTU_SET_COUNTER                0x08    /*  Simplified method to setup counter.     */
+
+/*
+ *  Data Type Used to Call ioctl
+ */
+struct gptu_ioctl_param {
+    unsigned int                        timer;  /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
+                                                 *  GPTU_SET_COUNTER, this field is ID of expected      *
+                                                 *  timer/counter. If it's zero, a timer/counter would  *
+                                                 *  be dynamically allocated and ID would be stored in  *
+                                                 *  this field.                                         *
+                                                 *  In command GPTU_GET_COUNT_VALUE, this field is      *
+                                                 *  ignored.                                            *
+                                                 *  In other command, this field is ID of timer/counter *
+                                                 *  allocated.                                          */
+    unsigned int                        flag;   /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
+                                                 *  GPTU_SET_COUNTER, this field contains flags to      *
+                                                 *  specify how to configure timer/counter.             *
+                                                 *  In command GPTU_START_TIMER, zero indicate start    *
+                                                 *  and non-zero indicate resume timer/counter.         *
+                                                 *  In other command, this field is ignored.            */
+    unsigned long                       value;  /*  In command GPTU_REQUEST_TIMER, this field contains  *
+                                                 *  init/reload value.                                  *
+                                                 *  In command GPTU_SET_TIMER, this field contains      *
+                                                 *  frequency (0.001Hz) of timer.                       *
+                                                 *  In command GPTU_GET_COUNT_VALUE, current count      *
+                                                 *  value would be stored in this field.                *
+                                                 *  In command GPTU_CALCULATE_DIVIDER, this field       *
+                                                 *  contains frequency wanted, and after calculation,   *
+                                                 *  divider would be stored in this field to overwrite  *
+                                                 *  the frequency.                                      *
+                                                 *  In other command, this field is ignored.            */
+    int                                 pid;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
+                                                 *  if signal is required, this field contains process  *
+                                                 *  ID to which signal would be sent.                   *
+                                                 *  In other command, this field is ignored.            */
+    int                                 sig;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
+                                                 *  if signal is required, this field contains signal   *
+                                                 *  number which would be sent.                         *
+                                                 *  In other command, this field is ignored.            */
+};
+
+/*
+ * ####################################
+ *              Data Type
+ * ####################################
+ */
+typedef void (*timer_callback)(unsigned long arg);
+
+extern int ifxmips_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
+extern int ifxmips_free_timer(unsigned int);
+extern int ifxmips_start_timer(unsigned int, int);
+extern int ifxmips_stop_timer(unsigned int);
+extern int ifxmips_reset_counter_flags(u32 timer, u32 flags);
+extern int ifxmips_get_count_value(unsigned int, unsigned long *);
+extern u32 ifxmips_cal_divider(unsigned long);
+extern int ifxmips_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
+extern int ifxmips_set_counter(unsigned int timer, unsigned int flag,
+       u32 reload, unsigned long arg1, unsigned long arg2);
+
+#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */
diff --git a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_irq.h b/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_irq.h
new file mode 100644 (file)
index 0000000..f84fdcb
--- /dev/null
@@ -0,0 +1,74 @@
+/*
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   Copyright (C) 2005 infineon
+ *   Copyright (C) 2007 John Crispin <blogic@openwrt.org>
+ */
+#ifndef _IFXMIPS_IRQ__
+#define _IFXMIPS_IRQ__
+
+#define INT_NUM_IRQ0                   8
+#define INT_NUM_IM0_IRL0               (INT_NUM_IRQ0 + 0)
+#define INT_NUM_IM1_IRL0               (INT_NUM_IRQ0 + 32)
+#define INT_NUM_IM2_IRL0               (INT_NUM_IRQ0 + 64)
+#define INT_NUM_IM3_IRL0               (INT_NUM_IRQ0 + 96)
+#define INT_NUM_IM4_IRL0               (INT_NUM_IRQ0 + 128)
+#define INT_NUM_IM_OFFSET              (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
+
+#define IFXMIPSASC_TIR(x)              (INT_NUM_IM3_IRL0 + (x * 7))
+#define IFXMIPSASC_RIR(x)              (INT_NUM_IM3_IRL0 + (x * 7) + 2)
+#define IFXMIPSASC_EIR(x)              (INT_NUM_IM3_IRL0 + (x * 7) + 3)
+
+#define IFXMIPS_SSC_TIR                        (INT_NUM_IM0_IRL0 + 15)
+#define IFXMIPS_SSC_RIR                        (INT_NUM_IM0_IRL0 + 14)
+#define IFXMIPS_SSC_EIR                        (INT_NUM_IM0_IRL0 + 16)
+
+#define IFXMIPS_MEI_INT                        (INT_NUM_IM1_IRL0 + 23)
+
+#define IFXMIPS_TIMER6_INT             (INT_NUM_IM1_IRL0 + 23)
+#define IFXMIPS_USB_OC_INT             (INT_NUM_IM4_IRL0 + 23)
+
+#define MIPS_CPU_TIMER_IRQ             7
+
+#define IFXMIPS_DMA_CH0_INT            (INT_NUM_IM2_IRL0)
+#define IFXMIPS_DMA_CH1_INT            (INT_NUM_IM2_IRL0 + 1)
+#define IFXMIPS_DMA_CH2_INT            (INT_NUM_IM2_IRL0 + 2)
+#define IFXMIPS_DMA_CH3_INT            (INT_NUM_IM2_IRL0 + 3)
+#define IFXMIPS_DMA_CH4_INT            (INT_NUM_IM2_IRL0 + 4)
+#define IFXMIPS_DMA_CH5_INT            (INT_NUM_IM2_IRL0 + 5)
+#define IFXMIPS_DMA_CH6_INT            (INT_NUM_IM2_IRL0 + 6)
+#define IFXMIPS_DMA_CH7_INT            (INT_NUM_IM2_IRL0 + 7)
+#define IFXMIPS_DMA_CH8_INT            (INT_NUM_IM2_IRL0 + 8)
+#define IFXMIPS_DMA_CH9_INT            (INT_NUM_IM2_IRL0 + 9)
+#define IFXMIPS_DMA_CH10_INT           (INT_NUM_IM2_IRL0 + 10)
+#define IFXMIPS_DMA_CH11_INT           (INT_NUM_IM2_IRL0 + 11)
+#define IFXMIPS_DMA_CH12_INT           (INT_NUM_IM2_IRL0 + 25)
+#define IFXMIPS_DMA_CH13_INT           (INT_NUM_IM2_IRL0 + 26)
+#define IFXMIPS_DMA_CH14_INT           (INT_NUM_IM2_IRL0 + 27)
+#define IFXMIPS_DMA_CH15_INT           (INT_NUM_IM2_IRL0 + 28)
+#define IFXMIPS_DMA_CH16_INT           (INT_NUM_IM2_IRL0 + 29)
+#define IFXMIPS_DMA_CH17_INT           (INT_NUM_IM2_IRL0 + 30)
+#define IFXMIPS_DMA_CH18_INT           (INT_NUM_IM2_IRL0 + 16)
+#define IFXMIPS_DMA_CH19_INT           (INT_NUM_IM2_IRL0 + 21)
+
+#define IFXMIPS_PPE_MBOX_INT           (INT_NUM_IM2_IRL0 + 24)
+
+#define IFXMIPS_USB_INT                        (INT_NUM_IM4_IRL0 + 22)
+#define IFXMIPS_USB_OC_INT             (INT_NUM_IM4_IRL0 + 23)
+
+
+extern void ifxmips_mask_and_ack_irq(unsigned int irq_nr);
+
+#endif
diff --git a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_led.h b/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_led.h
new file mode 100644 (file)
index 0000000..c97657a
--- /dev/null
@@ -0,0 +1,26 @@
+/*
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   Copyright (C) 2007 John Crispin <blogic@openwrt.org>
+ */
+#ifndef _IFXMIPS_LED_H__
+#define _IFXMIPS_LED_H__
+
+extern void ifxmips_led_set(unsigned int led);
+extern void ifxmips_led_clear(unsigned int led);
+extern void ifxmips_led_blink_set(unsigned int led);
+extern void ifxmips_led_blink_clear(unsigned int led);
+
+#endif
diff --git a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_pmu.h b/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_pmu.h
new file mode 100644 (file)
index 0000000..dd1f0d6
--- /dev/null
@@ -0,0 +1,32 @@
+/*
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   Copyright (C) 2007 John Crispin <blogic@openwrt.org>
+ */
+#ifndef _IFXMIPS_PMU_H__
+#define _IFXMIPS_PMU_H__
+
+
+#define IFXMIPS_PMU_PWDCR_DMA          0x0020
+#define IFXMIPS_PMU_PWDCR_USB          0x8041
+#define IFXMIPS_PMU_PWDCR_LED          0x0800
+#define IFXMIPS_PMU_PWDCR_GPT          0x1000
+#define IFXMIPS_PMU_PWDCR_PPE          0x2000
+#define IFXMIPS_PMU_PWDCR_FPI          0x4000
+
+void ifxmips_pmu_enable(unsigned int module);
+void ifxmips_pmu_disable(unsigned int module);
+
+#endif
diff --git a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_prom.h b/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_prom.h
new file mode 100644 (file)
index 0000000..e640ad7
--- /dev/null
@@ -0,0 +1,26 @@
+/*
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ *
+ *   Copyright (C) 2008 John Crispin <blogic@openwrt.org>
+ */
+#ifndef _IFXPROM_H__
+#define _IFXPROM_H__
+
+extern void prom_printf(const char *fmt, ...);
+extern u32 *prom_get_cp1_base(void);
+extern u32 prom_get_cp1_size(void);
+extern int ifxmips_has_brn_block(void);
+
+#endif
index e04c246..fde6357 100644 (file)
@@ -4,11 +4,11 @@
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/mm.h>
-#include <asm/ifxmips/ifxmips.h>
-#include <asm/ifxmips/ifxmips_irq.h>
 #include <asm/addrspace.h>
 #include <linux/vmalloc.h>
-#include <asm/ifxmips/ifxmips_ebu.h>
+#include <ifxmips.h>
+#include <ifxmips_irq.h>
+#include <ifxmips_ebu.h>
 
 #define IFXMIPS_PCI_CFG_BUSNUM_SHF 16
 #define IFXMIPS_PCI_CFG_DEVNUM_SHF 11
index 47bb1e6..e50cb3b 100644 (file)
@@ -4,11 +4,11 @@
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/mm.h>
-#include <asm/ifxmips/ifxmips.h>
-#include <asm/ifxmips/ifxmips_irq.h>
-#include <asm/mach-ifxmips/cgu.h>
 #include <asm/addrspace.h>
 #include <linux/vmalloc.h>
+#include <ifxmips.h>
+#include <ifxmips_irq.h>
+#include <ifxmips_cgu.h>
 
 #define IFXMIPS_PCI_MEM_BASE    0x18000000
 #define IFXMIPS_PCI_MEM_SIZE    0x02000000
@@ -49,6 +49,8 @@ static struct pci_controller ifxmips_pci_controller =
        .io_offset      = 0x00000000UL,
 };
 
+/* the cpu can can generate the 33Mhz or rely on an external clock the cgu needs the
+   proper setting, otherwise the cpu hangs. we have no way of runtime detecting this */
 u32 ifxmips_pci_mapped_cfg;
 int ifxmips_pci_external_clock = 0;
 
index 86116d6..3123d82 100644 (file)
@@ -31,9 +31,9 @@
 #include <linux/leds.h>
 #include <linux/delay.h>
 
-#include <asm/ifxmips/ifxmips.h>
-#include <asm/ifxmips/ifxmips_gpio.h>
-#include <asm/ifxmips/ifxmips_pmu.h>
+#include <ifxmips.h>
+#include <ifxmips_gpio.h>
+#include <ifxmips_pmu.h>
 
 #define DRVNAME                                        "ifxmips_led"
 
index 6498d12..3a3569a 100644 (file)
@@ -29,9 +29,9 @@
 #include <linux/magic.h>
 #include <linux/platform_device.h>
 
-#include <asm/ifxmips/ifxmips.h>
-#include <asm/ifxmips/ifxmips_prom.h>
-#include <asm/ifxmips/ifxmips_ebu.h>
+#include <ifxmips.h>
+#include <ifxmips_prom.h>
+#include <ifxmips_ebu.h>
 
 #ifndef CONFIG_MTD_PARTITIONS
 #error Please enable CONFIG_MTD_PARTITIONS
@@ -244,7 +244,7 @@ static int ifxmips_mtd_probe(struct platform_device *dev)
        add_mtd_partitions(ifxmips_mtd, &ifxmips_meta_partition, 1);
 
        printk(KERN_INFO "ifxmips_mtd: added %s flash with %dMB\n",
-               ifxmips_map.name, ifxmips_mtd->size >> 20);
+               ifxmips_map.name, ifxmips_mtd->size);
        return 0;
 }
 
index 43fe735..9af0e38 100644 (file)
 #include <linux/ethtool.h>
 #include <linux/init.h>
 #include <linux/delay.h>
+
 #include <asm/checksum.h>
-#include <asm/ifxmips/ifxmips.h>
-#include <asm/ifxmips/ifxmips_dma.h>
-#include <asm/ifxmips/ifxmips_pmu.h>
+
+#include <ifxmips.h>
+#include <ifxmips_dma.h>
+#include <ifxmips_pmu.h>
 
 struct ifxmips_mii_priv {
        struct net_device_stats stats;
index d6bf180..55bf41a 100644 (file)
@@ -48,8 +48,8 @@
 
 #include <asm/system.h>
 
-#include <asm/ifxmips/ifxmips.h>
-#include <asm/ifxmips/ifxmips_irq.h>
+#include <ifxmips.h>
+#include <ifxmips_irq.h>
 
 #define PORT_IFXMIPSASC  111
 
index d75eeea..b06307c 100644 (file)
@@ -25,8 +25,8 @@
 #include <linux/platform_device.h>
 #include <linux/uaccess.h>
 
-#include <asm/mach-ifxmips/cgu.h>
-#include <asm/ifxmips/ifxmips.h>
+#include <ifxmips.h>
+#include <ifxmips_cgu.h>
 
 #define IFXMIPS_WDT_PW1                        0x00BE0000
 #define IFXMIPS_WDT_PW2                        0x00DC0000
index 62a683d..1627269 100644 (file)
@@ -53,15 +53,6 @@ Index: linux-2.6.30.5/arch/mips/Makefile
  # DECstation family
  #
  core-$(CONFIG_MACH_DECSTATION)        += arch/mips/dec/
-Index: linux-2.6.30.5/arch/mips/pci/Makefile
-===================================================================
---- linux-2.6.30.5.orig/arch/mips/pci/Makefile 2009-09-02 22:12:48.000000000 +0200
-+++ linux-2.6.30.5/arch/mips/pci/Makefile      2009-09-02 22:12:53.000000000 +0200
-@@ -52,3 +52,4 @@
- obj-$(CONFIG_ZAO_CAPCELLA)    += fixup-capcella.o
- obj-$(CONFIG_WR_PPMC)         += fixup-wrppmc.o
- obj-$(CONFIG_MIKROTIK_RB532)  += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
-+obj-$(CONFIG_IFXMIPS)         += pci-ifxmips.o ops-ifxmips.o
 Index: linux-2.6.30.5/arch/mips/include/asm/bootinfo.h
 ===================================================================
 --- linux-2.6.30.5.orig/arch/mips/include/asm/bootinfo.h       2009-09-02 22:12:48.000000000 +0200
diff --git a/target/linux/ifxmips/patches-2.6.30/110-drivers.patch b/target/linux/ifxmips/patches-2.6.30/110-drivers.patch
deleted file mode 100644 (file)
index 1c2fd19..0000000
+++ /dev/null
@@ -1,139 +0,0 @@
-Index: linux-2.6.30.5/drivers/char/Makefile
-===================================================================
---- linux-2.6.30.5.orig/drivers/char/Makefile  2009-09-02 18:22:49.000000000 +0200
-+++ linux-2.6.30.5/drivers/char/Makefile       2009-09-02 18:29:51.000000000 +0200
-@@ -112,6 +112,10 @@
- obj-$(CONFIG_JS_RTC)          += js-rtc.o
- js-rtc-y = rtc.o
-+obj-$(CONFIG_IFXMIPS_SSC)  += ifxmips_ssc.o
-+obj-$(CONFIG_IFXMIPS_EEPROM)   += ifxmips_eeprom.o
-+obj-$(CONFIG_IFXMIPS_MEI)  += ifxmips_mei_core.o
-+
- # Files generated that shall be removed upon make clean
- clean-files := consolemap_deftbl.c defkeymap.c
-Index: linux-2.6.30.5/drivers/mtd/maps/Makefile
-===================================================================
---- linux-2.6.30.5.orig/drivers/mtd/maps/Makefile      2009-08-16 23:19:38.000000000 +0200
-+++ linux-2.6.30.5/drivers/mtd/maps/Makefile   2009-09-02 18:30:09.000000000 +0200
-@@ -62,3 +62,4 @@
- obj-$(CONFIG_MTD_BFIN_ASYNC)  += bfin-async-flash.o
- obj-$(CONFIG_MTD_RBTX4939)    += rbtx4939-flash.o
- obj-$(CONFIG_MTD_VMU)         += vmu-flash.o
-+obj-$(CONFIG_MTD_IFXMIPS)  += ifxmips.o
-Index: linux-2.6.30.5/drivers/net/Kconfig
-===================================================================
---- linux-2.6.30.5.orig/drivers/net/Kconfig    2009-09-02 18:22:49.000000000 +0200
-+++ linux-2.6.30.5/drivers/net/Kconfig 2009-09-02 18:29:51.000000000 +0200
-@@ -353,6 +353,12 @@
- source "drivers/net/arm/Kconfig"
-+config IFXMIPS_MII0
-+      tristate "Infineon IFXMips eth0 driver"
-+      depends on IFXMIPS
-+      help
-+        Support for the MII0 inside the IFXMips SOC
-+
- config AX88796
-       tristate "ASIX AX88796 NE2000 clone support"
-       depends on ARM || MIPS || SUPERH
-Index: linux-2.6.30.5/drivers/serial/Kconfig
-===================================================================
---- linux-2.6.30.5.orig/drivers/serial/Kconfig 2009-08-16 23:19:38.000000000 +0200
-+++ linux-2.6.30.5/drivers/serial/Kconfig      2009-09-02 18:29:51.000000000 +0200
-@@ -1365,6 +1365,14 @@
-       help
-         Support for Console on the NWP serial ports.
-+config SERIAL_IFXMIPS
-+      bool "IFXMips serial driver"
-+      depends on IFXMIPS
-+      select SERIAL_CORE
-+      select SERIAL_CORE_CONSOLE
-+      help
-+        Driver for the ifxmipss built in ASC hardware
-+
- config SERIAL_QE
-       tristate "Freescale QUICC Engine serial port support"
-       depends on QUICC_ENGINE
-Index: linux-2.6.30.5/drivers/serial/Makefile
-===================================================================
---- linux-2.6.30.5.orig/drivers/serial/Makefile        2009-08-16 23:19:38.000000000 +0200
-+++ linux-2.6.30.5/drivers/serial/Makefile     2009-09-02 18:29:51.000000000 +0200
-@@ -77,3 +77,4 @@
- obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o
- obj-$(CONFIG_KGDB_SERIAL_CONSOLE) += kgdboc.o
- obj-$(CONFIG_SERIAL_QE) += ucc_uart.o
-+obj-$(CONFIG_SERIAL_IFXMIPS) += ifxmips_asc.o
-Index: linux-2.6.30.5/drivers/watchdog/Makefile
-===================================================================
---- linux-2.6.30.5.orig/drivers/watchdog/Makefile      2009-08-16 23:19:38.000000000 +0200
-+++ linux-2.6.30.5/drivers/watchdog/Makefile   2009-09-02 18:29:51.000000000 +0200
-@@ -105,6 +105,7 @@
- obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o
- obj-$(CONFIG_AR7_WDT) += ar7_wdt.o
- obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
-+obj-$(CONFIG_IFXMIPS_WDT) += ifxmips_wdt.o
- # PARISC Architecture
-Index: linux-2.6.30.5/drivers/net/Makefile
-===================================================================
---- linux-2.6.30.5.orig/drivers/net/Makefile   2009-09-02 18:22:49.000000000 +0200
-+++ linux-2.6.30.5/drivers/net/Makefile        2009-09-02 18:30:37.000000000 +0200
-@@ -234,6 +234,7 @@
- obj-$(CONFIG_MLX4_CORE) += mlx4/
- obj-$(CONFIG_ENC28J60) += enc28j60.o
- obj-$(CONFIG_ETHOC) += ethoc.o
-+obj-$(CONFIG_IFXMIPS_MII0) += ifxmips_mii0.o
- obj-$(CONFIG_XTENSA_XT2000_SONIC) += xtsonic.o
-Index: linux-2.6.30.5/drivers/leds/Kconfig
-===================================================================
---- linux-2.6.30.5.orig/drivers/leds/Kconfig   2009-09-02 18:22:49.000000000 +0200
-+++ linux-2.6.30.5/drivers/leds/Kconfig        2009-09-02 18:29:51.000000000 +0200
-@@ -227,6 +227,12 @@
-         This option enables support for BD2802GU RGB LED driver chips
-         accessed via the I2C bus.
-+config LEDS_IFXMIPS
-+      tristate "LED Support for IFXMIPS  LEDs"
-+      depends on LEDS_CLASS && IFXMIPS
-+      help
-+        This option enables support for the CM-X270 LEDs.
-+
- comment "LED Triggers"
- config LEDS_TRIGGERS
-Index: linux-2.6.30.5/drivers/leds/Makefile
-===================================================================
---- linux-2.6.30.5.orig/drivers/leds/Makefile  2009-09-02 18:22:49.000000000 +0200
-+++ linux-2.6.30.5/drivers/leds/Makefile       2009-09-02 18:31:23.000000000 +0200
-@@ -27,6 +27,7 @@
- obj-$(CONFIG_LEDS_DA903X)             += leds-da903x.o
- obj-$(CONFIG_LEDS_WM8350)             += leds-wm8350.o
- obj-$(CONFIG_LEDS_PWM)                        += leds-pwm.o
-+obj-$(CONFIG_LEDS_IFXMIPS)            += leds-ifxmips.o
- # LED SPI Drivers
- obj-$(CONFIG_LEDS_DAC124S085)         += leds-dac124s085.o
-Index: linux-2.6.30.5/drivers/watchdog/Kconfig
-===================================================================
---- linux-2.6.30.5.orig/drivers/watchdog/Kconfig       2009-08-16 23:19:38.000000000 +0200
-+++ linux-2.6.30.5/drivers/watchdog/Kconfig    2009-09-02 18:29:51.000000000 +0200
-@@ -764,6 +764,12 @@
-       help
-         Hardware driver for the built-in watchdog timer on TXx9 MIPS SoCs.
-+config IFXMIPS_WDT
-+      bool "IFXMips watchdog"
-+      depends on IFXMIPS
-+      help
-+        Hardware driver for the IFXMIPS Watchdog Timer.
-+
- # PARISC Architecture
- # POWERPC Architecture
diff --git a/target/linux/ifxmips/patches-2.6.30/110-pci.patch b/target/linux/ifxmips/patches-2.6.30/110-pci.patch
new file mode 100644 (file)
index 0000000..fae887b
--- /dev/null
@@ -0,0 +1,9 @@
+Index: linux-2.6.30.5/arch/mips/pci/Makefile
+===================================================================
+--- linux-2.6.30.5.orig/arch/mips/pci/Makefile 2009-09-02 22:12:48.000000000 +0200
++++ linux-2.6.30.5/arch/mips/pci/Makefile      2009-09-02 22:12:53.000000000 +0200
+@@ -52,3 +52,4 @@
+ obj-$(CONFIG_ZAO_CAPCELLA)    += fixup-capcella.o
+ obj-$(CONFIG_WR_PPMC)         += fixup-wrppmc.o
+ obj-$(CONFIG_MIKROTIK_RB532)  += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
++obj-$(CONFIG_IFXMIPS)         += pci-ifxmips.o ops-ifxmips.o
diff --git a/target/linux/ifxmips/patches-2.6.30/120-serial.patch b/target/linux/ifxmips/patches-2.6.30/120-serial.patch
new file mode 100644 (file)
index 0000000..d012e44
--- /dev/null
@@ -0,0 +1,28 @@
+Index: linux-2.6.30.5/drivers/serial/Kconfig
+===================================================================
+--- linux-2.6.30.5.orig/drivers/serial/Kconfig 2009-08-16 23:19:38.000000000 +0200
++++ linux-2.6.30.5/drivers/serial/Kconfig      2009-09-02 18:29:51.000000000 +0200
+@@ -1365,6 +1365,14 @@
+       help
+         Support for Console on the NWP serial ports.
++config SERIAL_IFXMIPS
++      bool "IFXMips serial driver"
++      depends on IFXMIPS
++      select SERIAL_CORE
++      select SERIAL_CORE_CONSOLE
++      help
++        Driver for the ifxmipss built in ASC hardware
++
+ config SERIAL_QE
+       tristate "Freescale QUICC Engine serial port support"
+       depends on QUICC_ENGINE
+Index: linux-2.6.30.5/drivers/serial/Makefile
+===================================================================
+--- linux-2.6.30.5.orig/drivers/serial/Makefile        2009-08-16 23:19:38.000000000 +0200
++++ linux-2.6.30.5/drivers/serial/Makefile     2009-09-02 18:29:51.000000000 +0200
+@@ -77,3 +77,4 @@
+ obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o
+ obj-$(CONFIG_KGDB_SERIAL_CONSOLE) += kgdboc.o
+ obj-$(CONFIG_SERIAL_QE) += ucc_uart.o
++obj-$(CONFIG_SERIAL_IFXMIPS) += ifxmips_asc.o
diff --git a/target/linux/ifxmips/patches-2.6.30/130-ethernet.patch b/target/linux/ifxmips/patches-2.6.30/130-ethernet.patch
new file mode 100644 (file)
index 0000000..da87bb7
--- /dev/null
@@ -0,0 +1,29 @@
+Index: linux-2.6.30.5/drivers/net/Kconfig
+===================================================================
+--- linux-2.6.30.5.orig/drivers/net/Kconfig    2009-09-02 18:22:49.000000000 +0200
++++ linux-2.6.30.5/drivers/net/Kconfig 2009-09-02 18:29:51.000000000 +0200
+@@ -353,6 +353,12 @@
+ source "drivers/net/arm/Kconfig"
++config IFXMIPS_MII0
++      tristate "Infineon IFXMips eth0 driver"
++      depends on IFXMIPS
++      help
++        Support for the MII0 inside the IFXMips SOC
++
+ config AX88796
+       tristate "ASIX AX88796 NE2000 clone support"
+       depends on ARM || MIPS || SUPERH
+Index: linux-2.6.30.5/drivers/net/Makefile
+===================================================================
+--- linux-2.6.30.5.orig/drivers/net/Makefile   2009-09-02 18:22:49.000000000 +0200
++++ linux-2.6.30.5/drivers/net/Makefile        2009-09-02 18:30:37.000000000 +0200
+@@ -234,6 +234,7 @@
+ obj-$(CONFIG_MLX4_CORE) += mlx4/
+ obj-$(CONFIG_ENC28J60) += enc28j60.o
+ obj-$(CONFIG_ETHOC) += ethoc.o
++obj-$(CONFIG_IFXMIPS_MII0) += ifxmips_mii0.o
+ obj-$(CONFIG_XTENSA_XT2000_SONIC) += xtsonic.o
diff --git a/target/linux/ifxmips/patches-2.6.30/140-mtd.patch b/target/linux/ifxmips/patches-2.6.30/140-mtd.patch
new file mode 100644 (file)
index 0000000..55d4f89
--- /dev/null
@@ -0,0 +1,9 @@
+Index: linux-2.6.30.5/drivers/mtd/maps/Makefile
+===================================================================
+--- linux-2.6.30.5.orig/drivers/mtd/maps/Makefile      2009-08-16 23:19:38.000000000 +0200
++++ linux-2.6.30.5/drivers/mtd/maps/Makefile   2009-09-02 18:30:09.000000000 +0200
+@@ -62,3 +62,4 @@
+ obj-$(CONFIG_MTD_BFIN_ASYNC)  += bfin-async-flash.o
+ obj-$(CONFIG_MTD_RBTX4939)    += rbtx4939-flash.o
+ obj-$(CONFIG_MTD_VMU)         += vmu-flash.o
++obj-$(CONFIG_MTD_IFXMIPS)  += ifxmips.o
diff --git a/target/linux/ifxmips/patches-2.6.30/150-wdt.patch b/target/linux/ifxmips/patches-2.6.30/150-wdt.patch
new file mode 100644 (file)
index 0000000..9f58916
--- /dev/null
@@ -0,0 +1,29 @@
+Index: linux-2.6.30.5/drivers/watchdog/Makefile
+===================================================================
+--- linux-2.6.30.5.orig/drivers/watchdog/Makefile      2009-08-16 23:19:38.000000000 +0200
++++ linux-2.6.30.5/drivers/watchdog/Makefile   2009-09-02 18:29:51.000000000 +0200
+@@ -105,6 +105,7 @@
+ obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o
+ obj-$(CONFIG_AR7_WDT) += ar7_wdt.o
+ obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
++obj-$(CONFIG_IFXMIPS_WDT) += ifxmips_wdt.o
+ # PARISC Architecture
+Index: linux-2.6.30.5/drivers/watchdog/Kconfig
+===================================================================
+--- linux-2.6.30.5.orig/drivers/watchdog/Kconfig       2009-08-16 23:19:38.000000000 +0200
++++ linux-2.6.30.5/drivers/watchdog/Kconfig    2009-09-02 18:29:51.000000000 +0200
+@@ -764,6 +764,12 @@
+       help
+         Hardware driver for the built-in watchdog timer on TXx9 MIPS SoCs.
++config IFXMIPS_WDT
++      bool "IFXMips watchdog"
++      depends on IFXMIPS
++      help
++        Hardware driver for the IFXMIPS Watchdog Timer.
++
+ # PARISC Architecture
+ # POWERPC Architecture
diff --git a/target/linux/ifxmips/patches-2.6.30/160-cfi-swap.patch b/target/linux/ifxmips/patches-2.6.30/160-cfi-swap.patch
deleted file mode 100644 (file)
index 109f958..0000000
+++ /dev/null
@@ -1,15 +0,0 @@
-Index: linux-2.6.30.5/drivers/mtd/chips/cfi_cmdset_0002.c
-===================================================================
---- linux-2.6.30.5.orig/drivers/mtd/chips/cfi_cmdset_0002.c    2009-09-02 18:22:49.000000000 +0200
-+++ linux-2.6.30.5/drivers/mtd/chips/cfi_cmdset_0002.c 2009-09-02 18:31:31.000000000 +0200
-@@ -1090,7 +1090,9 @@
-       int retry_cnt = 0;
-       adr += chip->start;
--
-+#ifdef CONFIG_IFXMIPS
-+      adr ^= 2;
-+#endif
-       spin_lock(chip->mutex);
-       ret = get_chip(map, chip, adr, FL_WRITING);
-       if (ret) {
diff --git a/target/linux/ifxmips/patches-2.6.30/160-led.patch b/target/linux/ifxmips/patches-2.6.30/160-led.patch
new file mode 100644 (file)
index 0000000..aca11d5
--- /dev/null
@@ -0,0 +1,29 @@
+Index: linux-2.6.30.5/drivers/leds/Kconfig
+===================================================================
+--- linux-2.6.30.5.orig/drivers/leds/Kconfig   2009-09-02 18:22:49.000000000 +0200
++++ linux-2.6.30.5/drivers/leds/Kconfig        2009-09-02 18:29:51.000000000 +0200
+@@ -227,6 +227,12 @@
+         This option enables support for BD2802GU RGB LED driver chips
+         accessed via the I2C bus.
++config LEDS_IFXMIPS
++      tristate "LED Support for IFXMIPS  LEDs"
++      depends on LEDS_CLASS && IFXMIPS
++      help
++        This option enables support for the CM-X270 LEDs.
++
+ comment "LED Triggers"
+ config LEDS_TRIGGERS
+Index: linux-2.6.30.5/drivers/leds/Makefile
+===================================================================
+--- linux-2.6.30.5.orig/drivers/leds/Makefile  2009-09-02 18:22:49.000000000 +0200
++++ linux-2.6.30.5/drivers/leds/Makefile       2009-09-02 18:31:23.000000000 +0200
+@@ -27,6 +27,7 @@
+ obj-$(CONFIG_LEDS_DA903X)             += leds-da903x.o
+ obj-$(CONFIG_LEDS_WM8350)             += leds-wm8350.o
+ obj-$(CONFIG_LEDS_PWM)                        += leds-pwm.o
++obj-$(CONFIG_LEDS_IFXMIPS)            += leds-ifxmips.o
+ # LED SPI Drivers
+ obj-$(CONFIG_LEDS_DAC124S085)         += leds-dac124s085.o
diff --git a/target/linux/ifxmips/patches-2.6.30/170-dma_hack.patch b/target/linux/ifxmips/patches-2.6.30/170-dma_hack.patch
deleted file mode 100644 (file)
index 469dc74..0000000
+++ /dev/null
@@ -1,13 +0,0 @@
-Index: linux-2.6.30.5/arch/mips/mm/cache.c
-===================================================================
---- linux-2.6.30.5.orig/arch/mips/mm/cache.c   2009-09-02 18:31:37.000000000 +0200
-+++ linux-2.6.30.5/arch/mips/mm/cache.c        2009-09-02 18:31:42.000000000 +0200
-@@ -52,6 +52,8 @@
- void (*_dma_cache_inv)(unsigned long start, unsigned long size);
- EXPORT_SYMBOL(_dma_cache_wback_inv);
-+EXPORT_SYMBOL(_dma_cache_wback);
-+EXPORT_SYMBOL(_dma_cache_inv);
- #endif /* CONFIG_DMA_NONCOHERENT */
diff --git a/target/linux/ifxmips/patches-2.6.30/300-cfi-swap.patch b/target/linux/ifxmips/patches-2.6.30/300-cfi-swap.patch
new file mode 100644 (file)
index 0000000..109f958
--- /dev/null
@@ -0,0 +1,15 @@
+Index: linux-2.6.30.5/drivers/mtd/chips/cfi_cmdset_0002.c
+===================================================================
+--- linux-2.6.30.5.orig/drivers/mtd/chips/cfi_cmdset_0002.c    2009-09-02 18:22:49.000000000 +0200
++++ linux-2.6.30.5/drivers/mtd/chips/cfi_cmdset_0002.c 2009-09-02 18:31:31.000000000 +0200
+@@ -1090,7 +1090,9 @@
+       int retry_cnt = 0;
+       adr += chip->start;
+-
++#ifdef CONFIG_IFXMIPS
++      adr ^= 2;
++#endif
+       spin_lock(chip->mutex);
+       ret = get_chip(map, chip, adr, FL_WRITING);
+       if (ret) {