ralink: make the mt7621 irq core with with the new CM api
authorJohn Crispin <john@openwrt.org>
Thu, 12 Feb 2015 08:07:39 +0000 (08:07 +0000)
committerJohn Crispin <john@openwrt.org>
Thu, 12 Feb 2015 08:07:39 +0000 (08:07 +0000)
Signed-off-by: John Crispin <blogic@openwrt.org>
SVN-Revision: 44418

target/linux/ramips/mt7621/config-default
target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch

index c71a847..d95338d 100644 (file)
@@ -2,9 +2,11 @@ CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
 CONFIG_ARCH_DISCARD_MEMBLOCK=y
 CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
 CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+# CONFIG_ARCH_HAS_SG_CHAIN is not set
 CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
 CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
 CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
+# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
 CONFIG_ARCH_REQUIRE_GPIOLIB=y
 CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
 CONFIG_BOARD_SCACHE=y
@@ -26,11 +28,13 @@ CONFIG_CPU_MIPS32_R2=y
 CONFIG_CPU_MIPSR2=y
 CONFIG_CPU_MIPSR2_IRQ_EI=y
 CONFIG_CPU_MIPSR2_IRQ_VI=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
 CONFIG_CPU_R4K_CACHE_TLB=y
 CONFIG_CPU_R4K_FPU=y
 CONFIG_CPU_RMAP=y
 CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
 CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_MSA=y
 CONFIG_CSRC_R4K=y
 CONFIG_DEBUG_PINCTRL=y
 CONFIG_DMA_NONCOHERENT=y
@@ -44,7 +48,6 @@ CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 CONFIG_GENERIC_CMOS_UPDATE=y
 CONFIG_GENERIC_IO=y
 CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_NET_UTILS=y
 CONFIG_GENERIC_PCI_IOMAP=y
 CONFIG_GENERIC_SMP_IDLE_THREAD=y
 CONFIG_GPIOLIB=y
@@ -55,12 +58,14 @@ CONFIG_GPIO_SYSFS=y
 CONFIG_HARDWARE_WATCHPOINTS=y
 CONFIG_HAS_DMA=y
 CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
 # CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
 CONFIG_HAVE_ARCH_JUMP_LABEL=y
 CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
 CONFIG_HAVE_ARCH_TRACEHOOK=y
 # CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_BPF_JIT=y
 CONFIG_HAVE_CC_STACKPROTECTOR=y
 CONFIG_HAVE_CLK=y
 CONFIG_HAVE_CONTEXT_TRACKING=y
@@ -69,11 +74,11 @@ CONFIG_HAVE_DEBUG_KMEMLEAK=y
 CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
 CONFIG_HAVE_DMA_API_DEBUG=y
 CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
 CONFIG_HAVE_DYNAMIC_FTRACE=y
 CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
 CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
 CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
 CONFIG_HAVE_GENERIC_DMA_COHERENT=y
 CONFIG_HAVE_IDE=y
 CONFIG_HAVE_KVM=y
@@ -95,19 +100,21 @@ CONFIG_IRQ_DOMAIN=y
 CONFIG_IRQ_FORCED_THREADING=y
 CONFIG_IRQ_GIC=y
 CONFIG_IRQ_WORK=y
+CONFIG_KERNFS=y
+CONFIG_LIBFDT=y
 CONFIG_MDIO_BOARDINFO=y
 CONFIG_MIPS=y
+CONFIG_MIPS_CM=y
 CONFIG_MIPS_CMP=y
 CONFIG_MIPS_CPU_SCACHE=y
+CONFIG_MIPS_GIC_IPI=y
 # CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
 CONFIG_MIPS_L1_CACHE_SHIFT=6
 CONFIG_MIPS_L1_CACHE_SHIFT_6=y
 # CONFIG_MIPS_MACHINE is not set
 CONFIG_MIPS_MT=y
-# CONFIG_MIPS_MT_DISABLED is not set
 CONFIG_MIPS_MT_FPAFF=y
 CONFIG_MIPS_MT_SMP=y
-# CONFIG_MIPS_MT_SMTC is not set
 # CONFIG_MIPS_O32_FP64_SUPPORT is not set
 CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
 # CONFIG_MIPS_VPE_LOADER is not set
@@ -115,10 +122,10 @@ CONFIG_MODULES_USE_ELF_REL=y
 CONFIG_MT7621_WDT=y
 # CONFIG_MTD_CFI_INTELEXT is not set
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_M25P80=y
 CONFIG_MTD_PHYSMAP=y
 CONFIG_MTD_SPLIT_FIRMWARE=y
 CONFIG_MTD_SPLIT_SEAMA_FW=y
+CONFIG_MTD_SPLIT_SUPPORT=y
 CONFIG_MTD_SPLIT_TRX_FW=y
 CONFIG_MTD_SPLIT_UIMAGE_FW=y
 CONFIG_NEED_DMA_MAP_STATE=y
@@ -128,9 +135,11 @@ CONFIG_NET_RALINK_GSW_MT7620=y
 CONFIG_NET_RALINK_MDIO=y
 CONFIG_NET_RALINK_MT7620=y
 CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+# CONFIG_NO_IOPORT_MAP is not set
 CONFIG_NR_CPUS=4
 CONFIG_OF=y
 CONFIG_OF_ADDRESS=y
+CONFIG_OF_ADDRESS_PCI=y
 CONFIG_OF_EARLY_FLATTREE=y
 CONFIG_OF_FLATTREE=y
 CONFIG_OF_GPIO=y
@@ -146,16 +155,18 @@ CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
 CONFIG_PCI_DOMAINS=y
 CONFIG_PERF_USE_VMALLOC=y
 CONFIG_PHYLIB=y
-# CONFIG_PINCONF is not set
+# CONFIG_PHY_RALINK_USB is not set
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_RT2880=y
 # CONFIG_PINCTRL_SINGLE is not set
 CONFIG_POWER_RESET=y
 CONFIG_POWER_RESET_GPIO=y
+# CONFIG_POWER_RESET_GPIO_RESTART is not set
+# CONFIG_POWER_RESET_LTC2952 is not set
+# CONFIG_POWER_RESET_SYSCON is not set
 CONFIG_POWER_SUPPLY=y
 # CONFIG_PREEMPT_RCU is not set
 CONFIG_RALINK=y
-CONFIG_RALINK_USBPHY=y
 # CONFIG_RALINK_WDT is not set
 CONFIG_RCU_STALL_COMMON=y
 CONFIG_RESET_CONTROLLER=y
@@ -188,21 +199,16 @@ CONFIG_SYS_HAS_EARLY_PRINTK=y
 CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
 CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
 CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
 CONFIG_SYS_SUPPORTS_MIPS_CMP=y
 CONFIG_SYS_SUPPORTS_MULTITHREADING=y
 CONFIG_SYS_SUPPORTS_SCHED_SMT=y
 CONFIG_SYS_SUPPORTS_SMP=y
 CONFIG_TICK_CPU_ACCOUNTING=y
 CONFIG_TREE_RCU=y
-# CONFIG_USB_EHCI_HCD is not set
-CONFIG_USB_MT7621_XHCI_PLATFORM=y
-CONFIG_USB_PHY=y
 CONFIG_USB_SUPPORT=y
-# CONFIG_USB_UHCI_HCD is not set
-CONFIG_USB_XHCI_PLATFORM=y
 CONFIG_USE_OF=y
 CONFIG_WATCHDOG_CORE=y
 CONFIG_WEAK_ORDERING=y
 CONFIG_XPS=y
 CONFIG_ZONE_DMA_FLAG=0
-# CONFIG_MTK_MTD_NAND is not set
index 699c71c..0eebadb 100644 (file)
@@ -78,7 +78,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +#endif
 --- a/arch/mips/kernel/vmlinux.lds.S
 +++ b/arch/mips/kernel/vmlinux.lds.S
-@@ -51,6 +51,7 @@ SECTIONS
+@@ -51,6 +51,7 @@
        /* read-only */
        _text = .;      /* Text and read-only data */
        .text : {
@@ -88,7 +88,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
                LOCK_TEXT
 --- a/arch/mips/ralink/Kconfig
 +++ b/arch/mips/ralink/Kconfig
-@@ -7,6 +7,11 @@ config CLKEVT_RT3352
+@@ -7,6 +7,11 @@
        select CLKSRC_OF
        select CLKSRC_MMIO
  
@@ -100,7 +100,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  choice
        prompt "Ralink SoC selection"
        default SOC_RT305X
-@@ -28,6 +33,15 @@ choice
+@@ -28,6 +33,15 @@
        config SOC_MT7620
                bool "MT7620"
  
@@ -116,7 +116,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  endchoice
  
  choice
-@@ -59,6 +73,10 @@ choice
+@@ -59,6 +73,10 @@
                depends on SOC_MT7620
                select BUILTIN_DTB
  
@@ -154,7 +154,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
 --- a/arch/mips/ralink/Platform
 +++ b/arch/mips/ralink/Platform
-@@ -27,3 +27,8 @@ cflags-$(CONFIG_SOC_RT3883)  += -I$(srctr
+@@ -27,3 +27,8 @@
  #
  load-$(CONFIG_SOC_MT7620)     += 0xffffffff80000000
  cflags-$(CONFIG_SOC_MT7620)   += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7620
@@ -165,7 +165,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +cflags-$(CONFIG_SOC_MT7621)   += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7621
 --- /dev/null
 +++ b/arch/mips/ralink/irq-gic.c
-@@ -0,0 +1,271 @@
+@@ -0,0 +1,268 @@
 +#include <linux/init.h>
 +#include <linux/sched.h>
 +#include <linux/slab.h>
@@ -185,9 +185,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +#include <asm/setup.h>
 +
 +#include <asm/gic.h>
-+#include <asm/gcmpregs.h>
 +
 +#include <asm/mach-ralink/mt7621.h>
++#define GIC_BASE_ADDR                 0x1fbc0000
 +
 +unsigned long _gcmp_base;
 +static int gic_resched_int_base = 56;
@@ -241,7 +241,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +              gic_intr_map[i].pin = GIC_CPU_INT0;
 +              gic_intr_map[i].polarity = GIC_POL_POS;
 +              gic_intr_map[i].trigtype = GIC_TRIG_LEVEL;
-+              gic_intr_map[i].flags = GIC_FLAG_IPI;
++              gic_intr_map[i].flags = 0;
 +      }
 +
 +#if defined(CONFIG_MIPS_MT_SMP)
@@ -388,11 +388,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +      if (!_gcmp_base)
 +              panic("Failed to remap gcmp memory\n");
 +
-+      if ((GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) != gcmp.start)
-+              panic("Failed to find gcmp core\n");
-+
 +      /* tell the gcmp where to find the gic */
-+      GCMPGCB(GICBA) = gic.start | GCMP_GCB_GICBA_EN_MSK;
++      write_gcr_gic_base(GIC_BASE_ADDR | CM_GCR_GIC_BASE_GICEN_MSK);
 +      gic_present = 1;
 +      if (cpu_has_vint) {
 +              set_vi_handler(2, gic_irqdispatch);
@@ -523,7 +520,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +}
 --- /dev/null
 +++ b/arch/mips/ralink/mt7621.c
-@@ -0,0 +1,183 @@
+@@ -0,0 +1,192 @@
 +/*
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms of the GNU General Public License version 2 as published
@@ -539,10 +536,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +#include <linux/kernel.h>
 +#include <linux/init.h>
 +#include <linux/module.h>
-+#include <asm/gcmpregs.h>
 +
 +#include <asm/mipsregs.h>
 +#include <asm/smp-ops.h>
++#include <asm/mips-cm.h>
++#include <asm/mips-cpc.h>
 +#include <asm/mach-ralink/ralink_regs.h>
 +#include <asm/mach-ralink/mt7621.h>
 +
@@ -704,6 +702,34 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +
 +      rt2880_pinmux_data = mt7621_pinmux_data;
 +
-+      if (register_cmp_smp_ops())
-+              panic("failed to register_vsmp_smp_ops()");
++      /* Early detection of CMP support */
++      mips_cm_probe();
++      mips_cpc_probe();
++
++      if (!register_cps_smp_ops())
++              return;
++      if (!register_cmp_smp_ops())
++              return;
++      if (!register_vsmp_smp_ops())
++              return;
 +}
+--- a/arch/mips/kernel/mips-cm.c
++++ b/arch/mips/kernel/mips-cm.c
+@@ -105,7 +105,7 @@
+       write_gcr_base(base_reg);
+       /* disable CM regions */
+-      write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
++/*    write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
+       write_gcr_reg0_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
+       write_gcr_reg1_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
+       write_gcr_reg1_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
+@@ -113,7 +113,7 @@
+       write_gcr_reg2_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
+       write_gcr_reg3_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
+       write_gcr_reg3_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
+-
++*/
+       /* probe for an L2-only sync region */
+       mips_cm_probe_l2sync();