FEATURES:=jffs2 targz ubifs audio
SUBTARGETS:=qi_lb60 n516 n526
-LINUX_VERSION:=2.6.34.1
+LINUX_VERSION:=2.6.35
DEVICE_TYPE=other
--- /dev/null
+CONFIG_32BIT=y
+# CONFIG_64BIT is not set
+# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
+# CONFIG_AR7 is not set
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_ARPD is not set
+# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
+# CONFIG_BACKLIGHT_GENERIC is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+# CONFIG_BATTERY_JZ4740 is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_BCM63XX is not set
+CONFIG_BITREVERSE=y
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
+# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
+CONFIG_CHARGER_GPIO=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+# CONFIG_CPU_CAVIUM_OCTEON is not set
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+# CONFIG_CPU_LOONGSON2E is not set
+# CONFIG_CPU_LOONGSON2F is not set
+CONFIG_CPU_MIPS32_R1=y
+# CONFIG_CPU_MIPS32_R2 is not set
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+CONFIG_CPU_MIPSR1=y
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R5500 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_VR41XX is not set
+CONFIG_CRC16=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_DEFAULT_AS=y
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_ELF_CORE=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+CONFIG_FAT_FS=y
+# CONFIG_FB_JZ4740 is not set
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FONT_10x18 is not set
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_8x16 is not set
+# CONFIG_FONT_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_SUN12x22 is not set
+CONFIG_FONT_SUN8x16=y
+CONFIG_FONTS=y
+CONFIG_FORCE_MAX_ZONEORDER=12
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+CONFIG_FREEZER=y
+# CONFIG_INLINE_READ_UNLOCK is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_UNLOCK is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_UNLOCK is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
+CONFIG_INOTIFY_USER=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_GPIOLIB=y
+# CONFIG_HAMRADIO is not set
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_PWM=y
+# CONFIG_HIBERNATION is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_HW_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_GPIO_BUTTONS is not set
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT=y
+CONFIG_IRQ_CPU=y
+CONFIG_JBD=y
+# CONFIG_JZ4740_ADC is not set
+# CONFIG_JZ4740_N516 is not set
+# CONFIG_JZ4740_N526 is not set
+# CONFIG_JZ4740_QI_LB60 is not set
+CONFIG_JZRISC=y
+CONFIG_JZSOC=y
+CONFIG_KALLSYMS=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_LCD_CLASS_DEVICE is not set
+# CONFIG_LCD_GPM940B0 is not set
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_L4F00242T03 is not set
+# CONFIG_LCD_LMS283GF05 is not set
+# CONFIG_LCD_LTV350QV is not set
+# CONFIG_LCD_PLATFORM is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+# CONFIG_LEDS_PWM is not set
+CONFIG_LEGACY_PTY_COUNT=2
+CONFIG_LEGACY_PTYS=y
+CONFIG_LOCK_KERNEL=y
+# CONFIG_LOGO_LINUX_CLUT224 is not set
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+# CONFIG_LOGO_OPENWRT_CLUT224 is not set
+# CONFIG_LOGO is not set
+# CONFIG_LOONGSON_MC146818 is not set
+CONFIG_LOONGSON_UART_BASE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+CONFIG_MACH_JZ=y
+# CONFIG_MACH_LOONGSON is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_MINI_FO is not set
+# CONFIG_MIPS_COBALT is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_MACHINE is not set
+# CONFIG_MIPS_MALTA is not set
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+# CONFIG_MIPS_SIM is not set
+CONFIG_MIPS=y
+# CONFIG_MMC_AT91 is not set
+# CONFIG_MMC_ATMELMCI is not set
+# CONFIG_MMC_BLOCK_BOUNCE is not set
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_JZ=y
+CONFIG_MMC_UNSAFE_RESUME=y
+CONFIG_MMC=y
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_NAND_JZ4740=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_DEBUG is not set
+# CONFIG_MTD_UBI_GLUEBI is not set
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI=y
+# CONFIG_MTD_SM_COMMON is not set
+# CONFIG_N516_LPC is not set
+CONFIG_NEED_DMA_MAP_STATE=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NET_ETHERNET is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_CODEPAGE_1250=y
+CONFIG_NLS_CODEPAGE_1251=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=y
+CONFIG_NLS_CODEPAGE_775=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_855=y
+CONFIG_NLS_CODEPAGE_857=y
+CONFIG_NLS_CODEPAGE_860=y
+CONFIG_NLS_CODEPAGE_861=y
+CONFIG_NLS_CODEPAGE_862=y
+CONFIG_NLS_CODEPAGE_863=y
+CONFIG_NLS_CODEPAGE_864=y
+CONFIG_NLS_CODEPAGE_865=y
+CONFIG_NLS_CODEPAGE_866=y
+CONFIG_NLS_CODEPAGE_869=y
+CONFIG_NLS_CODEPAGE_874=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_949=y
+CONFIG_NLS_CODEPAGE_950=y
+CONFIG_NLS_ISO8859_13=y
+CONFIG_NLS_ISO8859_14=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_3=y
+CONFIG_NLS_ISO8859_4=y
+CONFIG_NLS_ISO8859_5=y
+CONFIG_NLS_ISO8859_6=y
+CONFIG_NLS_ISO8859_7=y
+CONFIG_NLS_ISO8859_8=y
+CONFIG_NLS_ISO8859_9=y
+CONFIG_NLS_KOI8_R=y
+CONFIG_NLS_KOI8_U=y
+CONFIG_NLS_UTF8=y
+CONFIG_NLS=y
+# CONFIG_NO_IOPORT is not set
+# CONFIG_NXP_STB220 is not set
+# CONFIG_NXP_STB225 is not set
+# CONFIG_PACKET_MMAP is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+# CONFIG_PCI is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_OPS=y
+# CONFIG_PM_RUNTIME is not set
+CONFIG_PM_SLEEP=y
+CONFIG_PM=y
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_POWERTV is not set
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT=y
+CONFIG_PRINTK_TIME=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DRV_CMOS is not set
+CONFIG_RTC_DRV_JZ4740=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_SCSI_MOD=y
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SDIO_UART is not set
+# CONFIG_SERIAL_8250_EXTENDED is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SND_SOC_ALL_CODECS is not set
+# CONFIG_SND_SOC_JZCODEC is not set
+# CONFIG_SND_SOC_JZ4740 is not set
+# CONFIG_SND_JZ4740_SOC_N516 is not set
+# CONFIG_SND_JZ4740_SOC_N526 is not set
+# CONFIG_SND_JZ4740_SOC_QI_LB60 is not set
+CONFIG_MACH_JZ4740=y
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_STAGING is not set
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_SUSPEND=y
+# CONFIG_SYN_COOKIES is not set
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+# CONFIG_TEST_POWER is not set
+CONFIG_TRAD_SIGNALS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
+# CONFIG_UBIFS_FS_DEBUG is not set
+CONFIG_UBIFS_FS_LZO=y
+# CONFIG_UBIFS_FS_XATTR is not set
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+# CONFIG_USB_ETH_EEM is not set
+CONFIG_USB_ETH_RNDIS=y
+CONFIG_USB_ETH=y
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_FUNCTIONFS is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_IMX is not set
+CONFIG_USB_GADGET_JZ4740=y
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+CONFIG_USB_GADGET_SELECTED=y
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET=y
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_G_SERIAL is not set
+CONFIG_USB_JZ4740=y
+# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_ZERO is not set
+CONFIG_VFAT_FS=y
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_VLAN_8021Q is not set
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_VT=y
+# CONFIG_WATCHDOG is not set
+# CONFIG_WLAN_80211 is not set
+CONFIG_ZONE_DMA_FLAG=0
SUBMENU:=$(SOUND_MENU)
DEPENDS:=kmod-sound-soc-core @TARGET_xburst
TITLE:=JZ4740 SoC internal codec support
- KCONFIG:=CONFIG_SND_SOC_JZCODEC
+ KCONFIG:=CONFIG_SND_SOC_JZCODEC CONFIG_SND_SOC_JZ4740_CODEC
FILES:=$(LINUX_DIR)/sound/soc/codecs/snd-soc-jzcodec.ko
AUTOLOAD:=$(call AutoLoad,60,snd-soc-jzcodec)
endef
--- /dev/null
+CONFIG_FB_DEFERRED_IO=y
+CONFIG_FB_JZ4740=y
+CONFIG_FB_METRONOME=m
+CONFIG_FB_SYS_FOPS=m
+CONFIG_HWMON=y
+# CONFIG_HWMON_DEBUG_CHIP is not set
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_GPIO=y
+CONFIG_JZ4740_N516=y
+CONFIG_LEDS_GPIO=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_N516_LPC=y
+CONFIG_NEW_LEDS=y
+CONFIG_SENSORS_LM75=y
--- /dev/null
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+CONFIG_JZ4740_N516=y
--- /dev/null
+From 2b3ca15058c974f2c20bd057a58a10c414b83fef Mon Sep 17 00:00:00 2001
+From: Lars-Peter Clausen <lars@metafoo.de>
+Date: Sat, 17 Jul 2010 11:07:51 +0000
+Subject: [PATCH] MIPS: JZ4740: Add base support for Ingenic JZ4740 System-on-a-Chip
+
+Adds a new cpu type for the JZ4740 to the Linux MIPS architecture code.
+It also adds the iomem addresses for the different components found on
+a JZ4740 SoC.
+
+Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
+Cc: linux-mips@linux-mips.org
+Cc: linux-kernel@vger.kernel.org
+Patchwork: https://patchwork.linux-mips.org/patch/1464/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/include/asm/bootinfo.h | 6 ++
+ arch/mips/include/asm/cpu.h | 9 +++-
+ arch/mips/include/asm/mach-jz4740/base.h | 26 ++++++++++
+ .../asm/mach-jz4740/cpu-feature-overrides.h | 51 ++++++++++++++++++++
+ arch/mips/include/asm/mach-jz4740/war.h | 25 ++++++++++
+ arch/mips/kernel/cpu-probe.c | 20 ++++++++
+ arch/mips/mm/tlbex.c | 5 ++
+ 7 files changed, 141 insertions(+), 1 deletions(-)
+ create mode 100644 arch/mips/include/asm/mach-jz4740/base.h
+ create mode 100644 arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h
+ create mode 100644 arch/mips/include/asm/mach-jz4740/war.h
+
+--- a/arch/mips/include/asm/bootinfo.h
++++ b/arch/mips/include/asm/bootinfo.h
+@@ -71,6 +71,12 @@
+ #define MACH_LEMOTE_LL2F 7
+ #define MACH_LOONGSON_END 8
+
++/*
++ * Valid machtype for group INGENIC
++ */
++#define MACH_INGENIC_JZ4730 0 /* JZ4730 SOC */
++#define MACH_INGENIC_JZ4740 1 /* JZ4740 SOC */
++
+ extern char *system_type;
+ const char *get_system_type(void);
+
+--- a/arch/mips/include/asm/cpu.h
++++ b/arch/mips/include/asm/cpu.h
+@@ -34,7 +34,7 @@
+ #define PRID_COMP_LSI 0x080000
+ #define PRID_COMP_LEXRA 0x0b0000
+ #define PRID_COMP_CAVIUM 0x0d0000
+-
++#define PRID_COMP_INGENIC 0xd00000
+
+ /*
+ * Assigned values for the product ID register. In order to detect a
+@@ -133,6 +133,12 @@
+ #define PRID_IMP_CAVIUM_CN52XX 0x0700
+
+ /*
++ * These are the PRID's for when 23:16 == PRID_COMP_INGENIC
++ */
++
++#define PRID_IMP_JZRISC 0x0200
++
++/*
+ * Definitions for 7:0 on legacy processors
+ */
+
+@@ -219,6 +225,7 @@ enum cpu_type_enum {
+ CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
+ CPU_ALCHEMY, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
+ CPU_BCM6338, CPU_BCM6345, CPU_BCM6348, CPU_BCM6358,
++ CPU_JZRISC,
+
+ /*
+ * MIPS64 class processors
+--- /dev/null
++++ b/arch/mips/include/asm/mach-jz4740/base.h
+@@ -0,0 +1,26 @@
++#ifndef __ASM_MACH_JZ4740_BASE_H__
++#define __ASM_MACH_JZ4740_BASE_H__
++
++#define JZ4740_CPM_BASE_ADDR 0x10000000
++#define JZ4740_INTC_BASE_ADDR 0x10001000
++#define JZ4740_WDT_BASE_ADDR 0x10002000
++#define JZ4740_TCU_BASE_ADDR 0x10002010
++#define JZ4740_RTC_BASE_ADDR 0x10003000
++#define JZ4740_GPIO_BASE_ADDR 0x10010000
++#define JZ4740_AIC_BASE_ADDR 0x10020000
++#define JZ4740_MSC_BASE_ADDR 0x10021000
++#define JZ4740_UART0_BASE_ADDR 0x10030000
++#define JZ4740_UART1_BASE_ADDR 0x10031000
++#define JZ4740_I2C_BASE_ADDR 0x10042000
++#define JZ4740_SSI_BASE_ADDR 0x10043000
++#define JZ4740_SADC_BASE_ADDR 0x10070000
++#define JZ4740_EMC_BASE_ADDR 0x13010000
++#define JZ4740_DMAC_BASE_ADDR 0x13020000
++#define JZ4740_UHC_BASE_ADDR 0x13030000
++#define JZ4740_UDC_BASE_ADDR 0x13040000
++#define JZ4740_LCD_BASE_ADDR 0x13050000
++#define JZ4740_SLCD_BASE_ADDR 0x13050000
++#define JZ4740_CIM_BASE_ADDR 0x13060000
++#define JZ4740_IPU_BASE_ADDR 0x13080000
++
++#endif
+--- /dev/null
++++ b/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h
+@@ -0,0 +1,51 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ */
++#ifndef __ASM_MACH_JZ4740_CPU_FEATURE_OVERRIDES_H
++#define __ASM_MACH_JZ4740_CPU_FEATURE_OVERRIDES_H
++
++#define cpu_has_tlb 1
++#define cpu_has_4kex 1
++#define cpu_has_3k_cache 0
++#define cpu_has_4k_cache 1
++#define cpu_has_tx39_cache 0
++#define cpu_has_fpu 0
++#define cpu_has_32fpr 0
++#define cpu_has_counter 0
++#define cpu_has_watch 1
++#define cpu_has_divec 1
++#define cpu_has_vce 0
++#define cpu_has_cache_cdex_p 0
++#define cpu_has_cache_cdex_s 0
++#define cpu_has_prefetch 1
++#define cpu_has_mcheck 1
++#define cpu_has_ejtag 1
++#define cpu_has_llsc 1
++#define cpu_has_mips16 0
++#define cpu_has_mdmx 0
++#define cpu_has_mips3d 0
++#define cpu_has_smartmips 0
++#define kernel_uses_llsc 1
++#define cpu_has_vtag_icache 1
++#define cpu_has_dc_aliases 0
++#define cpu_has_ic_fills_f_dc 0
++#define cpu_has_pindexed_dcache 0
++#define cpu_has_mips32r1 1
++#define cpu_has_mips32r2 0
++#define cpu_has_mips64r1 0
++#define cpu_has_mips64r2 0
++#define cpu_has_dsp 0
++#define cpu_has_mipsmt 0
++#define cpu_has_userlocal 0
++#define cpu_has_nofpuex 0
++#define cpu_has_64bits 0
++#define cpu_has_64bit_zero_reg 0
++#define cpu_has_inclusive_pcaches 0
++
++#define cpu_dcache_line_size() 32
++#define cpu_icache_line_size() 32
++
++#endif
+--- /dev/null
++++ b/arch/mips/include/asm/mach-jz4740/war.h
+@@ -0,0 +1,25 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
++ */
++#ifndef __ASM_MIPS_MACH_JZ4740_WAR_H
++#define __ASM_MIPS_MACH_JZ4740_WAR_H
++
++#define R4600_V1_INDEX_ICACHEOP_WAR 0
++#define R4600_V1_HIT_CACHEOP_WAR 0
++#define R4600_V2_HIT_CACHEOP_WAR 0
++#define R5432_CP0_INTERRUPT_WAR 0
++#define BCM1250_M3_WAR 0
++#define SIBYTE_1956_WAR 0
++#define MIPS4K_ICACHE_REFILL_WAR 0
++#define MIPS_CACHE_SYNC_WAR 0
++#define TX49XX_ICACHE_INDEX_INV_WAR 0
++#define RM9000_CDEX_SMP_WAR 0
++#define ICACHE_REFILLS_WORKAROUND_WAR 0
++#define R10000_LLSC_WAR 0
++#define MIPS34K_MISSED_ITLB_WAR 0
++
++#endif /* __ASM_MIPS_MACH_JZ4740_WAR_H */
+--- a/arch/mips/kernel/cpu-probe.c
++++ b/arch/mips/kernel/cpu-probe.c
+@@ -187,6 +187,7 @@ void __init check_wait(void)
+ case CPU_BCM6358:
+ case CPU_CAVIUM_OCTEON:
+ case CPU_CAVIUM_OCTEON_PLUS:
++ case CPU_JZRISC:
+ cpu_wait = r4k_wait;
+ break;
+
+@@ -956,6 +957,22 @@ platform:
+ }
+ }
+
++static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
++{
++ decode_configs(c);
++ /* JZRISC does not implement the CP0 counter. */
++ c->options &= ~MIPS_CPU_COUNTER;
++ switch (c->processor_id & 0xff00) {
++ case PRID_IMP_JZRISC:
++ c->cputype = CPU_JZRISC;
++ __cpu_name[cpu] = "Ingenic JZRISC";
++ break;
++ default:
++ panic("Unknown Ingenic Processor ID!");
++ break;
++ }
++}
++
+ const char *__cpu_name[NR_CPUS];
+ const char *__elf_platform;
+
+@@ -994,6 +1011,9 @@ __cpuinit void cpu_probe(void)
+ case PRID_COMP_CAVIUM:
+ cpu_probe_cavium(c, cpu);
+ break;
++ case PRID_COMP_INGENIC:
++ cpu_probe_ingenic(c, cpu);
++ break;
+ }
+
+ BUG_ON(!__cpu_name[cpu]);
+--- a/arch/mips/mm/tlbex.c
++++ b/arch/mips/mm/tlbex.c
+@@ -409,6 +409,11 @@ static void __cpuinit build_tlb_write_en
+ tlbw(p);
+ break;
+
++ case CPU_JZRISC:
++ tlbw(p);
++ uasm_i_nop(p);
++ break;
++
+ default:
+ panic("No TLB refill handler yet (CPU type: %d)",
+ current_cpu_data.cputype);
--- /dev/null
+From 296b9882edc2e6779e6c3d97f537166aa2334b93 Mon Sep 17 00:00:00 2001
+From: Lars-Peter Clausen <lars@metafoo.de>
+Date: Sat, 24 Apr 2010 17:34:29 +0200
+Subject: [PATCH] JZ4740 cache quirks
+
+---
+ arch/mips/include/asm/r4kcache.h | 231 ++++++++++++++++++++++++++++++++++++++
+ 1 files changed, 231 insertions(+), 0 deletions(-)
+
+--- a/arch/mips/include/asm/r4kcache.h
++++ b/arch/mips/include/asm/r4kcache.h
+@@ -17,6 +17,58 @@
+ #include <asm/cpu-features.h>
+ #include <asm/mipsmtregs.h>
+
++#ifdef CONFIG_JZRISC
++
++#define K0_TO_K1() \
++do { \
++ unsigned long __k0_addr; \
++ \
++ __asm__ __volatile__( \
++ "la %0, 1f\n\t" \
++ "or %0, %0, %1\n\t" \
++ "jr %0\n\t" \
++ "nop\n\t" \
++ "1: nop\n" \
++ : "=&r"(__k0_addr) \
++ : "r" (0x20000000) ); \
++} while(0)
++
++#define K1_TO_K0() \
++do { \
++ unsigned long __k0_addr; \
++ __asm__ __volatile__( \
++ "nop;nop;nop;nop;nop;nop;nop\n\t" \
++ "la %0, 1f\n\t" \
++ "jr %0\n\t" \
++ "nop\n\t" \
++ "1: nop\n" \
++ : "=&r" (__k0_addr)); \
++} while (0)
++
++#define INVALIDATE_BTB() \
++do { \
++ unsigned long tmp; \
++ __asm__ __volatile__( \
++ ".set mips32\n\t" \
++ "mfc0 %0, $16, 7\n\t" \
++ "nop\n\t" \
++ "ori %0, 2\n\t" \
++ "mtc0 %0, $16, 7\n\t" \
++ "nop\n\t" \
++ : "=&r" (tmp)); \
++} while (0)
++
++#define SYNC_WB() __asm__ __volatile__ ("sync")
++
++#else /* CONFIG_JZRISC */
++
++#define K0_TO_K1() do { } while (0)
++#define K1_TO_K0() do { } while (0)
++#define INVALIDATE_BTB() do { } while (0)
++#define SYNC_WB() do { } while (0)
++
++#endif /* CONFIG_JZRISC */
++
+ /*
+ * This macro return a properly sign-extended address suitable as base address
+ * for indexed cache operations. Two issues here:
+@@ -144,6 +196,7 @@ static inline void flush_icache_line_ind
+ {
+ __iflush_prologue
+ cache_op(Index_Invalidate_I, addr);
++ INVALIDATE_BTB();
+ __iflush_epilogue
+ }
+
+@@ -151,6 +204,7 @@ static inline void flush_dcache_line_ind
+ {
+ __dflush_prologue
+ cache_op(Index_Writeback_Inv_D, addr);
++ SYNC_WB();
+ __dflush_epilogue
+ }
+
+@@ -163,6 +217,7 @@ static inline void flush_icache_line(uns
+ {
+ __iflush_prologue
+ cache_op(Hit_Invalidate_I, addr);
++ INVALIDATE_BTB();
+ __iflush_epilogue
+ }
+
+@@ -170,6 +225,7 @@ static inline void flush_dcache_line(uns
+ {
+ __dflush_prologue
+ cache_op(Hit_Writeback_Inv_D, addr);
++ SYNC_WB();
+ __dflush_epilogue
+ }
+
+@@ -177,6 +233,7 @@ static inline void invalidate_dcache_lin
+ {
+ __dflush_prologue
+ cache_op(Hit_Invalidate_D, addr);
++ SYNC_WB();
+ __dflush_epilogue
+ }
+
+@@ -209,6 +266,7 @@ static inline void flush_scache_line(uns
+ static inline void protected_flush_icache_line(unsigned long addr)
+ {
+ protected_cache_op(Hit_Invalidate_I, addr);
++ INVALIDATE_BTB();
+ }
+
+ /*
+@@ -220,6 +278,7 @@ static inline void protected_flush_icach
+ static inline void protected_writeback_dcache_line(unsigned long addr)
+ {
+ protected_cache_op(Hit_Writeback_Inv_D, addr);
++ SYNC_WB();
+ }
+
+ static inline void protected_writeback_scache_line(unsigned long addr)
+@@ -396,8 +455,10 @@ static inline void blast_##pfx##cache##l
+ __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
+ __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
+ __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
++#ifndef CONFIG_JZRISC
+ __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
+ __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
++#endif
+ __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
+ __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64)
+ __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
+@@ -405,12 +466,122 @@ __BUILD_BLAST_CACHE(s, scache, Index_Wri
+ __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
+
+ __BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16)
++#ifndef CONFIG_JZRISC
+ __BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32)
++#endif
+ __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16)
+ __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32)
+ __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64)
+ __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128)
+
++#ifdef CONFIG_JZRISC
++
++static inline void blast_dcache32(void)
++{
++ unsigned long start = INDEX_BASE;
++ unsigned long end = start + current_cpu_data.dcache.waysize;
++ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
++ unsigned long ws_end = current_cpu_data.dcache.ways <<
++ current_cpu_data.dcache.waybit;
++ unsigned long ws, addr;
++
++ for (ws = 0; ws < ws_end; ws += ws_inc)
++ for (addr = start; addr < end; addr += 0x400)
++ cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
++
++ SYNC_WB();
++}
++
++static inline void blast_dcache32_page(unsigned long page)
++{
++ unsigned long start = page;
++ unsigned long end = page + PAGE_SIZE;
++
++ do {
++ cache32_unroll32(start,Hit_Writeback_Inv_D);
++ start += 0x400;
++ } while (start < end);
++
++ SYNC_WB();
++}
++
++static inline void blast_dcache32_page_indexed(unsigned long page)
++{
++ unsigned long indexmask = current_cpu_data.dcache.waysize - 1;
++ unsigned long start = INDEX_BASE + (page & indexmask);
++ unsigned long end = start + PAGE_SIZE;
++ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
++ unsigned long ws_end = current_cpu_data.dcache.ways <<
++ current_cpu_data.dcache.waybit;
++ unsigned long ws, addr;
++
++ for (ws = 0; ws < ws_end; ws += ws_inc)
++ for (addr = start; addr < end; addr += 0x400)
++ cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
++
++ SYNC_WB();
++}
++
++static inline void blast_icache32(void)
++{
++ unsigned long start = INDEX_BASE;
++ unsigned long end = start + current_cpu_data.icache.waysize;
++ unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
++ unsigned long ws_end = current_cpu_data.icache.ways <<
++ current_cpu_data.icache.waybit;
++ unsigned long ws, addr;
++
++ K0_TO_K1();
++
++ for (ws = 0; ws < ws_end; ws += ws_inc)
++ for (addr = start; addr < end; addr += 0x400)
++ cache32_unroll32(addr|ws,Index_Invalidate_I);
++
++ INVALIDATE_BTB();
++
++ K1_TO_K0();
++}
++
++static inline void blast_icache32_page(unsigned long page)
++{
++ unsigned long start = page;
++ unsigned long end = page + PAGE_SIZE;
++
++ K0_TO_K1();
++
++ do {
++ cache32_unroll32(start,Hit_Invalidate_I);
++ start += 0x400;
++ } while (start < end);
++
++ INVALIDATE_BTB();
++
++ K1_TO_K0();
++}
++
++static inline void blast_icache32_page_indexed(unsigned long page)
++{
++ unsigned long indexmask = current_cpu_data.icache.waysize - 1;
++ unsigned long start = INDEX_BASE + (page & indexmask);
++ unsigned long end = start + PAGE_SIZE;
++ unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
++ unsigned long ws_end = current_cpu_data.icache.ways <<
++ current_cpu_data.icache.waybit;
++ unsigned long ws, addr;
++
++ K0_TO_K1();
++
++ for (ws = 0; ws < ws_end; ws += ws_inc)
++ for (addr = start; addr < end; addr += 0x400)
++ cache32_unroll32(addr|ws,Index_Invalidate_I);
++
++ INVALIDATE_BTB();
++
++ K1_TO_K0();
++}
++
++#endif /* CONFIG_JZRISC */
++
+ /* build blast_xxx_range, protected_blast_xxx_range */
+ #define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
+ static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
+@@ -432,13 +603,73 @@ static inline void prot##blast_##pfx##ca
+ __##pfx##flush_epilogue \
+ }
+
++#ifndef CONFIG_JZRISC
+ __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
++#endif
+ __BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
++#ifndef CONFIG_JZRISC
+ __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
+ __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
++#endif
+ __BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
+ /* blast_inv_dcache_range */
+ __BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
+ __BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
+
++#ifdef CONFIG_JZRISC
++
++static inline void protected_blast_dcache_range(unsigned long start,
++ unsigned long end)
++{
++ unsigned long lsize = cpu_dcache_line_size();
++ unsigned long addr = start & ~(lsize - 1);
++ unsigned long aend = (end - 1) & ~(lsize - 1);
++
++ while (1) {
++ protected_cache_op(Hit_Writeback_Inv_D, addr);
++ if (addr == aend)
++ break;
++ addr += lsize;
++ }
++ SYNC_WB();
++}
++
++static inline void protected_blast_icache_range(unsigned long start,
++ unsigned long end)
++{
++ unsigned long lsize = cpu_icache_line_size();
++ unsigned long addr = start & ~(lsize - 1);
++ unsigned long aend = (end - 1) & ~(lsize - 1);
++
++ K0_TO_K1();
++
++ while (1) {
++ protected_cache_op(Hit_Invalidate_I, addr);
++ if (addr == aend)
++ break;
++ addr += lsize;
++ }
++ INVALIDATE_BTB();
++
++ K1_TO_K0();
++}
++
++static inline void blast_dcache_range(unsigned long start,
++ unsigned long end)
++{
++ unsigned long lsize = cpu_dcache_line_size();
++ unsigned long addr = start & ~(lsize - 1);
++ unsigned long aend = (end - 1) & ~(lsize - 1);
++
++ while (1) {
++ cache_op(Hit_Writeback_Inv_D, addr);
++ if (addr == aend)
++ break;
++ addr += lsize;
++ }
++ SYNC_WB();
++}
++
++#endif /* CONFIG_JZRISC */
++
+ #endif /* _ASM_R4KCACHE_H */
--- /dev/null
+From dd6ffa07b42d40ff680ce9bce34da88cf8920837 Mon Sep 17 00:00:00 2001
+From: Lars-Peter Clausen <lars@metafoo.de>
+Date: Sat, 17 Jul 2010 11:10:00 +0000
+Subject: [PATCH] MIPS: JZ4740: Add clock API support.
+
+Add support for managing the clocks found on JZ4740 SoC through the
+Linux clock API.
+
+Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
+Cc: linux-mips@linux-mips.org
+Cc: linux-kernel@vger.kernel.org
+Patchwork: https://patchwork.linux-mips.org/patch/1466/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/include/asm/mach-jz4740/clock.h | 28 +
+ arch/mips/jz4740/clock-debugfs.c | 109 ++++
+ arch/mips/jz4740/clock.c | 924 +++++++++++++++++++++++++++++
+ arch/mips/jz4740/clock.h | 76 +++
+ 4 files changed, 1137 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/include/asm/mach-jz4740/clock.h
+ create mode 100644 arch/mips/jz4740/clock-debugfs.c
+ create mode 100644 arch/mips/jz4740/clock.c
+ create mode 100644 arch/mips/jz4740/clock.h
+
+--- /dev/null
++++ b/arch/mips/include/asm/mach-jz4740/clock.h
+@@ -0,0 +1,28 @@
++/*
++ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#ifndef __ASM_JZ4740_CLOCK_H__
++#define __ASM_JZ4740_CLOCK_H__
++
++enum jz4740_wait_mode {
++ JZ4740_WAIT_MODE_IDLE,
++ JZ4740_WAIT_MODE_SLEEP,
++};
++
++void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode);
++
++void jz4740_clock_udc_enable_auto_suspend(void);
++void jz4740_clock_udc_disable_auto_suspend(void);
++
++#endif
+--- /dev/null
++++ b/arch/mips/jz4740/clock-debugfs.c
+@@ -0,0 +1,109 @@
++/*
++ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
++ * JZ4740 SoC clock support debugfs entries
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/clk.h>
++#include <linux/err.h>
++
++#include <linux/debugfs.h>
++#include <linux/uaccess.h>
++
++#include <asm/mach-jz4740/clock.h>
++#include "clock.h"
++
++static struct dentry *jz4740_clock_debugfs;
++
++static int jz4740_clock_debugfs_show_enabled(void *data, uint64_t *value)
++{
++ struct clk *clk = data;
++ *value = clk_is_enabled(clk);
++
++ return 0;
++}
++
++static int jz4740_clock_debugfs_set_enabled(void *data, uint64_t value)
++{
++ struct clk *clk = data;
++
++ if (value)
++ return clk_enable(clk);
++ else
++ clk_disable(clk);
++
++ return 0;
++}
++
++DEFINE_SIMPLE_ATTRIBUTE(jz4740_clock_debugfs_ops_enabled,
++ jz4740_clock_debugfs_show_enabled,
++ jz4740_clock_debugfs_set_enabled,
++ "%llu\n");
++
++static int jz4740_clock_debugfs_show_rate(void *data, uint64_t *value)
++{
++ struct clk *clk = data;
++ *value = clk_get_rate(clk);
++
++ return 0;
++}
++
++DEFINE_SIMPLE_ATTRIBUTE(jz4740_clock_debugfs_ops_rate,
++ jz4740_clock_debugfs_show_rate,
++ NULL,
++ "%llu\n");
++
++void jz4740_clock_debugfs_add_clk(struct clk *clk)
++{
++ if (!jz4740_clock_debugfs)
++ return;
++
++ clk->debugfs_entry = debugfs_create_dir(clk->name, jz4740_clock_debugfs);
++ debugfs_create_file("rate", S_IWUGO | S_IRUGO, clk->debugfs_entry, clk,
++ &jz4740_clock_debugfs_ops_rate);
++ debugfs_create_file("enabled", S_IRUGO, clk->debugfs_entry, clk,
++ &jz4740_clock_debugfs_ops_enabled);
++
++ if (clk->parent) {
++ char parent_path[100];
++ snprintf(parent_path, 100, "../%s", clk->parent->name);
++ clk->debugfs_parent_entry = debugfs_create_symlink("parent",
++ clk->debugfs_entry,
++ parent_path);
++ }
++}
++
++/* TODO: Locking */
++void jz4740_clock_debugfs_update_parent(struct clk *clk)
++{
++ if (clk->debugfs_parent_entry)
++ debugfs_remove(clk->debugfs_parent_entry);
++
++ if (clk->parent) {
++ char parent_path[100];
++ snprintf(parent_path, 100, "../%s", clk->parent->name);
++ clk->debugfs_parent_entry = debugfs_create_symlink("parent",
++ clk->debugfs_entry,
++ parent_path);
++ } else {
++ clk->debugfs_parent_entry = NULL;
++ }
++}
++
++void jz4740_clock_debugfs_init(void)
++{
++ jz4740_clock_debugfs = debugfs_create_dir("jz4740-clock", NULL);
++ if (IS_ERR(jz4740_clock_debugfs))
++ jz4740_clock_debugfs = NULL;
++}
+--- /dev/null
++++ b/arch/mips/jz4740/clock.c
+@@ -0,0 +1,924 @@
++/*
++ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
++ * JZ4740 SoC clock support
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/errno.h>
++#include <linux/clk.h>
++#include <linux/spinlock.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/list.h>
++#include <linux/err.h>
++
++#include <asm/mach-jz4740/clock.h>
++#include <asm/mach-jz4740/base.h>
++
++#include "clock.h"
++
++#define JZ_REG_CLOCK_CTRL 0x00
++#define JZ_REG_CLOCK_LOW_POWER 0x04
++#define JZ_REG_CLOCK_PLL 0x10
++#define JZ_REG_CLOCK_GATE 0x20
++#define JZ_REG_CLOCK_SLEEP_CTRL 0x24
++#define JZ_REG_CLOCK_I2S 0x60
++#define JZ_REG_CLOCK_LCD 0x64
++#define JZ_REG_CLOCK_MMC 0x68
++#define JZ_REG_CLOCK_UHC 0x6C
++#define JZ_REG_CLOCK_SPI 0x74
++
++#define JZ_CLOCK_CTRL_I2S_SRC_PLL BIT(31)
++#define JZ_CLOCK_CTRL_KO_ENABLE BIT(30)
++#define JZ_CLOCK_CTRL_UDC_SRC_PLL BIT(29)
++#define JZ_CLOCK_CTRL_UDIV_MASK 0x1f800000
++#define JZ_CLOCK_CTRL_CHANGE_ENABLE BIT(22)
++#define JZ_CLOCK_CTRL_PLL_HALF BIT(21)
++#define JZ_CLOCK_CTRL_LDIV_MASK 0x001f0000
++#define JZ_CLOCK_CTRL_UDIV_OFFSET 23
++#define JZ_CLOCK_CTRL_LDIV_OFFSET 16
++#define JZ_CLOCK_CTRL_MDIV_OFFSET 12
++#define JZ_CLOCK_CTRL_PDIV_OFFSET 8
++#define JZ_CLOCK_CTRL_HDIV_OFFSET 4
++#define JZ_CLOCK_CTRL_CDIV_OFFSET 0
++
++#define JZ_CLOCK_GATE_UART0 BIT(0)
++#define JZ_CLOCK_GATE_TCU BIT(1)
++#define JZ_CLOCK_GATE_RTC BIT(2)
++#define JZ_CLOCK_GATE_I2C BIT(3)
++#define JZ_CLOCK_GATE_SPI BIT(4)
++#define JZ_CLOCK_GATE_AIC BIT(5)
++#define JZ_CLOCK_GATE_I2S BIT(6)
++#define JZ_CLOCK_GATE_MMC BIT(7)
++#define JZ_CLOCK_GATE_ADC BIT(8)
++#define JZ_CLOCK_GATE_CIM BIT(9)
++#define JZ_CLOCK_GATE_LCD BIT(10)
++#define JZ_CLOCK_GATE_UDC BIT(11)
++#define JZ_CLOCK_GATE_DMAC BIT(12)
++#define JZ_CLOCK_GATE_IPU BIT(13)
++#define JZ_CLOCK_GATE_UHC BIT(14)
++#define JZ_CLOCK_GATE_UART1 BIT(15)
++
++#define JZ_CLOCK_I2S_DIV_MASK 0x01ff
++
++#define JZ_CLOCK_LCD_DIV_MASK 0x01ff
++
++#define JZ_CLOCK_MMC_DIV_MASK 0x001f
++
++#define JZ_CLOCK_UHC_DIV_MASK 0x000f
++
++#define JZ_CLOCK_SPI_SRC_PLL BIT(31)
++#define JZ_CLOCK_SPI_DIV_MASK 0x000f
++
++#define JZ_CLOCK_PLL_M_MASK 0x01ff
++#define JZ_CLOCK_PLL_N_MASK 0x001f
++#define JZ_CLOCK_PLL_OD_MASK 0x0003
++#define JZ_CLOCK_PLL_STABLE BIT(10)
++#define JZ_CLOCK_PLL_BYPASS BIT(9)
++#define JZ_CLOCK_PLL_ENABLED BIT(8)
++#define JZ_CLOCK_PLL_STABLIZE_MASK 0x000f
++#define JZ_CLOCK_PLL_M_OFFSET 23
++#define JZ_CLOCK_PLL_N_OFFSET 18
++#define JZ_CLOCK_PLL_OD_OFFSET 16
++
++#define JZ_CLOCK_LOW_POWER_MODE_DOZE BIT(2)
++#define JZ_CLOCK_LOW_POWER_MODE_SLEEP BIT(0)
++
++#define JZ_CLOCK_SLEEP_CTRL_SUSPEND_UHC BIT(7)
++#define JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC BIT(6)
++
++static void __iomem *jz_clock_base;
++static spinlock_t jz_clock_lock;
++static LIST_HEAD(jz_clocks);
++
++struct main_clk {
++ struct clk clk;
++ uint32_t div_offset;
++};
++
++struct divided_clk {
++ struct clk clk;
++ uint32_t reg;
++ uint32_t mask;
++};
++
++struct static_clk {
++ struct clk clk;
++ unsigned long rate;
++};
++
++static uint32_t jz_clk_reg_read(int reg)
++{
++ return readl(jz_clock_base + reg);
++}
++
++static void jz_clk_reg_write_mask(int reg, uint32_t val, uint32_t mask)
++{
++ uint32_t val2;
++
++ spin_lock(&jz_clock_lock);
++ val2 = readl(jz_clock_base + reg);
++ val2 &= ~mask;
++ val2 |= val;
++ writel(val2, jz_clock_base + reg);
++ spin_unlock(&jz_clock_lock);
++}
++
++static void jz_clk_reg_set_bits(int reg, uint32_t mask)
++{
++ uint32_t val;
++
++ spin_lock(&jz_clock_lock);
++ val = readl(jz_clock_base + reg);
++ val |= mask;
++ writel(val, jz_clock_base + reg);
++ spin_unlock(&jz_clock_lock);
++}
++
++static void jz_clk_reg_clear_bits(int reg, uint32_t mask)
++{
++ uint32_t val;
++
++ spin_lock(&jz_clock_lock);
++ val = readl(jz_clock_base + reg);
++ val &= ~mask;
++ writel(val, jz_clock_base + reg);
++ spin_unlock(&jz_clock_lock);
++}
++
++static int jz_clk_enable_gating(struct clk *clk)
++{
++ if (clk->gate_bit == JZ4740_CLK_NOT_GATED)
++ return -EINVAL;
++
++ jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, clk->gate_bit);
++ return 0;
++}
++
++static int jz_clk_disable_gating(struct clk *clk)
++{
++ if (clk->gate_bit == JZ4740_CLK_NOT_GATED)
++ return -EINVAL;
++
++ jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, clk->gate_bit);
++ return 0;
++}
++
++static int jz_clk_is_enabled_gating(struct clk *clk)
++{
++ if (clk->gate_bit == JZ4740_CLK_NOT_GATED)
++ return 1;
++
++ return !(jz_clk_reg_read(JZ_REG_CLOCK_GATE) & clk->gate_bit);
++}
++
++static unsigned long jz_clk_static_get_rate(struct clk *clk)
++{
++ return ((struct static_clk *)clk)->rate;
++}
++
++static int jz_clk_ko_enable(struct clk *clk)
++{
++ jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_KO_ENABLE);
++ return 0;
++}
++
++static int jz_clk_ko_disable(struct clk *clk)
++{
++ jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_KO_ENABLE);
++ return 0;
++}
++
++static int jz_clk_ko_is_enabled(struct clk *clk)
++{
++ return !!(jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_KO_ENABLE);
++}
++
++static const int pllno[] = {1, 2, 2, 4};
++
++static unsigned long jz_clk_pll_get_rate(struct clk *clk)
++{
++ uint32_t val;
++ int m;
++ int n;
++ int od;
++
++ val = jz_clk_reg_read(JZ_REG_CLOCK_PLL);
++
++ if (val & JZ_CLOCK_PLL_BYPASS)
++ return clk_get_rate(clk->parent);
++
++ m = ((val >> 23) & 0x1ff) + 2;
++ n = ((val >> 18) & 0x1f) + 2;
++ od = (val >> 16) & 0x3;
++
++ return ((clk_get_rate(clk->parent) / n) * m) / pllno[od];
++}
++
++static unsigned long jz_clk_pll_half_get_rate(struct clk *clk)
++{
++ uint32_t reg;
++
++ reg = jz_clk_reg_read(JZ_REG_CLOCK_CTRL);
++ if (reg & JZ_CLOCK_CTRL_PLL_HALF)
++ return jz_clk_pll_get_rate(clk->parent);
++ return jz_clk_pll_get_rate(clk->parent) >> 1;
++}
++
++static const int jz_clk_main_divs[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
++
++static unsigned long jz_clk_main_round_rate(struct clk *clk, unsigned long rate)
++{
++ unsigned long parent_rate = jz_clk_pll_get_rate(clk->parent);
++ int div;
++
++ div = parent_rate / rate;
++ if (div > 32)
++ return parent_rate / 32;
++ else if (div < 1)
++ return parent_rate;
++
++ div &= (0x3 << (ffs(div) - 1));
++
++ return parent_rate / div;
++}
++
++static unsigned long jz_clk_main_get_rate(struct clk *clk)
++{
++ struct main_clk *mclk = (struct main_clk *)clk;
++ uint32_t div;
++
++ div = jz_clk_reg_read(JZ_REG_CLOCK_CTRL);
++
++ div >>= mclk->div_offset;
++ div &= 0xf;
++
++ if (div >= ARRAY_SIZE(jz_clk_main_divs))
++ div = ARRAY_SIZE(jz_clk_main_divs) - 1;
++
++ return jz_clk_pll_get_rate(clk->parent) / jz_clk_main_divs[div];
++}
++
++static int jz_clk_main_set_rate(struct clk *clk, unsigned long rate)
++{
++ struct main_clk *mclk = (struct main_clk *)clk;
++ int i;
++ int div;
++ unsigned long parent_rate = jz_clk_pll_get_rate(clk->parent);
++
++ rate = jz_clk_main_round_rate(clk, rate);
++
++ div = parent_rate / rate;
++
++ i = (ffs(div) - 1) << 1;
++ if (i > 0 && !(div & BIT(i-1)))
++ i -= 1;
++
++ jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, i << mclk->div_offset,
++ 0xf << mclk->div_offset);
++
++ return 0;
++}
++
++static struct clk_ops jz_clk_static_ops = {
++ .get_rate = jz_clk_static_get_rate,
++ .enable = jz_clk_enable_gating,
++ .disable = jz_clk_disable_gating,
++ .is_enabled = jz_clk_is_enabled_gating,
++};
++
++static struct static_clk jz_clk_ext = {
++ .clk = {
++ .name = "ext",
++ .gate_bit = JZ4740_CLK_NOT_GATED,
++ .ops = &jz_clk_static_ops,
++ },
++};
++
++static struct clk_ops jz_clk_pll_ops = {
++ .get_rate = jz_clk_pll_get_rate,
++};
++
++static struct clk jz_clk_pll = {
++ .name = "pll",
++ .parent = &jz_clk_ext.clk,
++ .ops = &jz_clk_pll_ops,
++};
++
++static struct clk_ops jz_clk_pll_half_ops = {
++ .get_rate = jz_clk_pll_half_get_rate,
++};
++
++static struct clk jz_clk_pll_half = {
++ .name = "pll half",
++ .parent = &jz_clk_pll,
++ .ops = &jz_clk_pll_half_ops,
++};
++
++static const struct clk_ops jz_clk_main_ops = {
++ .get_rate = jz_clk_main_get_rate,
++ .set_rate = jz_clk_main_set_rate,
++ .round_rate = jz_clk_main_round_rate,
++};
++
++static struct main_clk jz_clk_cpu = {
++ .clk = {
++ .name = "cclk",
++ .parent = &jz_clk_pll,
++ .ops = &jz_clk_main_ops,
++ },
++ .div_offset = JZ_CLOCK_CTRL_CDIV_OFFSET,
++};
++
++static struct main_clk jz_clk_memory = {
++ .clk = {
++ .name = "mclk",
++ .parent = &jz_clk_pll,
++ .ops = &jz_clk_main_ops,
++ },
++ .div_offset = JZ_CLOCK_CTRL_MDIV_OFFSET,
++};
++
++static struct main_clk jz_clk_high_speed_peripheral = {
++ .clk = {
++ .name = "hclk",
++ .parent = &jz_clk_pll,
++ .ops = &jz_clk_main_ops,
++ },
++ .div_offset = JZ_CLOCK_CTRL_HDIV_OFFSET,
++};
++
++
++static struct main_clk jz_clk_low_speed_peripheral = {
++ .clk = {
++ .name = "pclk",
++ .parent = &jz_clk_pll,
++ .ops = &jz_clk_main_ops,
++ },
++ .div_offset = JZ_CLOCK_CTRL_PDIV_OFFSET,
++};
++
++static const struct clk_ops jz_clk_ko_ops = {
++ .enable = jz_clk_ko_enable,
++ .disable = jz_clk_ko_disable,
++ .is_enabled = jz_clk_ko_is_enabled,
++};
++
++static struct clk jz_clk_ko = {
++ .name = "cko",
++ .parent = &jz_clk_memory.clk,
++ .ops = &jz_clk_ko_ops,
++};
++
++static int jz_clk_spi_set_parent(struct clk *clk, struct clk *parent)
++{
++ if (parent == &jz_clk_pll)
++ jz_clk_reg_set_bits(JZ_CLOCK_SPI_SRC_PLL, JZ_REG_CLOCK_SPI);
++ else if (parent == &jz_clk_ext.clk)
++ jz_clk_reg_clear_bits(JZ_CLOCK_SPI_SRC_PLL, JZ_REG_CLOCK_SPI);
++ else
++ return -EINVAL;
++
++ clk->parent = parent;
++
++ return 0;
++}
++
++static int jz_clk_i2s_set_parent(struct clk *clk, struct clk *parent)
++{
++ if (parent == &jz_clk_pll_half)
++ jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_I2S_SRC_PLL);
++ else if (parent == &jz_clk_ext.clk)
++ jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_I2S_SRC_PLL);
++ else
++ return -EINVAL;
++
++ clk->parent = parent;
++
++ return 0;
++}
++
++static int jz_clk_udc_enable(struct clk *clk)
++{
++ jz_clk_reg_set_bits(JZ_REG_CLOCK_SLEEP_CTRL,
++ JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC);
++
++ return 0;
++}
++
++static int jz_clk_udc_disable(struct clk *clk)
++{
++ jz_clk_reg_clear_bits(JZ_REG_CLOCK_SLEEP_CTRL,
++ JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC);
++
++ return 0;
++}
++
++static int jz_clk_udc_is_enabled(struct clk *clk)
++{
++ return !!(jz_clk_reg_read(JZ_REG_CLOCK_SLEEP_CTRL) &
++ JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC);
++}
++
++static int jz_clk_udc_set_parent(struct clk *clk, struct clk *parent)
++{
++ if (parent == &jz_clk_pll_half)
++ jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_UDC_SRC_PLL);
++ else if (parent == &jz_clk_ext.clk)
++ jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_UDC_SRC_PLL);
++ else
++ return -EINVAL;
++
++ clk->parent = parent;
++
++ return 0;
++}
++
++static int jz_clk_udc_set_rate(struct clk *clk, unsigned long rate)
++{
++ int div;
++
++ if (clk->parent == &jz_clk_ext.clk)
++ return -EINVAL;
++
++ div = clk_get_rate(clk->parent) / rate - 1;
++
++ if (div < 0)
++ div = 0;
++ else if (div > 63)
++ div = 63;
++
++ jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, div << JZ_CLOCK_CTRL_UDIV_OFFSET,
++ JZ_CLOCK_CTRL_UDIV_MASK);
++ return 0;
++}
++
++static unsigned long jz_clk_udc_get_rate(struct clk *clk)
++{
++ int div;
++
++ if (clk->parent == &jz_clk_ext.clk)
++ return clk_get_rate(clk->parent);
++
++ div = (jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_UDIV_MASK);
++ div >>= JZ_CLOCK_CTRL_UDIV_OFFSET;
++ div += 1;
++
++ return clk_get_rate(clk->parent) / div;
++}
++
++static unsigned long jz_clk_divided_get_rate(struct clk *clk)
++{
++ struct divided_clk *dclk = (struct divided_clk *)clk;
++ int div;
++
++ if (clk->parent == &jz_clk_ext.clk)
++ return clk_get_rate(clk->parent);
++
++ div = (jz_clk_reg_read(dclk->reg) & dclk->mask) + 1;
++
++ return clk_get_rate(clk->parent) / div;
++}
++
++static int jz_clk_divided_set_rate(struct clk *clk, unsigned long rate)
++{
++ struct divided_clk *dclk = (struct divided_clk *)clk;
++ int div;
++
++ if (clk->parent == &jz_clk_ext.clk)
++ return -EINVAL;
++
++ div = clk_get_rate(clk->parent) / rate - 1;
++
++ if (div < 0)
++ div = 0;
++ else if (div > dclk->mask)
++ div = dclk->mask;
++
++ jz_clk_reg_write_mask(dclk->reg, div, dclk->mask);
++
++ return 0;
++}
++
++static unsigned long jz_clk_ldclk_round_rate(struct clk *clk, unsigned long rate)
++{
++ int div;
++ unsigned long parent_rate = jz_clk_pll_half_get_rate(clk->parent);
++
++ if (rate > 150000000)
++ return 150000000;
++
++ div = parent_rate / rate;
++ if (div < 1)
++ div = 1;
++ else if (div > 32)
++ div = 32;
++
++ return parent_rate / div;
++}
++
++static int jz_clk_ldclk_set_rate(struct clk *clk, unsigned long rate)
++{
++ int div;
++
++ if (rate > 150000000)
++ return -EINVAL;
++
++ div = jz_clk_pll_half_get_rate(clk->parent) / rate - 1;
++ if (div < 0)
++ div = 0;
++ else if (div > 31)
++ div = 31;
++
++ jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, div << JZ_CLOCK_CTRL_LDIV_OFFSET,
++ JZ_CLOCK_CTRL_LDIV_MASK);
++
++ return 0;
++}
++
++static unsigned long jz_clk_ldclk_get_rate(struct clk *clk)
++{
++ int div;
++
++ div = jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_LDIV_MASK;
++ div >>= JZ_CLOCK_CTRL_LDIV_OFFSET;
++
++ return jz_clk_pll_half_get_rate(clk->parent) / (div + 1);
++}
++
++static const struct clk_ops jz_clk_ops_ld = {
++ .set_rate = jz_clk_ldclk_set_rate,
++ .get_rate = jz_clk_ldclk_get_rate,
++ .round_rate = jz_clk_ldclk_round_rate,
++ .enable = jz_clk_enable_gating,
++ .disable = jz_clk_disable_gating,
++ .is_enabled = jz_clk_is_enabled_gating,
++};
++
++static struct clk jz_clk_ld = {
++ .name = "lcd",
++ .gate_bit = JZ_CLOCK_GATE_LCD,
++ .parent = &jz_clk_pll_half,
++ .ops = &jz_clk_ops_ld,
++};
++
++static const struct clk_ops jz_clk_i2s_ops = {
++ .set_rate = jz_clk_divided_set_rate,
++ .get_rate = jz_clk_divided_get_rate,
++ .enable = jz_clk_enable_gating,
++ .disable = jz_clk_disable_gating,
++ .is_enabled = jz_clk_is_enabled_gating,
++ .set_parent = jz_clk_i2s_set_parent,
++};
++
++static const struct clk_ops jz_clk_spi_ops = {
++ .set_rate = jz_clk_divided_set_rate,
++ .get_rate = jz_clk_divided_get_rate,
++ .enable = jz_clk_enable_gating,
++ .disable = jz_clk_disable_gating,
++ .is_enabled = jz_clk_is_enabled_gating,
++ .set_parent = jz_clk_spi_set_parent,
++};
++
++static const struct clk_ops jz_clk_divided_ops = {
++ .set_rate = jz_clk_divided_set_rate,
++ .get_rate = jz_clk_divided_get_rate,
++ .enable = jz_clk_enable_gating,
++ .disable = jz_clk_disable_gating,
++ .is_enabled = jz_clk_is_enabled_gating,
++};
++
++static struct divided_clk jz4740_clock_divided_clks[] = {
++ [0] = {
++ .clk = {
++ .name = "i2s",
++ .parent = &jz_clk_ext.clk,
++ .gate_bit = JZ_CLOCK_GATE_I2S,
++ .ops = &jz_clk_i2s_ops,
++ },
++ .reg = JZ_REG_CLOCK_I2S,
++ .mask = JZ_CLOCK_I2S_DIV_MASK,
++ },
++ [1] = {
++ .clk = {
++ .name = "spi",
++ .parent = &jz_clk_ext.clk,
++ .gate_bit = JZ_CLOCK_GATE_SPI,
++ .ops = &jz_clk_spi_ops,
++ },
++ .reg = JZ_REG_CLOCK_SPI,
++ .mask = JZ_CLOCK_SPI_DIV_MASK,
++ },
++ [2] = {
++ .clk = {
++ .name = "lcd_pclk",
++ .parent = &jz_clk_pll_half,
++ .gate_bit = JZ4740_CLK_NOT_GATED,
++ .ops = &jz_clk_divided_ops,
++ },
++ .reg = JZ_REG_CLOCK_LCD,
++ .mask = JZ_CLOCK_LCD_DIV_MASK,
++ },
++ [3] = {
++ .clk = {
++ .name = "mmc",
++ .parent = &jz_clk_pll_half,
++ .gate_bit = JZ_CLOCK_GATE_MMC,
++ .ops = &jz_clk_divided_ops,
++ },
++ .reg = JZ_REG_CLOCK_MMC,
++ .mask = JZ_CLOCK_MMC_DIV_MASK,
++ },
++ [4] = {
++ .clk = {
++ .name = "uhc",
++ .parent = &jz_clk_pll_half,
++ .gate_bit = JZ_CLOCK_GATE_UHC,
++ .ops = &jz_clk_divided_ops,
++ },
++ .reg = JZ_REG_CLOCK_UHC,
++ .mask = JZ_CLOCK_UHC_DIV_MASK,
++ },
++};
++
++static const struct clk_ops jz_clk_udc_ops = {
++ .set_parent = jz_clk_udc_set_parent,
++ .set_rate = jz_clk_udc_set_rate,
++ .get_rate = jz_clk_udc_get_rate,
++ .enable = jz_clk_udc_enable,
++ .disable = jz_clk_udc_disable,
++ .is_enabled = jz_clk_udc_is_enabled,
++};
++
++static const struct clk_ops jz_clk_simple_ops = {
++ .enable = jz_clk_enable_gating,
++ .disable = jz_clk_disable_gating,
++ .is_enabled = jz_clk_is_enabled_gating,
++};
++
++static struct clk jz4740_clock_simple_clks[] = {
++ [0] = {
++ .name = "udc",
++ .parent = &jz_clk_ext.clk,
++ .ops = &jz_clk_udc_ops,
++ },
++ [1] = {
++ .name = "uart0",
++ .parent = &jz_clk_ext.clk,
++ .gate_bit = JZ_CLOCK_GATE_UART0,
++ .ops = &jz_clk_simple_ops,
++ },
++ [2] = {
++ .name = "uart1",
++ .parent = &jz_clk_ext.clk,
++ .gate_bit = JZ_CLOCK_GATE_UART1,
++ .ops = &jz_clk_simple_ops,
++ },
++ [3] = {
++ .name = "dma",
++ .parent = &jz_clk_high_speed_peripheral.clk,
++ .gate_bit = JZ_CLOCK_GATE_UART0,
++ .ops = &jz_clk_simple_ops,
++ },
++ [4] = {
++ .name = "ipu",
++ .parent = &jz_clk_high_speed_peripheral.clk,
++ .gate_bit = JZ_CLOCK_GATE_IPU,
++ .ops = &jz_clk_simple_ops,
++ },
++ [5] = {
++ .name = "adc",
++ .parent = &jz_clk_ext.clk,
++ .gate_bit = JZ_CLOCK_GATE_ADC,
++ .ops = &jz_clk_simple_ops,
++ },
++ [6] = {
++ .name = "i2c",
++ .parent = &jz_clk_ext.clk,
++ .gate_bit = JZ_CLOCK_GATE_I2C,
++ .ops = &jz_clk_simple_ops,
++ },
++ [7] = {
++ .name = "aic",
++ .parent = &jz_clk_ext.clk,
++ .gate_bit = JZ_CLOCK_GATE_AIC,
++ .ops = &jz_clk_simple_ops,
++ },
++};
++
++static struct static_clk jz_clk_rtc = {
++ .clk = {
++ .name = "rtc",
++ .gate_bit = JZ_CLOCK_GATE_RTC,
++ .ops = &jz_clk_static_ops,
++ },
++ .rate = 32768,
++};
++
++int clk_enable(struct clk *clk)
++{
++ if (!clk->ops->enable)
++ return -EINVAL;
++
++ return clk->ops->enable(clk);
++}
++EXPORT_SYMBOL_GPL(clk_enable);
++
++void clk_disable(struct clk *clk)
++{
++ if (clk->ops->disable)
++ clk->ops->disable(clk);
++}
++EXPORT_SYMBOL_GPL(clk_disable);
++
++int clk_is_enabled(struct clk *clk)
++{
++ if (clk->ops->is_enabled)
++ return clk->ops->is_enabled(clk);
++
++ return 1;
++}
++
++unsigned long clk_get_rate(struct clk *clk)
++{
++ if (clk->ops->get_rate)
++ return clk->ops->get_rate(clk);
++ if (clk->parent)
++ return clk_get_rate(clk->parent);
++
++ return -EINVAL;
++}
++EXPORT_SYMBOL_GPL(clk_get_rate);
++
++int clk_set_rate(struct clk *clk, unsigned long rate)
++{
++ if (!clk->ops->set_rate)
++ return -EINVAL;
++ return clk->ops->set_rate(clk, rate);
++}
++EXPORT_SYMBOL_GPL(clk_set_rate);
++
++long clk_round_rate(struct clk *clk, unsigned long rate)
++{
++ if (clk->ops->round_rate)
++ return clk->ops->round_rate(clk, rate);
++
++ return -EINVAL;
++}
++EXPORT_SYMBOL_GPL(clk_round_rate);
++
++int clk_set_parent(struct clk *clk, struct clk *parent)
++{
++ int ret;
++ int enabled;
++
++ if (!clk->ops->set_parent)
++ return -EINVAL;
++
++ enabled = clk_is_enabled(clk);
++ if (enabled)
++ clk_disable(clk);
++ ret = clk->ops->set_parent(clk, parent);
++ if (enabled)
++ clk_enable(clk);
++
++ jz4740_clock_debugfs_update_parent(clk);
++
++ return ret;
++}
++EXPORT_SYMBOL_GPL(clk_set_parent);
++
++struct clk *clk_get(struct device *dev, const char *name)
++{
++ struct clk *clk;
++
++ list_for_each_entry(clk, &jz_clocks, list) {
++ if (strcmp(clk->name, name) == 0)
++ return clk;
++ }
++ return ERR_PTR(-ENXIO);
++}
++EXPORT_SYMBOL_GPL(clk_get);
++
++void clk_put(struct clk *clk)
++{
++}
++EXPORT_SYMBOL_GPL(clk_put);
++
++static inline void clk_add(struct clk *clk)
++{
++ list_add_tail(&clk->list, &jz_clocks);
++
++ jz4740_clock_debugfs_add_clk(clk);
++}
++
++static void clk_register_clks(void)
++{
++ size_t i;
++
++ clk_add(&jz_clk_ext.clk);
++ clk_add(&jz_clk_pll);
++ clk_add(&jz_clk_pll_half);
++ clk_add(&jz_clk_cpu.clk);
++ clk_add(&jz_clk_high_speed_peripheral.clk);
++ clk_add(&jz_clk_low_speed_peripheral.clk);
++ clk_add(&jz_clk_ko);
++ clk_add(&jz_clk_ld);
++ clk_add(&jz_clk_rtc.clk);
++
++ for (i = 0; i < ARRAY_SIZE(jz4740_clock_divided_clks); ++i)
++ clk_add(&jz4740_clock_divided_clks[i].clk);
++
++ for (i = 0; i < ARRAY_SIZE(jz4740_clock_simple_clks); ++i)
++ clk_add(&jz4740_clock_simple_clks[i]);
++}
++
++void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode)
++{
++ switch (mode) {
++ case JZ4740_WAIT_MODE_IDLE:
++ jz_clk_reg_clear_bits(JZ_REG_CLOCK_LOW_POWER, JZ_CLOCK_LOW_POWER_MODE_SLEEP);
++ break;
++ case JZ4740_WAIT_MODE_SLEEP:
++ jz_clk_reg_set_bits(JZ_REG_CLOCK_LOW_POWER, JZ_CLOCK_LOW_POWER_MODE_SLEEP);
++ break;
++ }
++}
++
++void jz4740_clock_udc_disable_auto_suspend(void)
++{
++ jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC);
++}
++EXPORT_SYMBOL_GPL(jz4740_clock_udc_disable_auto_suspend);
++
++void jz4740_clock_udc_enable_auto_suspend(void)
++{
++ jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC);
++}
++EXPORT_SYMBOL_GPL(jz4740_clock_udc_enable_auto_suspend);
++
++void jz4740_clock_suspend(void)
++{
++ jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE,
++ JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0);
++
++ jz_clk_reg_clear_bits(JZ_REG_CLOCK_PLL, JZ_CLOCK_PLL_ENABLED);
++}
++
++void jz4740_clock_resume(void)
++{
++ uint32_t pll;
++
++ jz_clk_reg_set_bits(JZ_REG_CLOCK_PLL, JZ_CLOCK_PLL_ENABLED);
++
++ do {
++ pll = jz_clk_reg_read(JZ_REG_CLOCK_PLL);
++ } while (!(pll & JZ_CLOCK_PLL_STABLE));
++
++ jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE,
++ JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0);
++}
++
++static int jz4740_clock_init(void)
++{
++ uint32_t val;
++
++ jz_clock_base = ioremap(JZ4740_CPM_BASE_ADDR, 0x100);
++ if (!jz_clock_base)
++ return -EBUSY;
++
++ spin_lock_init(&jz_clock_lock);
++
++ jz_clk_ext.rate = jz4740_clock_bdata.ext_rate;
++ jz_clk_rtc.rate = jz4740_clock_bdata.rtc_rate;
++
++ val = jz_clk_reg_read(JZ_REG_CLOCK_SPI);
++
++ if (val & JZ_CLOCK_SPI_SRC_PLL)
++ jz4740_clock_divided_clks[1].clk.parent = &jz_clk_pll_half;
++
++ val = jz_clk_reg_read(JZ_REG_CLOCK_CTRL);
++
++ if (val & JZ_CLOCK_CTRL_I2S_SRC_PLL)
++ jz4740_clock_divided_clks[0].clk.parent = &jz_clk_pll_half;
++
++ if (val & JZ_CLOCK_CTRL_UDC_SRC_PLL)
++ jz4740_clock_simple_clks[0].parent = &jz_clk_pll_half;
++
++ jz4740_clock_debugfs_init();
++
++ clk_register_clks();
++
++ return 0;
++}
++arch_initcall(jz4740_clock_init);
+--- /dev/null
++++ b/arch/mips/jz4740/clock.h
+@@ -0,0 +1,76 @@
++/*
++ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
++ * JZ4740 SoC clock support
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#ifndef __MIPS_JZ4740_CLOCK_H__
++#define __MIPS_JZ4740_CLOCK_H__
++
++#include <linux/list.h>
++
++struct jz4740_clock_board_data {
++ unsigned long ext_rate;
++ unsigned long rtc_rate;
++};
++
++extern struct jz4740_clock_board_data jz4740_clock_bdata;
++
++void jz4740_clock_suspend(void);
++void jz4740_clock_resume(void);
++
++struct clk;
++
++struct clk_ops {
++ unsigned long (*get_rate)(struct clk *clk);
++ unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
++ int (*set_rate)(struct clk *clk, unsigned long rate);
++ int (*enable)(struct clk *clk);
++ int (*disable)(struct clk *clk);
++ int (*is_enabled)(struct clk *clk);
++
++ int (*set_parent)(struct clk *clk, struct clk *parent);
++
++};
++
++struct clk {
++ const char *name;
++ struct clk *parent;
++
++ uint32_t gate_bit;
++
++ const struct clk_ops *ops;
++
++ struct list_head list;
++
++#ifdef CONFIG_DEBUG_FS
++ struct dentry *debugfs_entry;
++ struct dentry *debugfs_parent_entry;
++#endif
++
++};
++
++#define JZ4740_CLK_NOT_GATED ((uint32_t)-1)
++
++int clk_is_enabled(struct clk *clk);
++
++#ifdef CONFIG_DEBUG_FS
++void jz4740_clock_debugfs_init(void);
++void jz4740_clock_debugfs_add_clk(struct clk *clk);
++void jz4740_clock_debugfs_update_parent(struct clk *clk);
++#else
++static inline void jz4740_clock_debugfs_init(void) {};
++static inline void jz4740_clock_debugfs_add_clk(struct clk *clk) {};
++static inline void jz4740_clock_debugfs_update_parent(struct clk *clk) {};
++#endif
++
++#endif
--- /dev/null
+From f6a9c8215a4553357b8a1939fafb2d6dfbacf944 Mon Sep 17 00:00:00 2001
+From: Lars-Peter Clausen <lars@metafoo.de>
+Date: Sat, 17 Jul 2010 11:08:43 +0000
+Subject: [PATCH] MIPS: JZ4740: Add IRQ handler code
+
+Add support for IRQ handling on a JZ4740 SoC.
+
+Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
+Cc: linux-mips@linux-mips.org
+Cc: linux-kernel@vger.kernel.org
+Patchwork: https://patchwork.linux-mips.org/patch/1465/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/include/asm/mach-jz4740/irq.h | 57 +++++++++++
+ arch/mips/jz4740/irq.c | 167 +++++++++++++++++++++++++++++++
+ arch/mips/jz4740/irq.h | 21 ++++
+ 3 files changed, 245 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/include/asm/mach-jz4740/irq.h
+ create mode 100644 arch/mips/jz4740/irq.c
+ create mode 100644 arch/mips/jz4740/irq.h
+
+--- /dev/null
++++ b/arch/mips/include/asm/mach-jz4740/irq.h
+@@ -0,0 +1,57 @@
++/*
++ * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
++ * JZ4740 IRQ definitions
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#ifndef __ASM_MACH_JZ4740_IRQ_H__
++#define __ASM_MACH_JZ4740_IRQ_H__
++
++#define MIPS_CPU_IRQ_BASE 0
++#define JZ4740_IRQ_BASE 8
++
++/* 1st-level interrupts */
++#define JZ4740_IRQ(x) (JZ4740_IRQ_BASE + (x))
++#define JZ4740_IRQ_I2C JZ4740_IRQ(1)
++#define JZ4740_IRQ_UHC JZ4740_IRQ(3)
++#define JZ4740_IRQ_UART1 JZ4740_IRQ(8)
++#define JZ4740_IRQ_UART0 JZ4740_IRQ(9)
++#define JZ4740_IRQ_SADC JZ4740_IRQ(12)
++#define JZ4740_IRQ_MSC JZ4740_IRQ(14)
++#define JZ4740_IRQ_RTC JZ4740_IRQ(15)
++#define JZ4740_IRQ_SSI JZ4740_IRQ(16)
++#define JZ4740_IRQ_CIM JZ4740_IRQ(17)
++#define JZ4740_IRQ_AIC JZ4740_IRQ(18)
++#define JZ4740_IRQ_ETH JZ4740_IRQ(19)
++#define JZ4740_IRQ_DMAC JZ4740_IRQ(20)
++#define JZ4740_IRQ_TCU2 JZ4740_IRQ(21)
++#define JZ4740_IRQ_TCU1 JZ4740_IRQ(22)
++#define JZ4740_IRQ_TCU0 JZ4740_IRQ(23)
++#define JZ4740_IRQ_UDC JZ4740_IRQ(24)
++#define JZ4740_IRQ_GPIO3 JZ4740_IRQ(25)
++#define JZ4740_IRQ_GPIO2 JZ4740_IRQ(26)
++#define JZ4740_IRQ_GPIO1 JZ4740_IRQ(27)
++#define JZ4740_IRQ_GPIO0 JZ4740_IRQ(28)
++#define JZ4740_IRQ_IPU JZ4740_IRQ(29)
++#define JZ4740_IRQ_LCD JZ4740_IRQ(30)
++
++/* 2nd-level interrupts */
++#define JZ4740_IRQ_DMA(x) (JZ4740_IRQ(32) + (X))
++
++#define JZ4740_IRQ_INTC_GPIO(x) (JZ4740_IRQ_GPIO0 - (x))
++#define JZ4740_IRQ_GPIO(x) (JZ4740_IRQ(48) + (x))
++
++#define JZ4740_IRQ_ADC_BASE JZ4740_IRQ(176)
++
++#define NR_IRQS (JZ4740_IRQ_ADC_BASE + 6)
++
++#endif
+--- /dev/null
++++ b/arch/mips/jz4740/irq.c
+@@ -0,0 +1,167 @@
++/*
++ * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
++ * JZ4740 platform IRQ support
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/errno.h>
++#include <linux/init.h>
++#include <linux/types.h>
++#include <linux/interrupt.h>
++#include <linux/ioport.h>
++#include <linux/timex.h>
++#include <linux/slab.h>
++#include <linux/delay.h>
++
++#include <linux/debugfs.h>
++#include <linux/seq_file.h>
++
++#include <asm/io.h>
++#include <asm/mipsregs.h>
++#include <asm/irq_cpu.h>
++
++#include <asm/mach-jz4740/base.h>
++
++static void __iomem *jz_intc_base;
++static uint32_t jz_intc_wakeup;
++static uint32_t jz_intc_saved;
++
++#define JZ_REG_INTC_STATUS 0x00
++#define JZ_REG_INTC_MASK 0x04
++#define JZ_REG_INTC_SET_MASK 0x08
++#define JZ_REG_INTC_CLEAR_MASK 0x0c
++#define JZ_REG_INTC_PENDING 0x10
++
++#define IRQ_BIT(x) BIT((x) - JZ4740_IRQ_BASE)
++
++static void intc_irq_unmask(unsigned int irq)
++{
++ writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
++}
++
++static void intc_irq_mask(unsigned int irq)
++{
++ writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_SET_MASK);
++}
++
++static int intc_irq_set_wake(unsigned int irq, unsigned int on)
++{
++ if (on)
++ jz_intc_wakeup |= IRQ_BIT(irq);
++ else
++ jz_intc_wakeup &= ~IRQ_BIT(irq);
++
++ return 0;
++}
++
++static struct irq_chip intc_irq_type = {
++ .name = "INTC",
++ .mask = intc_irq_mask,
++ .mask_ack = intc_irq_mask,
++ .unmask = intc_irq_unmask,
++ .set_wake = intc_irq_set_wake,
++};
++
++static irqreturn_t jz4740_cascade(int irq, void *data)
++{
++ uint32_t irq_reg;
++
++ irq_reg = readl(jz_intc_base + JZ_REG_INTC_PENDING);
++
++ if (irq_reg)
++ generic_handle_irq(__fls(irq_reg) + JZ4740_IRQ_BASE);
++
++ return IRQ_HANDLED;
++}
++
++static struct irqaction jz4740_cascade_action = {
++ .handler = jz4740_cascade,
++ .name = "JZ4740 cascade interrupt",
++};
++
++void __init arch_init_irq(void)
++{
++ int i;
++ mips_cpu_irq_init();
++
++ jz_intc_base = ioremap(JZ4740_INTC_BASE_ADDR, 0x14);
++
++ for (i = JZ4740_IRQ_BASE; i < JZ4740_IRQ_BASE + 32; i++) {
++ intc_irq_mask(i);
++ set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);
++ }
++
++ setup_irq(2, &jz4740_cascade_action);
++}
++
++asmlinkage void plat_irq_dispatch(void)
++{
++ unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
++ if (pending & STATUSF_IP2)
++ do_IRQ(2);
++ else if (pending & STATUSF_IP3)
++ do_IRQ(3);
++ else
++ spurious_interrupt();
++}
++
++void jz4740_intc_suspend(void)
++{
++ jz_intc_saved = readl(jz_intc_base + JZ_REG_INTC_MASK);
++ writel(~jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_SET_MASK);
++ writel(jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
++}
++
++void jz4740_intc_resume(void)
++{
++ writel(~jz_intc_saved, jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
++ writel(jz_intc_saved, jz_intc_base + JZ_REG_INTC_SET_MASK);
++}
++
++#ifdef CONFIG_DEBUG_FS
++
++static inline void intc_seq_reg(struct seq_file *s, const char *name,
++ unsigned int reg)
++{
++ seq_printf(s, "%s:\t\t%08x\n", name, readl(jz_intc_base + reg));
++}
++
++static int intc_regs_show(struct seq_file *s, void *unused)
++{
++ intc_seq_reg(s, "Status", JZ_REG_INTC_STATUS);
++ intc_seq_reg(s, "Mask", JZ_REG_INTC_MASK);
++ intc_seq_reg(s, "Pending", JZ_REG_INTC_PENDING);
++
++ return 0;
++}
++
++static int intc_regs_open(struct inode *inode, struct file *file)
++{
++ return single_open(file, intc_regs_show, NULL);
++}
++
++static const struct file_operations intc_regs_operations = {
++ .open = intc_regs_open,
++ .read = seq_read,
++ .llseek = seq_lseek,
++ .release = single_release,
++};
++
++static int __init intc_debugfs_init(void)
++{
++ (void) debugfs_create_file("jz_regs_intc", S_IFREG | S_IRUGO,
++ NULL, NULL, &intc_regs_operations);
++ return 0;
++}
++subsys_initcall(intc_debugfs_init);
++
++#endif
+--- /dev/null
++++ b/arch/mips/jz4740/irq.h
+@@ -0,0 +1,21 @@
++/*
++ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#ifndef __MIPS_JZ4740_IRQ_H__
++#define __MIPS_JZ4740_IRQ_H__
++
++extern void jz4740_intc_suspend(void);
++extern void jz4740_intc_resume(void);
++
++#endif
--- /dev/null
+From ad817ad0a57d0fa6041071395d4cf0d2e9a44635 Mon Sep 17 00:00:00 2001
+From: Lars-Peter Clausen <lars@metafoo.de>
+Date: Sat, 19 Jun 2010 04:08:09 +0000
+Subject: [PATCH] MIPS: JZ4740: Add timer support
+
+Add support for the timer/counter unit on a JZ4740 SoC. This code is used
+as a common base for the JZ4740 clocksource/clockevent implementation and
+PWM support.
+
+Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
+Cc: linux-mips@linux-mips.org
+Cc: linux-kernel@vger.kernel.org
+Patchwork: https://patchwork.linux-mips.org/patch/1396/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/include/asm/mach-jz4740/timer.h | 22 +++++
+ arch/mips/jz4740/timer.c | 48 ++++++++++
+ arch/mips/jz4740/timer.h | 136 +++++++++++++++++++++++++++++
+ 3 files changed, 206 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/include/asm/mach-jz4740/timer.h
+ create mode 100644 arch/mips/jz4740/timer.c
+ create mode 100644 arch/mips/jz4740/timer.h
+
+--- /dev/null
++++ b/arch/mips/include/asm/mach-jz4740/timer.h
+@@ -0,0 +1,22 @@
++/*
++ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
++ * JZ4740 platform timer support
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#ifndef __ASM_MACH_JZ4740_TIMER
++#define __ASM_MACH_JZ4740_TIMER
++
++void jz4740_timer_enable_watchdog(void);
++void jz4740_timer_disable_watchdog(void);
++
++#endif
+--- /dev/null
++++ b/arch/mips/jz4740/timer.c
+@@ -0,0 +1,48 @@
++/*
++ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
++ * JZ4740 platform timer support
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/io.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++
++#include "timer.h"
++
++#include <asm/mach-jz4740/base.h>
++
++void __iomem *jz4740_timer_base;
++
++void jz4740_timer_enable_watchdog(void)
++{
++ writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
++}
++
++void jz4740_timer_disable_watchdog(void)
++{
++ writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
++}
++
++void __init jz4740_timer_init(void)
++{
++ jz4740_timer_base = ioremap(JZ4740_TCU_BASE_ADDR, 0x100);
++
++ if (!jz4740_timer_base)
++ panic("Failed to ioremap timer registers");
++
++ /* Disable all timer clocks except for those used as system timers */
++ writel(0x000100fc, jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
++
++ /* Timer irqs are unmasked by default, mask them */
++ writel(0x00ff00ff, jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
++}
+--- /dev/null
++++ b/arch/mips/jz4740/timer.h
+@@ -0,0 +1,136 @@
++/*
++ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
++ * JZ4740 platform timer support
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#ifndef __MIPS_JZ4740_TIMER_H__
++#define __MIPS_JZ4740_TIMER_H__
++
++#include <linux/module.h>
++#include <linux/io.h>
++
++#define JZ_REG_TIMER_STOP 0x0C
++#define JZ_REG_TIMER_STOP_SET 0x1C
++#define JZ_REG_TIMER_STOP_CLEAR 0x2C
++#define JZ_REG_TIMER_ENABLE 0x00
++#define JZ_REG_TIMER_ENABLE_SET 0x04
++#define JZ_REG_TIMER_ENABLE_CLEAR 0x08
++#define JZ_REG_TIMER_FLAG 0x10
++#define JZ_REG_TIMER_FLAG_SET 0x14
++#define JZ_REG_TIMER_FLAG_CLEAR 0x18
++#define JZ_REG_TIMER_MASK 0x20
++#define JZ_REG_TIMER_MASK_SET 0x24
++#define JZ_REG_TIMER_MASK_CLEAR 0x28
++
++#define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x30)
++#define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x34)
++#define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x38)
++#define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x3C)
++
++#define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10)
++#define JZ_TIMER_IRQ_FULL(x) BIT(x)
++
++#define JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN BIT(9)
++#define JZ_TIMER_CTRL_PWM_ACTIVE_LOW BIT(8)
++#define JZ_TIMER_CTRL_PWM_ENABLE BIT(7)
++#define JZ_TIMER_CTRL_PRESCALE_MASK 0x1c
++#define JZ_TIMER_CTRL_PRESCALE_OFFSET 0x3
++#define JZ_TIMER_CTRL_PRESCALE_1 (0 << 3)
++#define JZ_TIMER_CTRL_PRESCALE_4 (1 << 3)
++#define JZ_TIMER_CTRL_PRESCALE_16 (2 << 3)
++#define JZ_TIMER_CTRL_PRESCALE_64 (3 << 3)
++#define JZ_TIMER_CTRL_PRESCALE_256 (4 << 3)
++#define JZ_TIMER_CTRL_PRESCALE_1024 (5 << 3)
++
++#define JZ_TIMER_CTRL_PRESCALER(x) ((x) << JZ_TIMER_CTRL_PRESCALE_OFFSET)
++
++#define JZ_TIMER_CTRL_SRC_EXT BIT(2)
++#define JZ_TIMER_CTRL_SRC_RTC BIT(1)
++#define JZ_TIMER_CTRL_SRC_PCLK BIT(0)
++
++extern void __iomem *jz4740_timer_base;
++void __init jz4740_timer_init(void);
++
++static inline void jz4740_timer_stop(unsigned int timer)
++{
++ writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
++}
++
++static inline void jz4740_timer_start(unsigned int timer)
++{
++ writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
++}
++
++static inline bool jz4740_timer_is_enabled(unsigned int timer)
++{
++ return readb(jz4740_timer_base + JZ_REG_TIMER_ENABLE) & BIT(timer);
++}
++
++static inline void jz4740_timer_enable(unsigned int timer)
++{
++ writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
++}
++
++static inline void jz4740_timer_disable(unsigned int timer)
++{
++ writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
++}
++
++
++static inline void jz4740_timer_set_period(unsigned int timer, uint16_t period)
++{
++ writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer));
++}
++
++static inline void jz4740_timer_set_duty(unsigned int timer, uint16_t duty)
++{
++ writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer));
++}
++
++static inline void jz4740_timer_set_count(unsigned int timer, uint16_t count)
++{
++ writew(count, jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
++}
++
++static inline uint16_t jz4740_timer_get_count(unsigned int timer)
++{
++ return readw(jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
++}
++
++static inline void jz4740_timer_ack_full(unsigned int timer)
++{
++ writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
++}
++
++static inline void jz4740_timer_irq_full_enable(unsigned int timer)
++{
++ writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
++ writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
++}
++
++static inline void jz4740_timer_irq_full_disable(unsigned int timer)
++{
++ writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
++}
++
++static inline void jz4740_timer_set_ctrl(unsigned int timer, uint16_t ctrl)
++{
++ writew(ctrl, jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
++}
++
++static inline uint16_t jz4740_timer_get_ctrl(unsigned int timer)
++{
++ return readw(jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
++}
++
++#endif
--- /dev/null
+From ebf176a38105200dca51a96ad1535c8d56235653 Mon Sep 17 00:00:00 2001
+From: Lars-Peter Clausen <lars@metafoo.de>
+Date: Sat, 19 Jun 2010 04:08:10 +0000
+Subject: [PATCH] MIPS: JZ4740: Add clocksource/clockevent support.
+
+Add clocksource and clockevent support for the timer/counter unit on
+JZ4740 SoCs.
+
+Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
+Cc: linux-mips@linux-mips.org
+Cc: linux-kernel@vger.kernel.org
+Patchwork: https://patchwork.linux-mips.org/patch/1397/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/jz4740/time.c | 144 +++++++++++++++++++++++++++++++++++++++++++++++
+ 1 files changed, 144 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/jz4740/time.c
+
+--- /dev/null
++++ b/arch/mips/jz4740/time.c
+@@ -0,0 +1,144 @@
++/*
++ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
++ * JZ4740 platform time support
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/interrupt.h>
++#include <linux/kernel.h>
++#include <linux/time.h>
++
++#include <linux/clockchips.h>
++
++#include <asm/mach-jz4740/irq.h>
++#include <asm/time.h>
++
++#include "clock.h"
++#include "timer.h"
++
++#define TIMER_CLOCKEVENT 0
++#define TIMER_CLOCKSOURCE 1
++
++static uint16_t jz4740_jiffies_per_tick;
++
++static cycle_t jz4740_clocksource_read(struct clocksource *cs)
++{
++ return jz4740_timer_get_count(TIMER_CLOCKSOURCE);
++}
++
++static struct clocksource jz4740_clocksource = {
++ .name = "jz4740-timer",
++ .rating = 200,
++ .read = jz4740_clocksource_read,
++ .mask = CLOCKSOURCE_MASK(16),
++ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
++};
++
++static irqreturn_t jz4740_clockevent_irq(int irq, void *devid)
++{
++ struct clock_event_device *cd = devid;
++
++ jz4740_timer_ack_full(TIMER_CLOCKEVENT);
++
++ if (cd->mode != CLOCK_EVT_MODE_PERIODIC)
++ jz4740_timer_disable(TIMER_CLOCKEVENT);
++
++ cd->event_handler(cd);
++
++ return IRQ_HANDLED;
++}
++
++static void jz4740_clockevent_set_mode(enum clock_event_mode mode,
++ struct clock_event_device *cd)
++{
++ switch (mode) {
++ case CLOCK_EVT_MODE_PERIODIC:
++ jz4740_timer_set_count(TIMER_CLOCKEVENT, 0);
++ jz4740_timer_set_period(TIMER_CLOCKEVENT, jz4740_jiffies_per_tick);
++ case CLOCK_EVT_MODE_RESUME:
++ jz4740_timer_irq_full_enable(TIMER_CLOCKEVENT);
++ jz4740_timer_enable(TIMER_CLOCKEVENT);
++ break;
++ case CLOCK_EVT_MODE_ONESHOT:
++ case CLOCK_EVT_MODE_SHUTDOWN:
++ jz4740_timer_disable(TIMER_CLOCKEVENT);
++ break;
++ default:
++ break;
++ }
++}
++
++static int jz4740_clockevent_set_next(unsigned long evt,
++ struct clock_event_device *cd)
++{
++ jz4740_timer_set_count(TIMER_CLOCKEVENT, 0);
++ jz4740_timer_set_period(TIMER_CLOCKEVENT, evt);
++ jz4740_timer_enable(TIMER_CLOCKEVENT);
++
++ return 0;
++}
++
++static struct clock_event_device jz4740_clockevent = {
++ .name = "jz4740-timer",
++ .features = CLOCK_EVT_FEAT_PERIODIC,
++ .set_next_event = jz4740_clockevent_set_next,
++ .set_mode = jz4740_clockevent_set_mode,
++ .rating = 200,
++ .irq = JZ4740_IRQ_TCU0,
++};
++
++static struct irqaction timer_irqaction = {
++ .handler = jz4740_clockevent_irq,
++ .flags = IRQF_PERCPU | IRQF_TIMER,
++ .name = "jz4740-timerirq",
++ .dev_id = &jz4740_clockevent,
++};
++
++void __init plat_time_init(void)
++{
++ int ret;
++ uint32_t clk_rate;
++ uint16_t ctrl;
++
++ jz4740_timer_init();
++
++ clk_rate = jz4740_clock_bdata.ext_rate >> 4;
++ jz4740_jiffies_per_tick = DIV_ROUND_CLOSEST(clk_rate, HZ);
++
++ clockevent_set_clock(&jz4740_clockevent, clk_rate);
++ jz4740_clockevent.min_delta_ns = clockevent_delta2ns(100, &jz4740_clockevent);
++ jz4740_clockevent.max_delta_ns = clockevent_delta2ns(0xffff, &jz4740_clockevent);
++ jz4740_clockevent.cpumask = cpumask_of(0);
++
++ clockevents_register_device(&jz4740_clockevent);
++
++ clocksource_set_clock(&jz4740_clocksource, clk_rate);
++ ret = clocksource_register(&jz4740_clocksource);
++
++ if (ret)
++ printk(KERN_ERR "Failed to register clocksource: %d\n", ret);
++
++ setup_irq(JZ4740_IRQ_TCU0, &timer_irqaction);
++
++ ctrl = JZ_TIMER_CTRL_PRESCALE_16 | JZ_TIMER_CTRL_SRC_EXT;
++
++ jz4740_timer_set_ctrl(TIMER_CLOCKEVENT, ctrl);
++ jz4740_timer_set_ctrl(TIMER_CLOCKSOURCE, ctrl);
++
++ jz4740_timer_set_period(TIMER_CLOCKEVENT, jz4740_jiffies_per_tick);
++ jz4740_timer_irq_full_enable(TIMER_CLOCKEVENT);
++
++ jz4740_timer_set_period(TIMER_CLOCKSOURCE, 0xffff);
++
++ jz4740_timer_enable(TIMER_CLOCKEVENT);
++ jz4740_timer_enable(TIMER_CLOCKSOURCE);
++}
--- /dev/null
+From 0c5476ab44aaffafcdce4885f09e86b300eb2241 Mon Sep 17 00:00:00 2001
+From: Lars-Peter Clausen <lars@metafoo.de>
+Date: Sat, 19 Jun 2010 04:08:11 +0000
+Subject: [PATCH] MIPS: JZ4740: Add power-management and system reset support
+
+Add support for suspend/resume and poweroff/reboot on a JZ4740 SoC.
+
+Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
+Cc: linux-mips@linux-mips.org
+Cc: linux-kernel@vger.kernel.org
+Patchwork: https://patchwork.linux-mips.org/patch/1398/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/jz4740/pm.c | 56 ++++++++++++++++++++++++++++++++
+ arch/mips/jz4740/reset.c | 79 ++++++++++++++++++++++++++++++++++++++++++++++
+ arch/mips/jz4740/reset.h | 6 +++
+ 3 files changed, 141 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/jz4740/pm.c
+ create mode 100644 arch/mips/jz4740/reset.c
+ create mode 100644 arch/mips/jz4740/reset.h
+
+--- /dev/null
++++ b/arch/mips/jz4740/pm.c
+@@ -0,0 +1,56 @@
++/*
++ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
++ * JZ4740 SoC power management support
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/init.h>
++#include <linux/pm.h>
++#include <linux/delay.h>
++#include <linux/suspend.h>
++
++#include <asm/mach-jz4740/clock.h>
++
++#include "clock.h"
++#include "irq.h"
++
++static int jz4740_pm_enter(suspend_state_t state)
++{
++ jz4740_intc_suspend();
++ jz4740_clock_suspend();
++
++ jz4740_clock_set_wait_mode(JZ4740_WAIT_MODE_SLEEP);
++
++ __asm__(".set\tmips3\n\t"
++ "wait\n\t"
++ ".set\tmips0");
++
++ jz4740_clock_set_wait_mode(JZ4740_WAIT_MODE_IDLE);
++
++ jz4740_clock_resume();
++ jz4740_intc_resume();
++
++ return 0;
++}
++
++static struct platform_suspend_ops jz4740_pm_ops = {
++ .valid = suspend_valid_only_mem,
++ .enter = jz4740_pm_enter,
++};
++
++static int __init jz4740_pm_init(void)
++{
++ suspend_set_ops(&jz4740_pm_ops);
++ return 0;
++
++}
++late_initcall(jz4740_pm_init);
+--- /dev/null
++++ b/arch/mips/jz4740/reset.c
+@@ -0,0 +1,79 @@
++/*
++ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/io.h>
++#include <linux/kernel.h>
++#include <linux/pm.h>
++
++#include <asm/reboot.h>
++
++#include <asm/mach-jz4740/base.h>
++#include <asm/mach-jz4740/timer.h>
++
++static void jz4740_halt(void)
++{
++ while (1) {
++ __asm__(".set push;\n"
++ ".set mips3;\n"
++ "wait;\n"
++ ".set pop;\n"
++ );
++ }
++}
++
++#define JZ_REG_WDT_DATA 0x00
++#define JZ_REG_WDT_COUNTER_ENABLE 0x04
++#define JZ_REG_WDT_COUNTER 0x08
++#define JZ_REG_WDT_CTRL 0x0c
++
++static void jz4740_restart(char *command)
++{
++ void __iomem *wdt_base = ioremap(JZ4740_WDT_BASE_ADDR, 0x0f);
++
++ jz4740_timer_enable_watchdog();
++
++ writeb(0, wdt_base + JZ_REG_WDT_COUNTER_ENABLE);
++
++ writew(0, wdt_base + JZ_REG_WDT_COUNTER);
++ writew(0, wdt_base + JZ_REG_WDT_DATA);
++ writew(BIT(2), wdt_base + JZ_REG_WDT_CTRL);
++
++ writeb(1, wdt_base + JZ_REG_WDT_COUNTER_ENABLE);
++ jz4740_halt();
++}
++
++#define JZ_REG_RTC_CTRL 0x00
++#define JZ_REG_RTC_HIBERNATE 0x20
++
++#define JZ_RTC_CTRL_WRDY BIT(7)
++
++static void jz4740_power_off(void)
++{
++ void __iomem *rtc_base = ioremap(JZ4740_RTC_BASE_ADDR, 0x24);
++ uint32_t ctrl;
++
++ do {
++ ctrl = readl(rtc_base + JZ_REG_RTC_CTRL);
++ } while (!(ctrl & JZ_RTC_CTRL_WRDY));
++
++ writel(1, rtc_base + JZ_REG_RTC_HIBERNATE);
++ jz4740_halt();
++}
++
++void jz4740_reset_init(void)
++{
++ _machine_restart = jz4740_restart;
++ _machine_halt = jz4740_halt;
++ pm_power_off = jz4740_power_off;
++}
+--- /dev/null
++++ b/arch/mips/jz4740/reset.h
+@@ -0,0 +1,6 @@
++#ifndef __MIPS_JZ4740_RESET_H__
++#define __MIPS_JZ4740_RESET_H__
++
++extern void jz4740_reset_init(void);
++
++#endif
--- /dev/null
+From 05e8cc3590af4f29d48346e626b980741d480f77 Mon Sep 17 00:00:00 2001
+From: Lars-Peter Clausen <lars@metafoo.de>
+Date: Sat, 19 Jun 2010 04:08:12 +0000
+Subject: [PATCH] MIPS: JZ4740: Add setup code
+
+Add plat_mem_setup and get_system_type for JZ4740 SoCs.
+
+Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
+Cc: linux-mips@linux-mips.org
+Cc: linux-kernel@vger.kernel.org
+Patchwork: https://patchwork.linux-mips.org/patch/1399/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/jz4740/setup.c | 29 +++++++++++++++++++++++++++++
+ 1 files changed, 29 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/jz4740/setup.c
+
+--- /dev/null
++++ b/arch/mips/jz4740/setup.c
+@@ -0,0 +1,29 @@
++/*
++ * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
++ * JZ4740 setup code
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++
++#include "reset.h"
++
++void __init plat_mem_setup(void)
++{
++ jz4740_reset_init();
++}
++
++const char *get_system_type(void)
++{
++ return "JZ4740";
++}
--- /dev/null
+From 9b2439903f4015233930ddab5b99b34c622c4876 Mon Sep 17 00:00:00 2001
+From: Lars-Peter Clausen <lars@metafoo.de>
+Date: Sat, 17 Jul 2010 11:11:19 +0000
+Subject: [PATCH] MIPS: JZ4740: Add GPIO support
+
+Add gpiolib support for JZ4740 SoCs.
+
+Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
+Cc: linux-mips@linux-mips.org
+Cc: linux-kernel@vger.kernel.org
+Patchwork: https://patchwork.linux-mips.org/patch/1467/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/include/asm/mach-jz4740/gpio.h | 398 ++++++++++++++++++++
+ arch/mips/jz4740/gpio.c | 604 ++++++++++++++++++++++++++++++
+ 2 files changed, 1002 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/include/asm/mach-jz4740/gpio.h
+ create mode 100644 arch/mips/jz4740/gpio.c
+
+--- /dev/null
++++ b/arch/mips/include/asm/mach-jz4740/gpio.h
+@@ -0,0 +1,398 @@
++/*
++ * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
++ * JZ4740 GPIO pin definitions
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#ifndef _JZ_GPIO_H
++#define _JZ_GPIO_H
++
++#include <linux/types.h>
++
++enum jz_gpio_function {
++ JZ_GPIO_FUNC_NONE,
++ JZ_GPIO_FUNC1,
++ JZ_GPIO_FUNC2,
++ JZ_GPIO_FUNC3,
++};
++
++
++/*
++ Usually a driver for a SoC component has to request several gpio pins and
++ configure them as funcion pins.
++ jz_gpio_bulk_request can be used to ease this process.
++ Usually one would do something like:
++
++ const static struct jz_gpio_bulk_request i2c_pins[] = {
++ JZ_GPIO_BULK_PIN(I2C_SDA),
++ JZ_GPIO_BULK_PIN(I2C_SCK),
++ };
++
++ inside the probe function:
++
++ ret = jz_gpio_bulk_request(i2c_pins, ARRAY_SIZE(i2c_pins));
++ if (ret) {
++ ...
++
++ inside the remove function:
++
++ jz_gpio_bulk_free(i2c_pins, ARRAY_SIZE(i2c_pins));
++
++
++*/
++struct jz_gpio_bulk_request {
++ int gpio;
++ const char *name;
++ enum jz_gpio_function function;
++};
++
++#define JZ_GPIO_BULK_PIN(pin) { \
++ .gpio = JZ_GPIO_ ## pin, \
++ .name = #pin, \
++ .function = JZ_GPIO_FUNC_ ## pin \
++}
++
++int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num);
++void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num);
++void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num);
++void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num);
++void jz_gpio_enable_pullup(unsigned gpio);
++void jz_gpio_disable_pullup(unsigned gpio);
++int jz_gpio_set_function(int gpio, enum jz_gpio_function function);
++
++int jz_gpio_port_direction_input(int port, uint32_t mask);
++int jz_gpio_port_direction_output(int port, uint32_t mask);
++void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask);
++uint32_t jz_gpio_port_get_value(int port, uint32_t mask);
++
++#include <asm/mach-generic/gpio.h>
++
++#define JZ_GPIO_PORTA(x) ((x) + 32 * 0)
++#define JZ_GPIO_PORTB(x) ((x) + 32 * 1)
++#define JZ_GPIO_PORTC(x) ((x) + 32 * 2)
++#define JZ_GPIO_PORTD(x) ((x) + 32 * 3)
++
++/* Port A function pins */
++#define JZ_GPIO_MEM_DATA0 JZ_GPIO_PORTA(0)
++#define JZ_GPIO_MEM_DATA1 JZ_GPIO_PORTA(1)
++#define JZ_GPIO_MEM_DATA2 JZ_GPIO_PORTA(2)
++#define JZ_GPIO_MEM_DATA3 JZ_GPIO_PORTA(3)
++#define JZ_GPIO_MEM_DATA4 JZ_GPIO_PORTA(4)
++#define JZ_GPIO_MEM_DATA5 JZ_GPIO_PORTA(5)
++#define JZ_GPIO_MEM_DATA6 JZ_GPIO_PORTA(6)
++#define JZ_GPIO_MEM_DATA7 JZ_GPIO_PORTA(7)
++#define JZ_GPIO_MEM_DATA8 JZ_GPIO_PORTA(8)
++#define JZ_GPIO_MEM_DATA9 JZ_GPIO_PORTA(9)
++#define JZ_GPIO_MEM_DATA10 JZ_GPIO_PORTA(10)
++#define JZ_GPIO_MEM_DATA11 JZ_GPIO_PORTA(11)
++#define JZ_GPIO_MEM_DATA12 JZ_GPIO_PORTA(12)
++#define JZ_GPIO_MEM_DATA13 JZ_GPIO_PORTA(13)
++#define JZ_GPIO_MEM_DATA14 JZ_GPIO_PORTA(14)
++#define JZ_GPIO_MEM_DATA15 JZ_GPIO_PORTA(15)
++#define JZ_GPIO_MEM_DATA16 JZ_GPIO_PORTA(16)
++#define JZ_GPIO_MEM_DATA17 JZ_GPIO_PORTA(17)
++#define JZ_GPIO_MEM_DATA18 JZ_GPIO_PORTA(18)
++#define JZ_GPIO_MEM_DATA19 JZ_GPIO_PORTA(19)
++#define JZ_GPIO_MEM_DATA20 JZ_GPIO_PORTA(20)
++#define JZ_GPIO_MEM_DATA21 JZ_GPIO_PORTA(21)
++#define JZ_GPIO_MEM_DATA22 JZ_GPIO_PORTA(22)
++#define JZ_GPIO_MEM_DATA23 JZ_GPIO_PORTA(23)
++#define JZ_GPIO_MEM_DATA24 JZ_GPIO_PORTA(24)
++#define JZ_GPIO_MEM_DATA25 JZ_GPIO_PORTA(25)
++#define JZ_GPIO_MEM_DATA26 JZ_GPIO_PORTA(26)
++#define JZ_GPIO_MEM_DATA27 JZ_GPIO_PORTA(27)
++#define JZ_GPIO_MEM_DATA28 JZ_GPIO_PORTA(28)
++#define JZ_GPIO_MEM_DATA29 JZ_GPIO_PORTA(29)
++#define JZ_GPIO_MEM_DATA30 JZ_GPIO_PORTA(30)
++#define JZ_GPIO_MEM_DATA31 JZ_GPIO_PORTA(31)
++
++#define JZ_GPIO_FUNC_MEM_DATA0 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_DATA1 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_DATA2 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_DATA3 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_DATA4 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_DATA5 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_DATA6 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_DATA7 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_DATA8 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_DATA9 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_DATA10 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_DATA11 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_DATA12 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_DATA13 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_DATA14 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_DATA15 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_DATA16 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_DATA17 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_DATA18 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_DATA19 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_DATA20 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_DATA21 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_DATA22 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_DATA23 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_DATA24 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_DATA25 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_DATA26 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_DATA27 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_DATA28 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_DATA29 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_DATA30 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_DATA31 JZ_GPIO_FUNC1
++
++/* Port B function pins */
++#define JZ_GPIO_MEM_ADDR0 JZ_GPIO_PORTB(0)
++#define JZ_GPIO_MEM_ADDR1 JZ_GPIO_PORTB(1)
++#define JZ_GPIO_MEM_ADDR2 JZ_GPIO_PORTB(2)
++#define JZ_GPIO_MEM_ADDR3 JZ_GPIO_PORTB(3)
++#define JZ_GPIO_MEM_ADDR4 JZ_GPIO_PORTB(4)
++#define JZ_GPIO_MEM_ADDR5 JZ_GPIO_PORTB(5)
++#define JZ_GPIO_MEM_ADDR6 JZ_GPIO_PORTB(6)
++#define JZ_GPIO_MEM_ADDR7 JZ_GPIO_PORTB(7)
++#define JZ_GPIO_MEM_ADDR8 JZ_GPIO_PORTB(8)
++#define JZ_GPIO_MEM_ADDR9 JZ_GPIO_PORTB(9)
++#define JZ_GPIO_MEM_ADDR10 JZ_GPIO_PORTB(10)
++#define JZ_GPIO_MEM_ADDR11 JZ_GPIO_PORTB(11)
++#define JZ_GPIO_MEM_ADDR12 JZ_GPIO_PORTB(12)
++#define JZ_GPIO_MEM_ADDR13 JZ_GPIO_PORTB(13)
++#define JZ_GPIO_MEM_ADDR14 JZ_GPIO_PORTB(14)
++#define JZ_GPIO_MEM_ADDR15 JZ_GPIO_PORTB(15)
++#define JZ_GPIO_MEM_ADDR16 JZ_GPIO_PORTB(16)
++#define JZ_GPIO_LCD_CLS JZ_GPIO_PORTB(17)
++#define JZ_GPIO_LCD_SPL JZ_GPIO_PORTB(18)
++#define JZ_GPIO_MEM_DCS JZ_GPIO_PORTB(19)
++#define JZ_GPIO_MEM_RAS JZ_GPIO_PORTB(20)
++#define JZ_GPIO_MEM_CAS JZ_GPIO_PORTB(21)
++#define JZ_GPIO_MEM_SDWE JZ_GPIO_PORTB(22)
++#define JZ_GPIO_MEM_CKE JZ_GPIO_PORTB(23)
++#define JZ_GPIO_MEM_CKO JZ_GPIO_PORTB(24)
++#define JZ_GPIO_MEM_CS0 JZ_GPIO_PORTB(25)
++#define JZ_GPIO_MEM_CS1 JZ_GPIO_PORTB(26)
++#define JZ_GPIO_MEM_CS2 JZ_GPIO_PORTB(27)
++#define JZ_GPIO_MEM_CS3 JZ_GPIO_PORTB(28)
++#define JZ_GPIO_MEM_RD JZ_GPIO_PORTB(29)
++#define JZ_GPIO_MEM_WR JZ_GPIO_PORTB(30)
++#define JZ_GPIO_MEM_WE0 JZ_GPIO_PORTB(31)
++
++#define JZ_GPIO_FUNC_MEM_ADDR0 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_ADDR1 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_ADDR2 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_ADDR3 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_ADDR4 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_ADDR5 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_ADDR6 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_ADDR7 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_ADDR8 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_ADDR9 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_ADDR10 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_ADDR11 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_ADDR12 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_ADDR13 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_ADDR14 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_ADDR15 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_ADDR16 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_LCD_CLS JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_LCD_SPL JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_DCS JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_RAS JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_CAS JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_SDWE JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_CKE JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_CKO JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_CS0 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_CS1 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_CS2 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_CS3 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_RD JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_WR JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_WE0 JZ_GPIO_FUNC1
++
++
++#define JZ_GPIO_MEM_ADDR21 JZ_GPIO_PORTB(17)
++#define JZ_GPIO_MEM_ADDR22 JZ_GPIO_PORTB(18)
++
++#define JZ_GPIO_FUNC_MEM_ADDR21 JZ_GPIO_FUNC2
++#define JZ_GPIO_FUNC_MEM_ADDR22 JZ_GPIO_FUNC2
++
++/* Port C function pins */
++#define JZ_GPIO_LCD_DATA0 JZ_GPIO_PORTC(0)
++#define JZ_GPIO_LCD_DATA1 JZ_GPIO_PORTC(1)
++#define JZ_GPIO_LCD_DATA2 JZ_GPIO_PORTC(2)
++#define JZ_GPIO_LCD_DATA3 JZ_GPIO_PORTC(3)
++#define JZ_GPIO_LCD_DATA4 JZ_GPIO_PORTC(4)
++#define JZ_GPIO_LCD_DATA5 JZ_GPIO_PORTC(5)
++#define JZ_GPIO_LCD_DATA6 JZ_GPIO_PORTC(6)
++#define JZ_GPIO_LCD_DATA7 JZ_GPIO_PORTC(7)
++#define JZ_GPIO_LCD_DATA8 JZ_GPIO_PORTC(8)
++#define JZ_GPIO_LCD_DATA9 JZ_GPIO_PORTC(9)
++#define JZ_GPIO_LCD_DATA10 JZ_GPIO_PORTC(10)
++#define JZ_GPIO_LCD_DATA11 JZ_GPIO_PORTC(11)
++#define JZ_GPIO_LCD_DATA12 JZ_GPIO_PORTC(12)
++#define JZ_GPIO_LCD_DATA13 JZ_GPIO_PORTC(13)
++#define JZ_GPIO_LCD_DATA14 JZ_GPIO_PORTC(14)
++#define JZ_GPIO_LCD_DATA15 JZ_GPIO_PORTC(15)
++#define JZ_GPIO_LCD_DATA16 JZ_GPIO_PORTC(16)
++#define JZ_GPIO_LCD_DATA17 JZ_GPIO_PORTC(17)
++#define JZ_GPIO_LCD_PCLK JZ_GPIO_PORTC(18)
++#define JZ_GPIO_LCD_HSYNC JZ_GPIO_PORTC(19)
++#define JZ_GPIO_LCD_VSYNC JZ_GPIO_PORTC(20)
++#define JZ_GPIO_LCD_DE JZ_GPIO_PORTC(21)
++#define JZ_GPIO_LCD_PS JZ_GPIO_PORTC(22)
++#define JZ_GPIO_LCD_REV JZ_GPIO_PORTC(23)
++#define JZ_GPIO_MEM_WE1 JZ_GPIO_PORTC(24)
++#define JZ_GPIO_MEM_WE2 JZ_GPIO_PORTC(25)
++#define JZ_GPIO_MEM_WE3 JZ_GPIO_PORTC(26)
++#define JZ_GPIO_MEM_WAIT JZ_GPIO_PORTC(27)
++#define JZ_GPIO_MEM_FRE JZ_GPIO_PORTC(28)
++#define JZ_GPIO_MEM_FWE JZ_GPIO_PORTC(29)
++
++#define JZ_GPIO_FUNC_LCD_DATA0 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_LCD_DATA1 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_LCD_DATA2 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_LCD_DATA3 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_LCD_DATA4 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_LCD_DATA5 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_LCD_DATA6 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_LCD_DATA7 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_LCD_DATA8 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_LCD_DATA9 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_LCD_DATA10 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_LCD_DATA11 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_LCD_DATA12 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_LCD_DATA13 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_LCD_DATA14 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_LCD_DATA15 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_LCD_DATA16 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_LCD_DATA17 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_LCD_PCLK JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_LCD_VSYNC JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_LCD_HSYNC JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_LCD_DE JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_LCD_PS JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_LCD_REV JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_WE1 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_WE2 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_WE3 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_WAIT JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_FRE JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MEM_FWE JZ_GPIO_FUNC1
++
++
++#define JZ_GPIO_MEM_ADDR19 JZ_GPIO_PORTB(22)
++#define JZ_GPIO_MEM_ADDR20 JZ_GPIO_PORTB(23)
++
++#define JZ_GPIO_FUNC_MEM_ADDR19 JZ_GPIO_FUNC2
++#define JZ_GPIO_FUNC_MEM_ADDR20 JZ_GPIO_FUNC2
++
++/* Port D function pins */
++#define JZ_GPIO_CIM_DATA0 JZ_GPIO_PORTD(0)
++#define JZ_GPIO_CIM_DATA1 JZ_GPIO_PORTD(1)
++#define JZ_GPIO_CIM_DATA2 JZ_GPIO_PORTD(2)
++#define JZ_GPIO_CIM_DATA3 JZ_GPIO_PORTD(3)
++#define JZ_GPIO_CIM_DATA4 JZ_GPIO_PORTD(4)
++#define JZ_GPIO_CIM_DATA5 JZ_GPIO_PORTD(5)
++#define JZ_GPIO_CIM_DATA6 JZ_GPIO_PORTD(6)
++#define JZ_GPIO_CIM_DATA7 JZ_GPIO_PORTD(7)
++#define JZ_GPIO_MSC_CMD JZ_GPIO_PORTD(8)
++#define JZ_GPIO_MSC_CLK JZ_GPIO_PORTD(9)
++#define JZ_GPIO_MSC_DATA0 JZ_GPIO_PORTD(10)
++#define JZ_GPIO_MSC_DATA1 JZ_GPIO_PORTD(11)
++#define JZ_GPIO_MSC_DATA2 JZ_GPIO_PORTD(12)
++#define JZ_GPIO_MSC_DATA3 JZ_GPIO_PORTD(13)
++#define JZ_GPIO_CIM_MCLK JZ_GPIO_PORTD(14)
++#define JZ_GPIO_CIM_PCLK JZ_GPIO_PORTD(15)
++#define JZ_GPIO_CIM_VSYNC JZ_GPIO_PORTD(16)
++#define JZ_GPIO_CIM_HSYNC JZ_GPIO_PORTD(17)
++#define JZ_GPIO_SPI_CLK JZ_GPIO_PORTD(18)
++#define JZ_GPIO_SPI_CE0 JZ_GPIO_PORTD(19)
++#define JZ_GPIO_SPI_DT JZ_GPIO_PORTD(20)
++#define JZ_GPIO_SPI_DR JZ_GPIO_PORTD(21)
++#define JZ_GPIO_SPI_CE1 JZ_GPIO_PORTD(22)
++#define JZ_GPIO_PWM0 JZ_GPIO_PORTD(23)
++#define JZ_GPIO_PWM1 JZ_GPIO_PORTD(24)
++#define JZ_GPIO_PWM2 JZ_GPIO_PORTD(25)
++#define JZ_GPIO_PWM3 JZ_GPIO_PORTD(26)
++#define JZ_GPIO_PWM4 JZ_GPIO_PORTD(27)
++#define JZ_GPIO_PWM5 JZ_GPIO_PORTD(28)
++#define JZ_GPIO_PWM6 JZ_GPIO_PORTD(30)
++#define JZ_GPIO_PWM7 JZ_GPIO_PORTD(31)
++
++#define JZ_GPIO_FUNC_CIM_DATA JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_CIM_DATA0 JZ_GPIO_FUNC_CIM_DATA
++#define JZ_GPIO_FUNC_CIM_DATA1 JZ_GPIO_FUNC_CIM_DATA
++#define JZ_GPIO_FUNC_CIM_DATA2 JZ_GPIO_FUNC_CIM_DATA
++#define JZ_GPIO_FUNC_CIM_DATA3 JZ_GPIO_FUNC_CIM_DATA
++#define JZ_GPIO_FUNC_CIM_DATA4 JZ_GPIO_FUNC_CIM_DATA
++#define JZ_GPIO_FUNC_CIM_DATA5 JZ_GPIO_FUNC_CIM_DATA
++#define JZ_GPIO_FUNC_CIM_DATA6 JZ_GPIO_FUNC_CIM_DATA
++#define JZ_GPIO_FUNC_CIM_DATA7 JZ_GPIO_FUNC_CIM_DATA
++#define JZ_GPIO_FUNC_MSC_CMD JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MSC_CLK JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MSC_DATA JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_MSC_DATA0 JZ_GPIO_FUNC_MSC_DATA
++#define JZ_GPIO_FUNC_MSC_DATA1 JZ_GPIO_FUNC_MSC_DATA
++#define JZ_GPIO_FUNC_MSC_DATA2 JZ_GPIO_FUNC_MSC_DATA
++#define JZ_GPIO_FUNC_MSC_DATA3 JZ_GPIO_FUNC_MSC_DATA
++#define JZ_GPIO_FUNC_CIM_MCLK JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_CIM_PCLK JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_CIM_VSYNC JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_CIM_HSYNC JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_SPI_CLK JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_SPI_CE0 JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_SPI_DT JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_SPI_DR JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_SPI_CE1 JZ_GPIO_FUNC1
++
++#define JZ_GPIO_FUNC_PWM JZ_GPIO_FUNC1
++#define JZ_GPIO_FUNC_PWM0 JZ_GPIO_FUNC_PWM
++#define JZ_GPIO_FUNC_PWM1 JZ_GPIO_FUNC_PWM
++#define JZ_GPIO_FUNC_PWM2 JZ_GPIO_FUNC_PWM
++#define JZ_GPIO_FUNC_PWM3 JZ_GPIO_FUNC_PWM
++#define JZ_GPIO_FUNC_PWM4 JZ_GPIO_FUNC_PWM
++#define JZ_GPIO_FUNC_PWM5 JZ_GPIO_FUNC_PWM
++#define JZ_GPIO_FUNC_PWM6 JZ_GPIO_FUNC_PWM
++#define JZ_GPIO_FUNC_PWM7 JZ_GPIO_FUNC_PWM
++
++#define JZ_GPIO_MEM_SCLK_RSTN JZ_GPIO_PORTD(18)
++#define JZ_GPIO_MEM_BCLK JZ_GPIO_PORTD(19)
++#define JZ_GPIO_MEM_SDATO JZ_GPIO_PORTD(20)
++#define JZ_GPIO_MEM_SDATI JZ_GPIO_PORTD(21)
++#define JZ_GPIO_MEM_SYNC JZ_GPIO_PORTD(22)
++#define JZ_GPIO_I2C_SDA JZ_GPIO_PORTD(23)
++#define JZ_GPIO_I2C_SCK JZ_GPIO_PORTD(24)
++#define JZ_GPIO_UART0_TXD JZ_GPIO_PORTD(25)
++#define JZ_GPIO_UART0_RXD JZ_GPIO_PORTD(26)
++#define JZ_GPIO_MEM_ADDR17 JZ_GPIO_PORTD(27)
++#define JZ_GPIO_MEM_ADDR18 JZ_GPIO_PORTD(28)
++#define JZ_GPIO_UART0_CTS JZ_GPIO_PORTD(30)
++#define JZ_GPIO_UART0_RTS JZ_GPIO_PORTD(31)
++
++#define JZ_GPIO_FUNC_MEM_SCLK_RSTN JZ_GPIO_FUNC2
++#define JZ_GPIO_FUNC_MEM_BCLK JZ_GPIO_FUNC2
++#define JZ_GPIO_FUNC_MEM_SDATO JZ_GPIO_FUNC2
++#define JZ_GPIO_FUNC_MEM_SDATI JZ_GPIO_FUNC2
++#define JZ_GPIO_FUNC_MEM_SYNC JZ_GPIO_FUNC2
++#define JZ_GPIO_FUNC_I2C_SDA JZ_GPIO_FUNC2
++#define JZ_GPIO_FUNC_I2C_SCK JZ_GPIO_FUNC2
++#define JZ_GPIO_FUNC_UART0_TXD JZ_GPIO_FUNC2
++#define JZ_GPIO_FUNC_UART0_RXD JZ_GPIO_FUNC2
++#define JZ_GPIO_FUNC_MEM_ADDR17 JZ_GPIO_FUNC2
++#define JZ_GPIO_FUNC_MEM_ADDR18 JZ_GPIO_FUNC2
++#define JZ_GPIO_FUNC_UART0_CTS JZ_GPIO_FUNC2
++#define JZ_GPIO_FUNC_UART0_RTS JZ_GPIO_FUNC2
++
++#define JZ_GPIO_UART1_RXD JZ_GPIO_PORTD(30)
++#define JZ_GPIO_UART1_TXD JZ_GPIO_PORTD(31)
++
++#define JZ_GPIO_FUNC_UART1_RXD JZ_GPIO_FUNC3
++#define JZ_GPIO_FUNC_UART1_TXD JZ_GPIO_FUNC3
++
++#endif
+--- /dev/null
++++ b/arch/mips/jz4740/gpio.c
+@@ -0,0 +1,604 @@
++/*
++ * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
++ * JZ4740 platform GPIO support
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/init.h>
++
++#include <linux/spinlock.h>
++#include <linux/sysdev.h>
++#include <linux/io.h>
++#include <linux/gpio.h>
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++#include <linux/bitops.h>
++
++#include <linux/debugfs.h>
++#include <linux/seq_file.h>
++
++#include <asm/mach-jz4740/base.h>
++
++#define JZ4740_GPIO_BASE_A (32*0)
++#define JZ4740_GPIO_BASE_B (32*1)
++#define JZ4740_GPIO_BASE_C (32*2)
++#define JZ4740_GPIO_BASE_D (32*3)
++
++#define JZ4740_GPIO_NUM_A 32
++#define JZ4740_GPIO_NUM_B 32
++#define JZ4740_GPIO_NUM_C 31
++#define JZ4740_GPIO_NUM_D 32
++
++#define JZ4740_IRQ_GPIO_BASE_A (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_A)
++#define JZ4740_IRQ_GPIO_BASE_B (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_B)
++#define JZ4740_IRQ_GPIO_BASE_C (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_C)
++#define JZ4740_IRQ_GPIO_BASE_D (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_D)
++
++#define JZ_REG_GPIO_PIN 0x00
++#define JZ_REG_GPIO_DATA 0x10
++#define JZ_REG_GPIO_DATA_SET 0x14
++#define JZ_REG_GPIO_DATA_CLEAR 0x18
++#define JZ_REG_GPIO_MASK 0x20
++#define JZ_REG_GPIO_MASK_SET 0x24
++#define JZ_REG_GPIO_MASK_CLEAR 0x28
++#define JZ_REG_GPIO_PULL 0x30
++#define JZ_REG_GPIO_PULL_SET 0x34
++#define JZ_REG_GPIO_PULL_CLEAR 0x38
++#define JZ_REG_GPIO_FUNC 0x40
++#define JZ_REG_GPIO_FUNC_SET 0x44
++#define JZ_REG_GPIO_FUNC_CLEAR 0x48
++#define JZ_REG_GPIO_SELECT 0x50
++#define JZ_REG_GPIO_SELECT_SET 0x54
++#define JZ_REG_GPIO_SELECT_CLEAR 0x58
++#define JZ_REG_GPIO_DIRECTION 0x60
++#define JZ_REG_GPIO_DIRECTION_SET 0x64
++#define JZ_REG_GPIO_DIRECTION_CLEAR 0x68
++#define JZ_REG_GPIO_TRIGGER 0x70
++#define JZ_REG_GPIO_TRIGGER_SET 0x74
++#define JZ_REG_GPIO_TRIGGER_CLEAR 0x78
++#define JZ_REG_GPIO_FLAG 0x80
++#define JZ_REG_GPIO_FLAG_CLEAR 0x14
++
++#define GPIO_TO_BIT(gpio) BIT(gpio & 0x1f)
++#define GPIO_TO_REG(gpio, reg) (gpio_to_jz_gpio_chip(gpio)->base + (reg))
++#define CHIP_TO_REG(chip, reg) (gpio_chip_to_jz_gpio_chip(chip)->base + (reg))
++
++struct jz_gpio_chip {
++ unsigned int irq;
++ unsigned int irq_base;
++ uint32_t wakeup;
++ uint32_t suspend_mask;
++ uint32_t edge_trigger_both;
++
++ void __iomem *base;
++
++ spinlock_t lock;
++
++ struct gpio_chip gpio_chip;
++ struct irq_chip irq_chip;
++ struct sys_device sysdev;
++};
++
++static struct jz_gpio_chip jz4740_gpio_chips[];
++
++static inline struct jz_gpio_chip *gpio_to_jz_gpio_chip(unsigned int gpio)
++{
++ return &jz4740_gpio_chips[gpio >> 5];
++}
++
++static inline struct jz_gpio_chip *gpio_chip_to_jz_gpio_chip(struct gpio_chip *gpio_chip)
++{
++ return container_of(gpio_chip, struct jz_gpio_chip, gpio_chip);
++}
++
++static inline struct jz_gpio_chip *irq_to_jz_gpio_chip(unsigned int irq)
++{
++ return get_irq_chip_data(irq);
++}
++
++static inline void jz_gpio_write_bit(unsigned int gpio, unsigned int reg)
++{
++ writel(GPIO_TO_BIT(gpio), GPIO_TO_REG(gpio, reg));
++}
++
++int jz_gpio_set_function(int gpio, enum jz_gpio_function function)
++{
++ if (function == JZ_GPIO_FUNC_NONE) {
++ jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_CLEAR);
++ jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
++ jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
++ } else {
++ jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_SET);
++ jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
++ switch (function) {
++ case JZ_GPIO_FUNC1:
++ jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
++ break;
++ case JZ_GPIO_FUNC3:
++ jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_SET);
++ case JZ_GPIO_FUNC2: /* Falltrough */
++ jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_SET);
++ break;
++ default:
++ BUG();
++ break;
++ }
++ }
++
++ return 0;
++}
++EXPORT_SYMBOL_GPL(jz_gpio_set_function);
++
++int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num)
++{
++ size_t i;
++ int ret;
++
++ for (i = 0; i < num; ++i, ++request) {
++ ret = gpio_request(request->gpio, request->name);
++ if (ret)
++ goto err;
++ jz_gpio_set_function(request->gpio, request->function);
++ }
++
++ return 0;
++
++err:
++ for (--request; i > 0; --i, --request) {
++ gpio_free(request->gpio);
++ jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
++ }
++
++ return ret;
++}
++EXPORT_SYMBOL_GPL(jz_gpio_bulk_request);
++
++void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num)
++{
++ size_t i;
++
++ for (i = 0; i < num; ++i, ++request) {
++ gpio_free(request->gpio);
++ jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
++ }
++
++}
++EXPORT_SYMBOL_GPL(jz_gpio_bulk_free);
++
++void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num)
++{
++ size_t i;
++
++ for (i = 0; i < num; ++i, ++request) {
++ jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
++ jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_DIRECTION_CLEAR);
++ jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_PULL_SET);
++ }
++}
++EXPORT_SYMBOL_GPL(jz_gpio_bulk_suspend);
++
++void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num)
++{
++ size_t i;
++
++ for (i = 0; i < num; ++i, ++request)
++ jz_gpio_set_function(request->gpio, request->function);
++}
++EXPORT_SYMBOL_GPL(jz_gpio_bulk_resume);
++
++void jz_gpio_enable_pullup(unsigned gpio)
++{
++ jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_CLEAR);
++}
++EXPORT_SYMBOL_GPL(jz_gpio_enable_pullup);
++
++void jz_gpio_disable_pullup(unsigned gpio)
++{
++ jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_SET);
++}
++EXPORT_SYMBOL_GPL(jz_gpio_disable_pullup);
++
++static int jz_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
++{
++ return !!(readl(CHIP_TO_REG(chip, JZ_REG_GPIO_PIN)) & BIT(gpio));
++}
++
++static void jz_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
++{
++ uint32_t __iomem *reg = CHIP_TO_REG(chip, JZ_REG_GPIO_DATA_SET);
++ reg += !value;
++ writel(BIT(gpio), reg);
++}
++
++static int jz_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
++ int value)
++{
++ writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_SET));
++ jz_gpio_set_value(chip, gpio, value);
++
++ return 0;
++}
++
++static int jz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
++{
++ writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_CLEAR));
++
++ return 0;
++}
++
++int jz_gpio_port_direction_input(int port, uint32_t mask)
++{
++ writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_CLEAR));
++
++ return 0;
++}
++EXPORT_SYMBOL(jz_gpio_port_direction_input);
++
++int jz_gpio_port_direction_output(int port, uint32_t mask)
++{
++ writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_SET));
++
++ return 0;
++}
++EXPORT_SYMBOL(jz_gpio_port_direction_output);
++
++void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask)
++{
++ writel(~value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_CLEAR));
++ writel(value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_SET));
++}
++EXPORT_SYMBOL(jz_gpio_port_set_value);
++
++uint32_t jz_gpio_port_get_value(int port, uint32_t mask)
++{
++ uint32_t value = readl(GPIO_TO_REG(port, JZ_REG_GPIO_PIN));
++
++ return value & mask;
++}
++EXPORT_SYMBOL(jz_gpio_port_get_value);
++
++int gpio_to_irq(unsigned gpio)
++{
++ return JZ4740_IRQ_GPIO(0) + gpio;
++}
++EXPORT_SYMBOL_GPL(gpio_to_irq);
++
++int irq_to_gpio(unsigned irq)
++{
++ return irq - JZ4740_IRQ_GPIO(0);
++}
++EXPORT_SYMBOL_GPL(irq_to_gpio);
++
++#define IRQ_TO_BIT(irq) BIT(irq_to_gpio(irq) & 0x1f)
++
++static void jz_gpio_check_trigger_both(struct jz_gpio_chip *chip, unsigned int irq)
++{
++ uint32_t value;
++ void __iomem *reg;
++ uint32_t mask = IRQ_TO_BIT(irq);
++
++ if (!(chip->edge_trigger_both & mask))
++ return;
++
++ reg = chip->base;
++
++ value = readl(chip->base + JZ_REG_GPIO_PIN);
++ if (value & mask)
++ reg += JZ_REG_GPIO_DIRECTION_CLEAR;
++ else
++ reg += JZ_REG_GPIO_DIRECTION_SET;
++
++ writel(mask, reg);
++}
++
++static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
++{
++ uint32_t flag;
++ unsigned int gpio_irq;
++ unsigned int gpio_bank;
++ struct jz_gpio_chip *chip = get_irq_desc_data(desc);
++
++ gpio_bank = JZ4740_IRQ_GPIO0 - irq;
++
++ flag = readl(chip->base + JZ_REG_GPIO_FLAG);
++
++ if (!flag)
++ return;
++
++ gpio_irq = __fls(flag);
++
++ jz_gpio_check_trigger_both(chip, irq);
++
++ gpio_irq += (gpio_bank << 5) + JZ4740_IRQ_GPIO(0);
++
++ generic_handle_irq(gpio_irq);
++};
++
++static inline void jz_gpio_set_irq_bit(unsigned int irq, unsigned int reg)
++{
++ struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq);
++ writel(IRQ_TO_BIT(irq), chip->base + reg);
++}
++
++static void jz_gpio_irq_mask(unsigned int irq)
++{
++ jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_SET);
++};
++
++static void jz_gpio_irq_unmask(unsigned int irq)
++{
++ struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq);
++
++ jz_gpio_check_trigger_both(chip, irq);
++
++ jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_CLEAR);
++};
++
++/* TODO: Check if function is gpio */
++static unsigned int jz_gpio_irq_startup(unsigned int irq)
++{
++ struct irq_desc *desc = irq_to_desc(irq);
++
++ jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_SET);
++
++ desc->status &= ~IRQ_MASKED;
++ jz_gpio_irq_unmask(irq);
++
++ return 0;
++}
++
++static void jz_gpio_irq_shutdown(unsigned int irq)
++{
++ struct irq_desc *desc = irq_to_desc(irq);
++
++ jz_gpio_irq_mask(irq);
++ desc->status |= IRQ_MASKED;
++
++ /* Set direction to input */
++ jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
++ jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_CLEAR);
++}
++
++static void jz_gpio_irq_ack(unsigned int irq)
++{
++ jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_FLAG_CLEAR);
++};
++
++static int jz_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
++{
++ struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq);
++ struct irq_desc *desc = irq_to_desc(irq);
++
++ jz_gpio_irq_mask(irq);
++
++ if (flow_type == IRQ_TYPE_EDGE_BOTH) {
++ uint32_t value = readl(chip->base + JZ_REG_GPIO_PIN);
++ if (value & IRQ_TO_BIT(irq))
++ flow_type = IRQ_TYPE_EDGE_FALLING;
++ else
++ flow_type = IRQ_TYPE_EDGE_RISING;
++ chip->edge_trigger_both |= IRQ_TO_BIT(irq);
++ } else {
++ chip->edge_trigger_both &= ~IRQ_TO_BIT(irq);
++ }
++
++ switch (flow_type) {
++ case IRQ_TYPE_EDGE_RISING:
++ jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET);
++ jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET);
++ break;
++ case IRQ_TYPE_EDGE_FALLING:
++ jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
++ jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET);
++ break;
++ case IRQ_TYPE_LEVEL_HIGH:
++ jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET);
++ jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR);
++ break;
++ case IRQ_TYPE_LEVEL_LOW:
++ jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
++ jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR);
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ if (!(desc->status & IRQ_MASKED))
++ jz_gpio_irq_unmask(irq);
++
++ return 0;
++}
++
++static int jz_gpio_irq_set_wake(unsigned int irq, unsigned int on)
++{
++ struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq);
++ spin_lock(&chip->lock);
++ if (on)
++ chip->wakeup |= IRQ_TO_BIT(irq);
++ else
++ chip->wakeup &= ~IRQ_TO_BIT(irq);
++ spin_unlock(&chip->lock);
++
++ set_irq_wake(chip->irq, on);
++ return 0;
++}
++
++/*
++ * This lock class tells lockdep that GPIO irqs are in a different
++ * category than their parents, so it won't report false recursion.
++ */
++static struct lock_class_key gpio_lock_class;
++
++#define JZ4740_GPIO_CHIP(_bank) { \
++ .irq_base = JZ4740_IRQ_GPIO_BASE_ ## _bank, \
++ .gpio_chip = { \
++ .label = "Bank " # _bank, \
++ .owner = THIS_MODULE, \
++ .set = jz_gpio_set_value, \
++ .get = jz_gpio_get_value, \
++ .direction_output = jz_gpio_direction_output, \
++ .direction_input = jz_gpio_direction_input, \
++ .base = JZ4740_GPIO_BASE_ ## _bank, \
++ .ngpio = JZ4740_GPIO_NUM_ ## _bank, \
++ }, \
++ .irq_chip = { \
++ .name = "GPIO Bank " # _bank, \
++ .mask = jz_gpio_irq_mask, \
++ .unmask = jz_gpio_irq_unmask, \
++ .ack = jz_gpio_irq_ack, \
++ .startup = jz_gpio_irq_startup, \
++ .shutdown = jz_gpio_irq_shutdown, \
++ .set_type = jz_gpio_irq_set_type, \
++ .set_wake = jz_gpio_irq_set_wake, \
++ }, \
++}
++
++static struct jz_gpio_chip jz4740_gpio_chips[] = {
++ JZ4740_GPIO_CHIP(A),
++ JZ4740_GPIO_CHIP(B),
++ JZ4740_GPIO_CHIP(C),
++ JZ4740_GPIO_CHIP(D),
++};
++
++static inline struct jz_gpio_chip *sysdev_to_chip(struct sys_device *dev)
++{
++ return container_of(dev, struct jz_gpio_chip, sysdev);
++}
++
++static int jz4740_gpio_suspend(struct sys_device *dev, pm_message_t state)
++{
++ struct jz_gpio_chip *chip = sysdev_to_chip(dev);
++
++ chip->suspend_mask = readl(chip->base + JZ_REG_GPIO_MASK);
++ writel(~(chip->wakeup), chip->base + JZ_REG_GPIO_MASK_SET);
++ writel(chip->wakeup, chip->base + JZ_REG_GPIO_MASK_CLEAR);
++
++ return 0;
++}
++
++static int jz4740_gpio_resume(struct sys_device *dev)
++{
++ struct jz_gpio_chip *chip = sysdev_to_chip(dev);
++ uint32_t mask = chip->suspend_mask;
++
++ writel(~mask, chip->base + JZ_REG_GPIO_MASK_CLEAR);
++ writel(mask, chip->base + JZ_REG_GPIO_MASK_SET);
++
++ return 0;
++}
++
++static struct sysdev_class jz4740_gpio_sysdev_class = {
++ .name = "gpio",
++ .suspend = jz4740_gpio_suspend,
++ .resume = jz4740_gpio_resume,
++};
++
++static int jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
++{
++ int ret, irq;
++
++ chip->sysdev.id = id;
++ chip->sysdev.cls = &jz4740_gpio_sysdev_class;
++ ret = sysdev_register(&chip->sysdev);
++
++ if (ret)
++ return ret;
++
++ spin_lock_init(&chip->lock);
++
++ chip->base = ioremap(JZ4740_GPIO_BASE_ADDR + (id * 0x100), 0x100);
++
++ gpiochip_add(&chip->gpio_chip);
++
++ chip->irq = JZ4740_IRQ_INTC_GPIO(id);
++ set_irq_data(chip->irq, chip);
++ set_irq_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
++
++ for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) {
++ lockdep_set_class(&irq_desc[irq].lock, &gpio_lock_class);
++ set_irq_chip_data(irq, chip);
++ set_irq_chip_and_handler(irq, &chip->irq_chip, handle_level_irq);
++ }
++
++ return 0;
++}
++
++static int __init jz4740_gpio_init(void)
++{
++ unsigned int i;
++ int ret;
++
++ ret = sysdev_class_register(&jz4740_gpio_sysdev_class);
++ if (ret)
++ return ret;
++
++ for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i)
++ jz4740_gpio_chip_init(&jz4740_gpio_chips[i], i);
++
++ printk(KERN_INFO "JZ4740 GPIO initalized\n");
++
++ return 0;
++}
++arch_initcall(jz4740_gpio_init);
++
++#ifdef CONFIG_DEBUG_FS
++
++static inline void gpio_seq_reg(struct seq_file *s, struct jz_gpio_chip *chip,
++ const char *name, unsigned int reg)
++{
++ seq_printf(s, "\t%s: %08x\n", name, readl(chip->base + reg));
++}
++
++static int gpio_regs_show(struct seq_file *s, void *unused)
++{
++ struct jz_gpio_chip *chip = jz4740_gpio_chips;
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i, ++chip) {
++ seq_printf(s, "==GPIO %d==\n", i);
++ gpio_seq_reg(s, chip, "Pin", JZ_REG_GPIO_PIN);
++ gpio_seq_reg(s, chip, "Data", JZ_REG_GPIO_DATA);
++ gpio_seq_reg(s, chip, "Mask", JZ_REG_GPIO_MASK);
++ gpio_seq_reg(s, chip, "Pull", JZ_REG_GPIO_PULL);
++ gpio_seq_reg(s, chip, "Func", JZ_REG_GPIO_FUNC);
++ gpio_seq_reg(s, chip, "Select", JZ_REG_GPIO_SELECT);
++ gpio_seq_reg(s, chip, "Direction", JZ_REG_GPIO_DIRECTION);
++ gpio_seq_reg(s, chip, "Trigger", JZ_REG_GPIO_TRIGGER);
++ gpio_seq_reg(s, chip, "Flag", JZ_REG_GPIO_FLAG);
++ }
++
++ return 0;
++}
++
++static int gpio_regs_open(struct inode *inode, struct file *file)
++{
++ return single_open(file, gpio_regs_show, NULL);
++}
++
++static const struct file_operations gpio_regs_operations = {
++ .open = gpio_regs_open,
++ .read = seq_read,
++ .llseek = seq_lseek,
++ .release = single_release,
++};
++
++static int __init gpio_debugfs_init(void)
++{
++ (void) debugfs_create_file("jz_regs_gpio", S_IFREG | S_IRUGO,
++ NULL, NULL, &gpio_regs_operations);
++ return 0;
++}
++subsys_initcall(gpio_debugfs_init);
++
++#endif
--- /dev/null
+From ced95a5a9d7a3ba168e8518d9b5004c9a0cad1fe Mon Sep 17 00:00:00 2001
+From: Lars-Peter Clausen <lars@metafoo.de>
+Date: Sat, 19 Jun 2010 04:08:14 +0000
+Subject: [PATCH] MIPS: JZ4740: Add DMA support.
+
+Add support for DMA transfers on JZ4740 SoCs.
+
+Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
+Cc: linux-mips@linux-mips.org
+Cc: linux-kernel@vger.kernel.org
+Patchwork: https://patchwork.linux-mips.org/patch/1401/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/include/asm/mach-jz4740/dma.h | 90 ++++++++++
+ arch/mips/jz4740/dma.c | 289 +++++++++++++++++++++++++++++++
+ 2 files changed, 379 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/include/asm/mach-jz4740/dma.h
+ create mode 100644 arch/mips/jz4740/dma.c
+
+--- /dev/null
++++ b/arch/mips/include/asm/mach-jz4740/dma.h
+@@ -0,0 +1,90 @@
++/*
++ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
++ * JZ7420/JZ4740 DMA definitions
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#ifndef __ASM_MACH_JZ4740_DMA_H__
++#define __ASM_MACH_JZ4740_DMA_H__
++
++struct jz4740_dma_chan;
++
++enum jz4740_dma_request_type {
++ JZ4740_DMA_TYPE_AUTO_REQUEST = 8,
++ JZ4740_DMA_TYPE_UART_TRANSMIT = 20,
++ JZ4740_DMA_TYPE_UART_RECEIVE = 21,
++ JZ4740_DMA_TYPE_SPI_TRANSMIT = 22,
++ JZ4740_DMA_TYPE_SPI_RECEIVE = 23,
++ JZ4740_DMA_TYPE_AIC_TRANSMIT = 24,
++ JZ4740_DMA_TYPE_AIC_RECEIVE = 25,
++ JZ4740_DMA_TYPE_MMC_TRANSMIT = 26,
++ JZ4740_DMA_TYPE_MMC_RECEIVE = 27,
++ JZ4740_DMA_TYPE_TCU = 28,
++ JZ4740_DMA_TYPE_SADC = 29,
++ JZ4740_DMA_TYPE_SLCD = 30,
++};
++
++enum jz4740_dma_width {
++ JZ4740_DMA_WIDTH_32BIT = 0,
++ JZ4740_DMA_WIDTH_8BIT = 1,
++ JZ4740_DMA_WIDTH_16BIT = 2,
++};
++
++enum jz4740_dma_transfer_size {
++ JZ4740_DMA_TRANSFER_SIZE_4BYTE = 0,
++ JZ4740_DMA_TRANSFER_SIZE_1BYTE = 1,
++ JZ4740_DMA_TRANSFER_SIZE_2BYTE = 2,
++ JZ4740_DMA_TRANSFER_SIZE_16BYTE = 3,
++ JZ4740_DMA_TRANSFER_SIZE_32BYTE = 4,
++};
++
++enum jz4740_dma_flags {
++ JZ4740_DMA_SRC_AUTOINC = 0x2,
++ JZ4740_DMA_DST_AUTOINC = 0x1,
++};
++
++enum jz4740_dma_mode {
++ JZ4740_DMA_MODE_SINGLE = 0,
++ JZ4740_DMA_MODE_BLOCK = 1,
++};
++
++struct jz4740_dma_config {
++ enum jz4740_dma_width src_width;
++ enum jz4740_dma_width dst_width;
++ enum jz4740_dma_transfer_size transfer_size;
++ enum jz4740_dma_request_type request_type;
++ enum jz4740_dma_flags flags;
++ enum jz4740_dma_mode mode;
++};
++
++typedef void (*jz4740_dma_complete_callback_t)(struct jz4740_dma_chan *, int, void *);
++
++struct jz4740_dma_chan *jz4740_dma_request(void *dev, const char *name);
++void jz4740_dma_free(struct jz4740_dma_chan *dma);
++
++void jz4740_dma_configure(struct jz4740_dma_chan *dma,
++ const struct jz4740_dma_config *config);
++
++
++void jz4740_dma_enable(struct jz4740_dma_chan *dma);
++void jz4740_dma_disable(struct jz4740_dma_chan *dma);
++
++void jz4740_dma_set_src_addr(struct jz4740_dma_chan *dma, dma_addr_t src);
++void jz4740_dma_set_dst_addr(struct jz4740_dma_chan *dma, dma_addr_t dst);
++void jz4740_dma_set_transfer_count(struct jz4740_dma_chan *dma, uint32_t count);
++
++uint32_t jz4740_dma_get_residue(const struct jz4740_dma_chan *dma);
++
++void jz4740_dma_set_complete_cb(struct jz4740_dma_chan *dma,
++ jz4740_dma_complete_callback_t cb);
++
++#endif /* __ASM_JZ4740_DMA_H__ */
+--- /dev/null
++++ b/arch/mips/jz4740/dma.c
+@@ -0,0 +1,289 @@
++/*
++ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
++ * JZ4740 SoC DMA support
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/spinlock.h>
++#include <linux/interrupt.h>
++
++#include <linux/dma-mapping.h>
++#include <asm/mach-jz4740/dma.h>
++#include <asm/mach-jz4740/base.h>
++
++#define JZ_REG_DMA_SRC_ADDR(x) (0x00 + (x) * 0x20)
++#define JZ_REG_DMA_DST_ADDR(x) (0x04 + (x) * 0x20)
++#define JZ_REG_DMA_TRANSFER_COUNT(x) (0x08 + (x) * 0x20)
++#define JZ_REG_DMA_REQ_TYPE(x) (0x0C + (x) * 0x20)
++#define JZ_REG_DMA_STATUS_CTRL(x) (0x10 + (x) * 0x20)
++#define JZ_REG_DMA_CMD(x) (0x14 + (x) * 0x20)
++#define JZ_REG_DMA_DESC_ADDR(x) (0x18 + (x) * 0x20)
++
++#define JZ_REG_DMA_CTRL 0x300
++#define JZ_REG_DMA_IRQ 0x304
++#define JZ_REG_DMA_DOORBELL 0x308
++#define JZ_REG_DMA_DOORBELL_SET 0x30C
++
++#define JZ_DMA_STATUS_CTRL_NO_DESC BIT(31)
++#define JZ_DMA_STATUS_CTRL_DESC_INV BIT(6)
++#define JZ_DMA_STATUS_CTRL_ADDR_ERR BIT(4)
++#define JZ_DMA_STATUS_CTRL_TRANSFER_DONE BIT(3)
++#define JZ_DMA_STATUS_CTRL_HALT BIT(2)
++#define JZ_DMA_STATUS_CTRL_COUNT_TERMINATE BIT(1)
++#define JZ_DMA_STATUS_CTRL_ENABLE BIT(0)
++
++#define JZ_DMA_CMD_SRC_INC BIT(23)
++#define JZ_DMA_CMD_DST_INC BIT(22)
++#define JZ_DMA_CMD_RDIL_MASK (0xf << 16)
++#define JZ_DMA_CMD_SRC_WIDTH_MASK (0x3 << 14)
++#define JZ_DMA_CMD_DST_WIDTH_MASK (0x3 << 12)
++#define JZ_DMA_CMD_INTERVAL_LENGTH_MASK (0x7 << 8)
++#define JZ_DMA_CMD_BLOCK_MODE BIT(7)
++#define JZ_DMA_CMD_DESC_VALID BIT(4)
++#define JZ_DMA_CMD_DESC_VALID_MODE BIT(3)
++#define JZ_DMA_CMD_VALID_IRQ_ENABLE BIT(2)
++#define JZ_DMA_CMD_TRANSFER_IRQ_ENABLE BIT(1)
++#define JZ_DMA_CMD_LINK_ENABLE BIT(0)
++
++#define JZ_DMA_CMD_FLAGS_OFFSET 22
++#define JZ_DMA_CMD_RDIL_OFFSET 16
++#define JZ_DMA_CMD_SRC_WIDTH_OFFSET 14
++#define JZ_DMA_CMD_DST_WIDTH_OFFSET 12
++#define JZ_DMA_CMD_TRANSFER_SIZE_OFFSET 8
++#define JZ_DMA_CMD_MODE_OFFSET 7
++
++#define JZ_DMA_CTRL_PRIORITY_MASK (0x3 << 8)
++#define JZ_DMA_CTRL_HALT BIT(3)
++#define JZ_DMA_CTRL_ADDRESS_ERROR BIT(2)
++#define JZ_DMA_CTRL_ENABLE BIT(0)
++
++
++static void __iomem *jz4740_dma_base;
++static spinlock_t jz4740_dma_lock;
++
++static inline uint32_t jz4740_dma_read(size_t reg)
++{
++ return readl(jz4740_dma_base + reg);
++}
++
++static inline void jz4740_dma_write(size_t reg, uint32_t val)
++{
++ writel(val, jz4740_dma_base + reg);
++}
++
++static inline void jz4740_dma_write_mask(size_t reg, uint32_t val, uint32_t mask)
++{
++ uint32_t val2;
++ val2 = jz4740_dma_read(reg);
++ val2 &= ~mask;
++ val2 |= val;
++ jz4740_dma_write(reg, val2);
++}
++
++struct jz4740_dma_chan {
++ unsigned int id;
++ void *dev;
++ const char *name;
++
++ enum jz4740_dma_flags flags;
++ uint32_t transfer_shift;
++
++ jz4740_dma_complete_callback_t complete_cb;
++
++ unsigned used:1;
++};
++
++#define JZ4740_DMA_CHANNEL(_id) { .id = _id }
++
++struct jz4740_dma_chan jz4740_dma_channels[] = {
++ JZ4740_DMA_CHANNEL(0),
++ JZ4740_DMA_CHANNEL(1),
++ JZ4740_DMA_CHANNEL(2),
++ JZ4740_DMA_CHANNEL(3),
++ JZ4740_DMA_CHANNEL(4),
++ JZ4740_DMA_CHANNEL(5),
++};
++
++struct jz4740_dma_chan *jz4740_dma_request(void *dev, const char *name)
++{
++ unsigned int i;
++ struct jz4740_dma_chan *dma = NULL;
++
++ spin_lock(&jz4740_dma_lock);
++
++ for (i = 0; i < ARRAY_SIZE(jz4740_dma_channels); ++i) {
++ if (!jz4740_dma_channels[i].used) {
++ dma = &jz4740_dma_channels[i];
++ dma->used = 1;
++ break;
++ }
++ }
++
++ spin_unlock(&jz4740_dma_lock);
++
++ if (!dma)
++ return NULL;
++
++ dma->dev = dev;
++ dma->name = name;
++
++ return dma;
++}
++EXPORT_SYMBOL_GPL(jz4740_dma_request);
++
++void jz4740_dma_configure(struct jz4740_dma_chan *dma,
++ const struct jz4740_dma_config *config)
++{
++ uint32_t cmd;
++
++ switch (config->transfer_size) {
++ case JZ4740_DMA_TRANSFER_SIZE_2BYTE:
++ dma->transfer_shift = 1;
++ break;
++ case JZ4740_DMA_TRANSFER_SIZE_4BYTE:
++ dma->transfer_shift = 2;
++ break;
++ case JZ4740_DMA_TRANSFER_SIZE_16BYTE:
++ dma->transfer_shift = 4;
++ break;
++ case JZ4740_DMA_TRANSFER_SIZE_32BYTE:
++ dma->transfer_shift = 5;
++ break;
++ default:
++ dma->transfer_shift = 0;
++ break;
++ }
++
++ cmd = config->flags << JZ_DMA_CMD_FLAGS_OFFSET;
++ cmd |= config->src_width << JZ_DMA_CMD_SRC_WIDTH_OFFSET;
++ cmd |= config->dst_width << JZ_DMA_CMD_DST_WIDTH_OFFSET;
++ cmd |= config->transfer_size << JZ_DMA_CMD_TRANSFER_SIZE_OFFSET;
++ cmd |= config->mode << JZ_DMA_CMD_MODE_OFFSET;
++ cmd |= JZ_DMA_CMD_TRANSFER_IRQ_ENABLE;
++
++ jz4740_dma_write(JZ_REG_DMA_CMD(dma->id), cmd);
++ jz4740_dma_write(JZ_REG_DMA_STATUS_CTRL(dma->id), 0);
++ jz4740_dma_write(JZ_REG_DMA_REQ_TYPE(dma->id), config->request_type);
++}
++EXPORT_SYMBOL_GPL(jz4740_dma_configure);
++
++void jz4740_dma_set_src_addr(struct jz4740_dma_chan *dma, dma_addr_t src)
++{
++ jz4740_dma_write(JZ_REG_DMA_SRC_ADDR(dma->id), src);
++}
++EXPORT_SYMBOL_GPL(jz4740_dma_set_src_addr);
++
++void jz4740_dma_set_dst_addr(struct jz4740_dma_chan *dma, dma_addr_t dst)
++{
++ jz4740_dma_write(JZ_REG_DMA_DST_ADDR(dma->id), dst);
++}
++EXPORT_SYMBOL_GPL(jz4740_dma_set_dst_addr);
++
++void jz4740_dma_set_transfer_count(struct jz4740_dma_chan *dma, uint32_t count)
++{
++ count >>= dma->transfer_shift;
++ jz4740_dma_write(JZ_REG_DMA_TRANSFER_COUNT(dma->id), count);
++}
++EXPORT_SYMBOL_GPL(jz4740_dma_set_transfer_count);
++
++void jz4740_dma_set_complete_cb(struct jz4740_dma_chan *dma,
++ jz4740_dma_complete_callback_t cb)
++{
++ dma->complete_cb = cb;
++}
++EXPORT_SYMBOL_GPL(jz4740_dma_set_complete_cb);
++
++void jz4740_dma_free(struct jz4740_dma_chan *dma)
++{
++ dma->dev = NULL;
++ dma->complete_cb = NULL;
++ dma->used = 0;
++}
++EXPORT_SYMBOL_GPL(jz4740_dma_free);
++
++void jz4740_dma_enable(struct jz4740_dma_chan *dma)
++{
++ jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id),
++ JZ_DMA_STATUS_CTRL_NO_DESC | JZ_DMA_STATUS_CTRL_ENABLE,
++ JZ_DMA_STATUS_CTRL_HALT | JZ_DMA_STATUS_CTRL_NO_DESC |
++ JZ_DMA_STATUS_CTRL_ENABLE);
++
++ jz4740_dma_write_mask(JZ_REG_DMA_CTRL,
++ JZ_DMA_CTRL_ENABLE,
++ JZ_DMA_CTRL_HALT | JZ_DMA_CTRL_ENABLE);
++}
++EXPORT_SYMBOL_GPL(jz4740_dma_enable);
++
++void jz4740_dma_disable(struct jz4740_dma_chan *dma)
++{
++ jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id), 0,
++ JZ_DMA_STATUS_CTRL_ENABLE);
++}
++EXPORT_SYMBOL_GPL(jz4740_dma_disable);
++
++uint32_t jz4740_dma_get_residue(const struct jz4740_dma_chan *dma)
++{
++ uint32_t residue;
++ residue = jz4740_dma_read(JZ_REG_DMA_TRANSFER_COUNT(dma->id));
++ return residue << dma->transfer_shift;
++}
++EXPORT_SYMBOL_GPL(jz4740_dma_get_residue);
++
++static void jz4740_dma_chan_irq(struct jz4740_dma_chan *dma)
++{
++ uint32_t status;
++
++ status = jz4740_dma_read(JZ_REG_DMA_STATUS_CTRL(dma->id));
++
++ jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id), 0,
++ JZ_DMA_STATUS_CTRL_ENABLE | JZ_DMA_STATUS_CTRL_TRANSFER_DONE);
++
++ if (dma->complete_cb)
++ dma->complete_cb(dma, 0, dma->dev);
++}
++
++static irqreturn_t jz4740_dma_irq(int irq, void *dev_id)
++{
++ uint32_t irq_status;
++ unsigned int i;
++
++ irq_status = readl(jz4740_dma_base + JZ_REG_DMA_IRQ);
++
++ for (i = 0; i < 6; ++i) {
++ if (irq_status & (1 << i))
++ jz4740_dma_chan_irq(&jz4740_dma_channels[i]);
++ }
++
++ return IRQ_HANDLED;
++}
++
++static int jz4740_dma_init(void)
++{
++ unsigned int ret;
++
++ jz4740_dma_base = ioremap(JZ4740_DMAC_BASE_ADDR, 0x400);
++
++ if (!jz4740_dma_base)
++ return -EBUSY;
++
++ spin_lock_init(&jz4740_dma_lock);
++
++ ret = request_irq(JZ4740_IRQ_DMAC, jz4740_dma_irq, 0, "DMA", NULL);
++
++ if (ret)
++ printk(KERN_ERR "JZ4740 DMA: Failed to request irq: %d\n", ret);
++
++ return ret;
++}
++arch_initcall(jz4740_dma_init);
--- /dev/null
+From 5cd5a44b94b451ecaf593bb49919cfbb51ccb622 Mon Sep 17 00:00:00 2001
+From: Lars-Peter Clausen <lars@metafoo.de>
+Date: Sat, 17 Jul 2010 11:12:20 +0000
+Subject: [PATCH] MIPS: JZ4740: Add PWM support
+
+Add support for the PWM part of the timer unit on a JZ4740 SoC.
+
+Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
+Cc: linux-mips@linux-mips.org
+Cc: linux-kernel@vger.kernel.org
+Patchwork: https://patchwork.linux-mips.org/patch/1468/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/jz4740/pwm.c | 177 ++++++++++++++++++++++++++++++++++++++++++++++++
+ 1 files changed, 177 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/jz4740/pwm.c
+
+--- /dev/null
++++ b/arch/mips/jz4740/pwm.c
+@@ -0,0 +1,177 @@
++/*
++ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
++ * JZ4740 platform PWM support
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/kernel.h>
++
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/pwm.h>
++#include <linux/gpio.h>
++
++#include <asm/mach-jz4740/gpio.h>
++#include "timer.h"
++
++static struct clk *jz4740_pwm_clk;
++
++DEFINE_MUTEX(jz4740_pwm_mutex);
++
++struct pwm_device {
++ unsigned int id;
++ unsigned int gpio;
++ bool used;
++};
++
++static struct pwm_device jz4740_pwm_list[] = {
++ { 2, JZ_GPIO_PWM2, false },
++ { 3, JZ_GPIO_PWM3, false },
++ { 4, JZ_GPIO_PWM4, false },
++ { 5, JZ_GPIO_PWM5, false },
++ { 6, JZ_GPIO_PWM6, false },
++ { 7, JZ_GPIO_PWM7, false },
++};
++
++struct pwm_device *pwm_request(int id, const char *label)
++{
++ int ret = 0;
++ struct pwm_device *pwm;
++
++ if (id < 2 || id > 7 || !jz4740_pwm_clk)
++ return ERR_PTR(-ENODEV);
++
++ mutex_lock(&jz4740_pwm_mutex);
++
++ pwm = &jz4740_pwm_list[id - 2];
++ if (pwm->used)
++ ret = -EBUSY;
++ else
++ pwm->used = true;
++
++ mutex_unlock(&jz4740_pwm_mutex);
++
++ if (ret)
++ return ERR_PTR(ret);
++
++ ret = gpio_request(pwm->gpio, label);
++
++ if (ret) {
++ printk(KERN_ERR "Failed to request pwm gpio: %d\n", ret);
++ pwm->used = false;
++ return ERR_PTR(ret);
++ }
++
++ jz_gpio_set_function(pwm->gpio, JZ_GPIO_FUNC_PWM);
++
++ jz4740_timer_start(id);
++
++ return pwm;
++}
++
++void pwm_free(struct pwm_device *pwm)
++{
++ pwm_disable(pwm);
++ jz4740_timer_set_ctrl(pwm->id, 0);
++
++ jz_gpio_set_function(pwm->gpio, JZ_GPIO_FUNC_NONE);
++ gpio_free(pwm->gpio);
++
++ jz4740_timer_stop(pwm->id);
++
++ pwm->used = false;
++}
++
++int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
++{
++ unsigned long long tmp;
++ unsigned long period, duty;
++ unsigned int prescaler = 0;
++ unsigned int id = pwm->id;
++ uint16_t ctrl;
++ bool is_enabled;
++
++ if (duty_ns < 0 || duty_ns > period_ns)
++ return -EINVAL;
++
++ tmp = (unsigned long long)clk_get_rate(jz4740_pwm_clk) * period_ns;
++ do_div(tmp, 1000000000);
++ period = tmp;
++
++ while (period > 0xffff && prescaler < 6) {
++ period >>= 2;
++ ++prescaler;
++ }
++
++ if (prescaler == 6)
++ return -EINVAL;
++
++ tmp = (unsigned long long)period * duty_ns;
++ do_div(tmp, period_ns);
++ duty = period - tmp;
++
++ if (duty >= period)
++ duty = period - 1;
++
++ is_enabled = jz4740_timer_is_enabled(id);
++ if (is_enabled)
++ pwm_disable(pwm);
++
++ jz4740_timer_set_count(id, 0);
++ jz4740_timer_set_duty(id, duty);
++ jz4740_timer_set_period(id, period);
++
++ ctrl = JZ_TIMER_CTRL_PRESCALER(prescaler) | JZ_TIMER_CTRL_SRC_EXT |
++ JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN;
++
++ jz4740_timer_set_ctrl(id, ctrl);
++
++ if (is_enabled)
++ pwm_enable(pwm);
++
++ return 0;
++}
++
++int pwm_enable(struct pwm_device *pwm)
++{
++ uint32_t ctrl = jz4740_timer_get_ctrl(pwm->id);
++
++ ctrl |= JZ_TIMER_CTRL_PWM_ENABLE;
++ jz4740_timer_set_ctrl(pwm->id, ctrl);
++ jz4740_timer_enable(pwm->id);
++
++ return 0;
++}
++
++void pwm_disable(struct pwm_device *pwm)
++{
++ uint32_t ctrl = jz4740_timer_get_ctrl(pwm->id);
++
++ ctrl &= ~JZ_TIMER_CTRL_PWM_ENABLE;
++ jz4740_timer_disable(pwm->id);
++ jz4740_timer_set_ctrl(pwm->id, ctrl);
++}
++
++static int __init jz4740_pwm_init(void)
++{
++ int ret = 0;
++
++ jz4740_pwm_clk = clk_get(NULL, "ext");
++
++ if (IS_ERR(jz4740_pwm_clk)) {
++ ret = PTR_ERR(jz4740_pwm_clk);
++ jz4740_pwm_clk = NULL;
++ }
++
++ return ret;
++}
++subsys_initcall(jz4740_pwm_init);
--- /dev/null
+From d9d3dc9a5a28b2bbb82fedca63aadae8ca540e94 Mon Sep 17 00:00:00 2001
+From: Lars-Peter Clausen <lars@metafoo.de>
+Date: Sat, 19 Jun 2010 04:08:16 +0000
+Subject: [PATCH] MIPS: JZ4740: Add serial support
+
+The JZ4740 UART interface is almost 16550 compatible.
+The UART module needs to be enabled by setting a bit in the FCR register
+and it has support for receive timeout interrupts. Instead of adding yet
+another machine specific quirk to the 8250 serial driver we provide a
+serial_out implementation which sets the required additional flags.
+
+Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
+Cc: linux-mips@linux-mips.org
+Cc: linux-kernel@vger.kernel.org
+Patchwork: https://patchwork.linux-mips.org/patch/1403/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/jz4740/serial.c | 33 +++++++++++++++++++++++++++++++++
+ arch/mips/jz4740/serial.h | 20 ++++++++++++++++++++
+ 2 files changed, 53 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/jz4740/serial.c
+ create mode 100644 arch/mips/jz4740/serial.h
+
+--- /dev/null
++++ b/arch/mips/jz4740/serial.c
+@@ -0,0 +1,33 @@
++/*
++ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
++ * JZ4740 serial support
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/io.h>
++#include <linux/serial_core.h>
++#include <linux/serial_reg.h>
++
++void jz4740_serial_out(struct uart_port *p, int offset, int value)
++{
++ switch (offset) {
++ case UART_FCR:
++ value |= 0x10; /* Enable uart module */
++ break;
++ case UART_IER:
++ value |= (value & 0x4) << 2;
++ break;
++ default:
++ break;
++ }
++ writeb(value, p->membase + (offset << p->regshift));
++}
+--- /dev/null
++++ b/arch/mips/jz4740/serial.h
+@@ -0,0 +1,20 @@
++/*
++ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
++ * JZ4740 serial support
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#ifndef __MIPS_JZ4740_SERIAL_H__
++
++void jz4740_serial_out(struct uart_port *p, int offset, int value);
++
++#endif
--- /dev/null
+From c615e4c64389ef138c6a13afa744e09134db2c82 Mon Sep 17 00:00:00 2001
+From: Lars-Peter Clausen <lars@metafoo.de>
+Date: Sat, 19 Jun 2010 04:08:17 +0000
+Subject: [PATCH] MIPS: JZ4740: Add prom support
+
+Add support for initializing arcs_cmdline on JZ4740 based machines and
+provides a prom_putchar implementation.
+
+Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
+Cc: linux-mips@linux-mips.org
+Cc: linux-kernel@vger.kernel.org
+Patchwork: https://patchwork.linux-mips.org/patch/1404/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/jz4740/prom.c | 68 +++++++++++++++++++++++++++++++++++++++++++++++
+ 1 files changed, 68 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/jz4740/prom.c
+
+--- /dev/null
++++ b/arch/mips/jz4740/prom.c
+@@ -0,0 +1,68 @@
++/*
++ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
++ * JZ4740 SoC prom code
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/string.h>
++
++#include <linux/serial_reg.h>
++
++#include <asm/bootinfo.h>
++#include <asm/mach-jz4740/base.h>
++
++void jz4740_init_cmdline(int argc, char *argv[])
++{
++ unsigned int count = COMMAND_LINE_SIZE - 1;
++ int i;
++ char *dst = &(arcs_cmdline[0]);
++ char *src;
++
++ for (i = 1; i < argc && count; ++i) {
++ src = argv[i];
++ while (*src && count) {
++ *dst++ = *src++;
++ --count;
++ }
++ *dst++ = ' ';
++ }
++ if (i > 1)
++ --dst;
++
++ *dst = 0;
++}
++
++void __init prom_init(void)
++{
++ jz4740_init_cmdline((int)fw_arg0, (char **)fw_arg1);
++ mips_machtype = MACH_INGENIC_JZ4740;
++}
++
++void __init prom_free_prom_memory(void)
++{
++}
++
++#define UART_REG(_reg) ((void __iomem *)CKSEG1ADDR(JZ4740_UART0_BASE_ADDR + (_reg << 2)))
++
++void prom_putchar(char c)
++{
++ uint8_t lsr;
++
++ do {
++ lsr = readb(UART_REG(UART_LSR));
++ } while ((lsr & UART_LSR_TEMT) == 0);
++
++ writeb(c, UART_REG(UART_TX));
++}
--- /dev/null
+From c7efc7b27ca91012c99618ad5efeec705671bd66 Mon Sep 17 00:00:00 2001
+From: Lars-Peter Clausen <lars@metafoo.de>
+Date: Sat, 17 Jul 2010 11:13:29 +0000
+Subject: [PATCH] MIPS: JZ4740: Add platform devices
+
+Add platform devices for all the JZ4740 platform drivers.
+
+Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
+Cc: linux-mips@linux-mips.org
+Cc: linux-kernel@vger.kernel.org
+Patchwork: https://patchwork.linux-mips.org/patch/1469/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/include/asm/mach-jz4740/platform.h | 36 ++++
+ arch/mips/jz4740/platform.c | 291 ++++++++++++++++++++++++++
+ 2 files changed, 327 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/include/asm/mach-jz4740/platform.h
+ create mode 100644 arch/mips/jz4740/platform.c
+
+--- /dev/null
++++ b/arch/mips/include/asm/mach-jz4740/platform.h
+@@ -0,0 +1,36 @@
++/*
++ * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
++ * JZ4740 platform device definitions
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++
++#ifndef __JZ4740_PLATFORM_H
++#define __JZ4740_PLATFORM_H
++
++#include <linux/platform_device.h>
++
++extern struct platform_device jz4740_usb_ohci_device;
++extern struct platform_device jz4740_udc_device;
++extern struct platform_device jz4740_mmc_device;
++extern struct platform_device jz4740_rtc_device;
++extern struct platform_device jz4740_i2c_device;
++extern struct platform_device jz4740_nand_device;
++extern struct platform_device jz4740_framebuffer_device;
++extern struct platform_device jz4740_i2s_device;
++extern struct platform_device jz4740_pcm_device;
++extern struct platform_device jz4740_codec_device;
++extern struct platform_device jz4740_adc_device;
++
++void jz4740_serial_device_register(void);
++
++#endif
+--- /dev/null
++++ b/arch/mips/jz4740/platform.c
+@@ -0,0 +1,291 @@
++/*
++ * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
++ * JZ4740 platform devices
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/device.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/platform_device.h>
++#include <linux/resource.h>
++
++#include <linux/dma-mapping.h>
++
++#include <asm/mach-jz4740/platform.h>
++#include <asm/mach-jz4740/base.h>
++#include <asm/mach-jz4740/irq.h>
++
++#include <linux/serial_core.h>
++#include <linux/serial_8250.h>
++
++#include "serial.h"
++#include "clock.h"
++
++/* OHCI controller */
++static struct resource jz4740_usb_ohci_resources[] = {
++ {
++ .start = JZ4740_UHC_BASE_ADDR,
++ .end = JZ4740_UHC_BASE_ADDR + 0x1000 - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .start = JZ4740_IRQ_UHC,
++ .end = JZ4740_IRQ_UHC,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++struct platform_device jz4740_usb_ohci_device = {
++ .name = "jz4740-ohci",
++ .id = -1,
++ .dev = {
++ .dma_mask = &jz4740_usb_ohci_device.dev.coherent_dma_mask,
++ .coherent_dma_mask = DMA_BIT_MASK(32),
++ },
++ .num_resources = ARRAY_SIZE(jz4740_usb_ohci_resources),
++ .resource = jz4740_usb_ohci_resources,
++};
++
++/* UDC (USB gadget controller) */
++static struct resource jz4740_usb_gdt_resources[] = {
++ {
++ .start = JZ4740_UDC_BASE_ADDR,
++ .end = JZ4740_UDC_BASE_ADDR + 0x1000 - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .start = JZ4740_IRQ_UDC,
++ .end = JZ4740_IRQ_UDC,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++struct platform_device jz4740_udc_device = {
++ .name = "jz-udc",
++ .id = -1,
++ .dev = {
++ .dma_mask = &jz4740_udc_device.dev.coherent_dma_mask,
++ .coherent_dma_mask = DMA_BIT_MASK(32),
++ },
++ .num_resources = ARRAY_SIZE(jz4740_usb_gdt_resources),
++ .resource = jz4740_usb_gdt_resources,
++};
++
++/* MMC/SD controller */
++static struct resource jz4740_mmc_resources[] = {
++ {
++ .start = JZ4740_MSC_BASE_ADDR,
++ .end = JZ4740_MSC_BASE_ADDR + 0x1000 - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .start = JZ4740_IRQ_MSC,
++ .end = JZ4740_IRQ_MSC,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++struct platform_device jz4740_mmc_device = {
++ .name = "jz4740-mmc",
++ .id = 0,
++ .dev = {
++ .dma_mask = &jz4740_mmc_device.dev.coherent_dma_mask,
++ .coherent_dma_mask = DMA_BIT_MASK(32),
++ },
++ .num_resources = ARRAY_SIZE(jz4740_mmc_resources),
++ .resource = jz4740_mmc_resources,
++};
++
++/* RTC controller */
++static struct resource jz4740_rtc_resources[] = {
++ {
++ .start = JZ4740_RTC_BASE_ADDR,
++ .end = JZ4740_RTC_BASE_ADDR + 0x38 - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .start = JZ4740_IRQ_RTC,
++ .end = JZ4740_IRQ_RTC,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++struct platform_device jz4740_rtc_device = {
++ .name = "jz4740-rtc",
++ .id = -1,
++ .num_resources = ARRAY_SIZE(jz4740_rtc_resources),
++ .resource = jz4740_rtc_resources,
++};
++
++/* I2C controller */
++static struct resource jz4740_i2c_resources[] = {
++ {
++ .start = JZ4740_I2C_BASE_ADDR,
++ .end = JZ4740_I2C_BASE_ADDR + 0x1000 - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .start = JZ4740_IRQ_I2C,
++ .end = JZ4740_IRQ_I2C,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++struct platform_device jz4740_i2c_device = {
++ .name = "jz4740-i2c",
++ .id = 0,
++ .num_resources = ARRAY_SIZE(jz4740_i2c_resources),
++ .resource = jz4740_i2c_resources,
++};
++
++/* NAND controller */
++static struct resource jz4740_nand_resources[] = {
++ {
++ .name = "mmio",
++ .start = JZ4740_EMC_BASE_ADDR,
++ .end = JZ4740_EMC_BASE_ADDR + 0x1000 - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "bank",
++ .start = 0x18000000,
++ .end = 0x180C0000 - 1,
++ .flags = IORESOURCE_MEM,
++ },
++};
++
++struct platform_device jz4740_nand_device = {
++ .name = "jz4740-nand",
++ .num_resources = ARRAY_SIZE(jz4740_nand_resources),
++ .resource = jz4740_nand_resources,
++};
++
++/* LCD controller */
++static struct resource jz4740_framebuffer_resources[] = {
++ {
++ .start = JZ4740_LCD_BASE_ADDR,
++ .end = JZ4740_LCD_BASE_ADDR + 0x1000 - 1,
++ .flags = IORESOURCE_MEM,
++ },
++};
++
++struct platform_device jz4740_framebuffer_device = {
++ .name = "jz4740-fb",
++ .id = -1,
++ .num_resources = ARRAY_SIZE(jz4740_framebuffer_resources),
++ .resource = jz4740_framebuffer_resources,
++ .dev = {
++ .dma_mask = &jz4740_framebuffer_device.dev.coherent_dma_mask,
++ .coherent_dma_mask = DMA_BIT_MASK(32),
++ },
++};
++
++/* I2S controller */
++static struct resource jz4740_i2s_resources[] = {
++ {
++ .start = JZ4740_AIC_BASE_ADDR,
++ .end = JZ4740_AIC_BASE_ADDR + 0x38 - 1,
++ .flags = IORESOURCE_MEM,
++ },
++};
++
++struct platform_device jz4740_i2s_device = {
++ .name = "jz4740-i2s",
++ .id = -1,
++ .num_resources = ARRAY_SIZE(jz4740_i2s_resources),
++ .resource = jz4740_i2s_resources,
++};
++
++/* PCM */
++struct platform_device jz4740_pcm_device = {
++ .name = "jz4740-pcm",
++ .id = -1,
++};
++
++/* Codec */
++static struct resource jz4740_codec_resources[] = {
++ {
++ .start = JZ4740_AIC_BASE_ADDR + 0x80,
++ .end = JZ4740_AIC_BASE_ADDR + 0x88 - 1,
++ .flags = IORESOURCE_MEM,
++ },
++};
++
++struct platform_device jz4740_codec_device = {
++ .name = "jz4740-codec",
++ .id = -1,
++ .num_resources = ARRAY_SIZE(jz4740_codec_resources),
++ .resource = jz4740_codec_resources,
++};
++
++/* ADC controller */
++static struct resource jz4740_adc_resources[] = {
++ {
++ .start = JZ4740_SADC_BASE_ADDR,
++ .end = JZ4740_SADC_BASE_ADDR + 0x30,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .start = JZ4740_IRQ_SADC,
++ .end = JZ4740_IRQ_SADC,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .start = JZ4740_IRQ_ADC_BASE,
++ .end = JZ4740_IRQ_ADC_BASE,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++struct platform_device jz4740_adc_device = {
++ .name = "jz4740-adc",
++ .id = -1,
++ .num_resources = ARRAY_SIZE(jz4740_adc_resources),
++ .resource = jz4740_adc_resources,
++};
++
++/* Serial */
++#define JZ4740_UART_DATA(_id) \
++ { \
++ .flags = UPF_SKIP_TEST | UPF_IOREMAP | UPF_FIXED_TYPE, \
++ .iotype = UPIO_MEM, \
++ .regshift = 2, \
++ .serial_out = jz4740_serial_out, \
++ .type = PORT_16550, \
++ .mapbase = JZ4740_UART ## _id ## _BASE_ADDR, \
++ .irq = JZ4740_IRQ_UART ## _id, \
++ }
++
++static struct plat_serial8250_port jz4740_uart_data[] = {
++ JZ4740_UART_DATA(0),
++ JZ4740_UART_DATA(1),
++ {},
++};
++
++static struct platform_device jz4740_uart_device = {
++ .name = "serial8250",
++ .id = 0,
++ .dev = {
++ .platform_data = jz4740_uart_data,
++ },
++};
++
++void jz4740_serial_device_register(void)
++{
++ struct plat_serial8250_port *p;
++
++ for (p = jz4740_uart_data; p->flags != 0; ++p)
++ p->uartclk = jz4740_clock_bdata.ext_rate;
++
++ platform_device_register(&jz4740_uart_device);
++}
--- /dev/null
+From a486767b412d7f19a02ef704cc60e4bc79404633 Mon Sep 17 00:00:00 2001
+From: Lars-Peter Clausen <lars@metafoo.de>
+Date: Wed, 2 Jun 2010 21:10:30 +0200
+Subject: [PATCH] MIPS: JZ4740: Add Kbuild files
+
+This patch adds the Kbuild files for the JZ4740 architecture and adds JZ4740
+support to the MIPS Kbuild files.
+
+Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
+---
+ arch/mips/Kconfig | 13 +++++++++++++
+ arch/mips/Makefile | 6 ++++++
+ arch/mips/jz4740/Kconfig | 8 ++++++++
+ arch/mips/jz4740/Makefile | 18 ++++++++++++++++++
+ 4 files changed, 45 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/jz4740/Kconfig
+ create mode 100644 arch/mips/jz4740/Makefile
+
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -162,6 +162,18 @@ config MACH_JAZZ
+ Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
+ Olivetti M700-10 workstations.
+
++config MACH_JZ4740
++ bool "Ingenic JZ4740 based machines"
++ select SYS_HAS_CPU_MIPS32_R1
++ select SYS_SUPPORTS_32BIT_KERNEL
++ select SYS_SUPPORTS_LITTLE_ENDIAN
++ select DMA_NONCOHERENT
++ select IRQ_CPU
++ select GENERIC_GPIO
++ select ARCH_REQUIRE_GPIOLIB
++ select SYS_HAS_EARLY_PRINTK
++ select HAVE_PWM
++
+ config LASAT
+ bool "LASAT Networks platforms"
+ select CEVT_R4K
+@@ -686,6 +698,7 @@ endchoice
+ source "arch/mips/alchemy/Kconfig"
+ source "arch/mips/bcm63xx/Kconfig"
+ source "arch/mips/jazz/Kconfig"
++source "arch/mips/jz4740/Kconfig"
+ source "arch/mips/lasat/Kconfig"
+ source "arch/mips/pmc-sierra/Kconfig"
+ source "arch/mips/powertv/Kconfig"
+--- a/arch/mips/Makefile
++++ b/arch/mips/Makefile
+@@ -661,6 +661,12 @@ else
+ load-$(CONFIG_CPU_CAVIUM_OCTEON) += 0xffffffff81100000
+ endif
+
++# Ingenic JZ4740
++#
++core-$(CONFIG_MACH_JZ4740) += arch/mips/jz4740/
++cflags-$(CONFIG_MACH_JZ4740) += -I$(srctree)/arch/mips/include/asm/mach-jz4740
++load-$(CONFIG_MACH_JZ4740) += 0xffffffff80010000
++
+ cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic
+ drivers-$(CONFIG_PCI) += arch/mips/pci/
+
+--- /dev/null
++++ b/arch/mips/jz4740/Kconfig
+@@ -0,0 +1,8 @@
++choice
++ prompt "Machine type"
++ depends on MACH_JZ4740
++
++endchoice
++
++config HAVE_PWM
++ bool
+--- /dev/null
++++ b/arch/mips/jz4740/Makefile
+@@ -0,0 +1,18 @@
++#
++# Makefile for the Ingenic JZ4740.
++#
++
++# Object file lists.
++
++obj-y += prom.o irq.o time.o reset.o setup.o dma.o \
++ gpio.o clock.o platform.o timer.o pwm.o serial.o
++
++obj-$(CONFIG_DEBUG_FS) += clock-debugfs.o
++
++# board specific support
++
++# PM support
++
++obj-$(CONFIG_PM) += pm.o
++
++EXTRA_CFLAGS += -Werror -Wall
--- /dev/null
+From e0548316a6aa5b9fa0df8126a4f0f749fdc5176a Mon Sep 17 00:00:00 2001
+From: Lars-Peter Clausen <lars@metafoo.de>
+Date: Sat, 17 Jul 2010 11:16:29 +0000
+Subject: [PATCH] MIPS: JZ4740: Add qi_lb60 board support
+
+Add support for the qi_lb60 (a.k.a QI Ben NanoNote) clamshell device.
+
+Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
+Cc: linux-mips@linux-mips.org
+Cc: linux-kernel@vger.kernel.org
+Patchwork: https://patchwork.linux-mips.org/patch/1472/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/jz4740/Kconfig | 4 +
+ arch/mips/jz4740/Makefile | 2 +
+ arch/mips/jz4740/board-qi_lb60.c | 495 ++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 501 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/jz4740/board-qi_lb60.c
+
+diff --git a/arch/mips/jz4740/Kconfig b/arch/mips/jz4740/Kconfig
+index 8a5e850..3e7141f 100644
+--- a/arch/mips/jz4740/Kconfig
++++ b/arch/mips/jz4740/Kconfig
+@@ -1,6 +1,10 @@
+ choice
+ prompt "Machine type"
+ depends on MACH_JZ4740
++ default JZ4740_QI_LB60
++
++config JZ4740_QI_LB60
++ bool "Qi Hardware Ben NanoNote"
+
+ endchoice
+
+diff --git a/arch/mips/jz4740/Makefile b/arch/mips/jz4740/Makefile
+index a803ccb..a604eae 100644
+--- a/arch/mips/jz4740/Makefile
++++ b/arch/mips/jz4740/Makefile
+@@ -11,6 +11,8 @@ obj-$(CONFIG_DEBUG_FS) += clock-debugfs.o
+
+ # board specific support
+
++obj-$(CONFIG_JZ4740_QI_LB60) += board-qi_lb60.o
++
+ # PM support
+
+ obj-$(CONFIG_PM) += pm.o
+diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c
+new file mode 100644
+index 0000000..d19732a
+--- /dev/null
++++ b/arch/mips/jz4740/board-qi_lb60.c
+@@ -0,0 +1,495 @@
++/*
++ * linux/arch/mips/jz4740/board-qi_lb60.c
++ *
++ * QI_LB60 board support
++ *
++ * Copyright (c) 2009 Qi Hardware inc.,
++ * Author: Xiangfu Liu <xiangfu@qi-hardware.com>
++ * Copyright 2010, Lars-Petrer Clausen <lars@metafoo.de>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 or later
++ * as published by the Free Software Foundation.
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/gpio.h>
++
++#include <linux/input.h>
++#include <linux/gpio_keys.h>
++#include <linux/input/matrix_keypad.h>
++#include <linux/spi/spi.h>
++#include <linux/spi/spi_gpio.h>
++#include <linux/power_supply.h>
++#include <linux/power/jz4740-battery.h>
++#include <linux/power/gpio-charger.h>
++
++#include <asm/mach-jz4740/jz4740_fb.h>
++#include <asm/mach-jz4740/jz4740_mmc.h>
++#include <asm/mach-jz4740/jz4740_nand.h>
++
++#include <linux/regulator/fixed.h>
++#include <linux/regulator/machine.h>
++
++#include <linux/leds_pwm.h>
++
++#include <asm/mach-jz4740/platform.h>
++
++#include "clock.h"
++
++static bool is_avt2;
++
++/* GPIOs */
++#define QI_LB60_GPIO_SD_CD JZ_GPIO_PORTD(0)
++#define QI_LB60_GPIO_SD_VCC_EN_N JZ_GPIO_PORTD(2)
++
++#define QI_LB60_GPIO_KEYOUT(x) (JZ_GPIO_PORTC(10) + (x))
++#define QI_LB60_GPIO_KEYIN(x) (JZ_GPIO_PORTD(18) + (x))
++#define QI_LB60_GPIO_KEYIN8 JZ_GPIO_PORTD(26)
++
++/* NAND */
++static struct nand_ecclayout qi_lb60_ecclayout_1gb = {
++/* .eccbytes = 36,
++ .eccpos = {
++ 6, 7, 8, 9, 10, 11, 12, 13,
++ 14, 15, 16, 17, 18, 19, 20, 21,
++ 22, 23, 24, 25, 26, 27, 28, 29,
++ 30, 31, 32, 33, 34, 35, 36, 37,
++ 38, 39, 40, 41
++ },*/
++ .oobfree = {
++ { .offset = 2, .length = 4 },
++ { .offset = 42, .length = 22 }
++ },
++};
++
++/* Early prototypes of the QI LB60 had only 1GB of NAND.
++ * In order to support these devices aswell the partition and ecc layout is
++ * initalized depending on the NAND size */
++static struct mtd_partition qi_lb60_partitions_1gb[] = {
++ {
++ .name = "NAND BOOT partition",
++ .offset = 0 * 0x100000,
++ .size = 4 * 0x100000,
++ },
++ {
++ .name = "NAND KERNEL partition",
++ .offset = 4 * 0x100000,
++ .size = 4 * 0x100000,
++ },
++ {
++ .name = "NAND ROOTFS partition",
++ .offset = 8 * 0x100000,
++ .size = (504 + 512) * 0x100000,
++ },
++};
++
++static struct nand_ecclayout qi_lb60_ecclayout_2gb = {
++/* .eccbytes = 72,
++ .eccpos = {
++ 12, 13, 14, 15, 16, 17, 18, 19,
++ 20, 21, 22, 23, 24, 25, 26, 27,
++ 28, 29, 30, 31, 32, 33, 34, 35,
++ 36, 37, 38, 39, 40, 41, 42, 43,
++ 44, 45, 46, 47, 48, 49, 50, 51,
++ 52, 53, 54, 55, 56, 57, 58, 59,
++ 60, 61, 62, 63, 64, 65, 66, 67,
++ 68, 69, 70, 71, 72, 73, 74, 75,
++ 76, 77, 78, 79, 80, 81, 82, 83
++ },*/
++ .oobfree = {
++ { .offset = 2, .length = 10 },
++ { .offset = 84, .length = 44 },
++ },
++};
++
++static struct mtd_partition qi_lb60_partitions_2gb[] = {
++ {
++ .name = "NAND BOOT partition",
++ .offset = 0 * 0x100000,
++ .size = 4 * 0x100000,
++ },
++ {
++ .name = "NAND KERNEL partition",
++ .offset = 4 * 0x100000,
++ .size = 4 * 0x100000,
++ },
++ {
++ .name = "NAND ROOTFS partition",
++ .offset = 8 * 0x100000,
++ .size = (504 + 512 + 1024) * 0x100000,
++ },
++};
++
++static void qi_lb60_nand_ident(struct platform_device *pdev,
++ struct nand_chip *chip, struct mtd_partition **partitions,
++ int *num_partitions)
++{
++ if (chip->page_shift == 12) {
++ chip->ecc.layout = &qi_lb60_ecclayout_2gb;
++ *partitions = qi_lb60_partitions_2gb;
++ *num_partitions = ARRAY_SIZE(qi_lb60_partitions_2gb);
++ } else {
++ chip->ecc.layout = &qi_lb60_ecclayout_1gb;
++ *partitions = qi_lb60_partitions_1gb;
++ *num_partitions = ARRAY_SIZE(qi_lb60_partitions_1gb);
++ }
++}
++
++static struct jz_nand_platform_data qi_lb60_nand_pdata = {
++ .ident_callback = qi_lb60_nand_ident,
++ .busy_gpio = 94,
++};
++
++/* Keyboard*/
++
++#define KEY_QI_QI KEY_F13
++#define KEY_QI_UPRED KEY_RIGHTALT
++#define KEY_QI_VOLUP KEY_VOLUMEUP
++#define KEY_QI_VOLDOWN KEY_VOLUMEDOWN
++#define KEY_QI_FN KEY_LEFTCTRL
++
++static const uint32_t qi_lb60_keymap[] = {
++ KEY(0, 0, KEY_F1), /* S2 */
++ KEY(0, 1, KEY_F2), /* S3 */
++ KEY(0, 2, KEY_F3), /* S4 */
++ KEY(0, 3, KEY_F4), /* S5 */
++ KEY(0, 4, KEY_F5), /* S6 */
++ KEY(0, 5, KEY_F6), /* S7 */
++ KEY(0, 6, KEY_F7), /* S8 */
++
++ KEY(1, 0, KEY_Q), /* S10 */
++ KEY(1, 1, KEY_W), /* S11 */
++ KEY(1, 2, KEY_E), /* S12 */
++ KEY(1, 3, KEY_R), /* S13 */
++ KEY(1, 4, KEY_T), /* S14 */
++ KEY(1, 5, KEY_Y), /* S15 */
++ KEY(1, 6, KEY_U), /* S16 */
++ KEY(1, 7, KEY_I), /* S17 */
++ KEY(2, 0, KEY_A), /* S18 */
++ KEY(2, 1, KEY_S), /* S19 */
++ KEY(2, 2, KEY_D), /* S20 */
++ KEY(2, 3, KEY_F), /* S21 */
++ KEY(2, 4, KEY_G), /* S22 */
++ KEY(2, 5, KEY_H), /* S23 */
++ KEY(2, 6, KEY_J), /* S24 */
++ KEY(2, 7, KEY_K), /* S25 */
++ KEY(3, 0, KEY_ESC), /* S26 */
++ KEY(3, 1, KEY_Z), /* S27 */
++ KEY(3, 2, KEY_X), /* S28 */
++ KEY(3, 3, KEY_C), /* S29 */
++ KEY(3, 4, KEY_V), /* S30 */
++ KEY(3, 5, KEY_B), /* S31 */
++ KEY(3, 6, KEY_N), /* S32 */
++ KEY(3, 7, KEY_M), /* S33 */
++ KEY(4, 0, KEY_TAB), /* S34 */
++ KEY(4, 1, KEY_CAPSLOCK), /* S35 */
++ KEY(4, 2, KEY_BACKSLASH), /* S36 */
++ KEY(4, 3, KEY_APOSTROPHE), /* S37 */
++ KEY(4, 4, KEY_COMMA), /* S38 */
++ KEY(4, 5, KEY_DOT), /* S39 */
++ KEY(4, 6, KEY_SLASH), /* S40 */
++ KEY(4, 7, KEY_UP), /* S41 */
++ KEY(5, 0, KEY_O), /* S42 */
++ KEY(5, 1, KEY_L), /* S43 */
++ KEY(5, 2, KEY_EQUAL), /* S44 */
++ KEY(5, 3, KEY_QI_UPRED), /* S45 */
++ KEY(5, 4, KEY_SPACE), /* S46 */
++ KEY(5, 5, KEY_QI_QI), /* S47 */
++ KEY(5, 6, KEY_RIGHTCTRL), /* S48 */
++ KEY(5, 7, KEY_LEFT), /* S49 */
++ KEY(6, 0, KEY_F8), /* S50 */
++ KEY(6, 1, KEY_P), /* S51 */
++ KEY(6, 2, KEY_BACKSPACE),/* S52 */
++ KEY(6, 3, KEY_ENTER), /* S53 */
++ KEY(6, 4, KEY_QI_VOLUP), /* S54 */
++ KEY(6, 5, KEY_QI_VOLDOWN), /* S55 */
++ KEY(6, 6, KEY_DOWN), /* S56 */
++ KEY(6, 7, KEY_RIGHT), /* S57 */
++
++ KEY(7, 0, KEY_LEFTSHIFT), /* S58 */
++ KEY(7, 1, KEY_LEFTALT), /* S59 */
++ KEY(7, 2, KEY_QI_FN), /* S60 */
++};
++
++static const struct matrix_keymap_data qi_lb60_keymap_data = {
++ .keymap = qi_lb60_keymap,
++ .keymap_size = ARRAY_SIZE(qi_lb60_keymap),
++};
++
++static const unsigned int qi_lb60_keypad_cols[] = {
++ QI_LB60_GPIO_KEYOUT(0),
++ QI_LB60_GPIO_KEYOUT(1),
++ QI_LB60_GPIO_KEYOUT(2),
++ QI_LB60_GPIO_KEYOUT(3),
++ QI_LB60_GPIO_KEYOUT(4),
++ QI_LB60_GPIO_KEYOUT(5),
++ QI_LB60_GPIO_KEYOUT(6),
++ QI_LB60_GPIO_KEYOUT(7),
++};
++
++static const unsigned int qi_lb60_keypad_rows[] = {
++ QI_LB60_GPIO_KEYIN(0),
++ QI_LB60_GPIO_KEYIN(1),
++ QI_LB60_GPIO_KEYIN(2),
++ QI_LB60_GPIO_KEYIN(3),
++ QI_LB60_GPIO_KEYIN(4),
++ QI_LB60_GPIO_KEYIN(5),
++ QI_LB60_GPIO_KEYIN(7),
++ QI_LB60_GPIO_KEYIN8,
++};
++
++static struct matrix_keypad_platform_data qi_lb60_pdata = {
++ .keymap_data = &qi_lb60_keymap_data,
++ .col_gpios = qi_lb60_keypad_cols,
++ .row_gpios = qi_lb60_keypad_rows,
++ .num_col_gpios = ARRAY_SIZE(qi_lb60_keypad_cols),
++ .num_row_gpios = ARRAY_SIZE(qi_lb60_keypad_rows),
++ .col_scan_delay_us = 10,
++ .debounce_ms = 10,
++ .wakeup = 1,
++ .active_low = 1,
++};
++
++static struct platform_device qi_lb60_keypad = {
++ .name = "matrix-keypad",
++ .id = -1,
++ .dev = {
++ .platform_data = &qi_lb60_pdata,
++ },
++};
++
++/* Display */
++static struct fb_videomode qi_lb60_video_modes[] = {
++ {
++ .name = "320x240",
++ .xres = 320,
++ .yres = 240,
++ .refresh = 30,
++ .left_margin = 140,
++ .right_margin = 273,
++ .upper_margin = 20,
++ .lower_margin = 2,
++ .hsync_len = 1,
++ .vsync_len = 1,
++ .sync = 0,
++ .vmode = FB_VMODE_NONINTERLACED,
++ },
++};
++
++static struct jz4740_fb_platform_data qi_lb60_fb_pdata = {
++ .width = 60,
++ .height = 45,
++ .num_modes = ARRAY_SIZE(qi_lb60_video_modes),
++ .modes = qi_lb60_video_modes,
++ .bpp = 24,
++ .lcd_type = JZ_LCD_TYPE_8BIT_SERIAL,
++ .pixclk_falling_edge = 1,
++};
++
++struct spi_gpio_platform_data spigpio_platform_data = {
++ .sck = JZ_GPIO_PORTC(23),
++ .mosi = JZ_GPIO_PORTC(22),
++ .miso = -1,
++ .num_chipselect = 1,
++};
++
++static struct platform_device spigpio_device = {
++ .name = "spi_gpio",
++ .id = 1,
++ .dev = {
++ .platform_data = &spigpio_platform_data,
++ },
++};
++
++static struct spi_board_info qi_lb60_spi_board_info[] = {
++ {
++ .modalias = "ili8960",
++ .controller_data = (void *)JZ_GPIO_PORTC(21),
++ .chip_select = 0,
++ .bus_num = 1,
++ .max_speed_hz = 30 * 1000,
++ .mode = SPI_3WIRE,
++ },
++};
++
++/* Battery */
++static struct jz_battery_platform_data qi_lb60_battery_pdata = {
++ .gpio_charge = JZ_GPIO_PORTC(27),
++ .gpio_charge_active_low = 1,
++ .info = {
++ .name = "battery",
++ .technology = POWER_SUPPLY_TECHNOLOGY_LIPO,
++ .voltage_max_design = 4200000,
++ .voltage_min_design = 3600000,
++ },
++};
++
++/* GPIO Key: power */
++static struct gpio_keys_button qi_lb60_gpio_keys_buttons[] = {
++ [0] = {
++ .code = KEY_POWER,
++ .gpio = JZ_GPIO_PORTD(29),
++ .active_low = 1,
++ .desc = "Power",
++ .wakeup = 1,
++ },
++};
++
++static struct gpio_keys_platform_data qi_lb60_gpio_keys_data = {
++ .nbuttons = ARRAY_SIZE(qi_lb60_gpio_keys_buttons),
++ .buttons = qi_lb60_gpio_keys_buttons,
++};
++
++static struct platform_device qi_lb60_gpio_keys = {
++ .name = "gpio-keys",
++ .id = -1,
++ .dev = {
++ .platform_data = &qi_lb60_gpio_keys_data,
++ }
++};
++
++static struct jz4740_mmc_platform_data qi_lb60_mmc_pdata = {
++ .gpio_card_detect = QI_LB60_GPIO_SD_CD,
++ .gpio_read_only = -1,
++ .gpio_power = QI_LB60_GPIO_SD_VCC_EN_N,
++ .power_active_low = 1,
++};
++
++/* OHCI */
++static struct regulator_consumer_supply avt2_usb_regulator_consumer =
++ REGULATOR_SUPPLY("vbus", "jz4740-ohci");
++
++static struct regulator_init_data avt2_usb_regulator_init_data = {
++ .num_consumer_supplies = 1,
++ .consumer_supplies = &avt2_usb_regulator_consumer,
++ .constraints = {
++ .name = "USB power",
++ .min_uV = 5000000,
++ .max_uV = 5000000,
++ .valid_modes_mask = REGULATOR_MODE_NORMAL,
++ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
++ },
++};
++
++static struct fixed_voltage_config avt2_usb_regulator_data = {
++ .supply_name = "USB power",
++ .microvolts = 5000000,
++ .gpio = JZ_GPIO_PORTB(17),
++ .init_data = &avt2_usb_regulator_init_data,
++};
++
++static struct platform_device avt2_usb_regulator_device = {
++ .name = "reg-fixed-voltage",
++ .id = -1,
++ .dev = {
++ .platform_data = &avt2_usb_regulator_data,
++ }
++};
++
++/* beeper */
++static struct platform_device qi_lb60_pwm_beeper = {
++ .name = "pwm-beeper",
++ .id = -1,
++ .dev = {
++ .platform_data = (void *)4,
++ },
++};
++
++/* charger */
++static char *qi_lb60_batteries[] = {
++ "battery",
++};
++
++static struct gpio_charger_platform_data qi_lb60_charger_pdata = {
++ .name = "usb",
++ .type = POWER_SUPPLY_TYPE_USB,
++ .gpio = JZ_GPIO_PORTD(28),
++ .gpio_active_low = 1,
++ .batteries = qi_lb60_batteries,
++ .num_batteries = ARRAY_SIZE(qi_lb60_batteries),
++};
++
++static struct platform_device qi_lb60_charger_device = {
++ .name = "gpio-charger",
++ .dev = {
++ .platform_data = &qi_lb60_charger_pdata,
++ },
++};
++
++
++static struct platform_device *jz_platform_devices[] __initdata = {
++ &jz4740_udc_device,
++ &jz4740_mmc_device,
++ &jz4740_nand_device,
++ &qi_lb60_keypad,
++ &spigpio_device,
++ &jz4740_framebuffer_device,
++ &jz4740_pcm_device,
++ &jz4740_i2s_device,
++ &jz4740_codec_device,
++ &jz4740_rtc_device,
++ &jz4740_adc_device,
++ &qi_lb60_gpio_keys,
++ &qi_lb60_pwm_beeper,
++ &qi_lb60_charger_device,
++};
++
++static void __init board_gpio_setup(void)
++{
++ /* We only need to enable/disable pullup here for pins used in generic
++ * drivers. Everything else is done by the drivers themselfs. */
++ jz_gpio_disable_pullup(QI_LB60_GPIO_SD_VCC_EN_N);
++ jz_gpio_disable_pullup(QI_LB60_GPIO_SD_CD);
++}
++
++static int __init qi_lb60_init_platform_devices(void)
++{
++ jz4740_framebuffer_device.dev.platform_data = &qi_lb60_fb_pdata;
++ jz4740_nand_device.dev.platform_data = &qi_lb60_nand_pdata;
++ jz4740_adc_device.dev.platform_data = &qi_lb60_battery_pdata;
++ jz4740_mmc_device.dev.platform_data = &qi_lb60_mmc_pdata;
++
++ jz4740_serial_device_register();
++
++ spi_register_board_info(qi_lb60_spi_board_info,
++ ARRAY_SIZE(qi_lb60_spi_board_info));
++
++ if (is_avt2) {
++ platform_device_register(&avt2_usb_regulator_device);
++ platform_device_register(&jz4740_usb_ohci_device);
++ }
++
++ return platform_add_devices(jz_platform_devices,
++ ARRAY_SIZE(jz_platform_devices));
++
++}
++
++struct jz4740_clock_board_data jz4740_clock_bdata = {
++ .ext_rate = 12000000,
++ .rtc_rate = 32768,
++};
++
++static __init int board_avt2(char *str)
++{
++ qi_lb60_mmc_pdata.card_detect_active_low = 1;
++ is_avt2 = true;
++
++ return 1;
++}
++__setup("avt2", board_avt2);
++
++static int __init qi_lb60_board_setup(void)
++{
++ printk(KERN_INFO "Qi Hardware JZ4740 QI %s setup\n",
++ is_avt2 ? "AVT2" : "LB60");
++
++ board_gpio_setup();
++
++ if (qi_lb60_init_platform_devices())
++ panic("Failed to initalize platform devices\n");
++
++ return 0;
++}
++arch_initcall(qi_lb60_board_setup);
+--
+1.5.6.5
+
--- /dev/null
+From c260fa2e5fe9699824190555e075d6c1157d5f36 Mon Sep 17 00:00:00 2001
+From: Lars-Peter Clausen <lars@metafoo.de>
+Date: Sat, 24 Apr 2010 17:25:01 +0200
+Subject: [PATCH] Add n516 board support
+
+---
+ arch/mips/include/asm/mach-jz4740/board-n516.h | 39 +++
+ arch/mips/jz4740/Kconfig | 4 +
+ arch/mips/jz4740/Makefile | 1 +
+ arch/mips/jz4740/board-n516-display.c | 394 ++++++++++++++++++++++++
+ arch/mips/jz4740/board-n516.c | 203 ++++++++++++
+ 5 files changed, 641 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/include/asm/mach-jz4740/board-n516.h
+ create mode 100644 arch/mips/jz4740/board-n516-display.c
+ create mode 100644 arch/mips/jz4740/board-n516.c
+
+--- /dev/null
++++ b/arch/mips/include/asm/mach-jz4740/board-n516.h
+@@ -0,0 +1,39 @@
++/*
++ * linux/include/asm-mips/mach-jz4740/board-n516.h
++ *
++ * JZ4730-based N516 board definition.
++ *
++ * Copyright (C) 2009, Yauhen Kharuzhy <jekhor@gmail.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef __ASM_JZ4740_N516_H__
++#define __ASM_JZ4740_N516_H__
++
++#include <asm/mach-jz4740/gpio.h>
++
++/*
++ * GPIO
++ */
++#define GPIO_SD_VCC_EN_N JZ_GPIO_PORTD(17)
++#define GPIO_SD_CD_N JZ_GPIO_PORTD(7)
++#define GPIO_SD_WP JZ_GPIO_PORTD(15)
++#define GPIO_USB_DETECT JZ_GPIO_PORTD(19)
++#define GPIO_CHARG_STAT_N JZ_GPIO_PORTD(16)
++#define GPIO_LED_ENABLE JZ_GPIO_PORTD(28)
++#define GPIO_LPC_INT JZ_GPIO_PORTD(14)
++#define GPIO_HPHONE_DETECT JZ_GPIO_PORTD(20)
++#define GPIO_SPEAKER_ENABLE JZ_GPIO_PORTD(21)
++
++/* Display */
++#define GPIO_DISPLAY_RST_L JZ_GPIO_PORTB(18)
++#define GPIO_DISPLAY_RDY JZ_GPIO_PORTB(17)
++#define GPIO_DISPLAY_STBY JZ_GPIO_PORTC(22)
++#define GPIO_DISPLAY_ERR JZ_GPIO_PORTC(23)
++#define GPIO_DISPLAY_OFF_N JZ_GPIO_PORTD(1)
++
++#endif /* __ASM_JZ4740_N516_H__ */
+--- a/arch/mips/jz4740/Kconfig
++++ b/arch/mips/jz4740/Kconfig
+@@ -6,6 +6,10 @@ choice
+ config JZ4740_QI_LB60
+ bool "Qi Hardware Ben NanoNote"
+
++config JZ4740_N516
++ bool "Hanvon n516 eBook reader"
++ select SOC_JZ4740
++
+ endchoice
+
+ config HAVE_PWM
+--- a/arch/mips/jz4740/Makefile
++++ b/arch/mips/jz4740/Makefile
+@@ -12,6 +12,7 @@ obj-$(CONFIG_DEBUG_FS) += clock-debugfs.
+ # board specific support
+
+ obj-$(CONFIG_JZ4740_QI_LB60) += board-qi_lb60.o
++obj-$(CONFIG_JZ4740_N516) += board-n516.o board-n516-display.o
+
+ # PM support
+
+--- /dev/null
++++ b/arch/mips/jz4740/board-n516-display.c
+@@ -0,0 +1,394 @@
++/*
++ * board-n516-display.c -- Platform device for N516 display
++ *
++ * Copyright (C) 2009, Yauhen Kharuzhy <jekhor@gmail.com>
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file COPYING in the main directory of this archive for
++ * more details.
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/errno.h>
++#include <linux/string.h>
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++#include <linux/fb.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/irq.h>
++#include <linux/gpio.h>
++
++#include <asm/mach-jz4740/jz4740_fb.h>
++
++#include <asm/mach-jz4740/platform.h>
++#include <asm/mach-jz4740/board-n516.h>
++
++#include <video/metronomefb.h>
++#include <linux/console.h>
++
++static struct fb_videomode n516_fb_modes[] = {
++ [0] = {
++ .name = "Metronome 800x600",
++ .refresh = 50,
++ .xres = 400,
++ .yres = 624,
++ .hsync_len = 31,
++ .vsync_len = 23,
++ .right_margin = 31,
++ .left_margin = 5,
++ .upper_margin = 1,
++ .lower_margin = 2,
++ .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ },
++};
++
++static struct jz4740_fb_platform_data n516_fb_pdata = {
++ .num_modes = ARRAY_SIZE(n516_fb_modes),
++ .modes = n516_fb_modes,
++ .bpp = 16,
++ .lcd_type = JZ_LCD_TYPE_GENERIC_16_BIT,
++};
++
++struct n516_board_info {
++ uint8_t *metromem;
++ size_t wfm_size;
++ struct fb_info *host_fbinfo; /* the host LCD controller's fbi */
++ unsigned int fw;
++ unsigned int fh;
++};
++
++static struct platform_device *n516_device;
++static struct n516_board_info n516_board_info;
++
++static int metronome_gpios[] = {
++ GPIO_DISPLAY_STBY,
++ GPIO_DISPLAY_RST_L,
++ GPIO_DISPLAY_RDY,
++ GPIO_DISPLAY_ERR,
++/* GPIO_DISPLAY_OFF_N,*/
++};
++
++static const char *metronome_gpio_names[] = {
++ "Metronome STDBY",
++ "Metronome RST",
++ "Metronome RDY",
++ "Metronome ERR",
++/* "Metronone OFF",*/
++};
++
++static int n516_enable_hostfb(bool enable)
++{
++ int ret;
++ int blank = enable ? FB_BLANK_UNBLANK : FB_BLANK_POWERDOWN;
++
++ acquire_console_sem();
++ ret = fb_blank(n516_board_info.host_fbinfo, blank);
++ release_console_sem();
++
++ return ret;
++}
++
++static int n516_init_metronome_gpios(struct metronomefb_par *par)
++{
++ int i;
++ int ret;
++
++ for (i = 0; i < ARRAY_SIZE(metronome_gpios); ++i) {
++ ret = gpio_request(metronome_gpios[i], metronome_gpio_names[i]);
++ if (ret)
++ goto err;
++ }
++
++ gpio_direction_output(GPIO_DISPLAY_OFF_N, 0);
++ gpio_direction_output(GPIO_DISPLAY_RST_L, 0);
++ gpio_direction_output(GPIO_DISPLAY_STBY, 0);
++ gpio_direction_input(GPIO_DISPLAY_RDY);
++ gpio_direction_input(GPIO_DISPLAY_ERR);
++
++ return 0;
++err:
++ for (--i; i >= 0; --i)
++ gpio_free(metronome_gpios[i]);
++
++ return ret;
++}
++
++static int n516_share_video_mem(struct fb_info *info)
++{
++ int ret;
++
++ dev_dbg(&n516_device->dev, "ENTER %s\n", __func__);
++ dev_dbg(&n516_device->dev, "%s, info->var.xres = %u, info->var.yres = %u\n", __func__, info->var.xres, info->var.yres);
++ /* rough check if this is our desired fb and not something else */
++ if ((info->var.xres != n516_fb_pdata.modes[0].xres)
++ || (info->var.yres != n516_fb_pdata.modes[0].yres))
++ return 0;
++
++ /* we've now been notified that we have our new fb */
++ n516_board_info.metromem = info->screen_base;
++ n516_board_info.host_fbinfo = info;
++
++ n516_enable_hostfb(false);
++ /* try to refcount host drv since we are the consumer after this */
++ if (!try_module_get(info->fbops->owner))
++ return -ENODEV;
++
++ /* this _add binds metronomefb to n516. metronomefb refcounts n516 */
++ ret = platform_device_add(n516_device);
++
++ if (ret) {
++ platform_device_put(n516_device);
++ return ret;
++ }
++
++ /* request our platform independent driver */
++ request_module("metronomefb");
++
++ return 0;
++}
++
++static int n516_unshare_video_mem(struct fb_info *info)
++{
++ dev_dbg(&n516_device->dev, "ENTER %s\n", __func__);
++
++ if (info != n516_board_info.host_fbinfo)
++ return 0;
++
++ module_put(n516_board_info.host_fbinfo->fbops->owner);
++ return 0;
++}
++
++static int n516_fb_notifier_callback(struct notifier_block *self,
++ unsigned long event, void *data)
++{
++ struct fb_event *evdata = data;
++ struct fb_info *info = evdata->info;
++
++ dev_dbg(&n516_device->dev, "ENTER %s\n", __func__);
++
++ if (event == FB_EVENT_FB_REGISTERED)
++ return n516_share_video_mem(info);
++ else if (event == FB_EVENT_FB_UNREGISTERED)
++ return n516_unshare_video_mem(info);
++
++ return 0;
++}
++
++static struct notifier_block n516_fb_notif = {
++ .notifier_call = n516_fb_notifier_callback,
++};
++
++/* this gets called as part of our init. these steps must be done now so
++ * that we can use set_pxa_fb_info */
++static void __init n516_presetup_fb(void)
++{
++ int padding_size;
++ int totalsize;
++
++ /* the frame buffer is divided as follows:
++ command | CRC | padding
++ 16kb waveform data | CRC | padding
++ image data | CRC
++ */
++
++ n516_board_info.fw = 800;
++ n516_board_info.fh = 624;
++
++ /* waveform must be 16k + 2 for checksum */
++ n516_board_info.wfm_size = roundup(16*1024 + 2, n516_board_info.fw);
++
++ padding_size = PAGE_SIZE + (4 * n516_board_info.fw);
++
++ /* total is 1 cmd , 1 wfm, padding and image */
++ totalsize = n516_board_info.fw + n516_board_info.wfm_size;
++ totalsize += padding_size + (n516_board_info.fw*n516_board_info.fh);
++
++ /* save this off because we're manipulating fw after this and
++ * we'll need it when we're ready to setup the framebuffer */
++
++ /* the reason we do this adjustment is because we want to acquire
++ * more framebuffer memory without imposing custom awareness on the
++ * underlying driver */
++ n516_fb_pdata.modes[0].yres = DIV_ROUND_UP(totalsize, n516_board_info.fw);
++
++ jz4740_framebuffer_device.dev.platform_data = &n516_fb_pdata;
++ platform_device_register(&jz4740_framebuffer_device);
++}
++
++/* this gets called by metronomefb as part of its init, in our case, we
++ * have already completed initial framebuffer init in presetup_fb so we
++ * can just setup the fb access pointers */
++static int n516_setup_fb(struct metronomefb_par *par)
++{
++ /* metromem was set up by the notifier in share_video_mem so now
++ * we can use its value to calculate the other entries */
++ par->metromem_cmd = (struct metromem_cmd *) n516_board_info.metromem;
++ par->metromem_wfm = n516_board_info.metromem + n516_board_info.fw;
++ par->metromem_img = par->metromem_wfm + n516_board_info.wfm_size;
++ par->metromem_img_csum = (u16 *) (par->metromem_img + (n516_board_info.fw * n516_board_info.fh));
++ par->metromem_dma = n516_board_info.host_fbinfo->fix.smem_start;
++
++ return 0;
++}
++
++static int n516_get_panel_type(void)
++{
++ return 5;
++}
++
++static irqreturn_t n516_handle_irq(int irq, void *dev_id)
++{
++ struct metronomefb_par *par = dev_id;
++
++ dev_dbg(&par->pdev->dev, "Metronome IRQ! RDY=%d\n", gpio_get_value(GPIO_DISPLAY_RDY));
++ wake_up_all(&par->waitq);
++
++ return IRQ_HANDLED;
++}
++
++static void n516_power_ctl(struct metronomefb_par *par, int cmd)
++{
++ switch (cmd) {
++ case METRONOME_POWER_OFF:
++ gpio_set_value(GPIO_DISPLAY_OFF_N, 1);
++ n516_enable_hostfb(false);
++ break;
++ case METRONOME_POWER_ON:
++ gpio_set_value(GPIO_DISPLAY_OFF_N, 0);
++ n516_enable_hostfb(true);
++ break;
++ }
++}
++
++static int n516_get_rdy(struct metronomefb_par *par)
++{
++ return gpio_get_value(GPIO_DISPLAY_RDY);
++}
++
++static int n516_get_err(struct metronomefb_par *par)
++{
++ return gpio_get_value(GPIO_DISPLAY_ERR);
++}
++
++static int n516_setup_irq(struct fb_info *info)
++{
++ int ret;
++
++ dev_dbg(&n516_device->dev, "ENTER %s\n", __func__);
++
++ ret = request_irq(gpio_to_irq(GPIO_DISPLAY_RDY), n516_handle_irq,
++ IRQF_TRIGGER_RISING,
++ "n516", info->par);
++ if (ret)
++ dev_err(&n516_device->dev, "request_irq failed: %d\n", ret);
++
++ return ret;
++}
++
++static void n516_set_rst(struct metronomefb_par *par, int state)
++{
++ dev_dbg(&n516_device->dev, "ENTER %s, RDY=%d\n", __func__, gpio_get_value(GPIO_DISPLAY_RDY));
++ if (state)
++ gpio_set_value(GPIO_DISPLAY_RST_L, 1);
++ else
++ gpio_set_value(GPIO_DISPLAY_RST_L, 0);
++}
++
++static void n516_set_stdby(struct metronomefb_par *par, int state)
++{
++ dev_dbg(&n516_device->dev, "ENTER %s, RDY=%d\n", __func__, gpio_get_value(GPIO_DISPLAY_RDY));
++ if (state)
++ gpio_set_value(GPIO_DISPLAY_STBY, 1);
++ else
++ gpio_set_value(GPIO_DISPLAY_STBY, 0);
++}
++
++static int n516_wait_event(struct metronomefb_par *par)
++{
++ unsigned long timeout = jiffies + HZ / 20;
++
++ dev_dbg(&n516_device->dev, "ENTER1 %s, RDY=%d\n",
++ __func__, gpio_get_value(GPIO_DISPLAY_RDY));
++ while (n516_get_rdy(par) && time_before(jiffies, timeout))
++ schedule();
++
++ dev_dbg(&n516_device->dev, "ENTER2 %s, RDY=%d\n",
++ __func__, gpio_get_value(GPIO_DISPLAY_RDY));
++ return wait_event_timeout(par->waitq,
++ n516_get_rdy(par), HZ * 2) ? 0 : -EIO;
++}
++
++static int n516_wait_event_intr(struct metronomefb_par *par)
++{
++ unsigned long timeout = jiffies + HZ/20;
++
++ dev_dbg(&n516_device->dev, "ENTER1 %s, RDY=%d\n",
++ __func__, gpio_get_value(GPIO_DISPLAY_RDY));
++ while (n516_get_rdy(par) && time_before(jiffies, timeout))
++ schedule();
++
++ dev_dbg(&n516_device->dev, "ENTER2 %s, RDY=%d\n",
++ __func__, gpio_get_value(GPIO_DISPLAY_RDY));
++ return wait_event_interruptible_timeout(par->waitq,
++ n516_get_rdy(par), HZ * 2) ? 0 : -EIO;
++}
++
++static void n516_cleanup(struct metronomefb_par *par)
++{
++ int i;
++
++ free_irq(gpio_to_irq(GPIO_DISPLAY_RDY), par);
++ for (i = 0; i < ARRAY_SIZE(metronome_gpios); ++i)
++ gpio_free(metronome_gpios[i]);
++}
++
++static struct metronome_board n516_board __initdata = {
++ .owner = THIS_MODULE,
++ .power_ctl = n516_power_ctl,
++ .setup_irq = n516_setup_irq,
++ .setup_io = n516_init_metronome_gpios,
++ .setup_fb = n516_setup_fb,
++ .set_rst = n516_set_rst,
++ .get_err = n516_get_err,
++ .get_rdy = n516_get_rdy,
++ .set_stdby = n516_set_stdby,
++ .met_wait_event = n516_wait_event,
++ .met_wait_event_intr = n516_wait_event_intr,
++ .get_panel_type = n516_get_panel_type,
++ .cleanup = n516_cleanup,
++};
++
++static int __init n516_init(void)
++{
++ int ret;
++
++ /* Keep the metronome off, until its driver is loaded */
++ ret = gpio_request(GPIO_DISPLAY_OFF_N, "Display off");
++ if (ret)
++ return ret;
++
++ gpio_direction_output(GPIO_DISPLAY_OFF_N, 1);
++
++ /* before anything else, we request notification for any fb
++ * creation events */
++ fb_register_client(&n516_fb_notif);
++
++ n516_device = platform_device_alloc("metronomefb", -1);
++ if (!n516_device)
++ return -ENOMEM;
++
++ /* the n516_board that will be seen by metronomefb is a copy */
++ platform_device_add_data(n516_device, &n516_board,
++ sizeof(n516_board));
++
++ n516_presetup_fb();
++
++ return 0;
++}
++module_init(n516_init);
++
++MODULE_DESCRIPTION("board driver for n516 display");
++MODULE_AUTHOR("Yauhen Kharuzhy");
++MODULE_LICENSE("GPL");
+--- /dev/null
++++ b/arch/mips/jz4740/board-n516.c
+@@ -0,0 +1,203 @@
++/*
++ * linux/arch/mips/jz4740/board-516.c
++ *
++ * JZ4740 n516 board setup routines.
++ *
++ * Copyright (c) 2009, Yauhen Kharuzhy <jekhor@gmail.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#include <linux/init.h>
++#include <linux/sched.h>
++#include <linux/ioport.h>
++#include <linux/mm.h>
++#include <linux/console.h>
++#include <linux/delay.h>
++#include <linux/i2c.h>
++#include <linux/platform_device.h>
++#include <linux/mtd/mtd.h>
++#include <linux/leds.h>
++
++#include <linux/power_supply.h>
++#include <linux/power/gpio-charger.h>
++
++#include <linux/i2c.h>
++#include <linux/i2c-gpio.h>
++
++#include <asm/mach-jz4740/jz4740_mmc.h>
++#include <asm/mach-jz4740/jz4740_nand.h>
++
++#include <asm/mach-jz4740/board-n516.h>
++#include <asm/mach-jz4740/platform.h>
++
++#include "clock.h"
++
++static long n516_panic_blink(long time)
++{
++ gpio_set_value(GPIO_LED_ENABLE, 1);
++ mdelay(200);
++ gpio_set_value(GPIO_LED_ENABLE, 0);
++ mdelay(200);
++
++ return 400;
++}
++
++static void __init board_gpio_setup(void)
++{
++/* jz_gpio_enable_pullup(JZ_GPIO_PORTD(23));
++ jz_gpio_enable_pullup(JZ_GPIO_PORTD(24));*/
++}
++
++static struct i2c_gpio_platform_data n516_i2c_pdata = {
++ .sda_pin = JZ_GPIO_PORTD(23),
++ .scl_pin = JZ_GPIO_PORTD(24),
++ .udelay = 2,
++ .timeout = 3 * HZ,
++};
++
++static struct platform_device n516_i2c_device = {
++ .name = "i2c-gpio",
++ .id = -1,
++ .dev = {
++ .platform_data = &n516_i2c_pdata,
++ },
++};
++
++static const struct i2c_board_info n516_i2c_board_info[] = {
++ {
++ .type = "LPC524",
++ .addr = 0x54,
++ },
++ {
++ .type = "lm75a",
++ .addr = 0x48,
++ }
++};
++
++static struct jz4740_mmc_platform_data n516_mmc_pdata = {
++ .gpio_card_detect = GPIO_SD_CD_N,
++ .card_detect_active_low = 1,
++ .gpio_read_only = -1,
++ .gpio_power = GPIO_SD_VCC_EN_N,
++ .power_active_low = 1,
++};
++
++static struct gpio_led n516_leds[] = {
++ {
++ .name = "n516:blue:power",
++ .gpio = GPIO_LED_ENABLE,
++ .default_state = LEDS_GPIO_DEFSTATE_ON,
++ .default_trigger = "nand-disk",
++ }
++};
++
++static struct gpio_led_platform_data n516_leds_pdata = {
++ .leds = n516_leds,
++ .num_leds = ARRAY_SIZE(n516_leds),
++};
++
++static struct platform_device n516_leds_device = {
++ .name = "leds-gpio",
++ .id = -1,
++ .dev = {
++ .platform_data = &n516_leds_pdata,
++ },
++};
++
++static struct mtd_partition n516_partitions[] = {
++ { .name = "NAND BOOT partition",
++ .offset = 0 * 0x100000,
++ .size = 4 * 0x100000,
++ },
++ { .name = "NAND KERNEL partition",
++ .offset = 4 * 0x100000,
++ .size = 4 * 0x100000,
++ },
++ { .name = "NAND ROOTFS partition",
++ .offset = 8 * 0x100000,
++ .size = 504 * 0x100000,
++ },
++};
++
++static struct nand_ecclayout n516_ecclayout = {
++/* .eccbytes = 36,
++ .eccpos = {
++ 6, 7, 8, 9, 10, 11, 12, 13, 14,
++ 15, 16, 17, 18, 19, 20, 21, 22, 23,
++ 24, 25, 26, 27, 28, 29, 30, 31, 32,
++ 33, 34, 35, 36, 37, 38, 39, 40, 41,
++ },*/
++ .oobfree = {
++ {
++ .offset = 2,
++ .length = 4
++ },
++ {
++ .offset = 42,
++ .length = 22,
++ }
++ }
++};
++
++static struct jz_nand_platform_data n516_nand_pdata = {
++ .ecc_layout = &n516_ecclayout,
++ .partitions = n516_partitions,
++ .num_partitions = ARRAY_SIZE(n516_partitions),
++ .busy_gpio = 94,
++};
++
++static char *n516_batteries[] = {
++ "n516_battery",
++};
++
++static struct gpio_charger_platform_data n516_charger_pdata = {
++ .name = "usb",
++ .type = POWER_SUPPLY_TYPE_USB,
++ .gpio = GPIO_USB_DETECT,
++ .gpio_active_low = 1,
++ .batteries = n516_batteries,
++ .num_batteries = ARRAY_SIZE(n516_batteries),
++};
++
++static struct platform_device n516_charger_device = {
++ .name = "gpio-charger",
++ .dev = {
++ .platform_data = &n516_charger_pdata,
++ },
++};
++
++static struct platform_device *n516_devices[] __initdata = {
++ &jz4740_nand_device,
++ &n516_leds_device,
++ &jz4740_mmc_device,
++ &jz4740_i2s_device,
++ &jz4740_codec_device,
++ &jz4740_rtc_device,
++ &jz4740_udc_device,
++ &n516_i2c_device,
++ &n516_charger_device,
++};
++
++struct jz4740_clock_board_data jz4740_clock_bdata = {
++ .ext_rate = 12000000,
++ .rtc_rate = 32768,
++};
++
++extern int jz_gpiolib_init(void);
++
++static int n516_setup_platform(void)
++{
++ board_gpio_setup();
++
++ panic_blink = n516_panic_blink;
++ i2c_register_board_info(0, n516_i2c_board_info, ARRAY_SIZE(n516_i2c_board_info));
++ jz4740_mmc_device.dev.platform_data = &n516_mmc_pdata;
++ jz4740_nand_device.dev.platform_data = &n516_nand_pdata;
++
++ return platform_add_devices(n516_devices, ARRAY_SIZE(n516_devices));
++}
++arch_initcall(n516_setup_platform);
--- /dev/null
+From 7c51f9f9bab723d2cf7ea458ea459cc392a753f7 Mon Sep 17 00:00:00 2001
+From: Lars-Peter Clausen <lars@metafoo.de>
+Date: Sat, 24 Apr 2010 17:25:23 +0200
+Subject: [PATCH] Add n526 board support
+
+---
+ arch/mips/jz4740/Kconfig | 4 +
+ arch/mips/jz4740/Makefile | 1 +
+ arch/mips/jz4740/board-n526.c | 327 +++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 332 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/jz4740/board-n526.c
+
+--- a/arch/mips/jz4740/Kconfig
++++ b/arch/mips/jz4740/Kconfig
+@@ -10,6 +10,10 @@ config JZ4740_N516
+ bool "Hanvon n516 eBook reader"
+ select SOC_JZ4740
+
++config JZ4740_N526
++ bool "Hanvon n526 eBook reader"
++ select SOC_JZ4740
++
+ endchoice
+
+ config HAVE_PWM
+--- a/arch/mips/jz4740/Makefile
++++ b/arch/mips/jz4740/Makefile
+@@ -13,6 +13,7 @@ obj-$(CONFIG_DEBUG_FS) += clock-debugfs.
+
+ obj-$(CONFIG_JZ4740_QI_LB60) += board-qi_lb60.o
+ obj-$(CONFIG_JZ4740_N516) += board-n516.o board-n516-display.o
++obj-$(CONFIG_JZ4740_N526) += board-n526.o
+
+ # PM support
+
+--- /dev/null
++++ b/arch/mips/jz4740/board-n526.c
+@@ -0,0 +1,327 @@
++/*
++ * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
++ * N526 eBook reader support
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/gpio.h>
++
++
++#include <linux/power_supply.h>
++
++#include <video/broadsheetfb.h>
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++
++#include <linux/input.h>
++#include <linux/gpio_keys.h>
++
++#include <linux/i2c.h>
++#include <linux/i2c-gpio.h>
++
++#include "clock.h"
++
++#include <asm/mach-jz4740/jz4740_mmc.h>
++#include <asm/mach-jz4740/jz4740_nand.h>
++#include <asm/mach-jz4740/jz4740_fb.h>
++
++#include <asm/mach-jz4740/platform.h>
++
++/* NAND */
++static struct nand_ecclayout n526_ecclayout = {
++/* .eccbytes = 36,
++ .eccpos = {
++ 6, 7, 8, 9, 10, 11, 12, 13,
++ 14, 15, 16, 17, 18, 19, 20, 21,
++ 22, 23, 24, 25, 26, 27, 28, 29,
++ 30, 31, 32, 33, 34, 35, 36, 37,
++ 38, 39, 40, 41},*/
++ .oobfree = {
++ {.offset = 2,
++ .length = 4},
++ {.offset = 42,
++ .length = 22}}
++};
++
++static struct mtd_partition n526_partitions[] = {
++ { .name = "NAND BOOT partition",
++ .offset = 0 * 0x100000,
++ .size = 4 * 0x100000,
++ },
++ { .name = "NAND KERNEL partition",
++ .offset = 4 * 0x100000,
++ .size = 4 * 0x100000,
++ },
++ { .name = "NAND ROOTFS partition",
++ .offset = 16 * 0x100000,
++ .size = 498 * 0x100000,
++ },
++};
++
++static struct jz_nand_platform_data n526_nand_pdata = {
++ .ecc_layout = &n526_ecclayout,
++ .partitions = n526_partitions,
++ .num_partitions = ARRAY_SIZE(n526_partitions),
++ .busy_gpio = 94,
++};
++
++static struct jz4740_mmc_platform_data n526_mmc_pdata = {
++ .gpio_card_detect = JZ_GPIO_PORTD(7),
++ .card_detect_active_low = 1,
++ .gpio_read_only = -1,
++ .gpio_power = JZ_GPIO_PORTD(17),
++ .power_active_low = 1,
++};
++
++static struct gpio_led n526_leds[] = {
++ {
++ .name = "n526:blue:power",
++ .gpio = JZ_GPIO_PORTD(28),
++ .default_state = LEDS_GPIO_DEFSTATE_ON,
++ }
++};
++
++static struct gpio_led_platform_data n526_leds_pdata = {
++ .leds = n526_leds,
++ .num_leds = ARRAY_SIZE(n526_leds),
++};
++
++static struct platform_device n526_leds_device = {
++ .name = "leds-gpio",
++ .id = -1,
++ .dev = {
++ .platform_data = &n526_leds_pdata,
++ },
++};
++
++static void __init board_gpio_setup(void)
++{
++ /* We only need to enable/disable pullup here for pins used in generic
++ * drivers. Everything else is done by the drivers themselfs. */
++ jz_gpio_disable_pullup(JZ_GPIO_PORTD(17));
++ jz_gpio_enable_pullup(JZ_GPIO_PORTD(7));
++ jz_gpio_disable_pullup(JZ_GPIO_PORTC(19));
++ jz_gpio_disable_pullup(JZ_GPIO_PORTC(20));
++ jz_gpio_disable_pullup(JZ_GPIO_PORTC(21));
++ jz_gpio_disable_pullup(JZ_GPIO_PORTC(23));
++}
++
++
++static const int n526_eink_ctrl_gpios[] = {
++ 0,
++ JZ_GPIO_PORTC(23),
++ JZ_GPIO_PORTC(19),
++ JZ_GPIO_PORTC(20),
++};
++
++static void n526_eink_set_ctl(struct broadsheetfb_par * par, unsigned char ctrl, u8
++value)
++{
++ gpio_set_value(n526_eink_ctrl_gpios[ctrl], value);
++}
++
++
++static int n526_eink_wait(struct broadsheetfb_par *par)
++{
++ wait_event(par->waitq, gpio_get_value(JZ_GPIO_PORTB(17)));
++
++ return 0;
++}
++
++static u16 n526_eink_get_hdb(struct broadsheetfb_par *par)
++{
++ u16 value = 0;
++ jz_gpio_port_direction_input(JZ_GPIO_PORTC(0), 0xffff);
++ gpio_set_value(JZ_GPIO_PORTC(21), 0);
++ mdelay(100);
++
++ value = jz_gpio_port_get_value(JZ_GPIO_PORTC(0), 0xffff);
++
++ gpio_set_value(JZ_GPIO_PORTC(21), 1);
++ jz_gpio_port_direction_output(JZ_GPIO_PORTC(0), 0xffff);
++ return value;
++}
++
++static void n526_eink_set_hdb(struct broadsheetfb_par *par, u16 value)
++{
++ jz_gpio_port_set_value(JZ_GPIO_PORTC(0), value, 0xffff);
++}
++
++static int n526_eink_init(struct broadsheetfb_par *par)
++{
++ int i;
++
++ gpio_request(JZ_GPIO_PORTD(1), "display reset");
++ gpio_direction_output(JZ_GPIO_PORTD(1), 1);
++ mdelay(10);
++ gpio_set_value(JZ_GPIO_PORTD(1), 0);
++
++ gpio_request(JZ_GPIO_PORTB(18), "eink enable");
++ gpio_direction_output(JZ_GPIO_PORTB(18), 0);
++
++ gpio_request(JZ_GPIO_PORTB(29), "foobar");
++ gpio_direction_output(JZ_GPIO_PORTB(29), 1);
++
++ for(i = 1; i < ARRAY_SIZE(n526_eink_ctrl_gpios); ++i) {
++ gpio_request(n526_eink_ctrl_gpios[i], "eink display ctrl");
++ gpio_direction_output(n526_eink_ctrl_gpios[i], 0);
++ }
++
++ gpio_request(JZ_GPIO_PORTC(22), "foobar");
++ gpio_direction_input(JZ_GPIO_PORTC(22));
++ gpio_request(JZ_GPIO_PORTC(21), "eink nRD");
++ gpio_direction_output(JZ_GPIO_PORTC(21), 1);
++
++ for(i = 0; i < 16; ++i) {
++ gpio_request(JZ_GPIO_PORTC(i), "eink display data");
++ }
++ jz_gpio_port_direction_output(JZ_GPIO_PORTC(0), 0xffff);
++
++ gpio_set_value(JZ_GPIO_PORTB(18), 1);
++
++ return 0;
++}
++
++static irqreturn_t n526_eink_busy_irq(int irq, void *devid)
++{
++ struct broadsheetfb_par *par = devid;
++ wake_up(&par->waitq);
++
++ return IRQ_HANDLED;
++}
++
++static int n526_eink_setup_irq(struct fb_info *info)
++{
++ int ret;
++ struct broadsheetfb_par *par = info->par;
++
++ gpio_request(JZ_GPIO_PORTB(17), "eink busy");
++ gpio_direction_input(JZ_GPIO_PORTB(17));
++
++ ret = request_irq(gpio_to_irq(JZ_GPIO_PORTB(17)), n526_eink_busy_irq,
++ IRQF_DISABLED | IRQF_TRIGGER_RISING,
++ "eink busyline", par);
++ if (ret)
++ printk("n526 display: Failed to request busyline irq: %d\n", ret);
++ return 0;
++}
++
++static void n526_eink_cleanup(struct broadsheetfb_par *par)
++{
++}
++
++static struct broadsheet_board broadsheet_pdata = {
++ .owner = THIS_MODULE,
++ .init = n526_eink_init,
++ .wait_for_rdy = n526_eink_wait,
++ .set_ctl = n526_eink_set_ctl,
++ .set_hdb = n526_eink_set_hdb,
++ .get_hdb = n526_eink_get_hdb,
++ .cleanup = n526_eink_cleanup,
++ .setup_irq = n526_eink_setup_irq,
++};
++
++static struct platform_device n526_broadsheet_device = {
++ .name = "broadsheetfb",
++ .id = -1,
++ .dev = {
++ .platform_data = &broadsheet_pdata,
++ },
++};
++
++static struct gpio_keys_button qi_lb60_gpio_keys_buttons[] = {
++ [0] = {
++ .code = KEY_ENTER,
++ .gpio = 0,
++ .active_low = 1,
++ .desc = "Power",
++ },
++};
++
++static struct gpio_keys_platform_data qi_lb60_gpio_keys_data = {
++ .nbuttons = ARRAY_SIZE(qi_lb60_gpio_keys_buttons),
++ .buttons = qi_lb60_gpio_keys_buttons,
++};
++
++static struct platform_device qi_lb60_gpio_keys = {
++ .name = "gpio-keys",
++ .id = -1,
++ .dev = {
++ .platform_data = &qi_lb60_gpio_keys_data,
++ }
++};
++
++static struct i2c_gpio_platform_data n526_i2c_pdata = {
++ .sda_pin = JZ_GPIO_PORTD(23),
++ .scl_pin = JZ_GPIO_PORTD(24),
++ .udelay = 2,
++ .timeout = 3 * HZ,
++};
++
++static struct platform_device n526_i2c_device = {
++ .name = "i2c-gpio",
++ .id = -1,
++ .dev = {
++ .platform_data = &n526_i2c_pdata,
++ },
++};
++
++static struct i2c_board_info n526_i2c_board_info = {
++ .type = "n526-lpc",
++ .addr = 0x54,
++};
++
++static struct platform_device *jz_platform_devices[] __initdata = {
++ &jz4740_usb_ohci_device,
++ &jz4740_udc_device,
++ &jz4740_mmc_device,
++ &jz4740_nand_device,
++ &jz4740_i2s_device,
++ &jz4740_codec_device,
++ &jz4740_rtc_device,
++ &n526_leds_device,
++ &n526_broadsheet_device,
++ &qi_lb60_gpio_keys,
++ &n526_i2c_device,
++};
++
++static int __init n526_init_platform_devices(void)
++{
++
++ jz4740_nand_device.dev.platform_data = &n526_nand_pdata;
++ jz4740_mmc_device.dev.platform_data = &n526_mmc_pdata;
++
++ n526_i2c_board_info.irq = gpio_to_irq(JZ_GPIO_PORTD(14)),
++ i2c_register_board_info(0, &n526_i2c_board_info, 1);
++
++ return platform_add_devices(jz_platform_devices,
++ ARRAY_SIZE(jz_platform_devices));
++
++}
++
++struct jz4740_clock_board_data jz4740_clock_bdata = {
++ .ext_rate = 12000000,
++ .rtc_rate = 32768,
++};
++
++static int __init n526_board_setup(void)
++{
++ board_gpio_setup();
++
++ if (n526_init_platform_devices())
++ panic("Failed to initalize platform devices\n");
++
++ return 0;
++}
++arch_initcall(n526_board_setup);
--- /dev/null
+From c09d9002953c1182843050df1d4c639dea4af7f6 Mon Sep 17 00:00:00 2001
+From: Lars-Peter Clausen <lars@metafoo.de>
+Date: Sat, 17 Jul 2010 11:15:29 +0000
+Subject: [PATCH] MTD: Nand: Add JZ4740 NAND driver
+
+Add support for the NAND controller on JZ4740 SoCs.
+
+Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
+Cc: David Woodhouse <dwmw2@infradead.org>
+Cc: linux-mtd@lists.infradead.org
+Cc: linux-mips@linux-mips.org
+Cc: linux-kernel@vger.kernel.org
+Patchwork: https://patchwork.linux-mips.org/patch/1470/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/include/asm/mach-jz4740/jz4740_nand.h | 34 ++
+ drivers/mtd/nand/Kconfig | 6 +
+ drivers/mtd/nand/Makefile | 1 +
+ drivers/mtd/nand/jz4740_nand.c | 516 +++++++++++++++++++++++
+ 4 files changed, 557 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/include/asm/mach-jz4740/jz4740_nand.h
+ create mode 100644 drivers/mtd/nand/jz4740_nand.c
+
+--- /dev/null
++++ b/arch/mips/include/asm/mach-jz4740/jz4740_nand.h
+@@ -0,0 +1,34 @@
++/*
++ * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
++ * JZ4740 SoC NAND controller driver
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#ifndef __ASM_MACH_JZ4740_JZ4740_NAND_H__
++#define __ASM_MACH_JZ4740_JZ4740_NAND_H__
++
++#include <linux/mtd/nand.h>
++#include <linux/mtd/partitions.h>
++
++struct jz_nand_platform_data {
++ int num_partitions;
++ struct mtd_partition *partitions;
++
++ struct nand_ecclayout *ecc_layout;
++
++ unsigned int busy_gpio;
++
++ void (*ident_callback)(struct platform_device *, struct nand_chip *,
++ struct mtd_partition **, int *num_partitions);
++};
++
++#endif
+--- a/drivers/mtd/nand/Kconfig
++++ b/drivers/mtd/nand/Kconfig
+@@ -526,4 +526,10 @@ config MTD_NAND_NUC900
+ This enables the driver for the NAND Flash on evaluation board based
+ on w90p910 / NUC9xx.
+
++config MTD_NAND_JZ4740
++ tristate "Support for JZ4740 SoC NAND controller"
++ depends on MACH_JZ4740
++ help
++ Enables support for NAND Flash on JZ4740 SoC based boards.
++
+ endif # MTD_NAND
+--- a/drivers/mtd/nand/Makefile
++++ b/drivers/mtd/nand/Makefile
+@@ -46,5 +46,6 @@ obj-$(CONFIG_MTD_NAND_NOMADIK) += nomad
+ obj-$(CONFIG_MTD_NAND_BCM_UMI) += bcm_umi_nand.o nand_bcm_umi.o
+ obj-$(CONFIG_MTD_NAND_MPC5121_NFC) += mpc5121_nfc.o
+ obj-$(CONFIG_MTD_NAND_RICOH) += r852.o
++obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o
+
+ nand-objs := nand_base.o nand_bbt.o
+--- /dev/null
++++ b/drivers/mtd/nand/jz4740_nand.c
+@@ -0,0 +1,516 @@
++/*
++ * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
++ * JZ4740 SoC NAND controller driver
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/ioport.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/nand.h>
++#include <linux/mtd/partitions.h>
++
++#include <linux/gpio.h>
++
++#include <asm/mach-jz4740/jz4740_nand.h>
++
++#define JZ_REG_NAND_CTRL 0x50
++#define JZ_REG_NAND_ECC_CTRL 0x100
++#define JZ_REG_NAND_DATA 0x104
++#define JZ_REG_NAND_PAR0 0x108
++#define JZ_REG_NAND_PAR1 0x10C
++#define JZ_REG_NAND_PAR2 0x110
++#define JZ_REG_NAND_IRQ_STAT 0x114
++#define JZ_REG_NAND_IRQ_CTRL 0x118
++#define JZ_REG_NAND_ERR(x) (0x11C + ((x) << 2))
++
++#define JZ_NAND_ECC_CTRL_PAR_READY BIT(4)
++#define JZ_NAND_ECC_CTRL_ENCODING BIT(3)
++#define JZ_NAND_ECC_CTRL_RS BIT(2)
++#define JZ_NAND_ECC_CTRL_RESET BIT(1)
++#define JZ_NAND_ECC_CTRL_ENABLE BIT(0)
++
++#define JZ_NAND_STATUS_ERR_COUNT (BIT(31) | BIT(30) | BIT(29))
++#define JZ_NAND_STATUS_PAD_FINISH BIT(4)
++#define JZ_NAND_STATUS_DEC_FINISH BIT(3)
++#define JZ_NAND_STATUS_ENC_FINISH BIT(2)
++#define JZ_NAND_STATUS_UNCOR_ERROR BIT(1)
++#define JZ_NAND_STATUS_ERROR BIT(0)
++
++#define JZ_NAND_CTRL_ENABLE_CHIP(x) BIT((x) << 1)
++#define JZ_NAND_CTRL_ASSERT_CHIP(x) BIT(((x) << 1) + 1)
++
++#define JZ_NAND_MEM_ADDR_OFFSET 0x10000
++#define JZ_NAND_MEM_CMD_OFFSET 0x08000
++
++struct jz_nand {
++ struct mtd_info mtd;
++ struct nand_chip chip;
++ void __iomem *base;
++ struct resource *mem;
++
++ void __iomem *bank_base;
++ struct resource *bank_mem;
++
++ struct jz_nand_platform_data *pdata;
++ bool is_reading;
++};
++
++static inline struct jz_nand *mtd_to_jz_nand(struct mtd_info *mtd)
++{
++ return container_of(mtd, struct jz_nand, mtd);
++}
++
++static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
++{
++ struct jz_nand *nand = mtd_to_jz_nand(mtd);
++ struct nand_chip *chip = mtd->priv;
++ uint32_t reg;
++
++ if (ctrl & NAND_CTRL_CHANGE) {
++ BUG_ON((ctrl & NAND_ALE) && (ctrl & NAND_CLE));
++ if (ctrl & NAND_ALE)
++ chip->IO_ADDR_W = nand->bank_base + JZ_NAND_MEM_ADDR_OFFSET;
++ else if (ctrl & NAND_CLE)
++ chip->IO_ADDR_W = nand->bank_base + JZ_NAND_MEM_CMD_OFFSET;
++ else
++ chip->IO_ADDR_W = nand->bank_base;
++
++ reg = readl(nand->base + JZ_REG_NAND_CTRL);
++ if (ctrl & NAND_NCE)
++ reg |= JZ_NAND_CTRL_ASSERT_CHIP(0);
++ else
++ reg &= ~JZ_NAND_CTRL_ASSERT_CHIP(0);
++ writel(reg, nand->base + JZ_REG_NAND_CTRL);
++ }
++ if (dat != NAND_CMD_NONE)
++ writeb(dat, chip->IO_ADDR_W);
++}
++
++static int jz_nand_dev_ready(struct mtd_info *mtd)
++{
++ struct jz_nand *nand = mtd_to_jz_nand(mtd);
++ return gpio_get_value_cansleep(nand->pdata->busy_gpio);
++}
++
++static void jz_nand_hwctl(struct mtd_info *mtd, int mode)
++{
++ struct jz_nand *nand = mtd_to_jz_nand(mtd);
++ uint32_t reg;
++
++ writel(0, nand->base + JZ_REG_NAND_IRQ_STAT);
++ reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
++
++ reg |= JZ_NAND_ECC_CTRL_RESET;
++ reg |= JZ_NAND_ECC_CTRL_ENABLE;
++ reg |= JZ_NAND_ECC_CTRL_RS;
++
++ switch (mode) {
++ case NAND_ECC_READ:
++ reg &= ~JZ_NAND_ECC_CTRL_ENCODING;
++ nand->is_reading = true;
++ break;
++ case NAND_ECC_WRITE:
++ reg |= JZ_NAND_ECC_CTRL_ENCODING;
++ nand->is_reading = false;
++ break;
++ default:
++ break;
++ }
++
++ writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
++}
++
++static int jz_nand_calculate_ecc_rs(struct mtd_info *mtd, const uint8_t *dat,
++ uint8_t *ecc_code)
++{
++ struct jz_nand *nand = mtd_to_jz_nand(mtd);
++ uint32_t reg, status;
++ int i;
++ unsigned int timeout = 1000;
++ static uint8_t empty_block_ecc[] = {0xcd, 0x9d, 0x90, 0x58, 0xf4,
++ 0x8b, 0xff, 0xb7, 0x6f};
++
++ if (nand->is_reading)
++ return 0;
++
++ do {
++ status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
++ } while (!(status & JZ_NAND_STATUS_ENC_FINISH) && --timeout);
++
++ if (timeout == 0)
++ return -1;
++
++ reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
++ reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
++ writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
++
++ for (i = 0; i < 9; ++i)
++ ecc_code[i] = readb(nand->base + JZ_REG_NAND_PAR0 + i);
++
++ /* If the written data is completly 0xff, we also want to write 0xff as
++ * ecc, otherwise we will get in trouble when doing subpage writes. */
++ if (memcmp(ecc_code, empty_block_ecc, 9) == 0)
++ memset(ecc_code, 0xff, 9);
++
++ return 0;
++}
++
++static void jz_nand_correct_data(uint8_t *dat, int index, int mask)
++{
++ int offset = index & 0x7;
++ uint16_t data;
++
++ index += (index >> 3);
++
++ data = dat[index];
++ data |= dat[index+1] << 8;
++
++ mask ^= (data >> offset) & 0x1ff;
++ data &= ~(0x1ff << offset);
++ data |= (mask << offset);
++
++ dat[index] = data & 0xff;
++ dat[index+1] = (data >> 8) & 0xff;
++}
++
++static int jz_nand_correct_ecc_rs(struct mtd_info *mtd, uint8_t *dat,
++ uint8_t *read_ecc, uint8_t *calc_ecc)
++{
++ struct jz_nand *nand = mtd_to_jz_nand(mtd);
++ int i, error_count, index;
++ uint32_t reg, status, error;
++ uint32_t t;
++ unsigned int timeout = 1000;
++
++ t = read_ecc[0];
++
++ if (t == 0xff) {
++ for (i = 1; i < 9; ++i)
++ t &= read_ecc[i];
++
++ t &= dat[0];
++ t &= dat[nand->chip.ecc.size / 2];
++ t &= dat[nand->chip.ecc.size - 1];
++
++ if (t == 0xff) {
++ for (i = 1; i < nand->chip.ecc.size - 1; ++i)
++ t &= dat[i];
++ if (t == 0xff)
++ return 0;
++ }
++ }
++
++ for (i = 0; i < 9; ++i)
++ writeb(read_ecc[i], nand->base + JZ_REG_NAND_PAR0 + i);
++
++ reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
++ reg |= JZ_NAND_ECC_CTRL_PAR_READY;
++ writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
++
++ do {
++ status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
++ } while (!(status & JZ_NAND_STATUS_DEC_FINISH) && --timeout);
++
++ if (timeout == 0)
++ return -1;
++
++ reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
++ reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
++ writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
++
++ if (status & JZ_NAND_STATUS_ERROR) {
++ if (status & JZ_NAND_STATUS_UNCOR_ERROR)
++ return -1;
++
++ error_count = (status & JZ_NAND_STATUS_ERR_COUNT) >> 29;
++
++ for (i = 0; i < error_count; ++i) {
++ error = readl(nand->base + JZ_REG_NAND_ERR(i));
++ index = ((error >> 16) & 0x1ff) - 1;
++ if (index >= 0 && index < 512)
++ jz_nand_correct_data(dat, index, error & 0x1ff);
++ }
++
++ return error_count;
++ }
++
++ return 0;
++}
++
++
++/* Copy paste of nand_read_page_hwecc_oob_first except for different eccpos
++ * handling. The ecc area is for 4k chips 72 bytes long and thus does not fit
++ * into the eccpos array. */
++static int jz_nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
++ struct nand_chip *chip, uint8_t *buf, int page)
++{
++ int i, eccsize = chip->ecc.size;
++ int eccbytes = chip->ecc.bytes;
++ int eccsteps = chip->ecc.steps;
++ uint8_t *p = buf;
++ unsigned int ecc_offset = chip->page_shift;
++
++ /* Read the OOB area first */
++ chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
++ chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
++ chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
++
++ for (i = ecc_offset; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
++ int stat;
++
++ chip->ecc.hwctl(mtd, NAND_ECC_READ);
++ chip->read_buf(mtd, p, eccsize);
++
++ stat = chip->ecc.correct(mtd, p, &chip->oob_poi[i], NULL);
++ if (stat < 0)
++ mtd->ecc_stats.failed++;
++ else
++ mtd->ecc_stats.corrected += stat;
++ }
++ return 0;
++}
++
++/* Copy-and-paste of nand_write_page_hwecc with different eccpos handling. */
++static void jz_nand_write_page_hwecc(struct mtd_info *mtd,
++ struct nand_chip *chip, const uint8_t *buf)
++{
++ int i, eccsize = chip->ecc.size;
++ int eccbytes = chip->ecc.bytes;
++ int eccsteps = chip->ecc.steps;
++ const uint8_t *p = buf;
++ unsigned int ecc_offset = chip->page_shift;
++
++ for (i = ecc_offset; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
++ chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
++ chip->write_buf(mtd, p, eccsize);
++ chip->ecc.calculate(mtd, p, &chip->oob_poi[i]);
++ }
++
++ chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
++}
++
++#ifdef CONFIG_MTD_CMDLINE_PARTS
++static const char *part_probes[] = {"cmdline", NULL};
++#endif
++
++static int jz_nand_ioremap_resource(struct platform_device *pdev,
++ const char *name, struct resource **res, void __iomem **base)
++{
++ int ret;
++
++ *res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
++ if (!*res) {
++ dev_err(&pdev->dev, "Failed to get platform %s memory\n", name);
++ ret = -ENXIO;
++ goto err;
++ }
++
++ *res = request_mem_region((*res)->start, resource_size(*res),
++ pdev->name);
++ if (!*res) {
++ dev_err(&pdev->dev, "Failed to request %s memory region\n", name);
++ ret = -EBUSY;
++ goto err;
++ }
++
++ *base = ioremap((*res)->start, resource_size(*res));
++ if (!*base) {
++ dev_err(&pdev->dev, "Failed to ioremap %s memory region\n", name);
++ ret = -EBUSY;
++ goto err_release_mem;
++ }
++
++ return 0;
++
++err_release_mem:
++ release_mem_region((*res)->start, resource_size(*res));
++err:
++ *res = NULL;
++ *base = NULL;
++ return ret;
++}
++
++static int __devinit jz_nand_probe(struct platform_device *pdev)
++{
++ int ret;
++ struct jz_nand *nand;
++ struct nand_chip *chip;
++ struct mtd_info *mtd;
++ struct jz_nand_platform_data *pdata = pdev->dev.platform_data;
++#ifdef CONFIG_MTD_PARTITIONS
++ struct mtd_partition *partition_info;
++ int num_partitions = 0;
++#endif
++
++ nand = kzalloc(sizeof(*nand), GFP_KERNEL);
++ if (!nand) {
++ dev_err(&pdev->dev, "Failed to allocate device structure.\n");
++ return -ENOMEM;
++ }
++
++ ret = jz_nand_ioremap_resource(pdev, "mmio", &nand->mem, &nand->base);
++ if (ret)
++ goto err_free;
++ ret = jz_nand_ioremap_resource(pdev, "bank", &nand->bank_mem,
++ &nand->bank_base);
++ if (ret)
++ goto err_iounmap_mmio;
++
++ if (pdata && gpio_is_valid(pdata->busy_gpio)) {
++ ret = gpio_request(pdata->busy_gpio, "NAND busy pin");
++ if (ret) {
++ dev_err(&pdev->dev,
++ "Failed to request busy gpio %d: %d\n",
++ pdata->busy_gpio, ret);
++ goto err_iounmap_mem;
++ }
++ }
++
++ mtd = &nand->mtd;
++ chip = &nand->chip;
++ mtd->priv = chip;
++ mtd->owner = THIS_MODULE;
++ mtd->name = "jz4740-nand";
++
++ chip->ecc.hwctl = jz_nand_hwctl;
++ chip->ecc.calculate = jz_nand_calculate_ecc_rs;
++ chip->ecc.correct = jz_nand_correct_ecc_rs;
++ chip->ecc.mode = NAND_ECC_HW_OOB_FIRST;
++ chip->ecc.size = 512;
++ chip->ecc.bytes = 9;
++
++ chip->ecc.read_page = jz_nand_read_page_hwecc_oob_first;
++ chip->ecc.write_page = jz_nand_write_page_hwecc;
++
++ if (pdata)
++ chip->ecc.layout = pdata->ecc_layout;
++
++ chip->chip_delay = 50;
++ chip->cmd_ctrl = jz_nand_cmd_ctrl;
++
++ if (pdata && gpio_is_valid(pdata->busy_gpio))
++ chip->dev_ready = jz_nand_dev_ready;
++
++ chip->IO_ADDR_R = nand->bank_base;
++ chip->IO_ADDR_W = nand->bank_base;
++
++ nand->pdata = pdata;
++ platform_set_drvdata(pdev, nand);
++
++ writel(JZ_NAND_CTRL_ENABLE_CHIP(0), nand->base + JZ_REG_NAND_CTRL);
++
++ ret = nand_scan_ident(mtd, 1, NULL);
++ if (ret) {
++ dev_err(&pdev->dev, "Failed to scan nand\n");
++ goto err_gpio_free;
++ }
++
++ if (pdata && pdata->ident_callback) {
++ pdata->ident_callback(pdev, chip, &pdata->partitions,
++ &pdata->num_partitions);
++ }
++
++ ret = nand_scan_tail(mtd);
++ if (ret) {
++ dev_err(&pdev->dev, "Failed to scan nand\n");
++ goto err_gpio_free;
++ }
++
++#ifdef CONFIG_MTD_PARTITIONS
++#ifdef CONFIG_MTD_CMDLINE_PARTS
++ num_partitions = parse_mtd_partitions(mtd, part_probes,
++ &partition_info, 0);
++#endif
++ if (num_partitions <= 0 && pdata) {
++ num_partitions = pdata->num_partitions;
++ partition_info = pdata->partitions;
++ }
++
++ if (num_partitions > 0)
++ ret = add_mtd_partitions(mtd, partition_info, num_partitions);
++ else
++#endif
++ ret = add_mtd_device(mtd);
++
++ if (ret) {
++ dev_err(&pdev->dev, "Failed to add mtd device\n");
++ goto err_nand_release;
++ }
++
++ dev_info(&pdev->dev, "Successfully registered JZ4740 NAND driver\n");
++
++ return 0;
++
++err_nand_release:
++ nand_release(&nand->mtd);
++err_gpio_free:
++ platform_set_drvdata(pdev, NULL);
++ gpio_free(pdata->busy_gpio);
++err_iounmap_mem:
++ iounmap(nand->bank_base);
++err_iounmap_mmio:
++ iounmap(nand->base);
++err_free:
++ kfree(nand);
++ return ret;
++}
++
++static int __devexit jz_nand_remove(struct platform_device *pdev)
++{
++ struct jz_nand *nand = platform_get_drvdata(pdev);
++
++ nand_release(&nand->mtd);
++
++ /* Deassert and disable all chips */
++ writel(0, nand->base + JZ_REG_NAND_CTRL);
++
++ iounmap(nand->bank_base);
++ release_mem_region(nand->bank_mem->start, resource_size(nand->bank_mem));
++ iounmap(nand->base);
++ release_mem_region(nand->mem->start, resource_size(nand->mem));
++
++ platform_set_drvdata(pdev, NULL);
++ kfree(nand);
++
++ return 0;
++}
++
++struct platform_driver jz_nand_driver = {
++ .probe = jz_nand_probe,
++ .remove = __devexit_p(jz_nand_remove),
++ .driver = {
++ .name = "jz4740-nand",
++ .owner = THIS_MODULE,
++ },
++};
++
++static int __init jz_nand_init(void)
++{
++ return platform_driver_register(&jz_nand_driver);
++}
++module_init(jz_nand_init);
++
++static void __exit jz_nand_exit(void)
++{
++ platform_driver_unregister(&jz_nand_driver);
++}
++module_exit(jz_nand_exit);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
++MODULE_DESCRIPTION("NAND controller driver for JZ4740 SoC");
++MODULE_ALIAS("platform:jz4740-nand");
--- /dev/null
+From 91ead9db8aabb54f4867e5a7ed4782dcca2273f5 Mon Sep 17 00:00:00 2001
+From: Lars-Peter Clausen <lars@metafoo.de>
+Date: Sat, 17 Jul 2010 11:14:34 +0000
+Subject: [PATCH] FBDEV: JZ4740: Add framebuffer driver
+
+Add support for the LCD controller on JZ4740 SoCs.
+
+Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
+Cc: Andrew Morton <akpm@linux-foundation.org>
+Cc: linux-fbdev@vger.kernel.org
+Cc: linux-mips@linux-mips.org
+Cc: linux-kernel@vger.kernel.org
+Patchwork: https://patchwork.linux-mips.org/patch/1470/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/include/asm/mach-jz4740/jz4740_fb.h | 67 ++
+ drivers/video/Kconfig | 9 +
+ drivers/video/Makefile | 1 +
+ drivers/video/jz4740_fb.c | 847 +++++++++++++++++++++++++
+ 4 files changed, 924 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/include/asm/mach-jz4740/jz4740_fb.h
+ create mode 100644 drivers/video/jz4740_fb.c
+
+--- /dev/null
++++ b/arch/mips/include/asm/mach-jz4740/jz4740_fb.h
+@@ -0,0 +1,67 @@
++/*
++ * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#ifndef __ASM_MACH_JZ4740_JZ4740_FB_H__
++#define __ASM_MACH_JZ4740_JZ4740_FB_H__
++
++#include <linux/fb.h>
++
++enum jz4740_fb_lcd_type {
++ JZ_LCD_TYPE_GENERIC_16_BIT = 0,
++ JZ_LCD_TYPE_GENERIC_18_BIT = 0 | (1 << 4),
++ JZ_LCD_TYPE_SPECIAL_TFT_1 = 1,
++ JZ_LCD_TYPE_SPECIAL_TFT_2 = 2,
++ JZ_LCD_TYPE_SPECIAL_TFT_3 = 3,
++ JZ_LCD_TYPE_NON_INTERLACED_CCIR656 = 5,
++ JZ_LCD_TYPE_INTERLACED_CCIR656 = 7,
++ JZ_LCD_TYPE_SINGLE_COLOR_STN = 8,
++ JZ_LCD_TYPE_SINGLE_MONOCHROME_STN = 9,
++ JZ_LCD_TYPE_DUAL_COLOR_STN = 10,
++ JZ_LCD_TYPE_DUAL_MONOCHROME_STN = 11,
++ JZ_LCD_TYPE_8BIT_SERIAL = 12,
++};
++
++#define JZ4740_FB_SPECIAL_TFT_CONFIG(start, stop) (((start) << 16) | (stop))
++
++/*
++* width: width of the lcd display in mm
++* height: height of the lcd display in mm
++* num_modes: size of modes
++* modes: list of valid video modes
++* bpp: bits per pixel for the lcd
++* lcd_type: lcd type
++*/
++
++struct jz4740_fb_platform_data {
++ unsigned int width;
++ unsigned int height;
++
++ size_t num_modes;
++ struct fb_videomode *modes;
++
++ unsigned int bpp;
++ enum jz4740_fb_lcd_type lcd_type;
++
++ struct {
++ uint32_t spl;
++ uint32_t cls;
++ uint32_t ps;
++ uint32_t rev;
++ } special_tft_config;
++
++ unsigned pixclk_falling_edge:1;
++ unsigned date_enable_active_low:1;
++};
++
++#endif
+--- a/drivers/video/Kconfig
++++ b/drivers/video/Kconfig
+@@ -2229,6 +2229,15 @@ config FB_BROADSHEET
+ and could also have been called by other names when coupled with
+ a bridge adapter.
+
++config FB_JZ4740
++ tristate "JZ4740 LCD framebuffer support"
++ depends on FB
++ select FB_SYS_FILLRECT
++ select FB_SYS_COPYAREA
++ select FB_SYS_IMAGEBLIT
++ help
++ Framebuffer support for the JZ4740 SoC.
++
+ source "drivers/video/omap/Kconfig"
+ source "drivers/video/omap2/Kconfig"
+
+--- a/drivers/video/Makefile
++++ b/drivers/video/Makefile
+@@ -131,6 +131,7 @@ obj-$(CONFIG_FB_CARMINE) += car
+ obj-$(CONFIG_FB_MB862XX) += mb862xx/
+ obj-$(CONFIG_FB_MSM) += msm/
+ obj-$(CONFIG_FB_NUC900) += nuc900fb.o
++obj-$(CONFIG_FB_JZ4740) += jz4740_fb.o
+
+ # Platform or fallback drivers go here
+ obj-$(CONFIG_FB_UVESA) += uvesafb.o
+--- /dev/null
++++ b/drivers/video/jz4740_fb.c
+@@ -0,0 +1,847 @@
++/*
++ * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
++ * JZ4740 SoC LCD framebuffer driver
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/mutex.h>
++#include <linux/platform_device.h>
++
++#include <linux/clk.h>
++#include <linux/delay.h>
++
++#include <linux/console.h>
++#include <linux/fb.h>
++
++#include <linux/dma-mapping.h>
++
++#include <asm/mach-jz4740/jz4740_fb.h>
++#include <asm/mach-jz4740/gpio.h>
++
++#define JZ_REG_LCD_CFG 0x00
++#define JZ_REG_LCD_VSYNC 0x04
++#define JZ_REG_LCD_HSYNC 0x08
++#define JZ_REG_LCD_VAT 0x0C
++#define JZ_REG_LCD_DAH 0x10
++#define JZ_REG_LCD_DAV 0x14
++#define JZ_REG_LCD_PS 0x18
++#define JZ_REG_LCD_CLS 0x1C
++#define JZ_REG_LCD_SPL 0x20
++#define JZ_REG_LCD_REV 0x24
++#define JZ_REG_LCD_CTRL 0x30
++#define JZ_REG_LCD_STATE 0x34
++#define JZ_REG_LCD_IID 0x38
++#define JZ_REG_LCD_DA0 0x40
++#define JZ_REG_LCD_SA0 0x44
++#define JZ_REG_LCD_FID0 0x48
++#define JZ_REG_LCD_CMD0 0x4C
++#define JZ_REG_LCD_DA1 0x50
++#define JZ_REG_LCD_SA1 0x54
++#define JZ_REG_LCD_FID1 0x58
++#define JZ_REG_LCD_CMD1 0x5C
++
++#define JZ_LCD_CFG_SLCD BIT(31)
++#define JZ_LCD_CFG_PS_DISABLE BIT(23)
++#define JZ_LCD_CFG_CLS_DISABLE BIT(22)
++#define JZ_LCD_CFG_SPL_DISABLE BIT(21)
++#define JZ_LCD_CFG_REV_DISABLE BIT(20)
++#define JZ_LCD_CFG_HSYNCM BIT(19)
++#define JZ_LCD_CFG_PCLKM BIT(18)
++#define JZ_LCD_CFG_INV BIT(17)
++#define JZ_LCD_CFG_SYNC_DIR BIT(16)
++#define JZ_LCD_CFG_PS_POLARITY BIT(15)
++#define JZ_LCD_CFG_CLS_POLARITY BIT(14)
++#define JZ_LCD_CFG_SPL_POLARITY BIT(13)
++#define JZ_LCD_CFG_REV_POLARITY BIT(12)
++#define JZ_LCD_CFG_HSYNC_ACTIVE_LOW BIT(11)
++#define JZ_LCD_CFG_PCLK_FALLING_EDGE BIT(10)
++#define JZ_LCD_CFG_DE_ACTIVE_LOW BIT(9)
++#define JZ_LCD_CFG_VSYNC_ACTIVE_LOW BIT(8)
++#define JZ_LCD_CFG_18_BIT BIT(7)
++#define JZ_LCD_CFG_PDW (BIT(5) | BIT(4))
++#define JZ_LCD_CFG_MODE_MASK 0xf
++
++#define JZ_LCD_CTRL_BURST_4 (0x0 << 28)
++#define JZ_LCD_CTRL_BURST_8 (0x1 << 28)
++#define JZ_LCD_CTRL_BURST_16 (0x2 << 28)
++#define JZ_LCD_CTRL_RGB555 BIT(27)
++#define JZ_LCD_CTRL_OFUP BIT(26)
++#define JZ_LCD_CTRL_FRC_GRAYSCALE_16 (0x0 << 24)
++#define JZ_LCD_CTRL_FRC_GRAYSCALE_4 (0x1 << 24)
++#define JZ_LCD_CTRL_FRC_GRAYSCALE_2 (0x2 << 24)
++#define JZ_LCD_CTRL_PDD_MASK (0xff << 16)
++#define JZ_LCD_CTRL_EOF_IRQ BIT(13)
++#define JZ_LCD_CTRL_SOF_IRQ BIT(12)
++#define JZ_LCD_CTRL_OFU_IRQ BIT(11)
++#define JZ_LCD_CTRL_IFU0_IRQ BIT(10)
++#define JZ_LCD_CTRL_IFU1_IRQ BIT(9)
++#define JZ_LCD_CTRL_DD_IRQ BIT(8)
++#define JZ_LCD_CTRL_QDD_IRQ BIT(7)
++#define JZ_LCD_CTRL_REVERSE_ENDIAN BIT(6)
++#define JZ_LCD_CTRL_LSB_FISRT BIT(5)
++#define JZ_LCD_CTRL_DISABLE BIT(4)
++#define JZ_LCD_CTRL_ENABLE BIT(3)
++#define JZ_LCD_CTRL_BPP_1 0x0
++#define JZ_LCD_CTRL_BPP_2 0x1
++#define JZ_LCD_CTRL_BPP_4 0x2
++#define JZ_LCD_CTRL_BPP_8 0x3
++#define JZ_LCD_CTRL_BPP_15_16 0x4
++#define JZ_LCD_CTRL_BPP_18_24 0x5
++
++#define JZ_LCD_CMD_SOF_IRQ BIT(15)
++#define JZ_LCD_CMD_EOF_IRQ BIT(16)
++#define JZ_LCD_CMD_ENABLE_PAL BIT(12)
++
++#define JZ_LCD_SYNC_MASK 0x3ff
++
++#define JZ_LCD_STATE_DISABLED BIT(0)
++
++struct jzfb_framedesc {
++ uint32_t next;
++ uint32_t addr;
++ uint32_t id;
++ uint32_t cmd;
++} __packed;
++
++struct jzfb {
++ struct fb_info *fb;
++ struct platform_device *pdev;
++ void __iomem *base;
++ struct resource *mem;
++ struct jz4740_fb_platform_data *pdata;
++
++ size_t vidmem_size;
++ void *vidmem;
++ dma_addr_t vidmem_phys;
++ struct jzfb_framedesc *framedesc;
++ dma_addr_t framedesc_phys;
++
++ struct clk *ldclk;
++ struct clk *lpclk;
++
++ unsigned is_enabled:1;
++ struct mutex lock;
++
++ uint32_t pseudo_palette[16];
++};
++
++static const struct fb_fix_screeninfo jzfb_fix __devinitdata = {
++ .id = "JZ4740 FB",
++ .type = FB_TYPE_PACKED_PIXELS,
++ .visual = FB_VISUAL_TRUECOLOR,
++ .xpanstep = 0,
++ .ypanstep = 0,
++ .ywrapstep = 0,
++ .accel = FB_ACCEL_NONE,
++};
++
++static const struct jz_gpio_bulk_request jz_lcd_ctrl_pins[] = {
++ JZ_GPIO_BULK_PIN(LCD_PCLK),
++ JZ_GPIO_BULK_PIN(LCD_HSYNC),
++ JZ_GPIO_BULK_PIN(LCD_VSYNC),
++ JZ_GPIO_BULK_PIN(LCD_DE),
++ JZ_GPIO_BULK_PIN(LCD_PS),
++ JZ_GPIO_BULK_PIN(LCD_REV),
++ JZ_GPIO_BULK_PIN(LCD_CLS),
++ JZ_GPIO_BULK_PIN(LCD_SPL),
++};
++
++static const struct jz_gpio_bulk_request jz_lcd_data_pins[] = {
++ JZ_GPIO_BULK_PIN(LCD_DATA0),
++ JZ_GPIO_BULK_PIN(LCD_DATA1),
++ JZ_GPIO_BULK_PIN(LCD_DATA2),
++ JZ_GPIO_BULK_PIN(LCD_DATA3),
++ JZ_GPIO_BULK_PIN(LCD_DATA4),
++ JZ_GPIO_BULK_PIN(LCD_DATA5),
++ JZ_GPIO_BULK_PIN(LCD_DATA6),
++ JZ_GPIO_BULK_PIN(LCD_DATA7),
++ JZ_GPIO_BULK_PIN(LCD_DATA8),
++ JZ_GPIO_BULK_PIN(LCD_DATA9),
++ JZ_GPIO_BULK_PIN(LCD_DATA10),
++ JZ_GPIO_BULK_PIN(LCD_DATA11),
++ JZ_GPIO_BULK_PIN(LCD_DATA12),
++ JZ_GPIO_BULK_PIN(LCD_DATA13),
++ JZ_GPIO_BULK_PIN(LCD_DATA14),
++ JZ_GPIO_BULK_PIN(LCD_DATA15),
++ JZ_GPIO_BULK_PIN(LCD_DATA16),
++ JZ_GPIO_BULK_PIN(LCD_DATA17),
++};
++
++static unsigned int jzfb_num_ctrl_pins(struct jzfb *jzfb)
++{
++ unsigned int num;
++
++ switch (jzfb->pdata->lcd_type) {
++ case JZ_LCD_TYPE_GENERIC_16_BIT:
++ num = 4;
++ break;
++ case JZ_LCD_TYPE_GENERIC_18_BIT:
++ num = 4;
++ break;
++ case JZ_LCD_TYPE_8BIT_SERIAL:
++ num = 3;
++ break;
++ case JZ_LCD_TYPE_SPECIAL_TFT_1:
++ case JZ_LCD_TYPE_SPECIAL_TFT_2:
++ case JZ_LCD_TYPE_SPECIAL_TFT_3:
++ num = 8;
++ break;
++ default:
++ num = 0;
++ break;
++ }
++ return num;
++}
++
++static unsigned int jzfb_num_data_pins(struct jzfb *jzfb)
++{
++ unsigned int num;
++
++ switch (jzfb->pdata->lcd_type) {
++ case JZ_LCD_TYPE_GENERIC_16_BIT:
++ num = 16;
++ break;
++ case JZ_LCD_TYPE_GENERIC_18_BIT:
++ num = 18;
++ break;
++ case JZ_LCD_TYPE_8BIT_SERIAL:
++ num = 8;
++ break;
++ case JZ_LCD_TYPE_SPECIAL_TFT_1:
++ case JZ_LCD_TYPE_SPECIAL_TFT_2:
++ case JZ_LCD_TYPE_SPECIAL_TFT_3:
++ if (jzfb->pdata->bpp == 18)
++ num = 18;
++ else
++ num = 16;
++ break;
++ default:
++ num = 0;
++ break;
++ }
++ return num;
++}
++
++/* Based on CNVT_TOHW macro from skeletonfb.c */
++static inline uint32_t jzfb_convert_color_to_hw(unsigned val,
++ struct fb_bitfield *bf)
++{
++ return (((val << bf->length) + 0x7FFF - val) >> 16) << bf->offset;
++}
++
++static int jzfb_setcolreg(unsigned regno, unsigned red, unsigned green,
++ unsigned blue, unsigned transp, struct fb_info *fb)
++{
++ uint32_t color;
++
++ if (regno >= 16)
++ return -EINVAL;
++
++ color = jzfb_convert_color_to_hw(red, &fb->var.red);
++ color |= jzfb_convert_color_to_hw(green, &fb->var.green);
++ color |= jzfb_convert_color_to_hw(blue, &fb->var.blue);
++ color |= jzfb_convert_color_to_hw(transp, &fb->var.transp);
++
++ ((uint32_t *)(fb->pseudo_palette))[regno] = color;
++
++ return 0;
++}
++
++static int jzfb_get_controller_bpp(struct jzfb *jzfb)
++{
++ switch (jzfb->pdata->bpp) {
++ case 18:
++ case 24:
++ return 32;
++ case 15:
++ return 16;
++ default:
++ return jzfb->pdata->bpp;
++ }
++}
++
++static struct fb_videomode *jzfb_get_mode(struct jzfb *jzfb,
++ struct fb_var_screeninfo *var)
++{
++ size_t i;
++ struct fb_videomode *mode = jzfb->pdata->modes;
++
++ for (i = 0; i < jzfb->pdata->num_modes; ++i, ++mode) {
++ if (mode->xres == var->xres && mode->yres == var->yres)
++ return mode;
++ }
++
++ return NULL;
++}
++
++static int jzfb_check_var(struct fb_var_screeninfo *var, struct fb_info *fb)
++{
++ struct jzfb *jzfb = fb->par;
++ struct fb_videomode *mode;
++
++ if (var->bits_per_pixel != jzfb_get_controller_bpp(jzfb) &&
++ var->bits_per_pixel != jzfb->pdata->bpp)
++ return -EINVAL;
++
++ mode = jzfb_get_mode(jzfb, var);
++ if (mode == NULL)
++ return -EINVAL;
++
++ fb_videomode_to_var(var, mode);
++
++ switch (jzfb->pdata->bpp) {
++ case 8:
++ break;
++ case 15:
++ var->red.offset = 10;
++ var->red.length = 5;
++ var->green.offset = 6;
++ var->green.length = 5;
++ var->blue.offset = 0;
++ var->blue.length = 5;
++ break;
++ case 16:
++ var->red.offset = 11;
++ var->red.length = 5;
++ var->green.offset = 5;
++ var->green.length = 6;
++ var->blue.offset = 0;
++ var->blue.length = 5;
++ break;
++ case 18:
++ var->red.offset = 16;
++ var->red.length = 6;
++ var->green.offset = 8;
++ var->green.length = 6;
++ var->blue.offset = 0;
++ var->blue.length = 6;
++ var->bits_per_pixel = 32;
++ break;
++ case 32:
++ case 24:
++ var->transp.offset = 24;
++ var->transp.length = 8;
++ var->red.offset = 16;
++ var->red.length = 8;
++ var->green.offset = 8;
++ var->green.length = 8;
++ var->blue.offset = 0;
++ var->blue.length = 8;
++ var->bits_per_pixel = 32;
++ break;
++ default:
++ break;
++ }
++
++ return 0;
++}
++
++static int jzfb_set_par(struct fb_info *info)
++{
++ struct jzfb *jzfb = info->par;
++ struct jz4740_fb_platform_data *pdata = jzfb->pdata;
++ struct fb_var_screeninfo *var = &info->var;
++ struct fb_videomode *mode;
++ uint16_t hds, vds;
++ uint16_t hde, vde;
++ uint16_t ht, vt;
++ uint32_t ctrl;
++ uint32_t cfg;
++ unsigned long rate;
++
++ mode = jzfb_get_mode(jzfb, var);
++ if (mode == NULL)
++ return -EINVAL;
++
++ if (mode == info->mode)
++ return 0;
++
++ info->mode = mode;
++
++ hds = mode->hsync_len + mode->left_margin;
++ hde = hds + mode->xres;
++ ht = hde + mode->right_margin;
++
++ vds = mode->vsync_len + mode->upper_margin;
++ vde = vds + mode->yres;
++ vt = vde + mode->lower_margin;
++
++ ctrl = JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16;
++
++ switch (pdata->bpp) {
++ case 1:
++ ctrl |= JZ_LCD_CTRL_BPP_1;
++ break;
++ case 2:
++ ctrl |= JZ_LCD_CTRL_BPP_2;
++ break;
++ case 4:
++ ctrl |= JZ_LCD_CTRL_BPP_4;
++ break;
++ case 8:
++ ctrl |= JZ_LCD_CTRL_BPP_8;
++ break;
++ case 15:
++ ctrl |= JZ_LCD_CTRL_RGB555; /* Falltrough */
++ case 16:
++ ctrl |= JZ_LCD_CTRL_BPP_15_16;
++ break;
++ case 18:
++ case 24:
++ case 32:
++ ctrl |= JZ_LCD_CTRL_BPP_18_24;
++ break;
++ default:
++ break;
++ }
++
++ cfg = pdata->lcd_type & 0xf;
++
++ if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
++ cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW;
++
++ if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
++ cfg |= JZ_LCD_CFG_VSYNC_ACTIVE_LOW;
++
++ if (pdata->pixclk_falling_edge)
++ cfg |= JZ_LCD_CFG_PCLK_FALLING_EDGE;
++
++ if (pdata->date_enable_active_low)
++ cfg |= JZ_LCD_CFG_DE_ACTIVE_LOW;
++
++ if (pdata->lcd_type == JZ_LCD_TYPE_GENERIC_18_BIT)
++ cfg |= JZ_LCD_CFG_18_BIT;
++
++ if (mode->pixclock) {
++ rate = PICOS2KHZ(mode->pixclock) * 1000;
++ mode->refresh = rate / vt / ht;
++ } else {
++ if (pdata->lcd_type == JZ_LCD_TYPE_8BIT_SERIAL)
++ rate = mode->refresh * (vt + 2 * mode->xres) * ht;
++ else
++ rate = mode->refresh * vt * ht;
++
++ mode->pixclock = KHZ2PICOS(rate / 1000);
++ }
++
++ mutex_lock(&jzfb->lock);
++ if (!jzfb->is_enabled)
++ clk_enable(jzfb->ldclk);
++ else
++ ctrl |= JZ_LCD_CTRL_ENABLE;
++
++ switch (pdata->lcd_type) {
++ case JZ_LCD_TYPE_SPECIAL_TFT_1:
++ case JZ_LCD_TYPE_SPECIAL_TFT_2:
++ case JZ_LCD_TYPE_SPECIAL_TFT_3:
++ writel(pdata->special_tft_config.spl, jzfb->base + JZ_REG_LCD_SPL);
++ writel(pdata->special_tft_config.cls, jzfb->base + JZ_REG_LCD_CLS);
++ writel(pdata->special_tft_config.ps, jzfb->base + JZ_REG_LCD_PS);
++ writel(pdata->special_tft_config.ps, jzfb->base + JZ_REG_LCD_REV);
++ break;
++ default:
++ cfg |= JZ_LCD_CFG_PS_DISABLE;
++ cfg |= JZ_LCD_CFG_CLS_DISABLE;
++ cfg |= JZ_LCD_CFG_SPL_DISABLE;
++ cfg |= JZ_LCD_CFG_REV_DISABLE;
++ break;
++ }
++
++ writel(mode->hsync_len, jzfb->base + JZ_REG_LCD_HSYNC);
++ writel(mode->vsync_len, jzfb->base + JZ_REG_LCD_VSYNC);
++
++ writel((ht << 16) | vt, jzfb->base + JZ_REG_LCD_VAT);
++
++ writel((hds << 16) | hde, jzfb->base + JZ_REG_LCD_DAH);
++ writel((vds << 16) | vde, jzfb->base + JZ_REG_LCD_DAV);
++
++ writel(cfg, jzfb->base + JZ_REG_LCD_CFG);
++
++ writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL);
++
++ if (!jzfb->is_enabled)
++ clk_disable(jzfb->ldclk);
++
++ mutex_unlock(&jzfb->lock);
++
++ clk_set_rate(jzfb->lpclk, rate);
++ clk_set_rate(jzfb->ldclk, rate * 3);
++
++ return 0;
++}
++
++static void jzfb_enable(struct jzfb *jzfb)
++{
++ uint32_t ctrl;
++
++ clk_enable(jzfb->ldclk);
++
++ jz_gpio_bulk_resume(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb));
++ jz_gpio_bulk_resume(jz_lcd_data_pins, jzfb_num_data_pins(jzfb));
++
++ writel(0, jzfb->base + JZ_REG_LCD_STATE);
++
++ writel(jzfb->framedesc->next, jzfb->base + JZ_REG_LCD_DA0);
++
++ ctrl = readl(jzfb->base + JZ_REG_LCD_CTRL);
++ ctrl |= JZ_LCD_CTRL_ENABLE;
++ ctrl &= ~JZ_LCD_CTRL_DISABLE;
++ writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL);
++}
++
++static void jzfb_disable(struct jzfb *jzfb)
++{
++ uint32_t ctrl;
++
++ ctrl = readl(jzfb->base + JZ_REG_LCD_CTRL);
++ ctrl |= JZ_LCD_CTRL_DISABLE;
++ writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL);
++ do {
++ ctrl = readl(jzfb->base + JZ_REG_LCD_STATE);
++ } while (!(ctrl & JZ_LCD_STATE_DISABLED));
++
++ jz_gpio_bulk_suspend(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb));
++ jz_gpio_bulk_suspend(jz_lcd_data_pins, jzfb_num_data_pins(jzfb));
++
++ clk_disable(jzfb->ldclk);
++}
++
++static int jzfb_blank(int blank_mode, struct fb_info *info)
++{
++ struct jzfb *jzfb = info->par;
++
++ switch (blank_mode) {
++ case FB_BLANK_UNBLANK:
++ mutex_lock(&jzfb->lock);
++ if (jzfb->is_enabled) {
++ mutex_unlock(&jzfb->lock);
++ return 0;
++ }
++
++ jzfb_enable(jzfb);
++ jzfb->is_enabled = 1;
++
++ mutex_unlock(&jzfb->lock);
++ break;
++ default:
++ mutex_lock(&jzfb->lock);
++ if (!jzfb->is_enabled) {
++ mutex_unlock(&jzfb->lock);
++ return 0;
++ }
++
++ jzfb_disable(jzfb);
++ jzfb->is_enabled = 0;
++
++ mutex_unlock(&jzfb->lock);
++ break;
++ }
++
++ return 0;
++}
++
++static int jzfb_alloc_devmem(struct jzfb *jzfb)
++{
++ int max_videosize = 0;
++ struct fb_videomode *mode = jzfb->pdata->modes;
++ void *page;
++ int i;
++
++ for (i = 0; i < jzfb->pdata->num_modes; ++mode, ++i) {
++ if (max_videosize < mode->xres * mode->yres)
++ max_videosize = mode->xres * mode->yres;
++ }
++
++ max_videosize *= jzfb_get_controller_bpp(jzfb) >> 3;
++
++ jzfb->framedesc = dma_alloc_coherent(&jzfb->pdev->dev,
++ sizeof(*jzfb->framedesc),
++ &jzfb->framedesc_phys, GFP_KERNEL);
++
++ if (!jzfb->framedesc)
++ return -ENOMEM;
++
++ jzfb->vidmem_size = PAGE_ALIGN(max_videosize);
++ jzfb->vidmem = dma_alloc_coherent(&jzfb->pdev->dev,
++ jzfb->vidmem_size,
++ &jzfb->vidmem_phys, GFP_KERNEL);
++
++ if (!jzfb->vidmem)
++ goto err_free_framedesc;
++
++ for (page = jzfb->vidmem;
++ page < jzfb->vidmem + PAGE_ALIGN(jzfb->vidmem_size);
++ page += PAGE_SIZE) {
++ SetPageReserved(virt_to_page(page));
++ }
++
++ jzfb->framedesc->next = jzfb->framedesc_phys;
++ jzfb->framedesc->addr = jzfb->vidmem_phys;
++ jzfb->framedesc->id = 0xdeafbead;
++ jzfb->framedesc->cmd = 0;
++ jzfb->framedesc->cmd |= max_videosize / 4;
++
++ return 0;
++
++err_free_framedesc:
++ dma_free_coherent(&jzfb->pdev->dev, sizeof(*jzfb->framedesc),
++ jzfb->framedesc, jzfb->framedesc_phys);
++ return -ENOMEM;
++}
++
++static void jzfb_free_devmem(struct jzfb *jzfb)
++{
++ dma_free_coherent(&jzfb->pdev->dev, jzfb->vidmem_size,
++ jzfb->vidmem, jzfb->vidmem_phys);
++ dma_free_coherent(&jzfb->pdev->dev, sizeof(*jzfb->framedesc),
++ jzfb->framedesc, jzfb->framedesc_phys);
++}
++
++static struct fb_ops jzfb_ops = {
++ .owner = THIS_MODULE,
++ .fb_check_var = jzfb_check_var,
++ .fb_set_par = jzfb_set_par,
++ .fb_blank = jzfb_blank,
++ .fb_fillrect = sys_fillrect,
++ .fb_copyarea = sys_copyarea,
++ .fb_imageblit = sys_imageblit,
++ .fb_setcolreg = jzfb_setcolreg,
++};
++
++static int __devinit jzfb_probe(struct platform_device *pdev)
++{
++ int ret;
++ struct jzfb *jzfb;
++ struct fb_info *fb;
++ struct jz4740_fb_platform_data *pdata = pdev->dev.platform_data;
++ struct resource *mem;
++
++ if (!pdata) {
++ dev_err(&pdev->dev, "Missing platform data\n");
++ return -ENXIO;
++ }
++
++ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!mem) {
++ dev_err(&pdev->dev, "Failed to get register memory resource\n");
++ return -ENXIO;
++ }
++
++ mem = request_mem_region(mem->start, resource_size(mem), pdev->name);
++ if (!mem) {
++ dev_err(&pdev->dev, "Failed to request register memory region\n");
++ return -EBUSY;
++ }
++
++ fb = framebuffer_alloc(sizeof(struct jzfb), &pdev->dev);
++ if (!fb) {
++ dev_err(&pdev->dev, "Failed to allocate framebuffer device\n");
++ ret = -ENOMEM;
++ goto err_release_mem_region;
++ }
++
++ fb->fbops = &jzfb_ops;
++ fb->flags = FBINFO_DEFAULT;
++
++ jzfb = fb->par;
++ jzfb->pdev = pdev;
++ jzfb->pdata = pdata;
++ jzfb->mem = mem;
++
++ jzfb->ldclk = clk_get(&pdev->dev, "lcd");
++ if (IS_ERR(jzfb->ldclk)) {
++ ret = PTR_ERR(jzfb->ldclk);
++ dev_err(&pdev->dev, "Failed to get lcd clock: %d\n", ret);
++ goto err_framebuffer_release;
++ }
++
++ jzfb->lpclk = clk_get(&pdev->dev, "lcd_pclk");
++ if (IS_ERR(jzfb->lpclk)) {
++ ret = PTR_ERR(jzfb->lpclk);
++ dev_err(&pdev->dev, "Failed to get lcd pixel clock: %d\n", ret);
++ goto err_put_ldclk;
++ }
++
++ jzfb->base = ioremap(mem->start, resource_size(mem));
++ if (!jzfb->base) {
++ dev_err(&pdev->dev, "Failed to ioremap register memory region\n");
++ ret = -EBUSY;
++ goto err_put_lpclk;
++ }
++
++ platform_set_drvdata(pdev, jzfb);
++
++ mutex_init(&jzfb->lock);
++
++ fb_videomode_to_modelist(pdata->modes, pdata->num_modes,
++ &fb->modelist);
++ fb_videomode_to_var(&fb->var, pdata->modes);
++ fb->var.bits_per_pixel = pdata->bpp;
++ jzfb_check_var(&fb->var, fb);
++
++ ret = jzfb_alloc_devmem(jzfb);
++ if (ret) {
++ dev_err(&pdev->dev, "Failed to allocate video memory\n");
++ goto err_iounmap;
++ }
++
++ fb->fix = jzfb_fix;
++ fb->fix.line_length = fb->var.bits_per_pixel * fb->var.xres / 8;
++ fb->fix.mmio_start = mem->start;
++ fb->fix.mmio_len = resource_size(mem);
++ fb->fix.smem_start = jzfb->vidmem_phys;
++ fb->fix.smem_len = fb->fix.line_length * fb->var.yres;
++ fb->screen_base = jzfb->vidmem;
++ fb->pseudo_palette = jzfb->pseudo_palette;
++
++ fb_alloc_cmap(&fb->cmap, 256, 0);
++
++ clk_enable(jzfb->ldclk);
++ jzfb->is_enabled = 1;
++
++ writel(jzfb->framedesc->next, jzfb->base + JZ_REG_LCD_DA0);
++
++ fb->mode = NULL;
++ jzfb_set_par(fb);
++
++ jz_gpio_bulk_request(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb));
++ jz_gpio_bulk_request(jz_lcd_data_pins, jzfb_num_data_pins(jzfb));
++
++ ret = register_framebuffer(fb);
++ if (ret) {
++ dev_err(&pdev->dev, "Failed to register framebuffer: %d\n", ret);
++ goto err_free_devmem;
++ }
++
++ jzfb->fb = fb;
++
++ return 0;
++
++err_free_devmem:
++ jz_gpio_bulk_free(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb));
++ jz_gpio_bulk_free(jz_lcd_data_pins, jzfb_num_data_pins(jzfb));
++
++ fb_dealloc_cmap(&fb->cmap);
++ jzfb_free_devmem(jzfb);
++err_iounmap:
++ iounmap(jzfb->base);
++err_put_lpclk:
++ clk_put(jzfb->lpclk);
++err_put_ldclk:
++ clk_put(jzfb->ldclk);
++err_framebuffer_release:
++ framebuffer_release(fb);
++err_release_mem_region:
++ release_mem_region(mem->start, resource_size(mem));
++ return ret;
++}
++
++static int __devexit jzfb_remove(struct platform_device *pdev)
++{
++ struct jzfb *jzfb = platform_get_drvdata(pdev);
++
++ jzfb_blank(FB_BLANK_POWERDOWN, jzfb->fb);
++
++ jz_gpio_bulk_free(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb));
++ jz_gpio_bulk_free(jz_lcd_data_pins, jzfb_num_data_pins(jzfb));
++
++ iounmap(jzfb->base);
++ release_mem_region(jzfb->mem->start, resource_size(jzfb->mem));
++
++ fb_dealloc_cmap(&jzfb->fb->cmap);
++ jzfb_free_devmem(jzfb);
++
++ platform_set_drvdata(pdev, NULL);
++
++ clk_put(jzfb->lpclk);
++ clk_put(jzfb->ldclk);
++
++ framebuffer_release(jzfb->fb);
++
++ return 0;
++}
++
++#ifdef CONFIG_PM
++
++static int jzfb_suspend(struct device *dev)
++{
++ struct jzfb *jzfb = dev_get_drvdata(dev);
++
++ acquire_console_sem();
++ fb_set_suspend(jzfb->fb, 1);
++ release_console_sem();
++
++ mutex_lock(&jzfb->lock);
++ if (jzfb->is_enabled)
++ jzfb_disable(jzfb);
++ mutex_unlock(&jzfb->lock);
++
++ return 0;
++}
++
++static int jzfb_resume(struct device *dev)
++{
++ struct jzfb *jzfb = dev_get_drvdata(dev);
++ clk_enable(jzfb->ldclk);
++
++ mutex_lock(&jzfb->lock);
++ if (jzfb->is_enabled)
++ jzfb_enable(jzfb);
++ mutex_unlock(&jzfb->lock);
++
++ acquire_console_sem();
++ fb_set_suspend(jzfb->fb, 0);
++ release_console_sem();
++
++ return 0;
++}
++
++static const struct dev_pm_ops jzfb_pm_ops = {
++ .suspend = jzfb_suspend,
++ .resume = jzfb_resume,
++ .poweroff = jzfb_suspend,
++ .restore = jzfb_resume,
++};
++
++#define JZFB_PM_OPS (&jzfb_pm_ops)
++
++#else
++#define JZFB_PM_OPS NULL
++#endif
++
++static struct platform_driver jzfb_driver = {
++ .probe = jzfb_probe,
++ .remove = __devexit_p(jzfb_remove),
++ .driver = {
++ .name = "jz4740-fb",
++ .pm = JZFB_PM_OPS,
++ },
++};
++
++static int __init jzfb_init(void)
++{
++ return platform_driver_register(&jzfb_driver);
++}
++module_init(jzfb_init);
++
++static void __exit jzfb_exit(void)
++{
++ platform_driver_unregister(&jzfb_driver);
++}
++module_exit(jzfb_exit);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
++MODULE_DESCRIPTION("JZ4740 SoC LCD framebuffer driver");
++MODULE_ALIAS("platform:jz4740-fb");
--- /dev/null
+From 21a0c050c7471b9d87e720a84f6733bbe8e19835 Mon Sep 17 00:00:00 2001
+From: Lars-Peter Clausen <lars@metafoo.de>
+Date: Sat, 19 Jun 2010 18:29:50 +0000
+Subject: [PATCH] RTC: Add JZ4740 RTC driver
+
+Add support for the RTC unit on JZ4740 SoCs.
+
+Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
+Cc: Alessandro Zummo <a.zummo@towertech.it>
+Cc: Paul Gortmaker <p_gortmaker@yahoo.com>
+Cc: rtc-linux@googlegroups.com
+Acked-by: Wan ZongShun <mcuos.com@gmail.com>
+Cc: linux-mips@linux-mips.org
+Cc: linux-kernel@vger.kernel.org
+Cc: Alessandro Zummo <a.zummo@towertech.it>,
+Patchwork: https://patchwork.linux-mips.org/patch/1424/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ drivers/rtc/Kconfig | 11 ++
+ drivers/rtc/Makefile | 1 +
+ drivers/rtc/rtc-jz4740.c | 345 ++++++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 357 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/rtc/rtc-jz4740.c
+
+--- a/drivers/rtc/Kconfig
++++ b/drivers/rtc/Kconfig
+@@ -914,4 +914,15 @@ config RTC_DRV_MPC5121
+ This driver can also be built as a module. If so, the module
+ will be called rtc-mpc5121.
+
++config RTC_DRV_JZ4740
++ tristate "Ingenic JZ4740 SoC"
++ depends on RTC_CLASS
++ depends on MACH_JZ4740
++ help
++ If you say yes here you get support for the Ingenic JZ4740 SoC RTC
++ controller.
++
++ This driver can also be buillt as a module. If so, the module
++ will be called rtc-jz4740.
++
+ endif # RTC_CLASS
+--- a/drivers/rtc/Makefile
++++ b/drivers/rtc/Makefile
+@@ -47,6 +47,7 @@ obj-$(CONFIG_RTC_DRV_EP93XX) += rtc-ep93
+ obj-$(CONFIG_RTC_DRV_FM3130) += rtc-fm3130.o
+ obj-$(CONFIG_RTC_DRV_GENERIC) += rtc-generic.o
+ obj-$(CONFIG_RTC_DRV_ISL1208) += rtc-isl1208.o
++obj-$(CONFIG_RTC_DRV_JZ4740) += rtc-jz4740.o
+ obj-$(CONFIG_RTC_DRV_M41T80) += rtc-m41t80.o
+ obj-$(CONFIG_RTC_DRV_M41T94) += rtc-m41t94.o
+ obj-$(CONFIG_RTC_DRV_M48T35) += rtc-m48t35.o
+--- /dev/null
++++ b/drivers/rtc/rtc-jz4740.c
+@@ -0,0 +1,345 @@
++/*
++ * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
++ * JZ4740 SoC RTC driver
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/rtc.h>
++#include <linux/slab.h>
++#include <linux/spinlock.h>
++
++#define JZ_REG_RTC_CTRL 0x00
++#define JZ_REG_RTC_SEC 0x04
++#define JZ_REG_RTC_SEC_ALARM 0x08
++#define JZ_REG_RTC_REGULATOR 0x0C
++#define JZ_REG_RTC_HIBERNATE 0x20
++#define JZ_REG_RTC_SCRATCHPAD 0x34
++
++#define JZ_RTC_CTRL_WRDY BIT(7)
++#define JZ_RTC_CTRL_1HZ BIT(6)
++#define JZ_RTC_CTRL_1HZ_IRQ BIT(5)
++#define JZ_RTC_CTRL_AF BIT(4)
++#define JZ_RTC_CTRL_AF_IRQ BIT(3)
++#define JZ_RTC_CTRL_AE BIT(2)
++#define JZ_RTC_CTRL_ENABLE BIT(0)
++
++struct jz4740_rtc {
++ struct resource *mem;
++ void __iomem *base;
++
++ struct rtc_device *rtc;
++
++ unsigned int irq;
++
++ spinlock_t lock;
++};
++
++static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg)
++{
++ return readl(rtc->base + reg);
++}
++
++static int jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc)
++{
++ uint32_t ctrl;
++ int timeout = 1000;
++
++ do {
++ ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
++ } while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout);
++
++ return timeout ? 0 : -EIO;
++}
++
++static inline int jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg,
++ uint32_t val)
++{
++ int ret;
++ ret = jz4740_rtc_wait_write_ready(rtc);
++ if (ret == 0)
++ writel(val, rtc->base + reg);
++
++ return ret;
++}
++
++static int jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask,
++ bool set)
++{
++ int ret;
++ unsigned long flags;
++ uint32_t ctrl;
++
++ spin_lock_irqsave(&rtc->lock, flags);
++
++ ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
++
++ /* Don't clear interrupt flags by accident */
++ ctrl |= JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF;
++
++ if (set)
++ ctrl |= mask;
++ else
++ ctrl &= ~mask;
++
++ ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CTRL, ctrl);
++
++ spin_unlock_irqrestore(&rtc->lock, flags);
++
++ return ret;
++}
++
++static int jz4740_rtc_read_time(struct device *dev, struct rtc_time *time)
++{
++ struct jz4740_rtc *rtc = dev_get_drvdata(dev);
++ uint32_t secs, secs2;
++ int timeout = 5;
++
++ /* If the seconds register is read while it is updated, it can contain a
++ * bogus value. This can be avoided by making sure that two consecutive
++ * reads have the same value.
++ */
++ secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
++ secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
++
++ while (secs != secs2 && --timeout) {
++ secs = secs2;
++ secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
++ }
++
++ if (timeout == 0)
++ return -EIO;
++
++ rtc_time_to_tm(secs, time);
++
++ return rtc_valid_tm(time);
++}
++
++static int jz4740_rtc_set_mmss(struct device *dev, unsigned long secs)
++{
++ struct jz4740_rtc *rtc = dev_get_drvdata(dev);
++
++ return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, secs);
++}
++
++static int jz4740_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
++{
++ struct jz4740_rtc *rtc = dev_get_drvdata(dev);
++ uint32_t secs;
++ uint32_t ctrl;
++
++ secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
++
++ ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
++
++ alrm->enabled = !!(ctrl & JZ_RTC_CTRL_AE);
++ alrm->pending = !!(ctrl & JZ_RTC_CTRL_AF);
++
++ rtc_time_to_tm(secs, &alrm->time);
++
++ return rtc_valid_tm(&alrm->time);
++}
++
++static int jz4740_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
++{
++ int ret;
++ struct jz4740_rtc *rtc = dev_get_drvdata(dev);
++ unsigned long secs;
++
++ rtc_tm_to_time(&alrm->time, &secs);
++
++ ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC_ALARM, secs);
++ if (!ret)
++ ret = jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AE, alrm->enabled);
++
++ return ret;
++}
++
++static int jz4740_rtc_update_irq_enable(struct device *dev, unsigned int enable)
++{
++ struct jz4740_rtc *rtc = dev_get_drvdata(dev);
++ return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ_IRQ, enable);
++}
++
++static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
++{
++ struct jz4740_rtc *rtc = dev_get_drvdata(dev);
++ return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ, enable);
++}
++
++static struct rtc_class_ops jz4740_rtc_ops = {
++ .read_time = jz4740_rtc_read_time,
++ .set_mmss = jz4740_rtc_set_mmss,
++ .read_alarm = jz4740_rtc_read_alarm,
++ .set_alarm = jz4740_rtc_set_alarm,
++ .update_irq_enable = jz4740_rtc_update_irq_enable,
++ .alarm_irq_enable = jz4740_rtc_alarm_irq_enable,
++};
++
++static irqreturn_t jz4740_rtc_irq(int irq, void *data)
++{
++ struct jz4740_rtc *rtc = data;
++ uint32_t ctrl;
++ unsigned long events = 0;
++
++ ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
++
++ if (ctrl & JZ_RTC_CTRL_1HZ)
++ events |= (RTC_UF | RTC_IRQF);
++
++ if (ctrl & JZ_RTC_CTRL_AF)
++ events |= (RTC_AF | RTC_IRQF);
++
++ rtc_update_irq(rtc->rtc, 1, events);
++
++ jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF, false);
++
++ return IRQ_HANDLED;
++}
++
++void jz4740_rtc_poweroff(struct device *dev)
++{
++ struct jz4740_rtc *rtc = dev_get_drvdata(dev);
++ jz4740_rtc_reg_write(rtc, JZ_REG_RTC_HIBERNATE, 1);
++}
++EXPORT_SYMBOL_GPL(jz4740_rtc_poweroff);
++
++static int __devinit jz4740_rtc_probe(struct platform_device *pdev)
++{
++ int ret;
++ struct jz4740_rtc *rtc;
++ uint32_t scratchpad;
++
++ rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
++ if (!rtc)
++ return -ENOMEM;
++
++ rtc->irq = platform_get_irq(pdev, 0);
++ if (rtc->irq < 0) {
++ ret = -ENOENT;
++ dev_err(&pdev->dev, "Failed to get platform irq\n");
++ goto err_free;
++ }
++
++ rtc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!rtc->mem) {
++ ret = -ENOENT;
++ dev_err(&pdev->dev, "Failed to get platform mmio memory\n");
++ goto err_free;
++ }
++
++ rtc->mem = request_mem_region(rtc->mem->start, resource_size(rtc->mem),
++ pdev->name);
++ if (!rtc->mem) {
++ ret = -EBUSY;
++ dev_err(&pdev->dev, "Failed to request mmio memory region\n");
++ goto err_free;
++ }
++
++ rtc->base = ioremap_nocache(rtc->mem->start, resource_size(rtc->mem));
++ if (!rtc->base) {
++ ret = -EBUSY;
++ dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
++ goto err_release_mem_region;
++ }
++
++ spin_lock_init(&rtc->lock);
++
++ platform_set_drvdata(pdev, rtc);
++
++ rtc->rtc = rtc_device_register(pdev->name, &pdev->dev, &jz4740_rtc_ops,
++ THIS_MODULE);
++ if (IS_ERR(rtc->rtc)) {
++ ret = PTR_ERR(rtc->rtc);
++ dev_err(&pdev->dev, "Failed to register rtc device: %d\n", ret);
++ goto err_iounmap;
++ }
++
++ ret = request_irq(rtc->irq, jz4740_rtc_irq, 0,
++ pdev->name, rtc);
++ if (ret) {
++ dev_err(&pdev->dev, "Failed to request rtc irq: %d\n", ret);
++ goto err_unregister_rtc;
++ }
++
++ scratchpad = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD);
++ if (scratchpad != 0x12345678) {
++ ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678);
++ ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, 0);
++ if (ret) {
++ dev_err(&pdev->dev, "Could not write write to RTC registers\n");
++ goto err_free_irq;
++ }
++ }
++
++ return 0;
++
++err_free_irq:
++ free_irq(rtc->irq, rtc);
++err_unregister_rtc:
++ rtc_device_unregister(rtc->rtc);
++err_iounmap:
++ platform_set_drvdata(pdev, NULL);
++ iounmap(rtc->base);
++err_release_mem_region:
++ release_mem_region(rtc->mem->start, resource_size(rtc->mem));
++err_free:
++ kfree(rtc);
++
++ return ret;
++}
++
++static int __devexit jz4740_rtc_remove(struct platform_device *pdev)
++{
++ struct jz4740_rtc *rtc = platform_get_drvdata(pdev);
++
++ free_irq(rtc->irq, rtc);
++
++ rtc_device_unregister(rtc->rtc);
++
++ iounmap(rtc->base);
++ release_mem_region(rtc->mem->start, resource_size(rtc->mem));
++
++ kfree(rtc);
++
++ platform_set_drvdata(pdev, NULL);
++
++ return 0;
++}
++
++struct platform_driver jz4740_rtc_driver = {
++ .probe = jz4740_rtc_probe,
++ .remove = __devexit_p(jz4740_rtc_remove),
++ .driver = {
++ .name = "jz4740-rtc",
++ .owner = THIS_MODULE,
++ },
++};
++
++static int __init jz4740_rtc_init(void)
++{
++ return platform_driver_register(&jz4740_rtc_driver);
++}
++module_init(jz4740_rtc_init);
++
++static void __exit jz4740_rtc_exit(void)
++{
++ platform_driver_unregister(&jz4740_rtc_driver);
++}
++module_exit(jz4740_rtc_exit);
++
++MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("RTC driver for the JZ4740 SoC\n");
++MODULE_ALIAS("platform:jz4740-rtc");
--- /dev/null
+From ae6e941c5d58262c0a09c355ae384b7109977053 Mon Sep 17 00:00:00 2001
+From: Lars-Peter Clausen <lars@metafoo.de>
+Date: Mon, 12 Jul 2010 03:48:08 +0200
+Subject: [PATCH] mfd: Add JZ4740 ADC driver
+
+This patch adds a MFD driver for the JZ4740 ADC unit. The driver is used to
+demultiplex IRQs and synchronize access to shared registers between the
+battery, hwmon and (future) touchscreen driver.
+
+Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
+Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
+---
+ drivers/mfd/Kconfig | 8 +
+ drivers/mfd/Makefile | 1 +
+ drivers/mfd/jz4740-adc.c | 394 ++++++++++++++++++++++++++++++++++++++++++++
+ include/linux/jz4740-adc.h | 32 ++++
+ 4 files changed, 435 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/mfd/jz4740-adc.c
+ create mode 100644 include/linux/jz4740-adc.h
+
+--- a/drivers/mfd/Kconfig
++++ b/drivers/mfd/Kconfig
+@@ -482,6 +482,14 @@ config MFD_JANZ_CMODIO
+ host many different types of MODULbus daughterboards, including
+ CAN and GPIO controllers.
+
++config MFD_JZ4740_ADC
++ tristate "Support for the JZ4740 SoC ADC core"
++ select MFD_CORE
++ depends on MACH_JZ4740
++ help
++ Say yes here if you want support for the ADC unit in the JZ4740 SoC.
++ This driver is necessary for jz4740-battery and jz4740-hwmon driver.
++
+ endif # MFD_SUPPORT
+
+ menu "Multimedia Capabilities Port drivers"
+--- a/drivers/mfd/Makefile
++++ b/drivers/mfd/Makefile
+@@ -71,3 +71,4 @@ obj-$(CONFIG_PMIC_ADP5520) += adp5520.o
+ obj-$(CONFIG_LPC_SCH) += lpc_sch.o
+ obj-$(CONFIG_MFD_RDC321X) += rdc321x-southbridge.o
+ obj-$(CONFIG_MFD_JANZ_CMODIO) += janz-cmodio.o
++obj-$(CONFIG_MFD_JZ4740_ADC) += jz4740-adc.o
+--- /dev/null
++++ b/drivers/mfd/jz4740-adc.c
+@@ -0,0 +1,394 @@
++/*
++ * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
++ * JZ4740 SoC ADC driver
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ * This driver synchronizes access to the JZ4740 ADC core between the
++ * JZ4740 battery and hwmon drivers.
++ */
++
++#include <linux/err.h>
++#include <linux/irq.h>
++#include <linux/interrupt.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/spinlock.h>
++
++#include <linux/clk.h>
++#include <linux/mfd/core.h>
++
++#include <linux/jz4740-adc.h>
++
++
++#define JZ_REG_ADC_ENABLE 0x00
++#define JZ_REG_ADC_CFG 0x04
++#define JZ_REG_ADC_CTRL 0x08
++#define JZ_REG_ADC_STATUS 0x0c
++
++#define JZ_REG_ADC_TOUCHSCREEN_BASE 0x10
++#define JZ_REG_ADC_BATTERY_BASE 0x1c
++#define JZ_REG_ADC_HWMON_BASE 0x20
++
++#define JZ_ADC_ENABLE_TOUCH BIT(2)
++#define JZ_ADC_ENABLE_BATTERY BIT(1)
++#define JZ_ADC_ENABLE_ADCIN BIT(0)
++
++enum {
++ JZ_ADC_IRQ_ADCIN = 0,
++ JZ_ADC_IRQ_BATTERY,
++ JZ_ADC_IRQ_TOUCH,
++ JZ_ADC_IRQ_PENUP,
++ JZ_ADC_IRQ_PENDOWN,
++};
++
++struct jz4740_adc {
++ struct resource *mem;
++ void __iomem *base;
++
++ int irq;
++ int irq_base;
++
++ struct clk *clk;
++ atomic_t clk_ref;
++
++ spinlock_t lock;
++};
++
++static inline void jz4740_adc_irq_set_masked(struct jz4740_adc *adc, int irq,
++ bool masked)
++{
++ unsigned long flags;
++ uint8_t val;
++
++ irq -= adc->irq_base;
++
++ spin_lock_irqsave(&adc->lock, flags);
++
++ val = readb(adc->base + JZ_REG_ADC_CTRL);
++ if (masked)
++ val |= BIT(irq);
++ else
++ val &= ~BIT(irq);
++ writeb(val, adc->base + JZ_REG_ADC_CTRL);
++
++ spin_unlock_irqrestore(&adc->lock, flags);
++}
++
++static void jz4740_adc_irq_mask(unsigned int irq)
++{
++ struct jz4740_adc *adc = get_irq_chip_data(irq);
++ jz4740_adc_irq_set_masked(adc, irq, true);
++}
++
++static void jz4740_adc_irq_unmask(unsigned int irq)
++{
++ struct jz4740_adc *adc = get_irq_chip_data(irq);
++ jz4740_adc_irq_set_masked(adc, irq, false);
++}
++
++static void jz4740_adc_irq_ack(unsigned int irq)
++{
++ struct jz4740_adc *adc = get_irq_chip_data(irq);
++
++ irq -= adc->irq_base;
++ writeb(BIT(irq), adc->base + JZ_REG_ADC_STATUS);
++}
++
++static struct irq_chip jz4740_adc_irq_chip = {
++ .name = "jz4740-adc",
++ .mask = jz4740_adc_irq_mask,
++ .unmask = jz4740_adc_irq_unmask,
++ .ack = jz4740_adc_irq_ack,
++};
++
++static void jz4740_adc_irq_demux(unsigned int irq, struct irq_desc *desc)
++{
++ struct jz4740_adc *adc = get_irq_desc_data(desc);
++ uint8_t status;
++ unsigned int i;
++
++ status = readb(adc->base + JZ_REG_ADC_STATUS);
++
++ for (i = 0; i < 5; ++i) {
++ if (status & BIT(i))
++ generic_handle_irq(adc->irq_base + i);
++ }
++}
++
++
++/* Refcounting for the ADC clock is done in here instead of in the clock
++ * framework, because it is the only clock which is shared between multiple
++ * devices and thus is the only clock which needs refcounting */
++static inline void jz4740_adc_clk_enable(struct jz4740_adc *adc)
++{
++ if (atomic_inc_return(&adc->clk_ref) == 1)
++ clk_enable(adc->clk);
++}
++
++static inline void jz4740_adc_clk_disable(struct jz4740_adc *adc)
++{
++ if (atomic_dec_return(&adc->clk_ref) == 0)
++ clk_disable(adc->clk);
++}
++
++static inline void jz4740_adc_set_enabled(struct jz4740_adc *adc, int engine,
++ bool enabled)
++{
++ unsigned long flags;
++ uint8_t val;
++
++ spin_lock_irqsave(&adc->lock, flags);
++
++ val = readb(adc->base + JZ_REG_ADC_ENABLE);
++ if (enabled)
++ val |= BIT(engine);
++ else
++ val &= BIT(engine);
++ writeb(val, adc->base + JZ_REG_ADC_ENABLE);
++
++ spin_unlock_irqrestore(&adc->lock, flags);
++}
++
++static int jz4740_adc_cell_enable(struct platform_device *pdev)
++{
++ struct jz4740_adc *adc = dev_get_drvdata(pdev->dev.parent);
++
++ jz4740_adc_clk_enable(adc);
++ jz4740_adc_set_enabled(adc, pdev->id, true);
++
++ return 0;
++}
++
++static int jz4740_adc_cell_disable(struct platform_device *pdev)
++{
++ struct jz4740_adc *adc = dev_get_drvdata(pdev->dev.parent);
++
++ jz4740_adc_set_enabled(adc, pdev->id, false);
++ jz4740_adc_clk_disable(adc);
++
++ return 0;
++}
++
++int jz4740_adc_set_config(struct device *dev, uint32_t mask, uint32_t val)
++{
++ struct jz4740_adc *adc = dev_get_drvdata(dev);
++ unsigned long flags;
++ uint32_t cfg;
++
++ if (!adc)
++ return -ENODEV;
++
++ spin_lock_irqsave(&adc->lock, flags);
++
++ cfg = readl(adc->base + JZ_REG_ADC_CFG);
++
++ cfg &= ~mask;
++ cfg |= val;
++
++ writel(cfg, adc->base + JZ_REG_ADC_CFG);
++
++ spin_unlock_irqrestore(&adc->lock, flags);
++
++ return 0;
++}
++EXPORT_SYMBOL_GPL(jz4740_adc_set_config);
++
++static struct resource jz4740_hwmon_resources[] = {
++ {
++ .start = JZ_ADC_IRQ_ADCIN,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .start = JZ_REG_ADC_HWMON_BASE,
++ .end = JZ_REG_ADC_HWMON_BASE + 3,
++ .flags = IORESOURCE_MEM,
++ },
++};
++
++static struct resource jz4740_battery_resources[] = {
++ {
++ .start = JZ_ADC_IRQ_BATTERY,
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .start = JZ_REG_ADC_BATTERY_BASE,
++ .end = JZ_REG_ADC_BATTERY_BASE + 3,
++ .flags = IORESOURCE_MEM,
++ },
++};
++
++const struct mfd_cell jz4740_adc_cells[] = {
++ {
++ .id = 0,
++ .name = "jz4740-hwmon",
++ .num_resources = ARRAY_SIZE(jz4740_hwmon_resources),
++ .resources = jz4740_hwmon_resources,
++ .platform_data = (void *)&jz4740_adc_cells[0],
++ .data_size = sizeof(struct mfd_cell),
++
++ .enable = jz4740_adc_cell_enable,
++ .disable = jz4740_adc_cell_disable,
++ },
++ {
++ .id = 1,
++ .name = "jz4740-battery",
++ .num_resources = ARRAY_SIZE(jz4740_battery_resources),
++ .resources = jz4740_battery_resources,
++ .platform_data = (void *)&jz4740_adc_cells[1],
++ .data_size = sizeof(struct mfd_cell),
++
++ .enable = jz4740_adc_cell_enable,
++ .disable = jz4740_adc_cell_disable,
++ },
++};
++
++static int __devinit jz4740_adc_probe(struct platform_device *pdev)
++{
++ int ret;
++ struct jz4740_adc *adc;
++ struct resource *mem_base;
++ int irq;
++
++ adc = kmalloc(sizeof(*adc), GFP_KERNEL);
++ if (!adc) {
++ dev_err(&pdev->dev, "Failed to allocate driver structure\n");
++ return -ENOMEM;
++ }
++
++ adc->irq = platform_get_irq(pdev, 0);
++ if (adc->irq < 0) {
++ ret = adc->irq;
++ dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
++ goto err_free;
++ }
++
++ adc->irq_base = platform_get_irq(pdev, 1);
++ if (adc->irq_base < 0) {
++ ret = adc->irq_base;
++ dev_err(&pdev->dev, "Failed to get irq base: %d\n", ret);
++ goto err_free;
++ }
++
++ mem_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!mem_base) {
++ ret = -ENOENT;
++ dev_err(&pdev->dev, "Failed to get platform mmio resource\n");
++ goto err_free;
++ }
++
++ /* Only request the shared registers for the MFD driver */
++ adc->mem = request_mem_region(mem_base->start, JZ_REG_ADC_STATUS,
++ pdev->name);
++ if (!adc->mem) {
++ ret = -EBUSY;
++ dev_err(&pdev->dev, "Failed to request mmio memory region\n");
++ goto err_free;
++ }
++
++ adc->base = ioremap_nocache(adc->mem->start, resource_size(adc->mem));
++ if (!adc->base) {
++ ret = -EBUSY;
++ dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
++ goto err_release_mem_region;
++ }
++
++ adc->clk = clk_get(&pdev->dev, "adc");
++ if (IS_ERR(adc->clk)) {
++ ret = PTR_ERR(adc->clk);
++ dev_err(&pdev->dev, "Failed to get clock: %d\n", ret);
++ goto err_iounmap;
++ }
++
++ spin_lock_init(&adc->lock);
++ atomic_set(&adc->clk_ref, 0);
++
++ platform_set_drvdata(pdev, adc);
++
++ for (irq = adc->irq_base; irq < adc->irq_base + 5; ++irq) {
++ set_irq_chip_data(irq, adc);
++ set_irq_chip_and_handler(irq, &jz4740_adc_irq_chip,
++ handle_level_irq);
++ }
++
++ set_irq_data(adc->irq, adc);
++ set_irq_chained_handler(adc->irq, jz4740_adc_irq_demux);
++
++ writeb(0x00, adc->base + JZ_REG_ADC_ENABLE);
++ writeb(0xff, adc->base + JZ_REG_ADC_CTRL);
++
++ ret = mfd_add_devices(&pdev->dev, 0, jz4740_adc_cells,
++ ARRAY_SIZE(jz4740_adc_cells), mem_base, adc->irq_base);
++ if (ret < 0)
++ goto err_clk_put;
++
++ return 0;
++
++err_clk_put:
++ clk_put(adc->clk);
++err_iounmap:
++ platform_set_drvdata(pdev, NULL);
++ iounmap(adc->base);
++err_release_mem_region:
++ release_mem_region(adc->mem->start, resource_size(adc->mem));
++err_free:
++ kfree(adc);
++
++ return ret;
++}
++
++static int __devexit jz4740_adc_remove(struct platform_device *pdev)
++{
++ struct jz4740_adc *adc = platform_get_drvdata(pdev);
++
++ mfd_remove_devices(&pdev->dev);
++
++ set_irq_data(adc->irq, NULL);
++ set_irq_chained_handler(adc->irq, NULL);
++
++ iounmap(adc->base);
++ release_mem_region(adc->mem->start, resource_size(adc->mem));
++
++ clk_put(adc->clk);
++
++ platform_set_drvdata(pdev, NULL);
++
++ kfree(adc);
++
++ return 0;
++}
++
++struct platform_driver jz4740_adc_driver = {
++ .probe = jz4740_adc_probe,
++ .remove = __devexit_p(jz4740_adc_remove),
++ .driver = {
++ .name = "jz4740-adc",
++ .owner = THIS_MODULE,
++ },
++};
++
++static int __init jz4740_adc_init(void)
++{
++ return platform_driver_register(&jz4740_adc_driver);
++}
++module_init(jz4740_adc_init);
++
++static void __exit jz4740_adc_exit(void)
++{
++ platform_driver_unregister(&jz4740_adc_driver);
++}
++module_exit(jz4740_adc_exit);
++
++MODULE_DESCRIPTION("JZ4740 SoC ADC driver");
++MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:jz4740-adc");
+--- /dev/null
++++ b/include/linux/jz4740-adc.h
+@@ -0,0 +1,32 @@
++
++#ifndef __LINUX_JZ4740_ADC
++#define __LINUX_JZ4740_ADC
++
++#include <linux/device.h>
++
++/*
++ * jz4740_adc_set_config - Configure a JZ4740 adc device
++ * @dev: Pointer to a jz4740-adc device
++ * @mask: Mask for the config value to be set
++ * @val: Value to be set
++ *
++ * This function can be used by the JZ4740 ADC mfd cells to configure their
++ * options in the shared config register.
++*/
++int jz4740_adc_set_config(struct device *dev, uint32_t mask, uint32_t val);
++
++#define JZ_ADC_CONFIG_SPZZ BIT(31)
++#define JZ_ADC_CONFIG_EX_IN BIT(30)
++#define JZ_ADC_CONFIG_DNUM_MASK (0x7 << 16)
++#define JZ_ADC_CONFIG_DMA_ENABLE BIT(15)
++#define JZ_ADC_CONFIG_XYZ_MASK (0x2 << 13)
++#define JZ_ADC_CONFIG_SAMPLE_NUM_MASK (0x7 << 10)
++#define JZ_ADC_CONFIG_CLKDIV_MASK (0xf << 5)
++#define JZ_ADC_CONFIG_BAT_MB BIT(4)
++
++#define JZ_ADC_CONFIG_DNUM(dnum) ((dnum) << 16)
++#define JZ_ADC_CONFIG_XYZ_OFFSET(dnum) ((xyz) << 13)
++#define JZ_ADC_CONFIG_SAMPLE_NUM(x) ((x) << 10)
++#define JZ_ADC_CONFIG_CLKDIV(div) ((div) << 5)
++
++#endif
--- /dev/null
+From 34e75141dfd8edae48030b61741c294fd0f952b1 Mon Sep 17 00:00:00 2001
+From: Lars-Peter Clausen <lars@metafoo.de>
+Date: Thu, 15 Jul 2010 20:06:04 +0000
+Subject: [PATCH] MMC: Add support for the controller on JZ4740 SoCs.
+
+Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
+Acked-by: Matt Fleming <matt@console-pimps.org>
+Cc: Andrew Morton <akpm@linux-foundation.org>
+Cc: Matt Fleming <matt@console-pimps.org>
+Cc: linux-mmc@vger.kernel.org
+Cc: linux-mips@linux-mips.org
+Cc: linux-kernel@vger.kernel.org
+Patchwork: https://patchwork.linux-mips.org/patch/1463/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/include/asm/mach-jz4740/jz4740_mmc.h | 15 +
+ drivers/mmc/host/Kconfig | 9 +
+ drivers/mmc/host/Makefile | 1 +
+ drivers/mmc/host/jz4740_mmc.c | 1033 ++++++++++++++++++++++++
+ 4 files changed, 1058 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/include/asm/mach-jz4740/jz4740_mmc.h
+ create mode 100644 drivers/mmc/host/jz4740_mmc.c
+
+--- /dev/null
++++ b/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h
+@@ -0,0 +1,15 @@
++#ifndef __LINUX_MMC_JZ4740_MMC
++#define __LINUX_MMC_JZ4740_MMC
++
++struct jz4740_mmc_platform_data {
++ int gpio_power;
++ int gpio_card_detect;
++ int gpio_read_only;
++ unsigned card_detect_active_low:1;
++ unsigned read_only_active_low:1;
++ unsigned power_active_low:1;
++
++ unsigned data_1bit:1;
++};
++
++#endif
+--- a/drivers/mmc/host/Kconfig
++++ b/drivers/mmc/host/Kconfig
+@@ -457,3 +457,12 @@ config MMC_SH_MMCIF
+ This selects the MMC Host Interface controler (MMCIF).
+
+ This driver supports MMCIF in sh7724/sh7757/sh7372.
++
++config MMC_JZ4740
++ tristate "JZ4740 SD/Multimedia Card Interface support"
++ depends on MACH_JZ4740
++ help
++ This selects support for the SD/MMC controller on Ingenic JZ4740
++ SoCs.
++ If you have a board based on such a SoC and with a SD/MMC slot,
++ say Y or M here.
+--- a/drivers/mmc/host/Makefile
++++ b/drivers/mmc/host/Makefile
+@@ -37,6 +37,7 @@ obj-$(CONFIG_MMC_VIA_SDMMC) += via-sdmmc
+ obj-$(CONFIG_GPIOMMC) += gpiommc.o
+ obj-$(CONFIG_SDH_BFIN) += bfin_sdh.o
+ obj-$(CONFIG_MMC_SH_MMCIF) += sh_mmcif.o
++obj-$(CONFIG_MMC_JZ4740) += jz4740_mmc.o
+
+ obj-$(CONFIG_MMC_SDHCI_OF) += sdhci-of.o
+ sdhci-of-y := sdhci-of-core.o
+--- /dev/null
++++ b/drivers/mmc/host/jz4740_mmc.c
+@@ -0,0 +1,1033 @@
++/*
++ * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
++ * JZ4740 SD/MMC controller driver
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/mmc/host.h>
++#include <linux/io.h>
++#include <linux/irq.h>
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/delay.h>
++#include <linux/scatterlist.h>
++#include <linux/clk.h>
++
++#include <linux/bitops.h>
++#include <linux/gpio.h>
++#include <asm/mach-jz4740/gpio.h>
++#include <asm/cacheflush.h>
++#include <linux/dma-mapping.h>
++
++#include <asm/mach-jz4740/jz4740_mmc.h>
++
++#define JZ_REG_MMC_STRPCL 0x00
++#define JZ_REG_MMC_STATUS 0x04
++#define JZ_REG_MMC_CLKRT 0x08
++#define JZ_REG_MMC_CMDAT 0x0C
++#define JZ_REG_MMC_RESTO 0x10
++#define JZ_REG_MMC_RDTO 0x14
++#define JZ_REG_MMC_BLKLEN 0x18
++#define JZ_REG_MMC_NOB 0x1C
++#define JZ_REG_MMC_SNOB 0x20
++#define JZ_REG_MMC_IMASK 0x24
++#define JZ_REG_MMC_IREG 0x28
++#define JZ_REG_MMC_CMD 0x2C
++#define JZ_REG_MMC_ARG 0x30
++#define JZ_REG_MMC_RESP_FIFO 0x34
++#define JZ_REG_MMC_RXFIFO 0x38
++#define JZ_REG_MMC_TXFIFO 0x3C
++
++#define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7)
++#define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6)
++#define JZ_MMC_STRPCL_START_READWAIT BIT(5)
++#define JZ_MMC_STRPCL_STOP_READWAIT BIT(4)
++#define JZ_MMC_STRPCL_RESET BIT(3)
++#define JZ_MMC_STRPCL_START_OP BIT(2)
++#define JZ_MMC_STRPCL_CLOCK_CONTROL (BIT(1) | BIT(0))
++#define JZ_MMC_STRPCL_CLOCK_STOP BIT(0)
++#define JZ_MMC_STRPCL_CLOCK_START BIT(1)
++
++
++#define JZ_MMC_STATUS_IS_RESETTING BIT(15)
++#define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14)
++#define JZ_MMC_STATUS_PRG_DONE BIT(13)
++#define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12)
++#define JZ_MMC_STATUS_END_CMD_RES BIT(11)
++#define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10)
++#define JZ_MMC_STATUS_IS_READWAIT BIT(9)
++#define JZ_MMC_STATUS_CLK_EN BIT(8)
++#define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7)
++#define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6)
++#define JZ_MMC_STATUS_CRC_RES_ERR BIT(5)
++#define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4)
++#define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3)
++#define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2)
++#define JZ_MMC_STATUS_TIMEOUT_RES BIT(1)
++#define JZ_MMC_STATUS_TIMEOUT_READ BIT(0)
++
++#define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0))
++#define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2))
++
++
++#define JZ_MMC_CMDAT_IO_ABORT BIT(11)
++#define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10)
++#define JZ_MMC_CMDAT_DMA_EN BIT(8)
++#define JZ_MMC_CMDAT_INIT BIT(7)
++#define JZ_MMC_CMDAT_BUSY BIT(6)
++#define JZ_MMC_CMDAT_STREAM BIT(5)
++#define JZ_MMC_CMDAT_WRITE BIT(4)
++#define JZ_MMC_CMDAT_DATA_EN BIT(3)
++#define JZ_MMC_CMDAT_RESPONSE_FORMAT (BIT(2) | BIT(1) | BIT(0))
++#define JZ_MMC_CMDAT_RSP_R1 1
++#define JZ_MMC_CMDAT_RSP_R2 2
++#define JZ_MMC_CMDAT_RSP_R3 3
++
++#define JZ_MMC_IRQ_SDIO BIT(7)
++#define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6)
++#define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5)
++#define JZ_MMC_IRQ_END_CMD_RES BIT(2)
++#define JZ_MMC_IRQ_PRG_DONE BIT(1)
++#define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0)
++
++
++#define JZ_MMC_CLK_RATE 24000000
++
++enum jz4740_mmc_state {
++ JZ4740_MMC_STATE_READ_RESPONSE,
++ JZ4740_MMC_STATE_TRANSFER_DATA,
++ JZ4740_MMC_STATE_SEND_STOP,
++ JZ4740_MMC_STATE_DONE,
++};
++
++struct jz4740_mmc_host {
++ struct mmc_host *mmc;
++ struct platform_device *pdev;
++ struct jz4740_mmc_platform_data *pdata;
++ struct clk *clk;
++
++ int irq;
++ int card_detect_irq;
++
++ struct resource *mem;
++ void __iomem *base;
++ struct mmc_request *req;
++ struct mmc_command *cmd;
++
++ unsigned long waiting;
++
++ uint32_t cmdat;
++
++ uint16_t irq_mask;
++
++ spinlock_t lock;
++
++ struct timer_list timeout_timer;
++ struct sg_mapping_iter miter;
++ enum jz4740_mmc_state state;
++};
++
++static void jz4740_mmc_set_irq_enabled(struct jz4740_mmc_host *host,
++ unsigned int irq, bool enabled)
++{
++ unsigned long flags;
++
++ spin_lock_irqsave(&host->lock, flags);
++ if (enabled)
++ host->irq_mask &= ~irq;
++ else
++ host->irq_mask |= irq;
++ spin_unlock_irqrestore(&host->lock, flags);
++
++ writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK);
++}
++
++static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host,
++ bool start_transfer)
++{
++ uint16_t val = JZ_MMC_STRPCL_CLOCK_START;
++
++ if (start_transfer)
++ val |= JZ_MMC_STRPCL_START_OP;
++
++ writew(val, host->base + JZ_REG_MMC_STRPCL);
++}
++
++static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host)
++{
++ uint32_t status;
++ unsigned int timeout = 1000;
++
++ writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL);
++ do {
++ status = readl(host->base + JZ_REG_MMC_STATUS);
++ } while (status & JZ_MMC_STATUS_CLK_EN && --timeout);
++}
++
++static void jz4740_mmc_reset(struct jz4740_mmc_host *host)
++{
++ uint32_t status;
++ unsigned int timeout = 1000;
++
++ writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL);
++ udelay(10);
++ do {
++ status = readl(host->base + JZ_REG_MMC_STATUS);
++ } while (status & JZ_MMC_STATUS_IS_RESETTING && --timeout);
++}
++
++static void jz4740_mmc_request_done(struct jz4740_mmc_host *host)
++{
++ struct mmc_request *req;
++
++ req = host->req;
++ host->req = NULL;
++
++ mmc_request_done(host->mmc, req);
++}
++
++static unsigned int jz4740_mmc_poll_irq(struct jz4740_mmc_host *host,
++ unsigned int irq)
++{
++ unsigned int timeout = 0x800;
++ uint16_t status;
++
++ do {
++ status = readw(host->base + JZ_REG_MMC_IREG);
++ } while (!(status & irq) && --timeout);
++
++ if (timeout == 0) {
++ set_bit(0, &host->waiting);
++ mod_timer(&host->timeout_timer, jiffies + 5*HZ);
++ jz4740_mmc_set_irq_enabled(host, irq, true);
++ return true;
++ }
++
++ return false;
++}
++
++static void jz4740_mmc_transfer_check_state(struct jz4740_mmc_host *host,
++ struct mmc_data *data)
++{
++ int status;
++
++ status = readl(host->base + JZ_REG_MMC_STATUS);
++ if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK) {
++ if (status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) {
++ host->req->cmd->error = -ETIMEDOUT;
++ data->error = -ETIMEDOUT;
++ } else {
++ host->req->cmd->error = -EIO;
++ data->error = -EIO;
++ }
++ }
++}
++
++static bool jz4740_mmc_write_data(struct jz4740_mmc_host *host,
++ struct mmc_data *data)
++{
++ struct sg_mapping_iter *miter = &host->miter;
++ void __iomem *fifo_addr = host->base + JZ_REG_MMC_TXFIFO;
++ uint32_t *buf;
++ bool timeout;
++ size_t i, j;
++
++ while (sg_miter_next(miter)) {
++ buf = miter->addr;
++ i = miter->length / 4;
++ j = i / 8;
++ i = i & 0x7;
++ while (j) {
++ timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
++ if (unlikely(timeout))
++ goto poll_timeout;
++
++ writel(buf[0], fifo_addr);
++ writel(buf[1], fifo_addr);
++ writel(buf[2], fifo_addr);
++ writel(buf[3], fifo_addr);
++ writel(buf[4], fifo_addr);
++ writel(buf[5], fifo_addr);
++ writel(buf[6], fifo_addr);
++ writel(buf[7], fifo_addr);
++ buf += 8;
++ --j;
++ }
++ if (unlikely(i)) {
++ timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
++ if (unlikely(timeout))
++ goto poll_timeout;
++
++ while (i) {
++ writel(*buf, fifo_addr);
++ ++buf;
++ --i;
++ }
++ }
++ data->bytes_xfered += miter->length;
++ }
++ sg_miter_stop(miter);
++
++ return false;
++
++poll_timeout:
++ miter->consumed = (void *)buf - miter->addr;
++ data->bytes_xfered += miter->consumed;
++ sg_miter_stop(miter);
++
++ return true;
++}
++
++static bool jz4740_mmc_read_data(struct jz4740_mmc_host *host,
++ struct mmc_data *data)
++{
++ struct sg_mapping_iter *miter = &host->miter;
++ void __iomem *fifo_addr = host->base + JZ_REG_MMC_RXFIFO;
++ uint32_t *buf;
++ uint32_t d;
++ uint16_t status;
++ size_t i, j;
++ unsigned int timeout;
++
++ while (sg_miter_next(miter)) {
++ buf = miter->addr;
++ i = miter->length;
++ j = i / 32;
++ i = i & 0x1f;
++ while (j) {
++ timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
++ if (unlikely(timeout))
++ goto poll_timeout;
++
++ buf[0] = readl(fifo_addr);
++ buf[1] = readl(fifo_addr);
++ buf[2] = readl(fifo_addr);
++ buf[3] = readl(fifo_addr);
++ buf[4] = readl(fifo_addr);
++ buf[5] = readl(fifo_addr);
++ buf[6] = readl(fifo_addr);
++ buf[7] = readl(fifo_addr);
++
++ buf += 8;
++ --j;
++ }
++
++ if (unlikely(i)) {
++ timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
++ if (unlikely(timeout))
++ goto poll_timeout;
++
++ while (i >= 4) {
++ *buf++ = readl(fifo_addr);
++ i -= 4;
++ }
++ if (unlikely(i > 0)) {
++ d = readl(fifo_addr);
++ memcpy(buf, &d, i);
++ }
++ }
++ data->bytes_xfered += miter->length;
++
++ /* This can go away once MIPS implements
++ * flush_kernel_dcache_page */
++ flush_dcache_page(miter->page);
++ }
++ sg_miter_stop(miter);
++
++ /* For whatever reason there is sometime one word more in the fifo then
++ * requested */
++ timeout = 1000;
++ status = readl(host->base + JZ_REG_MMC_STATUS);
++ while (!(status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) && --timeout) {
++ d = readl(fifo_addr);
++ status = readl(host->base + JZ_REG_MMC_STATUS);
++ }
++
++ return false;
++
++poll_timeout:
++ miter->consumed = (void *)buf - miter->addr;
++ data->bytes_xfered += miter->consumed;
++ sg_miter_stop(miter);
++
++ return true;
++}
++
++static void jz4740_mmc_timeout(unsigned long data)
++{
++ struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)data;
++
++ if (!test_and_clear_bit(0, &host->waiting))
++ return;
++
++ jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, false);
++
++ host->req->cmd->error = -ETIMEDOUT;
++ jz4740_mmc_request_done(host);
++}
++
++static void jz4740_mmc_read_response(struct jz4740_mmc_host *host,
++ struct mmc_command *cmd)
++{
++ int i;
++ uint16_t tmp;
++ void __iomem *fifo_addr = host->base + JZ_REG_MMC_RESP_FIFO;
++
++ if (cmd->flags & MMC_RSP_136) {
++ tmp = readw(fifo_addr);
++ for (i = 0; i < 4; ++i) {
++ cmd->resp[i] = tmp << 24;
++ tmp = readw(fifo_addr);
++ cmd->resp[i] |= tmp << 8;
++ tmp = readw(fifo_addr);
++ cmd->resp[i] |= tmp >> 8;
++ }
++ } else {
++ cmd->resp[0] = readw(fifo_addr) << 24;
++ cmd->resp[0] |= readw(fifo_addr) << 8;
++ cmd->resp[0] |= readw(fifo_addr) & 0xff;
++ }
++}
++
++static void jz4740_mmc_send_command(struct jz4740_mmc_host *host,
++ struct mmc_command *cmd)
++{
++ uint32_t cmdat = host->cmdat;
++
++ host->cmdat &= ~JZ_MMC_CMDAT_INIT;
++ jz4740_mmc_clock_disable(host);
++
++ host->cmd = cmd;
++
++ if (cmd->flags & MMC_RSP_BUSY)
++ cmdat |= JZ_MMC_CMDAT_BUSY;
++
++ switch (mmc_resp_type(cmd)) {
++ case MMC_RSP_R1B:
++ case MMC_RSP_R1:
++ cmdat |= JZ_MMC_CMDAT_RSP_R1;
++ break;
++ case MMC_RSP_R2:
++ cmdat |= JZ_MMC_CMDAT_RSP_R2;
++ break;
++ case MMC_RSP_R3:
++ cmdat |= JZ_MMC_CMDAT_RSP_R3;
++ break;
++ default:
++ break;
++ }
++
++ if (cmd->data) {
++ cmdat |= JZ_MMC_CMDAT_DATA_EN;
++ if (cmd->data->flags & MMC_DATA_WRITE)
++ cmdat |= JZ_MMC_CMDAT_WRITE;
++ if (cmd->data->flags & MMC_DATA_STREAM)
++ cmdat |= JZ_MMC_CMDAT_STREAM;
++
++ writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN);
++ writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB);
++ }
++
++ writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD);
++ writel(cmd->arg, host->base + JZ_REG_MMC_ARG);
++ writel(cmdat, host->base + JZ_REG_MMC_CMDAT);
++
++ jz4740_mmc_clock_enable(host, 1);
++}
++
++static void jz_mmc_prepare_data_transfer(struct jz4740_mmc_host *host)
++{
++ struct mmc_command *cmd = host->req->cmd;
++ struct mmc_data *data = cmd->data;
++ int direction;
++
++ if (data->flags & MMC_DATA_READ)
++ direction = SG_MITER_TO_SG;
++ else
++ direction = SG_MITER_FROM_SG;
++
++ sg_miter_start(&host->miter, data->sg, data->sg_len, direction);
++}
++
++
++static irqreturn_t jz_mmc_irq_worker(int irq, void *devid)
++{
++ struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)devid;
++ struct mmc_command *cmd = host->req->cmd;
++ struct mmc_request *req = host->req;
++ bool timeout = false;
++
++ if (cmd->error)
++ host->state = JZ4740_MMC_STATE_DONE;
++
++ switch (host->state) {
++ case JZ4740_MMC_STATE_READ_RESPONSE:
++ if (cmd->flags & MMC_RSP_PRESENT)
++ jz4740_mmc_read_response(host, cmd);
++
++ if (!cmd->data)
++ break;
++
++ jz_mmc_prepare_data_transfer(host);
++
++ case JZ4740_MMC_STATE_TRANSFER_DATA:
++ if (cmd->data->flags & MMC_DATA_READ)
++ timeout = jz4740_mmc_read_data(host, cmd->data);
++ else
++ timeout = jz4740_mmc_write_data(host, cmd->data);
++
++ if (unlikely(timeout)) {
++ host->state = JZ4740_MMC_STATE_TRANSFER_DATA;
++ break;
++ }
++
++ jz4740_mmc_transfer_check_state(host, cmd->data);
++
++ timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_DATA_TRAN_DONE);
++ if (unlikely(timeout)) {
++ host->state = JZ4740_MMC_STATE_SEND_STOP;
++ break;
++ }
++ writew(JZ_MMC_IRQ_DATA_TRAN_DONE, host->base + JZ_REG_MMC_IREG);
++
++ case JZ4740_MMC_STATE_SEND_STOP:
++ if (!req->stop)
++ break;
++
++ jz4740_mmc_send_command(host, req->stop);
++
++ timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_PRG_DONE);
++ if (timeout) {
++ host->state = JZ4740_MMC_STATE_DONE;
++ break;
++ }
++ case JZ4740_MMC_STATE_DONE:
++ break;
++ }
++
++ if (!timeout)
++ jz4740_mmc_request_done(host);
++
++ return IRQ_HANDLED;
++}
++
++static irqreturn_t jz_mmc_irq(int irq, void *devid)
++{
++ struct jz4740_mmc_host *host = devid;
++ struct mmc_command *cmd = host->cmd;
++ uint16_t irq_reg, status, tmp;
++
++ irq_reg = readw(host->base + JZ_REG_MMC_IREG);
++
++ tmp = irq_reg;
++ irq_reg &= ~host->irq_mask;
++
++ tmp &= ~(JZ_MMC_IRQ_TXFIFO_WR_REQ | JZ_MMC_IRQ_RXFIFO_RD_REQ |
++ JZ_MMC_IRQ_PRG_DONE | JZ_MMC_IRQ_DATA_TRAN_DONE);
++
++ if (tmp != irq_reg)
++ writew(tmp & ~irq_reg, host->base + JZ_REG_MMC_IREG);
++
++ if (irq_reg & JZ_MMC_IRQ_SDIO) {
++ writew(JZ_MMC_IRQ_SDIO, host->base + JZ_REG_MMC_IREG);
++ mmc_signal_sdio_irq(host->mmc);
++ irq_reg &= ~JZ_MMC_IRQ_SDIO;
++ }
++
++ if (host->req && cmd && irq_reg) {
++ if (test_and_clear_bit(0, &host->waiting)) {
++ del_timer(&host->timeout_timer);
++
++ status = readl(host->base + JZ_REG_MMC_STATUS);
++
++ if (status & JZ_MMC_STATUS_TIMEOUT_RES) {
++ cmd->error = -ETIMEDOUT;
++ } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) {
++ cmd->error = -EIO;
++ } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR |
++ JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
++ if (cmd->data)
++ cmd->data->error = -EIO;
++ cmd->error = -EIO;
++ } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR |
++ JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
++ if (cmd->data)
++ cmd->data->error = -EIO;
++ cmd->error = -EIO;
++ }
++
++ jz4740_mmc_set_irq_enabled(host, irq_reg, false);
++ writew(irq_reg, host->base + JZ_REG_MMC_IREG);
++
++ return IRQ_WAKE_THREAD;
++ }
++ }
++
++ return IRQ_HANDLED;
++}
++
++static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate)
++{
++ int div = 0;
++ int real_rate;
++
++ jz4740_mmc_clock_disable(host);
++ clk_set_rate(host->clk, JZ_MMC_CLK_RATE);
++
++ real_rate = clk_get_rate(host->clk);
++
++ while (real_rate > rate && div < 7) {
++ ++div;
++ real_rate >>= 1;
++ }
++
++ writew(div, host->base + JZ_REG_MMC_CLKRT);
++ return real_rate;
++}
++
++static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
++{
++ struct jz4740_mmc_host *host = mmc_priv(mmc);
++
++ host->req = req;
++
++ writew(0xffff, host->base + JZ_REG_MMC_IREG);
++
++ writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG);
++ jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, true);
++
++ host->state = JZ4740_MMC_STATE_READ_RESPONSE;
++ set_bit(0, &host->waiting);
++ mod_timer(&host->timeout_timer, jiffies + 5*HZ);
++ jz4740_mmc_send_command(host, req->cmd);
++}
++
++static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
++{
++ struct jz4740_mmc_host *host = mmc_priv(mmc);
++ if (ios->clock)
++ jz4740_mmc_set_clock_rate(host, ios->clock);
++
++ switch (ios->power_mode) {
++ case MMC_POWER_UP:
++ jz4740_mmc_reset(host);
++ if (gpio_is_valid(host->pdata->gpio_power))
++ gpio_set_value(host->pdata->gpio_power,
++ !host->pdata->power_active_low);
++ host->cmdat |= JZ_MMC_CMDAT_INIT;
++ clk_enable(host->clk);
++ break;
++ case MMC_POWER_ON:
++ break;
++ default:
++ if (gpio_is_valid(host->pdata->gpio_power))
++ gpio_set_value(host->pdata->gpio_power,
++ host->pdata->power_active_low);
++ clk_disable(host->clk);
++ break;
++ }
++
++ switch (ios->bus_width) {
++ case MMC_BUS_WIDTH_1:
++ host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
++ break;
++ case MMC_BUS_WIDTH_4:
++ host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
++ break;
++ default:
++ break;
++ }
++}
++
++static int jz4740_mmc_get_ro(struct mmc_host *mmc)
++{
++ struct jz4740_mmc_host *host = mmc_priv(mmc);
++ if (!gpio_is_valid(host->pdata->gpio_read_only))
++ return -ENOSYS;
++
++ return gpio_get_value(host->pdata->gpio_read_only) ^
++ host->pdata->read_only_active_low;
++}
++
++static int jz4740_mmc_get_cd(struct mmc_host *mmc)
++{
++ struct jz4740_mmc_host *host = mmc_priv(mmc);
++ if (!gpio_is_valid(host->pdata->gpio_card_detect))
++ return -ENOSYS;
++
++ return gpio_get_value(host->pdata->gpio_card_detect) ^
++ host->pdata->card_detect_active_low;
++}
++
++static irqreturn_t jz4740_mmc_card_detect_irq(int irq, void *devid)
++{
++ struct jz4740_mmc_host *host = devid;
++
++ mmc_detect_change(host->mmc, HZ / 2);
++
++ return IRQ_HANDLED;
++}
++
++static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
++{
++ struct jz4740_mmc_host *host = mmc_priv(mmc);
++ jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_SDIO, enable);
++}
++
++static const struct mmc_host_ops jz4740_mmc_ops = {
++ .request = jz4740_mmc_request,
++ .set_ios = jz4740_mmc_set_ios,
++ .get_ro = jz4740_mmc_get_ro,
++ .get_cd = jz4740_mmc_get_cd,
++ .enable_sdio_irq = jz4740_mmc_enable_sdio_irq,
++};
++
++static const struct jz_gpio_bulk_request jz4740_mmc_pins[] = {
++ JZ_GPIO_BULK_PIN(MSC_CMD),
++ JZ_GPIO_BULK_PIN(MSC_CLK),
++ JZ_GPIO_BULK_PIN(MSC_DATA0),
++ JZ_GPIO_BULK_PIN(MSC_DATA1),
++ JZ_GPIO_BULK_PIN(MSC_DATA2),
++ JZ_GPIO_BULK_PIN(MSC_DATA3),
++};
++
++static int __devinit jz4740_mmc_request_gpio(struct device *dev, int gpio,
++ const char *name, bool output, int value)
++{
++ int ret;
++
++ if (!gpio_is_valid(gpio))
++ return 0;
++
++ ret = gpio_request(gpio, name);
++ if (ret) {
++ dev_err(dev, "Failed to request %s gpio: %d\n", name, ret);
projects / openwrt / svn-archive / archive.git / commitdiff