[omap]: switch to 3.12, enable support for AM33xx/OMAP3
authorImre Kaloz <kaloz@openwrt.org>
Fri, 8 Nov 2013 12:44:38 +0000 (12:44 +0000)
committerImre Kaloz <kaloz@openwrt.org>
Fri, 8 Nov 2013 12:44:38 +0000 (12:44 +0000)
Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
SVN-Revision: 38692

package/kernel/linux/modules/crypto.mk
package/kernel/linux/modules/usb.mk
target/linux/omap/Makefile
target/linux/omap/base-files/etc/inittab
target/linux/omap/config-default
target/linux/omap/image/Makefile
target/linux/omap/image/boot.script
target/linux/omap/patches-3.12/001-ti_git.patch [new file with mode: 0644]

index bb5bb28..7996d03 100644 (file)
@@ -205,6 +205,28 @@ endef
 $(eval $(call KernelPackage,crypto-hw-ppc4xx))
 
 
+define KernelPackage/crypto-hw-omap
+  TITLE:=TI OMAP hardware crypto modules
+  DEPENDS:=@TARGET_omap4
+  KCONFIG:= \
+       CONFIG_CRYPTO_DEV_OMAP_AES \
+       CONFIG_CRYPTO_DEV_OMAP_DES \
+       CONFIG_CRYPTO_DEV_OMAP_SHAM
+  FILES:= \
+       $(LINUX_DIR)/drivers/crypto/omap-aes.ko \
+       $(LINUX_DIR)/drivers/crypto/omap-des.ko \
+       $(LINUX_DIR)/drivers/crypto/omap-sham.ko
+  AUTOLOAD:=$(call AutoLoad,90,omap-aes omap-des omap-sham)
+  $(call AddDepends/crypto,+kmod-crypto-manager +kmod-crypto-hash)
+endef
+
+define KernelPackage/crypto-hw-omap/description
+  Kernel support for the TI OMAP HW crypto engine.
+endef
+
+$(eval $(call KernelPackage,crypto-hw-omap))
+
+
 define KernelPackage/crypto-aes
   TITLE:=AES cipher CryptoAPI module
   KCONFIG:=CONFIG_CRYPTO_AES CONFIG_CRYPTO_AES_586
index bec9f6b..e1611aa 100644 (file)
@@ -112,6 +112,7 @@ define KernelPackage/usb-ohci
        CONFIG_USB_OHCI_ATH79=y \
        CONFIG_USB_OHCI_BCM63XX=y \
        CONFIG_USB_OCTEON_OHCI=y \
+       CONFIG_USB_OHCI_HCD_OMAP3=y \
        CONFIG_USB_OHCI_HCD_PLATFORM=y
   FILES:=$(LINUX_DIR)/drivers/usb/host/ohci-hcd.ko
   AUTOLOAD:=$(call AutoLoad,50,ohci-hcd,1)
index 3a62911..78361fc 100644 (file)
@@ -13,11 +13,11 @@ FEATURES:=usb targz audio display
 CPU_TYPE:=cortex-a9
 CPU_SUBTYPE:=vfpv3
 
-LINUX_VERSION:=3.3.8
+LINUX_VERSION:=3.12
 
 MAINTAINER:=Imre Kaloz <kaloz@openwrt.org>
 
-KERNELNAME:="uImage"
+KERNELNAME:="zImage dtbs"
 
 DEFAULT_PACKAGES += uboot-omap-am335x_evm uboot-omap-omap3_beagle uboot-omap-omap3_overo uboot-omap-omap4_panda
 
index cc6c31a..502c6f8 100644 (file)
@@ -1,4 +1,5 @@
 ::sysinit:/etc/init.d/rcS S boot
 ::shutdown:/etc/init.d/rcS K shutdown
+ttyO0::askfirst:/bin/ash --login
 ttyO2::askfirst:/bin/ash --login
 tty1::askfirst:/bin/ash --login
index d51ebc4..a0cc53e 100644 (file)
@@ -1,39 +1,67 @@
 CONFIG_ALIGNMENT_TRAP=y
+CONFIG_AM335X_CONTROL_USB=y
+CONFIG_AM335X_PHY_USB=y
 # CONFIG_APM_EMULATION is not set
 CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
+CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+CONFIG_ARCH_HAS_BANDGAP=y
 CONFIG_ARCH_HAS_BARRIERS=y
 CONFIG_ARCH_HAS_CPUFREQ=y
-CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
 CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
 CONFIG_ARCH_HAS_OPP=y
-CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+# CONFIG_ARCH_MULTI_CPU_AUTO is not set
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y
+CONFIG_ARCH_NR_GPIO=192
 CONFIG_ARCH_OMAP=y
-# CONFIG_ARCH_OMAP1 is not set
-# CONFIG_ARCH_OMAP2 is not set
 CONFIG_ARCH_OMAP2PLUS=y
 CONFIG_ARCH_OMAP2PLUS_TYPICAL=y
-# CONFIG_ARCH_OMAP3 is not set
+CONFIG_ARCH_OMAP3=y
 CONFIG_ARCH_OMAP4=y
 CONFIG_ARCH_REQUIRE_GPIOLIB=y
 # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
 # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
-# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
 CONFIG_ARM=y
+# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set
 CONFIG_ARM_CPU_SUSPEND=y
 CONFIG_ARM_ERRATA_720789=y
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_ARM_ERRATA_775420=y
 CONFIG_ARM_GIC=y
+# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set
 CONFIG_ARM_L1_CACHE_SHIFT=6
 CONFIG_ARM_L1_CACHE_SHIFT_6=y
 # CONFIG_ARM_LPAE is not set
 CONFIG_ARM_NR_BANKS=8
+CONFIG_ARM_OMAP2PLUS_CPUFREQ=y
 CONFIG_ARM_PATCH_PHYS_VIRT=y
 CONFIG_ARM_THUMB=y
 # CONFIG_ARM_THUMBEE is not set
-# CONFIG_ATH_COMMON is not set
-# CONFIG_ATMEL_PWM is not set
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_AT803X_PHY=y
+# CONFIG_ATH_CARDS is not set
+CONFIG_AUTO_ZRELADDR=y
 CONFIG_AVERAGE=y
-CONFIG_BCMA_POSSIBLE=y
+# CONFIG_BACKLIGHT_ADP8860 is not set
+# CONFIG_BACKLIGHT_ADP8870 is not set
+# CONFIG_BACKLIGHT_BD6107 is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+# CONFIG_BACKLIGHT_GPIO is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_BACKLIGHT_LV5207LP is not set
+# CONFIG_BACKLIGHT_PANDORA is not set
+CONFIG_BACKLIGHT_PWM=y
+# CONFIG_BACKLIGHT_TPS65217 is not set
+CONFIG_BCH=y
+CONFIG_BCH_CONST_M=13
 CONFIG_BOUNCE=y
 CONFIG_CACHE_L2X0=y
 CONFIG_CACHE_PL310=y
@@ -46,6 +74,11 @@ CONFIG_CFG80211_DEFAULT_PS=y
 CONFIG_CFG80211_WEXT=y
 CONFIG_CLKDEV_LOOKUP=y
 CONFIG_CLKSRC_MMIO=y
+CONFIG_CLKSRC_OF=y
+# CONFIG_CLK_TWL6040 is not set
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="console=ttyO0,115200n8"
+CONFIG_COMMON_CLK=y
 CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_CPU_32v6K=y
 CONFIG_CPU_32v7=y
@@ -56,110 +89,196 @@ CONFIG_CPU_CACHE_VIPT=y
 CONFIG_CPU_COPY_V6=y
 CONFIG_CPU_CP15=y
 CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_FREQ=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_GOV_COMMON=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+CONFIG_CPU_FREQ_TABLE=y
 CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_HAS_PMU=y
 # CONFIG_CPU_ICACHE_DISABLE is not set
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
 CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
 CONFIG_CPU_RMAP=y
 CONFIG_CPU_TLB_V7=y
 CONFIG_CPU_V7=y
 CONFIG_CRC16=y
-CONFIG_CRYPTO_AES=m
-CONFIG_CRYPTO_ALGAPI=m
-CONFIG_CRYPTO_ALGAPI2=m
+# CONFIG_CROSSBAR is not set
 CONFIG_CRYPTO_ARC4=m
-# CONFIG_DEBUG_HIGHMEM is not set
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_BLKCIPHER2=m
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=m
+CONFIG_CRYPTO_WORKQUEUE=m
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DDR=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+# CONFIG_DEBUG_UART_8250 is not set
+# CONFIG_DEBUG_UART_PL01X is not set
 # CONFIG_DEBUG_USER is not set
-CONFIG_DECOMPRESS_LZMA=y
+# CONFIG_DISPLAY_DRA_EVM_ENCODER_TPD12S015 is not set
+# CONFIG_DISPLAY_ENCODER_SIL9022 is not set
+CONFIG_DISPLAY_PANEL_DPI=y
+CONFIG_DISPLAY_PANEL_DSI_CM=y
+# CONFIG_DISPLAY_PANEL_NEC_NL8048HL11 is not set
+CONFIG_DISPLAY_PANEL_SHARP_LS037V7DW01=y
+# CONFIG_DISPLAY_PANEL_SONY_ACX565AKM is not set
+# CONFIG_DISPLAY_PANEL_TFCS9700 is not set
+CONFIG_DMADEVICES=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OMAP=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DTC=y
 CONFIG_DUMMY_CONSOLE=y
-# CONFIG_DW_WATCHDOG is not set
+# CONFIG_DW_DMAC_CORE is not set
+CONFIG_EEPROM_AT24=y
 CONFIG_EXT4_FS=y
 CONFIG_FB=y
 CONFIG_FB_CFB_COPYAREA=y
 CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_CFB_REV_PIXELS_IN_BYTE=y
+CONFIG_FB_DA8XX=y
+# CONFIG_FB_DA8XX_TDA998X is not set
 CONFIG_FB_MODE_HELPERS=y
 CONFIG_FB_OMAP2=y
 CONFIG_FB_OMAP2_DEBUG_SUPPORT=y
 CONFIG_FB_OMAP2_NUM_FBS=3
-# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
-# CONFIG_FB_SM7XX is not set
-CONFIG_FB_TILEBLITTING=y
-# CONFIG_FB_WMT_GE_ROPS is not set
 CONFIG_FIRMWARE_EDID=y
 # CONFIG_FONTS is not set
 CONFIG_FONT_8x16=y
 CONFIG_FONT_8x8=y
+CONFIG_FONT_SUPPORT=y
+CONFIG_FORCE_MAX_ZONEORDER=12
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
 # CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
 CONFIG_FRAME_POINTER=y
+CONFIG_FREEZER=y
 CONFIG_FS_MBCACHE=y
 CONFIG_GENERIC_BUG=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
 CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_GPIO=y
+# CONFIG_GENERIC_CPUFREQ_CPU0 is not set
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IO=y
 CONFIG_GENERIC_IRQ_CHIP=y
 CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_NET_UTILS=y
 CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
 CONFIG_GPIOLIB=y
+CONFIG_GPIO_DEVRES=y
+CONFIG_GPIO_TPS65910=y
 CONFIG_GPIO_TWL4030=y
+# CONFIG_GPIO_TWL6040 is not set
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_HAS_DMA=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
-CONFIG_HAVE_AOUT=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
 CONFIG_HAVE_ARCH_KGDB=y
 CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
 CONFIG_HAVE_ARM_SCU=y
 CONFIG_HAVE_ARM_TWD=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_BPF_JIT=y
 CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
 CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
 CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
 CONFIG_HAVE_DYNAMIC_FTRACE=y
 CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
 CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
 CONFIG_HAVE_FUNCTION_TRACER=y
 CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IRQ_WORK=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
 CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZ4=y
 CONFIG_HAVE_KERNEL_LZMA=y
 CONFIG_HAVE_KERNEL_LZO=y
 CONFIG_HAVE_KERNEL_XZ=y
 CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_NET_DSA=y
 CONFIG_HAVE_OPROFILE=y
 CONFIG_HAVE_PERF_EVENTS=y
 CONFIG_HAVE_PROC_CPU=y
 CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_SCHED_CLOCK=y
 CONFIG_HAVE_SMP=y
-CONFIG_HAVE_SPARSE_IRQ=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_UID16=y
 CONFIG_HIGHMEM=y
 # CONFIG_HIGHPTE is not set
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HWMON=y
 CONFIG_HW_CONSOLE=y
-CONFIG_HZ=128
+CONFIG_HZ_FIXED=0
 CONFIG_I2C=y
 CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
 CONFIG_I2C_OMAP=y
 CONFIG_INITRAMFS_SOURCE=""
 CONFIG_INPUT=y
 CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_MATRIXKMAP=y
+CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_INPUT_TWL4030_PWRBUTTON=y
 # CONFIG_INPUT_TWL4030_VIBRA is not set
 # CONFIG_INPUT_TWL6040_VIBRA is not set
+CONFIG_IRQCHIP=y
 CONFIG_IRQ_DOMAIN=y
-# CONFIG_IWM is not set
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
 CONFIG_JBD2=y
 # CONFIG_KEYBOARD_GPIO is not set
-# CONFIG_KEYBOARD_OMAP4 is not set
 CONFIG_KEYBOARD_TWL4030=y
 CONFIG_KTIME_SCALAR=y
-# CONFIG_LEDS is not set
+# CONFIG_LCD_AMS369FG06 is not set
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_L4F00242T03 is not set
+# CONFIG_LCD_LD9040 is not set
+# CONFIG_LCD_LMS283GF05 is not set
+# CONFIG_LCD_LTV350QV is not set
+# CONFIG_LCD_PLATFORM is not set
+# CONFIG_LCD_S6E63M0 is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
 CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_PWM is not set
 # CONFIG_LEDS_REGULATOR is not set
-CONFIG_LOCAL_TIMERS=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
 CONFIG_LZO_COMPRESS=y
 CONFIG_LZO_DECOMPRESS=y
 CONFIG_MAC80211=m
@@ -174,191 +293,307 @@ CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
 CONFIG_MAC80211_RC_MINSTREL=y
 CONFIG_MAC80211_RC_MINSTREL_HT=y
 # CONFIG_MAC80211_RC_PID is not set
-CONFIG_MACH_OMAP4_PANDA=y
-# CONFIG_MACH_OMAP_4430SDP is not set
-# CONFIG_MACH_OMAP_GENERIC is not set
+# CONFIG_MACH_CM_T35 is not set
+# CONFIG_MACH_CM_T3517 is not set
+# CONFIG_MACH_CRANEBOARD is not set
+# CONFIG_MACH_DEVKIT8000 is not set
+# CONFIG_MACH_IGEP0020 is not set
+# CONFIG_MACH_IGEP0030 is not set
+# CONFIG_MACH_NOKIA_RM680 is not set
+# CONFIG_MACH_NOKIA_RX51 is not set
+# CONFIG_MACH_OMAP3517EVM is not set
+# CONFIG_MACH_OMAP3530_LV_SOM is not set
+# CONFIG_MACH_OMAP3EVM is not set
+CONFIG_MACH_OMAP3_BEAGLE=y
+# CONFIG_MACH_OMAP3_PANDORA is not set
+# CONFIG_MACH_OMAP3_TORPEDO is not set
+# CONFIG_MACH_OMAP_3430SDP is not set
+# CONFIG_MACH_OMAP_3630SDP is not set
+CONFIG_MACH_OMAP_GENERIC=y
+# CONFIG_MACH_OMAP_LDP is not set
+# CONFIG_MACH_OMAP_ZOOM2 is not set
+# CONFIG_MACH_OMAP_ZOOM3 is not set
+CONFIG_MACH_OVERO=y
+# CONFIG_MACH_SBC3530 is not set
+# CONFIG_MACH_TOUCHBOOK is not set
+CONFIG_MAILBOX=y
 CONFIG_MDIO_BOARDINFO=y
+CONFIG_MEMORY=y
+CONFIG_MFD_CORE=y
 CONFIG_MFD_OMAP_USB_HOST=y
-# CONFIG_MFD_T7L66XB is not set
-# CONFIG_MFD_TWL4030_AUDIO is not set
+CONFIG_MFD_TI_AM335X_TSCADC=y
+CONFIG_MFD_TPS65217=y
+# CONFIG_MFD_TPS65218 is not set
+CONFIG_MFD_TPS65910=y
+CONFIG_MFD_TWL4030_AUDIO=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
 CONFIG_MMC=y
 CONFIG_MMC_BLOCK=y
-CONFIG_MMC_OMAP=y
+# CONFIG_MMC_OMAP is not set
 CONFIG_MMC_OMAP_HS=y
 CONFIG_MMC_UNSAFE_RESUME=y
-# CONFIG_MPCORE_WATCHDOG is not set
+CONFIG_MODULES_USE_ELF_REL=y
 # CONFIG_MTD_CFI_INTELEXT is not set
 CONFIG_MTD_CMDLINE_PARTS=y
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
 CONFIG_MTD_DATAFLASH=y
 # CONFIG_MTD_DATAFLASH_OTP is not set
 # CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_BCH=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_BCH=y
+CONFIG_MTD_NAND_OMAP2=y
+CONFIG_MTD_NAND_OMAP_BCH=y
 CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_OF is not set
+# CONFIG_MTD_SM_COMMON is not set
 CONFIG_MULTI_IRQ_HANDLER=y
 CONFIG_MUTEX_SPIN_ON_OWNER=y
 # CONFIG_MWIFIEX is not set
 CONFIG_NEED_DMA_MAP_STATE=y
 CONFIG_NEON=y
+# CONFIG_NET_DMA is not set
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_RX_BUSY_POLL=y
 # CONFIG_NET_VENDOR_I825XX is not set
 # CONFIG_NL80211_TESTMODE is not set
 CONFIG_NLS=y
+CONFIG_NOP_USB_XCEIV=y
 CONFIG_NO_HZ=y
-CONFIG_NR_CPUS=2
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=4
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_MTD=y
+CONFIG_OF_NET=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OMAP2PLUS_MBOX=y
 CONFIG_OMAP2_DSS=y
-# CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS is not set
-CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y
 CONFIG_OMAP2_DSS_DPI=y
+CONFIG_OMAP2_DSS_DRA7XX_DPI=y
 CONFIG_OMAP2_DSS_DSI=y
-# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set
 CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0
-# CONFIG_OMAP2_DSS_RFBI is not set
+CONFIG_OMAP2_DSS_SDI=y
 CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET=y
 # CONFIG_OMAP2_DSS_VENC is not set
-CONFIG_OMAP2_VRAM=y
-CONFIG_OMAP2_VRAM_SIZE=32
+CONFIG_OMAP2_VRFB=y
+# CONFIG_OMAP3_EMU is not set
+# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set
+# CONFIG_OMAP3_SDRC_AC_TIMING is not set
 CONFIG_OMAP4_DSS_HDMI=y
+CONFIG_OMAP4_DSS_HDMI_AUDIO=y
 CONFIG_OMAP4_ERRATA_I688=y
+CONFIG_OMAP5_DSS_HDMI=y
 CONFIG_OMAP_32K_TIMER=y
-CONFIG_OMAP_32K_TIMER_HZ=128
+CONFIG_OMAP_CONTROL_PHY=y
 CONFIG_OMAP_DM_TIMER=y
-# CONFIG_OMAP_MBOX_FWK is not set
-CONFIG_OMAP_MCBSP=y
+CONFIG_OMAP_INTERCONNECT=y
+CONFIG_OMAP_MBOX=y
+CONFIG_OMAP_MBOX_KFIFO_SIZE=256
 CONFIG_OMAP_MUX=y
 # CONFIG_OMAP_MUX_DEBUG is not set
 CONFIG_OMAP_MUX_WARNINGS=y
-CONFIG_OMAP_PACKAGE_CBL=y
-CONFIG_OMAP_PACKAGE_CBS=y
+CONFIG_OMAP_OCP2SCP=y
+CONFIG_OMAP_PACKAGE_CBB=y
+# CONFIG_OMAP_PIPE3 is not set
 CONFIG_OMAP_PM_NOOP=y
 CONFIG_OMAP_RESET_CLOCKS=y
-# CONFIG_OMAP_SMARTREFLEX is not set
-# CONFIG_OMAP_WATCHDOG is not set
+CONFIG_OMAP_USB2=y
+CONFIG_OMAP_WATCHDOG=y
 CONFIG_OUTER_CACHE=y
 CONFIG_OUTER_CACHE_SYNC=y
 CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PANEL_DVI=y
-CONFIG_PANEL_GENERIC_DPI=y
-# CONFIG_PANEL_LGPHILIPS_LB035Q02 is not set
-# CONFIG_PANEL_PICODLP is not set
-# CONFIG_PANEL_TPO_TD043MTEA1 is not set
 # CONFIG_PCI_SYSCALL is not set
 CONFIG_PERF_USE_VMALLOC=y
 CONFIG_PHYLIB=y
+CONFIG_PINCTRL=y
 CONFIG_PL310_ERRATA_588369=y
 CONFIG_PL310_ERRATA_727915=y
 # CONFIG_PL310_ERRATA_753970 is not set
-CONFIG_PL310_ERRATA_769419=y
+# CONFIG_PL310_ERRATA_769419 is not set
 CONFIG_PM=y
 CONFIG_PM_CLK=y
 # CONFIG_PM_DEBUG is not set
 CONFIG_PM_OPP=y
 CONFIG_PM_RUNTIME=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_POWER_AVS=y
+# CONFIG_POWER_AVS_OMAP is not set
+CONFIG_PPS=y
 # CONFIG_PREEMPT_RCU is not set
+CONFIG_PROC_DEVICETREE=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PWM=y
+# CONFIG_PWM_PCA9685 is not set
+CONFIG_PWM_SYSFS=y
+CONFIG_PWM_TIECAP=y
+CONFIG_PWM_TIEHRPWM=y
+CONFIG_PWM_TIPWMSS=y
+# CONFIG_PWM_TWL is not set
+# CONFIG_PWM_TWL_LED is not set
+CONFIG_RCU_STALL_COMMON=y
 CONFIG_REGMAP=y
 CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_IRQ=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=y
 CONFIG_REGULATOR=y
-# CONFIG_REGULATOR_AD5398 is not set
 # CONFIG_REGULATOR_DEBUG is not set
-# CONFIG_REGULATOR_DUMMY is not set
+CONFIG_REGULATOR_DUMMY=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
-# CONFIG_REGULATOR_ISL6271A is not set
-# CONFIG_REGULATOR_LP3971 is not set
-# CONFIG_REGULATOR_LP3972 is not set
-# CONFIG_REGULATOR_MAX1586 is not set
-# CONFIG_REGULATOR_MAX8649 is not set
-# CONFIG_REGULATOR_MAX8660 is not set
-# CONFIG_REGULATOR_MAX8952 is not set
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_TIAVSCLASS0=y
 CONFIG_REGULATOR_TPS65023=y
 CONFIG_REGULATOR_TPS6507X=y
-# CONFIG_REGULATOR_TPS6524X is not set
+CONFIG_REGULATOR_TPS65217=y
+CONFIG_REGULATOR_TPS65910=y
 CONFIG_REGULATOR_TWL4030=y
 # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_TI=y
 # CONFIG_RFKILL_REGULATOR is not set
 CONFIG_RFS_ACCEL=y
 CONFIG_RPS=y
 CONFIG_RTC_CLASS=y
-# CONFIG_RTC_DRV_PT7C4338 is not set
+CONFIG_RTC_DRV_OMAP=y
+CONFIG_RTC_DRV_TPS65910=y
 CONFIG_RTC_DRV_TWL4030=y
-# CONFIG_RTL8192CU is not set
+CONFIG_SCHED_HRTICK=y
 # CONFIG_SCSI_DMA is not set
-# CONFIG_SERIAL_8250 is not set
+# CONFIG_SENSORS_G762 is not set
+# CONFIG_SENSORS_HTU21 is not set
+CONFIG_SENSORS_LM75=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_SERIAL_OMAP=y
 CONFIG_SERIAL_OMAP_CONSOLE=y
 CONFIG_SMP=y
 CONFIG_SMP_ON_UP=y
+CONFIG_SMSC911X=y
+# CONFIG_SMSC911X_ARCH_HOOKS is not set
+CONFIG_SND=y
+CONFIG_SND_AM33XX_SOC_EVM=y
+CONFIG_SND_ARM=y
+CONFIG_SND_COMPRESS_OFFLOAD=y
+CONFIG_SND_DAVINCI_SOC=y
+CONFIG_SND_DAVINCI_SOC_MCASP=y
+CONFIG_SND_DMAENGINE_PCM=y
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_JACK=y
+CONFIG_SND_OMAP_SOC=y
+CONFIG_SND_OMAP_SOC_DMIC=y
+CONFIG_SND_OMAP_SOC_HDMI=y
+CONFIG_SND_OMAP_SOC_MCBSP=y
+CONFIG_SND_OMAP_SOC_MCPDM=y
+CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040=y
+CONFIG_SND_OMAP_SOC_OMAP_HDMI=y
+CONFIG_SND_OMAP_SOC_OMAP_TWL4030=y
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+CONFIG_SND_PCM=y
+CONFIG_SND_PCM_OSS=y
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_DMIC=y
+CONFIG_SND_SOC_HDMI_CODEC=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+CONFIG_SND_SOC_TLV320AIC3X=y
+CONFIG_SND_SOC_TWL4030=y
+CONFIG_SND_SOC_TWL6040=y
+CONFIG_SND_TIMER=y
+# CONFIG_SND_USB_HIFACE is not set
+CONFIG_SOC_AM33XX=y
+CONFIG_SOC_AM43XX=y
+CONFIG_SOC_BUS=y
+CONFIG_SOC_HAS_OMAP2_SDRC=y
+# CONFIG_SOC_OMAP3430 is not set
+# CONFIG_SOC_TI81XX is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SPARSE_IRQ=y
 CONFIG_SPI=y
 CONFIG_SPI_MASTER=y
 # CONFIG_SPI_OMAP24XX is not set
 CONFIG_STOP_MACHINE=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
 CONFIG_SWP_EMULATE=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 # CONFIG_THUMB2_KERNEL is not set
+CONFIG_TICK_CPU_ACCOUNTING=y
+# CONFIG_TIDSPBRIDGE is not set
+CONFIG_TI_CPPI41=y
+CONFIG_TI_CPSW=y
+CONFIG_TI_CPSW_PHY_SEL=y
+CONFIG_TI_CPTS=y
+CONFIG_TI_DAVINCI_CPDMA=y
+# CONFIG_TI_DAVINCI_EMAC is not set
+CONFIG_TI_DAVINCI_MDIO=y
+CONFIG_TI_EDMA=y
+CONFIG_TI_EMIF=y
+CONFIG_TI_PRIV_EDMA=y
+# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
+# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set
+# CONFIG_TOUCHSCREEN_BU21013 is not set
+# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set
+# CONFIG_TOUCHSCREEN_DYNAPRO is not set
+# CONFIG_TOUCHSCREEN_EGALAX is not set
+# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
+# CONFIG_TOUCHSCREEN_MAX11801 is not set
+# CONFIG_TOUCHSCREEN_PIXCIR is not set
+# CONFIG_TOUCHSCREEN_ST1232 is not set
+CONFIG_TOUCHSCREEN_TI_AM335X_TSC=y
+# CONFIG_TOUCHSCREEN_TSC2005 is not set
+# CONFIG_TOUCHSCREEN_TSC_SERIO is not set
 CONFIG_TREE_RCU=y
 CONFIG_TWL4030_CORE=y
 # CONFIG_TWL4030_MADC is not set
 CONFIG_TWL4030_POWER=y
-CONFIG_TWL4030_USB=y
 CONFIG_TWL4030_WATCHDOG=y
-# CONFIG_TWL6030_PWM is not set
-CONFIG_TWL6030_USB=y
-# CONFIG_TWL6040_CORE is not set
+CONFIG_TWL6040_CORE=y
 CONFIG_UID16=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
 CONFIG_USB=y
-# CONFIG_USB_ARCH_HAS_XHCI is not set
-# CONFIG_USB_CDC_COMPOSITE is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 CONFIG_USB_COMMON=y
-# CONFIG_USB_DUMMY_HCD is not set
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_OMAP=y
+CONFIG_USB_EHCI_HCD=m
+CONFIG_USB_EHCI_HCD_OMAP=m
 # CONFIG_USB_EHCI_HCD_PLATFORM is not set
-CONFIG_USB_EHCI_TT_NEWSCHED=y
-# CONFIG_USB_ETH is not set
-# CONFIG_USB_FILE_STORAGE is not set
-# CONFIG_USB_FUNCTIONFS is not set
-# CONFIG_USB_FUSB300 is not set
-CONFIG_USB_GADGET=y
-# CONFIG_USB_GADGETFS is not set
-# CONFIG_USB_GADGET_DEBUG_FILES is not set
-# CONFIG_USB_GADGET_DEBUG_FS is not set
-CONFIG_USB_GADGET_VBUS_DRAW=2
-# CONFIG_USB_G_DBGP is not set
-# CONFIG_USB_G_HID is not set
-# CONFIG_USB_G_NCM is not set
-# CONFIG_USB_G_PRINTER is not set
-# CONFIG_USB_G_SERIAL is not set
-# CONFIG_USB_M66592 is not set
-# CONFIG_USB_MV_UDC is not set
-# CONFIG_USB_NET2272 is not set
 CONFIG_USB_NET_SMSC95XX=y
-# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_OMAP3=y
-# CONFIG_USB_OHCI_HCD_PLATFORM is not set
-CONFIG_USB_OMAP=y
-CONFIG_USB_OTG_UTILS=y
-# CONFIG_USB_R8A66597 is not set
+CONFIG_USB_OTG=y
+CONFIG_USB_PHY=y
 CONFIG_USB_SUPPORT=y
 CONFIG_USB_USBNET=y
-# CONFIG_USB_ZERO is not set
 CONFIG_USE_GENERIC_SMP_HELPERS=y
+CONFIG_USE_OF=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_VFP=y
 CONFIG_VFPv3=y
+CONFIG_VIDEOMODE_HELPERS=y
 CONFIG_VT=y
 CONFIG_VT_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_VT_CONSOLE_SLEEP=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
 # CONFIG_W35UND is not set
-# CONFIG_WL1251 is not set
-CONFIG_WL12XX=m
-CONFIG_WL12XX_MENU=m
-CONFIG_WL12XX_PLATFORM_DATA=y
-CONFIG_WL12XX_SDIO=m
-# CONFIG_WL12XX_SPI is not set
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_XEN is not set
 CONFIG_XPS=y
-CONFIG_XZ_DEC=y
 CONFIG_XZ_DEC_ARM=y
 CONFIG_XZ_DEC_BCJ=y
 CONFIG_ZBOOT_ROM_BSS=0
 CONFIG_ZBOOT_ROM_TEXT=0
+# CONFIG_ZBUD is not set
 CONFIG_ZONE_DMA_FLAG=0
index e118122..afd8398 100644 (file)
@@ -1,5 +1,5 @@
 #
-# Copyright (C) 2012 OpenWrt.org
+# Copyright (C) 2012-2013 OpenWrt.org
 #
 # This is free software, licensed under the GNU General Public License v2.
 # See /LICENSE for more information.
@@ -9,7 +9,11 @@ include $(INCLUDE_DIR)/image.mk
 
 define Image/BuildKernel
        mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n 'Boot Image' -d boot.script $(BIN_DIR)/boot.scr
-       cp $(KDIR)/uImage $(BIN_DIR)/openwrt-$(BOARD)-uImage
+       cp $(KDIR)/zImage $(BIN_DIR)/openwrt-$(BOARD)-zImage
+       -mkdir $(BIN_DIR)/dtbs
+       $(CP) $(LINUX_DIR)/arch/arm/boot/dts/am335x*.dtb $(BIN_DIR)/dtbs/
+       $(CP) $(LINUX_DIR)/arch/arm/boot/dts/omap3*.dtb $(BIN_DIR)/dtbs/
+       $(CP) $(LINUX_DIR)/arch/arm/boot/dts/omap4*.dtb $(BIN_DIR)/dtbs/
 endef
 
 define Image/Build
index d884a70..ecdacfc 100644 (file)
@@ -1,3 +1,3 @@
-fatload mmc 0:1 0x80000000 openwrt-omap-uImage
+fatload mmc 0:1 0x80000000 openwrt-omap-zImage
 setenv bootargs vram=32M fixrtc mem=1G@0x80000000 root=/dev/mmcblk0p2 rootfstype=ext4 console=ttyO2,115200n8 rootwait
-bootm 0x80000000
+bootz 0x80000000
diff --git a/target/linux/omap/patches-3.12/001-ti_git.patch b/target/linux/omap/patches-3.12/001-ti_git.patch
new file mode 100644 (file)
index 0000000..9a1b6c2
--- /dev/null
@@ -0,0 +1,82370 @@
+--- a/arch/arm/boot/dts/am335x-boneblack.dts
++++ b/arch/arm/boot/dts/am335x-boneblack.dts
+@@ -15,3 +15,80 @@
+       regulator-max-microvolt = <1800000>;
+       regulator-always-on;
+ };
++
++&mmc1 {
++      vmmc-supply = <&vmmcsd_fixed>;
++};
++
++&mmc2 {
++      vmmc-supply = <&vmmcsd_fixed>;
++      pinctrl-names = "default";
++      pinctrl-0 = <&emmc_pins>;
++      bus-width = <8>;
++      ti,non-removable;
++      status = "okay";
++};
++
++&am33xx_pinmux {
++      nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins {
++              pinctrl-single,pins = <
++                      0x1b0 0x03      /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
++                      0xa0 0x08       /* lcd_data0.lcd_data0, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
++                      0xa4 0x08       /* lcd_data1.lcd_data1, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
++                      0xa8 0x08       /* lcd_data2.lcd_data2, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
++                      0xac 0x08       /* lcd_data3.lcd_data3, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
++                      0xb0 0x08       /* lcd_data4.lcd_data4, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
++                      0xb4 0x08       /* lcd_data5.lcd_data5, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
++                      0xb8 0x08       /* lcd_data6.lcd_data6, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
++                      0xbc 0x08       /* lcd_data7.lcd_data7, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
++                      0xc0 0x08       /* lcd_data8.lcd_data8, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
++                      0xc4 0x08       /* lcd_data9.lcd_data9, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
++                      0xc8 0x08       /* lcd_data10.lcd_data10, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
++                      0xcc 0x08       /* lcd_data11.lcd_data11, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
++                      0xd0 0x08       /* lcd_data12.lcd_data12, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
++                      0xd4 0x08       /* lcd_data13.lcd_data13, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
++                      0xd8 0x08       /* lcd_data14.lcd_data14, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
++                      0xdc 0x08       /* lcd_data15.lcd_data15, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
++                      0xe0 0x00       /* lcd_vsync.lcd_vsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
++                      0xe4 0x00       /* lcd_hsync.lcd_hsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
++                      0xe8 0x00       /* lcd_pclk.lcd_pclk, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
++                      0xec 0x00       /* lcd_ac_bias_en.lcd_ac_bias_en, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
++              >;
++      };
++      nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins {
++              pinctrl-single,pins = <
++                      0x1b0 0x03      /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
++              >;
++      };
++};
++
++&i2c0 {
++      hdmi1: hdmi@70 {
++            compatible = "nxp,tda998x";
++            reg = <0x70>;
++      };
++};
++
++&lcdc {
++      pinctrl-names = "default", "off";
++      pinctrl-0 = <&nxp_hdmi_bonelt_pins>;
++      pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>;
++      status = "okay";
++      hdmi = <&hdmi1>;
++      display-timings {
++              640x480P60 {
++                 clock-frequency = <25200000>;
++                 hactive = <640>;
++                 vactive = <480>;
++                 hfront-porch = <16>;
++                 hback-porch = <48>;
++                 hsync-len = <96>;
++                 vback-porch = <31>;
++                 vfront-porch = <11>;
++                 vsync-len = <2>;
++                 hsync-active = <0>;
++                 vsync-active = <0>;
++              };
++      };
++};
++
+--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
++++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
+@@ -107,6 +107,27 @@
+                               0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       >;
+               };
++
++              mmc1_pins: pinmux_mmc1_pins {
++                      pinctrl-single,pins = <
++                              0x160 (PIN_INPUT | MUX_MODE7) /* GPIO0_6 */
++                      >;
++              };
++
++              emmc_pins: pinmux_emmc_pins {
++                      pinctrl-single,pins = <
++                              0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
++                              0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
++                              0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
++                              0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
++                              0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
++                              0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
++                              0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
++                              0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
++                              0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
++                              0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
++                      >;
++              };
+       };
+       ocp {
+@@ -183,15 +204,24 @@
+               led@4 {
+                       label = "beaglebone:green:usr2";
+                       gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
++                      linux,default-trigger = "cpu0";
+                       default-state = "off";
+               };
+               led@5 {
+                       label = "beaglebone:green:usr3";
+                       gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
++                      linux,default-trigger = "mmc1";
+                       default-state = "off";
+               };
+       };
++
++      vmmcsd_fixed: fixedregulator@0 {
++              compatible = "regulator-fixed";
++              regulator-name = "vmmcsd_fixed";
++              regulator-min-microvolt = <3300000>;
++              regulator-max-microvolt = <3300000>;
++      };
+ };
+ /include/ "tps65217.dtsi"
+@@ -260,3 +290,12 @@
+       pinctrl-0 = <&davinci_mdio_default>;
+       pinctrl-1 = <&davinci_mdio_sleep>;
+ };
++
++&mmc1 {
++      status = "okay";
++      bus-width = <0x4>;
++      pinctrl-names = "default";
++      pinctrl-0 = <&mmc1_pins>;
++      cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
++      cd-inverted;
++};
+--- a/arch/arm/boot/dts/am335x-bone.dts
++++ b/arch/arm/boot/dts/am335x-bone.dts
+@@ -9,3 +9,13 @@
+ #include "am33xx.dtsi"
+ #include "am335x-bone-common.dtsi"
++
++&ldo3_reg {
++      regulator-min-microvolt = <1800000>;
++      regulator-max-microvolt = <3300000>;
++      regulator-always-on;
++};
++
++&mmc1 {
++      vmmc-supply = <&ldo3_reg>;
++};
+--- a/arch/arm/boot/dts/am335x-evm.dts
++++ b/arch/arm/boot/dts/am335x-evm.dts
+@@ -149,6 +149,54 @@
+                               0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       >;
+               };
++
++              mmc1_pins: pinmux_mmc1_pins {
++                      pinctrl-single,pins = <
++                              0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
++                      >;
++              };
++
++              lcd_pins_s0: lcd_pins_s0 {
++                      pinctrl-single,pins = <
++                              0x20 0x01       /* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */
++                              0x24 0x01       /* gpmc_ad9.lcd_data17, OUTPUT | MODE1 */
++                              0x28 0x01       /* gpmc_ad10.lcd_data18, OUTPUT | MODE1 */
++                              0x2c 0x01       /* gpmc_ad11.lcd_data19, OUTPUT | MODE1 */
++                              0x30 0x01       /* gpmc_ad12.lcd_data20, OUTPUT | MODE1 */
++                              0x34 0x01       /* gpmc_ad13.lcd_data21, OUTPUT | MODE1 */
++                              0x38 0x01       /* gpmc_ad14.lcd_data22, OUTPUT | MODE1 */
++                              0x3c 0x01       /* gpmc_ad15.lcd_data23, OUTPUT | MODE1 */
++                              0xa0 0x00       /* lcd_data0.lcd_data0, OUTPUT | MODE0 */
++                              0xa4 0x00       /* lcd_data1.lcd_data1, OUTPUT | MODE0 */
++                              0xa8 0x00       /* lcd_data2.lcd_data2, OUTPUT | MODE0 */
++                              0xac 0x00       /* lcd_data3.lcd_data3, OUTPUT | MODE0 */
++                              0xb0 0x00       /* lcd_data4.lcd_data4, OUTPUT | MODE0 */
++                              0xb4 0x00       /* lcd_data5.lcd_data5, OUTPUT | MODE0 */
++                              0xb8 0x00       /* lcd_data6.lcd_data6, OUTPUT | MODE0 */
++                              0xbc 0x00       /* lcd_data7.lcd_data7, OUTPUT | MODE0 */
++                              0xc0 0x00       /* lcd_data8.lcd_data8, OUTPUT | MODE0 */
++                              0xc4 0x00       /* lcd_data9.lcd_data9, OUTPUT | MODE0 */
++                              0xc8 0x00       /* lcd_data10.lcd_data10, OUTPUT | MODE0 */
++                              0xcc 0x00       /* lcd_data11.lcd_data11, OUTPUT | MODE0 */
++                              0xd0 0x00       /* lcd_data12.lcd_data12, OUTPUT | MODE0 */
++                              0xd4 0x00       /* lcd_data13.lcd_data13, OUTPUT | MODE0 */
++                              0xd8 0x00       /* lcd_data14.lcd_data14, OUTPUT | MODE0 */
++                              0xdc 0x00       /* lcd_data15.lcd_data15, OUTPUT | MODE0 */
++                              0xe0 0x00       /* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */
++                              0xe4 0x00       /* lcd_hsync.lcd_hsync, OUTPUT | MODE0 */
++                              0xe8 0x00       /* lcd_pclk.lcd_pclk, OUTPUT | MODE0 */
++                              0xec 0x00       /* lcd_ac_bias_en.lcd_ac_bias_en, OUTPUT | MODE0 */
++                      >;
++              };
++
++              am335x_evm_audio_pins: am335x_evm_audio_pins {
++                      pinctrl-single,pins = <
++                              0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rx_dv.mcasp1_aclkx */
++                              0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_txd3.mcasp1_fsx */
++                              0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
++                              0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
++                      >;
++              };
+       };
+       ocp {
+@@ -244,6 +292,18 @@
+                               compatible = "ti,tmp275";
+                               reg = <0x48>;
+                       };
++
++                      tlv320aic3106: tlv320aic3106@1b {
++                              compatible = "ti,tlv320aic3106";
++                              reg = <0x1b>;
++                              status = "okay";
++
++                              /* Regulators */
++                              AVDD-supply = <&vaux2_reg>;
++                              IOVDD-supply = <&vaux2_reg>;
++                              DRVDD-supply = <&vaux2_reg>;
++                              DVDD-supply = <&vbat>;
++                      };
+               };
+               elm: elm@48080000 {
+@@ -268,8 +328,7 @@
+                       nand@0,0 {
+                               reg = <0 0 0>; /* CS0, offset 0 */
+                               nand-bus-width = <8>;
+-                              ti,nand-ecc-opt = "bch8";
+-                              gpmc,device-nand = "true";
++                              ti,nand-ecc-opt= "bch8";
+                               gpmc,device-width = <1>;
+                               gpmc,sync-clk-ps = <0>;
+                               gpmc,cs-on-ns = <0>;
+@@ -293,53 +352,78 @@
+                               gpmc,wait-monitoring-ns = <0>;
+                               gpmc,wr-access-ns = <40>;
+                               gpmc,wr-data-mux-bus-ns = <0>;
+-
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+-                              elm_id = <&elm>;
+-
++                              ti,elm-id = <&elm>;
+                               /* MTD partition table */
+                               partition@0 {
+                                       label = "SPL1";
+                                       reg = <0x00000000 0x000020000>;
+                               };
+-
+                               partition@1 {
+                                       label = "SPL2";
+                                       reg = <0x00020000 0x00020000>;
+                               };
+-
+                               partition@2 {
+                                       label = "SPL3";
+                                       reg = <0x00040000 0x00020000>;
+                               };
+-
+                               partition@3 {
+                                       label = "SPL4";
+                                       reg = <0x00060000 0x00020000>;
+                               };
+-
+                               partition@4 {
+                                       label = "U-boot";
+                                       reg = <0x00080000 0x001e0000>;
+                               };
+-
+                               partition@5 {
+                                       label = "environment";
+                                       reg = <0x00260000 0x00020000>;
+                               };
+-
+                               partition@6 {
+                                       label = "Kernel";
+                                       reg = <0x00280000 0x00500000>;
+                               };
+-
+                               partition@7 {
+                                       label = "File-System";
+                                       reg = <0x00780000 0x0F880000>;
+                               };
+                       };
+               };
++
++              lcdc: lcdc@0x4830e000 {         
++                      pinctrl-names = "default";
++                      pinctrl-0 = <&lcd_pins_s0>;
++                      status = "okay";
++                      display-timings {
++                              800x480p62 {
++                                      clock-frequency = <30000000>;
++                                      hactive = <800>;
++                                      vactive = <480>;
++                                      hfront-porch = <39>;
++                                      hback-porch = <39>;
++                                      hsync-len = <47>;
++                                      vback-porch = <29>;
++                                      vfront-porch = <13>;
++                                      vsync-len = <2>;
++                                      hsync-active = <1>;
++                                      vsync-active = <1>;
++                              };
++                      };
++              };
++
++              sound {
++                      compatible = "ti,da830-evm-audio";
++                      ti,model = "AM335x-EVM";
++                      ti,audio-codec = <&tlv320aic3106>;
++                      ti,mcasp-controller = <&mcasp1>;
++                      ti,codec-clock-rate = <12000000>;
++                      ti,audio-routing =
++                              "Headphone Jack",       "HPLOUT",
++                              "Headphone Jack",       "HPROUT",
++                              "LINE1L",               "Line In",
++                              "LINE1R",               "Line In";
++              };
+       };
+       vbat: fixedregulator@0 {
+@@ -403,10 +487,63 @@
+               brightness-levels = <0 51 53 56 62 75 101 152 255>;
+               default-brightness-level = <8>;
+       };
++
++      panel {
++              compatible = "ti,tilcdc,panel";
++              status = "okay";
++              pinctrl-names = "default";
++              pinctrl-0 = <&lcd_pins_s0>;
++              panel-info {
++                      ac-bias           = <255>;
++                      ac-bias-intrpt    = <0>;
++                      dma-burst-sz      = <16>;
++                      bpp               = <32>;
++                      fdd               = <0x80>;
++                      sync-edge         = <0>;
++                      sync-ctrl         = <1>;
++                      raster-order      = <0>;
++                      fifo-th           = <0>;
++              };
++
++              display-timings {
++                      800x480p62 {
++                              clock-frequency = <30000000>;
++                              hactive = <800>;
++                              vactive = <480>;
++                              hfront-porch = <39>;
++                              hback-porch = <39>;
++                              hsync-len = <47>;
++                              vback-porch = <29>;
++                              vfront-porch = <13>;
++                              vsync-len = <2>;
++                              hsync-active = <1>;
++                              vsync-active = <1>;
++                      };
++              };
++      };
+ };
+ #include "tps65910.dtsi"
++&mcasp1 {
++              pinctrl-names = "default";
++              pinctrl-0 = <&am335x_evm_audio_pins>;
++
++              status = "okay";
++
++              op-mode = <0>;          /* MCASP_IIS_MODE */
++              tdm-slots = <2>;
++              /* 16 serializer */
++              serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
++                      0 0 1 2
++                      0 0 0 0
++                      0 0 0 0
++                      0 0 0 0
++              >;
++              tx-num-evt = <1>;
++              rx-num-evt = <1>;
++};
++
+ &tps {
+       vcc1-supply = <&vbat>;
+       vcc2-supply = <&vbat>;
+@@ -477,6 +614,8 @@
+               };
+               vmmc_reg: regulator@12 {
++                      regulator-min-microvolt = <1800000>;
++                      regulator-max-microvolt = <3300000>;
+                       regulator-always-on;
+               };
+       };
+@@ -509,7 +648,7 @@
+       tsc {
+               ti,wires = <4>;
+               ti,x-plate-resistance = <200>;
+-              ti,coordiante-readouts = <5>;
++              ti,coordinate-readouts = <5>;
+               ti,wire-config = <0x00 0x11 0x22 0x33>;
+       };
+@@ -517,3 +656,12 @@
+               ti,adc-channels = <4 5 6 7>;
+       };
+ };
++
++&mmc1 {
++      status = "okay";
++      vmmc-supply = <&vmmc_reg>;
++      bus-width = <4>;
++      pinctrl-names = "default";
++      pinctrl-0 = <&mmc1_pins>;
++      cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
++};
+--- /dev/null
++++ b/arch/arm/boot/dts/am335x-evm-profile2.dts
+@@ -0,0 +1,296 @@
++/*
++ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++/dts-v1/;
++
++#include "am33xx.dtsi"
++
++/ {
++      model = "TI AM335x EVM";
++      compatible = "ti,am335x-evm", "ti,am33xx";
++
++      cpus {
++              cpu@0 {
++                      cpu0-supply = <&vdd1_reg>;
++              };
++      };
++
++      memory {
++              device_type = "memory";
++              reg = <0x80000000 0x10000000>; /* 256 MB */
++      };
++
++      am33xx_pinmux: pinmux@44e10800 {
++              pinctrl-names = "default";
++              pinctrl-0 = <&matrix_keypad_s0 &clkout2_pin>;
++
++              matrix_keypad_s0: matrix_keypad_s0 {
++                      pinctrl-single,pins = <
++                              0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a5.gpio1_21 */
++                              0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a6.gpio1_22 */
++                              0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a9.gpio1_25 */
++                              0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a10.gpio1_26 */
++                              0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a11.gpio1_27 */
++                      >;
++              };
++
++              i2c0_pins: pinmux_i2c0_pins {
++                      pinctrl-single,pins = <
++                              0x188 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_sda.i2c0_sda */
++                              0x18c (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_scl.i2c0_scl */
++                      >;
++              };
++
++              spi0_pins: pinmux_spi0_pins {
++                      pinctrl-single,pins = <
++                              0x150 (PIN_INPUT_PULLUP | MUX_MODE0)    /* spi0_clk.spi0_clk */
++                              0x154 (PIN_INPUT_PULLUP | MUX_MODE0)    /* spi0_d0.spi0_d0 */
++                              0x158 (PIN_INPUT_PULLUP | MUX_MODE0)    /* spi0_d1.spi0_d1 */
++                              0x15c (PIN_INPUT_PULLUP | MUX_MODE0)    /* spi0_cs0.spi0_cs0 */
++                      >;
++              };
++
++              uart0_pins: pinmux_uart0_pins {
++                      pinctrl-single,pins = <
++                              0x170 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart0_rxd.uart0_rxd */
++                              0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
++                      >;
++              };
++
++              clkout2_pin: pinmux_clkout2_pin {
++                      pinctrl-single,pins = <
++                              0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
++                      >;
++              };
++
++              cpsw_default: cpsw_default {
++                      pinctrl-single,pins = <
++                              /* Slave 1 */
++                              0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
++                              0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxdv.rgmii1_rctl */
++                              0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
++                              0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
++                              0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
++                              0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
++                              0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
++                              0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxclk.rgmii1_rclk */
++                              0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd3.rgmii1_rd3 */
++                              0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd2.rgmii1_rd2 */
++                              0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd1.rgmii1_rd1 */
++                              0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd0.rgmii1_rd0 */
++                      >;
++              };
++
++              cpsw_sleep: cpsw_sleep {
++                      pinctrl-single,pins = <
++                              /* Slave 1 reset value */
++                              0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                              0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                              0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                              0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                              0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                              0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                              0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                              0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                              0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                              0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                              0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                              0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                      >;
++              };
++
++              davinci_mdio_default: davinci_mdio_default {
++                      pinctrl-single,pins = <
++                              /* MDIO */
++                              0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
++                              0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
++                      >;
++              };
++
++              davinci_mdio_sleep: davinci_mdio_sleep {
++                      pinctrl-single,pins = <
++                              /* MDIO reset value */
++                              0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                              0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                      >;
++              };
++      };
++
++      ocp {
++              uart0: serial@44e09000 {
++                      pinctrl-names = "default";
++                      pinctrl-0 = <&uart0_pins>;
++
++                      status = "okay";
++              };
++
++              i2c0: i2c@44e0b000 {
++                      pinctrl-names = "default";
++                      pinctrl-0 = <&i2c0_pins>;
++
++                      status = "okay";
++                      clock-frequency = <400000>;
++
++                      tps: tps@2d {
++                              reg = <0x2d>;
++                      };
++              };
++
++              spi0: spi@48030000 {
++                      pinctrl-names = "default";
++                      pinctrl-0 = <&spi0_pins>;
++
++                      status = "okay";
++                      m25p80@0 {
++                              compatible = "w25q64";
++                              spi-max-frequency = <24000000>;
++                              reg = <0x0>;
++                      };
++              };
++      };
++
++      vbat: fixedregulator@0 {
++              compatible = "regulator-fixed";
++              regulator-name = "vbat";
++              regulator-min-microvolt = <5000000>;
++              regulator-max-microvolt = <5000000>;
++              regulator-boot-on;
++      };
++
++      lis3_reg: fixedregulator@1 {
++              compatible = "regulator-fixed";
++              regulator-name = "lis3_reg";
++              regulator-boot-on;
++      };
++
++      matrix_keypad: matrix_keypad@0 {
++              compatible = "gpio-matrix-keypad";
++              debounce-delay-ms = <5>;
++              col-scan-delay-us = <2>;
++
++              row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH         /* Bank1, pin25 */
++                           &gpio1 26 GPIO_ACTIVE_HIGH         /* Bank1, pin26 */
++                           &gpio1 27 GPIO_ACTIVE_HIGH>;       /* Bank1, pin27 */
++
++              col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH         /* Bank1, pin21 */
++                           &gpio1 22 GPIO_ACTIVE_HIGH>;       /* Bank1, pin22 */
++
++              linux,keymap = <0x0000008b      /* MENU */
++                              0x0100009e      /* BACK */
++                              0x02000069      /* LEFT */
++                              0x0001006a      /* RIGHT */
++                              0x0101001c      /* ENTER */
++                              0x0201006c>;    /* DOWN */
++      };
++};
++
++#include "tps65910.dtsi"
++
++&tps {
++      vcc1-supply = <&vbat>;
++      vcc2-supply = <&vbat>;
++      vcc3-supply = <&vbat>;
++      vcc4-supply = <&vbat>;
++      vcc5-supply = <&vbat>;
++      vcc6-supply = <&vbat>;
++      vcc7-supply = <&vbat>;
++      vccio-supply = <&vbat>;
++
++      regulators {
++              vrtc_reg: regulator@0 {
++                      regulator-always-on;
++              };
++
++              vio_reg: regulator@1 {
++                      regulator-always-on;
++              };
++
++              vdd1_reg: regulator@2 {
++                      /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
++                      regulator-name = "vdd_mpu";
++                      regulator-min-microvolt = <912500>;
++                      regulator-max-microvolt = <1312500>;
++                      regulator-boot-on;
++                      regulator-always-on;
++              };
++
++              vdd2_reg: regulator@3 {
++                      /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
++                      regulator-name = "vdd_core";
++                      regulator-min-microvolt = <912500>;
++                      regulator-max-microvolt = <1150000>;
++                      regulator-boot-on;
++                      regulator-always-on;
++              };
++
++              vdd3_reg: regulator@4 {
++                      regulator-always-on;
++              };
++
++              vdig1_reg: regulator@5 {
++                      regulator-always-on;
++              };
++
++              vdig2_reg: regulator@6 {
++                      regulator-always-on;
++              };
++
++              vpll_reg: regulator@7 {
++                      regulator-always-on;
++              };
++
++              vdac_reg: regulator@8 {
++                      regulator-always-on;
++              };
++
++              vaux1_reg: regulator@9 {
++                      regulator-always-on;
++              };
++
++              vaux2_reg: regulator@10 {
++                      regulator-always-on;
++              };
++
++              vaux33_reg: regulator@11 {
++                      regulator-always-on;
++              };
++
++              vmmc_reg: regulator@12 {
++                      regulator-min-microvolt = <1800000>;
++                      regulator-max-microvolt = <3300000>;
++                      regulator-always-on;
++              };
++      };
++};
++
++&mac {
++      pinctrl-names = "default", "sleep";
++      pinctrl-0 = <&cpsw_default>;
++      pinctrl-1 = <&cpsw_sleep>;
++};
++
++&davinci_mdio {
++      pinctrl-names = "default", "sleep";
++      pinctrl-0 = <&davinci_mdio_default>;
++      pinctrl-1 = <&davinci_mdio_sleep>;
++};
++
++&cpsw_emac0 {
++      phy_id = <&davinci_mdio>, <0>;
++      phy-mode = "rgmii-txid";
++};
++
++&cpsw_emac1 {
++      phy_id = <&davinci_mdio>, <1>;
++      phy-mode = "rgmii-txid";
++};
++
++&mmc1 {
++      status = "okay";
++      vmmc-supply = <&vmmc_reg>;
++      bus-width = <4>;
++};
+--- a/arch/arm/boot/dts/am335x-evmsk.dts
++++ b/arch/arm/boot/dts/am335x-evmsk.dts
+@@ -35,6 +35,39 @@
+               pinctrl-names = "default";
+               pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>;
++              lcd_pins_s0: lcd_pins_s0 {
++                      pinctrl-single,pins = <
++                              0x20 0x01       /* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */
++                              0x24 0x01       /* gpmc_ad9.lcd_data17, OUTPUT | MODE1 */
++                              0x28 0x01       /* gpmc_ad10.lcd_data18, OUTPUT | MODE1 */
++                              0x2c 0x01       /* gpmc_ad11.lcd_data19, OUTPUT | MODE1 */
++                              0x30 0x01       /* gpmc_ad12.lcd_data20, OUTPUT | MODE1 */
++                              0x34 0x01       /* gpmc_ad13.lcd_data21, OUTPUT | MODE1 */
++                              0x38 0x01       /* gpmc_ad14.lcd_data22, OUTPUT | MODE1 */
++                              0x3c 0x01       /* gpmc_ad15.lcd_data23, OUTPUT | MODE1 */
++                              0xa0 0x00       /* lcd_data0.lcd_data0, OUTPUT | MODE0 */
++                              0xa4 0x00       /* lcd_data1.lcd_data1, OUTPUT | MODE0 */
++                              0xa8 0x00       /* lcd_data2.lcd_data2, OUTPUT | MODE0 */
++                              0xac 0x00       /* lcd_data3.lcd_data3, OUTPUT | MODE0 */
++                              0xb0 0x00       /* lcd_data4.lcd_data4, OUTPUT | MODE0 */
++                              0xb4 0x00       /* lcd_data5.lcd_data5, OUTPUT | MODE0 */
++                              0xb8 0x00       /* lcd_data6.lcd_data6, OUTPUT | MODE0 */
++                              0xbc 0x00       /* lcd_data7.lcd_data7, OUTPUT | MODE0 */
++                              0xc0 0x00       /* lcd_data8.lcd_data8, OUTPUT | MODE0 */
++                              0xc4 0x00       /* lcd_data9.lcd_data9, OUTPUT | MODE0 */
++                              0xc8 0x00       /* lcd_data10.lcd_data10, OUTPUT | MODE0 */
++                              0xcc 0x00       /* lcd_data11.lcd_data11, OUTPUT | MODE0 */
++                              0xd0 0x00       /* lcd_data12.lcd_data12, OUTPUT | MODE0 */
++                              0xd4 0x00       /* lcd_data13.lcd_data13, OUTPUT | MODE0 */
++                              0xd8 0x00       /* lcd_data14.lcd_data14, OUTPUT | MODE0 */
++                              0xdc 0x00       /* lcd_data15.lcd_data15, OUTPUT | MODE0 */
++                              0xe0 0x00       /* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */
++                              0xe4 0x00       /* lcd_hsync.lcd_hsync, OUTPUT | MODE0 */
++                              0xe8 0x00       /* lcd_pclk.lcd_pclk, OUTPUT | MODE0 */
++                              0xec 0x00       /* lcd_ac_bias_en.lcd_ac_bias_en, OUTPUT | MODE0 */
++                      >;
++              };
++
+               user_leds_s0: user_leds_s0 {
+                       pinctrl-single,pins = <
+                               0x10 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_ad4.gpio1_4 */
+@@ -158,6 +191,21 @@
+                               0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                       >;
+               };
++
++              mmc1_pins: pinmux_mmc1_pins {
++                      pinctrl-single,pins = <
++                              0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
++                      >;
++              };
++
++              mcasp1_pins: mcasp1_pins {
++                      pinctrl-single,pins = <
++                              0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
++                              0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
++                              0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
++                              0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
++                      >;
++              };
+       };
+       ocp {
+@@ -206,6 +254,18 @@
+                               st,max-limit-y = <550>;
+                               st,max-limit-z = <750>;
+                       };
++
++                      tlv320aic3106: tlv320aic3106@1b {
++                              compatible = "ti,tlv320aic3106";
++                              reg = <0x1b>;
++                              status = "okay";
++
++                              /* Regulators */
++                              AVDD-supply = <&vaux2_reg>;
++                              IOVDD-supply = <&vaux2_reg>;
++                              DRVDD-supply = <&vaux2_reg>;
++                              DVDD-supply = <&vbat>;
++                      };
+               };
+               musb: usb@47400000 {
+@@ -219,9 +279,22 @@
+                               status = "okay";
+                       };
++                      usb-phy@47401b00 {
++                              status = "okay";
++                      };
++
+                       usb@47401000 {
+                               status = "okay";
+                       };
++
++                      usb@47401800 {
++                              status = "okay";
++                              dr_mode = "host";
++                      };
++
++                      dma-controller@07402000  {
++                              status = "okay";
++                      };
+               };
+               epwmss2: epwmss@48304000 {
+@@ -233,6 +306,38 @@
+                               pinctrl-0 = <&ecap2_pins>;
+                       };
+               };
++
++              lcdc: lcdc@0x4830e000 {
++                      pinctrl-names = "default";
++                      pinctrl-0 = <&lcd_pins_s0>;
++                      status = "okay";
++                      display-timings {
++                              480x272 {
++                                      hactive         = <480>;
++                                      vactive         = <272>;
++                                      hback-porch     = <43>;
++                                      hfront-porch    = <8>;
++                                      hsync-len       = <4>;
++                                      vback-porch     = <12>;
++                                      vfront-porch    = <4>;
++                                      vsync-len       = <10>;
++                                      clock-frequency = <9000000>;
++                                      hsync-active    = <0>;
++                                      vsync-active    = <0>;
++                              };
++                      };
++              };
++
++              sound {
++                      compatible = "ti,da830-evm-audio";
++                      ti,model = "AM335x-EVMSK";
++                      ti,audio-codec = <&tlv320aic3106>;
++                      ti,mcasp-controller = <&mcasp1>;
++                      ti,codec-clock-rate = <24576000>;
++                      ti,audio-routing =
++                              "Headphone Jack",       "HPLOUT",
++                              "Headphone Jack",       "HPROUT";
++              };
+       };
+       vbat: fixedregulator@0 {
+@@ -393,6 +498,8 @@
+               };
+               vmmc_reg: regulator@12 {
++                      regulator-min-microvolt = <1800000>;
++                      regulator-max-microvolt = <3300000>;
+                       regulator-always-on;
+               };
+       };
+@@ -419,3 +526,45 @@
+       phy_id = <&davinci_mdio>, <1>;
+       phy-mode = "rgmii-txid";
+ };
++
++&tscadc {
++      status = "okay";
++      tsc {
++              ti,wires = <4>;
++              ti,x-plate-resistance = <200>;
++              ti,coordinate-readouts = <5>;
++              ti,wire-config = <0x00 0x11 0x22 0x33>;
++      };
++};
++
++&gpio0 {
++      ti,no-reset;
++};
++
++&mmc1 {
++      status = "okay";
++      vmmc-supply = <&vmmc_reg>;
++      bus-width = <4>;
++      pinctrl-names = "default";
++      pinctrl-0 = <&mmc1_pins>;
++      cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
++};
++
++&mcasp1 {
++              pinctrl-names = "default";
++              pinctrl-0 = <&mcasp1_pins>;
++
++              status = "okay";
++
++              op-mode = <0>;          /* MCASP_IIS_MODE */
++              tdm-slots = <2>;
++              /* 16 serializer */
++              serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
++                      0 0 1 2
++                      0 0 0 0
++                      0 0 0 0
++                      0 0 0 0
++              >;
++              tx-num-evt = <1>;
++              rx-num-evt = <1>;
++};
+--- /dev/null
++++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
+@@ -0,0 +1,661 @@
++/*
++ * Device Tree Source for AM33xx clock data
++ *
++ * Copyright (C) 2013 Texas Instruments, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++clk_32768_ck: clk_32768_ck {
++      #clock-cells = <0>;
++      compatible = "fixed-clock";
++      clock-frequency = <32768>;
++};
++
++clk_rc32k_ck: clk_rc32k_ck {
++      #clock-cells = <0>;
++      compatible = "fixed-clock";
++      clock-frequency = <32000>;
++};
++
++virt_19200000_ck: virt_19200000_ck {
++      #clock-cells = <0>;
++      compatible = "fixed-clock";
++      clock-frequency = <19200000>;
++};
++
++virt_24000000_ck: virt_24000000_ck {
++      #clock-cells = <0>;
++      compatible = "fixed-clock";
++      clock-frequency = <24000000>;
++};
++
++virt_25000000_ck: virt_25000000_ck {
++      #clock-cells = <0>;
++      compatible = "fixed-clock";
++      clock-frequency = <25000000>;
++};
++
++virt_26000000_ck: virt_26000000_ck {
++      #clock-cells = <0>;
++      compatible = "fixed-clock";
++      clock-frequency = <26000000>;
++};
++
++sys_clkin_ck: sys_clkin_ck@44e10040 {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
++      bit-shift = <22>;
++      reg = <0x44e10040 0x4>;
++      bit-mask = <0x3>;
++};
++
++tclkin_ck: tclkin_ck {
++      #clock-cells = <0>;
++      compatible = "fixed-clock";
++      clock-frequency = <12000000>;
++};
++
++dpll_core_ck: dpll_core_ck@44e00490 {
++      #clock-cells = <0>;
++      compatible = "ti,omap4-dpll-core-clock";
++      clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
++      reg = <0x44e00490 0x4>, <0x44e0045c 0x4>, <0x44e00468 0x4>;
++      reg-names = "control", "idlest", "mult-div1";
++};
++
++dpll_core_x2_ck: dpll_core_x2_ck {
++      #clock-cells = <0>;
++      compatible = "ti,omap4-dpll-x2-clock";
++      clocks = <&dpll_core_ck>;
++};
++
++dpll_core_m4_ck: dpll_core_m4_ck@44e00480 {
++      #clock-cells = <0>;
++      compatible = "divider-clock";
++      clocks = <&dpll_core_x2_ck>;
++      reg = <0x44e00480 0x4>;
++      bit-mask = <0x1f>;
++      index-starts-at-one;
++};
++
++dpll_core_m5_ck: dpll_core_m5_ck@44e00484 {
++      #clock-cells = <0>;
++      compatible = "divider-clock";
++      clocks = <&dpll_core_x2_ck>;
++      reg = <0x44e00484 0x4>;
++      bit-mask = <0x1f>;
++      index-starts-at-one;
++};
++
++dpll_core_m6_ck: dpll_core_m6_ck@44e004d8 {
++      #clock-cells = <0>;
++      compatible = "divider-clock";
++      clocks = <&dpll_core_x2_ck>;
++      reg = <0x44e004d8 0x4>;
++      bit-mask = <0x1f>;
++      index-starts-at-one;
++};
++
++dpll_mpu_ck: dpll_mpu_ck@44e00488 {
++      #clock-cells = <0>;
++      compatible = "ti,omap4-dpll-clock";
++      clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
++      reg = <0x44e00488 0x4>, <0x44e00420 0x4>, <0x44e0042c 0x4>;
++      reg-names = "control", "idlest", "mult-div1";
++};
++
++dpll_mpu_m2_ck: dpll_mpu_m2_ck@44e004a8 {
++      #clock-cells = <0>;
++      compatible = "divider-clock";
++      clocks = <&dpll_mpu_ck>;
++      reg = <0x44e004a8 0x4>;
++      bit-mask = <0x1f>;
++      index-starts-at-one;
++};
++
++dpll_ddr_ck: dpll_ddr_ck@44e00494 {
++      #clock-cells = <0>;
++      compatible = "ti,omap4-dpll-no-gate-clock";
++      clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
++      reg = <0x44e00494 0x4>, <0x44e00434 0x4>, <0x44e00440 0x4>;
++      reg-names = "control", "idlest", "mult-div1";
++};
++
++dpll_ddr_m2_ck: dpll_ddr_m2_ck@44e004a0 {
++      #clock-cells = <0>;
++      compatible = "divider-clock";
++      clocks = <&dpll_ddr_ck>;
++      reg = <0x44e004a0 0x4>;
++      bit-mask = <0x1f>;
++      index-starts-at-one;
++};
++
++dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&dpll_ddr_m2_ck>;
++      clock-mult = <1>;
++      clock-div = <2>;
++};
++
++dpll_disp_ck: dpll_disp_ck@44e00498 {
++      #clock-cells = <0>;
++      compatible = "ti,omap4-dpll-no-gate-clock";
++      clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
++      reg = <0x44e00498 0x4>, <0x44e00448 0x4>, <0x44e00454 0x4>;
++      reg-names = "control", "idlest", "mult-div1";
++};
++
++dpll_disp_m2_ck: dpll_disp_m2_ck@44e004a4 {
++      #clock-cells = <0>;
++      compatible = "divider-clock";
++      clocks = <&dpll_disp_ck>;
++      reg = <0x44e004a4 0x4>;
++      bit-mask = <0x1f>;
++      index-starts-at-one;
++      set-rate-parent;
++};
++
++dpll_per_ck: dpll_per_ck@44e0048c {
++      #clock-cells = <0>;
++      compatible = "ti,omap4-dpll-no-gate-j-type-clock";
++      clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
++      reg = <0x44e0048c 0x4>, <0x44e00470 0x4>, <0x44e0049c 0x4>;
++      reg-names = "control", "idlest", "mult-div1";
++};
++
++dpll_per_m2_ck: dpll_per_m2_ck@44e004ac {
++      #clock-cells = <0>;
++      compatible = "divider-clock";
++      clocks = <&dpll_per_ck>;
++      reg = <0x44e004ac 0x4>;
++      bit-mask = <0x1f>;
++      index-starts-at-one;
++};
++
++dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&dpll_per_m2_ck>;
++      clock-mult = <1>;
++      clock-div = <4>;
++};
++
++dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&dpll_per_m2_ck>;
++      clock-mult = <1>;
++      clock-div = <4>;
++};
++
++adc_tsc_fck: adc_tsc_fck {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&sys_clkin_ck>;
++      clock-mult = <1>;
++      clock-div = <1>;
++};
++
++cefuse_fck: cefuse_fck@44e00a20 {
++      #clock-cells = <0>;
++      compatible = "gate-clock";
++      clocks = <&sys_clkin_ck>;
++      bit-shift = <1>;
++      reg = <0x44e00a20 0x4>;
++};
++
++clk_24mhz: clk_24mhz {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&dpll_per_m2_ck>;
++      clock-mult = <1>;
++      clock-div = <8>;
++};
++
++clkdiv32k_ck: clkdiv32k_ck {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&clk_24mhz>;
++      clock-mult = <1>;
++      clock-div = <732>;
++};
++
++clkdiv32k_ick: clkdiv32k_ick@44e0014c {
++      #clock-cells = <0>;
++      compatible = "ti,gate-clock";
++      clocks = <&clkdiv32k_ck>;
++      reg = <0x44e0014c 0x4>;
++      bit-shift = <1>;
++};
++
++dcan0_fck: dcan0_fck {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&sys_clkin_ck>;
++      clock-mult = <1>;
++      clock-div = <1>;
++};
++
++dcan1_fck: dcan1_fck {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&sys_clkin_ck>;
++      clock-mult = <1>;
++      clock-div = <1>;
++};
++
++l3_gclk: l3_gclk {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&dpll_core_m4_ck>;
++      clock-mult = <1>;
++      clock-div = <1>;
++};
++
++pruss_ocp_gclk: pruss_ocp_gclk@44e00530 {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
++      reg = <0x44e00530 0x4>;
++      bit-mask = <0x1>;
++};
++
++mcasp0_fck: mcasp0_fck {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&sys_clkin_ck>;
++      clock-mult = <1>;
++      clock-div = <1>;
++};
++
++mcasp1_fck: mcasp1_fck {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&sys_clkin_ck>;
++      clock-mult = <1>;
++      clock-div = <1>;
++};
++
++mmu_fck: mmu_fck@44e00914 {
++      #clock-cells = <0>;
++      compatible = "gate-clock";
++      clocks = <&dpll_core_m4_ck>;
++      bit-shift = <1>;
++      reg = <0x44e00914 0x4>;
++};
++
++smartreflex0_fck: smartreflex0_fck {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&sys_clkin_ck>;
++      clock-mult = <1>;
++      clock-div = <1>;
++};
++
++smartreflex1_fck: smartreflex1_fck {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&sys_clkin_ck>;
++      clock-mult = <1>;
++      clock-div = <1>;
++};
++
++sha0_fck: sha0_fck {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&sys_clkin_ck>;
++      clock-mult = <1>;
++      clock-div = <1>;
++};
++
++rng_fck: rng_fck {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&sys_clkin_ck>;
++      clock-mult = <1>;
++      clock-div = <1>;
++};
++
++aes0_fck: aes0_fck {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&sys_clkin_ck>;
++      clock-mult = <1>;
++      clock-div = <1>;
++};
++
++timer1_fck: timer1_fck@44e00528 {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
++      reg = <0x44e00528 0x4>;
++      bit-mask = <0x7>;
++};
++
++timer2_fck: timer2_fck@44e00508 {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
++      reg = <0x44e00508 0x4>;
++      bit-mask = <0x3>;
++};
++
++timer3_fck: timer3_fck@44e0050c {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
++      reg = <0x44e0050c 0x4>;
++      bit-mask = <0x3>;
++};
++
++timer4_fck: timer4_fck@44e00510 {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
++      reg = <0x44e00510 0x4>;
++      bit-mask = <0x3>;
++};
++
++timer5_fck: timer5_fck@44e00518 {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
++      reg = <0x44e00518 0x4>;
++      bit-mask = <0x3>;
++};
++
++timer6_fck: timer6_fck@44e0051c {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
++      reg = <0x44e0051c 0x4>;
++      bit-mask = <0x3>;
++};
++
++timer7_fck: timer7_fck@44e00504 {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
++      reg = <0x44e00504 0x4>;
++      bit-mask = <0x3>;
++};
++
++usbotg_fck: usbotg_fck@44e0047c {
++      #clock-cells = <0>;
++      compatible = "gate-clock";
++      clocks = <&dpll_per_ck>;
++      bit-shift = <8>;
++      reg = <0x44e0047c 0x4>;
++};
++
++dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&dpll_core_m4_ck>;
++      clock-mult = <1>;
++      clock-div = <2>;
++};
++
++ieee5000_fck: ieee5000_fck@44e000e4 {
++      #clock-cells = <0>;
++      compatible = "gate-clock";
++      clocks = <&dpll_core_m4_div2_ck>;
++      bit-shift = <1>;
++      reg = <0x44e000e4 0x4>;
++};
++
++wdt1_fck: wdt1_fck@44e00538 {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
++      reg = <0x44e00538 0x4>;
++      bit-mask = <0x3>;
++};
++
++l4_rtc_gclk: l4_rtc_gclk {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&dpll_core_m4_ck>;
++      clock-mult = <1>;
++      clock-div = <2>;
++};
++
++l4hs_gclk: l4hs_gclk {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&dpll_core_m4_ck>;
++      clock-mult = <1>;
++      clock-div = <1>;
++};
++
++l3s_gclk: l3s_gclk {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&dpll_core_m4_div2_ck>;
++      clock-mult = <1>;
++      clock-div = <1>;
++};
++
++l4fw_gclk: l4fw_gclk {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&dpll_core_m4_div2_ck>;
++      clock-mult = <1>;
++      clock-div = <1>;
++};
++
++l4ls_gclk: l4ls_gclk {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&dpll_core_m4_div2_ck>;
++      clock-mult = <1>;
++      clock-div = <1>;
++};
++
++sysclk_div_ck: sysclk_div_ck {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&dpll_core_m4_ck>;
++      clock-mult = <1>;
++      clock-div = <1>;
++};
++
++cpsw_125mhz_gclk: cpsw_125mhz_gclk {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&dpll_core_m5_ck>;
++      clock-mult = <1>;
++      clock-div = <2>;
++};
++
++cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@44e00520 {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
++      reg = <0x44e00520 0x4>;
++      bit-mask = <0x1>;
++};
++
++gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@44e0053c {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>;
++      reg = <0x44e0053c 0x4>;
++      bit-mask = <0x3>;
++};
++
++gpio0_dbclk: gpio0_dbclk@44e00408 {
++      #clock-cells = <0>;
++      compatible = "gate-clock";
++      clocks = <&gpio0_dbclk_mux_ck>;
++      bit-shift = <18>;
++      reg = <0x44e00408 0x4>;
++};
++
++gpio1_dbclk: gpio1_dbclk@44e000ac {
++      #clock-cells = <0>;
++      compatible = "gate-clock";
++      clocks = <&clkdiv32k_ick>;
++      bit-shift = <18>;
++      reg = <0x44e000ac 0x4>;
++};
++
++gpio2_dbclk: gpio2_dbclk@44e000b0 {
++      #clock-cells = <0>;
++      compatible = "gate-clock";
++      clocks = <&clkdiv32k_ick>;
++      bit-shift = <18>;
++      reg = <0x44e000b0 0x4>;
++};
++
++gpio3_dbclk: gpio3_dbclk@44e000b4 {
++      #clock-cells = <0>;
++      compatible = "gate-clock";
++      clocks = <&clkdiv32k_ick>;
++      bit-shift = <18>;
++      reg = <0x44e000b4 0x4>;
++};
++
++lcd_gclk: lcd_gclk@44e00534 {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
++      reg = <0x44e00534 0x4>;
++      bit-mask = <0x3>;
++      set-rate-parent;
++};
++
++mmc_clk: mmc_clk {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&dpll_per_m2_ck>;
++      clock-mult = <1>;
++      clock-div = <2>;
++};
++
++gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@44e0052c {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
++      bit-shift = <1>;
++      reg = <0x44e0052c 0x4>;
++      bit-mask = <0x1>;
++};
++
++gfx_fck_div_ck: gfx_fck_div_ck@44e0052c {
++      #clock-cells = <0>;
++      compatible = "divider-clock";
++      clocks = <&gfx_fclk_clksel_ck>;
++      reg = <0x44e0052c 0x4>;
++      table = < 1 0 >, < 2 1 >;
++      bit-mask = <0x1>;
++};
++
++sysclkout_pre_ck: sysclkout_pre_ck@44e00700 {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
++      reg = <0x44e00700 0x4>;
++      bit-mask = <0x7>;
++};
++
++clkout2_div_ck: clkout2_div_ck@44e00700 {
++      #clock-cells = <0>;
++      compatible = "divider-clock";
++      clocks = <&sysclkout_pre_ck>;
++      bit-shift = <3>;
++      reg = <0x44e00700 0x4>;
++      table = < 1 0 >, < 2 1 >, < 3 2 >, < 4 3 >, < 5 4 >, < 6 5 >, < 7 6 >, < 8 7 >;
++      bit-mask = <0x7>;
++};
++
++dbg_sysclk_ck: dbg_sysclk_ck@44e00414 {
++      #clock-cells = <0>;
++      compatible = "gate-clock";
++      clocks = <&sys_clkin_ck>;
++      bit-shift = <19>;
++      reg = <0x44e00414 0x4>;
++};
++
++dbg_clka_ck: dbg_clka_ck@44e00414 {
++      #clock-cells = <0>;
++      compatible = "gate-clock";
++      clocks = <&dpll_core_m4_ck>;
++      bit-shift = <30>;
++      reg = <0x44e00414 0x4>;
++};
++
++stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck@44e00414 {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
++      bit-shift = <22>;
++      reg = <0x44e00414 0x4>;
++      bit-mask = <0x3>;
++};
++
++trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck@44e00414 {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
++      bit-shift = <20>;
++      reg = <0x44e00414 0x4>;
++      bit-mask = <0x3>;
++};
++
++stm_clk_div_ck: stm_clk_div_ck@44e00414 {
++      #clock-cells = <0>;
++      compatible = "divider-clock";
++      clocks = <&stm_pmd_clock_mux_ck>;
++      bit-shift = <27>;
++      reg = <0x44e00414 0x4>;
++      bit-mask = <0x7>;
++      index-power-of-two;
++};
++
++trace_clk_div_ck: trace_clk_div_ck@44e00414 {
++      #clock-cells = <0>;
++      compatible = "divider-clock";
++      clocks = <&trace_pmd_clk_mux_ck>;
++      bit-shift = <24>;
++      reg = <0x44e00414 0x4>;
++      bit-mask = <0x7>;
++      index-power-of-two;
++};
++
++clkout2_ck: clkout2_ck@44e00700 {
++      #clock-cells = <0>;
++      compatible = "gate-clock";
++      clocks = <&clkout2_div_ck>;
++      bit-shift = <7>;
++      reg = <0x44e00700 0x4>;
++};
++
++ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
++      #clock-cells = <0>;
++      compatible = "gate-clock";
++      clocks = <&dpll_per_m2_ck>;
++      bit-shift = <0>;
++      reg = <0x44e10664 0x4>;
++};
++
++ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
++      #clock-cells = <0>;
++      compatible = "gate-clock";
++      clocks = <&dpll_per_m2_ck>;
++      bit-shift = <1>;
++      reg = <0x44e10664 0x4>;
++};
++
++ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
++      #clock-cells = <0>;
++      compatible = "gate-clock";
++      clocks = <&dpll_per_m2_ck>;
++      bit-shift = <2>;
++      reg = <0x44e10664 0x4>;
++};
+--- a/arch/arm/boot/dts/am33xx.dtsi
++++ b/arch/arm/boot/dts/am33xx.dtsi
+@@ -18,6 +18,9 @@
+       interrupt-parent = <&intc>;
+       aliases {
++              i2c0 = &i2c0;
++              i2c1 = &i2c1;
++              i2c2 = &i2c2;
+               serial0 = &uart0;
+               serial1 = &uart1;
+               serial2 = &uart2;
+@@ -30,6 +33,8 @@
+               usb1 = &usb1;
+               phy0 = &usb0_phy;
+               phy1 = &usb1_phy;
++              ethernet0 = &cpsw_emac0;
++              ethernet1 = &cpsw_emac1;
+       };
+       cpus {
+@@ -53,6 +58,10 @@
+                               275000  1125000
+                       >;
+                       voltage-tolerance = <2>; /* 2 percentage */
++
++                      clocks = <&dpll_mpu_ck>;
++                      clock-names = "cpu";
++
+                       clock-latency = <300000>; /* From omap-cpufreq driver */
+               };
+       };
+@@ -91,6 +100,8 @@
+               #size-cells = <1>;
+               ranges;
+               ti,hwmods = "l3_main";
++              clocks = <&l3_gclk>;
++              clock-names = "fck";
+               intc: interrupt-controller@48200000 {
+                       compatible = "ti,omap2-intc";
+@@ -100,9 +111,23 @@
+                       reg = <0x48200000 0x1000>;
+               };
++              edma: edma@49000000 {
++                      compatible = "ti,edma3";
++                      ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
++                      reg =   <0x49000000 0x10000>,
++                              <0x44e10f90 0x10>;
++                      interrupts = <12 13 14>;
++                      #dma-cells = <1>;
++                      dma-channels = <64>;
++                      ti,edma-regions = <4>;
++                      ti,edma-slots = <256>;
++              };
++
+               gpio0: gpio@44e07000 {
+                       compatible = "ti,omap4-gpio";
+                       ti,hwmods = "gpio1";
++                      clocks = <&dpll_core_m4_div2_ck>, <&gpio0_dbclk>;
++                      clock-names = "fck", "dbclk";
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       interrupt-controller;
+@@ -114,6 +139,8 @@
+               gpio1: gpio@4804c000 {
+                       compatible = "ti,omap4-gpio";
+                       ti,hwmods = "gpio2";
++                      clocks = <&l4ls_gclk>, <&gpio1_dbclk>;
++                      clock-names = "fck", "dbclk";
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       interrupt-controller;
+@@ -125,6 +152,8 @@
+               gpio2: gpio@481ac000 {
+                       compatible = "ti,omap4-gpio";
+                       ti,hwmods = "gpio3";
++                      clocks = <&l4ls_gclk>, <&gpio2_dbclk>;
++                      clock-names = "fck", "dbclk";
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       interrupt-controller;
+@@ -136,6 +165,8 @@
+               gpio3: gpio@481ae000 {
+                       compatible = "ti,omap4-gpio";
+                       ti,hwmods = "gpio4";
++                      clocks = <&l4ls_gclk>, <&gpio3_dbclk>;
++                      clock-names = "fck", "dbclk";
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       interrupt-controller;
+@@ -147,6 +178,8 @@
+               uart0: serial@44e09000 {
+                       compatible = "ti,omap3-uart";
+                       ti,hwmods = "uart1";
++                      clocks = <&dpll_per_m2_div4_wkupdm_ck>;
++                      clock-names = "fck";
+                       clock-frequency = <48000000>;
+                       reg = <0x44e09000 0x2000>;
+                       interrupts = <72>;
+@@ -156,6 +189,8 @@
+               uart1: serial@48022000 {
+                       compatible = "ti,omap3-uart";
+                       ti,hwmods = "uart2";
++                      clocks = <&dpll_per_m2_div4_ck>;
++                      clock-names = "fck";
+                       clock-frequency = <48000000>;
+                       reg = <0x48022000 0x2000>;
+                       interrupts = <73>;
+@@ -165,6 +200,8 @@
+               uart2: serial@48024000 {
+                       compatible = "ti,omap3-uart";
+                       ti,hwmods = "uart3";
++                      clocks = <&dpll_per_m2_div4_ck>;
++                      clock-names = "fck";
+                       clock-frequency = <48000000>;
+                       reg = <0x48024000 0x2000>;
+                       interrupts = <74>;
+@@ -174,6 +211,8 @@
+               uart3: serial@481a6000 {
+                       compatible = "ti,omap3-uart";
+                       ti,hwmods = "uart4";
++                      clocks = <&dpll_per_m2_div4_ck>;
++                      clock-names = "fck";
+                       clock-frequency = <48000000>;
+                       reg = <0x481a6000 0x2000>;
+                       interrupts = <44>;
+@@ -183,6 +222,8 @@
+               uart4: serial@481a8000 {
+                       compatible = "ti,omap3-uart";
+                       ti,hwmods = "uart5";
++                      clocks = <&dpll_per_m2_div4_ck>;
++                      clock-names = "fck";
+                       clock-frequency = <48000000>;
+                       reg = <0x481a8000 0x2000>;
+                       interrupts = <45>;
+@@ -192,6 +233,8 @@
+               uart5: serial@481aa000 {
+                       compatible = "ti,omap3-uart";
+                       ti,hwmods = "uart6";
++                      clocks = <&dpll_per_m2_div4_ck>;
++                      clock-names = "fck";
+                       clock-frequency = <48000000>;
+                       reg = <0x481aa000 0x2000>;
+                       interrupts = <46>;
+@@ -203,6 +246,8 @@
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       ti,hwmods = "i2c1";
++                      clocks = <&dpll_per_m2_div4_wkupdm_ck>;
++                      clock-names = "fck";
+                       reg = <0x44e0b000 0x1000>;
+                       interrupts = <70>;
+                       status = "disabled";
+@@ -213,6 +258,8 @@
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       ti,hwmods = "i2c2";
++                      clocks = <&dpll_per_m2_div4_ck>;
++                      clock-names = "fck";
+                       reg = <0x4802a000 0x1000>;
+                       interrupts = <71>;
+                       status = "disabled";
+@@ -223,14 +270,62 @@
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       ti,hwmods = "i2c3";
++                      clocks = <&dpll_per_m2_div4_ck>;
++                      clock-names = "fck";
+                       reg = <0x4819c000 0x1000>;
+                       interrupts = <30>;
+                       status = "disabled";
+               };
++              mmc1: mmc@48060000 {
++                      compatible = "ti,omap4-hsmmc";
++                      ti,hwmods = "mmc1";
++                      clocks = <&mmc_clk>, <&clkdiv32k_ick>;
++                      clock-names = "fck", "mmchsdb_fck";
++                      ti,dual-volt;
++                      ti,needs-special-reset;
++                      ti,needs-special-hs-handling;
++                      dmas = <&edma 24
++                              &edma 25>;
++                      dma-names = "tx", "rx";
++                      interrupts = <64>;
++                      interrupt-parent = <&intc>;
++                      reg = <0x48060000 0x1000>;
++                      status = "disabled";
++              };
++
++              mmc2: mmc@481d8000 {
++                      compatible = "ti,omap4-hsmmc";
++                      ti,hwmods = "mmc2";
++                      clocks = <&mmc_clk>, <&clkdiv32k_ick>;
++                      clock-names = "fck", "mmchsdb_fck";
++                      ti,needs-special-reset;
++                      dmas = <&edma 2
++                              &edma 3>;
++                      dma-names = "tx", "rx";
++                      interrupts = <28>;
++                      interrupt-parent = <&intc>;
++                      reg = <0x481d8000 0x1000>;
++                      status = "disabled";
++              };
++
++              mmc3: mmc@47810000 {
++                      compatible = "ti,omap4-hsmmc";
++                      ti,hwmods = "mmc3";
++                      clocks = <&mmc_clk>, <&clkdiv32k_ick>;
++                      clock-names = "fck", "mmchsdb_fck";
++                      ti,needs-special-reset;
++                      interrupts = <29>;
++                      interrupt-parent = <&intc>;
++                      reg = <0x47810000 0x1000>;
++                      status = "disabled";
++              };
++
+               wdt2: wdt@44e35000 {
+                       compatible = "ti,omap3-wdt";
+                       ti,hwmods = "wd_timer2";
++                      clocks = <&wdt1_fck>;
++                      clock-names = "fck";
+                       reg = <0x44e35000 0x1000>;
+                       interrupts = <91>;
+               };
+@@ -238,6 +333,8 @@
+               dcan0: d_can@481cc000 {
+                       compatible = "bosch,d_can";
+                       ti,hwmods = "d_can0";
++                      clocks = <&dcan0_fck>;
++                      clock-names = "fck";
+                       reg = <0x481cc000 0x2000
+                               0x44e10644 0x4>;
+                       interrupts = <52>;
+@@ -247,17 +344,32 @@
+               dcan1: d_can@481d0000 {
+                       compatible = "bosch,d_can";
+                       ti,hwmods = "d_can1";
++                      clocks = <&dcan1_fck>;
++                      clock-names = "fck";
+                       reg = <0x481d0000 0x2000
+                               0x44e10644 0x4>;
+                       interrupts = <55>;
+                       status = "disabled";
+               };
++              mailbox: mailbox@480C8000 {
++                      compatible = "ti,omap4-mailbox";
++                      reg = <0x480C8000 0x200>;
++                      interrupts = <77>;
++                      ti,hwmods = "mailbox";
++                      ti,mbox-num-users = <4>;
++                      ti,mbox-num-fifos = <8>;
++                      ti,mbox-names = "wkup_m3";
++                      ti,mbox-data = <0 0 0 0>;
++              };
++
+               timer1: timer@44e31000 {
+                       compatible = "ti,am335x-timer-1ms";
+                       reg = <0x44e31000 0x400>;
+                       interrupts = <67>;
+                       ti,hwmods = "timer1";
++                      clocks = <&timer1_fck>;
++                      clock-names = "fck";
+                       ti,timer-alwon;
+               };
+@@ -266,6 +378,8 @@
+                       reg = <0x48040000 0x400>;
+                       interrupts = <68>;
+                       ti,hwmods = "timer2";
++                      clocks = <&timer2_fck>;
++                      clock-names = "fck";
+               };
+               timer3: timer@48042000 {
+@@ -273,6 +387,8 @@
+                       reg = <0x48042000 0x400>;
+                       interrupts = <69>;
+                       ti,hwmods = "timer3";
++                      clocks = <&timer3_fck>;
++                      clock-names = "fck";
+               };
+               timer4: timer@48044000 {
+@@ -280,6 +396,8 @@
+                       reg = <0x48044000 0x400>;
+                       interrupts = <92>;
+                       ti,hwmods = "timer4";
++                      clocks = <&timer4_fck>;
++                      clock-names = "fck";
+                       ti,timer-pwm;
+               };
+@@ -288,6 +406,8 @@
+                       reg = <0x48046000 0x400>;
+                       interrupts = <93>;
+                       ti,hwmods = "timer5";
++                      clocks = <&timer5_fck>;
++                      clock-names = "fck";
+                       ti,timer-pwm;
+               };
+@@ -296,6 +416,8 @@
+                       reg = <0x48048000 0x400>;
+                       interrupts = <94>;
+                       ti,hwmods = "timer6";
++                      clocks = <&timer6_fck>;
++                      clock-names = "fck";
+                       ti,timer-pwm;
+               };
+@@ -304,6 +426,8 @@
+                       reg = <0x4804a000 0x400>;
+                       interrupts = <95>;
+                       ti,hwmods = "timer7";
++                      clocks = <&timer7_fck>;
++                      clock-names = "fck";
+                       ti,timer-pwm;
+               };
+@@ -313,6 +437,8 @@
+                       interrupts = <75
+                                     76>;
+                       ti,hwmods = "rtc";
++                      clocks = <&clk_32768_ck>;
++                      clock-names = "fck";
+               };
+               spi0: spi@48030000 {
+@@ -323,6 +449,13 @@
+                       interrupts = <65>;
+                       ti,spi-num-cs = <2>;
+                       ti,hwmods = "spi0";
++                      clocks = <&dpll_per_m2_div4_ck>;
++                      clock-names = "fck";
++                      dmas = <&edma 16
++                              &edma 17
++                              &edma 18
++                              &edma 19>;
++                      dma-names = "tx0", "rx0", "tx1", "rx1";
+                       status = "disabled";
+               };
+@@ -334,6 +467,13 @@
+                       interrupts = <125>;
+                       ti,spi-num-cs = <2>;
+                       ti,hwmods = "spi1";
++                      clocks = <&dpll_per_m2_div4_ck>;
++                      clock-names = "fck";
++                      dmas = <&edma 42
++                              &edma 43
++                              &edma 44
++                              &edma 45>;
++                      dma-names = "tx0", "rx0", "tx1", "rx1";
+                       status = "disabled";
+               };
+@@ -345,6 +485,8 @@
+                       #size-cells = <1>;
+                       ti,hwmods = "usb_otg_hs";
+                       status = "disabled";
++                      clocks = <&usbotg_fck>;
++                      clock-names = "fck";
+                       ctrl_mod: control@44e10000 {
+                               compatible = "ti,am335x-usb-ctrl-module";
+@@ -469,6 +611,8 @@
+                       compatible = "ti,am33xx-pwmss";
+                       reg = <0x48300000 0x10>;
+                       ti,hwmods = "epwmss0";
++                      clocks = <&l4ls_gclk>;
++                      clock-names = "fck";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       status = "disabled";
+@@ -481,6 +625,8 @@
+                               #pwm-cells = <3>;
+                               reg = <0x48300100 0x80>;
+                               ti,hwmods = "ecap0";
++                      clocks = <&l4ls_gclk>;
++                      clock-names = "fck";
+                               status = "disabled";
+                       };
+@@ -489,6 +635,8 @@
+                               #pwm-cells = <3>;
+                               reg = <0x48300200 0x80>;
+                               ti,hwmods = "ehrpwm0";
++                      clocks = <&l4ls_gclk>;
++                      clock-names = "fck";
+                               status = "disabled";
+                       };
+               };
+@@ -497,6 +645,8 @@
+                       compatible = "ti,am33xx-pwmss";
+                       reg = <0x48302000 0x10>;
+                       ti,hwmods = "epwmss1";
++                      clocks = <&l4ls_gclk>;
++                      clock-names = "fck";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       status = "disabled";
+@@ -509,6 +659,8 @@
+                               #pwm-cells = <3>;
+                               reg = <0x48302100 0x80>;
+                               ti,hwmods = "ecap1";
++                      clocks = <&l4ls_gclk>;
++                      clock-names = "fck";
+                               status = "disabled";
+                       };
+@@ -517,6 +669,8 @@
+                               #pwm-cells = <3>;
+                               reg = <0x48302200 0x80>;
+                               ti,hwmods = "ehrpwm1";
++                      clocks = <&l4ls_gclk>;
++                      clock-names = "fck";
+                               status = "disabled";
+                       };
+               };
+@@ -525,6 +679,8 @@
+                       compatible = "ti,am33xx-pwmss";
+                       reg = <0x48304000 0x10>;
+                       ti,hwmods = "epwmss2";
++                      clocks = <&l4ls_gclk>;
++                      clock-names = "fck";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       status = "disabled";
+@@ -537,6 +693,8 @@
+                               #pwm-cells = <3>;
+                               reg = <0x48304100 0x80>;
+                               ti,hwmods = "ecap2";
++                      clocks = <&l4ls_gclk>;
++                      clock-names = "fck";
+                               status = "disabled";
+                       };
+@@ -545,6 +703,8 @@
+                               #pwm-cells = <3>;
+                               reg = <0x48304200 0x80>;
+                               ti,hwmods = "ehrpwm2";
++                      clocks = <&l4ls_gclk>;
++                      clock-names = "fck";
+                               status = "disabled";
+                       };
+               };
+@@ -552,6 +712,8 @@
+               mac: ethernet@4a100000 {
+                       compatible = "ti,cpsw";
+                       ti,hwmods = "cpgmac0";
++                      clocks = <&cpsw_125mhz_gclk>;
++                      clock-names = "fck";
+                       cpdma_channels = <8>;
+                       ale_entries = <1024>;
+                       bd_ram_size = <0x2000>;
+@@ -581,6 +743,8 @@
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               ti,hwmods = "davinci_mdio";
++                      clocks = <&cpsw_125mhz_gclk>;
++                      clock-names = "fck";
+                               bus_freq = <1000000>;
+                               reg = <0x4a101000 0x100>;
+                       };
+@@ -594,19 +758,33 @@
+                               /* Filled in by U-Boot */
+                               mac-address = [ 00 00 00 00 00 00 ];
+                       };
++
++                      phy_sel: cpsw-phy-sel@44e10650 {
++                              compatible = "ti,am3352-cpsw-phy-sel";
++                              reg= <0x44e10650 0x4>;
++                              reg-names = "gmii-sel";
++                      };
+               };
+               ocmcram: ocmcram@40300000 {
+                       compatible = "ti,am3352-ocmcram";
+                       reg = <0x40300000 0x10000>;
+                       ti,hwmods = "ocmcram";
++                      clocks = <&l3_gclk>;
++                      clock-names = "fck";
+               };
+               wkup_m3: wkup_m3@44d00000 {
+                       compatible = "ti,am3353-wkup-m3";
+-                      reg = <0x44d00000 0x4000        /* M3 UMEM */
+-                             0x44d80000 0x2000>;      /* M3 DMEM */
++                      reg = <0x44d00000 0x4000
++                             0x44d80000 0x2000
++                             0x44e11324 0x0024>;
++                      reg-names = "m3_umem", "m3_dmem", "ipc_regs";
++                      interrupts = <78>;
+                       ti,hwmods = "wkup_m3";
++                      ti,no-reset;
++                      clocks = <&dpll_core_m4_div2_ck>;
++                      clock-names = "fck";
+               };
+               elm: elm@48080000 {
+@@ -614,6 +792,8 @@
+                       reg = <0x48080000 0x2000>;
+                       interrupts = <4>;
+                       ti,hwmods = "elm";
++                      clocks = <&l4ls_gclk>;
++                      clock-names = "fck";
+                       status = "disabled";
+               };
+@@ -623,6 +803,8 @@
+                       interrupt-parent = <&intc>;
+                       interrupts = <16>;
+                       ti,hwmods = "adc_tsc";
++                      clocks = <&adc_tsc_fck>;
++                      clock-names = "fck";
+                       status = "disabled";
+                       tsc {
+@@ -637,6 +819,9 @@
+               gpmc: gpmc@50000000 {
+                       compatible = "ti,am3352-gpmc";
+                       ti,hwmods = "gpmc";
++                      ti,no-idle;
++                      clocks = <&l3s_gclk>;
++                      clock-names = "fck";
+                       reg = <0x50000000 0x2000>;
+                       interrupts = <100>;
+                       gpmc,num-cs = <7>;
+@@ -645,5 +830,102 @@
+                       #size-cells = <1>;
+                       status = "disabled";
+               };
++
++              prcm: prcm@44e00000 {
++                      compatible = "ti,am3352-prcm";
++                      reg = <0x44e00000 0x1300>;
++                      #reset-cells = <1>;
++              };
++
++              sham: sham@53100000 {
++                      compatible = "ti,omap4-sham";
++                      ti,hwmods = "sham";
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      reg = <0x53100000 0x200>;
++                      interrupt-parent = <&intc>;
++                      interrupts = <109>;
++                      dmas = <&edma 36>;
++                      dma-names = "rx";
++                      clocks = <&l3_gclk>;
++                      clock-names = "fck";
++              };
++
++              aes: aes@53500000 {
++                      compatible = "ti,omap4-aes";
++                      ti,hwmods = "aes";
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      reg = <0x53500000 0xa0>;
++                      interrupt-parent = <&intc>;
++                      interrupts = <103>;
++                      dmas = <&edma 6
++                              &edma 5>;
++                      dma-names = "tx", "rx";
++                      clocks = <&aes0_fck>;
++                      clock-names = "fck";
++              };
++
++              rng: rng@48310000 {
++                      compatible = "ti,omap4-rng";
++                      ti,hwmods = "rng";
++                      reg = <0x48310000 0x2000>;
++                      interrupts = <111>;
++                      clocks = <&rng_fck>;
++                      clock-names = "fck";
++              };
++
++              lcdc: lcdc@0x4830e000 {
++                      compatible = "ti,am33xx-tilcdc";
++                      reg = <0x4830e000 0x1000>;
++                      interrupt-parent = <&intc>;
++                      interrupts = <36>;
++                      clocks = <&lcd_gclk>;
++                      clock-names = "fck";
++                      ti,hwmods = "lcdc";
++                      status = "disabled";
++              };
++
++              mcasp0: mcasp@48038000 {
++                      compatible = "ti,omap2-mcasp-audio";
++                      ti,hwmods = "mcasp0";
++                      reg = <0x48038000 0x2000>,
++                            <0x46400000 0x400000>;
++                      reg-names = "mpu", "dma";
++                      interrupts = <80 81>;
++                      interrupts-names = "tx", "rx";
++                      status = "disabled";
++                      dmas = <&edma 8
++                              &edma 9>;
++                      dma-names = "tx", "rx";
++              };
++
++              mcasp1: mcasp@4803C000 {
++                      compatible = "ti,omap2-mcasp-audio";
++                      ti,hwmods = "mcasp1";
++                      reg = <0x4803C000 0x2000>,
++                            <0x46400000 0x400000>;
++                      reg-names = "mpu", "dma";
++                      interrupts = <82 83>;
++                      interrupts-names = "tx", "rx";
++                      status = "disabled";
++                      dmas = <&edma 10
++                              &edma 11>;
++                      dma-names = "tx", "rx";
++              };
++      };
++
++      clocks {
++              #address-cells = <1>;
++              #size-cells = <1>;
++              ranges;
++              /include/ "am33xx-clocks.dtsi"
+       };
++
++       clockdomains {
++               clk_24mhz_clkdm: clk_24mhz_clkdm {
++                       compatible = "ti,clockdomain";
++                       clocks = <&clkdiv32k_ick>;
++               };
++       };
+ };
+--- /dev/null
++++ b/arch/arm/boot/dts/am3517.dtsi
+@@ -0,0 +1,116 @@
++/*
++ * Device Tree Source for AM3517 SoC
++ *
++ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2.  This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++#include "omap3.dtsi"
++
++/ {
++      cpus {
++              cpu@0 {
++                      /* OMAP343x/OMAP35xx variants OPP1-5 */
++                      operating-points = <
++                              /* kHz    uV */
++                              125000   975000
++                              250000  1075000
++                              500000  1200000
++                              550000  1270000
++                              600000  1350000
++                      >;
++                      clock-latency = <300000>; /* From legacy driver */
++              };
++      };
++
++      clocks {
++              #address-cells = <1>;
++              #size-cells = <1>;
++              ranges;
++              /include/ "am35xx-clocks.dtsi"
++              /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
++      };
++
++      clockdomains {
++              dss_clkdm: dss_clkdm {
++                      compatible = "ti,clockdomain";
++                      clocks = <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
++              };
++
++              usbhost_clkdm: usbhost_clkdm {
++                      compatible = "ti,clockdomain";
++                      clocks = <&usbhost_48m_fck>, <&usbhost_ick>;
++              };
++
++              core_l4_clkdm: core_l4_clkdm {
++                      compatible = "ti,clockdomain";
++                      clocks = <&mmchs1_ick>, <&mmchs2_ick>, <&hdq_fck>,
++                               <&uart1_ick>, <&mcspi4_fck>, <&i2c3_fck>,
++                               <&mcspi2_ick>, <&uart2_ick>, <&mcspi3_ick>,
++                               <&i2c1_fck>, <&hdq_ick>, <&sha12_ick>,
++                               <&mcbsp5_ick>, <&mcspi3_fck>, <&aes2_ick>,
++                               <&mcspi1_ick>, <&uart2_fck>, <&mmchs2_fck>,
++                               <&mmchs1_fck>, <&i2c3_ick>, <&mcspi1_fck>,
++                               <&mcspi4_ick>, <&omapctrl_ick>, <&mcbsp1_ick>,
++                               <&mcspi2_fck>, <&gpt10_ick>, <&i2c2_fck>,
++                               <&i2c2_ick>, <&gpt11_ick>, <&i2c1_ick>,
++                               <&uart1_fck>;
++              };
++
++              wkup_clkdm: wkup_clkdm {
++                      compatible = "ti,clockdomain";
++                      clocks = <&wdt1_ick>, <&gpt12_ick>, <&gpio1_ick>,
++                               <&gpt1_ick>, <&omap_32ksync_ick>, <&wdt2_ick>,
++                               <&wdt2_fck>;
++              };
++
++              dpll4_clkdm: dpll4_clkdm {
++                      compatible = "ti,clockdomain";
++                      clocks = <&dpll4_ck>;
++              };
++
++              core_l3_clkdm: core_l3_clkdm {
++                      compatible = "ti,clockdomain";
++                      clocks = <&sdrc_ick>;
++              };
++
++              per_clkdm: per_clkdm {
++                      compatible = "ti,clockdomain";
++                      clocks = <&gpt2_ick>, <&uart3_fck>, <&gpio3_ick>,
++                               <&mcbsp2_ick>, <&gpt6_ick>, <&mcbsp4_ick>,
++                               <&gpt4_ick>, <&mcbsp3_ick>, <&gpt8_ick>,
++                               <&uart3_ick>, <&gpt5_ick>, <&gpt7_ick>,
++                               <&gpio2_ick>, <&gpio6_ick>, <&gpt9_ick>,
++                               <&gpt3_ick>, <&gpio5_ick>, <&wdt3_ick>,
++                               <&gpio4_ick>, <&wdt3_fck>, <&uart4_ick>;
++              };
++
++              emu_clkdm: emu_clkdm {
++                      compatible = "ti,clockdomain";
++                      clocks = <&emu_src_ck>;
++              };
++
++              sgx_clkdm: sgx_clkdm {
++                      compatible = "ti,clockdomain";
++                      clocks = <&sgx_ick>;
++              };
++
++              dpll3_clkdm: dpll3_clkdm {
++                      compatible = "ti,clockdomain";
++                      clocks = <&dpll3_ck>;
++              };
++
++              dpll5_clkdm: dpll5_clkdm {
++                      compatible = "ti,clockdomain";
++                      clocks = <&dpll5_ck>;
++              };
++
++              dpll1_clkdm: dpll1_clkdm {
++                      compatible = "ti,clockdomain";
++                      clocks = <&dpll1_ck>;
++              };
++      };
++};
+--- a/arch/arm/boot/dts/am3517-evm.dts
++++ b/arch/arm/boot/dts/am3517-evm.dts
+@@ -7,7 +7,7 @@
+  */
+ /dts-v1/;
+-#include "omap34xx.dtsi"
++#include "am3517.dtsi"
+ / {
+       model = "TI AM3517 EVM (AM3517/05)";
+--- a/arch/arm/boot/dts/am3517_mt_ventoux.dts
++++ b/arch/arm/boot/dts/am3517_mt_ventoux.dts
+@@ -7,7 +7,7 @@
+  */
+ /dts-v1/;
+-#include "omap34xx.dtsi"
++#include "am3517.dtsi"
+ / {
+       model = "TeeJet Mt.Ventoux";
+--- /dev/null
++++ b/arch/arm/boot/dts/am35xx-clocks.dtsi
+@@ -0,0 +1,101 @@
++/*
++ * Device Tree Source for AM35xx clock data
++ *
++ * Copyright (C) 2013 Texas Instruments, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++ipss_ick: ipss_ick@48004a10 {
++      #clock-cells = <0>;
++      compatible = "ti,am35xx-interface-clock";
++      clocks = <&core_l3_ick>;
++      reg = <0x48004a10 0x4>;
++      ti,enable-bit = <4>;
++};
++
++rmii_ck: rmii_ck {
++      #clock-cells = <0>;
++      compatible = "fixed-clock";
++      clock-frequency = <50000000>;
++};
++
++pclk_ck: pclk_ck {
++      #clock-cells = <0>;
++      compatible = "fixed-clock";
++      clock-frequency = <27000000>;
++};
++
++emac_ick: emac_ick@4800259c {
++      #clock-cells = <0>;
++      compatible = "ti,am35xx-gate-clock";
++      clocks = <&ipss_ick>;
++      reg = <0x4800259c 0x4>;
++      ti,enable-bit = <1>;
++};
++
++emac_fck: emac_fck@4800259c {
++      #clock-cells = <0>;
++      compatible = "gate-clock";
++      clocks = <&rmii_ck>;
++      reg = <0x4800259c 0x4>;
++      bit-shift = <9>;
++};
++
++vpfe_ick: vpfe_ick@4800259c {
++      #clock-cells = <0>;
++      compatible = "ti,am35xx-gate-clock";
++      clocks = <&ipss_ick>;
++      reg = <0x4800259c 0x4>;
++      ti,enable-bit = <2>;
++};
++
++vpfe_fck: vpfe_fck@4800259c {
++      #clock-cells = <0>;
++      compatible = "gate-clock";
++      clocks = <&pclk_ck>;
++      reg = <0x4800259c 0x4>;
++      bit-shift = <10>;
++};
++
++hsotgusb_ick: hsotgusb_ick@4800259c {
++      #clock-cells = <0>;
++      compatible = "ti,am35xx-gate-clock";
++      clocks = <&ipss_ick>;
++      reg = <0x4800259c 0x4>;
++      ti,enable-bit = <0>;
++};
++
++hsotgusb_fck_am35xx: hsotgusb_fck_am35xx@4800259c {
++      #clock-cells = <0>;
++      compatible = "gate-clock";
++      clocks = <&sys_ck>;
++      reg = <0x4800259c 0x4>;
++      bit-shift = <8>;
++};
++
++hecc_ck: hecc_ck@4800259c {
++      #clock-cells = <0>;
++      compatible = "ti,am35xx-gate-clock";
++      clocks = <&sys_ck>;
++      reg = <0x4800259c 0x4>;
++      ti,enable-bit = <3>;
++};
++
++uart4_ick_am35xx: uart4_ick_am35xx@48004a10 {
++      #clock-cells = <0>;
++      compatible = "ti,omap3-interface-clock";
++      clocks = <&core_l4_ick>;
++      reg = <0x48004a10 0x4>;
++      ti,enable-bit = <23>;
++};
++
++uart4_fck_am35xx: uart4_fck_am35xx@48004a00 {
++      #clock-cells = <0>;
++      compatible = "ti,gate-clock";
++      clocks = <&core_48m_fck>;
++      reg = <0x48004a00 0x4>;
++      ti,enable-bit = <23>;
++};
+--- a/arch/arm/boot/dts/am4372.dtsi
++++ b/arch/arm/boot/dts/am4372.dtsi
+@@ -8,6 +8,7 @@
+  * kind, whether express or implied.
+  */
++#include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include "skeleton.dtsi"
+@@ -18,12 +19,21 @@
+       aliases {
++              i2c0 = &i2c0;
++              i2c1 = &i2c1;
++              i2c2 = &i2c2;
+               serial0 = &uart0;
++              ethernet0 = &cpsw_emac0;
++              ethernet1 = &cpsw_emac1;
+       };
+       cpus {
++              #address-cells = <1>;
++              #size-cells = <0>;
+               cpu@0 {
+                       compatible = "arm,cortex-a9";
++                      device_type = "cpu";
++                      reg = <0>;
+               };
+       };
+@@ -35,16 +45,124 @@
+                     <0x48240100 0x0100>;
+       };
++      l2-cache-controller@48242000 {
++              compatible = "arm,pl310-cache";
++              reg = <0x48242000 0x1000>;
++              cache-unified;
++              cache-level = <2>;
++      };
++
++      am43xx_pinmux: pinmux@44e10800 {
++              compatible = "pinctrl-single";
++              reg = <0x44e10800 0x31c>;
++              #address-cells = <1>;
++              #size-cells = <0>;
++              pinctrl-single,register-width = <32>;
++              pinctrl-single,function-mask = <0xffffffff>;
++      };
++
+       ocp {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
++              ti,hwmods = "l3_main";
++              clocks = <&l3_gclk>;
++              clock-names = "fck";
++
++              edma: edma@49000000 {
++                      compatible = "ti,edma3";
++                      ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
++                      reg =   <0x49000000 0x10000>,
++                              <0x44e10f90 0x10>;
++                      interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
++                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
++                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
++                      #dma-cells = <1>;
++                      dma-channels = <64>;
++                      ti,edma-regions = <4>;
++                      ti,edma-slots = <256>;
++              };
+               uart0: serial@44e09000 {
+                       compatible = "ti,am4372-uart","ti,omap2-uart";
+                       reg = <0x44e09000 0x2000>;
+                       interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
++                      ti,hwmods = "uart1";
++                      clocks = <&dpll_per_m2_div4_wkupdm_ck>;
++                      clock-names = "fck";
++              };
++
++              uart1: serial@48022000 {
++                      compatible = "ti,am4372-uart","ti,omap2-uart";
++                      reg = <0x48022000 0x2000>;
++                      interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
++                      ti,hwmods = "uart2";
++                      clocks = <&dpll_per_m2_div4_ck>;
++                      clock-names = "fck";
++                      status = "disabled";
++              };
++
++              uart2: serial@48024000 {
++                      compatible = "ti,am4372-uart","ti,omap2-uart";
++                      reg = <0x48024000 0x2000>;
++                      interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
++                      ti,hwmods = "uart3";
++                      clocks = <&dpll_per_m2_div4_ck>;
++                      clock-names = "fck";
++                      status = "disabled";
++              };
++
++              uart3: serial@481a6000 {
++                      compatible = "ti,am4372-uart","ti,omap2-uart";
++                      reg = <0x481a6000 0x2000>;
++                      interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
++                      ti,hwmods = "uart4";
++                      clocks = <&dpll_per_m2_div4_ck>;
++                      clock-names = "fck";
++                      status = "disabled";
++              };
++
++              uart4: serial@481a8000 {
++                      compatible = "ti,am4372-uart","ti,omap2-uart";
++                      reg = <0x481a8000 0x2000>;
++                      interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
++                      ti,hwmods = "uart5";
++                      clocks = <&dpll_per_m2_div4_ck>;
++                      clock-names = "fck";
++                      status = "disabled";
++              };
++
++              uart5: serial@481aa000 {
++                      compatible = "ti,am4372-uart","ti,omap2-uart";
++                      reg = <0x481aa000 0x2000>;
++                      interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
++                      ti,hwmods = "uart6";
++                      clocks = <&dpll_per_m2_div4_ck>;
++                      clock-names = "fck";
++                      status = "disabled";
++              };
++
++              mailbox: mailbox@480C8000 {
++                      compatible = "ti,omap4-mailbox";
++                      reg = <0x480C8000 0x200>;
++                      interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
++                      ti,hwmods = "mailbox";
++                      ti,mbox-num-users = <4>;
++                      ti,mbox-num-fifos = <8>;
++                      ti,mbox-names = "wkup_m3";
++                      ti,mbox-data = <0 0 0 0>;
++              };
++
++              qspi: qspi@47900000 {
++                      compatible = "ti,am4372-qspi";
++                      reg = <0x47900000 0x100>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      ti,hwmods = "qspi";
++                      interrupts = <0 138 0x4>;
++                      num-cs = <4>;
++                      mmap_read;
+               };
+               timer1: timer@44e31000 {
+@@ -52,17 +170,818 @@
+                       reg = <0x44e31000 0x400>;
+                       interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+                       ti,timer-alwon;
++                      ti,hwmods = "timer1";
++                      clocks = <&timer1_fck>;
++                      clock-names = "fck";
+               };
+               timer2: timer@48040000  {
+                       compatible = "ti,am4372-timer","ti,am335x-timer";
+                       reg = <0x48040000  0x400>;
+                       interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
++                      ti,hwmods = "timer2";
++                      clocks = <&timer2_fck>;
++                      clock-names = "fck";
++              };
++
++              timer3: timer@48042000 {
++                      compatible = "ti,am4372-timer","ti,am335x-timer";
++                      reg = <0x48042000 0x400>;
++                      interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
++                      ti,hwmods = "timer3";
++                      clocks = <&timer3_fck>;
++                      clock-names = "fck";
++                      status = "disabled";
++              };
++
++              timer4: timer@48044000 {
++                      compatible = "ti,am4372-timer","ti,am335x-timer";
++                      reg = <0x48044000 0x400>;
++                      interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
++                      ti,timer-pwm;
++                      ti,hwmods = "timer4";
++                      clocks = <&timer4_fck>;
++                      clock-names = "fck";
++                      status = "disabled";
++              };
++
++              timer5: timer@48046000 {
++                      compatible = "ti,am4372-timer","ti,am335x-timer";
++                      reg = <0x48046000 0x400>;
++                      interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
++                      ti,timer-pwm;
++                      ti,hwmods = "timer5";
++                      clocks = <&timer5_fck>;
++                      clock-names = "fck";
++                      status = "disabled";
++              };
++
++              timer6: timer@48048000 {
++                      compatible = "ti,am4372-timer","ti,am335x-timer";
++                      reg = <0x48048000 0x400>;
++                      interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
++                      ti,timer-pwm;
++                      ti,hwmods = "timer6";
++                      clocks = <&timer6_fck>;
++                      clock-names = "fck";
++                      status = "disabled";
++              };
++
++              timer7: timer@4804a000 {
++                      compatible = "ti,am4372-timer","ti,am335x-timer";
++                      reg = <0x4804a000 0x400>;
++                      interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
++                      ti,timer-pwm;
++                      ti,hwmods = "timer7";
++                      clocks = <&timer7_fck>;
++                      clock-names = "fck";
++                      status = "disabled";
++              };
++
++              timer8: timer@481c1000 {
++                      compatible = "ti,am4372-timer","ti,am335x-timer";
++                      reg = <0x481c1000 0x400>;
++                      interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
++                      ti,hwmods = "timer8";
++                      clocks = <&timer8_fck>;
++                      clock-names = "fck";
++                      status = "disabled";
++              };
++
++              timer9: timer@4833d000 {
++                      compatible = "ti,am4372-timer","ti,am335x-timer";
++                      reg = <0x4833d000 0x400>;
++                      interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
++                      ti,hwmods = "timer9";
++                      clocks = <&timer9_fck>;
++                      clock-names = "fck";
++                      status = "disabled";
++              };
++
++              timer10: timer@4833f000 {
++                      compatible = "ti,am4372-timer","ti,am335x-timer";
++                      reg = <0x4833f000 0x400>;
++                      interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
++                      ti,hwmods = "timer10";
++                      clocks = <&timer10_fck>;
++                      clock-names = "fck";
++                      status = "disabled";
++              };
++
++              timer11: timer@48341000 {
++                      compatible = "ti,am4372-timer","ti,am335x-timer";
++                      reg = <0x48341000 0x400>;
++                      interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
++                      ti,hwmods = "timer11";
++                      clocks = <&timer11_fck>;
++                      clock-names = "fck";
++                      status = "disabled";
+               };
+               counter32k: counter@44e86000 {
+                       compatible = "ti,am4372-counter32k","ti,omap-counter32k";
+                       reg = <0x44e86000 0x40>;
++                      ti,hwmods = "counter_32k";
++                      clocks = <&synctimer_32kclk>;
++                      clock-names = "fck";
++              };
++
++              rtc: rtc@44e3e000 {
++                      compatible = "ti,am4372-rtc","ti,da830-rtc";
++                      reg = <0x44e3e000 0x1000>;
++                      interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
++                                    GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
++                      ti,hwmods = "rtc";
++                      clocks = <&clk_32768_ck>;
++                      clock-names = "fck";
++                      status = "disabled";
++              };
++
++              wdt@44e35000 {
++                      compatible = "ti,am4372-wdt","ti,omap3-wdt";
++                      reg = <0x44e35000 0x1000>;
++                      interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
++                      ti,hwmods = "wd_timer2";
++                      clocks = <&wdt1_fck>;
++                      clock-names = "fck";
++              };
++
++              gpio0: gpio@44e07000 {
++                      compatible = "ti,am4372-gpio","ti,omap4-gpio";
++                      reg = <0x44e07000 0x1000>;
++                      interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
++                      gpio-controller;
++                      #gpio-cells = <2>;
++                      interrupt-controller;
++                      #interrupt-cells = <2>;
++                      ti,hwmods = "gpio1";
++                      clocks = <&sys_clkin_ck>, <&gpio0_dbclk>;
++                      clock-names = "fck", "dbclk";
++                      status = "disabled";
++              };
++
++              gpio1: gpio@4804c000 {
++                      compatible = "ti,am4372-gpio","ti,omap4-gpio";
++                      reg = <0x4804c000 0x1000>;
++                      interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
++                      gpio-controller;
++                      #gpio-cells = <2>;
++                      interrupt-controller;
++                      #interrupt-cells = <2>;
++                      ti,hwmods = "gpio2";
++                      clocks = <&l4ls_gclk>, <&gpio1_dbclk>;
++                      clock-names = "fck", "dbclk";
++                      status = "disabled";
++              };
++
++              gpio2: gpio@481ac000 {
++                      compatible = "ti,am4372-gpio","ti,omap4-gpio";
++                      reg = <0x481ac000 0x1000>;
++                      interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
++                      gpio-controller;
++                      #gpio-cells = <2>;
++                      interrupt-controller;
++                      #interrupt-cells = <2>;
++                      ti,hwmods = "gpio3";
++                      clocks = <&l4ls_gclk>, <&gpio2_dbclk>;
++                      clock-names = "fck", "dbclk";
++                      status = "disabled";
++              };
++
++              gpio3: gpio@481ae000 {
++                      compatible = "ti,am4372-gpio","ti,omap4-gpio";
++                      reg = <0x481ae000 0x1000>;
++                      interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
++                      gpio-controller;
++                      #gpio-cells = <2>;
++                      interrupt-controller;
++                      #interrupt-cells = <2>;
++                      ti,hwmods = "gpio4";
++                      clocks = <&l4ls_gclk>, <&gpio3_dbclk>;
++                      clock-names = "fck", "dbclk";
++                      status = "disabled";
++              };
++
++              gpio4: gpio@48320000 {
++                      compatible = "ti,am4372-gpio","ti,omap4-gpio";
++                      reg = <0x48320000 0x1000>;
++                      interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
++                      gpio-controller;
++                      #gpio-cells = <2>;
++                      interrupt-controller;
++                      #interrupt-cells = <2>;
++                      ti,hwmods = "gpio5";
++                      clocks = <&l4ls_gclk>, <&gpio4_dbclk>;
++                      clock-names = "fck", "dbclk";
++                      status = "disabled";
++              };
++
++              gpio5: gpio@48322000 {
++                      compatible = "ti,am4372-gpio","ti,omap4-gpio";
++                      reg = <0x48322000 0x1000>;
++                      interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
++                      gpio-controller;
++                      #gpio-cells = <2>;
++                      interrupt-controller;
++                      #interrupt-cells = <2>;
++                      ti,hwmods = "gpio6";
++                      clocks = <&l4ls_gclk>, <&gpio5_dbclk>;
++                      clock-names = "fck", "dbclk";
++                      status = "disabled";
++              };
++
++              i2c0: i2c@44e0b000 {
++                      compatible = "ti,am4372-i2c","ti,omap4-i2c";
++                      reg = <0x44e0b000 0x1000>;
++                      interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
++                      ti,hwmods = "i2c1";
++                      clocks = <&dpll_per_m2_div4_wkupdm_ck>;
++                      clock-names = "fck";
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      status = "disabled";
++
++                      tps: tps@24 {
++                              reg = <0x24>;
++                      };
++              };
++
++              i2c1: i2c@4802a000 {
++                      compatible = "ti,am4372-i2c","ti,omap4-i2c";
++                      reg = <0x4802a000 0x1000>;
++                      interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
++                      ti,hwmods = "i2c2";
++                      clocks = <&dpll_per_m2_div4_ck>;
++                      clock-names = "fck";
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      status = "disabled";
++              };
++
++              i2c2: i2c@4819c000 {
++                      compatible = "ti,am4372-i2c","ti,omap4-i2c";
++                      reg = <0x4819c000 0x1000>;
++                      interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
++                      ti,hwmods = "i2c3";
++                      clocks = <&dpll_per_m2_div4_ck>;
++                      clock-names = "fck";
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      status = "disabled";
++              };
++
++              spi0: spi@48030000 {
++                      compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
++                      reg = <0x48030000 0x400>;
++                      interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
++                      ti,hwmods = "spi0";
++                      clocks = <&dpll_per_m2_div4_ck>;
++                      clock-names = "fck";
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      status = "disabled";
+               };
++
++              mmc1: mmc@48060000 {
++                      compatible = "ti,omap4-hsmmc";
++                      reg = <0x48060000 0x1000>;
++                      ti,hwmods = "mmc1";
++                      clocks = <&mmc_clk>, <&clkdiv32k_ick>;
++                      clock-names = "fck", "mmchsdb_fck";
++                      ti,dual-volt;
++                      ti,needs-special-reset;
++                      dmas = <&edma 24
++                              &edma 25>;
++                      dma-names = "tx", "rx";
++                      interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
++                      status = "disabled";
++              };
++
++              mmc2: mmc@481d8000 {
++                      compatible = "ti,omap4-hsmmc";
++                      reg = <0x481d8000 0x1000>;
++                      ti,hwmods = "mmc2";
++                      clocks = <&mmc_clk>, <&clkdiv32k_ick>;
++                      clock-names = "fck", "mmchsdb_fck";
++                      ti,needs-special-reset;
++                      dmas = <&edma 2
++                              &edma 3>;
++                      dma-names = "tx", "rx";
++                      interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
++                      status = "disabled";
++              };
++
++              mmc3: mmc@47810000 {
++                      compatible = "ti,omap4-hsmmc";
++                      reg = <0x47810000 0x1000>;
++                      ti,hwmods = "mmc3";
++                      clocks = <&mmc_clk>, <&clkdiv32k_ick>;
++                      clock-names = "fck", "mmchsdb_fck";
++                      ti,needs-special-reset;
++                      interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
++                      status = "disabled";
++              };
++
++              spi1: spi@481a0000 {
++                      compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
++                      reg = <0x481a0000 0x400>;
++                      interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
++                      ti,hwmods = "spi1";
++                      clocks = <&dpll_per_m2_div4_ck>;
++                      clock-names = "fck";
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      status = "disabled";
++              };
++
++              spi2: spi@481a2000 {
++                      compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
++                      reg = <0x481a2000 0x400>;
++                      interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
++                      ti,hwmods = "spi2";
++                      clocks = <&dpll_per_m2_div4_ck>;
++                      clock-names = "fck";
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      status = "disabled";
++              };
++
++              spi3: spi@481a4000 {
++                      compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
++                      reg = <0x481a4000 0x400>;
++                      interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
++                      ti,hwmods = "spi3";
++                      clocks = <&dpll_per_m2_div4_ck>;
++                      clock-names = "fck";
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      status = "disabled";
++              };
++
++              spi4: spi@48345000 {
++                      compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
++                      reg = <0x48345000 0x400>;
++                      interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
++                      ti,hwmods = "spi4";
++                      clocks = <&dpll_per_m2_div4_ck>;
++                      clock-names = "fck";
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      status = "disabled";
++              };
++
++              mac: ethernet@4a100000 {
++                      compatible = "ti,am4372-cpsw","ti,cpsw";
++                      reg = <0x4a100000 0x800
++                             0x4a101200 0x100>;
++                      interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
++                                    GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
++                                    GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
++                                    GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
++                      #address-cells = <1>;
++                      #size-cells = <1>;
++                      ti,hwmods = "cpgmac0";
++                      clocks = <&cpsw_125mhz_gclk>;
++                      clock-names = "fck";
++                      cpdma_channels = <8>;
++                      ale_entries = <1024>;
++                      bd_ram_size = <0x2000>;
++                      no_bd_ram = <0>;
++                      rx_descs = <64>;
++                      mac_control = <0x20>;
++                      slaves = <2>;
++                      active_slave = <0>;
++                      cpts_clock_mult = <0x80000000>;
++                      cpts_clock_shift = <29>;
++                      ranges;
++                      status = "disabled";
++
++                      davinci_mdio: mdio@4a101000 {
++                              compatible = "ti,am4372-mdio","ti,davinci_mdio";
++                              reg = <0x4a101000 0x100>;
++                              #address-cells = <1>;
++                              #size-cells = <0>;
++                              ti,hwmods = "davinci_mdio";
++                              clocks = <&cpsw_125mhz_gclk>;
++                              clock-names = "fck";
++                              bus_freq = <1000000>;
++                              status = "disabled";
++                      };
++
++                      cpsw_emac0: slave@4a100200 {
++                              /* Filled in by U-Boot */
++                              mac-address = [ 00 00 00 00 00 00 ];
++                      };
++
++                      cpsw_emac1: slave@4a100300 {
++                              /* Filled in by U-Boot */
++                              mac-address = [ 00 00 00 00 00 00 ];
++                      };
++
++                      phy_sel: cpsw-phy-sel@44e10650 {
++                              compatible = "ti,am3352-cpsw-phy-sel";
++                              reg= <0x44e10650 0x4>;
++                              reg-names = "gmii-sel";
++                      };
++              };
++
++              epwmss0: epwmss@48300000 {
++                      compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
++                      reg = <0x48300000 0x10>;
++                      #address-cells = <1>;
++                      #size-cells = <1>;
++                      ranges;
++                      ti,hwmods = "epwmss0";
++                      clocks = <&l4ls_gclk>;
++                      clock-names = "fck";
++                      status = "disabled";
++
++                      ecap0: ecap@48300100 {
++                              compatible = "ti,am4372-ecap","ti,am33xx-ecap";
++                              reg = <0x48300100 0x80>;
++                              ti,hwmods = "ecap0";
++                              clocks = <&l4ls_gclk>;
++                              clock-names = "fck";
++                              status = "disabled";
++                      };
++
++                      ehrpwm0: ehrpwm@48300200 {
++                              compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
++                              reg = <0x48300200 0x80>;
++                              ti,hwmods = "ehrpwm0";
++                              clocks = <&l4ls_gclk>;
++                              clock-names = "fck";
++                              status = "disabled";
++                      };
++              };
++
++              epwmss1: epwmss@48302000 {
++                      compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
++                      reg = <0x48302000 0x10>;
++                      #address-cells = <1>;
++                      #size-cells = <1>;
++                      ranges;
++                      ti,hwmods = "epwmss1";
++                      clocks = <&l4ls_gclk>;
++                      clock-names = "fck";
++                      status = "disabled";
++
++                      ecap1: ecap@48302100 {
++                              compatible = "ti,am4372-ecap","ti,am33xx-ecap";
++                              reg = <0x48302100 0x80>;
++                              ti,hwmods = "ecap1";
++                              clocks = <&l4ls_gclk>;
++                              clock-names = "fck";
++                              status = "disabled";
++                      };
++
++                      ehrpwm1: ehrpwm@48302200 {
++                              compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
++                              reg = <0x48302200 0x80>;
++                              ti,hwmods = "ehrpwm1";
++                              clocks = <&l4ls_gclk>;
++                              clock-names = "fck";
++                              status = "disabled";
++                      };
++              };
++
++              epwmss2: epwmss@48304000 {
++                      compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
++                      reg = <0x48304000 0x10>;
++                      #address-cells = <1>;
++                      #size-cells = <1>;
++                      ranges;
++                      ti,hwmods = "epwmss2";
++                      clocks = <&l4ls_gclk>;
++                      clock-names = "fck";
++                      status = "disabled";
++
++                      ecap2: ecap@48304100 {
++                              compatible = "ti,am4372-ecap","ti,am33xx-ecap";
++                              reg = <0x48304100 0x80>;
++                              ti,hwmods = "ecap2";
++                              clocks = <&l4ls_gclk>;
++                              clock-names = "fck";
++                              status = "disabled";
++                      };
++
++                      ehrpwm2: ehrpwm@48304200 {
++                              compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
++                              reg = <0x48304200 0x80>;
++                              ti,hwmods = "ehrpwm2";
++                              clocks = <&l4ls_gclk>;
++                              clock-names = "fck";
++                              status = "disabled";
++                      };
++              };
++
++              epwmss3: epwmss@48306000 {
++                      compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
++                      reg = <0x48306000 0x10>;
++                      #address-cells = <1>;
++                      #size-cells = <1>;
++                      ranges;
++                      ti,hwmods = "epwmss3";
++                      clocks = <&l4ls_gclk>;
++                      clock-names = "fck";
++                      status = "disabled";
++
++                      ehrpwm3: ehrpwm@48306200 {
++                              compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
++                              reg = <0x48306200 0x80>;
++                              ti,hwmods = "ehrpwm3";
++                              clocks = <&l4ls_gclk>;
++                              clock-names = "fck";
++                              status = "disabled";
++                      };
++              };
++
++              epwmss4: epwmss@48308000 {
++                      compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
++                      reg = <0x48308000 0x10>;
++                      #address-cells = <1>;
++                      #size-cells = <1>;
++                      ranges;
++                      ti,hwmods = "epwmss4";
++                      clocks = <&l4ls_gclk>;
++                      clock-names = "fck";
++                      status = "disabled";
++
++                      ehrpwm4: ehrpwm@48308200 {
++                              compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
++                              reg = <0x48308200 0x80>;
++                              ti,hwmods = "ehrpwm4";
++                              clocks = <&l4ls_gclk>;
++                              clock-names = "fck";
++                              status = "disabled";
++                      };
++              };
++
++              epwmss5: epwmss@4830a000 {
++                      compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
++                      reg = <0x4830a000 0x10>;
++                      #address-cells = <1>;
++                      #size-cells = <1>;
++                      ranges;
++                      ti,hwmods = "epwmss5";
++                      clocks = <&l4ls_gclk>;
++                      clock-names = "fck";
++                      status = "disabled";
++
++                      ehrpwm5: ehrpwm@4830a200 {
++                              compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
++                              reg = <0x4830a200 0x80>;
++                              ti,hwmods = "ehrpwm5";
++                              clocks = <&l4ls_gclk>;
++                              clock-names = "fck";
++                              status = "disabled";
++                      };
++              };
++
++              wkup_m3: wkup_m3@44d00000 {
++                      compatible = "ti,am4372-wkup-m3","ti,am3353-wkup-m3";
++                      reg = <0x44d00000 0x4000        /* M3 UMEM */
++                             0x44d80000 0x2000>;      /* M3 DMEM */
++                      ti,hwmods = "wkup_m3";
++                      clocks = <&sys_clkin_ck>;
++                      clock-names = "fck";
++                      status = "disabled";
++              };
++
++              tscadc: tscadc@44e0d000 {
++                      compatible = "ti,am4372-tscadc","ti,am3359-tscadc";
++                      reg = <0x44e0d000 0x1000>;
++                      ti,hwmods = "adc_tsc";
++                      clocks = <&adc_tsc_fck>;
++                      clock-names = "fck";
++                      status = "disabled";
++              };
++
++              ocmcram: ocmcram@40300000 {
++                      compatible = "ti,am4372-ocmcram","ti,am3352-ocmcram";
++                      reg = <0x40300000 0x40000>;
++                      ti,hwmods = "ocmcram";
++                      clocks = <&l3_gclk>;
++                      clock-names = "fck";
++                      status = "disabled";
++              };
++
++              dcan0: d_can@481cc000 {
++                      compatible = "bosch,d_can";
++                      ti,hwmods = "d_can0";
++                      clocks = <&dcan0_fck>;
++                      clock-names = "fck";
++                      reg = <0x481cc000 0x2000
++                              0x44e10644 0x4>;
++                      status = "disabled";
++              };
++
++              dcan1: d_can@481d0000 {
++                      compatible = "bosch,d_can";
++                      ti,hwmods = "d_can1";
++                      clocks = <&dcan1_fck>;
++                      clock-names = "fck";
++                      reg = <0x481d0000 0x2000
++                              0x44e10644 0x4>;
++                      status = "disabled";
++              };
++
++              elm: elm@48080000 {
++                      compatible = "ti,am4372-elm","ti,am3352-elm";
++                      reg = <0x48080000 0x2000>;
++                      ti,hwmods = "elm";
++                      clocks = <&l4ls_gclk>;
++                      clock-names = "fck";
++                      status = "disabled";
++              };
++
++              gpmc: gpmc@50000000 {
++                      compatible = "ti,am4372-gpmc","ti,am3352-gpmc";
++                      ti,hwmods = "gpmc";
++                      clocks = <&l3s_gclk>;
++                      clock-names = "fck";
++                      reg = <0x50000000 0x2000>;
++                      status = "disabled";
++              };
++
++              prcm: prcm@44df0000 {
++                      compatible = "ti,am4372-prcm";
++                      reg = <0x44df0000 0xa000>;
++                      #reset-cells = <1>;
++              };
++
++              rng: rng@48310000 {
++                      compatible = "ti,omap4-rng";
++                      ti,hwmods = "rng";
++                      reg = <0x48310000 0x2000>;
++                      interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
++                      clocks = <&rng_fck>;
++                      clock-names = "fck";
++              };
++
++              sham: sham@53100000 {
++                      compatible = "ti,omap5-sham";
++                      ti,hwmods = "sham";
++                      reg = <0x53100000 0x300>;
++                      dmas = <&edma 36>;
++                      dma-names = "rx";
++                      interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
++                      clocks = <&l3_gclk>;
++                      clock-names = "fck";
++              };
++
++              aes: aes@53501000 {
++                      compatible = "ti,omap4-aes";
++                      ti,hwmods = "aes";
++                      reg = <0x53501000 0xa0>;
++                      interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
++                      dmas = <&edma 6
++                              &edma 5>;
++                      dma-names = "tx", "rx";
++                      clocks = <&aes0_fck>;
++                      clock-names = "fck";
++              };
++
++              des: des@53701000 {
++                      compatible = "ti,omap4-des";
++                      ti,hwmods = "des";
++                      reg = <0x53701000 0xa0>;
++                      interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
++                      dmas = <&edma 34
++                              &edma 33>;
++                      dma-names = "tx", "rx";
++                      clocks = <&l3_gclk>;
++                      clock-names = "fck";
++              };
++
++              am43xx_control_usb2phy1: control-phy@44e10620 {
++                      compatible = "ti,control-phy-am437usb2";
++                      reg = <0x44e10620 0x4>;
++                      reg-names = "power";
++              };
++
++              am43xx_control_usb2phy2: control-phy@0x44e10628 {
++                      compatible = "ti,control-phy-am437usb2";
++                      reg = <0x44e10628 0x4>;
++                      reg-names = "power";
++              };
++
++              ocp2scp0: ocp2scp@483a8000 {
++                      compatible = "ti,omap-ocp2scp";
++                      #address-cells = <1>;
++                      #size-cells = <1>;
++                      ranges;
++                      ti,hwmods = "ocp2scp0";
++
++                      usb2_phy1: usb2phy1@483a8000 {
++                              compatible = "ti,am437x-usb2";
++                              reg = <0x483a8000 0x8000>;
++                              ctrl-module = <&am43xx_control_usb2phy1>;
++                              clocks = <&clk_32768_ck>,
++                                       <&usb_otg_ss0_refclk960m>;
++                              clock-names =   "wkupclk",
++                                              "refclk";
++                              #phy-cells = <0>;
++                      };
++
++              };
++
++              ocp2scp1: ocp2scp@483e8000 {
++                      compatible = "ti,omap-ocp2scp";
++                      #address-cells = <1>;
++                      #size-cells = <1>;
++                      ranges;
++                      ti,hwmods = "ocp2scp1";
++
++                      usb2_phy2: usb2phy2@483e8000 {
++                              compatible = "ti,am437x-usb2";
++                              reg = <0x483e8000 0x8000>;
++                              ctrl-module = <&am43xx_control_usb2phy2>;
++                              clocks = <&clk_32768_ck>,
++                                       <&usb_otg_ss1_refclk960m>;
++                              clock-names =   "wkupclk",
++                                              "refclk";
++                              #phy-cells = <0>;
++                      };
++
++              };
++
++              dwc3_1: omap_dwc3_1@48380000 {
++                      compatible = "ti,am437x-dwc3";
++                      ti,hwmods = "usb_otg_ss0";
++                      reg = <0x48380000 0x10000>;
++                      interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
++                      #address-cells = <1>;
++                      #size-cells = <1>;
++                      utmi-mode = <1>;
++                      ranges;
++                      usb1: usb@48390000 {
++                              compatible = "synopsys,dwc3";
++                              reg = <0x48390000 0x17000>;
++                              interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
++                              phys = <&usb2_phy1>;
++                              phy-names = "usb2-phy";
++                              maximum-speed = "high-speed";
++                              dr_mode = "peripheral";
++                      };
++              };
++
++              dwc3_2: omap_dwc3_2@483c0000 {
++                      compatible = "ti,am437x-dwc3";
++                      ti,hwmods = "usb_otg_ss1";
++                      reg = <0x483c0000 0x10000>;
++                      interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
++                      #address-cells = <1>;
++                      #size-cells = <1>;
++                      utmi-mode = <1>;
++                      ranges;
++                      usb2: usb@483d0000 {
++                              compatible = "synopsys,dwc3";
++                              reg = <0x483d0000 0x17000>;
++                              interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
++                              phys = <&usb2_phy2>;
++                              phy-names = "usb2-phy";
++                              maximum-speed = "high-speed";
++                              dr_mode = "host";
++                      };
++              };
++
++              dss: dss@4832A000 {
++                      compatible = "ti,omap3-dss", "simple-bus";
++                      reg = <0x4832A000 0x200>;
++                      ti,hwmods = "dss_core";
++                      #address-cells = <1>;
++                      #size-cells = <1>;
++                      ranges;
++
++                      dispc@4832A400 {
++                              compatible = "ti,omap3-dispc";
++                              reg = <0x4832A400 0x400>;
++                              interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
++                              ti,hwmods = "dss_dispc";
++                      };
++
++                      dpi: encoder@0 {
++                              compatible = "ti,omap3-dpi";
++                      };
++
++                      rfbi: rfbi@4832A800 {
++                              compatible = "ti,omap3-rfbi";
++                      reg = <0x4832A800 0x100>;
++                              ti,hwmods = "dss_rfbi";
++                      };
++
++              };
++
+       };
++
++      clocks {
++              #address-cells = <1>;
++              #size-cells = <1>;
++              ranges;
++              /include/ "am43xx-clocks.dtsi"
++      };
++
+ };
++
++/include/ "tps65218.dtsi"
+--- /dev/null
++++ b/arch/arm/boot/dts/am437x-gp-evm.dts
+@@ -0,0 +1,238 @@
++/*
++ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++/* AM437x GP EVM */
++
++/dts-v1/;
++
++#include "am43x-common-evm.dtsi"
++#include <dt-bindings/pinctrl/am43xx.h>
++
++/ {
++      model = "TI AM437x gp EVM";
++      compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
++
++      vmmcsd_fixed: fixedregulator-sd {
++              compatible = "regulator-fixed";
++              regulator-name = "vmmcsd_fixed";
++              regulator-min-microvolt = <3300000>;
++              regulator-max-microvolt = <3300000>;
++              enable-active-high;
++      };
++
++      aliases {
++              display0 = &lcd0;
++              display1 = &hdmi0;
++      };
++
++      lcd0: display@0 {
++              compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
++              video-source = <&dpi>;
++              data-lines = <24>;
++              gpios = <0                          /* No Enable GPIO */
++                       &gpio0 7 GPIO_ACTIVE_LOW>; /* LCD backlight GPIO */
++              activelow_backlight;                /* LCD backlight is Active low */
++              panel-timing {
++                      clock-frequency = <33000000>;
++                      hactive = <800>;
++                      vactive = <480>;
++                      hfront-porch = <210>;
++                      hback-porch = <16>;
++                      hsync-len = <30>;
++                      vback-porch = <10>;
++                      vfront-porch = <22>;
++                      vsync-len = <13>;
++                      hsync-active = <0>;
++                      vsync-active = <0>;
++                      de-active = <1>;
++                      pixelclk-active = <1>;
++              };
++      };
++
++      hdmi0: connector@1 {
++              compatible = "ti,hdmi_connector";
++              video-source = <&sii9022>;
++      };
++};
++
++&am43xx_pinmux {
++      pinctrl-names = "default";
++      pinctrl-0 = <&dss_pinctrl>;
++      cpsw_default: cpsw_default {
++              pinctrl-single,pins = <
++                      /* Slave 1 */
++                      0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
++                      0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxdv.rgmii1_rxctl */
++                      0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
++                      0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
++                      0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
++                      0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
++                      0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
++                      0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxclk.rmii1_rclk */
++                      0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd1.rgmii1_rxd3 */
++                      0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd0.rgmii1_rxd2 */
++                      0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd1.rgmii1_rxd1 */
++                      0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd0.rgmii1_rxd0 */
++              >;
++      };
++
++      cpsw_sleep: cpsw_sleep {
++              pinctrl-single,pins = <
++                      /* Slave 1 reset value */
++                      0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                      0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                      0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                      0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                      0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                      0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                      0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                      0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                      0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                      0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                      0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                      0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                      0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
++              >;
++      };
++
++      davinci_mdio_default: davinci_mdio_default {
++              pinctrl-single,pins = <
++                      /* MDIO */
++                      0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
++                      0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
++              >;
++      };
++
++      davinci_mdio_sleep: davinci_mdio_sleep {
++              pinctrl-single,pins = <
++                      /* MDIO reset value */
++                      0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                      0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
++              >;
++      };
++
++      mmc1_pins: pinmux_mmc1_pins {
++              pinctrl-single,pins = <
++                      0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
++              >;
++      };
++
++      i2c0_pins: pinmux_i2c0_pins {
++              pinctrl-single,pins = <
++                      0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* i2c0_sda.i2c0_sda */
++                      0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* i2c0_scl.i2c0_scl */
++              >;
++      };
++
++      i2c1_pins: i2c1_pins {
++              pinctrl-single,pins = <
++                      0x15c   (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_cs0.i2c1_scl */
++                      0x158   (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_d1.i2c1_sda */
++              >;
++      };
++
++      dss_pinctrl: dss_pinctrl {
++              pinctrl-single,pins = <
++                      0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
++                      0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
++                      0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
++                      0x02C (PIN_OUTPUT_PULLUP | MUX_MODE1)
++                      0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
++                      0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
++                      0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
++                      0x03C (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
++                      0x0A0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
++                      0x0A4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
++                      0x0A8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
++                      0x0AC (PIN_OUTPUT_PULLUP | MUX_MODE0)
++                      0x0B0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
++                      0x0B4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
++                      0x0B8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
++                      0x0BC (PIN_OUTPUT_PULLUP | MUX_MODE0)
++                      0x0C0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
++                      0x0C4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
++                      0x0C8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
++                      0x0CC (PIN_OUTPUT_PULLUP | MUX_MODE0)
++                      0x0D0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
++                      0x0D4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
++                      0x0D8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
++                      0x0DC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
++                      0x0E0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
++                      0x0E4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
++                      0x0E8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
++                      0x0EC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
++                      0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* GPIO 5_8 to select LCD / HDMI */
++                      0x164 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* ECAP0_IN_PWM0_OUT -> GPIO 0_7 BACKLIGHT */
++              >;
++      };
++};
++
++&rtc {
++      status = "okay";
++};
++
++&gpio0 {
++      status = "okay";
++};
++
++&gpio5 {
++      status = "okay";
++};
++
++&mac {
++      pinctrl-names = "default", "sleep";
++      pinctrl-0 = <&cpsw_default>;
++      pinctrl-1 = <&cpsw_sleep>;
++      status = "okay";
++};
++
++&davinci_mdio {
++      pinctrl-names = "default", "sleep";
++      pinctrl-0 = <&davinci_mdio_default>;
++      pinctrl-1 = <&davinci_mdio_sleep>;
++      status = "okay";
++};
++
++&cpsw_emac0 {
++      phy_id = <&davinci_mdio>, <0>;
++      phy-mode = "rgmii";
++};
++
++&cpsw_emac1 {
++      phy_id = <&davinci_mdio>, <1>;
++      phy-mode = "rgmii";
++};
++
++&mmc1 {
++      status = "okay";
++      vmmc-supply = <&vmmcsd_fixed>;
++      bus-width = <4>;
++      pinctrl-names = "default";
++      pinctrl-0 = <&mmc1_pins>;
++      cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
++};
++
++&i2c0 {
++        status = "okay";
++        pinctrl-names = "default";
++        pinctrl-0 = <&i2c0_pins>;
++};
++
++&i2c1 {
++        status = "okay";
++        pinctrl-names = "default";
++        pinctrl-0 = <&i2c1_pins>;
++
++      sii9022: sii9022@3b {
++              compatible = "sii,sii9022";
++              reg = <0x3b>;
++              reset-gpio = <&gpio5 8 GPIO_ACTIVE_LOW>;/* 'SelLCDorHDMI' Gpio, LOW to select HDMI */
++              video-source = <&dpi>;
++              data-lines = <24>;
++      };
++};
+--- /dev/null
++++ b/arch/arm/boot/dts/am43x-common-evm.dtsi
+@@ -0,0 +1,9 @@
++/*
++ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "am4372.dtsi"
+--- a/arch/arm/boot/dts/am43x-epos-evm.dts
++++ b/arch/arm/boot/dts/am43x-epos-evm.dts
+@@ -10,9 +10,289 @@
+ /dts-v1/;
+-#include "am4372.dtsi"
++#include "am43x-common-evm.dtsi"
++#include <dt-bindings/pinctrl/am43xx.h>
+ / {
+       model = "TI AM43x EPOS EVM";
+       compatible = "ti,am43x-epos-evm","ti,am4372","ti,am43";
++
++      vmmcsd_fixed: fixedregulator-sd {
++              compatible = "regulator-fixed";
++              regulator-name = "vmmcsd_fixed";
++              regulator-min-microvolt = <3300000>;
++              regulator-max-microvolt = <3300000>;
++              enable-active-high;
++      };
++
++      aliases {
++              display0 = &lcd0;
++              display1 = &hdmi0;
++      };
++
++      lcd0: display@0 {
++              compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
++              video-source = <&dpi>;
++              data-lines = <24>;
++              gpios = <0                          /* No Enable GPIO */
++                       &gpio0 7 GPIO_ACTIVE_LOW>; /* LCD backlight GPIO */
++              panel-timing {
++                      clock-frequency = <33000000>;
++                      hactive = <800>;
++                      vactive = <480>;
++                      hfront-porch = <210>;
++                      hback-porch = <16>;
++                      hsync-len = <30>;
++                      vback-porch = <10>;
++                      vfront-porch = <22>;
++                      vsync-len = <13>;
++                      hsync-active = <0>;
++                      vsync-active = <0>;
++                      de-active = <1>;
++                      pixelclk-active = <1>;
++              };
++      };
++
++      hdmi0: connector@1 {
++              compatible = "ti,hdmi_connector";
++              video-source = <&sii9022>;
++      };
++};
++
++&am43xx_pinmux {
++      pinctrl-names = "default";
++      pinctrl-0 = <&dss_pinctrl>;
++      cpsw_default: cpsw_default {
++              pinctrl-single,pins = <
++                      /* Slave 1 */
++                      0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_crs.rmii1_crs */
++                      0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_rxerr.rmii1_rxerr */
++                      0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
++                      0x118 (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_rxdv.rmii1_rxdv */
++                      0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
++                      0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
++                      0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_rxd1.rmii1_rxd1 */
++                      0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_rxd0.rmii1_rxd0 */
++                      0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0)  /* rmii1_refclk.rmii1_refclk */
++              >;
++      };
++
++      cpsw_sleep: cpsw_sleep {
++              pinctrl-single,pins = <
++                      /* Slave 1 reset value */
++                      0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                      0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                      0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                      0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                      0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                      0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                      0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                      0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                      0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
++              >;
++      };
++
++      davinci_mdio_default: davinci_mdio_default {
++              pinctrl-single,pins = <
++                      /* MDIO */
++                      0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
++                      0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
++              >;
++      };
++
++      davinci_mdio_sleep: davinci_mdio_sleep {
++              pinctrl-single,pins = <
++                      /* MDIO reset value */
++                      0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
++                      0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
++              >;
++      };
++
++      mmc1_pins: pinmux_mmc1_pins {
++              pinctrl-single,pins = <
++                      0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
++              >;
++      };
++
++      i2c0_pins: pinmux_i2c0_pins {
++              pinctrl-single,pins = <
++                      0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* i2c0_sda.i2c0_sda */
++                      0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* i2c0_scl.i2c0_scl */
++              >;
++      };
++
++      i2c2_pins: pinmux_i2c2_pins {
++              pinctrl-single,pins = <
++                      0x1c0 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* i2c2_sda.i2c2_sda */
++                      0x1c4 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* i2c2_scl.i2c2_scl */
++              >;
++      };
++
++      spi0_pins: pinmux_spi0_pins {
++              pinctrl-single,pins = <
++                      0x150 (PIN_INPUT | MUX_MODE0)           /* spi0_clk.spi0_clk */
++                      0x154 (PIN_OUTPUT | MUX_MODE0)           /* spi0_d0.spi0_d0 */
++                      0x158 (PIN_INPUT | MUX_MODE0)           /* spi0_d1.spi0_d1 */
++                      0x15c (PIN_OUTPUT | MUX_MODE0)          /* spi0_cs0.spi0_cs0 */
++              >;
++      };
++
++      spi1_pins: pinmux_spi1_pins {
++              pinctrl-single,pins = <
++                      0x190 (PIN_INPUT | MUX_MODE3)           /* mcasp0_aclkx.spi1_clk */
++                      0x194 (PIN_OUTPUT | MUX_MODE3)           /* mcasp0_fsx.spi1_d0 */
++                      0x198 (PIN_INPUT | MUX_MODE3)           /* mcasp0_axr0.spi1_d1 */
++                      0x19c (PIN_OUTPUT | MUX_MODE3)          /* mcasp0_ahclkr.spi1_cs0 */
++              >;
++      };
++
++      pixcir_ts_pins: pixcir_ts_pins {
++              pinctrl-single,pins = <
++                      0x48 (PIN_INPUT_PULLUP | MUX_MODE7)  /* gpmc_a1.gpio1_17 */
++              >;
++      };
++
++      dss_pinctrl: dss_pinctrl {
++              pinctrl-single,pins = <
++                      0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
++                      0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
++                      0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
++                      0x02C (PIN_OUTPUT_PULLUP | MUX_MODE1)
++                      0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
++                      0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
++                      0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
++                      0x03C (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
++                      0x0A0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
++                      0x0A4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
++                      0x0A8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
++                      0x0AC (PIN_OUTPUT_PULLUP | MUX_MODE0)
++                      0x0B0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
++                      0x0B4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
++                      0x0B8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
++                      0x0BC (PIN_OUTPUT_PULLUP | MUX_MODE0)
++                      0x0C0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
++                      0x0C4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
++                      0x0C8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
++                      0x0CC (PIN_OUTPUT_PULLUP | MUX_MODE0)
++                      0x0D0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
++                      0x0D4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
++                      0x0D8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
++                      0x0DC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
++                      0x0E0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
++                      0x0E4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
++                      0x0E8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
++                      0x0EC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
++                      0x08C (PIN_OUTPUT_PULLUP | MUX_MODE7) /* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */
++                      0x164 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* ECAP0_IN_PWM0_OUT -> GPIO 0_7 BACKLIGHT */
++              >;
++      };
++};
++
++&gpio0 {
++      status = "okay";
++};
++
++&gpio1 {
++      status = "okay";
++};
++
++&gpio2 {
++      status = "okay";
++};
++
++&qspi {
++      spi-max-frequency = <48000000>;
++      m25p80@0 {
++              compatible = "mx66l51235l";
++              spi-max-frequency = <48000000>;
++              reg = <0>;
++              spi-cpol;
++              spi-cpha;
++              tx-nbits = <1>;
++              rx-nbits = <4>;
++      };
++};
++
++&mac {
++      pinctrl-names = "default", "sleep";
++      pinctrl-0 = <&cpsw_default>;
++      pinctrl-1 = <&cpsw_sleep>;
++      status = "okay";
++};
++
++&davinci_mdio {
++      pinctrl-names = "default", "sleep";
++      pinctrl-0 = <&davinci_mdio_default>;
++      pinctrl-1 = <&davinci_mdio_sleep>;
++      status = "okay";
++};
++
++&cpsw_emac0 {
++      phy_id = <&davinci_mdio>, <16>;
++      phy-mode = "rmii";
++};
++
++&cpsw_emac1 {
++      phy_id = <&davinci_mdio>, <1>;
++      phy-mode = "rmii";
++};
++
++&phy_sel {
++      rmii-clock-ext;
++};
++
++&mmc1 {
++      status = "okay";
++      vmmc-supply = <&vmmcsd_fixed>;
++      bus-width = <4>;
++      pinctrl-names = "default";
++      pinctrl-0 = <&mmc1_pins>;
++      cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
++};
++
++&i2c0 {
++      pinctrl-names = "default";
++      pinctrl-0 = <&i2c0_pins>;
++      status = "okay";
++      clock-frequency = <400000>;
++
++      pixcir_ts@5c {
++              compatible = "pixcir,pixcir_tangoc";
++              pinctrl-names = "default";
++              pinctrl-0 = <&pixcir_ts_pins>;
++              reg = <0x5c>;
++              interrupt-parent = <&gpio1>;
++              interrupts = <17 0>;
++
++              attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
++
++              x-size = <1024>;
++              y-size = <600>;
++      };
++};
++
++&i2c2 {
++      pinctrl-names = "default";
++      pinctrl-0 = <&i2c2_pins>;
++      status = "okay";
++
++      sii9022: sii9022@3b {
++              compatible = "sii,sii9022";
++              reg = <0x3b>;
++              reset-gpio = <&gpio2 1 GPIO_ACTIVE_LOW>;/* 65'SelLCDorHDMI' Gpio, LOW to select HDMI */
++              video-source = <&dpi>;
++              data-lines = <24>;
++      };
++};
++
++&spi0 {
++      pinctrl-names = "default";
++      pinctrl-0 = <&spi0_pins>;
++      status = "okay";
++};
++
++&spi1 {
++      pinctrl-names = "default";
++      pinctrl-0 = <&spi1_pins>;
++      status = "okay";
+ };
+--- /dev/null
++++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
+@@ -0,0 +1,735 @@
++/*
++ * Device Tree Source for AM43xx clock data
++ *
++ * Copyright (C) 2013 Texas Instruments, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++clk_32768_ck: clk_32768_ck {
++      #clock-cells = <0>;
++      compatible = "fixed-clock";
++      clock-frequency = <32768>;
++};
++
++clk_rc32k_ck: clk_rc32k_ck {
++      #clock-cells = <0>;
++      compatible = "fixed-clock";
++      clock-frequency = <32768>;
++};
++
++virt_19200000_ck: virt_19200000_ck {
++      #clock-cells = <0>;
++      compatible = "fixed-clock";
++      clock-frequency = <19200000>;
++};
++
++virt_24000000_ck: virt_24000000_ck {
++      #clock-cells = <0>;
++      compatible = "fixed-clock";
++      clock-frequency = <24000000>;
++};
++
++virt_25000000_ck: virt_25000000_ck {
++      #clock-cells = <0>;
++      compatible = "fixed-clock";
++      clock-frequency = <25000000>;
++};
++
++virt_26000000_ck: virt_26000000_ck {
++      #clock-cells = <0>;
++      compatible = "fixed-clock";
++      clock-frequency = <26000000>;
++};
++
++crystal_freq_sel_ck: crystal_freq_sel_ck@44e10040 {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
++      bit-shift = <29>;
++      reg = <0x44e10040 0x4>;
++      bit-mask = <0x3>;
++};
++
++sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
++      bit-shift = <22>;
++      reg = <0x44e10040 0x4>;
++      bit-mask = <0x3>;
++};
++
++sys_clkin_ck: sys_clkin_ck@44e10040 {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
++      bit-shift = <31>;
++      reg = <0x44e10040 0x4>;
++      bit-mask = <0x1>;
++};
++
++tclkin_ck: tclkin_ck {
++      #clock-cells = <0>;
++      compatible = "fixed-clock";
++      clock-frequency = <26000000>;
++};
++
++dpll_core_ck: dpll_core_ck@44df2d20 {
++      #clock-cells = <0>;
++      compatible = "ti,omap4-dpll-core-clock";
++      clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
++      reg = <0x44df2d20 0x4>, <0x44df2d24 0x4>, <0x44df2d2c 0x4>;
++      reg-names = "control", "idlest", "mult-div1";
++};
++
++dpll_core_x2_ck: dpll_core_x2_ck {
++      #clock-cells = <0>;
++      compatible = "ti,omap4-dpll-x2-clock";
++      clocks = <&dpll_core_ck>;
++};
++
++dpll_core_m4_ck: dpll_core_m4_ck@44df2d38 {
++      #clock-cells = <0>;
++      compatible = "ti,divider-clock";
++      clocks = <&dpll_core_x2_ck>;
++      ti,autoidle-shift = <8>;
++      reg = <0x44df2d38 0x4>;
++      bit-mask = <0x1f>;
++      index-starts-at-one;
++      ti,autoidle-low;
++};
++
++dpll_core_m5_ck: dpll_core_m5_ck@44df2d3c {
++      #clock-cells = <0>;
++      compatible = "ti,divider-clock";
++      clocks = <&dpll_core_x2_ck>;
++      ti,autoidle-shift = <8>;
++      reg = <0x44df2d3c 0x4>;
++      bit-mask = <0x1f>;
++      index-starts-at-one;
++      ti,autoidle-low;
++};
++
++dpll_core_m6_ck: dpll_core_m6_ck@44df2d40 {
++      #clock-cells = <0>;
++      compatible = "ti,divider-clock";
++      clocks = <&dpll_core_x2_ck>;
++      ti,autoidle-shift = <8>;
++      reg = <0x44df2d40 0x4>;
++      bit-mask = <0x1f>;
++      index-starts-at-one;
++      ti,autoidle-low;
++};
++
++dpll_mpu_ck: dpll_mpu_ck@44df2d60 {
++      #clock-cells = <0>;
++      compatible = "ti,omap4-dpll-clock";
++      clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
++      reg = <0x44df2d60 0x4>, <0x44df2d64 0x4>, <0x44df2d6c 0x4>;
++      reg-names = "control", "idlest", "mult-div1";
++};
++
++dpll_mpu_m2_ck: dpll_mpu_m2_ck@44df2d70 {
++      #clock-cells = <0>;
++      compatible = "ti,divider-clock";
++      clocks = <&dpll_mpu_ck>;
++      ti,autoidle-shift = <8>;
++      reg = <0x44df2d70 0x4>;
++      bit-mask = <0x1f>;
++      index-starts-at-one;
++      ti,autoidle-low;
++};
++
++dpll_ddr_ck: dpll_ddr_ck@44df2da0 {
++      #clock-cells = <0>;
++      compatible = "ti,omap4-dpll-clock";
++      clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
++      reg = <0x44df2da0 0x4>, <0x44df2da4 0x4>, <0x44df2dac 0x4>;
++      reg-names = "control", "idlest", "mult-div1";
++};
++
++dpll_ddr_m2_ck: dpll_ddr_m2_ck@44df2db0 {
++      #clock-cells = <0>;
++      compatible = "ti,divider-clock";
++      clocks = <&dpll_ddr_ck>;
++      ti,autoidle-shift = <8>;
++      reg = <0x44df2db0 0x4>;
++      bit-mask = <0x1f>;
++      index-starts-at-one;
++      ti,autoidle-low;
++};
++
++dpll_disp_ck: dpll_disp_ck@44df2e20 {
++      #clock-cells = <0>;
++      compatible = "ti,omap4-dpll-clock";
++      clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
++      reg = <0x44df2e20 0x4>, <0x44df2e24 0x4>, <0x44df2e2c 0x4>;
++      reg-names = "control", "idlest", "mult-div1";
++};
++
++dpll_disp_m2_ck: dpll_disp_m2_ck@44df2e30 {
++      #clock-cells = <0>;
++      compatible = "ti,divider-clock";
++      clocks = <&dpll_disp_ck>;
++      ti,autoidle-shift = <8>;
++      reg = <0x44df2e30 0x4>;
++      bit-mask = <0x1f>;
++      index-starts-at-one;
++      ti,autoidle-low;
++};
++
++dpll_per_ck: dpll_per_ck@44df2de0 {
++      #clock-cells = <0>;
++      compatible = "ti,omap4-dpll-j-type-clock";
++      clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
++      reg = <0x44df2de0 0x4>, <0x44df2de4 0x4>, <0x44df2dec 0x4>;
++      reg-names = "control", "idlest", "mult-div1";
++};
++
++dpll_per_m2_ck: dpll_per_m2_ck@44df2df0 {
++      #clock-cells = <0>;
++      compatible = "ti,divider-clock";
++      clocks = <&dpll_per_ck>;
++      ti,autoidle-shift = <8>;
++      reg = <0x44df2df0 0x4>;
++      bit-mask = <0x7f>;
++      index-starts-at-one;
++      ti,autoidle-low;
++};
++
++dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&dpll_per_m2_ck>;
++      clock-mult = <1>;
++      clock-div = <4>;
++};
++
++dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&dpll_per_m2_ck>;
++      clock-mult = <1>;
++      clock-div = <4>;
++};
++
++adc_tsc_fck: adc_tsc_fck {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&sys_clkin_ck>;
++      clock-mult = <1>;
++      clock-div = <1>;
++};
++
++clk_24mhz: clk_24mhz {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&dpll_per_m2_ck>;
++      clock-mult = <1>;
++      clock-div = <8>;
++};
++
++clkdiv32k_ck: clkdiv32k_ck {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&clk_24mhz>;
++      clock-mult = <1>;
++      clock-div = <732>;
++};
++
++clkdiv32k_ick: clkdiv32k_ick@44df2a38 {
++      #clock-cells = <0>;
++      compatible = "gate-clock";
++      clocks = <&clkdiv32k_ck>;
++      bit-shift = <8>;
++      reg = <0x44df2a38 0x4>;
++};
++
++dcan0_fck: dcan0_fck {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&sys_clkin_ck>;
++      clock-mult = <1>;
++      clock-div = <1>;
++};
++
++dcan1_fck: dcan1_fck {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&sys_clkin_ck>;
++      clock-mult = <1>;
++      clock-div = <1>;
++};
++
++sysclk_div: sysclk_div {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&dpll_core_m4_ck>;
++      clock-mult = <1>;
++      clock-div = <1>;
++};
++
++pruss_ocp_gclk: pruss_ocp_gclk@44df4248 {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&sysclk_div>, <&dpll_disp_m2_ck>;
++      reg = <0x44df4248 0x4>;
++      bit-mask = <0x1>;
++};
++
++mcasp0_fck: mcasp0_fck {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&sys_clkin_ck>;
++      clock-mult = <1>;
++      clock-div = <1>;
++};
++
++mcasp1_fck: mcasp1_fck {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&sys_clkin_ck>;
++      clock-mult = <1>;
++      clock-div = <1>;
++};
++
++smartreflex0_fck: smartreflex0_fck {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&sys_clkin_ck>;
++      clock-mult = <1>;
++      clock-div = <1>;
++};
++
++smartreflex1_fck: smartreflex1_fck {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&sys_clkin_ck>;
++      clock-mult = <1>;
++      clock-div = <1>;
++};
++
++sha0_fck: sha0_fck {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&sys_clkin_ck>;
++      clock-mult = <1>;
++      clock-div = <1>;
++};
++
++rng_fck: rng_fck {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&sys_clkin_ck>;
++      clock-mult = <1>;
++      clock-div = <1>;
++};
++
++aes0_fck: aes0_fck {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&sys_clkin_ck>;
++      clock-mult = <1>;
++      clock-div = <1>;
++};
++
++clk_32k_tpm_ck: clk_32k_tpm_ck {
++      #clock-cells = <0>;
++      compatible = "fixed-clock";
++      clock-frequency = <32768>;
++};
++
++timer1_fck: timer1_fck@44df4200 {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
++      reg = <0x44df4200 0x4>;
++      bit-mask = <0x7>;
++};
++
++timer2_fck: timer2_fck@44df4204 {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
++      reg = <0x44df4204 0x4>;
++      bit-mask = <0x3>;
++};
++
++timer3_fck: timer3_fck@44df4208 {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
++      reg = <0x44df4208 0x4>;
++      bit-mask = <0x3>;
++};
++
++timer4_fck: timer4_fck@44df420c {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
++      reg = <0x44df420c 0x4>;
++      bit-mask = <0x3>;
++};
++
++timer5_fck: timer5_fck@44df4210 {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
++      reg = <0x44df4210 0x4>;
++      bit-mask = <0x3>;
++};
++
++timer6_fck: timer6_fck@44df4214 {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
++      reg = <0x44df4214 0x4>;
++      bit-mask = <0x3>;
++};
++
++timer7_fck: timer7_fck@44df4218 {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
++      reg = <0x44df4218 0x4>;
++      bit-mask = <0x3>;
++};
++
++wdt1_fck: wdt1_fck@44df422c {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
++      reg = <0x44df422c 0x4>;
++      bit-mask = <0x1>;
++};
++
++l3_gclk: l3_gclk {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&dpll_core_m4_ck>;
++      clock-mult = <1>;
++      clock-div = <1>;
++};
++
++dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&sysclk_div>;
++      clock-mult = <1>;
++      clock-div = <2>;
++};
++
++l4hs_gclk: l4hs_gclk {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&dpll_core_m4_ck>;
++      clock-mult = <1>;
++      clock-div = <1>;
++};
++
++l3s_gclk: l3s_gclk {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&dpll_core_m4_div2_ck>;
++      clock-mult = <1>;
++      clock-div = <1>;
++};
++
++l4ls_gclk: l4ls_gclk {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&dpll_core_m4_div2_ck>;
++      clock-mult = <1>;
++      clock-div = <1>;
++};
++
++cpsw_125mhz_gclk: cpsw_125mhz_gclk {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&dpll_core_m5_ck>;
++      clock-mult = <1>;
++      clock-div = <2>;
++};
++
++cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@44df4238 {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
++      reg = <0x44df4238 0x4>;
++      bit-mask = <0x3>;
++};
++
++clk_32k_mosc_ck: clk_32k_mosc_ck {
++      #clock-cells = <0>;
++      compatible = "fixed-clock";
++      clock-frequency = <32768>;
++};
++
++gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@44df4240 {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>;
++      reg = <0x44df4240 0x4>;
++      bit-mask = <0x7>;
++};
++
++gpio0_dbclk: gpio0_dbclk@44df2b68 {
++      #clock-cells = <0>;
++      compatible = "gate-clock";
++      clocks = <&gpio0_dbclk_mux_ck>;
++      bit-shift = <8>;
++      reg = <0x44df2b68 0x4>;
++};
++
++gpio1_dbclk: gpio1_dbclk@44df8c78 {
++      #clock-cells = <0>;
++      compatible = "gate-clock";
++      clocks = <&clkdiv32k_ick>;
++      bit-shift = <8>;
++      reg = <0x44df8c78 0x4>;
++};
++
++gpio2_dbclk: gpio2_dbclk@44df8c80 {
++      #clock-cells = <0>;
++      compatible = "gate-clock";
++      clocks = <&clkdiv32k_ick>;
++      bit-shift = <8>;
++      reg = <0x44df8c80 0x4>;
++};
++
++gpio3_dbclk: gpio3_dbclk@44df8c88 {
++      #clock-cells = <0>;
++      compatible = "gate-clock";
++      clocks = <&clkdiv32k_ick>;
++      bit-shift = <8>;
++      reg = <0x44df8c88 0x4>;
++};
++
++gpio4_dbclk: gpio4_dbclk@44df8c90 {
++      #clock-cells = <0>;
++      compatible = "gate-clock";
++      clocks = <&clkdiv32k_ick>;
++      bit-shift = <8>;
++      reg = <0x44df8c90 0x4>;
++};
++
++gpio5_dbclk: gpio5_dbclk@44df8c98 {
++      #clock-cells = <0>;
++      compatible = "gate-clock";
++      clocks = <&clkdiv32k_ick>;
++      bit-shift = <8>;
++      reg = <0x44df8c98 0x4>;
++};
++
++mmc_clk: mmc_clk {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&dpll_per_m2_ck>;
++      clock-mult = <1>;
++      clock-div = <2>;
++};
++
++gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@44df423c {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&sysclk_div>, <&dpll_per_m2_ck>;
++      bit-shift = <1>;
++      reg = <0x44df423c 0x4>;
++      bit-mask = <0x1>;
++};
++
++gfx_fck_div_ck: gfx_fck_div_ck@44df423c {
++      #clock-cells = <0>;
++      compatible = "divider-clock";
++      clocks = <&gfx_fclk_clksel_ck>;
++      reg = <0x44df423c 0x4>;
++      bit-mask = <0x1>;
++};
++
++disp_clk: disp_clk@44df4244 {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
++      reg = <0x44df4244 0x4>;
++      bit-mask = <0x3>;
++};
++
++dpll_extdev_ck: dpll_extdev_ck@44df2e60 {
++      #clock-cells = <0>;
++      compatible = "ti,omap4-dpll-clock";
++      clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
++      reg = <0x44df2e60 0x4>, <0x44df2e64 0x4>, <0x44df2e6c 0x4>;
++      reg-names = "control", "idlest", "mult-div1";
++};
++
++dpll_extdev_m2_ck: dpll_extdev_m2_ck@44df2e70 {
++      #clock-cells = <0>;
++      compatible = "ti,divider-clock";
++      clocks = <&dpll_extdev_ck>;
++      ti,autoidle-shift = <8>;
++      reg = <0x44df2e70 0x4>;
++      bit-mask = <0x7f>;
++      index-starts-at-one;
++      ti,autoidle-low;
++};
++
++mux_synctimer32k_ck: mux_synctimer32k_ck@44df4230 {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>;
++      reg = <0x44df4230 0x4>;
++      bit-mask = <0x3>;
++};
++
++synctimer_32kclk: synctimer_32kclk@44df2a30 {
++      #clock-cells = <0>;
++      compatible = "gate-clock";
++      clocks = <&mux_synctimer32k_ck>;
++      bit-shift = <8>;
++      reg = <0x44df2a30 0x4>;
++};
++
++timer8_fck: timer8_fck@44df421c {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
++      reg = <0x44df421c 0x4>;
++      bit-mask = <0x3>;
++};
++
++timer9_fck: timer9_fck@44df4220 {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
++      reg = <0x44df4220 0x4>;
++      bit-mask = <0x3>;
++};
++
++timer10_fck: timer10_fck@44df4224 {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
++      reg = <0x44df4224 0x4>;
++      bit-mask = <0x3>;
++};
++
++timer11_fck: timer11_fck@44df4228 {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
++      reg = <0x44df4228 0x4>;
++      bit-mask = <0x3>;
++};
++
++cpsw_50m_clkdiv: cpsw_50m_clkdiv {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&dpll_core_m5_ck>;
++      clock-mult = <1>;
++      clock-div = <1>;
++};
++
++cpsw_5m_clkdiv: cpsw_5m_clkdiv {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&cpsw_50m_clkdiv>;
++      clock-mult = <1>;
++      clock-div = <10>;
++};
++
++dpll_ddr_x2_ck: dpll_ddr_x2_ck {
++      #clock-cells = <0>;
++      compatible = "ti,omap4-dpll-x2-clock";
++      clocks = <&dpll_ddr_ck>;
++};
++
++dpll_ddr_m4_ck: dpll_ddr_m4_ck@44df2db8 {
++      #clock-cells = <0>;
++      compatible = "ti,divider-clock";
++      clocks = <&dpll_ddr_x2_ck>;
++      ti,autoidle-shift = <8>;
++      reg = <0x44df2db8 0x4>;
++      bit-mask = <0x1f>;
++      index-starts-at-one;
++      ti,autoidle-low;
++};
++
++dpll_per_clkdcoldo: dpll_per_clkdcoldo {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&dpll_per_ck>;
++      clock-mult = <1>;
++      clock-div = <1>;
++};
++
++dll_aging_clk_div: dll_aging_clk_div@44df4250 {
++      #clock-cells = <0>;
++      compatible = "divider-clock";
++      clocks = <&sys_clkin_ck>;
++      reg = <0x44df4250 0x4>;
++      table = < 8 0 >, < 16 1 >, < 32 2 >;
++      bit-mask = <0x3>;
++};
++
++div_core_25m_ck: div_core_25m_ck {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&sysclk_div>;
++      clock-mult = <1>;
++      clock-div = <8>;
++};
++
++func_12m_clk: func_12m_clk {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&dpll_per_m2_ck>;
++      clock-mult = <1>;
++      clock-div = <16>;
++};
++
++vtp_clk_div: vtp_clk_div {
++      #clock-cells = <0>;
++      compatible = "fixed-factor-clock";
++      clocks = <&sys_clkin_ck>;
++      clock-mult = <1>;
++      clock-div = <2>;
++};
++
++usbphy_32khz_clkmux: usbphy_32khz_clkmux@44df4260 {
++      #clock-cells = <0>;
++      compatible = "mux-clock";
++      clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;
++      reg = <0x44df4260 0x4>;
++      bit-mask = <0x1>;
++};
++
++usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m@44df8a60 {
++      #clock-cells = <0>;
++      compatible = "gate-clock";
++      clocks = <&dpll_per_clkdcoldo>;
++      bit-shift = <8>;
++      reg = <0x44df8a60 0x4>;
++};
++
++usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@44df8a68 {
++      #clock-cells = <0>;
++      compatible = "gate-clock";
++      clocks = <&dpll_per_clkdcoldo>;
++      bit-shift = <8>;
++      reg = <0x44df8a68 0x4>;
++};
++
++usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
++      #clock-cells = <0>;
++      compatible = "fixed-clock";
++      clocks = <&clk_32768_ck>;
++};
++
++usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k {
++      #clock-cells = <0>;
++      compatible = "fixed-clock";
++      clocks = <&clk_32768_ck>;
++};
+--- /dev/null
++++ b/arch/arm/boot/dts/dra7.dtsi
+@@ -0,0 +1,1278 @@
++/*
++ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ * Based on "omap4.dtsi"
++ */
++
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++
++#include "skeleton.dtsi"
++
++/ {
++      compatible = "ti,dra7xx";
++      interrupt-parent = <&gic>;
++
++      aliases {
++              i2c0 = &i2c1;
++              i2c1 = &i2c2;
++              i2c2 = &i2c3;
++              i2c3 = &i2c4;
++              i2c4 = &i2c5;
++              serial0 = &uart1;
++              serial1 = &uart2;
++              serial2 = &uart3;
++              serial3 = &uart4;
++              serial4 = &uart5;
++              serial5 = &uart6;
++              ethernet0 = &cpsw_emac0;
++              ethernet1 = &cpsw_emac1;
++      };
++
++      cpus {
++              #address-cells = <1>;
++              #size-cells = <0>;
++
++              cpu0: cpu@0 {
++                      device_type = "cpu";
++                      compatible = "arm,cortex-a15";
++                      reg = <0>;
++
++                      operating-points = <
++                              /* kHz    uV */
++                              1000000 1090000
++                              1176000 1210000
++                              >;
++
++                      clocks = <&dpll_mpu_ck>;
++                      clock-names = "cpu";
++
++                      clock-latency = <300000>; /* From omap-cpufreq driver */
++              };
++              cpu@1 {
++                      device_type = "cpu";
++                      compatible = "arm,cortex-a15";
++                      reg = <1>;
++              };
++      };
++
++      timer {
++              compatible = "arm,armv7-timer";
++              /* PPI secure/nonsecure IRQ */
++              interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
++                           <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
++                           <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
++                           <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
++              clock-frequency = <6144000>;
++      };
++
++      gic: interrupt-controller@48211000 {
++              compatible = "arm,cortex-a15-gic";
++              interrupt-controller;
++              #interrupt-cells = <3>;
++              reg = <0x48211000 0x1000>,
++                    <0x48212000 0x1000>,
++                    <0x48214000 0x2000>,
++                    <0x48216000 0x2000>;
++      };
++
++      /*
++       * The soc node represents the soc top level view. It is uses for IPs
++       * that are not memory mapped in the MPU view or for the MPU itself.
++       */
++      soc {
++              compatible = "ti,omap-infra";
++              mpu {
++                      compatible = "ti,omap5-mpu";
++                      ti,hwmods = "mpu";
++              };
++      };
++
++      /*
++       * XXX: Use a flat representation of the SOC interconnect.
++       * The real OMAP interconnect network is quite complex.
++       * Since that will not bring real advantage to represent that in DT for
++       * the moment, just use a fake OCP bus entry to represent the whole bus
++       * hierarchy.
++       */
++      ocp {
++              compatible = "ti,omap4-l3-noc", "simple-bus";
++              #address-cells = <1>;
++              #size-cells = <1>;
++              ranges;
++              ti,hwmods = "l3_main_1", "l3_main_2";
++
++              crossbar_mpu: mpuirq@4a002a48 {
++                      compatible = "crossbar";
++                      crossbar-name = "mpu-irq";
++                      reg = <0x4a002a48 0x0130>;
++                      reg-width = <16>;
++                      crossbar-lines = "mpu-irq", "rtc-ss-alarm", <0x9f 0xd9 0x12e>,
++                                       "mpu-irq", "mcasp3-arevt", <0x9e 0x96 0x12c>,
++                                       "mpu-irq", "mcasp3-axevt", <0x9d 0x97 0x12a>,
++                                       "mpu-irq", "mailbox5", <0x88 0xfb 0x100>,
++                                       "mpu-irq", "mailbox6", <0x8d 0xff 0x10a>,
++                                       "mpu-irq", "qspi", <0x7c 0x157 0x0ec>,
++                                       "mpu-irq", "vpe", <0x9c 0x162 0x128>,
++                                       "mpu-irq", "cpsw-rx-thresh", <0x32 0x14e 0x58>,
++                                       "mpu-irq", "cpsw-rx", <0x33 0x14f 0x5a>,
++                                       "mpu-irq", "cpsw-tx", <0x34 0x150 0x5c>,
++                                       "mpu-irq", "cpsw-misc", <0x35 0x151 0x5e>;
++              };
++
++              crossbar_dma: dmareq@4a002b78 {
++                      compatible = "crossbar";
++                      crossbar-name = "dma-req";
++                      reg = <0x4a002b78 0x0100>;
++                      reg-width = <16>;
++                      crossbar-lines = "dma-req", "mcasp3-rx", <0x7e 0x84 0xfc>,
++                                       "dma-req", "mcasp3-tx", <0x7d 0x85 0xfa>;
++              };
++
++              prcm: prcm@4ae06000 {
++                      compatible = "ti,dra7-prcm";
++                      reg = <0x4ae06000 0x1f00>;
++                      #reset-cells = <1>;
++              };
++
++              counter32k: counter@4ae04000 {
++                      compatible = "ti,omap-counter32k";
++                      reg = <0x4ae04000 0x40>;
++                      ti,hwmods = "counter_32k";
++                      clocks = <&wkupaon_iclk_mux>;
++                      clock-names = "fck";
++              };
++
++              avs_mpu: regulator-avs@0x4A003B18 {
++                      compatible = "ti,avsclass0";
++                      reg = <0x4A003B18 20>;
++                      efuse-settings = <1090000 8
++                      1210000 12
++                      1280000 16>;
++              };
++
++              avs_core: regulator-avs@0x4A0025EC {
++                      compatible = "ti,avsclass0";
++                      reg = <0x4A0025EC 20>;
++                      efuse-settings = <1030000 8>;
++              };
++
++              avs_gpu: regulator-avs@0x4A003B00 {
++                      compatible = "ti,avsclass0";
++                      reg = <0x4A003B00 20>;
++                      efuse-settings = <1090000 8
++                      1210000 12
++                      1280000 16>;
++              };
++
++              avs_dspeve: regulator-avs@0x4A0025D8 {
++                      compatible = "ti,avsclass0";
++                      reg = <0x4A0025D8 20>;
++                      efuse-settings = <1055000 8
++                      1150000 12
++                      1250000 16>;
++              };
++
++              avs_iva: regulator-avs@0x4A0025C4 {
++                      compatible = "ti,avsclass0";
++                      reg = <0x4A0025C4 20>;
++                      efuse-settings = <1055000 8
++                      1150000 12
++                      1250000 16>;
++              };
++
++              dra7_pmx_core: pinmux@4a003400 {
++                      compatible = "pinctrl-single";
++                      reg = <0x4a003400 0x0464>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      pinctrl-single,register-width = <32>;
++                      pinctrl-single,function-mask = <0x3fffffff>;
++              };
++
++              sdma: dma-controller@4a056000 {
++                      compatible = "ti,omap4430-sdma";
++                      reg = <0x4a056000 0x1000>;
++                      interrupts = <0 12 0x4>,
++                                   <0 13 0x4>,
++                                   <0 14 0x4>,
++                                   <0 15 0x4>;
++                      #dma-cells = <1>;
++                      #dma-channels = <32>;
++                      #dma-requests = <127>;
++                      clocks = <&l3_iclk_div>;
++                      clock-names = "fck";
++              };
++
++              gpio1: gpio@4ae10000 {
++                      compatible = "ti,omap4-gpio";
++                      reg = <0x4ae10000 0x200>;
++                      interrupts = <0 29 0x4>;
++                      ti,hwmods = "gpio1";
++                      clocks = <&wkupaon_iclk_mux>, <&gpio1_dbclk>;
++                      clock-names = "fck", "dbclk";
++                      gpio-controller;
++                      #gpio-cells = <2>;
++                      interrupt-controller;
++                      #interrupt-cells = <1>;
++              };
++
++              gpio2: gpio@48055000 {
++                      compatible = "ti,omap4-gpio";
++                      reg = <0x48055000 0x200>;
++                      interrupts = <0 30 0x4>;
++                      ti,hwmods = "gpio2";
++                      clocks = <&l3_iclk_div>, <&gpio2_dbclk>;
++                      clock-names = "fck", "dbclk";
++                      gpio-controller;
++                      #gpio-cells = <2>;
++                      interrupt-controller;
++                      #interrupt-cells = <1>;
++              };
++
++              gpio3: gpio@48057000 {
++                      compatible = "ti,omap4-gpio";
++                      reg = <0x48057000 0x200>;
++                      interrupts = <0 31 0x4>;
++                      ti,hwmods = "gpio3";
++                      clocks = <&l3_iclk_div>, <&gpio3_dbclk>;
++                      clock-names = "fck", "dbclk";
++                      gpio-controller;
++                      #gpio-cells = <2>;
++                      interrupt-controller;
++                      #interrupt-cells = <1>;
++              };
++
++              gpio4: gpio@48059000 {
++                      compatible = "ti,omap4-gpio";
++                      reg = <0x48059000 0x200>;
++                      interrupts = <0 32 0x4>;
++                      ti,hwmods = "gpio4";
++                      clocks = <&l3_iclk_div>, <&gpio4_dbclk>;
++                      clock-names = "fck", "dbclk";
++                      gpio-controller;
++                      #gpio-cells = <2>;
++                      interrupt-controller;
++                      #interrupt-cells = <1>;
++              };
++
++              gpio5: gpio@4805b000 {
++                      compatible = "ti,omap4-gpio";
++                      reg = <0x4805b000 0x200>;
++                      interrupts = <0 33 0x4>;
++                      ti,hwmods = "gpio5";
++                      clocks = <&l3_iclk_div>, <&gpio5_dbclk>;
++                      clock-names = "fck", "dbclk";
++                      gpio-controller;
++                      #gpio-cells = <2>;
++                      interrupt-controller;
++                      #interrupt-cells = <1>;
++              };
++
++              gpio6: gpio@4805d000 {
++                      compatible = "ti,omap4-gpio";
++                      reg = <0x4805d000 0x200>;
++                      interrupts = <0 34 0x4>;
++                      ti,hwmods = "gpio6";
++                      clocks = <&l3_iclk_div>, <&gpio6_dbclk>;
++                      clock-names = "fck", "dbclk";
++                      gpio-controller;
++                      #gpio-cells = <2>;
++                      interrupt-controller;
++                      #interrupt-cells = <1>;
++              };
++
++              gpio7: gpio@48051000 {
++                      compatible = "ti,omap4-gpio";
++                      reg = <0x48051000 0x200>;
++                      interrupts = <0 35 0x4>;
++                      ti,hwmods = "gpio7";
++                      clocks = <&l3_iclk_div>, <&gpio7_dbclk>;
++                      clock-names = "fck", "dbclk";
++                      gpio-controller;
++                      #gpio-cells = <2>;
++                      interrupt-controller;
++                      #interrupt-cells = <1>;
++              };
++
++              gpio8: gpio@48053000 {
++                      compatible = "ti,omap4-gpio";
++                      reg = <0x48053000 0x200>;
++                      interrupts = <0 121 0x4>;
++                      ti,hwmods = "gpio8";
++                      clocks = <&l3_iclk_div>, <&gpio8_dbclk>;
++                      clock-names = "fck", "dbclk";
++                      gpio-controller;
++                      #gpio-cells = <2>;
++                      interrupt-controller;
++                      #interrupt-cells = <1>;
++              };
++
++              uart1: serial@4806a000 {
++                      compatible = "ti,omap4-uart";
++                      reg = <0x4806a000 0x100>;
++                      interrupts = <0 72 0x4>;
++                      ti,hwmods = "uart1";
++                      clocks = <&uart1_gfclk_mux>;
++                      clock-names = "fck";
++                      clock-frequency = <48000000>;
++                      status = "disabled";
++              };
++
++              uart2: serial@4806c000 {
++                      compatible = "ti,omap4-uart";
++                      reg = <0x4806c000 0x100>;
++                      interrupts = <0 73 0x4>;
++                      ti,hwmods = "uart2";
++                      clocks = <&uart2_gfclk_mux>;
++                      clock-names = "fck";
++                      clock-frequency = <48000000>;
++                      status = "disabled";
++              };
++
++              uart3: serial@48020000 {
++                      compatible = "ti,omap4-uart";
++                      reg = <0x48020000 0x100>;
++                      interrupts = <0 74 0x4>;
++                      ti,hwmods = "uart3";
++                      clocks = <&uart3_gfclk_mux>;
++                      clock-names = "fck";
++                      clock-frequency = <48000000>;
++                      status = "disabled";
++              };
++
++              uart4: serial@4806e000 {
++                      compatible = "ti,omap4-uart";
++                      reg = <0x4806e000 0x100>;
++                      interrupts = <0 70 0x4>;
++                      ti,hwmods = "uart4";
++                      clocks = <&uart4_gfclk_mux>;
++                      clock-names = "fck";
++                      clock-frequency = <48000000>;
++                        status = "disabled";
++              };
++
++              uart5: serial@48066000 {
++                      compatible = "ti,omap4-uart";
++                      reg = <0x48066000 0x100>;
++                      interrupts = <0 105 0x4>;
++                      ti,hwmods = "uart5";
++                      clocks = <&uart5_gfclk_mux>;
++                      clock-names = "fck";
++                      clock-frequency = <48000000>;
++                      status = "disabled";
++              };
++
++              uart6: serial@48068000 {
++                      compatible = "ti,omap4-uart";
++                      reg = <0x48068000 0x100>;
++                      interrupts = <0 106 0x4>;
++                      ti,hwmods = "uart6";
++                      clocks = <&uart6_gfclk_mux>;
++                      clock-names = "fck";
++                      clock-frequency = <48000000>;
++                      status = "disabled";
++              };
++
++              uart7: serial@48420000 {
++                      compatible = "ti,omap4-uart";
++                      reg = <0x48420000 0x100>;
++                      ti,hwmods = "uart7";
++                      clock-frequency = <48000000>;
++                      status = "disabled";
++              };
++
++              uart8: serial@48422000 {
++                      compatible = "ti,omap4-uart";
++                      reg = <0x48422000 0x100>;
++                      ti,hwmods = "uart8";
++                      clock-frequency = <48000000>;
++                      status = "disabled";
++              };
++
++              uart9: serial@48424000 {
++                      compatible = "ti,omap4-uart";
++                      reg = <0x48424000 0x100>;
++                      ti,hwmods = "uart9";
++                      clock-frequency = <48000000>;
++                      status = "disabled";
++              };
++
++              uart10: serial@4ae2b000 {
++                      compatible = "ti,omap4-uart";
++                      reg = <0x4ae2b000 0x100>;
++                      ti,hwmods = "uart10";
++                      clock-frequency = <48000000>;
++                      status = "disabled";
++              };
++
++              mailbox1: mailbox@4a0f4000 {
++                      compatible = "ti,omap4-mailbox";
++                      reg = <0x4a0f4000 0x200>;
++                      interrupts = <0 26 0x4>;
++                      ti,hwmods = "mailbox1";
++                      ti,mbox-num-users = <3>;
++                      ti,mbox-num-fifos = <8>;
++                      #ti,mbox-data-cells = <4>;
++                      ti,mbox-names = "mbox1-1", "mbox1-2";
++                      ti,mbox-data = <0 1 0 0>, <3 2 0 0>;
++              };
++
++              mailbox2: mailbox@4883a000 {
++                      compatible = "ti,omap4-mailbox";
++                      reg = <0x4883a000 0x200>;
++                      ti,hwmods = "mailbox2";
++                      ti,mbox-num-users = <4>;
++                      ti,mbox-num-fifos = <12>;
++                      #ti,mbox-data-cells = <4>;
++                      status = "disabled";
++              };
++
++              mailbox3: mailbox@4883c000 {
++                      compatible = "ti,omap4-mailbox";
++                      reg = <0x4883c000 0x200>;
++                      ti,hwmods = "mailbox3";
++                      ti,mbox-num-users = <4>;
++                      ti,mbox-num-fifos = <12>;
++                      #ti,mbox-data-cells = <4>;
++                      status = "disabled";
++              };
++
++              mailbox4: mailbox@4883e000 {
++                      compatible = "ti,omap4-mailbox";
++                      reg = <0x4883e000 0x200>;
++                      ti,hwmods = "mailbox4";
++                      ti,mbox-num-users = <4>;
++                      ti,mbox-num-fifos = <12>;
++                      #ti,mbox-data-cells = <4>;
++                      status = "disabled";
++              };
++
++              mailbox5: mailbox@48840000 {
++                      compatible = "ti,omap4-mailbox";
++                      reg = <0x48840000 0x200>;
++                      interrupts = <0 136 0x4>;
++                      ti,hwmods = "mailbox5";
++                      ti,mbox-num-users = <4>;
++                      ti,mbox-num-fifos = <12>;
++                      #ti,mbox-data-cells = <4>;
++                      ti,mbox-names = "mbox-ipu1", "mbox-dsp1";
++                      ti,mbox-data = <6 4 0 2>, <5 1 0 2>;
++              };
++
++              mailbox6: mailbox@48842000 {
++                      compatible = "ti,omap4-mailbox";
++                      reg = <0x48842000 0x200>;
++                      interrupts = <0 141 0x4>;
++                      ti,hwmods = "mailbox6";
++                      ti,mbox-num-users = <4>;
++                      ti,mbox-num-fifos = <12>;
++                      #ti,mbox-data-cells = <4>;
++                      ti,mbox-names = "mbox-ipu2", "mbox-dsp2";
++                      ti,mbox-data = <6 4 0 2>, <5 1 0 2>;
++              };
++
++              mailbox7: mailbox@48844000 {
++                      compatible = "ti,omap4-mailbox";
++                      reg = <0x48844000 0x200>;
++                      ti,hwmods = "mailbox7";
++                      ti,mbox-num-users = <4>;
++                      ti,mbox-num-fifos = <12>;
++                      #ti,mbox-data-cells = <4>;
++                      status = "disabled";
++              };
++
++              mailbox8: mailbox@48846000 {
++                      compatible = "ti,omap4-mailbox";
++                      reg = <0x48846000 0x200>;
++                      ti,hwmods = "mailbox8";
++                      ti,mbox-num-users = <4>;
++                      ti,mbox-num-fifos = <12>;
++                      #ti,mbox-data-cells = <4>;
++                      status = "disabled";
++              };
++
++              mailbox9: mailbox@4885e000 {
++                      compatible = "ti,omap4-mailbox";
++                      reg = <0x4885e000 0x200>;
++                      ti,hwmods = "mailbox9";
++                      ti,mbox-num-users = <4>;
++                      ti,mbox-num-fifos = <12>;
++                      #ti,mbox-data-cells = <4>;
++                      status = "disabled";
++              };
++
++              mailbox10: mailbox@48860000 {
++                      compatible = "ti,omap4-mailbox";
++                      reg = <0x48860000 0x200>;
++                      ti,hwmods = "mailbox10";
++                      ti,mbox-num-users = <4>;
++                      ti,mbox-num-fifos = <12>;
++                      #ti,mbox-data-cells = <4>;
++                      status = "disabled";
++              };
++
++              mailbox11: mailbox@48862000 {
++                      compatible = "ti,omap4-mailbox";
++                      reg = <0x48862000 0x200>;
++                      ti,hwmods = "mailbox11";
++                      ti,mbox-num-users = <4>;
++                      ti,mbox-num-fifos = <12>;
++                      #ti,mbox-data-cells = <4>;
++                      status = "disabled";
++              };
++
++              mailbox12: mailbox@48864000 {
++                      compatible = "ti,omap4-mailbox";
++                      reg = <0x48864000 0x200>;
++                      ti,hwmods = "mailbox12";
++                      ti,mbox-num-users = <4>;
++                      ti,mbox-num-fifos = <12>;
++                      #ti,mbox-data-cells = <4>;
++                      status = "disabled";
++              };
++
++              mailbox13: mailbox@48802000 {
++                      compatible = "ti,omap4-mailbox";
++                      reg = <0x48802000 0x200>;
++                      ti,hwmods = "mailbox13";
++                      ti,mbox-num-users = <4>;
++                      ti,mbox-num-fifos = <12>;
++                      #ti,mbox-data-cells = <4>;
++                      status = "disabled";
++              };
++
++              timer1: timer@4ae18000 {
++                      compatible = "ti,omap5430-timer";
++                      reg = <0x4ae18000 0x80>;
++                      interrupts = <0 37 0x4>;
++                      ti,hwmods = "timer1";
++                      clocks = <&timer1_gfclk_mux>;
++                      clock-names = "fck";
++                      ti,timer-alwon;
++              };
++
++              timer2: timer@48032000 {
++                      compatible = "ti,omap5430-timer";
++                      reg = <0x48032000 0x80>;
++                      interrupts = <0 38 0x4>;
++                      ti,hwmods = "timer2";
++                      clocks = <&timer2_gfclk_mux>;
++                      clock-names = "fck";
++              };
++
++              timer3: timer@48034000 {
++                      compatible = "ti,omap5430-timer";
++                      reg = <0x48034000 0x80>;
++                      interrupts = <0 39 0x4>;
++                      ti,hwmods = "timer3";
++                      clocks = <&timer3_gfclk_mux>;
++                      clock-names = "fck";
++              };
++
++              timer4: timer@48036000 {
++                      compatible = "ti,omap5430-timer";
++                      reg = <0x48036000 0x80>;
++                      interrupts = <0 40 0x4>;
++                      ti,hwmods = "timer4";
++                      clocks = <&timer4_gfclk_mux>;
++                      clock-names = "fck";
++              };
++
++              timer5: timer@48820000 {
++                      compatible = "ti,omap5430-timer";
++                      reg = <0x48820000 0x80>;
++                      interrupts = <0 41 0x4>;
++                      ti,hwmods = "timer5";
++                      clocks = <&timer5_gfclk_mux>;
++                      clock-names = "fck";
++                      ti,timer-dsp;
++              };
++
++              timer6: timer@48822000 {
++                      compatible = "ti,omap5430-timer";
++                      reg = <0x48822000 0x80>;
++                      interrupts = <0 42 0x4>;
++                      ti,hwmods = "timer6";
++                      clocks = <&timer6_gfclk_mux>;
++                      clock-names = "fck";
++                      ti,timer-dsp;
++                      ti,timer-pwm;
++              };
++
++              timer7: timer@48824000 {
++                      compatible = "ti,omap5430-timer";
++                      reg = <0x48824000 0x80>;
++                      interrupts = <0 43 0x4>;
++                      ti,hwmods = "timer7";
++                      clocks = <&timer7_gfclk_mux>;
++                      clock-names = "fck";
++                      ti,timer-dsp;
++              };
++
++              timer8: timer@48826000 {
++                      compatible = "ti,omap5430-timer";
++                      reg = <0x48826000 0x80>;
++                      interrupts = <0 44 0x4>;
++                      ti,hwmods = "timer8";
++                      clocks = <&timer8_gfclk_mux>;
++                      clock-names = "fck";
++                      ti,timer-dsp;
++                      ti,timer-pwm;
++              };
++
++              timer9: timer@4803e000 {
++                      compatible = "ti,omap5430-timer";
++                      reg = <0x4803e000 0x80>;
++                      interrupts = <0 45 0x4>;
++                      ti,hwmods = "timer9";
++                      clocks = <&timer9_gfclk_mux>;
++                      clock-names = "fck";
++              };
++
++              timer10: timer@48086000 {
++                      compatible = "ti,omap5430-timer";
++                      reg = <0x48086000 0x80>;
++                      interrupts = <0 46 0x4>;
++                      ti,hwmods = "timer10";
++                      clocks = <&timer10_gfclk_mux>;
++                      clock-names = "fck";
++              };
++
++              timer11: timer@48088000 {
++                      compatible = "ti,omap5430-timer";
++                      reg = <0x48088000 0x80>;
++                      interrupts = <0 47 0x4>;
++                      ti,hwmods = "timer11";
++                      clocks = <&timer11_gfclk_mux>;
++                      clock-names = "fck";
++                      ti,timer-pwm;
++              };
++
++              timer13: timer@48828000 {
++                      compatible = "ti,omap5430-timer";
++                      reg = <0x48828000 0x80>;
++                      ti,hwmods = "timer13";
++                      status = "disabled";
++              };
++
++              timer14: timer@4882a000 {
++                      compatible = "ti,omap5430-timer";
++                      reg = <0x4882a000 0x80>;
++                      ti,hwmods = "timer14";
++                      status = "disabled";
++              };
++
++              timer15: timer@4882c000 {
++                      compatible = "ti,omap5430-timer";
++                      reg = <0x4882c000 0x80>;
++                      ti,hwmods = "timer15";
++                      status = "disabled";
++              };
++
++              timer16: timer@4882e000 {
++                      compatible = "ti,omap5430-timer";
++                      reg = <0x4882e000 0x80>;
++                      ti,hwmods = "timer16";
++                      status = "disabled";
++              };
++
++              wdt2: wdt@4ae14000 {
++                      compatible = "ti,omap4-wdt";
++                      reg = <0x4ae14000 0x80>;
++                      interrupts = <0 80 0x4>;
++                      ti,hwmods = "wd_timer2";
++                      clocks = <&sys_32k_ck>;
++                      clock-names = "fck";
++              };
++
++              i2c1: i2c@48070000 {
++                      compatible = "ti,omap4-i2c";
++                      reg = <0x48070000 0x100>;
++                      interrupts = <0 56 0x4>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      ti,hwmods = "i2c1";
++                      clocks = <&func_96m_fclk>;
++                      clock-names = "fck";
++                      status = "disabled";
++              };
++
++              i2c2: i2c@48072000 {
++                      compatible = "ti,omap4-i2c";
++                      reg = <0x48072000 0x100>;
++                      interrupts = <0 57 0x4>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      ti,hwmods = "i2c2";
++                      clocks = <&func_96m_fclk>;
++                      clock-names = "fck";
++                      status = "disabled";
++              };
++
++              i2c3: i2c@48060000 {
++                      compatible = "ti,omap4-i2c";
++                      reg = <0x48060000 0x100>;
++                      interrupts = <0 61 0x4>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      ti,hwmods = "i2c3";
++                      clocks = <&func_96m_fclk>;
++                      clock-names = "fck";
++                      status = "disabled";
++              };
++
++              i2c4: i2c@4807a000 {
++                      compatible = "ti,omap4-i2c";
++                      reg = <0x4807a000 0x100>;
++                      interrupts = <0 62 0x4>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      ti,hwmods = "i2c4";
++                      clocks = <&func_96m_fclk>;
++                      clock-names = "fck";
++                      status = "disabled";
++              };
++
++              i2c5: i2c@4807c000 {
++                      compatible = "ti,omap4-i2c";
++                      reg = <0x4807c000 0x100>;
++                      interrupts = <0 60 0x4>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      ti,hwmods = "i2c5";
++                      clocks = <&func_96m_fclk>;
++                      clock-names = "fck";
++                      status = "disabled";
++              };
++
++              mmc1: mmc@4809c000 {
++                      compatible = "ti,omap4-hsmmc";
++                      reg = <0x4809c000 0x400>;
++                      interrupts = <0 83 0x4>;
++                      ti,hwmods = "mmc1";
++                      clocks = <&mmc1_fclk_div>, <&mmc1_clk32k>;
++                      clock-names = "fck", "clk32k";
++                      ti,dual-volt;
++                      ti,needs-special-reset;
++                      dmas = <&sdma 61>, <&sdma 62>;
++                      dma-names = "tx", "rx";
++                      status = "disabled";
++              };
++
++              mmc2: mmc@480b4000 {
++                      compatible = "ti,omap4-hsmmc";
++                      reg = <0x480b4000 0x400>;
++                      interrupts = <0 86 0x4>;
++                      ti,hwmods = "mmc2";
++                      clocks = <&mmc2_fclk_div>, <&mmc2_clk32k>;
++                      clock-names = "fck", "clk32k";
++                      ti,needs-special-reset;
++                      dmas = <&sdma 47>, <&sdma 48>;
++                      dma-names = "tx", "rx";
++                      status = "disabled";
++              };
++
++              mmc3: mmc@480ad000 {
++                      compatible = "ti,omap4-hsmmc";
++                      reg = <0x480ad000 0x400>;
++                      interrupts = <0 94 0x4>;
++                      ti,hwmods = "mmc3";
++                      clocks = <&mmc3_gfclk_div>, <&mmc3_clk32k>;
++                      clock-names = "fck", "clk32k";
++                      ti,needs-special-reset;
++                      dmas = <&sdma 77>, <&sdma 78>;
++                      dma-names = "tx", "rx";
++                      status = "disabled";
++              };
++
++              mmc4: mmc@480d1000 {
++                      compatible = "ti,omap4-hsmmc";
++                      reg = <0x480d1000 0x400>;
++                      interrupts = <0 96 0x4>;
++                      ti,hwmods = "mmc4";
++                      clocks = <&mmc4_gfclk_div>, <&mmc4_clk32k>;
++                      clock-names = "fck", "clk32k";
++                      ti,needs-special-reset;
++                      dmas = <&sdma 57>, <&sdma 58>;
++                      dma-names = "tx", "rx";
++                      status = "disabled";
++              };
++
++              qspi: qspi@4b300000 {
++                      compatible = "ti,dra7xxx-qspi";
++                      reg = <0x4b300000 0x100>, <0x4a002558 0x4>,
++                              <0x5c000000 0x3ffffff>;
++                      reg-names = "qspi_base",
++                              "qspi_ctrlmod",
++                              "qspi_mmap";
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      ti,hwmods = "qspi";
++                      ti,spi-num-cs = <4>;
++                      interrupts = <0 124 0x4>;
++                      mmap_read;
++              };
++
++              omap_control_sata: control-phy@4a002374 {
++                      compatible = "ti,control-phy-pipe3";
++                      reg = <0x4a002374 0x4>;
++                      reg-names = "power";
++                      clocks = <&sys_clkin1>;
++                      clock-names = "sysclk";
++              };
++
++              ocp2scp@4a090000 {
++                      compatible = "ti,omap-ocp2scp";
++                      #address-cells = <1>;
++                      #size-cells = <1>;
++                      ranges;
++                      ti,hwmods = "ocp2scp3";
++                      reg = <0x4a090000 0x400>;       /* ocp2scp3 */
++                      sata_phy: sata-phy@4A096000 {
++                              compatible = "ti,phy-pipe3-sata";
++                              reg = <0x4A096000 0x80>, /* phy_rx */
++                                    <0x4A096400 0x64>, /* phy_tx */
++                                    <0x4A096800 0x40>; /* pll_ctrl */
++                              reg-names = "phy_rx", "phy_tx", "pll_ctrl";
++                              ctrl-module = <&omap_control_sata>;
++                              clocks = <&sata_ref_clk>;
++                              clock-names = "refclk";
++                              #phy-cells = <0>;
++                      };
++              };
++
++              sata@4a141100 {
++                      compatible = "ti,sata";
++                      ti,hwmods = "sata";
++                      reg = <0x4a141100 0x100>;
++                      #address-cells = <1>;
++                      #size-cells = <1>;
++                      ranges;
++                      sata@4a140000 {
++                                compatible = "snps,dwc-ahci";
++                                reg = <0x4a140000 0x1100>;
++                                interrupts = <0 54 0x4>;
++                                phys = <&sata_phy>;
++                                phy-names = "sata-phy";
++                      };
++              };
++
++
++              mcspi1: spi@48098000 {
++                      compatible = "ti,omap4-mcspi";
++                      reg = <0x48098000 0x200>;
++                      interrupts = <0 65 0x4>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      ti,hwmods = "mcspi1";
++                      clocks = <&func_48m_fclk>;
++                      clock-names = "fck";
++                      ti,spi-num-cs = <4>;
++                      dmas = <&sdma 35>,
++                             <&sdma 36>,
++                             <&sdma 37>,
++                             <&sdma 38>,
++                             <&sdma 39>,
++                             <&sdma 40>,
++                             <&sdma 41>,
++                             <&sdma 42>;
++                      dma-names = "tx0", "rx0", "tx1", "rx1",
++                                  "tx2", "rx2", "tx3", "rx3";
++                      status = "disabled";
++              };
++
++              mcspi2: spi@4809a000 {
++                      compatible = "ti,omap4-mcspi";
++                      reg = <0x4809a000 0x200>;
++                      interrupts = <0 66 0x4>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      ti,hwmods = "mcspi2";
++                      clocks = <&func_48m_fclk>;
++                      clock-names = "fck";
++                      ti,spi-num-cs = <2>;
++                      dmas = <&sdma 43>,
++                             <&sdma 44>,
++                             <&sdma 45>,
++                             <&sdma 46>;
++                      dma-names = "tx0", "rx0", "tx1", "rx1";
++                      status = "disabled";
++              };
++
++              mcspi3: spi@480b8000 {
++                      compatible = "ti,omap4-mcspi";
++                      reg = <0x480b8000 0x200>;
++                      interrupts = <0 91 0x4>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      ti,hwmods = "mcspi3";
++                      clocks = <&func_48m_fclk>;
++                      clock-names = "fck";
++                      ti,spi-num-cs = <2>;
++                      dmas = <&sdma 15>, <&sdma 16>;
++                      dma-names = "tx0", "rx0";
++                      status = "disabled";
++              };
++
++              mcspi4: spi@480ba000 {
++                      compatible = "ti,omap4-mcspi";
++                      reg = <0x480ba000 0x200>;
++                      interrupts = <0 48 0x4>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      ti,hwmods = "mcspi4";
++                      clocks = <&func_48m_fclk>;
++                      clock-names = "fck";
++                      ti,spi-num-cs = <1>;
++                      dmas = <&sdma 70>, <&sdma 71>;
++                      dma-names = "tx0", "rx0";
++                      status = "disabled";
++              };
++
++              rtcss@48838000 {
++                      compatible = "ti,da830-rtc";
++                      reg = <0x48838000 0x100>;
++                      interrupts = <0 159 0x4>,
++                                   <0 159 0x4>;
++                      ti,hwmods = "rtcss";
++                      clocks = <&sys_32k_ck>;
++                      clock-names = "fck";
++              };
++
++              omap_control_usb2phy1: control-phy@4a002300 {
++                      compatible = "ti,control-phy-usb2";
++                      reg = <0x4a002300 0x4>;
++                      reg-names = "power";
++              };
++
++              omap_control_usb3phy1: control-phy@4a002370 {
++                      compatible = "ti,control-phy-pipe3";
++                      reg = <0x4a002370 0x4>;
++                      reg-names = "power";
++              };
++
++              omap_control_usb2phy2: control-phy@0x4a002e74 {
++                      compatible = "ti,control-phy-dra7usb2";
++                      reg = <0x4a002e74 0x4>;
++                      reg-names = "power";
++              };
++
++              ocp2scp@4a080000 {
++                      compatible = "ti,omap-ocp2scp";
++                      #address-cells = <1>;
++                      #size-cells = <1>;
++                      ranges;
++                      ti,hwmods = "ocp2scp1";
++                      reg = <0x4a080000 0x400>;       /* ocp2scp1 */
++
++                      usb2_phy1: usb2phy1@4a084000 {
++                              compatible = "ti,omap-usb2";
++                              reg = <0x4a084000 0x400>;
++                              ctrl-module = <&omap_control_usb2phy1>;
++                              clocks = <&usb_phy1_always_on_clk32k>,
++                                       <&usb_otg_ss1_refclk960m>;
++                              clock-names =   "wkupclk",
++                                              "refclk";
++                              #phy-cells = <0>;
++                      };
++
++                      usb2_phy2: usb2phy2@4a085000 {
++                              compatible = "ti,omap-usb2";
++                              reg = <0x4a085000 0x400>;
++                              ctrl-module = <&omap_control_usb2phy2>;
++                              clocks = <&usb_phy2_always_on_clk32k>,
++                                       <&usb_otg_ss2_refclk960m>;
++                              clock-names =   "wkupclk",
++                                              "refclk";
++                              #phy-cells = <0>;
++                      };
++
++                      usb3_phy1: usb3phy@4a084400 {
++                              compatible = "ti,phy-pipe3-usb3";
++                              reg = <0x4a084400 0x80>,
++                                    <0x4a084800 0x64>,
++                                    <0x4a084c00 0x40>;
++                              reg-names = "phy_rx", "phy_tx", "pll_ctrl";
++                              ctrl-module = <&omap_control_usb3phy1>;
++                              clocks = <&usb_phy1_always_on_clk32k>,
++                                       <&usb_otg_ss1_refclk960m>,
++                                       <&dpll_core_h13x2_ck>;
++                              clock-names =   "wkupclk",
++                                              "refclk",
++                                              "refclk2";
++                              #phy-cells = <0>;
++                      };
++              };
++
++              dwc3_1: omap_dwc3_1@48880000 {
++                      compatible = "ti,dwc3";
++                      ti,hwmods = "usb_otg_ss1";
++                      reg = <0x48880000 0x10000>;
++                      interrupts = <0 77 4>;
++                      #address-cells = <1>;
++                      #size-cells = <1>;
++                      utmi-mode = <2>;
++                      ranges;
++                      usb1: usb@48890000 {
++                              compatible = "synopsys,dwc3";
++                              reg = <0x48890000 0x17000>;
++                              interrupts = <0 76 4>;
++                              phys = <&usb2_phy1>, <&usb3_phy1>;
++                              phy-names = "usb2-phy", "usb3-phy";
++                              tx-fifo-resize;
++                              maximum-speed = "super-speed";
++                              dr_mode = "otg";
++                      };
++              };
++
++              dwc3_2: omap_dwc3_2@488c0000 {
++                      compatible = "ti,dwc3";
++                      ti,hwmods = "usb_otg_ss2";
++                      reg = <0x488c0000 0x10000>;
++                      interrupts = <0 92 4>;
++                      #address-cells = <1>;
++                      #size-cells = <1>;
++                      utmi-mode = <2>;
++                      ranges;
++                      usb2: usb@488d0000 {
++                              compatible = "synopsys,dwc3";
++                              reg = <0x488d0000 0x17000>;
++                              interrupts = <0 78 4>;
++                              phys = <&usb2_phy2>;
++                              phy-names = "usb2-phy";
++                              tx-fifo-resize;
++                              maximum-speed = "high-speed";
++                              dr_mode = "otg";
++                      };
++              };
++
++              /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
++              dwc3_3: omap_dwc3_3@48900000 {
++                      compatible = "ti,dwc3";
++                      ti,hwmods = "usb_otg_ss3";
++                      reg = <0x48900000 0x10000>;
++              /*      interrupts = <0 TBD 4>; */
++                      #address-cells = <1>;
++                      #size-cells = <1>;
++                      utmi-mode = <2>;
++                      ranges;
++                      status = "disabled";
++                      usb3: usb@48910000 {
++                              compatible = "synopsys,dwc3";
++                              reg = <0x48910000 0x17000>;
++              /*              interrupts = <0 93 4>; */
++                              tx-fifo-resize;
++                              maximum-speed = "high-speed";
++                              dr_mode = "otg";
++                      };
++              };
++
++              dwc3_4: omap_dwc3_4@48940000 {
++                      compatible = "ti,dwc3";
++                      ti,hwmods = "usb_otg_ss4";
++                      reg = <0x48940000 0x10000>;
++              /*      interrupts = <0 TBD 4>; */
++                      #address-cells = <1>;
++                      #size-cells = <1>;
++                      utmi-mode = <2>;
++                      ranges;
++                      status = "disabled";
++                      usb4: usb@48950000 {
++                              compatible = "synopsys,dwc3";
++                              reg = <0x48950000 0x17000>;
++              /*              interrupts = <0 TBD 4>; */
++                              tx-fifo-resize;
++                              maximum-speed = "high-speed";
++                              dr_mode = "otg";
++                      };
++              };
++
++              dmm: dmm@4e000000 {
++                      compatible = "ti,omap5-dmm";
++                      reg = <0x4e000000 0x800>;
++                      interrupts = <0 113 0x4>;
++                      ti,hwmods = "dmm";
++              };
++
++              dss: dss@58000000 {
++                      compatible = "ti,omap4-dss", "simple-bus";
++                      reg = <0x58000000 0x80>,
++                            <0x58004000 0x340>,
++                            <0x58009000 0x340>;
++                      ti,hwmods = "dss_core";
++                      #address-cells = <1>;
++                      #size-cells = <1>;
++                      ranges;
++
++                      dispc@58001000 {
++                              compatible = "ti,omap4-dispc";
++                              reg = <0x58001000 0x1000>;
++                              interrupts = <0 25 0x4>;
++                              ti,hwmods = "dss_dispc";
++                      };
++
++                      dpi1: encoder@0 {
++                              compatible = "ti,dra7xx-dpi";
++                              id = <0>;
++                              channel = <0>;
++                      };
++
++                      dpi2: encoder@1 {
++                              compatible = "ti,dra7xx-dpi";
++                              id = <1>;
++                      };
++
++                      dpi3: encoder@2 {
++                              compatible = "ti,dra7xx-dpi";
++                              id = <2>;
++                      };
++
++                      hdmi: encoder@58040000 {
++                              compatible = "ti,omap5-hdmi";
++                              reg = <0x58040000 0x100>,
++                                    <0x58040200 0x40>,
++                                    <0x58040300 0x40>,
++                                    <0x58060000 0x19000>;
++                              reg-names = "hdmi_wp", "hdmi_pllctrl",
++                                          "hdmi_txphy", "hdmi_core";
++                              interrupts = <0 101 0x4>;
++                              ti,hwmods = "dss_hdmi";
++                      };
++              };
++
++              vpe {
++                      compatible = "ti,vpe";
++                      ti,hwmods = "vpe";
++                      reg = <0x489d0000 0x120>,
++                            <0x489d0300 0x20>,
++                            <0x489d0400 0x20>,
++                            <0x489d0500 0x20>,
++                            <0x489d0600 0x3c>,
++                            <0x489d0700 0x80>,
++                            <0x489d5700 0x18>,
++                            <0x489dd000 0x400>;
++                      reg-names = "vpe_top",
++                                  "vpe_chr_us0",
++                                  "vpe_chr_us1",
++                                  "vpe_chr_us2",
++                                  "vpe_dei",
++                                  "vpe_sc",
++                                  "vpe_csc",
++                                  "vpdma";
++                      interrupts = <0 0x9c 0x4>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++              };
++
++              mac: ethernet@4a100000 {
++                      compatible = "ti,cpsw";
++                      ti,hwmods = "gmac";
++                      cpdma_channels = <8>;
++                      ale_entries = <1024>;
++                      bd_ram_size = <0x2000>;
++                      no_bd_ram = <0>;
++                      rx_descs = <64>;
++                      mac_control = <0x20>;
++                      slaves = <2>;
++                      active_slave = <0>;
++                      cpts_clock_mult = <0x80000000>;
++                      cpts_clock_shift = <29>;
++                      reg = <0x48484000 0x800
++                             0x48485200 0x100>;
++                      #address-cells = <1>;
++                      #size-cells = <1>;
++                      /*
++                       * rx_thresh_pend
++                       * rx_pend
++                       * tx_pend
++                       * misc_pend
++                       */
++                      interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
++                                   <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
++                                   <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
++                                   <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
++                      ranges;
++                      status = "disabled";
++
++                      davinci_mdio: mdio@4a101000 {
++                              compatible = "ti,davinci_mdio";
++                              #address-cells = <1>;
++                              #size-cells = <0>;
++                              ti,hwmods = "davinci_mdio";
++                              bus_freq = <1000000>;
++                              reg = <0x48485000 0x100>;
++                      };
++
++                      cpsw_emac0: slave@4a100200 {
++                              /* Filled in by U-Boot */
++                              mac-address = [ 00 00 00 00 00 00 ];
++                      };
++
++                      cpsw_emac1: slave@4a100300 {
++                              /* Filled in by U-Boot */
++                              mac-address = [ 00 00 00 00 00 00 ];
++                      };
++              };
++
++              elm: elm@48078000 {
++                      compatible = "ti,am3352-elm";
++                      /* compatible = "ti,elm"; */
++                      reg = <0x48078000 0x2000>;
++                      interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
++                      ti,hwmods = "elm";
++                      status = "disabled";
++              };
++
++              gpmc: gpmc@50000000 {
++                      compatible = "ti,am3352-gpmc";
++              /*      compatible = "ti,gpmc"; */
++                      ti,hwmods = "gpmc";
++                      reg = <0x50000000 0x2000>;
++                      interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
++                      gpmc,num-cs = <8>;
++                      gpmc,num-waitpins = <2>;
++                      #address-cells = <2>;
++                      #size-cells = <1>;
++                      status = "disabled";
++              };
++
++              aes: aes@4b500000 {
++                      compatible = "ti,omap4-aes";
++                      ti,hwmods = "aes";
++                      reg = <0x4b500000 0xa0>;
++                      interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
++                      dmas = <&sdma 111>, <&sdma 110>;
++                      dma-names = "tx", "rx";
++                      clocks = <&l3_iclk_div>;
++                      clock-names = "fck";
++              };
++
++              des: des@480a5000 {
++                      compatible = "ti,omap4-des";
++                      ti,hwmods = "des";
++                      reg = <0x480a5000 0xa0>;
++                      interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
++                      dmas = <&sdma 117>, <&sdma 116>;
++                      dma-names = "tx", "rx";
++                      clocks = <&l3_iclk_div>;
++                      clock-names = "fck";
++              };
++      };
++
++      clocks {
++              #address-cells = <1>;
++              #size-cells = <1>;
++              ranges;
++              /include/ "dra7xx-clocks.dtsi"
++      };
++
++      clockdomains {
++              coreaon_clkdm: coreaon_clkdm {
++                      compatible = "ti,clockdomain";
++                      clocks = <&dpll_usb_ck>;
++              };
++      };
++};
+--- /dev/null
++++ b/arch/arm/boot/dts/dra7-evm.dts
+@@ -0,0 +1,761 @@
++/*
++ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++/dts-v1/;
++
++#include "dra7.dtsi"
++#include <dt-bindings/pinctrl/dra7xx.h>
++
++/ {
++      model = "TI DRA7";
++      compatible = "ti,dra7-evm", "ti,dra752", "ti,dra7";
++
++      memory {
++              device_type = "memory";
++              reg = <0x80000000 0x60000000>; /* 1536 MB */
++      };
++
++      extcon1: gpio_usbvid_extcon1 {
++              compatible = "ti,gpio-usb-id";
++              gpios = <&gpio21 1 0>;
++      };
++
++      extcon2: gpio_usbvid_extcon2 {
++              compatible = "ti,gpio-usb-id";
++              gpios = <&gpio21 2 0>;
++      };
++
++      mmc2_3v3: fixedregulator-mmc2 {
++              compatible = "regulator-fixed";
++              regulator-name = "mmc2_3v3";
++              regulator-min-microvolt = <3300000>;
++              regulator-max-microvolt = <3300000>;
++      };
++};
++
++&dra7_pmx_core {
++      pinctrl-names = "default";
++      pinctrl-0 = <
++              &vout1_pins
++              &irq_pins
++      >;
++
++      i2c1_pins: pinmux_i2c1_pins {
++              pinctrl-single,pins = <
++                      0x400 0x60000   /* i2c1_sda */
++                      0x404 0x60000   /* i2c1_scl */
++              >;
++      };
++
++      i2c2_pins: pinmux_i2c2_pins {
++              pinctrl-single,pins = <
++                      0x408 0x60000   /* i2c2_sda */
++                      0x40c 0x60000   /* i2c2_scl */
++              >;
++      };
++
++      i2c3_pins: pinmux_i2c3_pins {
++              pinctrl-single,pins = <
++                      0x410 0x60000   /* i2c3_sda */
++                      0x414 0x60000   /* i2c3_scl */
++              >;
++      };
++
++      irq_pins: pinmux_irq_pins {
++              pinctrl-single,pins = <
++                      0x420   0x1     /* Wakeup2 INPUT | MODE1 */
++              >;
++      };
++
++      mmc1_pins: pinmux_mmc1_pins {
++              pinctrl-single,pins = <
++                      0x36c 0x4000e   /* mmc1sdcd.gpio INPUT | MODE15 */
++              >;
++      };
++
++      mcspi1_pins: pinmux_mcspi1_pins {
++              pinctrl-single,pins = <
++                      0x3a4 0x40000   /* spi2_clk */
++                      0x3a8 0x40000   /* spi2_d1 */
++                      0x3ac 0x40000   /* spi2_d0 */
++                      0x3b0 0xc0000   /* spi2_cs0 */
++                      0x3b4 0xc0000   /* spi2_cs1 */
++                      0x3b8 0xe0006   /* spi2_cs2 */
++                      0x3bc 0xe0006   /* spi2_cs3 */
++              >;
++      };
++
++      mcspi2_pins: pinmux_mcspi2_pins {
++              pinctrl-single,pins = <
++                      0x3c0 0x40000   /* spi2_sclk */
++                      0x3c4 0xc0000   /* spi2_d1 */
++                      0x3c8 0xc0000   /* spi2_d1 */
++                      0x3cc 0xe0000   /* spi2_cs0 */
++              >;
++      };
++
++      uart1_pins: pinmux_uart1_pins {
++              pinctrl-single,pins = <
++                      0x3e0 0xe0000   /* uart1_rxd */
++                      0x3e4 0xe0000   /* uart1_txd */
++                      0x3e8 0x60003   /* uart1_ctsn */
++                      0x3ec 0x60003   /* uart1_rtsn */
++              >;
++      };
++
++      uart2_pins: pinmux_uart2_pins {
++              pinctrl-single,pins = <
++                      0x3f0 0x60000 /* uart2_rxd */
++                      0x3f4 0x60000 /* uart2_txd */
++                      0x3f8 0x60000 /* uart2_ctsn */
++                      0x3fc 0x60000 /* uart2_rtsn */
++              >;
++      };
++
++      uart3_pins: pinmux_uart3_pins {
++              pinctrl-single,pins = <
++                      0x248 0xc0000 /* uart3_rxd */
++                      0x24c 0xc0000 /* uart3_txd */
++              >;
++      };
++
++      qspi1_pins: pinmux_qspi1_pins {
++              pinctrl-single,pins = <
++                      0x4c 0x40001  /* gpmc_a3.qspi1_cs2 */
++                      0x50 0x40001  /* gpmc_a4.qspi1_cs3 */
++                      0x74 0x40001  /* gpmc_a13.qspi1_rtclk */
++                      0x78 0x40001  /* gpmc_a14.qspi1_d3 */
++                      0x7c 0x40001  /* gpmc_a15.qspi1_d2 */
++                      0x80 0x40001  /* gpmc_a16.qspi1_d1 */
++                      0x84 0x40001  /* gpmc_a17.qspi1_d0 */
++                      0x88 0x40001  /* qpmc_a18.qspi1_sclk */
++                      0xb8 0x60001  /* gpmc_cs2.qspi1_cs0 */
++                      0xbc 0x60001  /* gpmc_cs3.qspi1_cs1 */
++              >;
++      };
++
++      usb1_pins: pinmux_usb1_pins {
++                pinctrl-single,pins = <
++                      0x280   0xc0000 /* usb1_drvvbus, SLOW_SLEW | PULLUPEN | MODE0 */
++                >;
++        };
++
++      usb2_pins: pinmux_usb2_pins {
++                pinctrl-single,pins = <
++                      0x284   0xc0000 /* usb2_drvvbus, SLOW_SLEW | PULLUPEN | MODE0 */
++                >;
++        };
++
++      vout1_pins: pinmux_vout1_pins {
++              pinctrl-single,pins = <
++                      0x1C8   0x0     /* vout1_clk OUTPUT | MODE0 */
++                      0x1CC   0x0     /* vout1_de OUTPUT | MODE0 */
++                      0x1D0   0x0     /* vout1_fld OUTPUT | MODE0 */
++                      0x1D4   0x0     /* vout1_hsync OUTPUT | MODE0 */
++                      0x1D8   0x0     /* vout1_vsync OUTPUT | MODE0 */
++                      0x1DC   0x0     /* vout1_d0 OUTPUT | MODE0 */
++                      0x1E0   0x0     /* vout1_d1 OUTPUT | MODE0 */
++                      0x1E4   0x0     /* vout1_d2 OUTPUT | MODE0 */
++                      0x1E8   0x0     /* vout1_d3 OUTPUT | MODE0 */
++                      0x1EC   0x0     /* vout1_d4 OUTPUT | MODE0 */
++                      0x1F0   0x0     /* vout1_d5 OUTPUT | MODE0 */
++                      0x1F4   0x0     /* vout1_d6 OUTPUT | MODE0 */
++                      0x1F8   0x0     /* vout1_d7 OUTPUT | MODE0 */
++                      0x1FC   0x0     /* vout1_d8 OUTPUT | MODE0 */
++                      0x200   0x0     /* vout1_d9 OUTPUT | MODE0 */
++                      0x204   0x0     /* vout1_d10 OUTPUT | MODE0 */
++                      0x208   0x0     /* vout1_d11 OUTPUT | MODE0 */
++                      0x20C   0x0     /* vout1_d12 OUTPUT | MODE0 */
++                      0x210   0x0     /* vout1_d13 OUTPUT | MODE0 */
++                      0x214   0x0     /* vout1_d14 OUTPUT | MODE0 */
++                      0x218   0x0     /* vout1_d15 OUTPUT | MODE0 */
++                      0x21C   0x0     /* vout1_d16 OUTPUT | MODE0 */
++                      0x220   0x0     /* vout1_d17 OUTPUT | MODE0 */
++                      0x224   0x0     /* vout1_d18 OUTPUT | MODE0 */
++                      0x228   0x0     /* vout1_d19 OUTPUT | MODE0 */
++                      0x22C   0x0     /* vout1_d20 OUTPUT | MODE0 */
++                      0x230   0x0     /* vout1_d21 OUTPUT | MODE0 */
++                      0x234   0x0     /* vout1_d22 OUTPUT | MODE0 */
++                      0x238   0x0     /* vout1_d23 OUTPUT | MODE0 */
++              >;
++      };
++
++      cpsw_default: cpsw_default {
++              pinctrl-single,pins = <
++                      /* Slave 1 */
++                      0x250 (PIN_OUTPUT | MUX_MODE0)  /* rgmii1_tclk */
++                      0x254 (PIN_OUTPUT | MUX_MODE0)  /* rgmii1_tctl */
++                      0x258 (PIN_OUTPUT | MUX_MODE0)  /* rgmii1_td3 */
++                      0x25c (PIN_OUTPUT | MUX_MODE0)  /* rgmii1_td2 */
++                      0x260 (PIN_OUTPUT | MUX_MODE0)  /* rgmii1_td1 */
++                      0x264 (PIN_OUTPUT | MUX_MODE0)  /* rgmii1_td0 */
++                      0x268 (PIN_INPUT | MUX_MODE0)   /* rgmii1_rclk */
++                      0x26c (PIN_INPUT | MUX_MODE0)   /* rgmii1_rctl */
++                      0x270 (PIN_INPUT | MUX_MODE0)   /* rgmii1_rd3 */
++                      0x274 (PIN_INPUT | MUX_MODE0)   /* rgmii1_rd2 */
++                      0x278 (PIN_INPUT | MUX_MODE0)   /* rgmii1_rd1 */
++                      0x27c (PIN_INPUT | MUX_MODE0)   /* rgmii1_rd0 */
++
++                      /* Slave 2 */
++                      0x198 (PIN_OUTPUT | MUX_MODE3)  /* rgmii2_tclk */
++                      0x19c (PIN_OUTPUT | MUX_MODE3)  /* rgmii2_tctl */
++                      0x1a0 (PIN_OUTPUT | MUX_MODE3)  /* rgmii2_td3 */
++                      0x1a4 (PIN_OUTPUT | MUX_MODE3)  /* rgmii2_td2 */
++                      0x1a8 (PIN_OUTPUT | MUX_MODE3)  /* rgmii2_td1 */
++                      0x1ac (PIN_OUTPUT | MUX_MODE3)  /* rgmii2_td0 */
++                      0x1b0 (PIN_INPUT | MUX_MODE3)   /* rgmii2_rclk */
++                      0x1b4 (PIN_INPUT | MUX_MODE3)   /* rgmii2_rctl */
++                      0x1b8 (PIN_INPUT | MUX_MODE3)   /* rgmii2_rd3 */
++                      0x1bc (PIN_INPUT | MUX_MODE3)   /* rgmii2_rd2 */
++                      0x1c0 (PIN_INPUT | MUX_MODE3)   /* rgmii2_rd1 */
++                      0x1c4 (PIN_INPUT | MUX_MODE3)   /* rgmii2_rd0 */
++              >;
++
++      };
++      cpsw_sleep: cpsw_sleep {
++              pinctrl-single,pins = <
++                      /* Slave 1 */
++                      0x250 (PIN_OFF_NONE)
++                      0x254 (PIN_OFF_NONE)
++                      0x258 (PIN_OFF_NONE)
++                      0x25c (PIN_OFF_NONE)
++                      0x260 (PIN_OFF_NONE)
++                      0x264 (PIN_OFF_NONE)
++                      0x268 (PIN_OFF_NONE)
++                      0x26c (PIN_OFF_NONE)
++                      0x270 (PIN_OFF_NONE)
++                      0x274 (PIN_OFF_NONE)
++                      0x278 (PIN_OFF_NONE)
++                      0x27c (PIN_OFF_NONE)
++
++                      /* Slave 1 */
++                      0x198 (PIN_OFF_NONE)
++                      0x19c (PIN_OFF_NONE)
++                      0x1a0 (PIN_OFF_NONE)
++                      0x1a4 (PIN_OFF_NONE)
++                      0x1a8 (PIN_OFF_NONE)
++                      0x1ac (PIN_OFF_NONE)
++                      0x1b0 (PIN_OFF_NONE)
++                      0x1b4 (PIN_OFF_NONE)
++                      0x1b8 (PIN_OFF_NONE)
++                      0x1bc (PIN_OFF_NONE)
++                      0x1c0 (PIN_OFF_NONE)
++                      0x1c4 (PIN_OFF_NONE)
++              >;
++      };
++
++      davinci_mdio_default: davinci_mdio_default {
++              pinctrl-single,pins = <
++                      /* MDIO */
++                      0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0)   /* mdio_data */
++                      0x240 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mdio_clk */
++              >;
++      };
++
++      davinci_mdio_sleep: davinci_mdio_sleep {
++              pinctrl-single,pins = <
++                      0x23c (PIN_OFF_NONE)
++                      0x240 (PIN_OFF_NONE)
++              >;
++      };
++
++      nand_flash_x16: nand_flash_x16 {
++              /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
++               * So NAND flash requires following switch settings:
++               * SW5.9 (GPMC_WPN) = LOW
++               * SW5.1 (NAND_BOOTn) = HIGH */
++              pinctrl-single,pins = <
++                      0x0     0x70000 /* (PIN_INPUT | MUX_MODE0)      gpmc_ad0        */
++                      0x4     0x70000 /* (PIN_INPUT | MUX_MODE0)      gpmc_ad1        */
++                      0x8     0x70000 /* (PIN_INPUT | MUX_MODE0)      gpmc_ad2        */
++                      0xc     0x70000 /* (PIN_INPUT | MUX_MODE0)      gpmc_ad3        */
++                      0x10    0x70000 /* (PIN_INPUT | MUX_MODE0)      gpmc_ad4        */
++                      0x14    0x70000 /* (PIN_INPUT | MUX_MODE0)      gpmc_ad5        */
++                      0x18    0x70000 /* (PIN_INPUT | MUX_MODE0)      gpmc_ad6        */
++                      0x1c    0x70000 /* (PIN_INPUT | MUX_MODE0)      gpmc_ad7        */
++                      0x20    0x70000 /* (PIN_INPUT | MUX_MODE0)      gpmc_ad8        */
++                      0x24    0x70000 /* (PIN_INPUT | MUX_MODE0)      gpmc_ad9        */
++                      0x28    0x70000 /* (PIN_INPUT | MUX_MODE0)      gpmc_ad10       */
++                      0x2c    0x70000 /* (PIN_INPUT | MUX_MODE0)      gpmc_ad11       */
++                      0x30    0x70000 /* (PIN_INPUT | MUX_MODE0)      gpmc_ad12       */
++                      0x34    0x70000 /* (PIN_INPUT | MUX_MODE0)      gpmc_ad13       */
++                      0x38    0x70000 /* (PIN_INPUT | MUX_MODE0)      gpmc_ad14       */
++                      0x3c    0x70000 /* (PIN_INPUT | MUX_MODE0)      gpmc_ad15       */
++                      0xD8    0x70000 /* (PIN_INPUT | MUX_MODE0)      gpmc_wait0      */
++                      0xCC    0x0     /* (PIN_OUTPUT     | MUX_MODE0) gpmc_wen        */
++                      0xB4    0x0     /* (PIN_OUTPUT | MUX_MODE0)     gpmc_csn0       */
++                      0xC4    0x0     /* (PIN_OUTPUT     | MUX_MODE0) gpmc_advn_ale */
++                      0xC8    0x0     /* (PIN_OUTPUT     | MUX_MODE0) gpmc_oen_ren     */
++                      0xD0    0x0     /* (PIN_OUTPUT     | MUX_MODE0) gpmc_be0n_cle */
++              >;
++      };
++};
++
++&i2c1 {
++      status = "okay";
++      pinctrl-names = "default";
++      pinctrl-0 = <&i2c1_pins>;
++      clock-frequency = <400000>;
++
++      tps659038: tps659038@58 {
++              compatible = "ti,tps659038";
++              reg = <0x58>;
++
++              tps659038_pmic {
++                      compatible = "ti,tps659038-pmic";
++
++                      regulators {
++                              smps123_reg: smps123 {
++                                      /* VDD_MPU */
++                                              regulator-name = "smps123";
++                                              regulator-min-microvolt = < 850000>;
++                                              regulator-max-microvolt = <1250000>;
++                                              regulator-always-on;
++                                              regulator-boot-on;
++                                      };
++
++                              smps45_reg: smps45 {
++                                              /* VDD_DSPEVE */
++                                              regulator-name = "smps45";
++                                              regulator-min-microvolt = < 850000>;
++                                              regulator-max-microvolt = <1150000>;
++                                              regulator-boot-on;
++                                      };
++
++                              smps6_reg: smps6 {
++                                              /* VDD_GPU - over VDD_SMPS6 */
++                                              regulator-name = "smps6";
++                                              regulator-min-microvolt = <850000>;
++                                              regulator-max-microvolt = <12500000>;
++                                              regulator-boot-on;
++                                      };
++
++                              smps7_reg: smps7 {
++                                              /* CORE_VDD */
++                                              regulator-name = "smps7";
++                                              regulator-min-microvolt = <850000>;
++                                              regulator-max-microvolt = <1030000>;