add free bcm43xx driver as patch for brcm-2.6, needs more testing and Makefile change...
authorWaldemar Brodkorb <mail@waldemar-brodkorb.de>
Tue, 28 Mar 2006 23:37:21 +0000 (23:37 +0000)
committerWaldemar Brodkorb <mail@waldemar-brodkorb.de>
Tue, 28 Mar 2006 23:37:21 +0000 (23:37 +0000)
SVN-Revision: 3536

openwrt/target/linux/brcm-2.6/config
openwrt/target/linux/brcm-2.6/patches/005-bcm43xx-dscape-060328.patch [new file with mode: 0644]

index 38ddc40..81092f3 100644 (file)
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
 # Linux kernel version: 2.6.16
-# Thu Mar 23 15:31:19 2006
+# Wed Mar 29 00:13:01 2006
 #
 CONFIG_MIPS=y
 
@@ -586,6 +586,12 @@ CONFIG_BT_HCIUART_BCSP=y
 # CONFIG_BT_HCIBLUECARD is not set
 # CONFIG_BT_HCIBTUART is not set
 # CONFIG_BT_HCIVHCI is not set
+CONFIG_D80211=m
+CONFIG_D80211_DEBUG=y
+CONFIG_D80211_VERBOSE_DEBUG=y
+# CONFIG_TKIP_DEBUG is not set
+# CONFIG_D80211_DEBUG_COUNTERS is not set
+# CONFIG_HOSTAPD_WPA_TESTING is not set
 CONFIG_IEEE80211=m
 # CONFIG_IEEE80211_DEBUG is not set
 CONFIG_IEEE80211_CRYPT_WEP=m
@@ -955,6 +961,13 @@ CONFIG_HOSTAP_FIRMWARE_NVRAM=y
 CONFIG_HOSTAP_PLX=m
 CONFIG_HOSTAP_PCI=m
 CONFIG_HOSTAP_CS=m
+CONFIG_BCM43XX_D80211=m
+CONFIG_BCM43XX_D80211_DEBUG=y
+CONFIG_BCM43XX_D80211_DMA=y
+CONFIG_BCM43XX_D80211_PIO=y
+CONFIG_BCM43XX_D80211_DMA_AND_PIO_MODE=y
+# CONFIG_BCM43XX_D80211_DMA_MODE is not set
+# CONFIG_BCM43XX_D80211_PIO_MODE is not set
 CONFIG_NET_WIRELESS=y
 
 #
diff --git a/openwrt/target/linux/brcm-2.6/patches/005-bcm43xx-dscape-060328.patch b/openwrt/target/linux/brcm-2.6/patches/005-bcm43xx-dscape-060328.patch
new file mode 100644 (file)
index 0000000..0611a0b
--- /dev/null
@@ -0,0 +1,35744 @@
+diff -Nur linux-2.6.16/drivers/net/wireless/bcm43xx-d80211/bcm43xx_debugfs.c linux-2.6.16-bcm43xx/drivers/net/wireless/bcm43xx-d80211/bcm43xx_debugfs.c
+--- linux-2.6.16/drivers/net/wireless/bcm43xx-d80211/bcm43xx_debugfs.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.16-bcm43xx/drivers/net/wireless/bcm43xx-d80211/bcm43xx_debugfs.c 2006-03-28 22:16:14.000000000 +0200
+@@ -0,0 +1,499 @@
++/*
++
++  Broadcom BCM43xx wireless driver
++
++  debugfs driver debugging code
++
++  Copyright (c) 2005 Michael Buesch <mbuesch@freenet.de>
++
++  This program is free software; you can redistribute it and/or modify
++  it under the terms of the GNU General Public License as published by
++  the Free Software Foundation; either version 2 of the License, or
++  (at your option) any later version.
++
++  This program is distributed in the hope that it will be useful,
++  but WITHOUT ANY WARRANTY; without even the implied warranty of
++  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++  GNU General Public License for more details.
++
++  You should have received a copy of the GNU General Public License
++  along with this program; see the file COPYING.  If not, write to
++  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
++  Boston, MA 02110-1301, USA.
++
++*/
++
++
++
++#include <linux/fs.h>
++#include <linux/debugfs.h>
++#include <linux/slab.h>
++#include <linux/netdevice.h>
++#include <linux/pci.h>
++#include <asm/io.h>
++
++#include "bcm43xx.h"
++#include "bcm43xx_main.h"
++#include "bcm43xx_debugfs.h"
++#include "bcm43xx_dma.h"
++#include "bcm43xx_pio.h"
++#include "bcm43xx_xmit.h"
++
++#define REALLY_BIG_BUFFER_SIZE        (1024*256)
++
++static struct bcm43xx_debugfs fs;
++static char really_big_buffer[REALLY_BIG_BUFFER_SIZE];
++static DECLARE_MUTEX(big_buffer_sem);
++
++
++static ssize_t write_file_dummy(struct file *file, const char __user *buf,
++                              size_t count, loff_t *ppos)
++{
++      return count;
++}
++
++static int open_file_generic(struct inode *inode, struct file *file)
++{
++      file->private_data = inode->u.generic_ip;
++      return 0;
++}
++
++#define fappend(fmt, x...)    pos += snprintf(buf + pos, len - pos, fmt , ##x)
++
++static ssize_t devinfo_read_file(struct file *file, char __user *userbuf,
++                               size_t count, loff_t *ppos)
++{
++      const size_t len = REALLY_BIG_BUFFER_SIZE;
++
++      struct bcm43xx_private *bcm = file->private_data;
++      char *buf = really_big_buffer;
++      size_t pos = 0;
++      ssize_t res;
++      struct net_device *net_dev;
++      struct pci_dev *pci_dev;
++      unsigned long flags;
++      u16 tmp16;
++      int i;
++
++      down(&big_buffer_sem);
++
++      bcm43xx_lock_mmio(bcm, flags);
++      if (!bcm->initialized) {
++              fappend("Board not initialized.\n");
++              goto out;
++      }
++      net_dev = bcm->net_dev;
++      pci_dev = bcm->pci_dev;
++
++      /* This is where the information is written to the "devinfo" file */
++      fappend("*** %s devinfo ***\n", net_dev->name);
++      fappend("vendor:           0x%04x   device:           0x%04x\n",
++              pci_dev->vendor, pci_dev->device);
++      fappend("subsystem_vendor: 0x%04x   subsystem_device: 0x%04x\n",
++              pci_dev->subsystem_vendor, pci_dev->subsystem_device);
++      fappend("IRQ: %d\n", bcm->irq);
++      fappend("mmio_addr: 0x%p   mmio_len: %u\n", bcm->mmio_addr, bcm->mmio_len);
++      fappend("chip_id: 0x%04x   chip_rev: 0x%02x\n", bcm->chip_id, bcm->chip_rev);
++      if ((bcm->core_80211[0].rev >= 3) && (bcm43xx_read32(bcm, 0x0158) & (1 << 16)))
++              fappend("Radio disabled by hardware!\n");
++      if ((bcm->core_80211[0].rev < 3) && !(bcm43xx_read16(bcm, 0x049A) & (1 << 4)))
++              fappend("Radio disabled by hardware!\n");
++      fappend("board_vendor: 0x%04x   board_type: 0x%04x\n", bcm->board_vendor,
++              bcm->board_type);
++
++      fappend("\nCores:\n");
++#define fappend_core(name, info) fappend("core \"" name "\" %s, %s, id: 0x%04x, "     \
++                                       "rev: 0x%02x, index: 0x%02x\n",                \
++                                       (info).available                               \
++                                              ? "available" : "nonavailable",         \
++                                       (info).enabled                                 \
++                                              ? "enabled" : "disabled",               \
++                                       (info).id, (info).rev, (info).index)
++      fappend_core("CHIPCOMMON", bcm->core_chipcommon);
++      fappend_core("PCI", bcm->core_pci);
++      fappend_core("first 80211", bcm->core_80211[0]);
++      fappend_core("second 80211", bcm->core_80211[1]);
++#undef fappend_core
++      tmp16 = bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_CONTROL);
++      fappend("LEDs: ");
++      for (i = 0; i < BCM43xx_NR_LEDS; i++)
++              fappend("%d ", !!(tmp16 & (1 << i)));
++      fappend("\n");
++
++out:
++      bcm43xx_unlock_mmio(bcm, flags);
++      res = simple_read_from_buffer(userbuf, count, ppos, buf, pos);
++      up(&big_buffer_sem);
++      return res;
++}
++
++static ssize_t drvinfo_read_file(struct file *file, char __user *userbuf,
++                               size_t count, loff_t *ppos)
++{
++      const size_t len = REALLY_BIG_BUFFER_SIZE;
++
++      char *buf = really_big_buffer;
++      size_t pos = 0;
++      ssize_t res;
++
++      down(&big_buffer_sem);
++
++      /* This is where the information is written to the "driver" file */
++      fappend(KBUILD_MODNAME " driver\n");
++      fappend("Compiled at: %s %s\n", __DATE__, __TIME__);
++
++      res = simple_read_from_buffer(userbuf, count, ppos, buf, pos);
++      up(&big_buffer_sem);
++      return res;
++}
++
++static ssize_t spromdump_read_file(struct file *file, char __user *userbuf,
++                               size_t count, loff_t *ppos)
++{
++      const size_t len = REALLY_BIG_BUFFER_SIZE;
++
++      struct bcm43xx_private *bcm = file->private_data;
++      char *buf = really_big_buffer;
++      size_t pos = 0;
++      ssize_t res;
++      unsigned long flags;
++
++      down(&big_buffer_sem);
++      bcm43xx_lock_mmio(bcm, flags);
++      if (!bcm->initialized) {
++              fappend("Board not initialized.\n");
++              goto out;
++      }
++
++      /* This is where the information is written to the "sprom_dump" file */
++      fappend("boardflags: 0x%04x\n", bcm->sprom.boardflags);
++
++out:
++      bcm43xx_unlock_mmio(bcm, flags);
++      res = simple_read_from_buffer(userbuf, count, ppos, buf, pos);
++      up(&big_buffer_sem);
++      return res;
++}
++
++static ssize_t tsf_read_file(struct file *file, char __user *userbuf,
++                           size_t count, loff_t *ppos)
++{
++      const size_t len = REALLY_BIG_BUFFER_SIZE;
++
++      struct bcm43xx_private *bcm = file->private_data;
++      char *buf = really_big_buffer;
++      size_t pos = 0;
++      ssize_t res;
++      unsigned long flags;
++      u64 tsf;
++
++      down(&big_buffer_sem);
++      bcm43xx_lock_mmio(bcm, flags);
++      if (!bcm->initialized) {
++              fappend("Board not initialized.\n");
++              goto out;
++      }
++      bcm43xx_tsf_read(bcm, &tsf);
++      fappend("0x%08x%08x\n",
++              (unsigned int)((tsf & 0xFFFFFFFF00000000ULL) >> 32),
++              (unsigned int)(tsf & 0xFFFFFFFFULL));
++
++out:
++      bcm43xx_unlock_mmio(bcm, flags);
++      res = simple_read_from_buffer(userbuf, count, ppos, buf, pos);
++      up(&big_buffer_sem);
++      return res;
++}
++
++static ssize_t tsf_write_file(struct file *file, const char __user *user_buf,
++                            size_t count, loff_t *ppos)
++{
++      struct bcm43xx_private *bcm = file->private_data;
++      char *buf = really_big_buffer;
++      ssize_t buf_size;
++      ssize_t res;
++      unsigned long flags;
++      u64 tsf;
++
++      buf_size = min(count, sizeof (really_big_buffer) - 1);
++      down(&big_buffer_sem);
++      if (copy_from_user(buf, user_buf, buf_size)) {
++              res = -EFAULT;
++              goto out_up;
++      }
++      bcm43xx_lock_mmio(bcm, flags);
++      if (!bcm->initialized) {
++              printk(KERN_INFO PFX "debugfs: Board not initialized.\n");
++              res = -EFAULT;
++              goto out_unlock;
++      }
++      if (sscanf(buf, "%lli", &tsf) != 1) {
++              printk(KERN_INFO PFX "debugfs: invalid values for \"tsf\"\n");
++              res = -EINVAL;
++              goto out_unlock;
++      }
++      bcm43xx_tsf_write(bcm, tsf);
++      res = buf_size;
++      
++out_unlock:
++      bcm43xx_unlock_mmio(bcm, flags);
++out_up:
++      up(&big_buffer_sem);
++      return res;
++}
++
++static ssize_t txstat_read_file(struct file *file, char __user *userbuf,
++                              size_t count, loff_t *ppos)
++{
++      const size_t len = REALLY_BIG_BUFFER_SIZE;
++
++      struct bcm43xx_private *bcm = file->private_data;
++      char *buf = really_big_buffer;
++      size_t pos = 0;
++      ssize_t res;
++      unsigned long flags;
++      struct bcm43xx_dfsentry *e;
++      struct bcm43xx_xmitstatus *status;
++      int i, cnt, j = 0;
++
++      down(&big_buffer_sem);
++      bcm43xx_lock(bcm, flags);
++
++      fappend("Last %d logged xmitstatus blobs (Latest first):\n\n",
++              BCM43xx_NR_LOGGED_XMITSTATUS);
++      e = bcm->dfsentry;
++      if (e->xmitstatus_printing == 0) {
++              /* At the beginning, make a copy of all data to avoid
++               * concurrency, as this function is called multiple
++               * times for big logs. Without copying, the data might
++               * change between reads. This would result in total trash.
++               */
++              e->xmitstatus_printing = 1;
++              e->saved_xmitstatus_ptr = e->xmitstatus_ptr;
++              e->saved_xmitstatus_cnt = e->xmitstatus_cnt;
++              memcpy(e->xmitstatus_print_buffer, e->xmitstatus_buffer,
++                     BCM43xx_NR_LOGGED_XMITSTATUS * sizeof(*(e->xmitstatus_buffer)));
++      }
++      i = e->saved_xmitstatus_ptr - 1;
++      if (i < 0)
++              i = BCM43xx_NR_LOGGED_XMITSTATUS - 1;
++      cnt = e->saved_xmitstatus_cnt;
++      while (cnt) {
++              status = e->xmitstatus_print_buffer + i;
++              fappend("0x%02x:   cookie: 0x%04x,  flags: 0x%02x,  "
++                      "cnt1: 0x%02x,  cnt2: 0x%02x,  seq: 0x%04x,  "
++                      "unk: 0x%04x\n", j,
++                      status->cookie, status->flags,
++                      status->cnt1, status->cnt2, status->seq,
++                      status->unknown);
++              j++;
++              cnt--;
++              i--;
++              if (i < 0)
++                      i = BCM43xx_NR_LOGGED_XMITSTATUS - 1;
++      }
++
++      bcm43xx_unlock(bcm, flags);
++      res = simple_read_from_buffer(userbuf, count, ppos, buf, pos);
++      bcm43xx_lock(bcm, flags);
++      if (*ppos == pos) {
++              /* Done. Drop the copied data. */
++              e->xmitstatus_printing = 0;
++      }
++      bcm43xx_unlock(bcm, flags);
++      up(&big_buffer_sem);
++      return res;
++}
++
++#undef fappend
++
++
++static struct file_operations devinfo_fops = {
++      .read = devinfo_read_file,
++      .write = write_file_dummy,
++      .open = open_file_generic,
++};
++
++static struct file_operations spromdump_fops = {
++      .read = spromdump_read_file,
++      .write = write_file_dummy,
++      .open = open_file_generic,
++};
++
++static struct file_operations drvinfo_fops = {
++      .read = drvinfo_read_file,
++      .write = write_file_dummy,
++      .open = open_file_generic,
++};
++
++static struct file_operations tsf_fops = {
++      .read = tsf_read_file,
++      .write = tsf_write_file,
++      .open = open_file_generic,
++};
++
++static struct file_operations txstat_fops = {
++      .read = txstat_read_file,
++      .write = write_file_dummy,
++      .open = open_file_generic,
++};
++
++
++void bcm43xx_debugfs_add_device(struct bcm43xx_private *bcm)
++{
++      struct bcm43xx_dfsentry *e;
++      char devdir[IFNAMSIZ];
++
++      assert(bcm);
++      e = kzalloc(sizeof(*e), GFP_KERNEL);
++      if (!e) {
++              printk(KERN_ERR PFX "out of memory\n");
++              return;
++      }
++      e->bcm = bcm;
++      e->xmitstatus_buffer = kzalloc(BCM43xx_NR_LOGGED_XMITSTATUS
++                                     * sizeof(*(e->xmitstatus_buffer)),
++                                     GFP_KERNEL);
++      if (!e->xmitstatus_buffer) {
++              printk(KERN_ERR PFX "out of memory\n");
++              kfree(e);
++              return;
++      }
++      e->xmitstatus_print_buffer = kzalloc(BCM43xx_NR_LOGGED_XMITSTATUS
++                                           * sizeof(*(e->xmitstatus_buffer)),
++                                           GFP_KERNEL);
++      if (!e->xmitstatus_print_buffer) {
++              printk(KERN_ERR PFX "out of memory\n");
++              kfree(e);
++              return;
++      }
++
++
++      bcm->dfsentry = e;
++
++      strncpy(devdir, bcm->net_dev->name, ARRAY_SIZE(devdir));
++      e->subdir = debugfs_create_dir(devdir, fs.root);
++      e->dentry_devinfo = debugfs_create_file("devinfo", 0444, e->subdir,
++                                              bcm, &devinfo_fops);
++      if (!e->dentry_devinfo)
++              printk(KERN_ERR PFX "debugfs: creating \"devinfo\" for \"%s\" failed!\n", devdir);
++      e->dentry_spromdump = debugfs_create_file("sprom_dump", 0444, e->subdir,
++                                                bcm, &spromdump_fops);
++      if (!e->dentry_spromdump)
++              printk(KERN_ERR PFX "debugfs: creating \"sprom_dump\" for \"%s\" failed!\n", devdir);
++      e->dentry_tsf = debugfs_create_file("tsf", 0666, e->subdir,
++                                          bcm, &tsf_fops);
++      if (!e->dentry_tsf)
++              printk(KERN_ERR PFX "debugfs: creating \"tsf\" for \"%s\" failed!\n", devdir);
++      e->dentry_txstat = debugfs_create_file("tx_status", 0444, e->subdir,
++                                              bcm, &txstat_fops);
++      if (!e->dentry_txstat)
++              printk(KERN_ERR PFX "debugfs: creating \"tx_status\" for \"%s\" failed!\n", devdir);
++}
++
++void bcm43xx_debugfs_remove_device(struct bcm43xx_private *bcm)
++{
++      struct bcm43xx_dfsentry *e;
++
++      if (!bcm)
++              return;
++
++      e = bcm->dfsentry;
++      assert(e);
++      debugfs_remove(e->dentry_spromdump);
++      debugfs_remove(e->dentry_devinfo);
++      debugfs_remove(e->dentry_tsf);
++      debugfs_remove(e->dentry_txstat);
++      debugfs_remove(e->subdir);
++      kfree(e->xmitstatus_buffer);
++      kfree(e->xmitstatus_print_buffer);
++      kfree(e);
++}
++
++void bcm43xx_debugfs_log_txstat(struct bcm43xx_private *bcm,
++                              struct bcm43xx_xmitstatus *status)
++{
++      struct bcm43xx_dfsentry *e;
++      struct bcm43xx_xmitstatus *savedstatus;
++
++      /* This is protected by bcm->_lock */
++      e = bcm->dfsentry;
++      assert(e);
++      savedstatus = e->xmitstatus_buffer + e->xmitstatus_ptr;
++      memcpy(savedstatus, status, sizeof(*status));
++      e->xmitstatus_ptr++;
++      if (e->xmitstatus_ptr >= BCM43xx_NR_LOGGED_XMITSTATUS)
++              e->xmitstatus_ptr = 0;
++      if (e->xmitstatus_cnt < BCM43xx_NR_LOGGED_XMITSTATUS)
++              e->xmitstatus_cnt++;
++}
++
++void bcm43xx_debugfs_init(void)
++{
++      memset(&fs, 0, sizeof(fs));
++      fs.root = debugfs_create_dir(KBUILD_MODNAME, NULL);
++      if (!fs.root)
++              printk(KERN_ERR PFX "debugfs: creating \"" KBUILD_MODNAME "\" subdir failed!\n");
++      fs.dentry_driverinfo = debugfs_create_file("driver", 0444, fs.root, NULL, &drvinfo_fops);
++      if (!fs.dentry_driverinfo)
++              printk(KERN_ERR PFX "debugfs: creating \"" KBUILD_MODNAME "/driver\" failed!\n");
++}
++
++void bcm43xx_debugfs_exit(void)
++{
++      debugfs_remove(fs.dentry_driverinfo);
++      debugfs_remove(fs.root);
++}
++
++void bcm43xx_printk_dump(const char *data,
++                       size_t size,
++                       const char *description)
++{
++      size_t i;
++      char c;
++
++      printk(KERN_INFO PFX "Data dump (%s, %u bytes):",
++             description, size);
++      for (i = 0; i < size; i++) {
++              c = data[i];
++              if (i % 8 == 0)
++                      printk("\n" KERN_INFO PFX "0x%08x:  0x%02x, ", i, c & 0xff);
++              else
++                      printk("0x%02x, ", c & 0xff);
++      }
++      printk("\n");
++}
++
++void bcm43xx_printk_bitdump(const unsigned char *data,
++                          size_t bytes, int msb_to_lsb,
++                          const char *description)
++{
++      size_t i;
++      int j;
++      const unsigned char *d;
++
++      printk(KERN_INFO PFX "*** Bitdump (%s, %u bytes, %s) ***",
++             description, bytes, msb_to_lsb ? "MSB to LSB" : "LSB to MSB");
++      for (i = 0; i < bytes; i++) {
++              d = data + i;
++              if (i % 8 == 0)
++                      printk("\n" KERN_INFO PFX "0x%08x:  ", i);
++              if (msb_to_lsb) {
++                      for (j = 7; j >= 0; j--) {
++                              if (*d & (1 << j))
++                                      printk("1");
++                              else
++                                      printk("0");
++                      }
++              } else {
++                      for (j = 0; j < 8; j++) {
++                              if (*d & (1 << j))
++                                      printk("1");
++                              else
++                                      printk("0");
++                      }
++              }
++              printk(" ");
++      }
++      printk("\n");
++}
+diff -Nur linux-2.6.16/drivers/net/wireless/bcm43xx-d80211/bcm43xx_debugfs.h linux-2.6.16-bcm43xx/drivers/net/wireless/bcm43xx-d80211/bcm43xx_debugfs.h
+--- linux-2.6.16/drivers/net/wireless/bcm43xx-d80211/bcm43xx_debugfs.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.16-bcm43xx/drivers/net/wireless/bcm43xx-d80211/bcm43xx_debugfs.h 2006-03-28 22:16:14.000000000 +0200
+@@ -0,0 +1,117 @@
++#ifndef BCM43xx_DEBUGFS_H_
++#define BCM43xx_DEBUGFS_H_
++
++struct bcm43xx_private;
++struct bcm43xx_xmitstatus;
++
++#ifdef CONFIG_BCM43XX_D80211_DEBUG
++
++#include <linux/list.h>
++#include <asm/semaphore.h>
++
++struct dentry;
++
++/* limited by the size of the "really_big_buffer" */
++#define BCM43xx_NR_LOGGED_XMITSTATUS  100
++
++struct bcm43xx_dfsentry {
++      struct dentry *subdir;
++      struct dentry *dentry_devinfo;
++      struct dentry *dentry_spromdump;
++      struct dentry *dentry_tsf;
++      struct dentry *dentry_txstat;
++
++      struct bcm43xx_private *bcm;
++
++      /* saved xmitstatus. */
++      struct bcm43xx_xmitstatus *xmitstatus_buffer;
++      int xmitstatus_ptr;
++      int xmitstatus_cnt;
++      /* We need a seperate buffer while printing to avoid
++       * concurrency issues. (New xmitstatus can arrive
++       * while we are printing).
++       */
++      struct bcm43xx_xmitstatus *xmitstatus_print_buffer;
++      int saved_xmitstatus_ptr;
++      int saved_xmitstatus_cnt;
++      int xmitstatus_printing;
++};
++
++struct bcm43xx_debugfs {
++      struct dentry *root;
++      struct dentry *dentry_driverinfo;
++};
++
++void bcm43xx_debugfs_init(void);
++void bcm43xx_debugfs_exit(void);
++void bcm43xx_debugfs_add_device(struct bcm43xx_private *bcm);
++void bcm43xx_debugfs_remove_device(struct bcm43xx_private *bcm);
++void bcm43xx_debugfs_log_txstat(struct bcm43xx_private *bcm,
++                              struct bcm43xx_xmitstatus *status);
++
++/* Debug helper: Dump binary data through printk. */
++void bcm43xx_printk_dump(const char *data,
++                       size_t size,
++                       const char *description);
++/* Debug helper: Dump bitwise binary data through printk. */
++void bcm43xx_printk_bitdump(const unsigned char *data,
++                          size_t bytes, int msb_to_lsb,
++                          const char *description);
++#define bcm43xx_printk_bitdumpt(pointer, msb_to_lsb, description) \
++      do {                                                                    \
++              bcm43xx_printk_bitdump((const unsigned char *)(pointer),        \
++                                     sizeof(*(pointer)),                      \
++                                     (msb_to_lsb),                            \
++                                     (description));                          \
++      } while (0)
++
++#else /* CONFIG_BCM43XX_D80211_DEBUG*/
++
++static inline
++void bcm43xx_debugfs_init(void) { }
++static inline
++void bcm43xx_debugfs_exit(void) { }
++static inline
++void bcm43xx_debugfs_add_device(struct bcm43xx_private *bcm) { }
++static inline
++void bcm43xx_debugfs_remove_device(struct bcm43xx_private *bcm) { }
++static inline
++void bcm43xx_debugfs_log_txstat(struct bcm43xx_private *bcm,
++                              struct bcm43xx_xmitstatus *status) { }
++
++static inline
++void bcm43xx_printk_dump(const char *data,
++                       size_t size,
++                       const char *description)
++{
++}
++static inline
++void bcm43xx_printk_bitdump(const unsigned char *data,
++                          size_t bytes, int msb_to_lsb,
++                          const char *description)
++{
++}
++#define bcm43xx_printk_bitdumpt(pointer, msb_to_lsb, description)  do { /* nothing */ } while (0)
++
++#endif /* CONFIG_BCM43XX_D80211_DEBUG*/
++
++/* Ugly helper macros to make incomplete code more verbose on runtime */
++#ifdef TODO
++# undef TODO
++#endif
++#define TODO()  \
++      do {                                                                            \
++              printk(KERN_INFO PFX "TODO: Incomplete code in %s() at %s:%d\n",        \
++                     __FUNCTION__, __FILE__, __LINE__);                               \
++      } while (0)
++
++#ifdef FIXME
++# undef FIXME
++#endif
++#define FIXME()  \
++      do {                                                                            \
++              printk(KERN_INFO PFX "FIXME: Possibly broken code in %s() at %s:%d\n",  \
++                     __FUNCTION__, __FILE__, __LINE__);                               \
++      } while (0)
++
++#endif /* BCM43xx_DEBUGFS_H_ */
+diff -Nur linux-2.6.16/drivers/net/wireless/bcm43xx-d80211/bcm43xx_dma.c linux-2.6.16-bcm43xx/drivers/net/wireless/bcm43xx-d80211/bcm43xx_dma.c
+--- linux-2.6.16/drivers/net/wireless/bcm43xx-d80211/bcm43xx_dma.c     1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.16-bcm43xx/drivers/net/wireless/bcm43xx-d80211/bcm43xx_dma.c     2006-03-28 22:16:14.000000000 +0200
+@@ -0,0 +1,991 @@
++/*
++
++  Broadcom BCM43xx wireless driver
++
++  DMA ringbuffer and descriptor allocation/management
++
++  Copyright (c) 2005 Michael Buesch <mbuesch@freenet.de>
++
++  Some code in this file is derived from the b44.c driver
++  Copyright (C) 2002 David S. Miller
++  Copyright (C) Pekka Pietikainen
++
++  This program is free software; you can redistribute it and/or modify
++  it under the terms of the GNU General Public License as published by
++  the Free Software Foundation; either version 2 of the License, or
++  (at your option) any later version.
++
++  This program is distributed in the hope that it will be useful,
++  but WITHOUT ANY WARRANTY; without even the implied warranty of
++  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++  GNU General Public License for more details.
++
++  You should have received a copy of the GNU General Public License
++  along with this program; see the file COPYING.  If not, write to
++  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
++  Boston, MA 02110-1301, USA.
++
++*/
++
++#include "bcm43xx.h"
++#include "bcm43xx_dma.h"
++#include "bcm43xx_main.h"
++#include "bcm43xx_debugfs.h"
++#include "bcm43xx_power.h"
++#include "bcm43xx_xmit.h"
++
++#include <linux/dma-mapping.h>
++#include <linux/pci.h>
++#include <linux/delay.h>
++#include <linux/skbuff.h>
++
++
++static inline int free_slots(struct bcm43xx_dmaring *ring)
++{
++      return (ring->nr_slots - ring->used_slots);
++}
++
++static inline int next_slot(struct bcm43xx_dmaring *ring, int slot)
++{
++      assert(slot >= -1 && slot <= ring->nr_slots - 1);
++      if (slot == ring->nr_slots - 1)
++              return 0;
++      return slot + 1;
++}
++
++static inline int prev_slot(struct bcm43xx_dmaring *ring, int slot)
++{
++      assert(slot >= 0 && slot <= ring->nr_slots - 1);
++      if (slot == 0)
++              return ring->nr_slots - 1;
++      return slot - 1;
++}
++
++/* Request a slot for usage. */
++static inline
++int request_slot(struct bcm43xx_dmaring *ring)
++{
++      int slot;
++
++      assert(ring->tx);
++      assert(!ring->suspended);
++      assert(free_slots(ring) != 0);
++
++      slot = next_slot(ring, ring->current_slot);
++      ring->current_slot = slot;
++      ring->used_slots++;
++
++#ifdef CONFIG_BCM43XX_D80211_DEBUG
++      if (ring->used_slots > ring->max_used_slots)
++              ring->max_used_slots = ring->used_slots;
++#endif /* CONFIG_BCM43XX_D80211_DEBUG*/
++
++      return slot;
++}
++
++/* Return a slot to the free slots. */
++static inline
++void return_slot(struct bcm43xx_dmaring *ring, int slot)
++{
++      assert(ring->tx);
++
++      ring->used_slots--;
++}
++
++static inline
++dma_addr_t map_descbuffer(struct bcm43xx_dmaring *ring,
++                        unsigned char *buf,
++                        size_t len,
++                        int tx)
++{
++      dma_addr_t dmaaddr;
++
++      if (tx) {
++              dmaaddr = dma_map_single(&ring->bcm->pci_dev->dev,
++                                       buf, len,
++                                       DMA_TO_DEVICE);
++      } else {
++              dmaaddr = dma_map_single(&ring->bcm->pci_dev->dev,
++                                       buf, len,
++                                       DMA_FROM_DEVICE);
++      }
++
++      return dmaaddr;
++}
++
++static inline
++void unmap_descbuffer(struct bcm43xx_dmaring *ring,
++                    dma_addr_t addr,
++                    size_t len,
++                    int tx)
++{
++      if (tx) {
++              dma_unmap_single(&ring->bcm->pci_dev->dev,
++                               addr, len,
++                               DMA_TO_DEVICE);
++      } else {
++              dma_unmap_single(&ring->bcm->pci_dev->dev,
++                               addr, len,
++                               DMA_FROM_DEVICE);
++      }
++}
++
++static inline
++void sync_descbuffer_for_cpu(struct bcm43xx_dmaring *ring,
++                           dma_addr_t addr,
++                           size_t len)
++{
++      assert(!ring->tx);
++
++      dma_sync_single_for_cpu(&ring->bcm->pci_dev->dev,
++                              addr, len, DMA_FROM_DEVICE);
++}
++
++static inline
++void sync_descbuffer_for_device(struct bcm43xx_dmaring *ring,
++                              dma_addr_t addr,
++                              size_t len)
++{
++      assert(!ring->tx);
++
++      dma_sync_single_for_device(&ring->bcm->pci_dev->dev,
++                                 addr, len, DMA_FROM_DEVICE);
++}
++
++/* Unmap and free a descriptor buffer. */
++static inline
++void free_descriptor_buffer(struct bcm43xx_dmaring *ring,
++                          struct bcm43xx_dmadesc *desc,
++                          struct bcm43xx_dmadesc_meta *meta,
++                          int irq_context)
++{
++      assert(meta->skb);
++      if (irq_context)
++              dev_kfree_skb_irq(meta->skb);
++      else
++              dev_kfree_skb(meta->skb);
++      meta->skb = NULL;
++}
++
++static int alloc_ringmemory(struct bcm43xx_dmaring *ring)
++{
++      struct device *dev = &(ring->bcm->pci_dev->dev);
++
++      ring->vbase = dma_alloc_coherent(dev, BCM43xx_DMA_RINGMEMSIZE,
++                                       &(ring->dmabase), GFP_KERNEL);
++      if (!ring->vbase) {
++              printk(KERN_ERR PFX "DMA ringmemory allocation failed\n");
++              return -ENOMEM;
++      }
++      if (ring->dmabase + BCM43xx_DMA_RINGMEMSIZE > BCM43xx_DMA_BUSADDRMAX) {
++              printk(KERN_ERR PFX ">>>FATAL ERROR<<<  DMA RINGMEMORY >1G "
++                                  "(0x%08x, len: %lu)\n",
++                     ring->dmabase, BCM43xx_DMA_RINGMEMSIZE);
++              dma_free_coherent(dev, BCM43xx_DMA_RINGMEMSIZE,
++                                ring->vbase, ring->dmabase);
++              return -ENOMEM;
++      }
++      assert(!(ring->dmabase & 0x000003FF));
++      memset(ring->vbase, 0, BCM43xx_DMA_RINGMEMSIZE);
++
++      return 0;
++}
++
++static void free_ringmemory(struct bcm43xx_dmaring *ring)
++{
++      struct device *dev = &(ring->bcm->pci_dev->dev);
++
++      dma_free_coherent(dev, BCM43xx_DMA_RINGMEMSIZE,
++                        ring->vbase, ring->dmabase);
++}
++
++/* Reset the RX DMA channel */
++int bcm43xx_dmacontroller_rx_reset(struct bcm43xx_private *bcm,
++                                 u16 mmio_base)
++{
++      int i;
++      u32 value;
++
++      bcm43xx_write32(bcm,
++                      mmio_base + BCM43xx_DMA_RX_CONTROL,
++                      0x00000000);
++      for (i = 0; i < 1000; i++) {
++              value = bcm43xx_read32(bcm,
++                                     mmio_base + BCM43xx_DMA_RX_STATUS);
++              value &= BCM43xx_DMA_RXSTAT_STAT_MASK;
++              if (value == BCM43xx_DMA_RXSTAT_STAT_DISABLED) {
++                      i = -1;
++                      break;
++              }
++              udelay(10);
++      }
++      if (i != -1) {
++              printk(KERN_ERR PFX "Error: Wait on DMA RX status timed out.\n");
++              return -ENODEV;
++      }
++
++      return 0;
++}
++
++/* Reset the RX DMA channel */
++int bcm43xx_dmacontroller_tx_reset(struct bcm43xx_private *bcm,
++                                 u16 mmio_base)
++{
++      int i;
++      u32 value;
++
++      for (i = 0; i < 1000; i++) {
++              value = bcm43xx_read32(bcm,
++                                     mmio_base + BCM43xx_DMA_TX_STATUS);
++              value &= BCM43xx_DMA_TXSTAT_STAT_MASK;
++              if (value == BCM43xx_DMA_TXSTAT_STAT_DISABLED ||
++                  value == BCM43xx_DMA_TXSTAT_STAT_IDLEWAIT ||
++                  value == BCM43xx_DMA_TXSTAT_STAT_STOPPED)
++                      break;
++              udelay(10);
++      }
++      bcm43xx_write32(bcm,
++                      mmio_base + BCM43xx_DMA_TX_CONTROL,
++                      0x00000000);
++      for (i = 0; i < 1000; i++) {
++              value = bcm43xx_read32(bcm,
++                                     mmio_base + BCM43xx_DMA_TX_STATUS);
++              value &= BCM43xx_DMA_TXSTAT_STAT_MASK;
++              if (value == BCM43xx_DMA_TXSTAT_STAT_DISABLED) {
++                      i = -1;
++                      break;
++              }
++              udelay(10);
++      }
++      if (i != -1) {
++              printk(KERN_ERR PFX "Error: Wait on DMA TX status timed out.\n");
++              return -ENODEV;
++      }
++      /* ensure the reset is completed. */
++      udelay(300);
++
++      return 0;
++}
++
++static int setup_rx_descbuffer(struct bcm43xx_dmaring *ring,
++                             struct bcm43xx_dmadesc *desc,
++                             struct bcm43xx_dmadesc_meta *meta,
++                             gfp_t gfp_flags)
++{
++      struct bcm43xx_rxhdr *rxhdr;
++      dma_addr_t dmaaddr;
++      u32 desc_addr;
++      u32 desc_ctl;
++      const int slot = (int)(desc - ring->vbase);
++      struct sk_buff *skb;
++
++      assert(slot >= 0 && slot < ring->nr_slots);
++      assert(!ring->tx);
++
++      skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
++      if (unlikely(!skb))
++              return -ENOMEM;
++      dmaaddr = map_descbuffer(ring, skb->data,
++                               ring->rx_buffersize, 0);
++      if (unlikely(dmaaddr + ring->rx_buffersize > BCM43xx_DMA_BUSADDRMAX)) {
++              unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
++              dev_kfree_skb_any(skb);
++              printk(KERN_ERR PFX ">>>FATAL ERROR<<<  DMA RX SKB >1G "
++                                  "(0x%08x, len: %u)\n",
++                     dmaaddr, ring->rx_buffersize);
++              return -ENOMEM;
++      }
++      meta->skb = skb;
++      meta->dmaaddr = dmaaddr;
++      skb->dev = ring->bcm->net_dev;
++      desc_addr = (u32)(dmaaddr + ring->memoffset);
++      desc_ctl = (BCM43xx_DMADTOR_BYTECNT_MASK &
++                  (u32)(ring->rx_buffersize - ring->frameoffset));
++      if (slot == ring->nr_slots - 1)
++              desc_ctl |= BCM43xx_DMADTOR_DTABLEEND;
++      set_desc_addr(desc, desc_addr);
++      set_desc_ctl(desc, desc_ctl);
++
++      rxhdr = (struct bcm43xx_rxhdr *)(skb->data);
++      rxhdr->frame_length = 0;
++      rxhdr->flags1 = 0;
++
++      return 0;
++}
++
++/* Allocate the initial descbuffers.
++ * This is used for an RX ring only.
++ */
++static int alloc_initial_descbuffers(struct bcm43xx_dmaring *ring)
++{
++      int i, err = -ENOMEM;
++      struct bcm43xx_dmadesc *desc;
++      struct bcm43xx_dmadesc_meta *meta;
++
++      for (i = 0; i < ring->nr_slots; i++) {
++              desc = ring->vbase + i;
++              meta = ring->meta + i;
++
++              err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
++              if (err)
++                      goto err_unwind;
++      }
++      ring->used_slots = ring->nr_slots;
++      err = 0;
++out:
++      return err;
++
++err_unwind:
++      for (i--; i >= 0; i--) {
++              desc = ring->vbase + i;
++              meta = ring->meta + i;
++
++              unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
++              dev_kfree_skb(meta->skb);
++      }
++      goto out;
++}
++
++/* Do initial setup of the DMA controller.
++ * Reset the controller, write the ring busaddress
++ * and switch the "enable" bit on.
++ */
++static int dmacontroller_setup(struct bcm43xx_dmaring *ring)
++{
++      int err = 0;
++      u32 value;
++
++      if (ring->tx) {
++              /* Set Transmit Control register to "transmit enable" */
++              bcm43xx_dma_write(ring, BCM43xx_DMA_TX_CONTROL,
++                                BCM43xx_DMA_TXCTRL_ENABLE);
++              /* Set Transmit Descriptor ring address. */
++              bcm43xx_dma_write(ring, BCM43xx_DMA_TX_DESC_RING,
++                                ring->dmabase + ring->memoffset);
++      } else {
++              err = alloc_initial_descbuffers(ring);
++              if (err)
++                      goto out;
++              /* Set Receive Control "receive enable" and frame offset */
++              value = (ring->frameoffset << BCM43xx_DMA_RXCTRL_FRAMEOFF_SHIFT);
++              value |= BCM43xx_DMA_RXCTRL_ENABLE;
++              bcm43xx_dma_write(ring, BCM43xx_DMA_RX_CONTROL, value);
++              /* Set Receive Descriptor ring address. */
++              bcm43xx_dma_write(ring, BCM43xx_DMA_RX_DESC_RING,
++                                ring->dmabase + ring->memoffset);
++              /* Init the descriptor pointer. */
++              bcm43xx_dma_write(ring, BCM43xx_DMA_RX_DESC_INDEX, 200);
++      }
++
++out:
++      return err;
++}
++
++/* Shutdown the DMA controller. */
++static void dmacontroller_cleanup(struct bcm43xx_dmaring *ring)
++{
++      if (ring->tx) {
++              bcm43xx_dmacontroller_tx_reset(ring->bcm, ring->mmio_base);
++              /* Zero out Transmit Descriptor ring address. */
++              bcm43xx_dma_write(ring, BCM43xx_DMA_TX_DESC_RING, 0);
++      } else {
++              bcm43xx_dmacontroller_rx_reset(ring->bcm, ring->mmio_base);
++              /* Zero out Receive Descriptor ring address. */
++              bcm43xx_dma_write(ring, BCM43xx_DMA_RX_DESC_RING, 0);
++      }
++}
++
++static void free_all_descbuffers(struct bcm43xx_dmaring *ring)
++{
++      struct bcm43xx_dmadesc *desc;
++      struct bcm43xx_dmadesc_meta *meta;
++      int i;
++
++      if (!ring->used_slots)
++              return;
++      for (i = 0; i < ring->nr_slots; i++) {
++              desc = ring->vbase + i;
++              meta = ring->meta + i;
++
++              if (!meta->skb) {
++                      assert(ring->tx);
++                      continue;
++              }
++              if (ring->tx) {
++                      unmap_descbuffer(ring, meta->dmaaddr,
++                                       meta->skb->len, 1);
++              } else {
++                      unmap_descbuffer(ring, meta->dmaaddr,
++                                       ring->rx_buffersize, 0);
++              }
++              free_descriptor_buffer(ring, desc, meta, 0);
++      }
++}
++
++/* Main initialization function. */
++static
++struct bcm43xx_dmaring * bcm43xx_setup_dmaring(struct bcm43xx_private *bcm,
++                                             u16 dma_controller_base,
++                                             int nr_descriptor_slots,
++                                             int tx)
++{
++      struct bcm43xx_dmaring *ring;
++      int err;
++
++      ring = kzalloc(sizeof(*ring), GFP_KERNEL);
++      if (!ring)
++              goto out;
++
++      ring->meta = kzalloc(sizeof(*ring->meta) * nr_descriptor_slots,
++                           GFP_KERNEL);
++      if (!ring->meta)
++              goto err_kfree_ring;
++
++      ring->memoffset = BCM43xx_DMA_DMABUSADDROFFSET;
++#ifdef CONFIG_BCM947XX
++      if (bcm->pci_dev->bus->number == 0)
++              ring->memoffset = 0;
++#endif
++
++      ring->bcm = bcm;
++      ring->nr_slots = nr_descriptor_slots;
++      ring->mmio_base = dma_controller_base;
++      if (tx) {
++              ring->tx = 1;
++              ring->current_slot = -1;
++      } else {
++              switch (dma_controller_base) {
++              case BCM43xx_MMIO_DMA1_BASE:
++                      ring->rx_buffersize = BCM43xx_DMA1_RXBUFFERSIZE;
++                      ring->frameoffset = BCM43xx_DMA1_RX_FRAMEOFFSET;
++                      break;
++              case BCM43xx_MMIO_DMA4_BASE:
++                      ring->rx_buffersize = BCM43xx_DMA4_RXBUFFERSIZE;
++                      ring->frameoffset = BCM43xx_DMA4_RX_FRAMEOFFSET;
++                      break;
++              default:
++                      assert(0);
++              }
++      }
++
++      err = alloc_ringmemory(ring);
++      if (err)
++              goto err_kfree_meta;
++      err = dmacontroller_setup(ring);
++      if (err)
++              goto err_free_ringmemory;
++
++out:
++      return ring;
++
++err_free_ringmemory:
++      free_ringmemory(ring);
++err_kfree_meta:
++      kfree(ring->meta);
++err_kfree_ring:
++      kfree(ring);
++      ring = NULL;
++      goto out;
++}
++
++/* Main cleanup function. */
++static void bcm43xx_destroy_dmaring(struct bcm43xx_dmaring *ring)
++{
++      if (!ring)
++              return;
++
++      dprintk(KERN_INFO PFX "DMA 0x%04x (%s) max used slots: %d/%d\n",
++              ring->mmio_base,
++              (ring->tx) ? "TX" : "RX",
++              ring->max_used_slots, ring->nr_slots);
++      /* Device IRQs are disabled prior entering this function,
++       * so no need to take care of concurrency with rx handler stuff.
++       */
++      dmacontroller_cleanup(ring);
++      free_all_descbuffers(ring);
++      free_ringmemory(ring);
++
++      kfree(ring->meta);
++      kfree(ring);
++}
++
++void bcm43xx_dma_free(struct bcm43xx_private *bcm)
++{
++      struct bcm43xx_dma *dma;
++
++      if (bcm43xx_using_pio(bcm))
++              return;
++      dma = bcm43xx_current_dma(bcm);
++
++      bcm43xx_destroy_dmaring(dma->rx_ring1);
++      dma->rx_ring1 = NULL;
++      bcm43xx_destroy_dmaring(dma->rx_ring0);
++      dma->rx_ring0 = NULL;
++      bcm43xx_destroy_dmaring(dma->tx_ring3);
++      dma->tx_ring3 = NULL;
++      bcm43xx_destroy_dmaring(dma->tx_ring2);
++      dma->tx_ring2 = NULL;
++      bcm43xx_destroy_dmaring(dma->tx_ring1);
++      dma->tx_ring1 = NULL;
++      bcm43xx_destroy_dmaring(dma->tx_ring0);
++      dma->tx_ring0 = NULL;
++}
++
++int bcm43xx_dma_init(struct bcm43xx_private *bcm)
++{
++      struct bcm43xx_dma *dma = bcm43xx_current_dma(bcm);
++      struct bcm43xx_dmaring *ring;
++      int err = -ENOMEM;
++
++      /* setup TX DMA channels. */
++      ring = bcm43xx_setup_dmaring(bcm, BCM43xx_MMIO_DMA1_BASE,
++                                   BCM43xx_TXRING_SLOTS, 1);
++      if (!ring)
++              goto out;
++      dma->tx_ring0 = ring;
++
++      ring = bcm43xx_setup_dmaring(bcm, BCM43xx_MMIO_DMA2_BASE,
++                                   BCM43xx_TXRING_SLOTS, 1);
++      if (!ring)
++              goto err_destroy_tx0;
++      dma->tx_ring1 = ring;
++
++      ring = bcm43xx_setup_dmaring(bcm, BCM43xx_MMIO_DMA3_BASE,
++                                   BCM43xx_TXRING_SLOTS, 1);
++      if (!ring)
++              goto err_destroy_tx1;
++      dma->tx_ring2 = ring;
++
++      ring = bcm43xx_setup_dmaring(bcm, BCM43xx_MMIO_DMA4_BASE,
++                                   BCM43xx_TXRING_SLOTS, 1);
++      if (!ring)
++              goto err_destroy_tx2;
++      dma->tx_ring3 = ring;
++
++      /* setup RX DMA channels. */
++      ring = bcm43xx_setup_dmaring(bcm, BCM43xx_MMIO_DMA1_BASE,
++                                   BCM43xx_RXRING_SLOTS, 0);
++      if (!ring)
++              goto err_destroy_tx3;
++      dma->rx_ring0 = ring;
++
++      if (bcm->current_core->rev < 5) {
++              ring = bcm43xx_setup_dmaring(bcm, BCM43xx_MMIO_DMA4_BASE,
++                                           BCM43xx_RXRING_SLOTS, 0);
++              if (!ring)
++                      goto err_destroy_rx0;
++              dma->rx_ring1 = ring;
++      }
++
++      dprintk(KERN_INFO PFX "DMA initialized\n");
++      err = 0;
++out:
++      return err;
++
++err_destroy_rx0:
++      bcm43xx_destroy_dmaring(dma->rx_ring0);
++      dma->rx_ring0 = NULL;
++err_destroy_tx3:
++      bcm43xx_destroy_dmaring(dma->tx_ring3);
++      dma->tx_ring3 = NULL;
++err_destroy_tx2:
++      bcm43xx_destroy_dmaring(dma->tx_ring2);
++      dma->tx_ring2 = NULL;
++err_destroy_tx1:
++      bcm43xx_destroy_dmaring(dma->tx_ring1);
++      dma->tx_ring1 = NULL;
++err_destroy_tx0:
++      bcm43xx_destroy_dmaring(dma->tx_ring0);
++      dma->tx_ring0 = NULL;
++      goto out;
++}
++
++/* Generate a cookie for the TX header. */
++static u16 generate_cookie(struct bcm43xx_dmaring *ring,
++                         int slot)
++{
++      u16 cookie = 0x0000;
++
++      /* Use the upper 4 bits of the cookie as
++       * DMA controller ID and store the slot number
++       * in the lower 12 bits
++       */
++      switch (ring->mmio_base) {
++      default:
++              assert(0);
++      case BCM43xx_MMIO_DMA1_BASE:
++              break;
++      case BCM43xx_MMIO_DMA2_BASE:
++              cookie = 0x1000;
++              break;
++      case BCM43xx_MMIO_DMA3_BASE:
++              cookie = 0x2000;
++              break;
++      case BCM43xx_MMIO_DMA4_BASE:
++              cookie = 0x3000;
++              break;
++      }
++      assert(((u16)slot & 0xF000) == 0x0000);
++      cookie |= (u16)slot;
++
++      return cookie;
++}
++
++/* Inspect a cookie and find out to which controller/slot it belongs. */
++static
++struct bcm43xx_dmaring * parse_cookie(struct bcm43xx_private *bcm,
++                                    u16 cookie, int *slot)
++{
++      struct bcm43xx_dma *dma = bcm43xx_current_dma(bcm);
++      struct bcm43xx_dmaring *ring = NULL;
++
++      switch (cookie & 0xF000) {
++      case 0x0000:
++              ring = dma->tx_ring0;
++              break;
++      case 0x1000:
++              ring = dma->tx_ring1;
++              break;
++      case 0x2000:
++              ring = dma->tx_ring2;
++              break;
++      case 0x3000:
++              ring = dma->tx_ring3;
++              break;
++      default:
++              assert(0);
++      }
++      *slot = (cookie & 0x0FFF);
++      assert(*slot >= 0 && *slot < ring->nr_slots);
++
++      return ring;
++}
++
++static void dmacontroller_poke_tx(struct bcm43xx_dmaring *ring,
++                                int slot)
++{
++      /* Everything is ready to start. Buffers are DMA mapped and
++       * associated with slots.
++       * "slot" is the last slot of the new frame we want to transmit.
++       * Close your seat belts now, please.
++       */
++      wmb();
++      slot = next_slot(ring, slot);
++      bcm43xx_dma_write(ring, BCM43xx_DMA_TX_DESC_INDEX,
++                        (u32)(slot * sizeof(struct bcm43xx_dmadesc)));
++}
++
++static int dma_tx_fragment(struct bcm43xx_dmaring *ring,
++                         struct sk_buff *skb,
++                         struct ieee80211_tx_control *ctl)
++{
++      struct sk_buff *hdr_skb;
++      int slot;
++      struct bcm43xx_dmadesc *desc;
++      struct bcm43xx_dmadesc_meta *meta;
++      u32 desc_ctl;
++      u32 desc_addr;
++
++      assert(skb_shinfo(skb)->nr_frags == 0);
++
++      hdr_skb = dev_alloc_skb(sizeof(struct bcm43xx_txhdr));
++      if (unlikely(!hdr_skb))
++              return -ENOMEM;
++      skb_put(hdr_skb, sizeof(struct bcm43xx_txhdr));
++
++      slot = request_slot(ring);
++      desc = ring->vbase + slot;
++      meta = ring->meta + slot;
++
++      bcm43xx_generate_txhdr(ring->bcm,
++                             (struct bcm43xx_txhdr *)hdr_skb->data,
++                             skb->data, skb->len,
++                             1,//FIXME
++                             generate_cookie(ring, slot),
++                             ctl);
++
++      meta->skb = hdr_skb;
++      meta->dmaaddr = map_descbuffer(ring, hdr_skb->data, hdr_skb->len, 1);
++      if (unlikely(meta->dmaaddr + hdr_skb->len > BCM43xx_DMA_BUSADDRMAX)) {
++              return_slot(ring, slot);
++              dev_kfree_skb_irq(hdr_skb);
++              printk(KERN_ERR PFX ">>>FATAL ERROR<<<  DMA TX SKB >1G "
++                                  "(0x%08x, len: %u)\n",
++                     meta->dmaaddr, hdr_skb->len);
++              return -ENOMEM;
++      }
++
++      desc_addr = (u32)(meta->dmaaddr + ring->memoffset);
++      desc_ctl = BCM43xx_DMADTOR_FRAMESTART |
++                 (BCM43xx_DMADTOR_BYTECNT_MASK & (u32)(hdr_skb->len));
++      if (slot == ring->nr_slots - 1)
++              desc_ctl |= BCM43xx_DMADTOR_DTABLEEND;
++      set_desc_ctl(desc, desc_ctl);
++      set_desc_addr(desc, desc_addr);
++
++      slot = request_slot(ring);
++      desc = ring->vbase + slot;
++      meta = ring->meta + slot;
++
++      /* We inspect the txstatus on the FRAMESTART descriptor later
++       * on xmit-status IRQ.
++       */
++      meta->must_xmit_txstat = 1;
++      memset(&meta->txstat, 0, sizeof(meta->txstat));
++      memcpy(&meta->txstat.control, ctl, sizeof(*ctl));
++
++      meta->skb = skb;
++      meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
++      if (unlikely(meta->dmaaddr + skb->len > BCM43xx_DMA_BUSADDRMAX)) {
++              return_slot(ring, prev_slot(ring, slot));
++              return_slot(ring, slot);
++              dev_kfree_skb_irq(hdr_skb);
++              printk(KERN_ERR PFX ">>>FATAL ERROR<<<  DMA TX SKB >1G "
++                                  "(0x%08x, len: %u)\n",
++                     meta->dmaaddr, skb->len);
++              return -ENOMEM;
++      }
++
++      desc_addr = (u32)(meta->dmaaddr + ring->memoffset);
++      desc_ctl = (BCM43xx_DMADTOR_BYTECNT_MASK & (u32)(skb->len));
++      if (slot == ring->nr_slots - 1)
++              desc_ctl |= BCM43xx_DMADTOR_DTABLEEND;
++
++      desc_ctl |= BCM43xx_DMADTOR_FRAMEEND | BCM43xx_DMADTOR_COMPIRQ;
++      set_desc_ctl(desc, desc_ctl);
++      set_desc_addr(desc, desc_addr);
++      /* Now transfer the whole frame. */
++      dmacontroller_poke_tx(ring, slot);
++
++      return 0;
++}
++
++int bcm43xx_dma_tx(struct bcm43xx_private *bcm,
++                 struct sk_buff *skb,
++                 struct ieee80211_tx_control *ctl)
++{
++      struct bcm43xx_dmaring *ring = bcm43xx_current_dma(bcm)->tx_ring1;
++      int err;
++
++      assert(ring->tx);
++
++#define SLOTS_PER_PACKET  2
++      if (unlikely(free_slots(ring) < SLOTS_PER_PACKET)) {
++              /* This should never trigger, as the ieee80211 stack
++               * recognizes if the device queue is full and does
++               * not send data anymore.
++               */
++              printk(KERN_ERR PFX "DMA queue overflow\n");
++              return -ENOMEM;
++      }
++
++      err = dma_tx_fragment(ring, skb, ctl);
++      if (likely(!err))
++              ring->nr_tx_packets++;
++
++      return err;
++}
++
++void bcm43xx_dma_handle_xmitstatus(struct bcm43xx_private *bcm,
++                                 struct bcm43xx_xmitstatus *status)
++{
++      struct bcm43xx_dmaring *ring;
++      struct bcm43xx_dmadesc *desc;
++      struct bcm43xx_dmadesc_meta *meta;
++      int is_last_fragment;
++      int slot;
++
++      ring = parse_cookie(bcm, status->cookie, &slot);
++      assert(ring);
++      assert(ring->tx);
++      assert(get_desc_ctl(ring->vbase + slot) & BCM43xx_DMADTOR_FRAMESTART);
++      while (1) {
++              assert(slot >= 0 && slot < ring->nr_slots);
++              desc = ring->vbase + slot;
++              meta = ring->meta + slot;
++
++              is_last_fragment = !!(get_desc_ctl(desc) & BCM43xx_DMADTOR_FRAMEEND);
++              unmap_descbuffer(ring, meta->dmaaddr, meta->skb->len, 1);
++
++              if (meta->must_xmit_txstat) {
++                      meta->must_xmit_txstat = 0;
++                      /* Call back to inform the ieee80211 subsystem about the
++                       * status of the transmission.
++                       * Some fields of txstat are already filled in dma_tx().
++                       */
++                      meta->txstat.ack = !!(status->flags & BCM43xx_TXSTAT_FLAG_ACK);
++                      meta->txstat.retry_count = status->cnt2 - 1;
++                      //FIXME: Fill in more information?
++                      ieee80211_tx_status_irqsafe(bcm->net_dev, meta->skb, &(meta->txstat));
++                      meta->skb = NULL;
++              } else
++                      free_descriptor_buffer(ring, desc, meta, 1);
++              /* Everything belonging to the slot is unmapped
++               * and freed, so we can return it.
++               */
++              return_slot(ring, slot);
++
++              if (is_last_fragment)
++                      break;
++              slot = next_slot(ring, slot);
++      }
++      bcm->stats.last_tx = jiffies;
++}
++
++void bcm43xx_dma_get_tx_stats(struct bcm43xx_private *bcm,
++                            struct ieee80211_tx_queue_stats *stats)
++{
++      struct bcm43xx_dma *dma = bcm43xx_current_dma(bcm);
++      struct bcm43xx_dmaring *ring;
++      struct ieee80211_tx_queue_stats_data *data;
++
++      ring = dma->tx_ring1;
++      data = &(stats->data[0]);
++      data->len = ring->used_slots / SLOTS_PER_PACKET;
++      data->limit = ring->nr_slots / SLOTS_PER_PACKET;
++      data->count = ring->nr_tx_packets;
++}
++
++static void dma_rx(struct bcm43xx_dmaring *ring,
++                 int *slot)
++{
++      struct bcm43xx_dmadesc *desc;
++      struct bcm43xx_dmadesc_meta *meta;
++      struct bcm43xx_rxhdr *rxhdr;
++      struct sk_buff *skb;
++      u16 len;
++      int err;
++      dma_addr_t dmaaddr;
++
++      desc = ring->vbase + *slot;
++      meta = ring->meta + *slot;
++
++      sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize);
++      skb = meta->skb;
++
++      if (ring->mmio_base == BCM43xx_MMIO_DMA4_BASE) {
++              /* We received an xmit status. */
++              struct bcm43xx_hwxmitstatus *hw = (struct bcm43xx_hwxmitstatus *)skb->data;
++              struct bcm43xx_xmitstatus stat;
++
++              stat.cookie = le16_to_cpu(hw->cookie);
++              stat.flags = hw->flags;
++              stat.cnt1 = hw->cnt1;
++              stat.cnt2 = hw->cnt2;
++              stat.seq = le16_to_cpu(hw->seq);
++              stat.unknown = le16_to_cpu(hw->unknown);
++
++              bcm43xx_debugfs_log_txstat(ring->bcm, &stat);
++              bcm43xx_dma_handle_xmitstatus(ring->bcm, &stat);
++              /* recycle the descriptor buffer. */
++              sync_descbuffer_for_device(ring, meta->dmaaddr, ring->rx_buffersize);
++
++              return;
++      }
++      rxhdr = (struct bcm43xx_rxhdr *)skb->data;
++      len = le16_to_cpu(rxhdr->frame_length);
++      if (len == 0) {
++              int i = 0;
++
++              do {
++                      udelay(2);
++                      barrier();
++                      len = le16_to_cpu(rxhdr->frame_length);
++              } while (len == 0 && i++ < 5);
++              if (unlikely(len == 0)) {
++                      /* recycle the descriptor buffer. */
++                      sync_descbuffer_for_device(ring, meta->dmaaddr,
++                                                 ring->rx_buffersize);
++                      goto drop;
++              }
++      }
++      if (unlikely(len > ring->rx_buffersize)) {
++              /* The data did not fit into one descriptor buffer
++               * and is split over multiple buffers.
++               * This should never happen, as we try to allocate buffers
++               * big enough. So simply ignore this packet.
++               */
++              int cnt = 0;
++              s32 tmp = len;
++
++              while (1) {
++                      desc = ring->vbase + *slot;
++                      meta = ring->meta + *slot;
++                      /* recycle the descriptor buffer. */
++                      sync_descbuffer_for_device(ring, meta->dmaaddr,
++                                                 ring->rx_buffersize);
++                      *slot = next_slot(ring, *slot);
++                      cnt++;
++                      tmp -= ring->rx_buffersize;
++                      if (tmp <= 0)
++                              break;
++              }
++              printkl(KERN_ERR PFX "DMA RX buffer too small "
++                                   "(len: %u, buffer: %u, nr-dropped: %d)\n",
++                      len, ring->rx_buffersize, cnt);
++              goto drop;
++      }
++
++      dmaaddr = meta->dmaaddr;
++      err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
++      if (unlikely(err)) {
++              dprintkl(KERN_ERR PFX "DMA RX: setup_rx_descbuffer() failed\n");
++              sync_descbuffer_for_device(ring, dmaaddr,
++                                         ring->rx_buffersize);
++              goto drop;
++      }
++
++      unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
++      skb_put(skb, len + ring->frameoffset);
++      skb_pull(skb, ring->frameoffset);
++
++      bcm43xx_rx(ring->bcm, skb, rxhdr);
++drop:
++      return;
++}
++
++void bcm43xx_dma_rx(struct bcm43xx_dmaring *ring)
++{
++      u32 status;
++      u16 descptr;
++      int slot, current_slot;
++#ifdef CONFIG_BCM43XX_D80211_DEBUG
++      int used_slots = 0;
++#endif
++
++      assert(!ring->tx);
++      status = bcm43xx_dma_read(ring, BCM43xx_DMA_RX_STATUS);
++      descptr = (status & BCM43xx_DMA_RXSTAT_DPTR_MASK);
++      current_slot = descptr / sizeof(struct bcm43xx_dmadesc);
++      assert(current_slot >= 0 && current_slot < ring->nr_slots);
++
++      slot = ring->current_slot;
++      for ( ; slot != current_slot; slot = next_slot(ring, slot)) {
++              dma_rx(ring, &slot);
++#ifdef CONFIG_BCM43XX_D80211_DEBUG
++              if (++used_slots > ring->max_used_slots)
++                      ring->max_used_slots = used_slots;
++#endif
++      }
++      bcm43xx_dma_write(ring, BCM43xx_DMA_RX_DESC_INDEX,
++                        (u32)(slot * sizeof(struct bcm43xx_dmadesc)));
++      ring->current_slot = slot;
++}
++
++void bcm43xx_dma_tx_suspend(struct bcm43xx_dmaring *ring)
++{
++      assert(ring->tx);
++      bcm43xx_power_saving_ctl_bits(ring->bcm, -1, 1);
++      bcm43xx_dma_write(ring, BCM43xx_DMA_TX_CONTROL,
++                        bcm43xx_dma_read(ring, BCM43xx_DMA_TX_CONTROL)
++                        | BCM43xx_DMA_TXCTRL_SUSPEND);
++}
++
++void bcm43xx_dma_tx_resume(struct bcm43xx_dmaring *ring)
++{
++      assert(ring->tx);
++      bcm43xx_dma_write(ring, BCM43xx_DMA_TX_CONTROL,
++                        bcm43xx_dma_read(ring, BCM43xx_DMA_TX_CONTROL)
++                        & ~BCM43xx_DMA_TXCTRL_SUSPEND);
++      bcm43xx_power_saving_ctl_bits(ring->bcm, -1, -1);
++}
+diff -Nur linux-2.6.16/drivers/net/wireless/bcm43xx-d80211/bcm43xx_dma.h linux-2.6.16-bcm43xx/drivers/net/wireless/bcm43xx-d80211/bcm43xx_dma.h
+--- linux-2.6.16/drivers/net/wireless/bcm43xx-d80211/bcm43xx_dma.h     1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.16-bcm43xx/drivers/net/wireless/bcm43xx-d80211/bcm43xx_dma.h     2006-03-28 22:16:14.000000000 +0200
+@@ -0,0 +1,228 @@
++#ifndef BCM43xx_DMA_H_
++#define BCM43xx_DMA_H_
++
++#include <linux/list.h>
++#include <linux/spinlock.h>
++#include <linux/workqueue.h>
++#include <linux/linkage.h>
++#include <asm/atomic.h>
++
++#include "bcm43xx.h"
++
++
++/* DMA-Interrupt reasons. */
++#define BCM43xx_DMAIRQ_FATALMASK      ((1 << 10) | (1 << 11) | (1 << 12) \
++                                       | (1 << 14) | (1 << 15))
++#define BCM43xx_DMAIRQ_NONFATALMASK   (1 << 13)
++#define BCM43xx_DMAIRQ_RX_DONE                (1 << 16)
++
++/* DMA controller register offsets. (relative to BCM43xx_DMA#_BASE) */
++#define BCM43xx_DMA_TX_CONTROL                0x00
++#define BCM43xx_DMA_TX_DESC_RING      0x04
++#define BCM43xx_DMA_TX_DESC_INDEX     0x08
++#define BCM43xx_DMA_TX_STATUS         0x0c
++#define BCM43xx_DMA_RX_CONTROL                0x10
++#define BCM43xx_DMA_RX_DESC_RING      0x14
++#define BCM43xx_DMA_RX_DESC_INDEX     0x18
++#define BCM43xx_DMA_RX_STATUS         0x1c
++
++/* DMA controller channel control word values. */
++#define BCM43xx_DMA_TXCTRL_ENABLE             (1 << 0)
++#define BCM43xx_DMA_TXCTRL_SUSPEND            (1 << 1)
++#define BCM43xx_DMA_TXCTRL_LOOPBACK           (1 << 2)
++#define BCM43xx_DMA_TXCTRL_FLUSH              (1 << 4)
++#define BCM43xx_DMA_RXCTRL_ENABLE             (1 << 0)
++#define BCM43xx_DMA_RXCTRL_FRAMEOFF_MASK      0x000000fe
++#define BCM43xx_DMA_RXCTRL_FRAMEOFF_SHIFT     1
++#define BCM43xx_DMA_RXCTRL_PIO                        (1 << 8)
++/* DMA controller channel status word values. */
++#define BCM43xx_DMA_TXSTAT_DPTR_MASK          0x00000fff
++#define BCM43xx_DMA_TXSTAT_STAT_MASK          0x0000f000
++#define BCM43xx_DMA_TXSTAT_STAT_DISABLED      0x00000000
++#define BCM43xx_DMA_TXSTAT_STAT_ACTIVE                0x00001000
++#define BCM43xx_DMA_TXSTAT_STAT_IDLEWAIT      0x00002000
++#define BCM43xx_DMA_TXSTAT_STAT_STOPPED               0x00003000
++#define BCM43xx_DMA_TXSTAT_STAT_SUSP          0x00004000
++#define BCM43xx_DMA_TXSTAT_ERROR_MASK         0x000f0000
++#define BCM43xx_DMA_TXSTAT_FLUSHED            (1 << 20)
++#define BCM43xx_DMA_RXSTAT_DPTR_MASK          0x00000fff
++#define BCM43xx_DMA_RXSTAT_STAT_MASK          0x0000f000
++#define BCM43xx_DMA_RXSTAT_STAT_DISABLED      0x00000000
++#define BCM43xx_DMA_RXSTAT_STAT_ACTIVE                0x00001000
++#define BCM43xx_DMA_RXSTAT_STAT_IDLEWAIT      0x00002000
++#define BCM43xx_DMA_RXSTAT_STAT_RESERVED      0x00003000
++#define BCM43xx_DMA_RXSTAT_STAT_ERRORS                0x00004000
++#define BCM43xx_DMA_RXSTAT_ERROR_MASK         0x000f0000
++
++/* DMA descriptor control field values. */
++#define BCM43xx_DMADTOR_BYTECNT_MASK          0x00001fff
++#define BCM43xx_DMADTOR_DTABLEEND             (1 << 28) /* End of descriptor table */
++#define BCM43xx_DMADTOR_COMPIRQ                       (1 << 29) /* IRQ on completion request */
++#define BCM43xx_DMADTOR_FRAMEEND              (1 << 30)
++#define BCM43xx_DMADTOR_FRAMESTART            (1 << 31)
++
++/* Misc DMA constants */
++#define BCM43xx_DMA_RINGMEMSIZE               PAGE_SIZE
++#define BCM43xx_DMA_BUSADDRMAX                0x3FFFFFFF
++#define BCM43xx_DMA_DMABUSADDROFFSET  (1 << 30)
++#define BCM43xx_DMA1_RX_FRAMEOFFSET   30
++#define BCM43xx_DMA4_RX_FRAMEOFFSET   0
++
++/* DMA engine tuning knobs */
++#define BCM43xx_TXRING_SLOTS          512
++#define BCM43xx_RXRING_SLOTS          64
++#define BCM43xx_DMA1_RXBUFFERSIZE     (2304 + 100)
++#define BCM43xx_DMA4_RXBUFFERSIZE     16
++
++
++
++#ifdef CONFIG_BCM43XX_D80211_DMA
++
++
++struct sk_buff;
++struct bcm43xx_private;
++struct bcm43xx_xmitstatus;
++
++
++struct bcm43xx_dmadesc {
++      __le32 _control;
++      __le32 _address;
++} __attribute__((__packed__));
++
++/* Macros to access the bcm43xx_dmadesc struct */
++#define get_desc_ctl(desc)            le32_to_cpu((desc)->_control)
++#define set_desc_ctl(desc, ctl)               do { (desc)->_control = cpu_to_le32(ctl); } while (0)
++#define get_desc_addr(desc)           le32_to_cpu((desc)->_address)
++#define set_desc_addr(desc, addr)     do { (desc)->_address = cpu_to_le32(addr); } while (0)
++
++struct bcm43xx_dmadesc_meta {
++      /* The kernel DMA-able buffer. */
++      struct sk_buff *skb;
++      /* DMA base bus-address of the descriptor buffer. */
++      dma_addr_t dmaaddr;
++      /* ieee80211 TX status. Only used once per 802.11 frag. */
++      u8 must_xmit_txstat:1;
++      struct ieee80211_tx_status txstat;
++};
++
++struct bcm43xx_dmaring {
++      struct bcm43xx_private *bcm;
++      /* Kernel virtual base address of the ring memory. */
++      struct bcm43xx_dmadesc *vbase;
++      /* DMA memory offset */
++      dma_addr_t memoffset;
++      /* (Unadjusted) DMA base bus-address of the ring memory. */
++      dma_addr_t dmabase;
++      /* Meta data about all descriptors. */
++      struct bcm43xx_dmadesc_meta *meta;
++      /* Number of descriptor slots in the ring. */
++      int nr_slots;
++      /* Number of used descriptor slots. */
++      int used_slots;
++      /* Currently used slot in the ring. */
++      int current_slot;
++      /* Total number of packets sent. Statistics only. */
++      unsigned int nr_tx_packets;
++      /* Frameoffset in octets. */
++      u32 frameoffset;
++      /* Descriptor buffer size. */
++      u16 rx_buffersize;
++      /* The MMIO base register of the DMA controller, this
++       * ring is posted to.
++       */
++      u16 mmio_base;
++      u8 tx:1,        /* TRUE, if this is a TX ring. */
++         suspended:1; /* TRUE, if transfers are suspended on this ring. */
++#ifdef CONFIG_BCM43XX_D80211_DEBUG
++      /* Maximum number of used slots. */
++      int max_used_slots;
++#endif /* CONFIG_BCM43XX_D80211_DEBUG*/
++};
++
++
++static inline
++u32 bcm43xx_dma_read(struct bcm43xx_dmaring *ring,
++                   u16 offset)
++{
++      return bcm43xx_read32(ring->bcm, ring->mmio_base + offset);
++}
++
++static inline
++void bcm43xx_dma_write(struct bcm43xx_dmaring *ring,
++                     u16 offset, u32 value)
++{
++      bcm43xx_write32(ring->bcm, ring->mmio_base + offset, value);
++}
++
++
++int bcm43xx_dma_init(struct bcm43xx_private *bcm);
++void bcm43xx_dma_free(struct bcm43xx_private *bcm);
++
++int bcm43xx_dmacontroller_rx_reset(struct bcm43xx_private *bcm,
++                                 u16 dmacontroller_mmio_base);
++int bcm43xx_dmacontroller_tx_reset(struct bcm43xx_private *bcm,
++                                 u16 dmacontroller_mmio_base);
++
++void bcm43xx_dma_tx_suspend(struct bcm43xx_dmaring *ring);
++void bcm43xx_dma_tx_resume(struct bcm43xx_dmaring *ring);
++
++void bcm43xx_dma_get_tx_stats(struct bcm43xx_private *bcm,
++                            struct ieee80211_tx_queue_stats *stats);
++
++int bcm43xx_dma_tx(struct bcm43xx_private *bcm,
++                 struct sk_buff *skb,
++                 struct ieee80211_tx_control *ctl);
++void bcm43xx_dma_handle_xmitstatus(struct bcm43xx_private *bcm,
++                                 struct bcm43xx_xmitstatus *status);
++
++void bcm43xx_dma_rx(struct bcm43xx_dmaring *ring);
++
++
++#else /* CONFIG_BCM43XX_D80211_DMA */
++
++
++static inline
++int bcm43xx_dma_init(struct bcm43xx_private *bcm)
++{
++      return 0;
++}
++static inline
++void bcm43xx_dma_free(struct bcm43xx_private *bcm)
++{
++}
++static inline
++int bcm43xx_dmacontroller_rx_reset(struct bcm43xx_private *bcm,
++                                 u16 dmacontroller_mmio_base)
++{
++      return 0;
++}
++static inline
++int bcm43xx_dmacontroller_tx_reset(struct bcm43xx_private *bcm,
++                                 u16 dmacontroller_mmio_base)
++{
++      return 0;
++}
++static inline
++void bcm43xx_dma_get_tx_stats(struct bcm43xx_private *bcm,
++                            struct ieee80211_tx_queue_stats *stats)
++{
++}
++static inline
++int bcm43xx_dma_tx(struct bcm43xx_private *bcm,
++                 struct sk_buff *skb,
++                 struct ieee80211_tx_control *ctl)
++{
++      return 0;
++}
++static inline
++void bcm43xx_dma_handle_xmitstatus(struct bcm43xx_private *bcm,
++                                 struct bcm43xx_xmitstatus *status)
++{
++}
++static inline
++void bcm43xx_dma_rx(struct bcm43xx_dmaring *ring)
++{
++}
++
++#endif /* CONFIG_BCM43XX_D80211_DMA */
++#endif /* BCM43xx_DMA_H_ */
+diff -Nur linux-2.6.16/drivers/net/wireless/bcm43xx-d80211/bcm43xx_ethtool.c linux-2.6.16-bcm43xx/drivers/net/wireless/bcm43xx-d80211/bcm43xx_ethtool.c
+--- linux-2.6.16/drivers/net/wireless/bcm43xx-d80211/bcm43xx_ethtool.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.16-bcm43xx/drivers/net/wireless/bcm43xx-d80211/bcm43xx_ethtool.c 2006-03-28 22:16:14.000000000 +0200
+@@ -0,0 +1,50 @@
++/*
++
++  Broadcom BCM43xx wireless driver
++
++  ethtool support
++
++  Copyright (c) 2006 Jason Lunz <lunz@falooley.org>
++
++  Some code in this file is derived from the 8139too.c driver
++  Copyright (C) 2002 Jeff Garzik
++
++  This program is free software; you can redistribute it and/or modify
++  it under the terms of the GNU General Public License as published by
++  the Free Software Foundation; either version 2 of the License, or
++  (at your option) any later version.
++
++  This program is distributed in the hope that it will be useful,
++  but WITHOUT ANY WARRANTY; without even the implied warranty of
++  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++  GNU General Public License for more details.
++
++  You should have received a copy of the GNU General Public License
++  along with this program; see the file COPYING.  If not, write to
++  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
++  Boston, MA 02110-1301, USA.
++
++*/
++
++#include "bcm43xx.h"
++#include "bcm43xx_ethtool.h"
++
++#include <linux/netdevice.h>
++#include <linux/pci.h>
++#include <linux/string.h>
++#include <linux/version.h>
++
++
++static void bcm43xx_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
++{
++      struct bcm43xx_private *bcm = bcm43xx_priv(dev);
++
++      strncpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
++      strncpy(info->version, UTS_RELEASE, sizeof(info->version));
++      strncpy(info->bus_info, pci_name(bcm->pci_dev), ETHTOOL_BUSINFO_LEN);
++}
++
++struct ethtool_ops bcm43xx_ethtool_ops = {
++      .get_drvinfo = bcm43xx_get_drvinfo,
++      .get_link = ethtool_op_get_link,
++};
+diff -Nur linux-2.6.16/drivers/net/wireless/bcm43xx-d80211/bcm43xx_ethtool.h linux-2.6.16-bcm43xx/drivers/net/wireless/bcm43xx-d80211/bcm43xx_ethtool.h
+--- linux-2.6.16/drivers/net/wireless/bcm43xx-d80211/bcm43xx_ethtool.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.16-bcm43xx/drivers/net/wireless/bcm43xx-d80211/bcm43xx_ethtool.h 2006-03-28 22:16:14.000000000 +0200
+@@ -0,0 +1,8 @@
++#ifndef BCM43xx_ETHTOOL_H_
++#define BCM43xx_ETHTOOL_H_
++
++#include <linux/ethtool.h>
++
++extern struct ethtool_ops bcm43xx_ethtool_ops;
++
++#endif /* BCM43xx_ETHTOOL_H_ */
+diff -Nur linux-2.6.16/drivers/net/wireless/bcm43xx-d80211/bcm43xx.h linux-2.6.16-bcm43xx/drivers/net/wireless/bcm43xx-d80211/bcm43xx.h
+--- linux-2.6.16/drivers/net/wireless/bcm43xx-d80211/bcm43xx.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.16-bcm43xx/drivers/net/wireless/bcm43xx-d80211/bcm43xx.h 2006-03-28 22:16:14.000000000 +0200
+@@ -0,0 +1,917 @@
++#ifndef BCM43xx_H_
++#define BCM43xx_H_
++
++#include <linux/version.h>
++#include <linux/kernel.h>
++#include <linux/spinlock.h>
++#include <linux/interrupt.h>
++#include <linux/stringify.h>
++#include <linux/netdevice.h>
++#include <linux/pci.h>
++#include <asm/atomic.h>
++#include <asm/io.h>
++
++#include <linux/wireless.h>
++#include <net/d80211.h>
++#include <net/d80211_mgmt.h>
++#include <net/d80211_common.h>
++
++#include "bcm43xx_debugfs.h"
++#include "bcm43xx_leds.h"
++#include "bcm43xx_sysfs.h"
++
++
++#define PFX                           KBUILD_MODNAME ": "
++
++#define BCM43xx_SWITCH_CORE_MAX_RETRIES       50
++#define BCM43xx_IRQWAIT_MAX_RETRIES   50
++
++#define BCM43xx_IO_SIZE                       8192
++
++/* Active Core PCI Configuration Register. */
++#define BCM43xx_PCICFG_ACTIVE_CORE    0x80
++/* SPROM control register. */
++#define BCM43xx_PCICFG_SPROMCTL               0x88
++/* Interrupt Control PCI Configuration Register. (Only on PCI cores with rev >= 6) */
++#define BCM43xx_PCICFG_ICR            0x94
++
++/* MMIO offsets */
++#define BCM43xx_MMIO_DMA1_REASON      0x20
++#define BCM43xx_MMIO_DMA1_IRQ_MASK    0x24
++#define BCM43xx_MMIO_DMA2_REASON      0x28
++#define BCM43xx_MMIO_DMA2_IRQ_MASK    0x2C
++#define BCM43xx_MMIO_DMA3_REASON      0x30
++#define BCM43xx_MMIO_DMA3_IRQ_MASK    0x34
++#define BCM43xx_MMIO_DMA4_REASON      0x38
++#define BCM43xx_MMIO_DMA4_IRQ_MASK    0x3C
++#define BCM43xx_MMIO_STATUS_BITFIELD  0x120
++#define BCM43xx_MMIO_STATUS2_BITFIELD 0x124
++#define BCM43xx_MMIO_GEN_IRQ_REASON   0x128
++#define BCM43xx_MMIO_GEN_IRQ_MASK     0x12C
++#define BCM43xx_MMIO_RAM_CONTROL      0x130
++#define BCM43xx_MMIO_RAM_DATA         0x134
++#define BCM43xx_MMIO_PS_STATUS                0x140
++#define BCM43xx_MMIO_RADIO_HWENABLED_HI       0x158
++#define BCM43xx_MMIO_SHM_CONTROL      0x160
++#define BCM43xx_MMIO_SHM_DATA         0x164
++#define BCM43xx_MMIO_SHM_DATA_UNALIGNED       0x166
++#define BCM43xx_MMIO_XMITSTAT_0               0x170
++#define BCM43xx_MMIO_XMITSTAT_1               0x174
++#define BCM43xx_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */
++#define BCM43xx_MMIO_REV3PLUS_TSF_HIGH        0x184 /* core rev >= 3 only */
++#define BCM43xx_MMIO_DMA1_BASE                0x200
++#define BCM43xx_MMIO_DMA2_BASE                0x220
++#define BCM43xx_MMIO_DMA3_BASE                0x240
++#define BCM43xx_MMIO_DMA4_BASE                0x260
++#define BCM43xx_MMIO_PIO1_BASE                0x300
++#define BCM43xx_MMIO_PIO2_BASE                0x310
++#define BCM43xx_MMIO_PIO3_BASE                0x320
++#define BCM43xx_MMIO_PIO4_BASE                0x330
++#define BCM43xx_MMIO_PHY_VER          0x3E0
++#define BCM43xx_MMIO_PHY_RADIO                0x3E2
++#define BCM43xx_MMIO_ANTENNA          0x3E8
++#define BCM43xx_MMIO_CHANNEL          0x3F0
++#define BCM43xx_MMIO_CHANNEL_EXT      0x3F4
++#define BCM43xx_MMIO_RADIO_CONTROL    0x3F6
++#define BCM43xx_MMIO_RADIO_DATA_HIGH  0x3F8
++#define BCM43xx_MMIO_RADIO_DATA_LOW   0x3FA
++#define BCM43xx_MMIO_PHY_CONTROL      0x3FC
++#define BCM43xx_MMIO_PHY_DATA         0x3FE
++#define BCM43xx_MMIO_MACFILTER_CONTROL        0x420
++#define BCM43xx_MMIO_MACFILTER_DATA   0x422
++#define BCM43xx_MMIO_RADIO_HWENABLED_LO       0x49A
++#define BCM43xx_MMIO_GPIO_CONTROL     0x49C
++#define BCM43xx_MMIO_GPIO_MASK                0x49E
++#define BCM43xx_MMIO_TSF_0            0x632 /* core rev < 3 only */
++#define BCM43xx_MMIO_TSF_1            0x634 /* core rev < 3 only */
++#define BCM43xx_MMIO_TSF_2            0x636 /* core rev < 3 only */
++#define BCM43xx_MMIO_TSF_3            0x638 /* core rev < 3 only */
++#define BCM43xx_MMIO_POWERUP_DELAY    0x6A8
++
++/* SPROM offsets. */
++#define BCM43xx_SPROM_BASE            0x1000
++#define BCM43xx_SPROM_BOARDFLAGS2     0x1c
++#define BCM43xx_SPROM_IL0MACADDR      0x24
++#define BCM43xx_SPROM_ET0MACADDR      0x27
++#define BCM43xx_SPROM_ET1MACADDR      0x2a
++#define BCM43xx_SPROM_ETHPHY          0x2d
++#define BCM43xx_SPROM_BOARDREV                0x2e
++#define BCM43xx_SPROM_PA0B0           0x2f
++#define BCM43xx_SPROM_PA0B1           0x30
++#define BCM43xx_SPROM_PA0B2           0x31
++#define BCM43xx_SPROM_WL0GPIO0                0x32
++#define BCM43xx_SPROM_WL0GPIO2                0x33
++#define BCM43xx_SPROM_MAXPWR          0x34
++#define BCM43xx_SPROM_PA1B0           0x35
++#define BCM43xx_SPROM_PA1B1           0x36
++#define BCM43xx_SPROM_PA1B2           0x37
++#define BCM43xx_SPROM_IDL_TSSI_TGT    0x38
++#define BCM43xx_SPROM_BOARDFLAGS      0x39
++#define BCM43xx_SPROM_ANTENNA_GAIN    0x3a
++#define BCM43xx_SPROM_VERSION         0x3f
++
++/* BCM43xx_SPROM_BOARDFLAGS values */
++#define BCM43xx_BFL_BTCOEXIST         0x0001 /* implements Bluetooth coexistance */
++#define BCM43xx_BFL_PACTRL            0x0002 /* GPIO 9 controlling the PA */
++#define BCM43xx_BFL_AIRLINEMODE               0x0004 /* implements GPIO 13 radio disable indication */
++#define BCM43xx_BFL_RSSI              0x0008 /* software calculates nrssi slope. */
++#define BCM43xx_BFL_ENETSPI           0x0010 /* has ephy roboswitch spi */
++#define BCM43xx_BFL_XTAL_NOSLOW               0x0020 /* no slow clock available */
++#define BCM43xx_BFL_CCKHIPWR          0x0040 /* can do high power CCK transmission */
++#define BCM43xx_BFL_ENETADM           0x0080 /* has ADMtek switch */
++#define BCM43xx_BFL_ENETVLAN          0x0100 /* can do vlan */
++#define BCM43xx_BFL_AFTERBURNER               0x0200 /* supports Afterburner mode */
++#define BCM43xx_BFL_NOPCI             0x0400 /* leaves PCI floating */
++#define BCM43xx_BFL_FEM                       0x0800 /* supports the Front End Module */
++#define BCM43xx_BFL_EXTLNA            0x1000 /* has an external LNA */
++#define BCM43xx_BFL_HGPA              0x2000 /* had high gain PA */
++#define BCM43xx_BFL_BTCMOD            0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
++#define BCM43xx_BFL_ALTIQ             0x8000 /* alternate I/Q settings */
++
++/* GPIO register offset, in both ChipCommon and PCI core. */
++#define BCM43xx_GPIO_CONTROL          0x6c
++
++/* SHM Routing */
++#define BCM43xx_SHM_SHARED            0x0001
++#define BCM43xx_SHM_WIRELESS          0x0002
++#define BCM43xx_SHM_PCM                       0x0003
++#define BCM43xx_SHM_HWMAC             0x0004
++#define BCM43xx_SHM_UCODE             0x0300
++
++/* MacFilter offsets. */
++#define BCM43xx_MACFILTER_SELF                0x0000
++#define BCM43xx_MACFILTER_ASSOC               0x0003
++
++/* Chipcommon registers. */
++#define BCM43xx_CHIPCOMMON_CAPABILITIES       0x04
++#define BCM43xx_CHIPCOMMON_PLLONDELAY         0xB0
++#define BCM43xx_CHIPCOMMON_FREFSELDELAY               0xB4
++#define BCM43xx_CHIPCOMMON_SLOWCLKCTL         0xB8
++#define BCM43xx_CHIPCOMMON_SYSCLKCTL          0xC0
++
++/* PCI core specific registers. */
++#define BCM43xx_PCICORE_BCAST_ADDR    0x50
++#define BCM43xx_PCICORE_BCAST_DATA    0x54
++#define BCM43xx_PCICORE_SBTOPCI2      0x108
++
++/* SBTOPCI2 values. */
++#define BCM43xx_SBTOPCI2_PREFETCH     0x4
++#define BCM43xx_SBTOPCI2_BURST                0x8
++
++/* Chipcommon capabilities. */
++#define BCM43xx_CAPABILITIES_PCTL             0x00040000
++#define BCM43xx_CAPABILITIES_PLLMASK          0x00030000
++#define BCM43xx_CAPABILITIES_PLLSHIFT         16
++#define BCM43xx_CAPABILITIES_FLASHMASK                0x00000700
++#define BCM43xx_CAPABILITIES_FLASHSHIFT               8
++#define BCM43xx_CAPABILITIES_EXTBUSPRESENT    0x00000040
++#define BCM43xx_CAPABILITIES_UARTGPIO         0x00000020
++#define BCM43xx_CAPABILITIES_UARTCLOCKMASK    0x00000018
++#define BCM43xx_CAPABILITIES_UARTCLOCKSHIFT   3
++#define BCM43xx_CAPABILITIES_MIPSBIGENDIAN    0x00000004
++#define BCM43xx_CAPABILITIES_NRUARTSMASK      0x00000003
++
++/* PowerControl */
++#define BCM43xx_PCTL_IN                       0xB0
++#define BCM43xx_PCTL_OUT              0xB4
++#define BCM43xx_PCTL_OUTENABLE                0xB8
++#define BCM43xx_PCTL_XTAL_POWERUP     0x40
++#define BCM43xx_PCTL_PLL_POWERDOWN    0x80
++
++/* PowerControl Clock Modes */
++#define BCM43xx_PCTL_CLK_FAST         0x00
++#define BCM43xx_PCTL_CLK_SLOW         0x01
++#define BCM43xx_PCTL_CLK_DYNAMIC      0x02
++
++#define BCM43xx_PCTL_FORCE_SLOW               0x0800
++#define BCM43xx_PCTL_FORCE_PLL                0x1000
++#define BCM43xx_PCTL_DYN_XTAL         0x2000
++
++/* COREIDs */
++#define BCM43xx_COREID_CHIPCOMMON     0x800
++#define BCM43xx_COREID_ILINE20          0x801
++#define BCM43xx_COREID_SDRAM            0x803
++#define BCM43xx_COREID_PCI            0x804
++#define BCM43xx_COREID_MIPS             0x805
++#define BCM43xx_COREID_ETHERNET         0x806
++#define BCM43xx_COREID_V90            0x807
++#define BCM43xx_COREID_USB11_HOSTDEV    0x80a
++#define BCM43xx_COREID_IPSEC            0x80b
++#define BCM43xx_COREID_PCMCIA         0x80d
++#define BCM43xx_COREID_EXT_IF           0x80f
++#define BCM43xx_COREID_80211          0x812
++#define BCM43xx_COREID_MIPS_3302        0x816
++#define BCM43xx_COREID_USB11_HOST       0x817
++#define BCM43xx_COREID_USB11_DEV        0x818
++#define BCM43xx_COREID_USB20_HOST       0x819
++#define BCM43xx_COREID_USB20_DEV        0x81a
++#define BCM43xx_COREID_SDIO_HOST        0x81b
++
++/* Core Information Registers */
++#define BCM43xx_CIR_BASE              0xf00
++#define BCM43xx_CIR_SBTPSFLAG         (BCM43xx_CIR_BASE + 0x18)
++#define BCM43xx_CIR_SBIMSTATE         (BCM43xx_CIR_BASE + 0x90)
++#define BCM43xx_CIR_SBINTVEC          (BCM43xx_CIR_BASE + 0x94)
++#define BCM43xx_CIR_SBTMSTATELOW      (BCM43xx_CIR_BASE + 0x98)
++#define BCM43xx_CIR_SBTMSTATEHIGH     (BCM43xx_CIR_BASE + 0x9c)
++#define BCM43xx_CIR_SBIMCONFIGLOW     (BCM43xx_CIR_BASE + 0xa8)
++#define BCM43xx_CIR_SB_ID_HI          (BCM43xx_CIR_BASE + 0xfc)
++
++/* Mask to get the Backplane Flag Number from SBTPSFLAG. */
++#define BCM43xx_BACKPLANE_FLAG_NR_MASK        0x3f
++
++/* SBIMCONFIGLOW values/masks. */
++#define BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK               0x00000007
++#define BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_SHIFT      0
++#define BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK               0x00000070
++#define BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_SHIFT      4
++#define BCM43xx_SBIMCONFIGLOW_CONNID_MASK             0x00ff0000
++#define BCM43xx_SBIMCONFIGLOW_CONNID_SHIFT            16
++
++/* sbtmstatelow state flags */
++#define BCM43xx_SBTMSTATELOW_RESET            0x01
++#define BCM43xx_SBTMSTATELOW_REJECT           0x02
++#define BCM43xx_SBTMSTATELOW_CLOCK            0x10000
++#define BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK 0x20000
++
++/* sbtmstatehigh state flags */
++#define BCM43xx_SBTMSTATEHIGH_SERROR          0x1
++#define BCM43xx_SBTMSTATEHIGH_BUSY            0x4
++
++/* sbimstate flags */
++#define BCM43xx_SBIMSTATE_IB_ERROR            0x20000
++#define BCM43xx_SBIMSTATE_TIMEOUT             0x40000
++
++/* PHYVersioning */
++#define BCM43xx_PHYTYPE_A             0x00
++#define BCM43xx_PHYTYPE_B             0x01
++#define BCM43xx_PHYTYPE_G             0x02
++
++/* PHYRegisters */
++#define BCM43xx_PHY_ILT_A_CTRL                0x0072
++#define BCM43xx_PHY_ILT_A_DATA1               0x0073
++#define BCM43xx_PHY_ILT_A_DATA2               0x0074
++#define BCM43xx_PHY_G_LO_CONTROL      0x0810
++#define BCM43xx_PHY_ILT_G_CTRL                0x0472
++#define BCM43xx_PHY_ILT_G_DATA1               0x0473
++#define BCM43xx_PHY_ILT_G_DATA2               0x0474
++#define BCM43xx_PHY_A_PCTL            0x007B
++#define BCM43xx_PHY_G_PCTL            0x0029
++#define BCM43xx_PHY_A_CRS             0x0029
++#define BCM43xx_PHY_RADIO_BITFIELD    0x0401
++#define BCM43xx_PHY_G_CRS             0x0429
++#define BCM43xx_PHY_NRSSILT_CTRL      0x0803
++#define BCM43xx_PHY_NRSSILT_DATA      0x0804
++
++/* RadioRegisters */
++#define BCM43xx_RADIOCTL_ID           0x01
++
++/* StatusBitField */
++#define BCM43xx_SBF_MAC_ENABLED               0x00000001
++#define BCM43xx_SBF_2                 0x00000002 /*FIXME: fix name*/
++#define BCM43xx_SBF_CORE_READY                0x00000004
++#define BCM43xx_SBF_400                       0x00000400 /*FIXME: fix name*/
++#define BCM43xx_SBF_4000              0x00004000 /*FIXME: fix name*/
++#define BCM43xx_SBF_8000              0x00008000 /*FIXME: fix name*/
++#define BCM43xx_SBF_XFER_REG_BYTESWAP 0x00010000
++#define BCM43xx_SBF_MODE_NOTADHOC     0x00020000
++#define BCM43xx_SBF_MODE_AP           0x00040000
++#define BCM43xx_SBF_RADIOREG_LOCK     0x00080000
++#define BCM43xx_SBF_MODE_MONITOR      0x00400000
++#define BCM43xx_SBF_MODE_PROMISC      0x01000000
++#define BCM43xx_SBF_PS1                       0x02000000
++#define BCM43xx_SBF_PS2                       0x04000000
++#define BCM43xx_SBF_NO_SSID_BCAST     0x08000000
++#define BCM43xx_SBF_TIME_UPDATE               0x10000000
++#define BCM43xx_SBF_80000000          0x80000000 /*FIXME: fix name*/
++
++/* MicrocodeFlagsBitfield (addr + lo-word values?)*/
++#define BCM43xx_UCODEFLAGS_OFFSET     0x005E
++
++#define BCM43xx_UCODEFLAG_AUTODIV     0x0001
++#define BCM43xx_UCODEFLAG_UNKBGPHY    0x0002
++#define BCM43xx_UCODEFLAG_UNKBPHY     0x0004
++#define BCM43xx_UCODEFLAG_UNKGPHY     0x0020
++#define BCM43xx_UCODEFLAG_UNKPACTRL   0x0040
++#define BCM43xx_UCODEFLAG_JAPAN               0x0080
++
++/* Generic-Interrupt reasons. */
++#define BCM43xx_IRQ_READY             (1 << 0)
++#define BCM43xx_IRQ_BEACON            (1 << 1)
++#define BCM43xx_IRQ_PS                        (1 << 2)
++#define BCM43xx_IRQ_REG124            (1 << 5)
++#define BCM43xx_IRQ_PMQ                       (1 << 6)
++#define BCM43xx_IRQ_PIO_WORKAROUND    (1 << 8)
++#define BCM43xx_IRQ_XMIT_ERROR                (1 << 11)
++#define BCM43xx_IRQ_RX                        (1 << 15)
++#define BCM43xx_IRQ_SCAN              (1 << 16)
++#define BCM43xx_IRQ_NOISE             (1 << 18)
++#define BCM43xx_IRQ_XMIT_STATUS               (1 << 29)
++
++#define BCM43xx_IRQ_ALL                       0xffffffff
++#define BCM43xx_IRQ_INITIAL           (BCM43xx_IRQ_PS |               \
++                                       BCM43xx_IRQ_REG124 |           \
++                                       BCM43xx_IRQ_PMQ |              \
++                                       BCM43xx_IRQ_XMIT_ERROR |       \
++                                       BCM43xx_IRQ_RX |               \
++                                       BCM43xx_IRQ_SCAN |             \
++                                       BCM43xx_IRQ_NOISE |            \
++                                       BCM43xx_IRQ_XMIT_STATUS)
++
++/* Bus type PCI. */
++#define BCM43xx_BUSTYPE_PCI   0
++/* Bus type Silicone Backplane Bus. */
++#define BCM43xx_BUSTYPE_SB    1
++/* Bus type PCMCIA. */
++#define BCM43xx_BUSTYPE_PCMCIA        2
++
++/* Rate values. */
++#define BCM43xx_CCK_RATE_1MB          0x02
++#define BCM43xx_CCK_RATE_2MB          0x04
++#define BCM43xx_CCK_RATE_5MB          0x0B
++#define BCM43xx_CCK_RATE_11MB         0x16
++#define BCM43xx_OFDM_RATE_6MB         0x0C
++#define BCM43xx_OFDM_RATE_9MB         0x12
++#define BCM43xx_OFDM_RATE_12MB                0x18
++#define BCM43xx_OFDM_RATE_18MB                0x24
++#define BCM43xx_OFDM_RATE_24MB                0x30
++#define BCM43xx_OFDM_RATE_36MB                0x48
++#define BCM43xx_OFDM_RATE_48MB                0x60
++#define BCM43xx_OFDM_RATE_54MB                0x6C
++
++#define BCM43xx_DEFAULT_SHORT_RETRY_LIMIT     7
++#define BCM43xx_DEFAULT_LONG_RETRY_LIMIT      4
++
++/* Max size of a security key */
++#define BCM43xx_SEC_KEYSIZE                   16
++/* Security algorithms. */
++enum {
++      BCM43xx_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */
++      BCM43xx_SEC_ALGO_WEP,
++      BCM43xx_SEC_ALGO_UNKNOWN,
++      BCM43xx_SEC_ALGO_AES,
++      BCM43xx_SEC_ALGO_WEP104,
++      BCM43xx_SEC_ALGO_TKIP,
++};
++
++
++#ifdef assert
++# undef assert
++#endif
++#ifdef CONFIG_BCM43XX_D80211_DEBUG
++#define assert(expr) \
++      do {                                                                    \
++              if (unlikely(!(expr))) {                                        \
++              printk(KERN_ERR PFX "ASSERTION FAILED (%s) at: %s:%d:%s()\n",   \
++                      #expr, __FILE__, __LINE__, __FUNCTION__);               \
++              }                                                               \
++      } while (0)
++#else
++#define assert(expr)  do { /* nothing */ } while (0)
++#endif
++
++/* rate limited printk(). */
++#ifdef printkl
++# undef printkl
++#endif
++#define printkl(f, x...)  do { if (printk_ratelimit()) printk(f ,##x); } while (0)
++/* rate limited printk() for debugging */
++#ifdef dprintkl
++# undef dprintkl
++#endif
++#ifdef CONFIG_BCM43XX_D80211_DEBUG
++# define dprintkl             printkl
++#else
++# define dprintkl(f, x...)    do { /* nothing */ } while (0)
++#endif
++
++/* debugging printk() */
++#ifdef dprintk
++# undef dprintk
++#endif
++#ifdef CONFIG_BCM43XX_D80211_DEBUG
++# define dprintk(f, x...)  do { printk(f ,##x); } while (0)
++#else
++# define dprintk(f, x...)  do { /* nothing */ } while (0)
++#endif
++
++
++struct net_device;
++struct pci_dev;
++struct bcm43xx_dmaring;
++struct bcm43xx_pioqueue;
++
++struct bcm43xx_initval {
++      u16 offset;
++      u16 size;
++      u32 value;
++} __attribute__((__packed__));
++
++/* Values for bcm430x_sprominfo.locale */
++enum {
++      BCM43xx_LOCALE_WORLD = 0,
++      BCM43xx_LOCALE_THAILAND,
++      BCM43xx_LOCALE_ISRAEL,
++      BCM43xx_LOCALE_JORDAN,
++      BCM43xx_LOCALE_CHINA,
++      BCM43xx_LOCALE_JAPAN,
++      BCM43xx_LOCALE_USA_CANADA_ANZ,
++      BCM43xx_LOCALE_EUROPE,
++      BCM43xx_LOCALE_USA_LOW,
++      BCM43xx_LOCALE_JAPAN_HIGH,
++      BCM43xx_LOCALE_ALL,
++      BCM43xx_LOCALE_NONE,
++};
++
++#define BCM43xx_SPROM_SIZE    64 /* in 16-bit words. */
++struct bcm43xx_sprominfo {
++      u16 boardflags2;
++      u8 il0macaddr[6];
++      u8 et0macaddr[6];
++      u8 et1macaddr[6];
++      u8 et0phyaddr:5;
++      u8 et1phyaddr:5;
++      u8 et0mdcport:1;
++      u8 et1mdcport:1;
++      u8 boardrev;
++      u8 locale:4;
++      u8 antennas_aphy:2;
++      u8 antennas_bgphy:2;
++      u16 pa0b0;
++      u16 pa0b1;
++      u16 pa0b2;
++      u8 wl0gpio0;
++      u8 wl0gpio1;
++      u8 wl0gpio2;
++      u8 wl0gpio3;
++      u8 maxpower_aphy;
++      u8 maxpower_bgphy;
++      u16 pa1b0;
++      u16 pa1b1;
++      u16 pa1b2;
++      u8 idle_tssi_tgt_aphy;
++      u8 idle_tssi_tgt_bgphy;
++      u16 boardflags;
++      u16 antennagain_aphy;
++      u16 antennagain_bgphy;
++};
++
++/* Value pair to measure the LocalOscillator. */
++struct bcm43xx_lopair {
++      s8 low;
++      s8 high;
++      u8 used:1;
++};
++#define BCM43xx_LO_COUNT      (14*4)
++
++struct bcm43xx_phyinfo {
++      /* Hardware Data */
++      u8 version;
++      u8 type;
++      u8 rev;
++      u16 antenna_diversity;
++      u16 savedpctlreg;
++      u16 minlowsig[2];
++      u16 minlowsigpos[2];
++      u8 connected:1,
++         calibrated:1,
++         is_locked:1, /* used in bcm43xx_phy_{un}lock() */
++         dyn_tssi_tbl:1; /* used in bcm43xx_phy_init_tssi2dbm_table() */
++      /* LO Measurement Data.
++       * Use bcm43xx_get_lopair() to get a value.
++       */
++      struct bcm43xx_lopair *_lo_pairs;
++
++      /* TSSI to dBm table in use */
++      const s8 *tssi2dbm;
++      /* idle TSSI value */
++      s8 idle_tssi;
++
++      /* Values from bcm43xx_calc_loopback_gain() */
++      u16 loopback_gain[2];
++
++      /* PHY lock for core.rev < 3
++       * This lock is only used by bcm43xx_phy_{un}lock()
++       */
++      spinlock_t lock;
++};
++
++
++struct bcm43xx_radioinfo {
++      u16 manufact;
++      u16 version;
++      u8 revision;
++
++      /* Desired TX power level (in dBm).
++       * This is set by the user and adjusted in bcm43xx_phy_xmitpower(). */
++      u8 power_level;
++      /* TX Power control values. */
++      union {
++              /* B/G PHY */
++              struct {
++                      u16 baseband_atten;
++                      u16 radio_atten;
++                      u16 txctl1;
++                      u16 txctl2;
++              };
++              /* A PHY */
++              struct {
++                      u16 txpwr_offset;
++              };
++      };
++
++      /* Current Interference Mitigation mode */
++      int interfmode;
++      /* Stack of saved values from the Interference Mitigation code.
++       * Each value in the stack is layed out as follows:
++       * bit 0-11:  offset
++       * bit 12-15: register ID
++       * bit 16-32: value
++       * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
++       */
++#define BCM43xx_INTERFSTACK_SIZE      26
++      u32 interfstack[BCM43xx_INTERFSTACK_SIZE];
++
++      /* Saved values from the NRSSI Slope calculation */
++      s16 nrssi[2];
++      s32 nrssislope;
++      /* In memory nrssi lookup table. */
++      s8 nrssi_lt[64];
++
++      /* current channel */
++      u8 channel;
++      u8 initial_channel;
++
++      u16 lofcal;
++
++      u16 initval;
++
++      u8 enabled:1;
++      /* ACI (adjacent channel interference) flags. */
++      u8 aci_enable:1,
++         aci_wlan_automatic:1,
++         aci_hw_rssi:1;
++};
++
++/* Data structures for DMA transmission, per 80211 core. */
++struct bcm43xx_dma {
++      struct bcm43xx_dmaring *tx_ring0;
++      struct bcm43xx_dmaring *tx_ring1;
++      struct bcm43xx_dmaring *tx_ring2;
++      struct bcm43xx_dmaring *tx_ring3;
++      struct bcm43xx_dmaring *rx_ring0;
++      struct bcm43xx_dmaring *rx_ring1; /* only available on core.rev < 5 */
++};
++
++/* Data structures for PIO transmission, per 80211 core. */
++struct bcm43xx_pio {
++      struct bcm43xx_pioqueue *queue0;
++      struct bcm43xx_pioqueue *queue1;
++      struct bcm43xx_pioqueue *queue2;
++      struct bcm43xx_pioqueue *queue3;
++};
++
++#define BCM43xx_MAX_80211_CORES               2
++
++#ifdef CONFIG_BCM947XX
++#define core_offset(bcm) (bcm)->current_core_offset
++#else
++#define core_offset(bcm) 0
++#endif
++
++/* Generic information about a core. */
++struct bcm43xx_coreinfo {
++      u8 available:1,
++         enabled:1,
++         initialized:1;
++      /** core_id ID number */
++      u16 id;
++      /** core_rev revision number */
++      u8 rev;
++      /** Index number for _switch_core() */
++      u8 index;
++};
++
++/* Additional information for each 80211 core. */
++struct bcm43xx_coreinfo_80211 {
++      /* PHY device. */
++      struct bcm43xx_phyinfo phy;
++      /* Radio device. */
++      struct bcm43xx_radioinfo radio;
++      union {
++              /* DMA context. */
++              struct bcm43xx_dma dma;
++              /* PIO context. */
++              struct bcm43xx_pio pio;
++      };
++};
++
++/* Context information for a noise calculation (Link Quality). */
++struct bcm43xx_noise_calculation {
++      struct bcm43xx_coreinfo *core_at_start;
++      u8 channel_at_start;
++      u8 calculation_running:1;
++      u8 nr_samples;
++      s8 samples[8][4];
++};
++
++struct bcm43xx_stats {
++      u8 link_quality;
++      /* Store the last TX/RX times here for updating the leds. */
++      unsigned long last_tx;
++      unsigned long last_rx;
++};
++
++struct bcm43xx_key {
++      u8 enabled:1;
++      u8 algorithm;
++};
++
++struct bcm43xx_private {
++      struct bcm43xx_sysfs sysfs;
++
++      struct ieee80211_hw *ieee;
++      struct ieee80211_low_level_stats ieee_stats;
++      int iw_mode;
++
++      struct net_device *net_dev;
++      struct pci_dev *pci_dev;
++      unsigned int irq;
++
++      void __iomem *mmio_addr;
++      unsigned int mmio_len;
++
++      /* Do not use the lock directly. Use the bcm43xx_lock* helper
++       * functions, to be MMIO-safe. */
++      spinlock_t _lock;
++
++      /* Driver status flags. */
++      u32 initialized:1,              /* init_board() succeed */
++          was_initialized:1,          /* for PCI suspend/resume. */
++          shutting_down:1,            /* free_board() in progress */
++          __using_pio:1,              /* Internal, use bcm43xx_using_pio(). */
++          bad_frames_preempt:1,       /* Use "Bad Frames Preemption" (default off) */
++          reg124_set_0x4:1,           /* Some variable to keep track of IRQ stuff. */
++          powersaving:1,              /* TRUE if we are in PowerSaving mode. FALSE otherwise. */
++          short_preamble:1,           /* TRUE, if short preamble is enabled. */
++          short_slot:1,               /* TRUE, if short slot timing is enabled. */
++          firmware_norelease:1;       /* Do not release the firmware. Used on suspend. */
++
++      struct bcm43xx_stats stats;
++
++      /* Bus type we are connected to.
++       * This is currently always BCM43xx_BUSTYPE_PCI
++       */
++      u8 bustype;
++
++      u16 board_vendor;
++      u16 board_type;
++      u16 board_revision;
++
++      u16 chip_id;
++      u8 chip_rev;
++      u8 chip_package;
++
++      struct bcm43xx_sprominfo sprom;
++#define BCM43xx_NR_LEDS               4
++      struct bcm43xx_led leds[BCM43xx_NR_LEDS];
++
++      /* The currently active core. */
++      struct bcm43xx_coreinfo *current_core;
++#ifdef CONFIG_BCM947XX
++      /** current core memory offset */
++      u32 current_core_offset;
++#endif
++      struct bcm43xx_coreinfo *active_80211_core;
++      /* coreinfo structs for all possible cores follow.
++       * Note that a core might not exist.
++       * So check the coreinfo flags before using it.
++       */
++      struct bcm43xx_coreinfo core_chipcommon;
++      struct bcm43xx_coreinfo core_pci;
++      struct bcm43xx_coreinfo core_80211[ BCM43xx_MAX_80211_CORES ];
++      /* Additional information, specific to the 80211 cores. */
++      struct bcm43xx_coreinfo_80211 core_80211_ext[ BCM43xx_MAX_80211_CORES ];
++      /* Index of the current 80211 core. If current_core is not
++       * an 80211 core, this is -1.
++       */
++      int current_80211_core_idx;
++      /* Number of available 80211 cores. */
++      int nr_80211_available;
++
++      u32 chipcommon_capabilities;
++
++      /* Reason code of the last interrupt. */
++      u32 irq_reason;
++      u32 dma_reason[4];
++      /* saved irq enable/disable state bitfield. */
++      u32 irq_savedstate;
++      /* Link Quality calculation context. */
++      struct bcm43xx_noise_calculation noisecalc;
++
++      /* Interrupt Service Routine tasklet (bottom-half) */
++      struct tasklet_struct isr_tasklet;
++
++      /* Periodic tasks */
++      struct timer_list periodic_tasks;
++      unsigned int periodic_state;
++
++      struct work_struct restart_work;
++
++      /* Informational stuff. */
++      char nick[IW_ESSID_MAX_SIZE + 1];
++      u8 bssid[ETH_ALEN];
++
++      /* encryption/decryption */
++      u16 security_offset;
++      struct bcm43xx_key key[54];
++      u8 default_key_idx;
++
++      /* Firmware. */
++      const struct firmware *ucode;
++      const struct firmware *pcm;
++      const struct firmware *initvals0;
++      const struct firmware *initvals1;
++
++      /* Cached beacon template while uploading the template. */
++      struct sk_buff *cached_beacon;
++
++      /* Debugging stuff follows. */
++#ifdef CONFIG_BCM43XX_D80211_DEBUG
++      struct bcm43xx_dfsentry *dfsentry;
++#endif
++};
++
++/* bcm43xx_(un)lock() protect struct bcm43xx_private.
++ * Note that _NO_ MMIO writes are allowed. If you want to
++ * write to the device through MMIO in the critical section, use
++ * the *_mmio lock functions.
++ * MMIO read-access is allowed, though.
++ */
++#define bcm43xx_lock(bcm, flags)      spin_lock_irqsave(&(bcm)->_lock, flags)
++#define bcm43xx_unlock(bcm, flags)    spin_unlock_irqrestore(&(bcm)->_lock, flags)
++/* bcm43xx_(un)lock_mmio() protect struct bcm43xx_private and MMIO.
++ * MMIO write-access to the device is allowed.
++ * All MMIO writes are flushed on unlock, so it is guaranteed to not
++ * interfere with other threads writing MMIO registers.
++ */
++#define bcm43xx_lock_mmio(bcm, flags) bcm43xx_lock(bcm, flags)
++#define bcm43xx_unlock_mmio(bcm, flags)       do { mmiowb(); bcm43xx_unlock(bcm, flags); } while (0)
++
++static inline
++struct bcm43xx_private * bcm43xx_priv(struct net_device *dev)
++{
++      return ieee80211_dev_hw_data(dev);
++}
++
++/* Helper function, which returns a boolean.
++ * TRUE, if PIO is used; FALSE, if DMA is used.
++ */
++#if defined(CONFIG_BCM43XX_D80211_DMA) && defined(CONFIG_BCM43XX_D80211_PIO)
++static inline
++int bcm43xx_using_pio(struct bcm43xx_private *bcm)
++{
++      return bcm->__using_pio;
++}
++#elif defined(CONFIG_BCM43XX_D80211_DMA)
++static inline
++int bcm43xx_using_pio(struct bcm43xx_private *bcm)
++{
++      return 0;
++}
++#elif defined(CONFIG_BCM43XX_D80211_PIO)
++static inline
++int bcm43xx_using_pio(struct bcm43xx_private *bcm)
++{
++      return 1;
++}
++#else
++# error "Using neither DMA nor PIO? Confused..."
++#endif
++
++/* Helper functions to access data structures private to the 80211 cores.
++ * Note that we _must_ have an 80211 core mapped when calling
++ * any of these functions.
++ */
++static inline
++struct bcm43xx_pio * bcm43xx_current_pio(struct bcm43xx_private *bcm)
++{
++      assert(bcm43xx_using_pio(bcm));
++      assert(bcm->current_80211_core_idx >= 0);
++      assert(bcm->current_80211_core_idx < BCM43xx_MAX_80211_CORES);
++      return &(bcm->core_80211_ext[bcm->current_80211_core_idx].pio);
++}
++static inline
++struct bcm43xx_dma * bcm43xx_current_dma(struct bcm43xx_private *bcm)
++{
++      assert(!bcm43xx_using_pio(bcm));
++      assert(bcm->current_80211_core_idx >= 0);
++      assert(bcm->current_80211_core_idx < BCM43xx_MAX_80211_CORES);
++      return &(bcm->core_80211_ext[bcm->current_80211_core_idx].dma);
++}
++static inline
++struct bcm43xx_phyinfo * bcm43xx_current_phy(struct bcm43xx_private *bcm)
++{
++      assert(bcm->current_80211_core_idx >= 0);
++      assert(bcm->current_80211_core_idx < BCM43xx_MAX_80211_CORES);
++      return &(bcm->core_80211_ext[bcm->current_80211_core_idx].phy);
++}
++static inline
++struct bcm43xx_radioinfo * bcm43xx_current_radio(struct bcm43xx_private *bcm)
++{
++      assert(bcm->current_80211_core_idx >= 0);
++      assert(bcm->current_80211_core_idx < BCM43xx_MAX_80211_CORES);
++      return &(bcm->core_80211_ext[bcm->current_80211_core_idx].radio);
++}
++
++/* Are we running in init_board() context? */
++static inline
++int bcm43xx_is_initializing(struct bcm43xx_private *bcm)
++{
++      if (bcm->initialized)
++              return 0;
++      if (bcm->shutting_down)
++              return 0;
++      return 1;
++}
++
++static inline
++struct bcm43xx_lopair * bcm43xx_get_lopair(struct bcm43xx_phyinfo *phy,
++                                         u16 radio_attenuation,
++                                         u16 baseband_attenuation)
++{
++      return phy->_lo_pairs + (radio_attenuation + 14 * (baseband_attenuation / 2));
++}
++
++
++static inline
++u16 bcm43xx_read16(struct bcm43xx_private *bcm, u16 offset)
++{
++      return ioread16(bcm->mmio_addr + core_offset(bcm) + offset);
++}
++
++static inline
++void bcm43xx_write16(struct bcm43xx_private *bcm, u16 offset, u16 value)
++{
++      iowrite16(value, bcm->mmio_addr + core_offset(bcm) + offset);
++}
++
++static inline
++u32 bcm43xx_read32(struct bcm43xx_private *bcm, u16 offset)
++{
++      return ioread32(bcm->mmio_addr + core_offset(bcm) + offset);
++}
++
++static inline
++void bcm43xx_write32(struct bcm43xx_private *bcm, u16 offset, u32 value)
++{
++      iowrite32(value, bcm->mmio_addr + core_offset(bcm) + offset);
++}
++
++static inline
++int bcm43xx_pci_read_config16(struct bcm43xx_private *bcm, int offset, u16 *value)
++{
++      return pci_read_config_word(bcm->pci_dev, offset, value);
++}
++
++static inline
++int bcm43xx_pci_read_config32(struct bcm43xx_private *bcm, int offset, u32 *value)
++{
++      return pci_read_config_dword(bcm->pci_dev, offset, value);
++}
++
++static inline
++int bcm43xx_pci_write_config16(struct bcm43xx_private *bcm, int offset, u16 value)
++{
++      return pci_write_config_word(bcm->pci_dev, offset, value);
++}
++
++static inline
++int bcm43xx_pci_write_config32(struct bcm43xx_private *bcm, int offset, u32 value)
++{
++      return pci_write_config_dword(bcm->pci_dev, offset, value);
++}
++
++/** Limit a value between two limits */
++#ifdef limit_value
++# undef limit_value
++#endif
++#define limit_value(value, min, max)  \
++      ({                                              \
++              typeof(value) __value = (value);        \
++              typeof(value) __min = (min);            \
++              typeof(value) __max = (max);            \
++              if (__value < __min)                    \
++                      __value = __min;                \
++              else if (__value > __max)               \
++                      __value = __max;                \
++              __value;                                \
++      })
++
++/** Helpers to print MAC addresses. */
++#define BCM43xx_MACFMT                "%02x:%02x:%02x:%02x:%02x:%02x"
++#define BCM43xx_MACARG(x)     ((u8*)(x))[0], ((u8*)(x))[1], \
++                              ((u8*)(x))[2], ((u8*)(x))[3], \
++                              ((u8*)(x))[4], ((u8*)(x))[5]
++
++#endif /* BCM43xx_H_ */
+diff -Nur linux-2.6.16/drivers/net/wireless/bcm43xx-d80211/bcm43xx_ilt.c linux-2.6.16-bcm43xx/drivers/net/wireless/bcm43xx-d80211/bcm43xx_ilt.c
+--- linux-2.6.16/drivers/net/wireless/bcm43xx-d80211/bcm43xx_ilt.c     1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.16-bcm43xx/drivers/net/wireless/bcm43xx-d80211/bcm43xx_ilt.c     2006-03-28 22:16:14.000000000 +0200
+@@ -0,0 +1,337 @@
++/*
++
++  Broadcom BCM43xx wireless driver
++
++  Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
++                     Stefano Brivio <st3@riseup.net>
++                     Michael Buesch <mbuesch@freenet.de>
++                     Danny van Dyk <kugelfang@gentoo.org>
++                     Andreas Jaggi <andreas.jaggi@waterwave.ch>
++
++  This program is free software; you can redistribute it and/or modify
++  it under the terms of the GNU General Public License as published by
++  the Free Software Foundation; either version 2 of the License, or
++  (at your option) any later version.
++
++  This program is distributed in the hope that it will be useful,
++  but WITHOUT ANY WARRANTY; without even the implied warranty of
++  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++  GNU General Public License for more details.
++
++  You should have received a copy of the GNU General Public License
++  along with this program; see the file COPYING.  If not, write to
++  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
++  Boston, MA 02110-1301, USA.
++
++*/
++
++#include "bcm43xx.h"
++#include "bcm43xx_ilt.h"
++#include "bcm43xx_phy.h"
++
++
++/**** Initial Internal Lookup Tables ****/
++
++const u32 bcm43xx_ilt_rotor[BCM43xx_ILT_ROTOR_SIZE] = {
++      0xFEB93FFD, 0xFEC63FFD, /* 0 */
++      0xFED23FFD, 0xFEDF3FFD,
++      0xFEEC3FFE, 0xFEF83FFE,
++      0xFF053FFE, 0xFF113FFE,
++      0xFF1E3FFE, 0xFF2A3FFF, /* 8 */
++      0xFF373FFF, 0xFF443FFF,
++      0xFF503FFF, 0xFF5D3FFF,
++      0xFF693FFF, 0xFF763FFF,
++      0xFF824000, 0xFF8F4000, /* 16 */
++      0xFF9B4000, 0xFFA84000,
++      0xFFB54000, 0xFFC14000,
++      0xFFCE4000, 0xFFDA4000,
++      0xFFE74000, 0xFFF34000, /* 24 */
++      0x00004000, 0x000D4000,
++      0x00194000, 0x00264000,
++      0x00324000, 0x003F4000,
++      0x004B4000, 0x00584000, /* 32 */
++      0x00654000, 0x00714000,
++      0x007E4000, 0x008A3FFF,
++      0x00973FFF, 0x00A33FFF,
++      0x00B03FFF, 0x00BC3FFF, /* 40 */
++      0x00C93FFF, 0x00D63FFF,
++      0x00E23FFE, 0x00EF3FFE,
++      0x00FB3FFE, 0x01083FFE,
++      0x01143FFE, 0x01213FFD, /* 48 */
++      0x012E3FFD, 0x013A3FFD,
++      0x01473FFD,
++};
++
++const u32 bcm43xx_ilt_retard[BCM43xx_ILT_RETARD_SIZE] = {
++      0xDB93CB87, 0xD666CF64, /* 0 */
++      0xD1FDD358, 0xCDA6D826,
++      0xCA38DD9F, 0xC729E2B4,
++      0xC469E88E, 0xC26AEE2B,
++      0xC0DEF46C, 0xC073FA62, /* 8 */
++      0xC01D00D5, 0xC0760743,
++      0xC1560D1E, 0xC2E51369,
++      0xC4ED18FF, 0xC7AC1ED7,
++      0xCB2823B2, 0xCEFA28D9, /* 16 */
++      0xD2F62D3F, 0xD7BB3197,
++      0xDCE53568, 0xE1FE3875,
++      0xE7D13B35, 0xED663D35,
++      0xF39B3EC4, 0xF98E3FA7, /* 24 */
++      0x00004000, 0x06723FA7,
++      0x0C653EC4, 0x129A3D35,
++      0x182F3B35, 0x1E023875,
++      0x231B3568, 0x28453197, /* 32 */
++      0x2D0A2D3F, 0x310628D9,
++      0x34D823B2, 0x38541ED7,
++      0x3B1318FF, 0x3D1B1369,
++      0x3EAA0D1E, 0x3F8A0743, /* 40 */
++      0x3FE300D5, 0x3F8DFA62,
++      0x3F22F46C, 0x3D96EE2B,
++      0x3B97E88E, 0x38D7E2B4,
++      0x35C8DD9F, 0x325AD826, /* 48 */
++      0x2E03D358, 0x299ACF64,
++      0x246DCB87,
++};
++
++const u16 bcm43xx_ilt_finefreqa[BCM43xx_ILT_FINEFREQA_SIZE] = {
++      0x0082, 0x0082, 0x0102, 0x0182, /* 0 */
++      0x0202, 0x0282, 0x0302, 0x0382,
++      0x0402, 0x0482, 0x0502, 0x0582,
++      0x05E2, 0x0662, 0x06E2, 0x0762,
++      0x07E2, 0x0842, 0x08C2, 0x0942, /* 16 */
++      0x09C2, 0x0A22, 0x0AA2, 0x0B02,
++      0x0B82, 0x0BE2, 0x0C62, 0x0CC2,
++      0x0D42, 0x0DA2, 0x0E02, 0x0E62,
++      0x0EE2, 0x0F42, 0x0FA2, 0x1002, /* 32 */
++      0x1062, 0x10C2, 0x1122, 0x1182,
++      0x11E2, 0x1242, 0x12A2, 0x12E2,
++      0x1342, 0x13A2, 0x1402, 0x1442,
++      0x14A2, 0x14E2, 0x1542, 0x1582, /* 48 */
++      0x15E2, 0x1622, 0x1662, 0x16C1,
++      0x1701, 0x1741, 0x1781, 0x17E1,
++      0x1821, 0x1861, 0x18A1, 0x18E1,
++      0x1921, 0x1961, 0x19A1, 0x19E1, /* 64 */
++      0x1A21, 0x1A61, 0x1AA1, 0x1AC1,
++      0x1B01, 0x1B41, 0x1B81, 0x1BA1,
++      0x1BE1, 0x1C21, 0x1C41, 0x1C81,
++      0x1CA1, 0x1CE1, 0x1D01, 0x1D41, /* 80 */
++      0x1D61, 0x1DA1, 0x1DC1, 0x1E01,
++      0x1E21, 0x1E61, 0x1E81, 0x1EA1,
++      0x1EE1, 0x1F01, 0x1F21, 0x1F41,
++      0x1F81, 0x1FA1, 0x1FC1, 0x1FE1, /* 96 */
++      0x2001, 0x2041, 0x2061, 0x2081,
++      0x20A1, 0x20C1, 0x20E1, 0x2101,
++      0x2121, 0x2141, 0x2161, 0x2181,
++      0x21A1, 0x21C1, 0x21E1, 0x2201, /* 112 */
++      0x2221, 0x2241, 0x2261, 0x2281,
++      0x22A1, 0x22C1, 0x22C1, 0x22E1,
++      0x2301, 0x2321, 0x2341, 0x2361,
++      0x2361, 0x2381, 0x23A1, 0x23C1, /* 128 */
++      0x23E1, 0x23E1, 0x2401, 0x2421,
++      0x2441, 0x2441, 0x2461, 0x2481,
++      0x2481, 0x24A1, 0x24C1, 0x24C1,
++      0x24E1, 0x2501, 0x2501, 0x2521, /* 144 */
++      0x2541, 0x2541, 0x2561, 0x2561,
++      0x2581, 0x25A1, 0x25A1, 0x25C1,
++      0x25C1, 0x25E1, 0x2601, 0x2601,
++      0x2621, 0x2621, 0x2641, 0x2641, /* 160 */
++      0x2661, 0x2661, 0x2681, 0x2681,
++      0x26A1, 0x26A1, 0x26C1, 0x26C1,
++      0x26E1, 0x26E1, 0x2701, 0x2701,
++      0x2721, 0x2721, 0x2740, 0x2740, /* 176 */
++      0x2760, 0x2760, 0x2780, 0x2780,
++      0x2780, 0x27A0, 0x27A0, 0x27C0,
++      0x27C0, 0x27E0, 0x27E0, 0x27E0,
++      0x2800, 0x2800, 0x2820, 0x2820, /* 192 */
++      0x2820, 0x2840, 0x2840, 0x2840,
++      0x2860, 0x2860, 0x2880, 0x2880,
++      0x2880, 0x28A0, 0x28A0, 0x28A0,
++      0x28C0, 0x28C0, 0x28C0, 0x28E0, /* 208 */
++      0x28E0, 0x28E0, 0x2900, 0x2900,
++      0x2900, 0x2920, 0x2920, 0x2920,
++      0x2940, 0x2940, 0x2940, 0x2960,
++      0x2960, 0x2960, 0x2960, 0x2980, /* 224 */
++      0x2980, 0x2980, 0x29A0, 0x29A0,
++      0x29A0, 0x29A0, 0x29C0, 0x29C0,
++      0x29C0, 0x29E0, 0x29E0, 0x29E0,
++      0x29E0, 0x2A00, 0x2A00, 0x2A00, /* 240 */
++      0x2A00, 0x2A20, 0x2A20, 0x2A20,
++      0x2A20, 0x2A40, 0x2A40, 0x2A40,
++      0x2A40, 0x2A60, 0x2A60, 0x2A60,
++};
++
++const u16 bcm43xx_ilt_finefreqg[BCM43xx_ILT_FINEFREQG_SIZE] = {
++      0x0089, 0x02E9, 0x0409, 0x04E9, /* 0 */
++      0x05A9, 0x0669, 0x0709, 0x0789,
++      0x0829, 0x08A9, 0x0929, 0x0989,
++      0x0A09, 0x0A69, 0x0AC9, 0x0B29,
++      0x0BA9, 0x0BE9, 0x0C49, 0x0CA9, /* 16 */
++      0x0D09, 0x0D69, 0x0DA9, 0x0E09,
++      0x0E69, 0x0EA9, 0x0F09, 0x0F49,
++      0x0FA9, 0x0FE9, 0x1029, 0x1089,
++      0x10C9, 0x1109, 0x1169, 0x11A9, /* 32 */
++      0x11E9, 0x1229, 0x1289, 0x12C9,
++      0x1309, 0x1349, 0x1389, 0x13C9,
++      0x1409, 0x1449, 0x14A9, 0x14E9,
++      0x1529, 0x1569, 0x15A9, 0x15E9, /* 48 */
++      0x1629, 0x1669, 0x16A9, 0x16E8,
++      0x1728, 0x1768, 0x17A8, 0x17E8,
++      0x1828, 0x1868, 0x18A8, 0x18E8,
++      0x1928, 0x1968, 0x19A8, 0x19E8, /* 64 */
++      0x1A28, 0x1A68, 0x1AA8, 0x1AE8,
++      0x1B28, 0x1B68, 0x1BA8, 0x1BE8,
++      0x1C28, 0x1C68, 0x1CA8, 0x1CE8,
++      0x1D28, 0x1D68, 0x1DC8, 0x1E08, /* 80 */
++      0x1E48, 0x1E88, 0x1EC8, 0x1F08,
++      0x1F48, 0x1F88, 0x1FE8, 0x2028,
++      0x2068, 0x20A8, 0x2108, 0x2148,
++      0x2188, 0x21C8, 0x2228, 0x2268, /* 96 */
++      0x22C8, 0x2308, 0x2348, 0x23A8,
++      0x23E8, 0x2448, 0x24A8, 0x24E8,
++      0x2548, 0x25A8, 0x2608, 0x2668,
++      0x26C8, 0x2728, 0x2787, 0x27E7, /* 112 */
++      0x2847, 0x28C7, 0x2947, 0x29A7,
++      0x2A27, 0x2AC7, 0x2B47, 0x2BE7,
++      0x2CA7, 0x2D67, 0x2E47, 0x2F67,
++      0x3247, 0x3526, 0x3646, 0x3726, /* 128 */
++      0x3806, 0x38A6, 0x3946, 0x39E6,
++      0x3A66, 0x3AE6, 0x3B66, 0x3BC6,
++      0x3C45, 0x3CA5, 0x3D05, 0x3D85,
++      0x3DE5, 0x3E45, 0x3EA5, 0x3EE5, /* 144 */
++      0x3F45, 0x3FA5, 0x4005, 0x4045,
++      0x40A5, 0x40E5, 0x4145, 0x4185,
++      0x41E5, 0x4225, 0x4265, 0x42C5,
++      0x4305, 0x4345, 0x43A5, 0x43E5, /* 160 */
++      0x4424, 0x4464, 0x44C4, 0x4504,
++      0x4544, 0x4584, 0x45C4, 0x4604,
++      0x4644, 0x46A4, 0x46E4, 0x4724,
++      0x4764, 0x47A4, 0x47E4, 0x4824, /* 176 */
++      0x4864, 0x48A4, 0x48E4, 0x4924,
++      0x4964, 0x49A4, 0x49E4, 0x4A24,
++      0x4A64, 0x4AA4, 0x4AE4, 0x4B23,
++      0x4B63, 0x4BA3, 0x4BE3, 0x4C23, /* 192 */
++      0x4C63, 0x4CA3, 0x4CE3, 0x4D23,
++      0x4D63, 0x4DA3, 0x4DE3, 0x4E23,
++      0x4E63, 0x4EA3, 0x4EE3, 0x4F23,
++      0x4F63, 0x4FC3, 0x5003, 0x5043, /* 208 */
++      0x5083, 0x50C3, 0x5103, 0x5143,
++      0x5183, 0x51E2, 0x5222, 0x5262,
++      0x52A2, 0x52E2, 0x5342, 0x5382,
++      0x53C2, 0x5402, 0x5462, 0x54A2, /* 224 */
++      0x5502, 0x5542, 0x55A2, 0x55E2,
++      0x5642, 0x5682, 0x56E2, 0x5722,
++      0x5782, 0x57E1, 0x5841, 0x58A1,
++      0x5901, 0x5961, 0x59C1, 0x5A21, /* 240 */
++      0x5AA1, 0x5B01, 0x5B81, 0x5BE1,
++      0x5C61, 0x5D01, 0x5D80, 0x5E20,
++      0x5EE0, 0x5FA0, 0x6080, 0x61C0,
++};
++
++const u16 bcm43xx_ilt_noisea2[BCM43xx_ILT_NOISEA2_SIZE] = {
++      0x0001, 0x0001, 0x0001, 0xFFFE,
++      0xFFFE, 0x3FFF, 0x1000, 0x0393,
++};
++
++const u16 bcm43xx_ilt_noisea3[BCM43xx_ILT_NOISEA3_SIZE] = {
++      0x4C4C, 0x4C4C, 0x4C4C, 0x2D36,
++      0x4C4C, 0x4C4C, 0x4C4C, 0x2D36,
++};
++
++const u16 bcm43xx_ilt_noiseg1[BCM43xx_ILT_NOISEG1_SIZE] = {
++      0x013C, 0x01F5, 0x031A, 0x0631,
++      0x0001, 0x0001, 0x0001, 0x0001,
++};
++
++const u16 bcm43xx_ilt_noiseg2[BCM43xx_ILT_NOISEG2_SIZE] = {
++      0x5484, 0x3C40, 0x0000, 0x0000,
++      0x0000, 0x0000, 0x0000, 0x0000,
++};
++
++const u16 bcm43xx_ilt_noisescaleg1[BCM43xx_ILT_NOISESCALEG_SIZE] = {
++      0x6C77, 0x5162, 0x3B40, 0x3335, /* 0 */
++      0x2F2D, 0x2A2A, 0x2527, 0x1F21,
++      0x1A1D, 0x1719, 0x1616, 0x1414,
++      0x1414, 0x1400, 0x1414, 0x1614,
++      0x1716, 0x1A19, 0x1F1D, 0x2521, /* 16 */
++      0x2A27, 0x2F2A, 0x332D, 0x3B35,
++      0x5140, 0x6C62, 0x0077,
++};
++
++const u16 bcm43xx_ilt_noisescaleg2[BCM43xx_ILT_NOISESCALEG_SIZE] = {
++      0xD8DD, 0xCBD4, 0xBCC0, 0XB6B7, /* 0 */
++      0xB2B0, 0xADAD, 0xA7A9, 0x9FA1,
++      0x969B, 0x9195, 0x8F8F, 0x8A8A,
++      0x8A8A, 0x8A00, 0x8A8A, 0x8F8A,
++      0x918F, 0x9695, 0x9F9B, 0xA7A1, /* 16 */
++      0xADA9, 0xB2AD, 0xB6B0, 0xBCB7,
++      0xCBC0, 0xD8D4, 0x00DD,
++};
++
++const u16 bcm43xx_ilt_noisescaleg3[BCM43xx_ILT_NOISESCALEG_SIZE] = {
++      0xA4A4, 0xA4A4, 0xA4A4, 0xA4A4, /* 0 */
++      0xA4A4, 0xA4A4, 0xA4A4, 0xA4A4,
++      0xA4A4, 0xA4A4, 0xA4A4, 0xA4A4,
++      0xA4A4, 0xA400, 0xA4A4, 0xA4A4,
++      0xA4A4, 0xA4A4, 0xA4A4, 0xA4A4, /* 16 */
++      0xA4A4, 0xA4A4, 0xA4A4, 0xA4A4,
++      0xA4A4, 0xA4A4, 0x00A4,
++};
++
++const u16 bcm43xx_ilt_sigmasqr1[BCM43xx_ILT_SIGMASQR_SIZE] = {
++      0x007A, 0x0075, 0x0071, 0x006C, /* 0 */
++      0x0067, 0x0063, 0x005E, 0x0059,
++      0x0054, 0x0050, 0x004B, 0x0046,
++      0x0042, 0x003D, 0x003D, 0x003D,
++      0x003D, 0x003D, 0x003D, 0x003D, /* 16 */
++      0x003D, 0x003D, 0x003D, 0x003D,
++      0x003D, 0x003D, 0x0000, 0x003D,
++      0x003D, 0x003D, 0x003D, 0x003D,
++      0x003D, 0x003D, 0x003D, 0x003D, /* 32 */
++      0x003D, 0x003D, 0x003D, 0x003D,
++      0x0042, 0x0046, 0x004B, 0x0050,
++      0x0054, 0x0059, 0x005E, 0x0063,
++      0x0067, 0x006C, 0x0071, 0x0075, /* 48 */
++      0x007A,
++};
++
++const u16 bcm43xx_ilt_sigmasqr2[BCM43xx_ILT_SIGMASQR_SIZE] = {
++      0x00DE, 0x00DC, 0x00DA, 0x00D8, /* 0 */
++      0x00D6, 0x00D4, 0x00D2, 0x00CF,
++      0x00CD, 0x00CA, 0x00C7, 0x00C4,
++      0x00C1, 0x00BE, 0x00BE, 0x00BE,
++      0x00BE, 0x00BE, 0x00BE, 0x00BE, /* 16 */
++      0x00BE, 0x00BE, 0x00BE, 0x00BE,
++      0x00BE, 0x00BE, 0x0000, 0x00BE,
++      0x00BE, 0x00BE, 0x00BE, 0x00BE,
++      0x00BE, 0x00BE, 0x00BE, 0x00BE, /* 32 */
++      0x00BE, 0x00BE, 0x00BE, 0x00BE,
++      0x00C1, 0x00C4, 0x00C7, 0x00CA,
++      0x00CD, 0x00CF, 0x00D2, 0x00D4,
++      0x00D6, 0x00D8, 0x00DA, 0x00DC, /* 48 */
++      0x00DE,
++};
++
++/**** Helper functions to access the device Internal Lookup Tables ****/
++
++void bcm43xx_ilt_write(struct bcm43xx_private *bcm, u16 offset, u16 val)
++{
++      if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_A) {
++              bcm43xx_phy_write(bcm, BCM43xx_PHY_ILT_A_CTRL, offset);
++              mmiowb();
++              bcm43xx_phy_write(bcm, BCM43xx_PHY_ILT_A_DATA1, val);
++      } else {
++              bcm43xx_phy_write(bcm, BCM43xx_PHY_ILT_G_CTRL, offset);
++              mmiowb();
++              bcm43xx_phy_write(bcm, BCM43xx_PHY_ILT_G_DATA1, val);
++      }
++}
++
++u16 bcm43xx_ilt_read(struct bcm43xx_private *bcm, u16 offset)
++{
++      if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_A) {
++              bcm43xx_phy_write(bcm, BCM43xx_PHY_ILT_A_CTRL, offset);
++              return bcm43xx_phy_read(bcm, BCM43xx_PHY_ILT_A_DATA1);
++      } else {
++              bcm43xx_phy_write(bcm, BCM43xx_PHY_ILT_G_CTRL, offset);
++              return bcm43xx_phy_read(bcm, BCM43xx_PHY_ILT_G_DATA1);
++      }
++}
+diff -Nur linux-2.6.16/drivers/net/wireless/bcm43xx-d80211/bcm43xx_ilt.h linux-2.6.16-bcm43xx/drivers/net/wireless/bcm43xx-d80211/bcm43xx_ilt.h
+--- linux-2.6.16/drivers/net/wireless/bcm43xx-d80211/bcm43xx_ilt.h     1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.16-bcm43xx/drivers/net/wireless/bcm43xx-d80211/bcm43xx_ilt.h     2006-03-28 22:16:14.000000000 +0200
+@@ -0,0 +1,32 @@
++#ifndef BCM43xx_ILT_H_
++#define BCM43xx_ILT_H_
++
++#define BCM43xx_ILT_ROTOR_SIZE                53
++extern const u32 bcm43xx_ilt_rotor[BCM43xx_ILT_ROTOR_SIZE];
++#define BCM43xx_ILT_RETARD_SIZE               53
++extern const u32 bcm43xx_ilt_retard[BCM43xx_ILT_RETARD_SIZE];
++#define BCM43xx_ILT_FINEFREQA_SIZE    256
++extern const u16 bcm43xx_ilt_finefreqa[BCM43xx_ILT_FINEFREQA_SIZE];
++#define BCM43xx_ILT_FINEFREQG_SIZE    256
++extern const u16 bcm43xx_ilt_finefreqg[BCM43xx_ILT_FINEFREQG_SIZE];
++#define BCM43xx_ILT_NOISEA2_SIZE      8
++extern const u16 bcm43xx_ilt_noisea2[BCM43xx_ILT_NOISEA2_SIZE];
++#define BCM43xx_ILT_NOISEA3_SIZE      8
++extern const u16 bcm43xx_ilt_noisea3[BCM43xx_ILT_NOISEA3_SIZE];
++#define BCM43xx_ILT_NOISEG1_SIZE      8
++extern const u16 bcm43xx_ilt_noiseg1[BCM43xx_ILT_NOISEG1_SIZE];
++#define BCM43xx_ILT_NOISEG2_SIZE      8
++extern const u16 bcm43xx_ilt_noiseg2[BCM43xx_ILT_NOISEG2_SIZE];
++#define BCM43xx_ILT_NOISESCALEG_SIZE  27
++extern const u16 bcm43xx_ilt_noisescaleg1[BCM43xx_ILT_NOISESCALEG_SIZE];
++extern const u16 bcm43xx_ilt_noisescaleg2[BCM43xx_ILT_NOISESCALEG_SIZE];
++extern const u16 bcm43xx_ilt_noisescaleg3[BCM43xx_ILT_NOISESCALEG_SIZE];
++#define BCM43xx_ILT_SIGMASQR_SIZE     53
++extern const u16 bcm43xx_ilt_sigmasqr1[BCM43xx_ILT_SIGMASQR_SIZE];
++extern const u16 bcm43xx_ilt_sigmasqr2[BCM43xx_ILT_SIGMASQR_SIZE];
++
++
++void bcm43xx_ilt_write(struct bcm43xx_private *bcm, u16 offset, u16 val);
++u16 bcm43xx_ilt_read(struct bcm43xx_private *bcm, u16 offset);
++
++#endif /* BCM43xx_ILT_H_ */
+diff -Nur linux-2.6.16/drivers/net/wireless/bcm43xx-d80211/bcm43xx_leds.c linux-2.6.16-bcm43xx/drivers/net/wireless/bcm43xx-d80211/bcm43xx_leds.c
+--- linux-2.6.16/drivers/net/wireless/bcm43xx-d80211/bcm43xx_leds.c    1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.16-bcm43xx/drivers/net/wireless/bcm43xx-d80211/bcm43xx_leds.c    2006-03-28 22:16:14.000000000 +0200
+@@ -0,0 +1,293 @@
++/*
++
++  Broadcom BCM43xx wireless driver
++
++  Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
++                     Stefano Brivio <st3@riseup.net>
++                     Michael Buesch <mbuesch@freenet.de>
++                     Danny van Dyk <kugelfang@gentoo.org>
++                     Andreas Jaggi <andreas.jaggi@waterwave.ch>
++
++  This program is free software; you can redistribute it and/or modify
++  it under the terms of the GNU General Public License as published by
++  the Free Software Foundation; either version 2 of the License, or
++  (at your option) any later version.
++
++  This program is distributed in the hope that it will be useful,
++  but WITHOUT ANY WARRANTY; without even the implied warranty of
++  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++  GNU General Public License for more details.
++
++  You should have received a copy of the GNU General Public License
++  along with this program; see the file COPYING.  If not, write to
++  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
++  Boston, MA 02110-1301, USA.
++
++*/
++
++#include "bcm43xx_leds.h"
++#include "bcm43xx.h"
++
++#include <asm/bitops.h>
++
++
++static void bcm43xx_led_changestate(struct bcm43xx_led *led)
++{
++      struct bcm43xx_private *bcm = led->bcm;
++      const int index = bcm43xx_led_index(led);
++      const u16 mask = (1 << index);
++      u16 ledctl;
++
++      assert(index >= 0 && index < BCM43xx_NR_LEDS);
++      assert(led->blink_interval);
++      ledctl = bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_CONTROL);
++      ledctl = (ledctl & mask) ? (ledctl & ~mask) : (ledctl | mask);
++      bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_CONTROL, ledctl);
++}
++
++static void bcm43xx_led_blink(unsigned long d)
++{
++      struct bcm43xx_led *led = (struct bcm43xx_led *)d;
++      struct bcm43xx_private *bcm = led->bcm;
++      unsigned long flags;
++
++      bcm43xx_lock_mmio(bcm, flags);
++      if (led->blink_interval) {
++              bcm43xx_led_changestate(led);
++              mod_timer(&led->blink_timer, jiffies + led->blink_interval);
++      }
++      bcm43xx_unlock_mmio(bcm, flags);
++}
++
++static void bcm43xx_led_blink_start(struct bcm43xx_led *led,
++                                  unsigned long interval)
++{
++      if (led->blink_interval)
++              return;
++      led->blink_interval = interval;
++      bcm43xx_led_changestate(led);
++      led->blink_timer.expires = jiffies + interval;
++      add_timer(&led->blink_timer);
++}
++
++static void bcm43xx_led_blink_stop(struct bcm43xx_led *led, int sync)
++{
++      struct bcm43xx_private *bcm = led->bcm;
++      const int index = bcm43xx_led_index(led);
++      u16 ledctl;
++
++      if (!led->blink_interval)
++              return;
++      if (unlikely(sync))
++              del_timer_sync(&led->blink_timer);
++      else
++              del_timer(&led->blink_timer);
++      led->blink_interval = 0;
++
++      /* Make sure the LED is turned off. */
++      assert(index >= 0 && index < BCM43xx_NR_LEDS);
++      ledctl = bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_CONTROL);
++      if (led->activelow)
++              ledctl |= (1 << index);
++      else
++              ledctl &= ~(1 << index);
++      bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_CONTROL, ledctl);
++}
++
++static void bcm43xx_led_init_hardcoded(struct bcm43xx_private *bcm,
++                                     struct bcm43xx_led *led,
++                                     int led_index)
++{
++      /* This function is called, if the behaviour (and activelow)
++       * information for a LED is missing in the SPROM.
++       * We hardcode the behaviour values for various devices here.
++       * Note that the BCM43xx_LED_TEST_XXX behaviour values can
++       * be used to figure out which led is mapped to which index.
++       */
++
++      switch (led_index) {
++      case 0:
++              led->behaviour = BCM43xx_LED_ACTIVITY;
++              if (bcm->board_vendor == PCI_VENDOR_ID_COMPAQ)
++                      led->behaviour = BCM43xx_LED_RADIO_ALL;
++              break;
++      case 1:
++              led->behaviour = BCM43xx_LED_RADIO_B;
++              if (bcm->board_vendor == PCI_VENDOR_ID_ASUSTEK)
++                      led->behaviour = BCM43xx_LED_ASSOC;
++              break;
++      case 2:
++              led->behaviour = BCM43xx_LED_RADIO_A;
++              break;
++      case 3:
++              led->behaviour = BCM43xx_LED_OFF;
++              break;
++      default:
++              assert(0);
++      }
++}
++
++int bcm43xx_leds_init(struct bcm43xx_private *bcm)
++{
++      struct bcm43xx_led *led;
++      u8 sprom[4];
++      int i;
++
++      sprom[0] = bcm->sprom.wl0gpio0;
++      sprom[1] = bcm->sprom.wl0gpio1;
++      sprom[2] = bcm->sprom.wl0gpio2;
++      sprom[3] = bcm->sprom.wl0gpio3;
++
++      for (i = 0; i < BCM43xx_NR_LEDS; i++) {
++              led = &(bcm->leds[i]);
++              led->bcm = bcm;
++              setup_timer(&led->blink_timer,
++                          bcm43xx_led_blink,
++                          (unsigned long)led);
++
++              if (sprom[i] == 0xFF) {
++                      bcm43xx_led_init_hardcoded(bcm, led, i);
++              } else {
++                      led->behaviour = sprom[i] & BCM43xx_LED_BEHAVIOUR;
++                      led->activelow = !!(sprom[i] & BCM43xx_LED_ACTIVELOW);
++              }
++      }
++
++      return 0;
++}
++
++void bcm43xx_leds_exit(struct bcm43xx_private *bcm)
++{
++      struct bcm43xx_led *led;
++      int i;
++
++      for (i = 0; i < BCM43xx_NR_LEDS; i++) {
++              led = &(bcm->leds[i]);
++              bcm43xx_led_blink_stop(led, 1);
++      }
++      bcm43xx_leds_switch_all(bcm, 0);
++}
++
++void bcm43xx_leds_update(struct bcm43xx_private *bcm, int activity)
++{
++      struct bcm43xx_led *led;
++      struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
++      struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
++      const int transferring = (jiffies - bcm->stats.last_tx) < BCM43xx_LED_XFER_THRES;
++      int i, turn_on;
++      unsigned long interval = 0;
++      u16 ledctl;
++
++      ledctl = bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_CONTROL);
++      for (i = 0; i < BCM43xx_NR_LEDS; i++) {
++              led = &(bcm->leds[i]);
++
++              turn_on = 0;
++              switch (led->behaviour) {
++              case BCM43xx_LED_INACTIVE:
++                      continue;
++              case BCM43xx_LED_OFF:
++                      break;
++              case BCM43xx_LED_ON:
++                      turn_on = 1;
++                      break;
++              case BCM43xx_LED_ACTIVITY:
++                      turn_on = activity;
++                      break;
++              case BCM43xx_LED_RADIO_ALL:
++                      turn_on = radio->enabled;
++                      break;
++              case BCM43xx_LED_RADIO_A:
++                      turn_on = (radio->enabled && phy->type == BCM43xx_PHYTYPE_A);
++                      break;
++              case BCM43xx_LED_RADIO_B:
++                      turn_on = (radio->enabled &&
++                                 (phy->type == BCM43xx_PHYTYPE_B ||
++                                  phy->type == BCM43xx_PHYTYPE_G));
++                      break;
++              case BCM43xx_LED_MODE_BG:
++                      if (phy->type == BCM43xx_PHYTYPE_G &&
++                          1/*FIXME: using G rates.*/)
++                              turn_on = 1;
++                      break;
++              case BCM43xx_LED_TRANSFER:
++                      if (transferring)
++                              bcm43xx_led_blink_start(led, BCM43xx_LEDBLINK_MEDIUM);
++                      else
++                              bcm43xx_led_blink_stop(led, 0);
++                      continue;
++              case BCM43xx_LED_APTRANSFER:
++                      if (bcm->iw_mode == IW_MODE_MASTER) {
++                              if (transferring) {
++                                      interval = BCM43xx_LEDBLINK_FAST;
++                                      turn_on = 1;
++                              }
++                      } else {
++                              turn_on = 1;
++                              if (0/*TODO: not assoc*/)
++                                      interval = BCM43xx_LEDBLINK_SLOW;
++                              else if (transferring)
++                                      interval = BCM43xx_LEDBLINK_FAST;
++                              else
++                                      turn_on = 0;
++                      }
++                      if (turn_on)
++                              bcm43xx_led_blink_start(led, interval);
++                      else
++                              bcm43xx_led_blink_stop(led, 0);
++                      continue;
++              case BCM43xx_LED_WEIRD:
++                      //TODO
++                      break;
++              case BCM43xx_LED_ASSOC:
++                      if (1/*bcm->softmac->associated*/)
++                              turn_on = 1;
++                      break;
++#ifdef CONFIG_BCM43XX_DEBUG
++              case BCM43xx_LED_TEST_BLINKSLOW:
++                      bcm43xx_led_blink_start(led, BCM43xx_LEDBLINK_SLOW);
++                      continue;
++              case BCM43xx_LED_TEST_BLINKMEDIUM:
++                      bcm43xx_led_blink_start(led, BCM43xx_LEDBLINK_MEDIUM);
++                      continue;
++              case BCM43xx_LED_TEST_BLINKFAST:
++                      bcm43xx_led_blink_start(led, BCM43xx_LEDBLINK_FAST);
++                      continue;
++#endif /* CONFIG_BCM43XX_DEBUG */
++              default:
++                      assert(0);
++              };
++
++              if (led->activelow)
++                      turn_on = !turn_on;
++              if (turn_on)
++                      ledctl |= (1 << i);
++              else
++                      ledctl &= ~(1 << i);
++      }
++      bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_CONTROL, ledctl);
++}
++
++void bcm43xx_leds_switch_all(struct bcm43xx_private *bcm, int on)
++{
++      struct bcm43xx_led *led;
++      u16 ledctl;
++      int i;
++      int bit_on;
++
++      ledctl = bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_CONTROL);
++      for (i = 0; i < BCM43xx_NR_LEDS; i++) {
++              led = &(bcm->leds[i]);
++              if (led->behaviour == BCM43xx_LED_INACTIVE)
++                      continue;
++              if (on)
++                      bit_on = led->activelow ? 0 : 1;
++              else
++                      bit_on = led->activelow ? 1 : 0;
++              if (bit_on)
++                      ledctl |= (1 << i);
++              else
++                      ledctl &= ~(1 << i);
++      }
++      bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_CONTROL, ledctl);
++}
+diff -Nur linux-2.6.16/drivers/net/wireless/bcm43xx-d80211/bcm43xx_leds.h linux-2.6.16-bcm43xx/drivers/net/wireless/bcm43xx-d80211/bcm43xx_leds.h
+--- linux-2.6.16/drivers/net/wireless/bcm43xx-d80211/bcm43xx_leds.h    1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.16-bcm43xx/drivers/net/wireless/bcm43xx-d80211/bcm43xx_leds.h    2006-03-28 22:16:14.000000000 +0200
+@@ -0,0 +1,56 @@
++#ifndef BCM43xx_LEDS_H_
++#define BCM43xx_LEDS_H_
++
++#include <linux/types.h>
++#include <linux/timer.h>
++
++
++struct bcm43xx_led {
++      u8 behaviour:7;
++      u8 activelow:1;
++
++      struct bcm43xx_private *bcm;
++      struct timer_list blink_timer;
++      unsigned long blink_interval;
++};
++#define bcm43xx_led_index(led)        ((int)((led) - (led)->bcm->leds))
++
++/* Delay between state changes when blinking in jiffies */
++#define BCM43xx_LEDBLINK_SLOW         (HZ / 1)
++#define BCM43xx_LEDBLINK_MEDIUM               (HZ / 4)
++#define BCM43xx_LEDBLINK_FAST         (HZ / 8)
++
++#define BCM43xx_LED_XFER_THRES                (HZ / 100)
++
++#define BCM43xx_LED_BEHAVIOUR         0x7F
++#define BCM43xx_LED_ACTIVELOW         0x80
++enum { /* LED behaviour values */
++      BCM43xx_LED_OFF,
++      BCM43xx_LED_ON,
++      BCM43xx_LED_ACTIVITY,
++      BCM43xx_LED_RADIO_ALL,
++      BCM43xx_LED_RADIO_A,
++      BCM43xx_LED_RADIO_B,
++      BCM43xx_LED_MODE_BG,
++      BCM43xx_LED_TRANSFER,
++      BCM43xx_LED_APTRANSFER,
++      BCM43xx_LED_WEIRD,//FIXME
++      BCM43xx_LED_ASSOC,
++      BCM43xx_LED_INACTIVE,
++
++      /* Behaviour values for testing.
++       * With these values it is easier to figure out
++       * the real behaviour of leds, in case the SPROM
++       * is missing information.
++       */
++      BCM43xx_LED_TEST_BLINKSLOW,
++      BCM43xx_LED_TEST_BLINKMEDIUM,
++      BCM43xx_LED_TEST_BLINKFAST,
++};
++
++int bcm43xx_leds_init(struct bcm43xx_private *bcm);
++void bcm43xx_leds_exit(struct bcm43xx_private *bcm);
++void bcm43xx_leds_update(struct bcm43xx_private *bcm, int activity);
++void bcm43xx_leds_switch_all(struct bcm43xx_private *bcm, int on);
++
++#endif /* BCM43xx_LEDS_H_ */
+diff -Nur linux-2.6.16/drivers/net/wireless/bcm43xx-d80211/bcm43xx_main.c linux-2.6.16-bcm43xx/drivers/net/wireless/bcm43xx-d80211/bcm43xx_main.c
+--- linux-2.6.16/drivers/net/wireless/bcm43xx-d80211/bcm43xx_main.c    1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.16-bcm43xx/drivers/net/wireless/bcm43xx-d80211/bcm43xx_main.c    2006-03-28 22:16:14.000000000 +0200
+@@ -0,0 +1,4491 @@
++/*
++
++  Broadcom BCM43xx wireless driver
++
++  Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
++  Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
++  Copyright (c) 2005, 2006 Michael Buesch <mbuesch@freenet.de>
++  Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
++  Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
++
++  Some parts of the code in this file are derived from the ipw2200
++  driver  Copyright(c) 2003 - 2004 Intel Corporation.
++
++  This program is free software; you can redistribute it and/or modify
++  it under the terms of the GNU General Public License as published by
++  the Free Software Foundation; either version 2 of the License, or
++  (at your option) any later version.
++
++  This program is distributed in the hope that it will be useful,
++  but WITHOUT ANY WARRANTY; without even the implied warranty of
++  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++  GNU General Public License for more details.
++
++  You should have received a copy of the GNU General Public License
++  along with this program; see the file COPYING.  If not, write to
++  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
++  Boston, MA 02110-1301, USA.
++
++*/
++
++#include <linux/delay.h>
++#include <linux/init.h>
++#include <linux/moduleparam.h>
++#include <linux/if_arp.h>
++#include <linux/etherdevice.h>
++#include <linux/version.h>
++#include <linux/firmware.h>
++#include <linux/wireless.h>
++#include <linux/workqueue.h>
++#include <linux/skbuff.h>
++#include <linux/dma-mapping.h>
++#include <net/iw_handler.h>
++
++#include "bcm43xx.h"
++#include "bcm43xx_main.h"
++#include "bcm43xx_debugfs.h"
++#include "bcm43xx_radio.h"
++#include "bcm43xx_phy.h"
++#include "bcm43xx_dma.h"
++#include "bcm43xx_pio.h"
++#include "bcm43xx_power.h"
++#include "bcm43xx_sysfs.h"
++#include "bcm43xx_ethtool.h"
++#include "bcm43xx_xmit.h"
++
++
++MODULE_DESCRIPTION("Broadcom BCM43xx wireless driver");
++MODULE_AUTHOR("Martin Langer");
++MODULE_AUTHOR("Stefano Brivio");
++MODULE_AUTHOR("Michael Buesch");
++MODULE_LICENSE("GPL");
++
++#ifdef CONFIG_BCM947XX
++extern char *nvram_get(char *name);
++#endif
++
++#if defined(CONFIG_BCM43XX_D80211_DMA) && defined(CONFIG_BCM43XX_D80211_PIO)
++static int modparam_pio;
++module_param_named(pio, modparam_pio, int, 0444);
++MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
++#elif defined(CONFIG_BCM43XX_D80211_DMA)
++# define modparam_pio 0
++#elif defined(CONFIG_BCM43XX_D80211_PIO)
++# define modparam_pio 1
++#endif
++
++static int modparam_bad_frames_preempt;
++module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
++MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames Preemption");
++
++static int modparam_short_retry = BCM43xx_DEFAULT_SHORT_RETRY_LIMIT;
++module_param_named(short_retry, modparam_short_retry, int, 0444);
++MODULE_PARM_DESC(short_retry, "Short-Retry-Limit (0 - 15)");
++
++static int modparam_long_retry = BCM43xx_DEFAULT_LONG_RETRY_LIMIT;
++module_param_named(long_retry, modparam_long_retry, int, 0444);
++MODULE_PARM_DESC(long_retry, "Long-Retry-Limit (0 - 15)");
++
++static int modparam_noleds;
++module_param_named(noleds, modparam_noleds, int, 0444);
++MODULE_PARM_DESC(noleds, "Turn off all LED activity");
++
++#ifdef CONFIG_BCM43XX_D80211_DEBUG
++static char modparam_fwpostfix[64];
++module_param_string(fwpostfix, modparam_fwpostfix, 64, 0444);
++MODULE_PARM_DESC(fwpostfix, "Postfix for .fw files. Useful for debugging.");
++#else
++# define modparam_fwpostfix  ""
++#endif /* CONFIG_BCM43XX_D80211_DEBUG*/
++
++
++/* If you want to debug with just a single device, enable this,
++ * where the string is the pci device ID (as given by the kernel's
++ * pci_name function) of the device to be used.
++ */
++//#define DEBUG_SINGLE_DEVICE_ONLY    "0001:11:00.0"
++
++/* If you want to enable printing of each MMIO access, enable this. */
++//#define DEBUG_ENABLE_MMIO_PRINT
++
++/* If you want to enable printing of MMIO access within
++ * ucode/pcm upload, initvals write, enable this.
++ */
++//#define DEBUG_ENABLE_UCODE_MMIO_PRINT
++
++/* If you want to enable printing of PCI Config Space access, enable this */
++//#define DEBUG_ENABLE_PCILOG
++
++
++/* Detailed list maintained at:
++ * http://openfacts.berlios.de/index-en.phtml?title=Bcm43xxDevices
++ */
++static struct pci_device_id bcm43xx_pci_tbl[] = {
++      /* Broadcom 4303 802.11b */
++      { PCI_VENDOR_ID_BROADCOM, 0x4301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
++      /* Broadcom 4307 802.11b */
++      { PCI_VENDOR_ID_BROADCOM, 0x4307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
++      /* Broadcom 4318 802.11b/g */
++      { PCI_VENDOR_ID_BROADCOM, 0x4318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
++      /* Broadcom 4306 802.11b/g */
++      { PCI_VENDOR_ID_BROADCOM, 0x4320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
++      /* Broadcom 4306 802.11a */
++//    { PCI_VENDOR_ID_BROADCOM, 0x4321, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
++      /* Broadcom 4309 802.11a/b/g */
++      { PCI_VENDOR_ID_BROADCOM, 0x4324, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
++      /* Broadcom 43XG 802.11b/g */
++      { PCI_VENDOR_ID_BROADCOM, 0x4325, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
++#ifdef CONFIG_BCM947XX
++      /* SB bus on BCM947xx */
++      { PCI_VENDOR_ID_BROADCOM, 0x0800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
++#endif
++      { 0 },
++};
++MODULE_DEVICE_TABLE(pci, bcm43xx_pci_tbl);
++
++
++static void bcm43xx_ram_write(struct bcm43xx_private *bcm, u16 offset, u32 val)
++{
++      u32 status;
++
++      status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
++      if (!(status & BCM43xx_SBF_XFER_REG_BYTESWAP))
++              val = swab32(val);
++
++      bcm43xx_write32(bcm, BCM43xx_MMIO_RAM_CONTROL, offset);
++      mmiowb();
++      bcm43xx_write32(bcm, BCM43xx_MMIO_RAM_DATA, val);
++}
++
++static inline
++void bcm43xx_shm_control_word(struct bcm43xx_private *bcm,
++                            u16 routing, u16 offset)
++{
++      u32 control;
++
++      /* "offset" is the WORD offset. */
++
++      control = routing;
++      control <<= 16;
++      control |= offset;
++      bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_CONTROL, control);
++}
++
++u32 bcm43xx_shm_read32(struct bcm43xx_private *bcm,
++                     u16 routing, u16 offset)
++{
++      u32 ret;
++
++      if (routing == BCM43xx_SHM_SHARED) {
++              if (offset & 0x0003) {
++                      /* Unaligned access */
++                      bcm43xx_shm_control_word(bcm, routing, offset >> 2);
++                      ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED);
++                      ret <<= 16;
++                      bcm43xx_shm_control_word(bcm, routing, (offset >> 2) + 1);
++                      ret |= bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA);
++
++                      return ret;
++              }
++              offset >>= 2;
++      }
++      bcm43xx_shm_control_word(bcm, routing, offset);
++      ret = bcm43xx_read32(bcm, BCM43xx_MMIO_SHM_DATA);
++
++      return ret;
++}
++
++u16 bcm43xx_shm_read16(struct bcm43xx_private *bcm,
++                     u16 routing, u16 offset)
++{
++      u16 ret;
++
++      if (routing == BCM43xx_SHM_SHARED) {
++              if (offset & 0x0003) {
++                      /* Unaligned access */
++                      bcm43xx_shm_control_word(bcm, routing, offset >> 2);
++                      ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED);
++
++                      return ret;
++              }
++              offset >>= 2;
++      }
++      bcm43xx_shm_control_word(bcm, routing, offset);
++      ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA);
++
++      return ret;
++}
++
++void bcm43xx_shm_write32(struct bcm43xx_private *bcm,
++                       u16 routing, u16 offset,
++                       u32 value)
++{
++      if (routing == BCM43xx_SHM_SHARED) {
++              if (offset & 0x0003) {
++                      /* Unaligned access */
++                      bcm43xx_shm_control_word(bcm, routing, offset >> 2);
++                      mmiowb();
++                      bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
++                                      (value >> 16) & 0xffff);
++                      mmiowb();
++                      bcm43xx_shm_control_word(bcm, routing, (offset >> 2) + 1);
++                      mmiowb();
++                      bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA,
++                                      value & 0xffff);
++                      return;
++              }
++              offset >>= 2;
++      }
++      bcm43xx_shm_control_word(bcm, routing, offset);
++      mmiowb();
++      bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA, value);
++}
++
++void bcm43xx_shm_write16(struct bcm43xx_private *bcm,
++                       u16 routing, u16 offset,
++                       u16 value)
++{
++      if (routing == BCM43xx_SHM_SHARED) {
++              if (offset & 0x0003) {
++                      /* Unaligned access */
++                      bcm43xx_shm_control_word(bcm, routing, offset >> 2);
++                      mmiowb();
++                      bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
++                                      value);
++                      return;
++              }
++              offset >>= 2;
++      }
++      bcm43xx_shm_control_word(bcm, routing, offset);
++      mmiowb();
++      bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA, value);
++}
++
++void bcm43xx_tsf_read(struct bcm43xx_private *bcm, u64 *tsf)
++{
++      /* We need to be careful. As we read the TSF from multiple
++       * registers, we should take care of register overflows.
++       * In theory, the whole tsf read process should be atomic.
++       * We try to be atomic here, by restaring the read process,
++       * if any of the high registers changed (overflew).
++       */
++      if (bcm->current_core->rev >= 3) {
++              u32 low, high, high2;
++
++              do {
++                      high = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
++                      low = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW);
++                      high2 = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
++              } while (unlikely(high != high2));
++
++              *tsf = high;
++              *tsf <<= 32;
++              *tsf |= low;
++      } else {
++              u64 tmp;
++              u16 v0, v1, v2, v3;
++              u16 test1, test2, test3;
++
++              do {
++                      v3 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_3);
++                      v2 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_2);
++                      v1 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_1);
++                      v0 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_0);
++
++                      test3 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_3);
++                      test2 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_2);
++                      test1 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_1);
++              } while (v3 != test3 || v2 != test2 || v1 != test1);
++
++              *tsf = v3;
++              *tsf <<= 48;
++              tmp = v2;
++              tmp <<= 32;
++              *tsf |= tmp;
++              tmp = v1;
++              tmp <<= 16;
++              *tsf |= tmp;
++              *tsf |= v0;
++      }
++}
++
++void bcm43xx_tsf_write(struct bcm43xx_private *bcm, u64 tsf)
++{
++      u32 status;
++
++      status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
++      status |= BCM43xx_SBF_TIME_UPDATE;
++      bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
++      mmiowb();
++
++      /* Be careful with the in-progress timer.
++       * First zero out the low register, so we have a full
++       * register-overflow duration to complete the operation.
++       */
++      if (bcm->current_core->rev >= 3) {
++              u32 lo = (tsf & 0x00000000FFFFFFFFULL);
++              u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
++
++              bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW, 0);
++              mmiowb();
++              bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH, hi);
++              mmiowb();
++              bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW, lo);
++      } else {
++              u16 v0 = (tsf & 0x000000000000FFFFULL);
++              u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
++              u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
++              u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
++
++              bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_0, 0);
++              mmiowb();
++              bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_3, v3);
++              mmiowb();
++              bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_2, v2);
++              mmiowb();
++              bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_1, v1);
++              mmiowb();
++              bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_0, v0);
++      }
++
++      status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
++      status &= ~BCM43xx_SBF_TIME_UPDATE;
++      bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
++}
++
++static
++void bcm43xx_macfilter_set(struct bcm43xx_private *bcm,
++                         u16 offset,
++                         const u8 *mac)
++{
++      u16 data;
++
++      offset |= 0x0020;
++      bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_CONTROL, offset);
++
++      data = mac[0];
++      data |= mac[1] << 8;
++      bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
++      data = mac[2];
++      data |= mac[3] << 8;
++      bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
++      data = mac[4];
++      data |= mac[5] << 8;
++      bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
++}
++
++static void bcm43xx_macfilter_clear(struct bcm43xx_private *bcm,
++                                  u16 offset)
++{
++      const u8 zero_addr[ETH_ALEN] = { 0 };
++
++      bcm43xx_macfilter_set(bcm, offset, zero_addr);
++}
++
++static void bcm43xx_write_mac_bssid_templates(struct bcm43xx_private *bcm)
++{
++      const u8 *mac = (const u8 *)(bcm->net_dev->dev_addr);
++      const u8 *bssid = bcm->bssid;
++      u8 mac_bssid[ETH_ALEN * 2];
++      int i;
++
++      memcpy(mac_bssid, mac, ETH_ALEN);
++      memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
++
++      /* Write our MAC address and BSSID to template ram */
++      for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
++              bcm43xx_ram_write(bcm, 0x20 + i, *((u32 *)(mac_bssid + i)));
++      for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
++              bcm43xx_ram_write(bcm, 0x78 + i, *((u32 *)(mac_bssid + i)));
++      for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
++              bcm43xx_ram_write(bcm, 0x478 + i, *((u32 *)(mac_bssid + i)));
++}
++
++static void bcm43xx_set_slot_time(struct bcm43xx_private *bcm, u16 slot_time)
++{
++      /* slot_time is in usec. */
++      if (bcm43xx_current_phy(bcm)->type != BCM43xx_PHYTYPE_G)
++              return;
++      bcm43xx_write16(bcm, 0x684, 510 + slot_time);
++      bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0010, slot_time);
++}
++
++static void bcm43xx_short_slot_timing_enable(struct bcm43xx_private *bcm)
++{
++      bcm43xx_set_slot_time(bcm, 9);
++      bcm->short_slot = 1;
++}
++
++static void bcm43xx_short_slot_timing_disable(struct bcm43xx_private *bcm)
++{
++      bcm43xx_set_slot_time(bcm, 20);
++      bcm->short_slot = 0;
++}
++
++/* FIXME: To get the MAC-filter working, we need to implement the
++ *        following functions (and rename them :)
++ */
++#if 0
++static void bcm43xx_disassociate(struct bcm43xx_private *bcm)
++{
++      bcm43xx_mac_suspend(bcm);
++      bcm43xx_macfilter_clear(bcm, BCM43xx_MACFILTER_ASSOC);
++
++      bcm43xx_ram_write(bcm, 0x0026, 0x0000);
++      bcm43xx_ram_write(bcm, 0x0028, 0x0000);
++      bcm43xx_ram_write(bcm, 0x007E, 0x0000);
++      bcm43xx_ram_write(bcm, 0x0080, 0x0000);
++      bcm43xx_ram_write(bcm, 0x047E, 0x0000);
++      bcm43xx_ram_write(bcm, 0x0480, 0x0000);
++
++      if (bcm->current_core->rev < 3) {
++              bcm43xx_write16(bcm, 0x0610, 0x8000);
++              bcm43xx_write16(bcm, 0x060E, 0x0000);
++      } else
++              bcm43xx_write32(bcm, 0x0188, 0x80000000);
++
++      bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0004, 0x000003ff);
++
++#if 0
++      if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_G &&
++          ieee80211_is_ofdm_rate(bcm->softmac->txrates.default_rate))
++              bcm43xx_short_slot_timing_enable(bcm);
++#endif
++
++      bcm43xx_mac_enable(bcm);
++}
++
++static void bcm43xx_associate(struct bcm43xx_private *bcm,
++                            const u8 *mac)
++{
++      bcm43xx_mac_suspend(bcm);
++      bcm43xx_macfilter_set(bcm, BCM43xx_MACFILTER_ASSOC, mac);
++      bcm43xx_write_mac_bssid_templates(bcm);
++      bcm43xx_mac_enable(bcm);
++}
++#endif
++
++/* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
++ * Returns the _previously_ enabled IRQ mask.
++ */
++static inline u32 bcm43xx_interrupt_enable(struct bcm43xx_private *bcm, u32 mask)
++{
++      u32 old_mask;
++
++      old_mask = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
++      bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask | mask);
++
++      return old_mask;
++}
++
++/* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
++ * Returns the _previously_ enabled IRQ mask.
++ */
++static inline u32 bcm43xx_interrupt_disable(struct bcm43xx_private *bcm, u32 mask)
++{
++      u32 old_mask;
++
++      old_mask = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
++      bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
++
++      return old_mask;
++}
++
++/* Make sure we don't receive more data from the device. */
++static int bcm43xx_disable_interrupts_sync(struct bcm43xx_private *bcm, u32 *oldstate)
++{
++      u32 old;
++      unsigned long flags;
++
++      bcm43xx_lock_mmio(bcm, flags);
++      if (bcm43xx_is_initializing(bcm) || bcm->shutting_down) {
++              bcm43xx_unlock_mmio(bcm, flags);
++              return -EBUSY;
++      }
++      old = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
++      tasklet_disable(&bcm->isr_tasklet);
++      bcm43xx_unlock_mmio(bcm, flags);
++      if (oldstate)
++              *oldstate = old;
++
++      return 0;
++}
++
++static int bcm43xx_read_radioinfo(struct bcm43xx_private *bcm)
++{
++      struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
++      struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
++      u32 radio_id;
++      u16 manufact;
++      u16 version;
++      u8 revision;
++      s8 i;
++
++      if (bcm->chip_id == 0x4317) {
++              if (bcm->chip_rev == 0x00)
++                      radio_id = 0x3205017F;
++              else if (bcm->chip_rev == 0x01)
++                      radio_id = 0x4205017F;
++              else
++                      radio_id = 0x5205017F;
++      } else {
++              bcm43xx_write16(bcm, BCM43xx_MMIO_RADIO_CONTROL, BCM43xx_RADIOCTL_ID);
++              radio_id = bcm43xx_read16(bcm, BCM43xx_MMIO_RADIO_DATA_HIGH);
++              radio_id <<= 16;
++              bcm43xx_write16(bcm, BCM43xx_MMIO_RADIO_CONTROL, BCM43xx_RADIOCTL_ID);
++              radio_id |= bcm43xx_read16(bcm, BCM43xx_MMIO_RADIO_DATA_LOW);
++      }
++
++      manufact = (radio_id & 0x00000FFF);
++      version = (radio_id & 0x0FFFF000) >> 12;
++      revision = (radio_id & 0xF0000000) >> 28;
++
++      dprintk(KERN_INFO PFX "Detected Radio: ID: %x (Manuf: %x Ver: %x Rev: %x)\n",
++              radio_id, manufact, version, revision);
++
++      switch (phy->type) {
++      case BCM43xx_PHYTYPE_A:
++              if ((version != 0x2060) || (revision != 1) || (manufact != 0x17f))
++                      goto err_unsupported_radio;
++              break;
++      case BCM43xx_PHYTYPE_B:
++              if ((version & 0xFFF0) != 0x2050)
++                      goto err_unsupported_radio;
++              break;
++      case BCM43xx_PHYTYPE_G:
++              if (version != 0x2050)
++                      goto err_unsupported_radio;
++              break;
++      }
++
++      radio->manufact = manufact;
++      radio->version = version;
++      radio->revision = revision;
++
++      /* Set default attenuation values. */
++      radio->baseband_atten = bcm43xx_default_baseband_attenuation(bcm);
++      radio->radio_atten = bcm43xx_default_radio_attenuation(bcm);
++      radio->txctl1 = bcm43xx_default_txctl1(bcm);
++      radio->txctl2 = 0xFFFF;
++      radio->power_level = ~0;
++
++      /* Initialize the in-memory nrssi Lookup Table. */
++      for (i = 0; i < 64; i++)
++              radio->nrssi_lt[i] = i;
++
++      return 0;
++
++err_unsupported_radio:
++      printk(KERN_ERR PFX "Unsupported Radio connected to the PHY!\n");
++      return -ENODEV;
++}
++
++static inline u8 bcm43xx_crc8(u8 crc, u8 data)
++{
++      static const u8 t[] = {
++              0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
++              0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
++              0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
++              0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
++              0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
++              0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
++              0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
++              0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
++              0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
++              0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
++              0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
++              0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
++              0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
++              0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
++              0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
++              0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
++              0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
++              0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
++              0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
++              0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
++              0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
++              0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
++              0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
++              0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
++              0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
++              0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
++              0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
++              0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
++              0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
++              0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
++              0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
++              0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F,
++      };
++      return t[crc ^ data];
++}
++
++static u8 bcm43xx_sprom_crc(const u16 *sprom)
++{
++      int word;
++      u8 crc = 0xFF;
++
++      for (word = 0; word < BCM43xx_SPROM_SIZE - 1; word++) {
++              crc = bcm43xx_crc8(crc, sprom[word] & 0x00FF);
++              crc = bcm43xx_crc8(crc, (sprom[word] & 0xFF00) >> 8);
++      }
++      crc = bcm43xx_crc8(crc, sprom[BCM43xx_SPROM_VERSION] & 0x00FF);
++      crc ^= 0xFF;
++
++      return crc;
++}
++
++int bcm43xx_sprom_read(struct bcm43xx_private *bcm, u16 *sprom)
++{
++      int i;
++      u8 crc, expected_crc;
++
++      for (i = 0; i < BCM43xx_SPROM_SIZE; i++)
++              sprom[i] = bcm43xx_read16(bcm, BCM43xx_SPROM_BASE + (i * 2));
++      /* CRC-8 check. */
++      crc = bcm43xx_sprom_crc(sprom);
++      expected_crc = (sprom[BCM43xx_SPROM_VERSION] & 0xFF00) >> 8;
++      if (crc != expected_crc) {
++              printk(KERN_WARNING PFX "WARNING: Invalid SPROM checksum "
++                                      "(0x%02X, expected: 0x%02X)\n",
++                     crc, expected_crc);
++              return -EINVAL;
++      }
++
++      return 0;
++}
++
++int bcm43xx_sprom_write(struct bcm43xx_private *bcm, const u16 *sprom)
++{
++      int i, err;
++      u8 crc, expected_crc;
++      u32 spromctl;
++
++      /* CRC-8 validation of the input data. */
++      crc = bcm43xx_sprom_crc(sprom);
++      expected_crc = (sprom[BCM43xx_SPROM_VERSION] & 0xFF00) >> 8;
++      if (crc != expected_crc) {
++              printk(KERN_ERR PFX "SPROM input data: Invalid CRC\n");
++              return -EINVAL;
++      }
++
++      printk(KERN_INFO PFX "Writing SPROM. Do NOT turn off the power! Please stand by...\n");
++      err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_SPROMCTL, &spromctl);
++      if (err)
++              goto err_ctlreg;
++      spromctl |= 0x10; /* SPROM WRITE enable. */
++      bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_SPROMCTL, spromctl);
++      if (err)
++              goto err_ctlreg;
++      /* We must burn lots of CPU cycles here, but that does not
++       * really matter as one does not write the SPROM every other minute...
++       */
++      printk(KERN_INFO PFX "[ 0%%");
++      mdelay(500);
++      for (i = 0; i < BCM43xx_SPROM_SIZE; i++) {
++              if (i == 16)
++                      printk("25%%");
++              else if (i == 32)
++                      printk("50%%");
++              else if (i == 48)
++                      printk("75%%");
++              else if (i % 2)
++                      printk(".");
++              bcm43xx_write16(bcm, BCM43xx_SPROM_BASE + (i * 2), sprom[i]);
++              mmiowb();
++              mdelay(20);
++      }
++      spromctl &= ~0x10; /* SPROM WRITE enable. */
++      bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_SPROMCTL, spromctl);
++      if (err)
++              goto err_ctlreg;
++      mdelay(500);
++      printk("100%% ]\n");
++      printk(KERN_INFO PFX "SPROM written.\n");
++      bcm43xx_controller_restart(bcm, "SPROM update");
++
++      return 0;
++err_ctlreg:
++      printk(KERN_ERR PFX "Could not access SPROM control register.\n");
++      return -ENODEV;
++}
++
++static int bcm43xx_sprom_extract(struct bcm43xx_private *bcm)
++{
++      u16 value;
++      u16 *sprom;
++#ifdef CONFIG_BCM947XX
++      char *c;
++#endif
++
++      sprom = kzalloc(BCM43xx_SPROM_SIZE * sizeof(u16),
++                      GFP_KERNEL);
++      if (!sprom) {
++              printk(KERN_ERR PFX "sprom_extract OOM\n");
++              return -ENOMEM;
++      }
++#ifdef CONFIG_BCM947XX
++      sprom[BCM43xx_SPROM_BOARDFLAGS2] = atoi(nvram_get("boardflags2"));
++      sprom[BCM43xx_SPROM_BOARDFLAGS] = atoi(nvram_get("boardflags"));
++
++      if ((c = nvram_get("il0macaddr")) != NULL)
++              e_aton(c, (char *) &(sprom[BCM43xx_SPROM_IL0MACADDR]));
++
++      if ((c = nvram_get("et1macaddr")) != NULL)
++              e_aton(c, (char *) &(sprom[BCM43xx_SPROM_ET1MACADDR]));
++
++      sprom[BCM43xx_SPROM_PA0B0] = atoi(nvram_get("pa0b0"));
++      sprom[BCM43xx_SPROM_PA0B1] = atoi(nvram_get("pa0b1"));
++      sprom[BCM43xx_SPROM_PA0B2] = atoi(nvram_get("pa0b2"));
++
++      sprom[BCM43xx_SPROM_PA1B0] = atoi(nvram_get("pa1b0"));
++      sprom[BCM43xx_SPROM_PA1B1] = atoi(nvram_get("pa1b1"));
++      sprom[BCM43xx_SPROM_PA1B2] = atoi(nvram_get("pa1b2"));
++
++      sprom[BCM43xx_SPROM_BOARDREV] = atoi(nvram_get("boardrev"));
++#else
++      bcm43xx_sprom_read(bcm, sprom);
++#endif
++
++      /* boardflags2 */
++      value = sprom[BCM43xx_SPROM_BOARDFLAGS2];
++      bcm->sprom.boardflags2 = value;
++
++      /* il0macaddr */
++      value = sprom[BCM43xx_SPROM_IL0MACADDR + 0];
++      *(((u16 *)bcm->sprom.il0macaddr) + 0) = cpu_to_be16(value);
++      value = sprom[BCM43xx_SPROM_IL0MACADDR + 1];
++      *(((u16 *)bcm->sprom.il0macaddr) + 1) = cpu_to_be16(value);
++      value = sprom[BCM43xx_SPROM_IL0MACADDR + 2];
++      *(((u16 *)bcm->sprom.il0macaddr) + 2) = cpu_to_be16(value);
++
++      /* et0macaddr */
++      value = sprom[BCM43xx_SPROM_ET0MACADDR + 0];
++      *(((u16 *)bcm->sprom.et0macaddr) + 0) = cpu_to_be16(value);
++      value = sprom[BCM43xx_SPROM_ET0MACADDR + 1];
++      *(((u16 *)bcm->sprom.et0macaddr) + 1) = cpu_to_be16(value);
++      value = sprom[BCM43xx_SPROM_ET0MACADDR + 2];
++      *(((u16 *)bcm->sprom.et0macaddr) + 2) = cpu_to_be16(value);
++
++      /* et1macaddr */
++      value = sprom[BCM43xx_SPROM_ET1MACADDR + 0];
++      *(((u16 *)bcm->sprom.et1macaddr) + 0) = cpu_to_be16(value);
++      value = sprom[BCM43xx_SPROM_ET1MACADDR + 1];
++      *(((u16 *)bcm->sprom.et1macaddr) + 1) = cpu_to_be16(value);
++      value = sprom[BCM43xx_SPROM_ET1MACADDR + 2];
++      *(((u16 *)bcm->sprom.et1macaddr) + 2) = cpu_to_be16(value);
++
++      /* ethernet phy settings */
++      value = sprom[BCM43xx_SPROM_ETHPHY];
++      bcm->sprom.et0phyaddr = (value & 0x001F);
++      bcm->sprom.et1phyaddr = (value & 0x03E0) >> 5;
++      bcm->sprom.et0mdcport = (value & (1 << 14)) >> 14;
++      bcm->sprom.et1mdcport = (value & (1 << 15)) >> 15;
++
++      /* boardrev, antennas, locale */
++      value = sprom[BCM43xx_SPROM_BOARDREV];
++      bcm->sprom.boardrev = (value & 0x00FF);
++      bcm->sprom.locale = (value & 0x0F00) >> 8;
++      bcm->sprom.antennas_aphy = (value & 0x3000) >> 12;
++      bcm->sprom.antennas_bgphy = (value & 0xC000) >> 14;
++
++      /* pa0b* */
++      value = sprom[BCM43xx_SPROM_PA0B0];
++      bcm->sprom.pa0b0 = value;
++      value = sprom[BCM43xx_SPROM_PA0B1];
++      bcm->sprom.pa0b1 = value;
++      value = sprom[BCM43xx_SPROM_PA0B2];
++      bcm->sprom.pa0b2 = value;
++
++      /* wl0gpio* */
++      value = sprom[BCM43xx_SPROM_WL0GPIO0];
++      if (value == 0x0000)
++              value = 0xFFFF;
++      bcm->sprom.wl0gpio0 = value & 0x00FF;
++      bcm->sprom.wl0gpio1 = (value & 0xFF00) >> 8;
++      value = sprom[BCM43xx_SPROM_WL0GPIO2];
++      if (value == 0x0000)
++              value = 0xFFFF;
++      bcm->sprom.wl0gpio2 = value & 0x00FF;
++      bcm->sprom.wl0gpio3 = (value & 0xFF00) >> 8;
++
++      /* maxpower */
++      value = sprom[BCM43xx_SPROM_MAXPWR];
++      bcm->sprom.maxpower_aphy = (value & 0xFF00) >> 8;
++      bcm->sprom.maxpower_bgphy = value & 0x00FF;
++
++      /* pa1b* */
++      value = sprom[BCM43xx_SPROM_PA1B0];
++      bcm->sprom.pa1b0 = value;
++      value = sprom[BCM43xx_SPROM_PA1B1];
++      bcm->sprom.pa1b1 = value;
++      value = sprom[BCM43xx_SPROM_PA1B2];
++      bcm->sprom.pa1b2 = value;
++
++      /* idle tssi target */
++      value = sprom[BCM43xx_SPROM_IDL_TSSI_TGT];
++      bcm->sprom.idle_tssi_tgt_aphy = value & 0x00FF;
++      bcm->sprom.idle_tssi_tgt_bgphy = (value & 0xFF00) >> 8;
++
++      /* boardflags */
++      value = sprom[BCM43xx_SPROM_BOARDFLAGS];
++      if (value == 0xFFFF)
++              value = 0x0000;
++      bcm->sprom.boardflags = value;
++      /* boardflags workarounds */
++      if (bcm->board_vendor == PCI_VENDOR_ID_DELL &&
++          bcm->chip_id == 0x4301 &&
++          bcm->board_revision == 0x74)
++              bcm->sprom.boardflags |= BCM43xx_BFL_BTCOEXIST;
++      if (bcm->board_vendor == PCI_VENDOR_ID_APPLE &&
++          bcm->board_type == 0x4E &&
++          bcm->board_revision > 0x40)
++              bcm->sprom.boardflags |= BCM43xx_BFL_PACTRL;
++
++      /* antenna gain */
++      value = sprom[BCM43xx_SPROM_ANTENNA_GAIN];
++      if (value == 0x0000 || value == 0xFFFF)
++              value = 0x0202;
++      /* convert values to Q5.2 */
++      bcm->sprom.antennagain_aphy = ((value & 0xFF00) >> 8) * 4;
++      bcm->sprom.antennagain_bgphy = (value & 0x00FF) * 4;
++
++      kfree(sprom);
++
++      return 0;
++}
++
++/* DummyTransmission function, as documented on 
++ * http://bcm-specs.sipsolutions.net/DummyTransmission
++ */
++void bcm43xx_dummy_transmission(struct bcm43xx_private *bcm)
++{
++      struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
++      struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
++      unsigned int i, max_loop;
++      u16 value = 0;
++      u32 buffer[5] = {
++              0x00000000,
++              0x0000D400,
++              0x00000000,
++              0x00000001,
++              0x00000000,
++      };
++
++      switch (phy->type) {
++      case BCM43xx_PHYTYPE_A:
++              max_loop = 0x1E;
++              buffer[0] = 0xCC010200;
++              break;
++      case BCM43xx_PHYTYPE_B:
++      case BCM43xx_PHYTYPE_G:
++              max_loop = 0xFA;
++              buffer[0] = 0x6E840B00; 
++              break;
++      default:
++              assert(0);
++              return;
++      }
++
++      for (i = 0; i < 5; i++)
++              bcm43xx_ram_write(bcm, i * 4, buffer[i]);
++
++      bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
++
++      bcm43xx_write16(bcm, 0x0568, 0x0000);
++      bcm43xx_write16(bcm, 0x07C0, 0x0000);
++      bcm43xx_write16(bcm, 0x050C, ((phy->type == BCM43xx_PHYTYPE_A) ? 1 : 0));
++      bcm43xx_write16(bcm, 0x0508, 0x0000);
++      bcm43xx_write16(bcm, 0x050A, 0x0000);
++      bcm43xx_write16(bcm, 0x054C, 0x0000);
++      bcm43xx_write16(bcm, 0x056A, 0x0014);
++      bcm43xx_write16(bcm, 0x0568, 0x0826);
++      bcm43xx_write16(bcm, 0x0500, 0x0000);
++      bcm43xx_write16(bcm, 0x0502, 0x0030);
++
++      if (radio->version == 0x2050 && radio->revision <= 0x5)
++              bcm43xx_radio_write16(bcm, 0x0051, 0x0017);
++      for (i = 0x00; i < max_loop; i++) {
++              value = bcm43xx_read16(bcm, 0x050E);
++              if (value & 0x0080)
++                      break;
++              udelay(10);
++      }
++      for (i = 0x00; i < 0x0A; i++) {
++              value = bcm43xx_read16(bcm, 0x050E);
++              if (value & 0x0400)
++                      break;
++              udelay(10);
++      }
++      for (i = 0x00; i < 0x0A; i++) {
++              value = bcm43xx_read16(bcm, 0x0690);
++              if (!(value & 0x0100))
++                      break;
++              udelay(10);
++      }
++      if (radio->version == 0x2050 && radio->revision <= 0x5)
++              bcm43xx_radio_write16(bcm, 0x0051, 0x0037);
++}
++
++static void key_write(struct bcm43xx_private *bcm,
++                    u8 index, u8 algorithm, const u16 *key)
++{
++      unsigned int i, basic_wep = 0;
++      u32 offset;
++      u16 value;
++ 
++      /* Write associated key information */
++      bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x100 + (index * 2),
++                          ((index << 4) | (algorithm & 0x0F)));
++ 
++      /* The first 4 WEP keys need extra love */
++      if (((algorithm == BCM43xx_SEC_ALGO_WEP) ||
++          (algorithm == BCM43xx_SEC_ALGO_WEP104)) && (index < 4))
++              basic_wep = 1;
++ 
++      /* Write key payload, 8 little endian words */
++      offset = bcm->security_offset + (index * BCM43xx_SEC_KEYSIZE);
++      for (i = 0; i < (BCM43xx_SEC_KEYSIZE / sizeof(u16)); i++) {
++              value = cpu_to_le16(key[i]);
++              bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
++                                  offset + (i * 2), value);
++ 
++              if (!basic_wep)
++                      continue;
++ 
++              bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
++                                  offset + (i * 2) + 4 * BCM43xx_SEC_KEYSIZE,
++                                  value);
++      }
++}
++
++static void keymac_write(struct bcm43xx_private *bcm,
++                       u8 index, const u32 *addr)
++{
++      /* for keys 0-3 there is no associated mac address */
++      if (index < 4)
++              return;
++
++      index -= 4;
++      if (bcm->current_core->rev >= 5) {
++              bcm43xx_shm_write32(bcm,
++                                  BCM43xx_SHM_HWMAC,
++                                  index * 2,
++                                  cpu_to_be32(*addr));
++              bcm43xx_shm_write16(bcm,
++                                  BCM43xx_SHM_HWMAC,
++                                  (index * 2) + 1,
++                                  cpu_to_be16(*((u16 *)(addr + 1))));
++      } else {
++              if (index < 8) {
++                      TODO(); /* Put them in the macaddress filter */
++              } else {
++                      TODO();
++                      /* Put them BCM43xx_SHM_SHARED, stating index 0x0120.
++                         Keep in mind to update the count of keymacs in 0x003E as well! */
++              }
++      }
++}
++
++static int bcm43xx_key_write(struct bcm43xx_private *bcm,
++                           u8 index, u8 algorithm,
++                           const u8 *_key, int key_len,
++                           const u8 *mac_addr)
++{
++      u8 key[BCM43xx_SEC_KEYSIZE] = { 0 };
++
++      if (index >= ARRAY_SIZE(bcm->key))
++              return -EINVAL;
++      if (key_len > ARRAY_SIZE(key))
++              return -EINVAL;
++      if (algorithm < 1 || algorithm > 5)
++              return -EINVAL;
++
++      memcpy(key, _key, key_len);
++      key_write(bcm, index, algorithm, (const u16 *)key);
++      keymac_write(bcm, index, (const u32 *)mac_addr);
++
++      bcm->key[index].algorithm = algorithm;
++
++      return 0;
++}
++
++static void bcm43xx_clear_keys(struct bcm43xx_private *bcm)
++{
++      static const u32 zero_mac[2] = { 0 };
++      unsigned int i,j, nr_keys = 54;
++      u16 offset;
++
++      if (bcm->current_core->rev < 5)
++              nr_keys = 16;
++      assert(nr_keys <= ARRAY_SIZE(bcm->key));
++
++      for (i = 0; i < nr_keys; i++) {
++              bcm->key[i].enabled = 0;
++              /* returns for i < 4 immediately */
++              keymac_write(bcm, i, zero_mac);
++              bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
++                                  0x100 + (i * 2), 0x0000);
++              for (j = 0; j < 8; j++) {
++                      offset = bcm->security_offset + (j * 4) + (i * BCM43xx_SEC_KEYSIZE);
++                      bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
++                                          offset, 0x0000);
++              }
++      }
++      dprintk(KERN_INFO PFX "Keys cleared\n");
++}
++
++/* Lowlevel core-switch function. This is only to be used in
++ * bcm43xx_switch_core() and bcm43xx_probe_cores()
++ */
++static int _switch_core(struct bcm43xx_private *bcm, int core)
++{
++      int err;
++      int attempts = 0;
++      u32 current_core;
++
++      assert(core >= 0);
++      while (1) {
++              err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_ACTIVE_CORE,
++                                               (core * 0x1000) + 0x18000000);
++              if (unlikely(err))
++                      goto error;
++              err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_ACTIVE_CORE,
++                                              &current_core);
++              if (unlikely(err))
++                      goto error;
++              current_core = (current_core - 0x18000000) / 0x1000;
++              if (current_core == core)
++                      break;
++
++              if (unlikely(attempts++ > BCM43xx_SWITCH_CORE_MAX_RETRIES))
++                      goto error;
++              udelay(10);
++      }
++#ifdef CONFIG_BCM947XX
++      if (bcm->pci_dev->bus->number == 0)
++              bcm->current_core_offset = 0x1000 * core;
++      else
++              bcm->current_core_offset = 0;
++#endif
++
++      return 0;
++error:
++      printk(KERN_ERR PFX "Failed to switch to core %d\n", core);
++      return -ENODEV;
++}
++
++int bcm43xx_switch_core(struct bcm43xx_private *bcm, struct bcm43xx_coreinfo *new_core)
++{
++      int err;
++
++      if (unlikely(!new_core))
++              return 0;
++      if (!new_core->available)
++              return -ENODEV;
++      if (bcm->current_core == new_core)
++              return 0;
++      err = _switch_core(bcm, new_core->index);
++      if (unlikely(err))
++              goto out;
++
++      bcm->current_core = new_core;
++      bcm->current_80211_core_idx = -1;
++      if (new_core->id == BCM43xx_COREID_80211)
++              bcm->current_80211_core_idx = (int)(new_core - &(bcm->core_80211[0]));
++
++out:
++      return err;
++}
++
++static int bcm43xx_core_enabled(struct bcm43xx_private *bcm)
++{
++      u32 value;
++
++      value = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
++      value &= BCM43xx_SBTMSTATELOW_CLOCK | BCM43xx_SBTMSTATELOW_RESET
++               | BCM43xx_SBTMSTATELOW_REJECT;
++
++      return (value == BCM43xx_SBTMSTATELOW_CLOCK);
++}
++
++/* disable current core */
++static int bcm43xx_core_disable(struct bcm43xx_private *bcm, u32 core_flags)
++{
++      u32 sbtmstatelow;
++      u32 sbtmstatehigh;
++      int i;
++
++      /* fetch sbtmstatelow from core information registers */
++      sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
++
++      /* core is already in reset */
++      if (sbtmstatelow & BCM43xx_SBTMSTATELOW_RESET)
++              goto out;
++
++      if (sbtmstatelow & BCM43xx_SBTMSTATELOW_CLOCK) {
++              sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
++                             BCM43xx_SBTMSTATELOW_REJECT;
++              bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
++
++              for (i = 0; i < 1000; i++) {
++                      sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
++                      if (sbtmstatelow & BCM43xx_SBTMSTATELOW_REJECT) {
++                              i = -1;
++                              break;
++                      }
++                      udelay(10);
++              }
++              if (i != -1) {
++                      printk(KERN_ERR PFX "Error: core_disable() REJECT timeout!\n");
++                      return -EBUSY;
++              }
++
++              for (i = 0; i < 1000; i++) {
++                      sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
++                      if (!(sbtmstatehigh & BCM43xx_SBTMSTATEHIGH_BUSY)) {
++                              i = -1;
++                              break;
++                      }
++                      udelay(10);
++              }
++              if (i != -1) {
++                      printk(KERN_ERR PFX "Error: core_disable() BUSY timeout!\n");
++                      return -EBUSY;
++              }
++
++              sbtmstatelow = BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
++                             BCM43xx_SBTMSTATELOW_REJECT |
++                             BCM43xx_SBTMSTATELOW_RESET |
++                             BCM43xx_SBTMSTATELOW_CLOCK |
++                             core_flags;
++              bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
++              udelay(10);
++      }
++
++      sbtmstatelow = BCM43xx_SBTMSTATELOW_RESET |
++                     BCM43xx_SBTMSTATELOW_REJECT |
++                     core_flags;
++      bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
++
++out:
++      bcm->current_core->enabled = 0;
++
++      return 0;
++}
++
++/* enable (reset) current core */
++static int bcm43xx_core_enable(struct bcm43xx_private *bcm, u32 core_flags)
++{
++      u32 sbtmstatelow;
++      u32 sbtmstatehigh;
++      u32 sbimstate;
++      int err;
++
++      err = bcm43xx_core_disable(bcm, core_flags);
++      if (err)
++              goto out;
++
++      sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
++                     BCM43xx_SBTMSTATELOW_RESET |
++                     BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
++                     core_flags;
++      bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
++      udelay(1);
++
++      sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
++      if (sbtmstatehigh & BCM43xx_SBTMSTATEHIGH_SERROR) {
++              sbtmstatehigh = 0x00000000;
++              bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATEHIGH, sbtmstatehigh);
++      }
++
++      sbimstate = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMSTATE);
++      if (sbimstate & (BCM43xx_SBIMSTATE_IB_ERROR | BCM43xx_SBIMSTATE_TIMEOUT)) {
++              sbimstate &= ~(BCM43xx_SBIMSTATE_IB_ERROR | BCM43xx_SBIMSTATE_TIMEOUT);
++              bcm43xx_write32(bcm, BCM43xx_CIR_SBIMSTATE, sbimstate);
++      }
++
++      sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
++                     BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
++                     core_flags;
++      bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
++      udelay(1);
++
++      sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK | core_flags;
++      bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
++      udelay(1);
++
++      bcm->current_core->enabled = 1;
++      assert(err == 0);
++out:
++      return err;
++}
++
++/* http://bcm-specs.sipsolutions.net/80211CoreReset */
++void bcm43xx_wireless_core_reset(struct bcm43xx_private *bcm, int connect_phy)
++{
++      u32 flags = 0x00040000;
++
++      if ((bcm43xx_core_enabled(bcm)) &&
++          !bcm43xx_using_pio(bcm)) {
++//FIXME: Do we _really_ want #ifndef CONFIG_BCM947XX here?
++#ifndef CONFIG_BCM947XX
++              /* reset all used DMA controllers. */
++              bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA1_BASE);
++              bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA2_BASE);
++              bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA3_BASE);
++              bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA4_BASE);
++              bcm43xx_dmacontroller_rx_reset(bcm, BCM43xx_MMIO_DMA1_BASE);
++              if (bcm->current_core->rev < 5)
++                      bcm43xx_dmacontroller_rx_reset(bcm, BCM43xx_MMIO_DMA4_BASE);
++#endif
++      }
++      if (bcm->shutting_down) {
++              bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
++                              bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
++                              & ~(BCM43xx_SBF_MAC_ENABLED | 0x00000002));
++      } else {
++              if (connect_phy)
++                      flags |= 0x20000000;
++              bcm43xx_phy_connect(bcm, connect_phy);
++              bcm43xx_core_enable(bcm, flags);
++              bcm43xx_write16(bcm, 0x03E6, 0x0000);
++              bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
++                              bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
++                              | BCM43xx_SBF_400);
++      }
++}
++
++static void bcm43xx_wireless_core_disable(struct bcm43xx_private *bcm)
++{
++      bcm43xx_radio_turn_off(bcm);
++      bcm43xx_write16(bcm, 0x03E6, 0x00F4);
++      bcm43xx_core_disable(bcm, 0);
++}
++
++/* Mark the current 80211 core inactive.
++ * "active_80211_core" is the other 80211 core, which is used.
++ */
++static int bcm43xx_wireless_core_mark_inactive(struct bcm43xx_private *bcm,
++                                             struct bcm43xx_coreinfo *active_80211_core)
++{
++      u32 sbtmstatelow;
++      struct bcm43xx_coreinfo *old_core;
++      int err = 0;
++
++      bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
++      bcm43xx_radio_turn_off(bcm);
++      sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
++      sbtmstatelow &= ~0x200a0000;
++      sbtmstatelow |= 0xa0000;
++      bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
++      udelay(1);
++      sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
++      sbtmstatelow &= ~0xa0000;
++      sbtmstatelow |= 0x80000;
++      bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
++      udelay(1);
++
++      if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_G) {
++              old_core = bcm->current_core;
++              err = bcm43xx_switch_core(bcm, active_80211_core);
++              if (err)
++                      goto out;
++              sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
++              sbtmstatelow &= ~0x20000000;
++              sbtmstatelow |= 0x20000000;
++              bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
++              err = bcm43xx_switch_core(bcm, old_core);
++      }
++
++out:
++      return err;
++}
++
++static void handle_irq_transmit_status(struct bcm43xx_private *bcm)
++{
++      u32 v0, v1;
++      u16 tmp;
++      struct bcm43xx_xmitstatus stat;
++
++      while (1) {
++              v0 = bcm43xx_read32(bcm, BCM43xx_MMIO_XMITSTAT_0);
++              if (!v0)
++                      break;
++              v1 = bcm43xx_read32(bcm, BCM43xx_MMIO_XMITSTAT_1);
++
++              stat.cookie = (v0 >> 16) & 0x0000FFFF;
++              tmp = (u16)((v0 & 0xFFF0) | ((v0 & 0xF) >> 1));
++              stat.flags = tmp & 0xFF;
++              stat.cnt1 = (tmp & 0x0F00) >> 8;
++              stat.cnt2 = (tmp & 0xF000) >> 12;
++              stat.seq = (u16)(v1 & 0xFFFF);
++              stat.unknown = (u16)((v1 >> 16) & 0xFF);
++
++              bcm43xx_debugfs_log_txstat(bcm, &stat);
++
++              if (stat.flags & BCM43xx_TXSTAT_FLAG_IGNORE)
++                      continue;
++              if (!(stat.flags & BCM43xx_TXSTAT_FLAG_ACK))
++                      bcm->ieee_stats.dot11ACKFailureCount++;
++              //TODO: There are more (unknown) flags to test. see bcm43xx_main.h
++
++              if (bcm43xx_using_pio(bcm))
++                      bcm43xx_pio_handle_xmitstatus(bcm, &stat);
++              else
++                      bcm43xx_dma_handle_xmitstatus(bcm, &stat);
++      }
++}
++
++static void bcm43xx_generate_noise_sample(struct bcm43xx_private *bcm)
++{
++      bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x408, 0x7F7F);
++      bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x40A, 0x7F7F);
++      bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD,
++                      bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD) | (1 << 4));
++      assert(bcm->noisecalc.core_at_start == bcm->current_core);
++      assert(bcm->noisecalc.channel_at_start == bcm43xx_current_radio(bcm)->channel);
++}
++
++static void bcm43xx_calculate_link_quality(struct bcm43xx_private *bcm)
++{
++      /* Top half of Link Quality calculation. */
++
++      if (bcm->noisecalc.calculation_running)
++              return;
++      bcm->noisecalc.core_at_start = bcm->current_core;
++      bcm->noisecalc.channel_at_start = bcm43xx_current_radio(bcm)->channel;
++      bcm->noisecalc.calculation_running = 1;
++      bcm->noisecalc.nr_samples = 0;
++
++      bcm43xx_generate_noise_sample(bcm);
++}
++
++static void handle_irq_noise(struct bcm43xx_private *bcm)
++{
++      struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
++      u16 tmp;
++      u8 noise[4];
++      u8 i, j;
++      s32 average;
++
++      /* Bottom half of Link Quality calculation. */
++
++      assert(bcm->noisecalc.calculation_running);
++      if (bcm->noisecalc.core_at_start != bcm->current_core ||
++          bcm->noisecalc.channel_at_start != radio->channel)
++              goto drop_calculation;
++      tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x408);
++      noise[0] = (tmp & 0x00FF);
++      noise[1] = (tmp & 0xFF00) >> 8;
++      tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x40A);
++      noise[2] = (tmp & 0x00FF);
++      noise[3] = (tmp & 0xFF00) >> 8;
++      if (noise[0] == 0x7F || noise[1] == 0x7F ||
++          noise[2] == 0x7F || noise[3] == 0x7F)
++              goto generate_new;
++
++      /* Get the noise samples. */
++      assert(bcm->noisecalc.nr_samples <= 8);
++      i = bcm->noisecalc.nr_samples;
++      noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
++      noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
++      noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
++      noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
++      bcm->noisecalc.samples[i][0] = radio->nrssi_lt[noise[0]];
++      bcm->noisecalc.samples[i][1] = radio->nrssi_lt[noise[1]];
++      bcm->noisecalc.samples[i][2] = radio->nrssi_lt[noise[2]];
++      bcm->noisecalc.samples[i][3] = radio->nrssi_lt[noise[3]];
++      bcm->noisecalc.nr_samples++;
++      if (bcm->noisecalc.nr_samples == 8) {
++              /* Calculate the Link Quality by the noise samples. */
++              average = 0;
++              for (i = 0; i < 8; i++) {
++                      for (j = 0; j < 4; j++)
++                              average += bcm->noisecalc.samples[i][j];
++              }
++              average /= (8 * 4);
++              average *= 125;
++              average += 64;
++              average /= 128;
++              tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x40C);
++              tmp = (tmp / 128) & 0x1F;
++              if (tmp >= 8)
++                      average += 2;
++              else
++                      average -= 25;
++              if (tmp == 8)
++                      average -= 72;
++              else
++                      average -= 48;
++
++              if (average > -65)
++                      bcm->stats.link_quality = 0;
++              else if (average > -75)
++                      bcm->stats.link_quality = 1;
++              else if (average > -85)
++                      bcm->stats.link_quality = 2;
++              else
++                      bcm->stats.link_quality = 3;
++//            dprintk(KERN_INFO PFX "Link Quality: %u (avg was %d)\n", bcm->stats.link_quality, average);
++drop_calculation:
++              bcm->noisecalc.calculation_running = 0;
++              return;
++      }
++generate_new:
++      bcm43xx_generate_noise_sample(bcm);
++}
++
++static void handle_irq_ps(struct bcm43xx_private *bcm)
++{
++      if (bcm->iw_mode == IW_MODE_MASTER) {
++              ///TODO: PS TBTT
++      } else {
++              if (1/*FIXME: the last PSpoll frame was sent successfully */)
++                      bcm43xx_power_saving_ctl_bits(bcm, -1, -1);
++      }
++      if (bcm->iw_mode == IW_MODE_ADHOC)
++              bcm->reg124_set_0x4 = 1;
++      //FIXME else set to false?
++}
++
++static void handle_irq_reg124(struct bcm43xx_private *bcm)
++{
++      if (!bcm->reg124_set_0x4)
++              return;
++      bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD,
++                      bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD)
++                      | 0x4);
++      //FIXME: reset reg124_set_0x4 to false?
++}
++
++static void handle_irq_pmq(struct bcm43xx_private *bcm)
++{
++      u32 tmp;
++
++      //TODO: AP mode.
++
++      while (1) {
++              tmp = bcm43xx_read32(bcm, BCM43xx_MMIO_PS_STATUS);
++              if (!(tmp & 0x00000008))
++                      break;
++      }
++      /* 16bit write is odd, but correct. */
++      bcm43xx_write16(bcm, BCM43xx_MMIO_PS_STATUS, 0x0002);
++}
++
++static void bcm43xx_write_beacon_template(struct bcm43xx_private *bcm,
++                                        u16 ram_offset,
++                                        u16 shm_size_offset)
++{
++      u32 tmp;
++      u16 i, size;
++      const u8 *data;
++
++      data = (const u8 *)(bcm->cached_beacon->data);
++      size = min(bcm->cached_beacon->len, (unsigned int)17);
++
++      for (i = 0; i < size; i += sizeof(u32)) {
++              tmp = (u32)((data + i)[0]);
++              tmp |= (u32)((data + i)[1]) << 8;
++              tmp |= (u32)((data + i)[2]) << 16;
++              tmp |= (u32)((data + i)[3]) << 24;
++              bcm43xx_ram_write(bcm, ram_offset + i, tmp);
++      }
++      bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, shm_size_offset, size);
++}
++
++static void handle_irq_beacon(struct bcm43xx_private *bcm)
++{
++      u32 status;
++
++      bcm->irq_savedstate &= ~BCM43xx_IRQ_BEACON;
++      status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD);
++
++      if (!bcm->cached_beacon) {
++              struct ieee80211_tx_control control;
++
++              /* No cached template available, yet.
++               * Request the 80211 subsystem to generate a new beacon
++               * frame and use it as template.
++               */
++              bcm->cached_beacon = ieee80211_beacon_get(bcm->net_dev, 0, &control);
++              if (unlikely(!bcm->cached_beacon)) {
++                      dprintkl(KERN_WARNING PFX "Could not generate beacon template.\n");
++                      goto ack;
++              }
++      }
++
++      if ((status & 0x1) && (status & 0x2)) {
++ack:
++              /* ACK beacon IRQ. */
++              bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON,
++                              BCM43xx_IRQ_BEACON);
++              bcm->irq_savedstate |= BCM43xx_IRQ_BEACON;
++              if (likely(bcm->cached_beacon))
++                      kfree_skb(bcm->cached_beacon);
++              bcm->cached_beacon = NULL;
++              return;
++      }
++      if (!(status & 0x1)) {
++              bcm43xx_write_beacon_template(bcm, 0x68, 0x18);
++              status |= 0x1;
++              bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD, status);
++      }
++      if (!(status & 0x2)) {
++              bcm43xx_write_beacon_template(bcm, 0x468, 0x1A);
++              status |= 0x2;
++              bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD, status);
++      }
++}
++
++/* Interrupt handler bottom-half */
++static void bcm43xx_interrupt_tasklet(struct bcm43xx_private *bcm)
++{
++      u32 reason;
++      u32 dma_reason[4];
++      int activity = 0;
++      unsigned long flags;
++
++#ifdef CONFIG_BCM43XX_D80211_DEBUG
++      u32 _handled = 0x00000000;
++# define bcmirq_handled(irq)  do { _handled |= (irq); } while (0)
++#else
++# define bcmirq_handled(irq)  do { /* nothing */ } while (0)
++#endif /* CONFIG_BCM43XX_D80211_DEBUG*/
++
++      bcm43xx_lock_mmio(bcm, flags);
++      reason = bcm->irq_reason;
++      dma_reason[0] = bcm->dma_reason[0];
++      dma_reason[1] = bcm->dma_reason[1];
++      dma_reason[2] = bcm->dma_reason[2];
++      dma_reason[3] = bcm->dma_reason[3];
++
++      if (unlikely(reason & BCM43xx_IRQ_XMIT_ERROR)) {
++              /* TX error. We get this when Template Ram is written in wrong endianess
++               * in dummy_tx(). We also get this if something is wrong with the TX header
++               * on DMA or PIO queues.
++               * Maybe we get this in other error conditions, too.
++               */
++              printkl(KERN_ERR PFX "FATAL ERROR: BCM43xx_IRQ_XMIT_ERROR\n");
++              bcmirq_handled(BCM43xx_IRQ_XMIT_ERROR);
++      }
++      if (unlikely((dma_reason[0] & BCM43xx_DMAIRQ_FATALMASK) |
++                   (dma_reason[1] & BCM43xx_DMAIRQ_FATALMASK) |
++                   (dma_reason[2] & BCM43xx_DMAIRQ_FATALMASK) |
++                   (dma_reason[3] & BCM43xx_DMAIRQ_FATALMASK))) {
++              printkl(KERN_ERR PFX "FATAL ERROR: Fatal DMA error: "
++                                   "0x%08X, 0x%08X, 0x%08X, 0x%08X\n",
++                      dma_reason[0], dma_reason[1],
++                      dma_reason[2], dma_reason[3]);
++              bcm43xx_controller_restart(bcm, "DMA error");
++              bcm43xx_unlock_mmio(bcm, flags);
++              return;
++      }
++      if (unlikely((dma_reason[0] & BCM43xx_DMAIRQ_NONFATALMASK) |
++                   (dma_reason[1] & BCM43xx_DMAIRQ_NONFATALMASK) |
++                   (dma_reason[2] & BCM43xx_DMAIRQ_NONFATALMASK) |
++                   (dma_reason[3] & BCM43xx_DMAIRQ_NONFATALMASK))) {
++              printkl(KERN_ERR PFX "DMA error: "
++                                   "0x%08X, 0x%08X, 0x%08X, 0x%08X\n",
++                      dma_reason[0], dma_reason[1],
++                      dma_reason[2], dma_reason[3]);
++      }
++
++      if (reason & BCM43xx_IRQ_PS) {
++              handle_irq_ps(bcm);
++              bcmirq_handled(BCM43xx_IRQ_PS);
++      }
++
++      if (reason & BCM43xx_IRQ_REG124) {
++              handle_irq_reg124(bcm);
++              bcmirq_handled(BCM43xx_IRQ_REG124);
++      }
++
++      if (reason & BCM43xx_IRQ_BEACON) {
++              if (bcm->iw_mode == IW_MODE_MASTER)
++                      handle_irq_beacon(bcm);
++              bcmirq_handled(BCM43xx_IRQ_BEACON);
++      }
++
++      if (reason & BCM43xx_IRQ_PMQ) {
++              handle_irq_pmq(bcm);
++              bcmirq_handled(BCM43xx_IRQ_PMQ);
++      }
++
++      if (reason & BCM43xx_IRQ_SCAN) {
++              /*TODO*/
++              //bcmirq_handled(BCM43xx_IRQ_SCAN);
++      }
++
++      if (reason & BCM43xx_IRQ_NOISE) {
++              handle_irq_noise(bcm);
++              bcmirq_handled(BCM43xx_IRQ_NOISE);
++      }
++
++      /* Check the DMA reason registers for received data. */
++      assert(!(dma_reason[1] & BCM43xx_DMAIRQ_RX_DONE));
++      assert(!(dma_reason[2] & BCM43xx_DMAIRQ_RX_DONE));
++      if (dma_reason[0] & BCM43xx_DMAIRQ_RX_DONE) {
++              if (bcm43xx_using_pio(bcm))
++                      bcm43xx_pio_rx(bcm43xx_current_pio(bcm)->queue0);
++              else
++                      bcm43xx_dma_rx(bcm43xx_current_dma(bcm)->rx_ring0);
++              /* We intentionally don't set "activity" to 1, here. */
++      }
++      if (dma_reason[3] & BCM43xx_DMAIRQ_RX_DONE) {
++              if (bcm43xx_using_pio(bcm))
++                      bcm43xx_pio_rx(bcm43xx_current_pio(bcm)->queue3);
++              else
++                      bcm43xx_dma_rx(bcm43xx_current_dma(bcm)->rx_ring1);
++              activity = 1;
++      }
++      bcmirq_handled(BCM43xx_IRQ_RX);
++
++      if (reason & BCM43xx_IRQ_XMIT_STATUS) {
++              handle_irq_transmit_status(bcm);
++              activity = 1;
++              //TODO: In AP mode, this also causes sending of powersave responses.
++              bcmirq_handled(BCM43xx_IRQ_XMIT_STATUS);
++      }
++
++      /* IRQ_PIO_WORKAROUND is handled in the top-half. */
++      bcmirq_handled(BCM43xx_IRQ_PIO_WORKAROUND);
++#ifdef CONFIG_BCM43XX_D80211_DEBUG
++      if (unlikely(reason & ~_handled)) {
++              printkl(KERN_WARNING PFX
++                      "Unhandled IRQ! Reason: 0x%08x,  Unhandled: 0x%08x,  "
++                      "DMA: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
++                      reason, (reason & ~_handled),
++                      dma_reason[0], dma_reason[1],
++                      dma_reason[2], dma_reason[3]);
++      }
++#endif
++#undef bcmirq_handled
++
++      if (!modparam_noleds)
++              bcm43xx_leds_update(bcm, activity);
++      bcm43xx_interrupt_enable(bcm, bcm->irq_savedstate);
++      bcm43xx_unlock_mmio(bcm, flags);
++}
++
++static void pio_irq_workaround(struct bcm43xx_private *bcm,
++                             u16 base, int queueidx)
++{
++      u16 rxctl;
++
++      rxctl = bcm43xx_read16(bcm, base + BCM43xx_PIO_RXCTL);
++      if (rxctl & BCM43xx_PIO_RXCTL_DATAAVAILABLE)
++              bcm->dma_reason[queueidx] |= BCM43xx_DMAIRQ_RX_DONE;
++      else
++              bcm->dma_reason[queueidx] &= ~BCM43xx_DMAIRQ_RX_DONE;
++}
++
++static void bcm43xx_interrupt_ack(struct bcm43xx_private *bcm, u32 reason)
++{
++      if (bcm43xx_using_pio(bcm) &&
++          (bcm->current_core->rev < 3) &&
++          (!(reason & BCM43xx_IRQ_PIO_WORKAROUND))) {
++              /* Apply a PIO specific workaround to the dma_reasons */
++              pio_irq_workaround(bcm, BCM43xx_MMIO_PIO1_BASE, 0);
++              pio_irq_workaround(bcm, BCM43xx_MMIO_PIO2_BASE, 1);
++              pio_irq_workaround(bcm, BCM43xx_MMIO_PIO3_BASE, 2);
++              pio_irq_workaround(bcm, BCM43xx_MMIO_PIO4_BASE, 3);
++      }
++
++      bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, reason);
++
++      bcm43xx_write32(bcm, BCM43xx_MMIO_DMA1_REASON,
++                      bcm->dma_reason[0]);
++      bcm43xx_write32(bcm, BCM43xx_MMIO_DMA2_REASON,
++                      bcm->dma_reason[1]);
++      bcm43xx_write32(bcm, BCM43xx_MMIO_DMA3_REASON,
++                      bcm->dma_reason[2]);
++      bcm43xx_write32(bcm, BCM43xx_MMIO_DMA4_REASON,
++                      bcm->dma_reason[3]);
++}
++
++/* Interrupt handler top-half */
++static irqreturn_t bcm43xx_interrupt_handler(int irq, void *dev_id, struct pt_regs *regs)
++{
++      irqreturn_t ret = IRQ_HANDLED;
++      struct bcm43xx_private *bcm = dev_id;
++      u32 reason;
++
++      if (!bcm)
++              return IRQ_NONE;
++
++      spin_lock(&bcm->_lock);
++
++      reason = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
++      if (reason == 0xffffffff) {
++              /* irq not for us (shared irq) */
++              ret = IRQ_NONE;
++              goto out;
++      }
++      reason &= bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
++      if (!reason)
++              goto out;
++
++      bcm->dma_reason[0] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA1_REASON)
++                           & 0x0001dc00;
++      bcm->dma_reason[1] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA2_REASON)
++                           & 0x0000dc00;
++      bcm->dma_reason[2] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA3_REASON)
++                           & 0x0000dc00;
++      bcm->dma_reason[3] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA4_REASON)
++                           & 0x0001dc00;
++
++      bcm43xx_interrupt_ack(bcm, reason);
++
++      /* Only accept IRQs, if we are initialized properly.
++       * This avoids an RX race while initializing.
++       * We should probably not enable IRQs before we are initialized
++       * completely, but some careful work is needed to fix this. I think it
++       * is best to stay with this cheap workaround for now... .
++       */
++      if (likely(bcm->initialized)) {
++              /* disable all IRQs. They are enabled again in the bottom half. */
++              bcm->irq_savedstate = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
++              /* save the reason code and call our bottom half. */
++              bcm->irq_reason = reason;
++              tasklet_schedule(&bcm->isr_tasklet);
++      }
++
++out:
++      mmiowb();
++      spin_unlock(&bcm->_lock);
++
++      return ret;
++}
++
++static void bcm43xx_release_firmware(struct bcm43xx_private *bcm, int force)
++{
++      if (bcm->firmware_norelease && !force)
++              return; /* Suspending or controller reset. */
++      release_firmware(bcm->ucode);
++      bcm->ucode = NULL;
++      release_firmware(bcm->pcm);
++      bcm->pcm = NULL;
++      release_firmware(bcm->initvals0);
++      bcm->initvals0 = NULL;
++      release_firmware(bcm->initvals1);
++      bcm->initvals1 = NULL;
++}
++
++static int bcm43xx_request_firmware(struct bcm43xx_private *bcm)
++{
++      struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
++      u8 rev = bcm->current_core->rev;
++      int err = 0;
++      int nr;
++      char buf[22 + sizeof(modparam_fwpostfix) - 1] = { 0 };
++
++      if (!bcm->ucode) {
++              snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_microcode%d%s.fw",
++                       (rev >= 5 ? 5 : rev),
++                       modparam_fwpostfix);
++              err = request_firmware(&bcm->ucode, buf, &bcm->pci_dev->dev);
++              if (err) {
++                      printk(KERN_ERR PFX 
++                             "Error: Microcode \"%s\" not available or load failed.\n",
++                              buf);
++                      goto error;
++              }
++      }
++
++      if (!bcm->pcm) {
++              snprintf(buf, ARRAY_SIZE(buf),
++                       "bcm43xx_pcm%d%s.fw",
++                       (rev < 5 ? 4 : 5),
++                       modparam_fwpostfix);
++              err = request_firmware(&bcm->pcm, buf, &bcm->pci_dev->dev);
++              if (err) {
++                      printk(KERN_ERR PFX
++                             "Error: PCM \"%s\" not available or load failed.\n",
++                             buf);
++                      goto error;
++              }
++      }
++
++      if (!bcm->initvals0) {
++              if (rev == 2 || rev == 4) {
++                      switch (phy->type) {
++                      case BCM43xx_PHYTYPE_A:
++                              nr = 3;
++                              break;
++                      case BCM43xx_PHYTYPE_B:
++                      case BCM43xx_PHYTYPE_G:
++                              nr = 1;
++                              break;
++                      default:
++                              goto err_noinitval;
++                      }
++              
++              } else if (rev >= 5) {
++                      switch (phy->type) {
++                      case BCM43xx_PHYTYPE_A:
++                              nr = 7;
++                              break;
++                      case BCM43xx_PHYTYPE_B:
++                      case BCM43xx_PHYTYPE_G:
++                              nr = 5;
++                              break;
++                      default:
++                              goto err_noinitval;
++                      }
++              } else
++                      goto err_noinitval;
++              snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
++                       nr, modparam_fwpostfix);
++
++              err = request_firmware(&bcm->initvals0, buf, &bcm->pci_dev->dev);
++              if (err) {
++                      printk(KERN_ERR PFX 
++                             "Error: InitVals \"%s\" not available or load failed.\n",
++                              buf);
++                      goto error;
++              }
++              if (bcm->initvals0->size % sizeof(struct bcm43xx_initval)) {
++                      printk(KERN_ERR PFX "InitVals fileformat error.\n");
++                      goto error;
++              }
++      }
++
++      if (!bcm->initvals1) {
++              if (rev >= 5) {
++                      u32 sbtmstatehigh;
++
++                      switch (phy->type) {
++                      case BCM43xx_PHYTYPE_A:
++                              sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
++                              if (sbtmstatehigh & 0x00010000)
++                                      nr = 9;
++                              else
++                                      nr = 10;
++                              break;
++                      case BCM43xx_PHYTYPE_B:
++                      case BCM43xx_PHYTYPE_G:
++                                      nr = 6;
++                              break;
++                      default:
++                              goto err_noinitval;
++                      }
++                      snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
++                               nr, modparam_fwpostfix);
++
++                      err = request_firmware(&bcm->initvals1, buf, &bcm->pci_dev->dev);
++                      if (err) {
++                              printk(KERN_ERR PFX 
++                                     "Error: InitVals \"%s\" not available or load failed.\n",
++                                      buf);
++                              goto error;
++                      }
++                      if (bcm->initvals1->size % sizeof(struct bcm43xx_initval)) {
++                              printk(KERN_ERR PFX "InitVals fileformat error.\n");
++                              goto error;
++                      }
++              }
++      }
++
++out:
++      return err;
++error:
++      bcm43xx_release_firmware(bcm, 1);
++      goto out;
++err_noinitval:
++      printk(KERN_ERR PFX "Error: No InitVals available!\n");
++      err = -ENOENT;
++      goto error;
++}
++
++static void bcm43xx_upload_microcode(struct bcm43xx_private *bcm)
++{
++      const u32 *data;
++      unsigned int i, len;
++
++      /* Upload Microcode. */
++      data = (u32 *)(bcm->ucode->data);
++      len = bcm->ucode->size / sizeof(u32);
++      bcm43xx_shm_control_word(bcm, BCM43xx_SHM_UCODE, 0x0000);
++      for (i = 0; i < len; i++) {
++              bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA,
++                              be32_to_cpu(data[i]));
++              udelay(10);
++      }
++
++      /* Upload PCM data. */
++      data = (u32 *)(bcm->pcm->data);
++      len = bcm->pcm->size / sizeof(u32);
++      bcm43xx_shm_control_word(bcm, BCM43xx_SHM_PCM, 0x01ea);
++      bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA, 0x00004000);
++      bcm43xx_shm_control_word(bcm, BCM43xx_SHM_PCM, 0x01eb);
++      for (i = 0; i < len; i++) {
++              bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA,
++                              be32_to_cpu(data[i]));
++              udelay(10);
++      }
++}
++
++static int bcm43xx_write_initvals(struct bcm43xx_private *bcm,
++                                const struct bcm43xx_initval *data,
++                                const unsigned int len)
++{
++      u16 offset, size;
++      u32 value;
++      unsigned int i;
++
++      for (i = 0; i < len; i++) {
++              offset = be16_to_cpu(data[i].offset);
++              size = be16_to_cpu(data[i].size);
++              value = be32_to_cpu(data[i].value);
++
++              if (unlikely(offset >= 0x1000))
++                      goto err_format;
++              if (size == 2) {
++                      if (unlikely(value & 0xFFFF0000))
++                              goto err_format;
++                      bcm43xx_write16(bcm, offset, (u16)value);
++              } else if (size == 4) {
++                      bcm43xx_write32(bcm, offset, value);
++              } else
++                      goto err_format;
++      }
++
++      return 0;
++
++err_format:
++      printk(KERN_ERR PFX "InitVals (bcm43xx_initvalXX.fw) file-format error. "
++                          "Please fix your bcm43xx firmware files.\n");
++      return -EPROTO;
++}
++
++static int bcm43xx_upload_initvals(struct bcm43xx_private *bcm)
++{
++      int err;
++
++      err = bcm43xx_write_initvals(bcm, (struct bcm43xx_initval *)bcm->initvals0->data,
++                                   bcm->initvals0->size / sizeof(struct bcm43xx_initval));
++      if (err)
++              goto out;
++      if (bcm->initvals1) {
++              err = bcm43xx_write_initvals(bcm, (struct bcm43xx_initval *)bcm->initvals1->data,
++                                           bcm->initvals1->size / sizeof(struct bcm43xx_initval));
++              if (err)
++                      goto out;
++      }
++out:
++      return err;
++}
++
++static int bcm43xx_initialize_irq(struct bcm43xx_private *bcm)
++{
++      int res;
++      unsigned int i;
++      u32 data;
++
++      bcm->irq = bcm->pci_dev->irq;
++#ifdef CONFIG_BCM947XX
++      if (bcm->pci_dev->bus->number == 0) {
++              struct pci_dev *d = NULL;
++              /* FIXME: we will probably need more device IDs here... */
++              d = pci_find_device(PCI_VENDOR_ID_BROADCOM, 0x4324, NULL);
++              if (d != NULL) {
++                      bcm->irq = d->irq;
++              }
++      }
++#endif
++      res = request_irq(bcm->irq, bcm43xx_interrupt_handler,
++                        SA_SHIRQ, KBUILD_MODNAME, bcm);
++      if (res) {
++              printk(KERN_ERR PFX "Cannot register IRQ%d\n", bcm->irq);
++              return -ENODEV;
++      }
++      bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, 0xffffffff);
++      bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, 0x00020402);
++      i = 0;
++      while (1) {
++              data = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
++              if (data == BCM43xx_IRQ_READY)
++                      break;
++              i++;
++              if (i >= BCM43xx_IRQWAIT_MAX_RETRIES) {
++                      printk(KERN_ERR PFX "Card IRQ register not responding. "
++                                          "Giving up.\n");
++                      free_irq(bcm->irq, bcm);
++                      return -ENODEV;
++              }
++              udelay(10);
++      }
++      // dummy read
++      bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
++
++      return 0;
++}
++
++/* Switch to the core used to write the GPIO register.
++ * This is either the ChipCommon, or the PCI core.
++ */
++static int switch_to_gpio_core(struct bcm43xx_private *bcm)
++{
++      int err;
++
++      /* Where to find the GPIO register depends on the chipset.
++       * If it has a ChipCommon, its register at offset 0x6c is the GPIO
++       * control register. Otherwise the register at offset 0x6c in the
++       * PCI core is the GPIO control register.
++       */
++      err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon);
++      if (err == -ENODEV) {
++              err = bcm43xx_switch_core(bcm, &bcm->core_pci);
++              if (unlikely(err == -ENODEV)) {
++                      printk(KERN_ERR PFX "gpio error: "
++                             "Neither ChipCommon nor PCI core available!\n");
++              }
++      }
++
++      return err;
++}
++
++/* Initialize the GPIOs
++ * http://bcm-specs.sipsolutions.net/GPIO
++ */
++static int bcm43xx_gpio_init(struct bcm43xx_private *bcm)
++{
++      struct bcm43xx_coreinfo *old_core;
++      int err;
++      u32 mask, set;
++
++      bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
++                      bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
++                      & 0xFFFF3FFF);
++
++      bcm43xx_leds_switch_all(bcm, 0);
++      bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
++                      bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK) | 0x000F);
++
++      mask = 0x0000001F;
++      set = 0x0000000F;
++      if (bcm->chip_id == 0x4301) {
++              mask |= 0x0060;
++              set |= 0x0060;
++      }
++      if (0 /* FIXME: conditional unknown */) {
++              bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
++                              bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK)
++                              | 0x0100);
++              mask |= 0x0180;
++              set |= 0x0180;
++      }
++      if (bcm->sprom.boardflags & BCM43xx_BFL_PACTRL) {
++              bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
++                              bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK)
++                              | 0x0200);
++              mask |= 0x0200;
++              set |= 0x0200;
++      }
++      if (bcm->current_core->rev >= 2)
++              mask  |= 0x0010; /* FIXME: This is redundant. */
++
++      old_core = bcm->current_core;
++      err = switch_to_gpio_core(bcm);
++      if (err)
++              goto out;
++      bcm43xx_write32(bcm, BCM43xx_GPIO_CONTROL,
++                      (bcm43xx_read32(bcm, BCM43xx_GPIO_CONTROL) & mask) | set);
++      err = bcm43xx_switch_core(bcm, old_core);
++out:
++      return err;
++}
++
++/* Turn off all GPIO stuff. Call this on module unload, for example. */
++static int bcm43xx_gpio_cleanup(struct bcm43xx_private *bcm)
++{
++      struct bcm43xx_coreinfo *old_core;
++      int err;
++
++      old_core = bcm->current_core;
++      err = switch_to_gpio_core(bcm);
++      if (err)
++              return err;
++      bcm43xx_write32(bcm, BCM43xx_GPIO_CONTROL, 0x00000000);
++      err = bcm43xx_switch_core(bcm, old_core);
++      assert(err == 0);
++
++      return 0;
++}
++
++/* http://bcm-specs.sipsolutions.net/EnableMac */
++void bcm43xx_mac_enable(struct bcm43xx_private *bcm)
++{
++      bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
++                      bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
++                      | BCM43xx_SBF_MAC_ENABLED);
++      bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, BCM43xx_IRQ_READY);
++      bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
++      bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
++      bcm43xx_power_saving_ctl_bits(bcm, -1, -1);
++}
++
++/* http://bcm-specs.sipsolutions.net/SuspendMAC */
++void bcm43xx_mac_suspend(struct bcm43xx_private *bcm)
++{
++      int i;
++      u32 tmp;
++
++      bcm43xx_power_saving_ctl_bits(bcm, -1, 1);
++      bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
++                      bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
++                      & ~BCM43xx_SBF_MAC_ENABLED);
++      bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
++      for (i = 100000; i; i--) {
++              tmp = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
++              if (tmp & BCM43xx_IRQ_READY)
++                      return;
++              udelay(10);
++      }
++      printkl(KERN_ERR PFX "MAC suspend failed\n");
++}
++
++void bcm43xx_set_iwmode(struct bcm43xx_private *bcm,
++                      int iw_mode)
++{
++      struct net_device *net_dev = bcm->net_dev;
++      u32 status;
++      u16 value;
++
++      bcm->iw_mode = iw_mode;
++      if (iw_mode == IW_MODE_MONITOR)
++              net_dev->type = ARPHRD_IEEE80211;
++      else
++              net_dev->type = ARPHRD_ETHER;
++
++      status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
++      /* Reset status to infrastructured mode */
++      status &= ~(BCM43xx_SBF_MODE_AP | BCM43xx_SBF_MODE_MONITOR);
++      status &= ~BCM43xx_SBF_MODE_PROMISC;
++      status |= BCM43xx_SBF_MODE_NOTADHOC;
++
++/* FIXME: Always enable promisc mode, until we get the MAC filters working correctly. */
++status |= BCM43xx_SBF_MODE_PROMISC;
++
++      switch (iw_mode) {
++      case IW_MODE_MONITOR:
++              status |= BCM43xx_SBF_MODE_MONITOR;
++              status |= BCM43xx_SBF_MODE_PROMISC;
++              break;
++      case IW_MODE_ADHOC:
++              status &= ~BCM43xx_SBF_MODE_NOTADHOC;
++              break;
++      case IW_MODE_MASTER:
++              status |= BCM43xx_SBF_MODE_AP;
++              break;
++      case IW_MODE_SECOND:
++      case IW_MODE_REPEAT:
++              TODO(); /* TODO */
++              break;
++      case IW_MODE_INFRA:
++              /* nothing to be done here... */
++              break;
++      default:
++              dprintk(KERN_ERR PFX "Unknown mode in set_iwmode: %d\n", iw_mode);
++      }
++      if (net_dev->flags & IFF_PROMISC)
++              status |= BCM43xx_SBF_MODE_PROMISC;
++      bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
++
++      value = 0x0002;
++      if (iw_mode != IW_MODE_ADHOC && iw_mode != IW_MODE_MASTER) {
++              if (bcm->chip_id == 0x4306 && bcm->chip_rev == 3)
++                      value = 0x0064;
++              else
++                      value = 0x0032;
++      }
++      bcm43xx_write16(bcm, 0x0612, value);
++}
++
++/* This is the opposite of bcm43xx_chip_init() */
++static void bcm43xx_chip_cleanup(struct bcm43xx_private *bcm)
++{
++      bcm43xx_radio_turn_off(bcm);
++      if (!modparam_noleds)
++              bcm43xx_leds_exit(bcm);
++      bcm43xx_gpio_cleanup(bcm);
++      free_irq(bcm->irq, bcm);
++      bcm43xx_release_firmware(bcm, 0);
++}
++
++/* Initialize the chip
++ * http://bcm-specs.sipsolutions.net/ChipInit
++ */
++static int bcm43xx_chip_init(struct bcm43xx_private *bcm)
++{
++      struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
++      struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
++      int err;
++      int tmp;
++      u32 value32;
++      u16 value16;
++
++      bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
++                      BCM43xx_SBF_CORE_READY
++                      | BCM43xx_SBF_400);
++
++      err = bcm43xx_request_firmware(bcm);
++      if (err)
++              goto out;
++      bcm43xx_upload_microcode(bcm);
++      err = bcm43xx_initialize_irq(bcm);
++      if (err)
++              goto err_release_fw;
++      err = bcm43xx_gpio_init(bcm);
++      if (err)
++              goto err_free_irq;
++      err = bcm43xx_upload_initvals(bcm);
++      if (err)
++              goto err_gpio_cleanup;
++      bcm43xx_radio_turn_on(bcm);
++
++      bcm43xx_write16(bcm, 0x03E6, 0x0000);
++      err = bcm43xx_phy_init(bcm);
++      if (err)
++              goto err_radio_off;
++
++      /* Select initial Interference Mitigation. */
++      tmp = radio->interfmode;
++      radio->interfmode = BCM43xx_RADIO_INTERFMODE_NONE;
++      bcm43xx_radio_set_interference_mitigation(bcm, tmp);
++
++      bcm43xx_phy_set_antenna_diversity(bcm);
++      bcm43xx_radio_set_txantenna(bcm, BCM43xx_RADIO_TXANTENNA_DEFAULT);
++      if (phy->type == BCM43xx_PHYTYPE_B) {
++              value16 = bcm43xx_read16(bcm, 0x005E);
++              value16 |= 0x0004;
++              bcm43xx_write16(bcm, 0x005E, value16);
++      }
++      bcm43xx_write32(bcm, 0x0100, 0x01000000);
++      if (bcm->current_core->rev < 5)
++              bcm43xx_write32(bcm, 0x010C, 0x01000000);
++
++      value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
++      value32 &= ~ BCM43xx_SBF_MODE_NOTADHOC;
++      bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
++      value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
++      value32 |= BCM43xx_SBF_MODE_NOTADHOC;
++      bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
++
++      value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
++      value32 |= 0x100000;
++      bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
++
++      if (bcm43xx_using_pio(bcm)) {
++              bcm43xx_write32(bcm, 0x0210, 0x00000100);
++              bcm43xx_write32(bcm, 0x0230, 0x00000100);
++              bcm43xx_write32(bcm, 0x0250, 0x00000100);
++              bcm43xx_write32(bcm, 0x0270, 0x00000100);
++              bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0034, 0x0000);
++      }
++
++      /* Probe Response Timeout value */
++      /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
++      bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0074, 0x0000);
++
++      /* Initially set the wireless operation mode. */
++      bcm43xx_set_iwmode(bcm, bcm->iw_mode);
++
++      if (bcm->current_core->rev < 3) {
++              bcm43xx_write16(bcm, 0x060E, 0x0000);
++              bcm43xx_write16(bcm, 0x0610, 0x8000);
++              bcm43xx_write16(bcm, 0x0604, 0x0000);
++              bcm43xx_write16(bcm, 0x0606, 0x0200);
++      } else {
++              bcm43xx_write32(bcm, 0x0188, 0x80000000);
++              bcm43xx_write32(bcm, 0x018C, 0x02000000);
++      }
++      bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, 0x00004000);
++      bcm43xx_write32(bcm, BCM43xx_MMIO_DMA1_IRQ_MASK, 0x0001DC00);
++      bcm43xx_write32(bcm, BCM43xx_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
++      bcm43xx_write32(bcm, BCM43xx_MMIO_DMA3_IRQ_MASK, 0x0000DC00);
++      bcm43xx_write32(bcm, BCM43xx_MMIO_DMA4_IRQ_MASK, 0x0001DC00);
++
++      value32 = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
++      value32 |= 0x00100000;
++      bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, value32);
++
++      bcm43xx_write16(bcm, BCM43xx_MMIO_POWERUP_DELAY, bcm43xx_pctl_powerup_delay(bcm));
++
++      assert(err == 0);
++      dprintk(KERN_INFO PFX "Chip initialized\n");
++out:
++      return err;
++
++err_radio_off:
++      bcm43xx_radio_turn_off(bcm);
++err_gpio_cleanup:
++      bcm43xx_gpio_cleanup(bcm);
++err_free_irq:
++      free_irq(bcm->irq, bcm);
++err_release_fw:
++      bcm43xx_release_firmware(bcm, 1);
++      goto out;
++}
++      
++/* Validate chip access
++ * http://bcm-specs.sipsolutions.net/ValidateChipAccess */
++static int bcm43xx_validate_chip(struct bcm43xx_private *bcm)
++{
++      u32 value;
++      u32 shm_backup;
++
++      shm_backup = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000);
++      bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, 0xAA5555AA);
++      if (bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000) != 0xAA5555AA)
++              goto error;
++      bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, 0x55AAAA55);
++      if (bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000) != 0x55AAAA55)
++              goto error;
++      bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, shm_backup);
++
++      value = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
++      if ((value | 0x80000000) != 0x80000400)
++              goto error;
++
++      value = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
++      if (value != 0x00000000)
++              goto error;
++
++      return 0;
++error:
++      printk(KERN_ERR PFX "Failed to validate the chipaccess\n");
++      return -ENODEV;
++}
++
++static void bcm43xx_init_struct_phyinfo(struct bcm43xx_phyinfo *phy)
++{
++      /* Initialize a "phyinfo" structure. The structure is already
++       * zeroed out.
++       */
++      phy->antenna_diversity = 0xFFFF;
++      phy->savedpctlreg = 0xFFFF;
++      phy->minlowsig[0] = 0xFFFF;
++      phy->minlowsig[1] = 0xFFFF;
++      spin_lock_init(&phy->lock);
++}
++
++static void bcm43xx_init_struct_radioinfo(struct bcm43xx_radioinfo *radio)
++{
++      /* Initialize a "radioinfo" structure. The structure is already
++       * zeroed out.
++       */
++      radio->interfmode = BCM43xx_RADIO_INTERFMODE_NONE;
++      radio->channel = 0xFF;
++      radio->initial_channel = 0xFF;
++      radio->lofcal = 0xFFFF;
++      radio->initval = 0xFFFF;
++      radio->nrssi[0] = -1000;
++      radio->nrssi[1] = -1000;
++}
++
++static int bcm43xx_probe_cores(struct bcm43xx_private *bcm)
++{
++      int err, i;
++      int current_core;
++      u32 core_vendor, core_id, core_rev;
++      u32 sb_id_hi, chip_id_32 = 0;
++      u16 pci_device, chip_id_16;
++      u8 core_count;
++
++      memset(&bcm->core_chipcommon, 0, sizeof(struct bcm43xx_coreinfo));
++      memset(&bcm->core_pci, 0, sizeof(struct bcm43xx_coreinfo));
++      memset(&bcm->core_80211, 0, sizeof(struct bcm43xx_coreinfo)
++                                  * BCM43xx_MAX_80211_CORES);
++      memset(&bcm->core_80211_ext, 0, sizeof(struct bcm43xx_coreinfo_80211)
++                                      * BCM43xx_MAX_80211_CORES);
++      bcm->current_80211_core_idx = -1;
++      bcm->nr_80211_available = 0;
++      bcm->current_core = NULL;
++      bcm->active_80211_core = NULL;
++
++      /* map core 0 */
++      err = _switch_core(bcm, 0);
++      if (err)
++              goto out;
++
++      /* fetch sb_id_hi from core information registers */
++      sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI);
++
++      core_id = (sb_id_hi & 0xFFF0) >> 4;
++      core_rev = (sb_id_hi & 0xF);
++      core_vendor = (sb_id_hi & 0xFFFF0000) >> 16;
++
++      /* if present, chipcommon is always core 0; read the chipid from it */
++      if (core_id == BCM43xx_COREID_CHIPCOMMON) {
++              chip_id_32 = bcm43xx_read32(bcm, 0);
++              chip_id_16 = chip_id_32 & 0xFFFF;
++              bcm->core_chipcommon.available = 1;
++              bcm->core_chipcommon.id = core_id;
++              bcm->core_chipcommon.rev = core_rev;
++              bcm->core_chipcommon.index = 0;
++              /* While we are at it, also read the capabilities. */
++              bcm->chipcommon_capabilities = bcm43xx_read32(bcm, BCM43xx_CHIPCOMMON_CAPABILITIES);
++      } else {
++              /* without a chipCommon, use a hard coded table. */
++              pci_device = bcm->pci_dev->device;
++              if (pci_device == 0x4301)
++                      chip_id_16 = 0x4301;
++              else if ((pci_device >= 0x4305) && (pci_device <= 0x4307))
++                      chip_id_16 = 0x4307;
++              else if ((pci_device >= 0x4402) && (pci_device <= 0x4403))
++                      chip_id_16 = 0x4402;
++              else if ((pci_device >= 0x4610) && (pci_device <= 0x4615))
++                      chip_id_16 = 0x4610;
++              else if ((pci_device >= 0x4710) && (pci_device <= 0x4715))
++                      chip_id_16 = 0x4710;
++#ifdef CONFIG_BCM947XX
++              else if ((pci_device >= 0x4320) && (pci_device <= 0x4325))
++                      chip_id_16 = 0x4309;
++#endif
++              else {
++                      printk(KERN_ERR PFX "Could not determine Chip ID\n");
++                      return -ENODEV;
++              }
++      }
++
++      /* ChipCommon with Core Rev >=4 encodes number of cores,
++       * otherwise consult hardcoded table */
++      if ((core_id == BCM43xx_COREID_CHIPCOMMON) && (core_rev >= 4)) {
++              core_count = (chip_id_32 & 0x0F000000) >> 24;
++      } else {
++              switch (chip_id_16) {
++                      case 0x4610:
++                      case 0x4704:
++                      case 0x4710:
++                              core_count = 9;
++                              break;
++                      case 0x4310:
++                              core_count = 8;
++                              break;
++                      case 0x5365:
++                              core_count = 7;
++                              break;
++                      case 0x4306:
++                              core_count = 6;
++                              break;
++                      case 0x4301:
++                      case 0x4307:
++                              core_count = 5;
++                              break;
++                      case 0x4402:
++                              core_count = 3;
++                              break;
++                      default:
++                              /* SOL if we get here */
++                              assert(0);
++                              core_count = 1;
++              }
++      }
++
++      bcm->chip_id = chip_id_16;
++      bcm->chip_rev = (chip_id_32 & 0x000F0000) >> 16;
++      bcm->chip_package = (chip_id_32 & 0x00F00000) >> 20;
++
++      dprintk(KERN_INFO PFX "Chip ID 0x%x, rev 0x%x\n",
++              bcm->chip_id, bcm->chip_rev);
++      dprintk(KERN_INFO PFX "Number of cores: %d\n", core_count);
++      if (bcm->core_chipcommon.available) {
++              dprintk(KERN_INFO PFX "Core 0: ID 0x%x, rev 0x%x, vendor 0x%x, %s\n",
++                      core_id, core_rev, core_vendor,
++                      bcm43xx_core_enabled(bcm) ? "enabled" : "disabled");
++      }
++
++      if (bcm->core_chipcommon.available)
++              current_core = 1;
++      else
++              current_core = 0;
++      for ( ; current_core < core_count; current_core++) {
++              struct bcm43xx_coreinfo *core;
++              struct bcm43xx_coreinfo_80211 *ext_80211;
++
++              err = _switch_core(bcm, current_core);
++              if (err)
++                      goto out;
++              /* Gather information */
++              /* fetch sb_id_hi from core information registers */
++              sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI);
++
++              /* extract core_id, core_rev, core_vendor */
++              core_id = (sb_id_hi & 0xFFF0) >> 4;
++              core_rev = (sb_id_hi & 0xF);
++              core_vendor = (sb_id_hi & 0xFFFF0000) >> 16;
++
++              dprintk(KERN_INFO PFX "Core %d: ID 0x%x, rev 0x%x, vendor 0x%x, %s\n",
++                      current_core, core_id, core_rev, core_vendor,
++                      bcm43xx_core_enabled(bcm) ? "enabled" : "disabled" );
++
++              core = NULL;
++              switch (core_id) {
++              case BCM43xx_COREID_PCI:
++                      core = &bcm->core_pci;
++                      if (core->available) {
++                              printk(KERN_WARNING PFX "Multiple PCI cores found.\n");
++                              continue;
++                      }
++                      break;
++              case BCM43xx_COREID_80211:
++                      for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
++                              core = &(bcm->core_80211[i]);
++                              ext_80211 = &(bcm->core_80211_ext[i]);
++                              if (!core->available)
++                                      break;
++                              core = NULL;
++                      }
++                      if (!core) {
++                              printk(KERN_WARNING PFX "More than %d cores of type 802.11 found.\n",
++                                     BCM43xx_MAX_80211_CORES);
++                              continue;
++                      }
++                      if (i != 0) {
++                              /* More than one 80211 core is only supported
++                               * by special chips.
++                               * There are chips with two 80211 cores, but with
++                               * dangling pins on the second core. Be careful
++                               * and ignore these cores here.
++                               */
++                              if (bcm->pci_dev->device != 0x4324) {
++                                      dprintk(KERN_INFO PFX "Ignoring additional 802.11 core.\n");
++                                      continue;
++                              }
++                      }
++                      switch (core_rev) {
++                      case 2:
++                      case 4:
++                      case 5:
++                      case 6:
++                      case 7:
++                      case 9:
++                              break;
++                      default:
++                              printk(KERN_ERR PFX "Error: Unsupported 80211 core revision %u\n",
++                                     core_rev);
++                              err = -ENODEV;
++                              goto out;
++                      }
++                      bcm->nr_80211_available++;
++                      bcm43xx_init_struct_phyinfo(&ext_80211->phy);
++                      bcm43xx_init_struct_radioinfo(&ext_80211->radio);
++                      break;
++              case BCM43xx_COREID_CHIPCOMMON:
++                      printk(KERN_WARNING PFX "Multiple CHIPCOMMON cores found.\n");
++                      break;
++              }
++              if (core) {
++                      core->available = 1;
++                      core->id = core_id;
++                      core->rev = core_rev;
++                      core->index = current_core;
++              }
++      }
++
++      if (!bcm->core_80211[0].available) {
++              printk(KERN_ERR PFX "Error: No 80211 core found!\n");
++              err = -ENODEV;
++              goto out;
++      }
++
++      err = bcm43xx_switch_core(bcm, &bcm->core_80211[0]);
++
++      assert(err == 0);
++out:
++      return err;
++}
++
++static void bcm43xx_gen_bssid(struct bcm43xx_private *bcm)
++{
++      const u8 *mac = (const u8*)(bcm->net_dev->dev_addr);
++      u8 *bssid = bcm->bssid;
++
++      switch (bcm->iw_mode) {
++      case IW_MODE_ADHOC:
++              random_ether_addr(bssid);
++              break;
++      case IW_MODE_MASTER:
++      case IW_MODE_INFRA:
++      case IW_MODE_REPEAT:
++      case IW_MODE_SECOND:
++      case IW_MODE_MONITOR:
++              memcpy(bssid, mac, ETH_ALEN);
++              break;
++      default:
++              assert(0);
++      }
++}
++
++static void bcm43xx_rate_memory_write(struct bcm43xx_private *bcm,
++                                    u16 rate,
++                                    int is_ofdm)
++{
++      u16 offset;
++
++      if (is_ofdm) {
++              offset = 0x480;
++              offset += (bcm43xx_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
++      } else {
++              offset = 0x4C0;
++              offset += (bcm43xx_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
++      }
++      bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, offset + 0x20,
++                          bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, offset));
++}
++
++static void bcm43xx_rate_memory_init(struct bcm43xx_private *bcm)
++{
++      switch (bcm43xx_current_phy(bcm)->type) {
++      case BCM43xx_PHYTYPE_A:
++      case BCM43xx_PHYTYPE_G:
++              bcm43xx_rate_memory_write(bcm, BCM43xx_OFDM_RATE_6MB, 1);
++              bcm43xx_rate_memory_write(bcm, BCM43xx_OFDM_RATE_12MB, 1);
++              bcm43xx_rate_memory_write(bcm, BCM43xx_OFDM_RATE_18MB, 1);
++              bcm43xx_rate_memory_write(bcm, BCM43xx_OFDM_RATE_24MB, 1);
++              bcm43xx_rate_memory_write(bcm, BCM43xx_OFDM_RATE_36MB, 1);
++              bcm43xx_rate_memory_write(bcm, BCM43xx_OFDM_RATE_48MB, 1);
++              bcm43xx_rate_memory_write(bcm, BCM43xx_OFDM_RATE_54MB, 1);
++      case BCM43xx_PHYTYPE_B:
++              bcm43xx_rate_memory_write(bcm, BCM43xx_CCK_RATE_1MB, 0);
++              bcm43xx_rate_memory_write(bcm, BCM43xx_CCK_RATE_2MB, 0);
++              bcm43xx_rate_memory_write(bcm, BCM43xx_CCK_RATE_5MB, 0);
++              bcm43xx_rate_memory_write(bcm, BCM43xx_CCK_RATE_11MB, 0);
++              break;
++      default:
++              assert(0);
++      }
++}
++
++static void bcm43xx_wireless_core_cleanup(struct bcm43xx_private *bcm)
++{
++      bcm43xx_chip_cleanup(bcm);
++      bcm43xx_pio_free(bcm);
++      bcm43xx_dma_free(bcm);
++
++      bcm->current_core->initialized = 0;
++}
++
++/* http://bcm-specs.sipsolutions.net/80211Init */
++static int bcm43xx_wireless_core_init(struct bcm43xx_private *bcm)
++{
++      struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
++      struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
++      u32 ucodeflags;
++      int err;
++      u32 sbimconfiglow;
++      u8 limit;
++
++      if (bcm->chip_rev < 5) {
++              sbimconfiglow = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
++              sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
++              sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
++              if (bcm->bustype == BCM43xx_BUSTYPE_PCI)
++                      sbimconfiglow |= 0x32;
++              else if (bcm->bustype == BCM43xx_BUSTYPE_SB)
++                      sbimconfiglow |= 0x53;
++              else
++                      assert(0);
++              bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, sbimconfiglow);
++      }
++
++      bcm43xx_phy_calibrate(bcm);
++      err = bcm43xx_chip_init(bcm);
++      if (err)
++              goto out;
++
++      bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0016, bcm->current_core->rev);
++      ucodeflags = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, BCM43xx_UCODEFLAGS_OFFSET);
++
++      if (0 /*FIXME: which condition has to be used here? */)
++              ucodeflags |= 0x00000010;
++
++      /* HW decryption needs to be set now. */
++      ucodeflags |= 0x40000000;
++
++      if (phy->type == BCM43xx_PHYTYPE_G) {
++              ucodeflags |= BCM43xx_UCODEFLAG_UNKBGPHY;
++              if (phy->rev == 1)
++                      ucodeflags |= BCM43xx_UCODEFLAG_UNKGPHY;
++              if (bcm->sprom.boardflags & BCM43xx_BFL_PACTRL)
++                      ucodeflags |= BCM43xx_UCODEFLAG_UNKPACTRL;
++      } else if (phy->type == BCM43xx_PHYTYPE_B) {
++              ucodeflags |= BCM43xx_UCODEFLAG_UNKBGPHY;
++              if (phy->rev >= 2 && radio->version == 0x2050)
++                      ucodeflags &= ~BCM43xx_UCODEFLAG_UNKGPHY;
++      }
++
++      if (ucodeflags != bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED,
++                                           BCM43xx_UCODEFLAGS_OFFSET)) {
++              bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED,
++                                  BCM43xx_UCODEFLAGS_OFFSET, ucodeflags);
++      }
++
++      /* Short/Long Retry Limit.
++       * The retry-limit is a 4-bit counter. Enforce this to avoid overflowing
++       * the chip-internal counter.
++       */
++      limit = limit_value(modparam_short_retry, 0, 0xF);
++      bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0006, limit);
++      limit = limit_value(modparam_long_retry, 0, 0xF);
++      bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0007, limit);
++
++      bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0044, 3);
++      bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0046, 2);
++
++      bcm43xx_rate_memory_init(bcm);
++
++      /* Minimum Contention Window */
++      if (phy->type == BCM43xx_PHYTYPE_B)
++              bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0003, 0x0000001f);
++      else
++              bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0003, 0x0000000f);
++      /* Maximum Contention Window */
++      bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0004, 0x000003ff);
++
++      bcm43xx_gen_bssid(bcm);
++      bcm43xx_write_mac_bssid_templates(bcm);
++
++      if (bcm->current_core->rev >= 5)
++              bcm43xx_write16(bcm, 0x043C, 0x000C);
++
++      if (bcm43xx_using_pio(bcm))
++              err = bcm43xx_pio_init(bcm);
++      else
++              err = bcm43xx_dma_init(bcm);
++      if (err)
++              goto err_chip_cleanup;
++      bcm43xx_write16(bcm, 0x0612, 0x0050);
++      bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0416, 0x0050);
++      bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0414, 0x01F4);
++
++      bcm43xx_mac_enable(bcm);
++      bcm43xx_interrupt_enable(bcm, bcm->irq_savedstate);
++
++      bcm->current_core->initialized = 1;
++out:
++      return err;
++
++err_chip_cleanup:
++      bcm43xx_chip_cleanup(bcm);
++      goto out;
++}
++
++static int bcm43xx_chipset_attach(struct bcm43xx_private *bcm)
++{
++      int err;
++      u16 pci_status;
++
++      err = bcm43xx_pctl_set_crystal(bcm, 1);
++      if (err)
++              goto out;
++      bcm43xx_pci_read_config16(bcm, PCI_STATUS, &pci_status);
++      bcm43xx_pci_write_config16(bcm, PCI_STATUS, pci_status & ~PCI_STATUS_SIG_TARGET_ABORT);
++
++out:
++      return err;
++}
++
++static void bcm43xx_chipset_detach(struct bcm43xx_private *bcm)
++{
++      bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_SLOW);
++      bcm43xx_pctl_set_crystal(bcm, 0);
++}
++
++static void bcm43xx_pcicore_broadcast_value(struct bcm43xx_private *bcm,
++                                          u32 address,
++                                          u32 data)
++{
++      bcm43xx_write32(bcm, BCM43xx_PCICORE_BCAST_ADDR, address);
++      bcm43xx_write32(bcm, BCM43xx_PCICORE_BCAST_DATA, data);
++}
++
++static int bcm43xx_pcicore_commit_settings(struct bcm43xx_private *bcm)
++{
++      int err;
++      struct bcm43xx_coreinfo *old_core;
++
++      old_core = bcm->current_core;
++      err = bcm43xx_switch_core(bcm, &bcm->core_pci);
++      if (err)
++              goto out;
++
++      bcm43xx_pcicore_broadcast_value(bcm, 0xfd8, 0x00000000);
++
++      bcm43xx_switch_core(bcm, old_core);
++      assert(err == 0);
++out:
++      return err;
++}
++
++/* Make an I/O Core usable. "core_mask" is the bitmask of the cores to enable.
++ * To enable core 0, pass a core_mask of 1<<0
++ */
++static int bcm43xx_setup_backplane_pci_connection(struct bcm43xx_private *bcm,
++                                                u32 core_mask)
++{
++      u32 backplane_flag_nr;
++      u32 value;
++      struct bcm43xx_coreinfo *old_core;
++      int err = 0;
++
++      value = bcm43xx_read32(bcm, BCM43xx_CIR_SBTPSFLAG);
++      backplane_flag_nr = value & BCM43xx_BACKPLANE_FLAG_NR_MASK;
++
++      old_core = bcm->current_core;
++      err = bcm43xx_switch_core(bcm, &bcm->core_pci);
++      if (err)
++              goto out;
++
++      if (bcm->core_pci.rev < 6) {
++              value = bcm43xx_read32(bcm, BCM43xx_CIR_SBINTVEC);
++              value |= (1 << backplane_flag_nr);
++              bcm43xx_write32(bcm, BCM43xx_CIR_SBINTVEC, value);
++      } else {
++              err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_ICR, &value);
++              if (err) {
++                      printk(KERN_ERR PFX "Error: ICR setup failure!\n");
++                      goto out_switch_back;
++              }
++              value |= core_mask << 8;
++              err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_ICR, value);
++              if (err) {
++                      printk(KERN_ERR PFX "Error: ICR setup failure!\n");
++                      goto out_switch_back;
++              }
++      }
++
++      value = bcm43xx_read32(bcm, BCM43xx_PCICORE_SBTOPCI2);
++      value |= BCM43xx_SBTOPCI2_PREFETCH | BCM43xx_SBTOPCI2_BURST;
++      bcm43xx_write32(bcm, BCM43xx_PCICORE_SBTOPCI2, value);
++
++      if (bcm->core_pci.rev < 5) {
++              value = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
++              value |= (2 << BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_SHIFT)
++                       & BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
++              value |= (3 << BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_SHIFT)
++                       & BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
++              bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, value);
++              err = bcm43xx_pcicore_commit_settings(bcm);
++              assert(err == 0);
++      }
++
++out_switch_back:
++      err = bcm43xx_switch_core(bcm, old_core);
++out:
++      return err;
++}
++
++static void bcm43xx_periodic_every120sec(struct bcm43xx_private *bcm)
++{
++      struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
++
++      if (phy->type != BCM43xx_PHYTYPE_G || phy->rev < 2)
++              return;
++
++      bcm43xx_mac_suspend(bcm);
++      bcm43xx_phy_lo_g_measure(bcm);
++      bcm43xx_mac_enable(bcm);
++}
++
++static void bcm43xx_periodic_every60sec(struct bcm43xx_private *bcm)
++{
++      bcm43xx_phy_lo_mark_all_unused(bcm);
++      if (bcm->sprom.boardflags & BCM43xx_BFL_RSSI) {
++              bcm43xx_mac_suspend(bcm);
++              bcm43xx_calc_nrssi_slope(bcm);
++              bcm43xx_mac_enable(bcm);
++      }
++}
++
++static void bcm43xx_periodic_every30sec(struct bcm43xx_private *bcm)
++{
++      /* Update device statistics. */
++      bcm43xx_calculate_link_quality(bcm);
++}
++
++static void bcm43xx_periodic_every15sec(struct bcm43xx_private *bcm)
++{
++      struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
++      struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
++
++      if (phy->type == BCM43xx_PHYTYPE_G) {
++              //TODO: update_aci_moving_average
++              if (radio->aci_enable && radio->aci_wlan_automatic) {
++                      bcm43xx_mac_suspend(bcm);
++                      if (!radio->aci_enable && 1 /*TODO: not scanning? */) {
++                              if (0 /*TODO: bunch of conditions*/) {
++                                      bcm43xx_radio_set_interference_mitigation(bcm,
++                                                                                BCM43xx_RADIO_INTERFMODE_MANUALWLAN);
++                              }
++                      } else if (1/*TODO*/) {
++                              /*
++                              if ((aci_average > 1000) && !(bcm43xx_radio_aci_scan(bcm))) {
++                                      bcm43xx_radio_set_interference_mitigation(bcm,
++                                                                                BCM43xx_RADIO_INTERFMODE_NONE);
++                              }
++                              */
++                      }
++                      bcm43xx_mac_enable(bcm);
++              } else if (radio->interfmode == BCM43xx_RADIO_INTERFMODE_NONWLAN &&
++                         phy->rev == 1) {
++                      //TODO: implement rev1 workaround
++              }
++      }
++      bcm43xx_phy_xmitpower(bcm); //FIXME: unless scanning?
++      //TODO for APHY (temperature?)
++}
++
++static void bcm43xx_periodic_task_handler(unsigned long d)
++{
++      struct bcm43xx_private *bcm = (struct bcm43xx_private *)d;
++      unsigned long flags;
++      unsigned int state;
++
++      bcm43xx_lock_mmio(bcm, flags);
++
++      assert(bcm->initialized);
++      state = bcm->periodic_state;
++      if (state % 8 == 0)
++              bcm43xx_periodic_every120sec(bcm);
++      if (state % 4 == 0)
++              bcm43xx_periodic_every60sec(bcm);
++      if (state % 2 == 0)
++              bcm43xx_periodic_every30sec(bcm);
++      bcm43xx_periodic_every15sec(bcm);
++      bcm->periodic_state = state + 1;
++
++      mod_timer(&bcm->periodic_tasks, jiffies + (HZ * 15));
++
++      bcm43xx_unlock_mmio(bcm, flags);
++}
++
++static void bcm43xx_periodic_tasks_delete(struct bcm43xx_private *bcm)
++{
++      del_timer_sync(&bcm->periodic_tasks);
++}
++
++static void bcm43xx_periodic_tasks_setup(struct bcm43xx_private *bcm)
++{
++      struct timer_list *timer = &(bcm->periodic_tasks);
++
++      assert(bcm->initialized);
++      setup_timer(timer,
++                  bcm43xx_periodic_task_handler,
++                  (unsigned long)bcm);
++      timer->expires = jiffies;
++      add_timer(timer);
++}
++
++static void bcm43xx_free_modes(struct bcm43xx_private *bcm)
++{
++      struct ieee80211_hw *ieee = bcm->ieee;
++      int i;
++
++      for (i = 0; i < ieee->num_modes; i++) {
++              kfree(ieee->modes[i].channels);
++              kfree(ieee->modes[i].rates);
++      }
++      kfree(ieee->modes);
++      ieee->modes = NULL;
++      ieee->num_modes = 0;
++}
++
++static int bcm43xx_append_mode(struct ieee80211_hw *ieee,
++                             int mode_id,
++                             int nr_channels,
++                             const struct ieee80211_channel *channels,
++                             int nr_rates,
++                             const struct ieee80211_rate *rates)
++{
++      struct ieee80211_hw_modes *mode;
++      int err = -ENOMEM;
++
++      mode = &(ieee->modes[ieee->num_modes]);
++
++      mode->mode = mode_id;
++      mode->num_channels = nr_channels;
++      mode->channels = kzalloc(sizeof(*channels) * nr_channels, GFP_KERNEL);
++      if (!mode->channels)
++              goto out;
++      memcpy(mode->channels, channels, sizeof(*channels) * nr_channels);
++
++      mode->num_rates = nr_rates;
++      mode->rates = kzalloc(sizeof(*rates) * nr_rates, GFP_KERNEL);
++      if (!mode->rates)
++              goto err_free_channels;
++      memcpy(mode->rates, rates, sizeof(*rates) * nr_rates);
++
++      ieee->num_modes++;
++      err = 0;
++out:
++      return err;
++
++err_free_channels:
++      kfree(mode->channels);
++      goto out;
++}
++
++static int bcm43xx_setup_modes_aphy(struct bcm43xx_private *bcm)
++{
++      int err = 0;
++
++      static const struct ieee80211_rate rates[] = {
++              {
++                      .rate   = 60,
++                      .val    = BCM43xx_OFDM_RATE_6MB,
++                      .flags  = IEEE80211_RATE_OFDM,
++                      .val2   = BCM43xx_OFDM_RATE_6MB,
++              }, {
++                      .rate   = 90,
++                      .val    = BCM43xx_OFDM_RATE_9MB,
++                      .flags  = IEEE80211_RATE_OFDM,
++                      .val2   = BCM43xx_OFDM_RATE_9MB,
++              }, {
++                      .rate   = 120,
++                      .val    = BCM43xx_OFDM_RATE_12MB,
++                      .flags  = IEEE80211_RATE_OFDM,
++                      .val2   = BCM43xx_OFDM_RATE_12MB,
++              }, {
++                      .rate   = 180,
++                      .val    = BCM43xx_OFDM_RATE_18MB,
++                      .flags  = IEEE80211_RATE_OFDM,
++                      .val2   = BCM43xx_OFDM_RATE_18MB,
++              }, {
++                      .rate   = 240,
++                      .val    = BCM43xx_OFDM_RATE_24MB,
++                      .flags  = IEEE80211_RATE_OFDM,
++                      .val2   = BCM43xx_OFDM_RATE_24MB,
++              }, {
++                      .rate   = 360,
++                      .val    = BCM43xx_OFDM_RATE_36MB,
++                      .flags  = IEEE80211_RATE_OFDM,
++                      .val2   = BCM43xx_OFDM_RATE_36MB,
++              }, {
++                      .rate   = 480,
++                      .val    = BCM43xx_OFDM_RATE_48MB,
++                      .flags  = IEEE80211_RATE_OFDM,
++                      .val2   = BCM43xx_OFDM_RATE_48MB,
++              }, {
++                      .rate   = 540,
++                      .val    = BCM43xx_OFDM_RATE_54MB,
++                      .flags  = IEEE80211_RATE_OFDM,
++                      .val2   = BCM43xx_OFDM_RATE_54MB,
++              },
++      };
++      static const struct ieee80211_channel channels[] = {
++              {
++                      .chan           = 36,
++                      .freq           = 5180,
++                      .val            = 36,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 40,
++                      .freq           = 5200,
++                      .val            = 40,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 44,
++                      .freq           = 5220,
++                      .val            = 44,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 48,
++                      .freq           = 5240,
++                      .val            = 48,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 52,
++                      .freq           = 5260,
++                      .val            = 52,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 56,
++                      .freq           = 5280,
++                      .val            = 56,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 60,
++                      .freq           = 5300,
++                      .val            = 60,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 64,
++                      .freq           = 5320,
++                      .val            = 64,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 149,
++                      .freq           = 5745,
++                      .val            = 149,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 153,
++                      .freq           = 5765,
++                      .val            = 153,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 157,
++                      .freq           = 5785,
++                      .val            = 157,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 161,
++                      .freq           = 5805,
++                      .val            = 161,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 165,
++                      .freq           = 5825,
++                      .val            = 165,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              },
++      };
++
++      if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_A) {
++              err = bcm43xx_append_mode(bcm->ieee, MODE_IEEE80211A,
++                                        ARRAY_SIZE(channels), channels,
++                                        ARRAY_SIZE(rates), rates);
++      }
++
++      return err;
++}
++
++static int bcm43xx_setup_modes_bphy(struct bcm43xx_private *bcm)
++{
++      int err = 0;
++
++      static const struct ieee80211_rate rates[] = {
++              {
++                      .rate   = 10,
++                      .val    = BCM43xx_CCK_RATE_1MB,
++                      .flags  = IEEE80211_RATE_CCK,
++                      .val2   = BCM43xx_CCK_RATE_1MB,
++              }, {
++                      .rate   = 20,
++                      .val    = BCM43xx_CCK_RATE_2MB,
++                      .flags  = IEEE80211_RATE_CCK_2,
++                      .val2   = BCM43xx_CCK_RATE_2MB,
++              }, {
++                      .rate   = 55,
++                      .val    = BCM43xx_CCK_RATE_5MB,
++                      .flags  = IEEE80211_RATE_CCK_2,
++                      .val2   = BCM43xx_CCK_RATE_5MB,
++              }, {
++                      .rate   = 110,
++                      .val    = BCM43xx_CCK_RATE_11MB,
++                      .flags  = IEEE80211_RATE_CCK_2,
++                      .val2   = BCM43xx_CCK_RATE_11MB,
++              },
++      };
++      static const struct ieee80211_channel channels[] = {
++              {
++                      .chan           = 1,
++                      .freq           = 2412,
++                      .val            = 1,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 2,
++                      .freq           = 2417,
++                      .val            = 2,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 3,
++                      .freq           = 2422,
++                      .val            = 3,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 4,
++                      .freq           = 2427,
++                      .val            = 4,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 5,
++                      .freq           = 2432,
++                      .val            = 5,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 6,
++                      .freq           = 2437,
++                      .val            = 6,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 7,
++                      .freq           = 2442,
++                      .val            = 7,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 8,
++                      .freq           = 2447,
++                      .val            = 8,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 9,
++                      .freq           = 2452,
++                      .val            = 9,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 10,
++                      .freq           = 2457,
++                      .val            = 10,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 11,
++                      .freq           = 2462,
++                      .val            = 11,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 12,
++                      .freq           = 2467,
++                      .val            = 12,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 13,
++                      .freq           = 2472,
++                      .val            = 13,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, /*{
++                      .chan           = 14,
++                      .freq           = 2484,
++                      .val            = 14,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              },*/
++      };
++
++      if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_B ||
++          bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_G) {
++              err = bcm43xx_append_mode(bcm->ieee, MODE_IEEE80211B,
++                                        ARRAY_SIZE(channels), channels,
++                                        ARRAY_SIZE(rates), rates);
++      }
++
++      return err;
++}
++
++static int bcm43xx_setup_modes_gphy(struct bcm43xx_private *bcm)
++{
++      int err = 0;
++
++      static const struct ieee80211_rate rates[] = {
++              {
++                      .rate   = 10,
++                      .val    = BCM43xx_CCK_RATE_1MB,
++                      .flags  = IEEE80211_RATE_CCK,
++                      .val2   = BCM43xx_CCK_RATE_1MB,
++              }, {
++                      .rate   = 20,
++                      .val    = BCM43xx_CCK_RATE_2MB,
++                      .flags  = IEEE80211_RATE_CCK_2,
++                      .val2   = BCM43xx_CCK_RATE_2MB,
++              }, {
++                      .rate   = 55,
++                      .val    = BCM43xx_CCK_RATE_5MB,
++                      .flags  = IEEE80211_RATE_CCK_2,
++                      .val2   = BCM43xx_CCK_RATE_5MB,
++              }, {
++                      .rate   = 60,
++                      .val    = BCM43xx_OFDM_RATE_6MB,
++                      .flags  = IEEE80211_RATE_OFDM,
++                      .val2   = BCM43xx_OFDM_RATE_6MB,
++              }, {
++                      .rate   = 90,
++                      .val    = BCM43xx_OFDM_RATE_9MB,
++                      .flags  = IEEE80211_RATE_OFDM,
++                      .val2   = BCM43xx_OFDM_RATE_9MB,
++              }, {
++                      .rate   = 110,
++                      .val    = BCM43xx_CCK_RATE_11MB,
++                      .flags  = IEEE80211_RATE_CCK_2,
++                      .val2   = BCM43xx_CCK_RATE_11MB,
++              }, {
++                      .rate   = 120,
++                      .val    = BCM43xx_OFDM_RATE_12MB,
++                      .flags  = IEEE80211_RATE_OFDM,
++                      .val2   = BCM43xx_OFDM_RATE_12MB,
++              }, {
++                      .rate   = 180,
++                      .val    = BCM43xx_OFDM_RATE_18MB,
++                      .flags  = IEEE80211_RATE_OFDM,
++                      .val2   = BCM43xx_OFDM_RATE_18MB,
++              }, {
++                      .rate   = 240,
++                      .val    = BCM43xx_OFDM_RATE_24MB,
++                      .flags  = IEEE80211_RATE_OFDM,
++                      .val2   = BCM43xx_OFDM_RATE_24MB,
++              }, {
++                      .rate   = 360,
++                      .val    = BCM43xx_OFDM_RATE_36MB,
++                      .flags  = IEEE80211_RATE_OFDM,
++                      .val2   = BCM43xx_OFDM_RATE_36MB,
++              }, {
++                      .rate   = 480,
++                      .val    = BCM43xx_OFDM_RATE_48MB,
++                      .flags  = IEEE80211_RATE_OFDM,
++                      .val2   = BCM43xx_OFDM_RATE_48MB,
++              }, {
++                      .rate   = 540,
++                      .val    = BCM43xx_OFDM_RATE_54MB,
++                      .flags  = IEEE80211_RATE_OFDM,
++                      .val2   = BCM43xx_OFDM_RATE_54MB,
++              },
++      };
++      static const struct ieee80211_channel channels[] = {
++              {
++                      .chan           = 1,
++                      .freq           = 2412,
++                      .val            = 1,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 2,
++                      .freq           = 2417,
++                      .val            = 2,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 3,
++                      .freq           = 2422,
++                      .val            = 3,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 4,
++                      .freq           = 2427,
++                      .val            = 4,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 5,
++                      .freq           = 2432,
++                      .val            = 5,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 6,
++                      .freq           = 2437,
++                      .val            = 6,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 7,
++                      .freq           = 2442,
++                      .val            = 7,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 8,
++                      .freq           = 2447,
++                      .val            = 8,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 9,
++                      .freq           = 2452,
++                      .val            = 9,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 10,
++                      .freq           = 2457,
++                      .val            = 10,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 11,
++                      .freq           = 2462,
++                      .val            = 11,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 12,
++                      .freq           = 2467,
++                      .val            = 12,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, {
++                      .chan           = 13,
++                      .freq           = 2472,
++                      .val            = 13,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              }, /*{
++                      .chan           = 14,
++                      .freq           = 2484,
++                      .val            = 14,
++                      .flag           = IEEE80211_CHAN_W_SCAN |
++                                        IEEE80211_CHAN_W_ACTIVE_SCAN |
++                                        IEEE80211_CHAN_W_IBSS,
++                      .power_level    = 0xFF,
++                      .antenna_max    = 0xFF,
++              },*/
++      };
++
++      if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_G) {
++              err = bcm43xx_append_mode(bcm->ieee, MODE_IEEE80211G,
++                                        ARRAY_SIZE(channels), channels,
++                                        ARRAY_SIZE(rates), rates);
++      }
++
++      return err;
++}
++
++static int bcm43xx_setup_modes(struct bcm43xx_private *bcm)
++{
++      struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
++      int err = -ENOMEM;
++      int nr;
++      struct ieee80211_hw *ieee = bcm->ieee;
++
++      if (phy->type == BCM43xx_PHYTYPE_A)
++              nr = 1;
++      else if (phy->type == BCM43xx_PHYTYPE_B)
++              nr = 1;
++      else
++              nr = 2;
++      ieee->modes = kzalloc(sizeof(*(ieee->modes)) * nr, GFP_KERNEL);
++      if (!ieee->modes)
++              goto out;
++      ieee->num_modes = 0;
++
++      err = bcm43xx_setup_modes_aphy(bcm);
++      if (err)
++              goto error;
++      err = bcm43xx_setup_modes_gphy(bcm);
++      if (err)
++              goto error;
++      err = bcm43xx_setup_modes_bphy(bcm);
++      if (err)
++              goto error;
++
++      assert(ieee->num_modes == nr && nr > 0);
++out:
++      return err;
++
++error:
++      bcm43xx_free_modes(bcm);
++      goto out;
++}
++
++static void bcm43xx_security_init(struct bcm43xx_private *bcm)
++{
++      bcm->security_offset = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
++                                                0x0056) * 2;
++      bcm43xx_clear_keys(bcm);
++}
++
++/* This is the opposite of bcm43xx_init_board() */
++static void bcm43xx_free_board(struct bcm43xx_private *bcm)
++{
++      int i, err;
++      unsigned long flags;
++
++      bcm43xx_sysfs_unregister(bcm);
++
++      bcm43xx_periodic_tasks_delete(bcm);
++
++      bcm43xx_lock(bcm, flags);
++      bcm->initialized = 0;
++      bcm->shutting_down = 1;
++      bcm43xx_unlock(bcm, flags);
++
++      for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
++              if (!bcm->core_80211[i].available)
++                      continue;
++              if (!bcm->core_80211[i].initialized)
++                      continue;
++
++              err = bcm43xx_switch_core(bcm, &bcm->core_80211[i]);
++              assert(err == 0);
++              bcm43xx_wireless_core_cleanup(bcm);
++      }
++
++      bcm43xx_pctl_set_crystal(bcm, 0);
++      bcm43xx_free_modes(bcm);
++
++      bcm43xx_lock(bcm, flags);
++      bcm->shutting_down = 0;
++      bcm43xx_unlock(bcm, flags);
++}
++
++static int bcm43xx_init_board(struct bcm43xx_private *bcm)
++{
++      int i, err;
++      int connect_phy;
++      unsigned long flags;
++
++      might_sleep();
++
++      bcm43xx_lock(bcm, flags);
++      bcm->initialized = 0;
++      bcm->shutting_down = 0;
++      bcm43xx_unlock(bcm, flags);
++
++      err = bcm43xx_pctl_set_crystal(bcm, 1);
++      if (err)
++              goto out;
++      err = bcm43xx_pctl_init(bcm);
++      if (err)
++              goto err_crystal_off;
++      err = bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_FAST);
++      if (err)
++              goto err_crystal_off;
++
++      tasklet_enable(&bcm->isr_tasklet);
++      for (i = 0; i < bcm->nr_80211_available; i++) {
++              err = bcm43xx_switch_core(bcm, &bcm->core_80211[i]);
++              assert(err != -ENODEV);
++              if (err)
++                      goto err_80211_unwind;
++
++              /* Enable the selected wireless core.
++               * Connect PHY only on the first core.
++               */
++              if (!bcm43xx_core_enabled(bcm)) {
++                      if (bcm->nr_80211_available == 1) {
++                              connect_phy = bcm43xx_current_phy(bcm)->connected;
++                      } else {
++                              if (i == 0)
++                                      connect_phy = 1;
++                              else
++                                      connect_phy = 0;
++                      }
++                      bcm43xx_wireless_core_reset(bcm, connect_phy);
++              }
++
++              if (i != 0)
++                      bcm43xx_wireless_core_mark_inactive(bcm, &bcm->core_80211[0]);
++
++              err = bcm43xx_wireless_core_init(bcm);
++              if (err)
++                      goto err_80211_unwind;
++
++              if (i != 0) {
++                      bcm43xx_mac_suspend(bcm);
++                      bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
++                      bcm43xx_radio_turn_off(bcm);
++              }
++      }
++      bcm->active_80211_core = &bcm->core_80211[0];
++      if (bcm->nr_80211_available >= 2) {
++              bcm43xx_switch_core(bcm, &bcm->core_80211[0]);
++              bcm43xx_mac_enable(bcm);
++      }
++      bcm43xx_macfilter_clear(bcm, BCM43xx_MACFILTER_ASSOC);
++      bcm43xx_macfilter_set(bcm, BCM43xx_MACFILTER_SELF, (u8 *)(bcm->net_dev->dev_addr));
++      dprintk(KERN_INFO PFX "80211 cores initialized\n");
++      bcm43xx_setup_modes(bcm);
++      bcm43xx_security_init(bcm);
++      ieee80211_update_hw(bcm->net_dev, bcm->ieee);
++      ieee80211_netif_oper(bcm->net_dev, NETIF_ATTACH);
++      ieee80211_netif_oper(bcm->net_dev, NETIF_START);
++      ieee80211_netif_oper(bcm->net_dev, NETIF_WAKE);
++
++      bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_DYNAMIC);
++
++      if (bcm43xx_current_radio(bcm)->initial_channel != 0xFF) {
++              bcm43xx_mac_suspend(bcm);
++              bcm43xx_radio_selectchannel(bcm, bcm43xx_current_radio(bcm)->initial_channel, 0);
++              bcm43xx_mac_enable(bcm);
++      }
++
++      /* Initialization of the board is done. Flag it as such. */
++      bcm43xx_lock(bcm, flags);
++      bcm->initialized = 1;
++      bcm43xx_unlock(bcm, flags);
++
++      bcm43xx_periodic_tasks_setup(bcm);
++      bcm43xx_sysfs_register(bcm);
++
++      assert(err == 0);
++out:
++      return err;
++
++err_80211_unwind:
++      tasklet_disable(&bcm->isr_tasklet);
++      /* unwind all 80211 initialization */
++      for (i = 0; i < bcm->nr_80211_available; i++) {
++              if (!bcm->core_80211[i].initialized)
++                      continue;
++              bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
++              bcm43xx_wireless_core_cleanup(bcm);
++      }
++err_crystal_off:
++      bcm43xx_pctl_set_crystal(bcm, 0);
++      goto out;
++}
++
++static void bcm43xx_detach_board(struct bcm43xx_private *bcm)
++{
++      struct pci_dev *pci_dev = bcm->pci_dev;
++      int i;
++
++      bcm43xx_chipset_detach(bcm);
++      /* Do _not_ access the chip, after it is detached. */
++      iounmap(bcm->mmio_addr);
++
++      pci_release_regions(pci_dev);
++      pci_disable_device(pci_dev);
++
++      /* Free allocated structures/fields */
++      for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
++              kfree(bcm->core_80211_ext[i].phy._lo_pairs);
++              if (bcm->core_80211_ext[i].phy.dyn_tssi_tbl)
++                      kfree(bcm->core_80211_ext[i].phy.tssi2dbm);
++      }
++}
++
++static int bcm43xx_read_phyinfo(struct bcm43xx_private *bcm)
++{
++      struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
++      u16 value;
++      u8 phy_version;
++      u8 phy_type;
++      u8 phy_rev;
++      int phy_rev_ok = 1;
++      void *p;
++
++      value = bcm43xx_read16(bcm, BCM43xx_MMIO_PHY_VER);
++
++      phy_version = (value & 0xF000) >> 12;
++      phy_type = (value & 0x0F00) >> 8;
++      phy_rev = (value & 0x000F);
++
++      dprintk(KERN_INFO PFX "Detected PHY: Version: %x, Type %x, Revision %x\n",
++              phy_version, phy_type, phy_rev);
++
++      switch (phy_type) {
++      case BCM43xx_PHYTYPE_A:
++              if (phy_rev >= 4)
++                      phy_rev_ok = 0;
++              break;
++      case BCM43xx_PHYTYPE_B:
++              if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6 && phy_rev != 7)
++                      phy_rev_ok = 0;
++              break;
++      case BCM43xx_PHYTYPE_G:
++              if (phy_rev > 7)
++                      phy_rev_ok = 0;
++              break;
++      default:
++              printk(KERN_ERR PFX "Error: Unknown PHY Type %x\n",
++                     phy_type);
++              return -ENODEV;
++      };
++      if (!phy_rev_ok) {
++              printk(KERN_WARNING PFX "Invalid PHY Revision %x\n",
++                     phy_rev);
++      }
++
++      phy->version = phy_version;
++      phy->type = phy_type;
++      phy->rev = phy_rev;
++      if ((phy_type == BCM43xx_PHYTYPE_B) || (phy_type == BCM43xx_PHYTYPE_G)) {
++              p = kzalloc(sizeof(struct bcm43xx_lopair) * BCM43xx_LO_COUNT,
++                          GFP_KERNEL);
++              if (!p)
++                      return -ENOMEM;
++              phy->_lo_pairs = p;
++      }
++
++      return 0;
++}
++
++static int bcm43xx_attach_board(struct bcm43xx_private *bcm)
++{
++      struct pci_dev *pci_dev = bcm->pci_dev;
++      struct net_device *net_dev = bcm->net_dev;
++      int err;
++      int i;
++      unsigned long mmio_start, mmio_flags, mmio_len;
++      u32 coremask;
++
++      err = pci_enable_device(pci_dev);
++      if (err) {
++              printk(KERN_ERR PFX "unable to wake up pci device (%i)\n", err);
++              goto out;
++      }
++      mmio_start = pci_resource_start(pci_dev, 0);
++      mmio_flags = pci_resource_flags(pci_dev, 0);
++      mmio_len = pci_resource_len(pci_dev, 0);
++      if (!(mmio_flags & IORESOURCE_MEM)) {
++              printk(KERN_ERR PFX
++                     "%s, region #0 not an MMIO resource, aborting\n",
++                     pci_name(pci_dev));
++              err = -ENODEV;
++              goto err_pci_disable;
++      }
++      err = pci_request_regions(pci_dev, KBUILD_MODNAME);
++      if (err) {
++              printk(KERN_ERR PFX
++                     "could not access PCI resources (%i)\n", err);
++              goto err_pci_disable;
++      }
++      /* enable PCI bus-mastering */
++      pci_set_master(pci_dev);
++      bcm->mmio_addr = ioremap(mmio_start, mmio_len);
++      if (!bcm->mmio_addr) {
++              printk(KERN_ERR PFX "%s: cannot remap MMIO, aborting\n",
++                     pci_name(pci_dev));
++              err = -EIO;
++              goto err_pci_release;
++      }
++      bcm->mmio_len = mmio_len;
++      net_dev->base_addr = (unsigned long)bcm->mmio_addr;
++
++      bcm43xx_pci_read_config16(bcm, PCI_SUBSYSTEM_VENDOR_ID,
++                                &bcm->board_vendor);
++      bcm43xx_pci_read_config16(bcm, PCI_SUBSYSTEM_ID,
++                                &bcm->board_type);
++      bcm43xx_pci_read_config16(bcm, PCI_REVISION_ID,
++                                &bcm->board_revision);
++
++      err = bcm43xx_chipset_attach(bcm);
++      if (err)
++              goto err_iounmap;
++      err = bcm43xx_pctl_init(bcm);
++      if (err)
++              goto err_chipset_detach;
++      err = bcm43xx_probe_cores(bcm);
++      if (err)
++              goto err_chipset_detach;
++      
++      /* Attach all IO cores to the backplane. */
++      coremask = 0;
++      for (i = 0; i < bcm->nr_80211_available; i++)
++              coremask |= (1 << bcm->core_80211[i].index);
++      //FIXME: Also attach some non80211 cores?
++      err = bcm43xx_setup_backplane_pci_connection(bcm, coremask);
++      if (err) {
++              printk(KERN_ERR PFX "Backplane->PCI connection failed!\n");
++              goto err_chipset_detach;
++      }
++
++      err = bcm43xx_sprom_extract(bcm);
++      if (err)
++              goto err_chipset_detach;
++      err = bcm43xx_leds_init(bcm);
++      if (err)
++              goto err_chipset_detach;
++
++      for (i = 0; i < bcm->nr_80211_available; i++) {
++              err = bcm43xx_switch_core(bcm, &bcm->core_80211[i]);
++              assert(err != -ENODEV);
++              if (err)
++                      goto err_80211_unwind;
++
++              /* Enable the selected wireless core.
++               * Connect PHY only on the first core.
++               */
++              bcm43xx_wireless_core_reset(bcm, (i == 0));
++
++              err = bcm43xx_read_phyinfo(bcm);
++              if (err && (i == 0))
++                      goto err_80211_unwind;
++
++              err = bcm43xx_read_radioinfo(bcm);
++              if (err && (i == 0))
++                      goto err_80211_unwind;
++
++              err = bcm43xx_validate_chip(bcm);
++              if (err && (i == 0))
++                      goto err_80211_unwind;
++
++              bcm43xx_radio_turn_off(bcm);
++              err = bcm43xx_phy_init_tssi2dbm_table(bcm);
++              if (err)
++                      goto err_80211_unwind;
++              bcm43xx_wireless_core_disable(bcm);
++      }
++      bcm43xx_pctl_set_crystal(bcm, 0);
++
++      /* Set the MAC address in the networking subsystem */
++      if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_A)
++              memcpy(bcm->net_dev->dev_addr, bcm->sprom.et1macaddr, 6);
++      else
++              memcpy(bcm->net_dev->dev_addr, bcm->sprom.il0macaddr, 6);
++
++      snprintf(bcm->nick, IW_ESSID_MAX_SIZE,
++               "Broadcom %04X", bcm->chip_id);
++
++      assert(err == 0);
++out:
++      return err;
++
++err_80211_unwind:
++      for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
++              kfree(bcm->core_80211_ext[i].phy._lo_pairs);
++              if (bcm->core_80211_ext[i].phy.dyn_tssi_tbl)
++                      kfree(bcm->core_80211_ext[i].phy.tssi2dbm);
++      }
++err_chipset_detach:
++      bcm43xx_chipset_detach(bcm);
++err_iounmap:
++      iounmap(bcm->mmio_addr);
++err_pci_release:
++      pci_release_regions(pci_dev);
++err_pci_disable:
++      pci_disable_device(pci_dev);
++      goto out;
++}
++
++/* hard_start_xmit() callback in struct ieee80211_device */
++static int bcm43xx_net_hard_start_xmit(struct net_device *net_dev,
++                                     struct sk_buff *skb,
++                                     struct ieee80211_tx_control *ctl)
++{
++      struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
++      int err = -ENODEV;
++      unsigned long flags;
++
++      bcm43xx_lock_mmio(bcm, flags);
++      if (likely(bcm->initialized)) {
++              if (bcm43xx_using_pio(bcm))
++                      err = bcm43xx_pio_tx(bcm, skb, ctl);
++              else
++                      err = bcm43xx_dma_tx(bcm, skb, ctl);
++      }
++      bcm43xx_unlock_mmio(bcm, flags);
++
++      return err;
++}
++
++static int bcm43xx_net_reset(struct net_device *net_dev)
++{
++      struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
++      unsigned long flags;
++
++      bcm43xx_lock_mmio(bcm, flags);
++      bcm43xx_controller_restart(bcm, "IEEE reset");
++      bcm43xx_unlock_mmio(bcm, flags);
++
++      return 0;
++}
++
++static int bcm43xx_net_config(struct net_device *net_dev,
++                            struct ieee80211_conf *conf)
++{
++      struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
++      struct bcm43xx_radioinfo *radio;
++      struct bcm43xx_phyinfo *phy;
++      unsigned long flags;
++
++      bcm43xx_lock_mmio(bcm, flags);
++      if (!bcm->initialized) {
++              bcm43xx_unlock_mmio(bcm, flags);
++              return 0;
++      }
++      radio = bcm43xx_current_radio(bcm);
++      phy = bcm43xx_current_phy(bcm);
++
++      if (conf->channel != radio->channel)
++              bcm43xx_radio_selectchannel(bcm, conf->channel, 0);
++
++      if (conf->mode != bcm->iw_mode)
++              bcm43xx_set_iwmode(bcm, conf->mode);
++
++      if (conf->short_slot_time != bcm->short_slot) {
++              assert(phy->type == BCM43xx_PHYTYPE_G);
++              if (conf->short_slot_time)
++                      bcm43xx_short_slot_timing_enable(bcm);
++              else
++                      bcm43xx_short_slot_timing_disable(bcm);
++      }
++
++      if (conf->power_level != 0) {
++              radio->power_level = conf->power_level;
++              bcm43xx_phy_xmitpower(bcm);
++      }
++//FIXME: This does not seem to wake up:
++#if 0
++      if (conf->power_level == 0) {
++              if (radio->enabled)
++                      bcm43xx_radio_turn_off(bcm);
++      } else {
++              if (!radio->enabled)
++                      bcm43xx_radio_turn_on(bcm);
++      }
++#endif
++
++      //TODO: phymode
++      //TODO: antennas
++
++      bcm43xx_unlock_mmio(bcm, flags);
++
++      return 0;
++}
++
++static int bcm43xx_net_set_key(struct net_device *net_dev,
++                             set_key_cmd cmd,
++                             u8 *addr,
++                             struct ieee80211_key_conf *key,
++                             int aid)
++{
++      struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
++      unsigned long flags;
++      u8 algorithm;
++      u8 index;
++      int err = -EINVAL;
++
++      switch (key->alg) {
++      default:
++      case ALG_NONE:
++      case ALG_NULL:
++              algorithm = BCM43xx_SEC_ALGO_NONE;
++              break;
++      case ALG_WEP:
++              if (key->keylen == 5)
++                      algorithm = BCM43xx_SEC_ALGO_WEP;
++              else
++                      algorithm = BCM43xx_SEC_ALGO_WEP104;
++              break;
++      case ALG_TKIP:
++              algorithm = BCM43xx_SEC_ALGO_TKIP;
++              break;
++      case ALG_CCMP:
++              algorithm = BCM43xx_SEC_ALGO_AES;
++              break;
++      }
++
++      index = (u8)(key->keyidx);
++      if (index >= ARRAY_SIZE(bcm->key))
++              goto out;
++      bcm43xx_lock_mmio(bcm, flags);
++      switch (cmd) {
++      case SET_KEY:
++              err = bcm43xx_key_write(bcm, index, algorithm,
++                                      key->key, key->keylen,
++                                      addr);
++              if (err)
++                      goto out_unlock;
++              key->hw_key_idx = index;
++              key->force_sw_encrypt = 0;
++              if (key->default_tx_key)
++                      bcm->default_key_idx = index;
++              bcm->key[index].enabled = 1;
++              break;
++      case DISABLE_KEY:
++              bcm->key[index].enabled = 0;
++              err = 0;
++              break;
++      case REMOVE_ALL_KEYS:
++              bcm43xx_clear_keys(bcm);
++              err = 0;
++              break;
++      case ENABLE_COMPRESSION:
++      case DISABLE_COMPRESSION:
++              err = 0;
++              break;
++      }
++out_unlock:
++      bcm43xx_unlock_mmio(bcm, flags);
++out:
++      return err;
++}
++
++static int bcm43xx_net_conf_tx(struct net_device *net_dev,
++                             int queue,
++                             const struct ieee80211_tx_queue_params *params)
++{
++      return 0;
++}
++
++static int bcm43xx_net_get_tx_stats(struct net_device *net_dev,
++                                  struct ieee80211_tx_queue_stats *stats)
++{
++      struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
++      unsigned long flags;
++
++      bcm43xx_lock(bcm, flags);
++      if (bcm43xx_using_pio(bcm))
++              bcm43xx_pio_get_tx_stats(bcm, stats);
++      else
++              bcm43xx_dma_get_tx_stats(bcm, stats);
++      bcm43xx_unlock(bcm, flags);
++
++      return 0;
++}
++
++static int bcm43xx_net_get_stats(struct net_device *net_dev,
++                               struct ieee80211_low_level_stats *stats)
++{
++      struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
++      unsigned long flags;
++
++      bcm43xx_lock(bcm, flags);
++      memcpy(stats, &bcm->ieee_stats, sizeof(*stats));
++      bcm43xx_unlock(bcm, flags);
++
++      return 0;
++}
++
++#ifdef CONFIG_NET_POLL_CONTROLLER
++static void bcm43xx_net_poll_controller(struct net_device *net_dev)
++{
++      struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
++      unsigned long flags;
++
++      local_irq_save(flags);
++      bcm43xx_interrupt_handler(bcm->irq, bcm, NULL);
++      local_irq_restore(flags);
++}
++#endif /* CONFIG_NET_POLL_CONTROLLER */
++
++static int bcm43xx_net_open(struct net_device *net_dev)
++{
++      struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
++
++      return bcm43xx_init_board(bcm);
++}
++
++static int bcm43xx_net_stop(struct net_device *net_dev)
++{
++      struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
++
++      if (bcm->initialized) {
++              bcm43xx_disable_interrupts_sync(bcm, NULL);
++              bcm43xx_free_board(bcm);
++      }
++
++      return 0;
++}
++
++/* Initialization of struct net_device, just after allocation. */
++static void bcm43xx_netdev_setup(struct net_device *net_dev)
++{
++#ifdef CONFIG_NET_POLL_CONTROLLER
++      net_dev->poll_controller = bcm43xx_net_poll_controller;
++#endif
++      SET_ETHTOOL_OPS(net_dev, &bcm43xx_ethtool_ops);
++}
++
++static int bcm43xx_init_private(struct bcm43xx_private *bcm,
++                              struct net_device *net_dev,
++                              struct pci_dev *pci_dev,
++                              struct ieee80211_hw *ieee)
++{
++      int err;
++
++      bcm->ieee = ieee;
++      bcm->irq_savedstate = BCM43xx_IRQ_INITIAL;
++      bcm->pci_dev = pci_dev;
++      bcm->net_dev = net_dev;
++      bcm->bad_frames_preempt = modparam_bad_frames_preempt;
++      spin_lock_init(&bcm->_lock);
++      tasklet_init(&bcm->isr_tasklet,
++                   (void (*)(unsigned long))bcm43xx_interrupt_tasklet,
++                   (unsigned long)bcm);
++      tasklet_disable_nosync(&bcm->isr_tasklet);
++      if (modparam_pio) {
++              bcm->__using_pio = 1;
++      } else {
++              err = pci_set_dma_mask(pci_dev, DMA_30BIT_MASK);
++              err |= pci_set_consistent_dma_mask(pci_dev, DMA_30BIT_MASK);
++              if (err) {
++#ifdef CONFIG_BCM43XX_D80211_PIO
++                      printk(KERN_WARNING PFX "DMA not supported. Falling back to PIO.\n");
++                      bcm->__using_pio = 1;
++#else
++                      printk(KERN_ERR PFX "FATAL: DMA not supported and PIO not configured. "
++                                          "Recompile the driver with PIO support, please.\n");
++                      return -ENODEV;
++#endif /* CONFIG_BCM43XX_D80211_PIO */
++              }
++      }
++
++      return 0;
++}
++
++static int __devinit bcm43xx_init_one(struct pci_dev *pdev,
++                                    const struct pci_device_id *ent)
++{
++      struct net_device *net_dev;
++      struct bcm43xx_private *bcm;
++      struct ieee80211_hw *ieee;
++      int err = -ENOMEM;
++
++#ifdef CONFIG_BCM947XX
++      if ((pdev->bus->number == 0) && (pdev->device != 0x0800))
++              return -ENODEV;
++#endif
++      
++#ifdef DEBUG_SINGLE_DEVICE_ONLY
++      if (strcmp(pci_name(pdev), DEBUG_SINGLE_DEVICE_ONLY))
++              return -ENODEV;
++#endif
++
++      ieee = kzalloc(sizeof(*ieee), GFP_KERNEL);
++      if (!ieee)
++              goto out;
++      ieee->version = IEEE80211_VERSION;
++      ieee->name = KBUILD_MODNAME;
++      ieee->host_gen_beacon = 1;
++      ieee->rx_includes_fcs = 1;
++      ieee->tx = bcm43xx_net_hard_start_xmit;
++      ieee->open = bcm43xx_net_open;
++      ieee->stop = bcm43xx_net_stop;
++      ieee->reset = bcm43xx_net_reset;
++      ieee->config = bcm43xx_net_config;
++//TODO        ieee->set_key = bcm43xx_net_set_key;
++      ieee->get_stats = bcm43xx_net_get_stats;
++      ieee->queues = 1;
++      ieee->get_tx_stats = bcm43xx_net_get_tx_stats;
++      ieee->conf_tx = bcm43xx_net_conf_tx;
++      ieee->wep_include_iv = 1;
++
++      net_dev = ieee80211_alloc_hw(sizeof(*bcm), bcm43xx_netdev_setup);
++      if (!net_dev) {
++              printk(KERN_ERR PFX
++                     "could not allocate ieee80211 device %s\n",
++                     pci_name(pdev));
++              goto err_free_ieee;
++      }
++      /* initialize the bcm43xx_private struct */
++      bcm = bcm43xx_priv(net_dev);
++      memset(bcm, 0, sizeof(*bcm));
++      err = bcm43xx_init_private(bcm, net_dev, pdev, ieee);
++      if (err)
++              goto err_free_netdev;
++
++      pci_set_drvdata(pdev, net_dev);
++
++      err = bcm43xx_attach_board(bcm);
++      if (err)
++              goto err_free_netdev;
++      err = ieee80211_register_hw(net_dev, ieee);
++      if (err)
++              goto err_detach_board;
++
++      bcm43xx_debugfs_add_device(bcm);
++
++      assert(err == 0);
++out:
++      return err;
++
++err_detach_board:
++      bcm43xx_detach_board(bcm);
++err_free_netdev:
++      ieee80211_free_hw(net_dev);
++err_free_ieee:
++      kfree(ieee);
++      goto out;
++}
++
++static void __devexit bcm43xx_remove_one(struct pci_dev *pdev)
++{
++      struct net_device *net_dev = pci_get_drvdata(pdev);
++      struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
++      struct ieee80211_hw *ieee = bcm->ieee;
++
++      bcm43xx_debugfs_remove_device(bcm);
++
++      /* Bring down the device early to stop all TX and RX operation. */
++      ieee80211_netif_oper(net_dev, NETIF_DETACH);
++      bcm43xx_net_stop(net_dev);
++
++      ieee80211_unregister_hw(net_dev);
++      bcm43xx_detach_board(bcm);
++      if (bcm->cached_beacon)
++              kfree_skb(bcm->cached_beacon);
++      bcm->cached_beacon = NULL;
++      assert(bcm->ucode == NULL);
++      ieee80211_free_hw(net_dev);
++      kfree(ieee);
++}
++
++/* Hard-reset the chip. Do not call this directly.
++ * Use bcm43xx_controller_restart()
++ */
++static void bcm43xx_chip_reset(void *_bcm)
++{
++      struct bcm43xx_private *bcm = _bcm;
++      struct net_device *net_dev = bcm->net_dev;
++      struct pci_dev *pci_dev = bcm->pci_dev;
++      struct ieee80211_hw *ieee = bcm->ieee;
++      int err;
++      int was_initialized = bcm->initialized;
++
++      ieee80211_netif_oper(bcm->net_dev, NETIF_DETACH);
++      tasklet_disable(&bcm->isr_tasklet);
++
++      bcm->firmware_norelease = 1;
++      if (was_initialized)
++              bcm43xx_free_board(bcm);
++      bcm->firmware_norelease = 0;
++      bcm43xx_detach_board(bcm);
++      err = bcm43xx_init_private(bcm, net_dev, pci_dev, ieee);
++      if (err)
++              goto failure;
++      err = bcm43xx_attach_board(bcm);
++      if (err)
++              goto failure;
++      if (was_initialized) {
++              err = bcm43xx_init_board(bcm);
++              if (err)
++                      goto failure;
++      }
++      ieee80211_netif_oper(bcm->net_dev, NETIF_ATTACH);
++      printk(KERN_INFO PFX "Controller restarted\n");
++
++      return;
++failure:
++      printk(KERN_ERR PFX "Controller restart failed\n");
++}
++
++/* Hard-reset the chip.
++ * This can be called from interrupt or process context.
++ * Make sure to _not_ re-enable device interrupts after this has been called.
++ */
++void bcm43xx_controller_restart(struct bcm43xx_private *bcm, const char *reason)
++{
++      bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
++      bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
++      printk(KERN_ERR PFX "Controller RESET (%s) ...\n", reason);
++      INIT_WORK(&bcm->restart_work, bcm43xx_chip_reset, bcm);
++      schedule_work(&bcm->restart_work);
++}
++
++#ifdef CONFIG_PM
++
++static int bcm43xx_suspend(struct pci_dev *pdev, pm_message_t state)
++{
++      struct net_device *net_dev = pci_get_drvdata(pdev);
++      struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
++      unsigned long flags;
++      int try_to_shutdown = 0, err;
++
++      dprintk(KERN_INFO PFX "Suspending...\n");
++
++      bcm43xx_lock(bcm, flags);
++      bcm->was_initialized = bcm->initialized;
++      if (bcm->initialized)
++              try_to_shutdown = 1;
++      bcm43xx_unlock(bcm, flags);
++
++      ieee80211_netif_oper(bcm->net_dev, NETIF_DETACH);
++      if (try_to_shutdown) {
++              err = bcm43xx_disable_interrupts_sync(bcm, &bcm->irq_savedstate);
++              if (unlikely(err)) {
++                      dprintk(KERN_ERR PFX "Suspend failed.\n");
++                      return -EAGAIN;
++              }
++              bcm->firmware_norelease = 1;
++              bcm43xx_free_board(bcm);
++              bcm->firmware_norelease = 0;
++      }
++      bcm43xx_chipset_detach(bcm);
++
++      pci_save_state(pdev);
++      pci_disable_device(pdev);
++      pci_set_power_state(pdev, pci_choose_state(pdev, state));
++
++      dprintk(KERN_INFO PFX "Device suspended.\n");
++
++      return 0;
++}
++
++static int bcm43xx_resume(struct pci_dev *pdev)
++{
++      struct net_device *net_dev = pci_get_drvdata(pdev);
++      struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
++      int err = 0;
++
++      dprintk(KERN_INFO PFX "Resuming...\n");
++
++      pci_set_power_state(pdev, 0);
++      pci_enable_device(pdev);
++      pci_restore_state(pdev);
++
++      bcm43xx_chipset_attach(bcm);
++      if (bcm->was_initialized) {
++              bcm->irq_savedstate = BCM43xx_IRQ_INITIAL;
++              err = bcm43xx_init_board(bcm);
++      }
++      if (err) {
++              printk(KERN_ERR PFX "Resume failed!\n");
++              return err;
++      }
++
++      ieee80211_netif_oper(bcm->net_dev, NETIF_ATTACH);
++
++      dprintk(KERN_INFO PFX "Device resumed.\n");
++
++      return 0;
++}
++
++#endif                                /* CONFIG_PM */
++
++static struct pci_driver bcm43xx_pci_driver = {
++      .name = KBUILD_MODNAME,
++      .id_table = bcm43xx_pci_tbl,
++      .probe = bcm43xx_init_one,
++      .remove = __devexit_p(bcm43xx_remove_one),
++#ifdef CONFIG_PM
++      .suspend = bcm43xx_suspend,
++      .resume = bcm43xx_resume,
++#endif                                /* CONFIG_PM */
++};
++
++static int __init bcm43xx_init(void)
++{
++      printk(KERN_INFO KBUILD_MODNAME " driver\n");
++      bcm43xx_debugfs_init();
++      return pci_register_driver(&bcm43xx_pci_driver);
++}
++
++static void __exit bcm43xx_exit(void)
++{
++      pci_unregister_driver(&bcm43xx_pci_driver);
++      bcm43xx_debugfs_exit();
++}
++
++module_init(bcm43xx_init)
++module_exit(bcm43xx_exit)
+diff -Nur linux-2.6.16/drivers/net/wireless/bcm43xx-d80211/bcm43xx_main.h linux-2.6.16-bcm43xx/drivers/net/wireless/bcm43xx-d80211/bcm43xx_main.h
+--- linux-2.6.16/drivers/net/wireless/bcm43xx-d80211/bcm43xx_main.h    1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.16-bcm43xx/drivers/net/wireless/bcm43xx-d80211/bcm43xx_main.h    2006-03-28 22:16:14.000000000 +0200
+@@ -0,0 +1,177 @@
++/*
++
++  Broadcom BCM43xx wireless driver
++
++  Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
++                     Stefano Brivio <st3@riseup.net>
++                     Michael Buesch <mbuesch@freenet.de>
++                     Danny van Dyk <kugelfang@gentoo.org>
++                     Andreas Jaggi <andreas.jaggi@waterwave.ch>
++
++  Some parts of the code in this file are derived from the ipw2200
++  driver  Copyright(c) 2003 - 2004 Intel Corporation.
++
++  This program is free software; you can redistribute it and/or modify
++  it under the terms of the GNU General Public License as published by
++  the Free Software Foundation; either version 2 of the License, or
++  (at your option) any later version.
++
++  This program is distributed in the hope that it will be useful,
++  but WITHOUT ANY WARRANTY; without even the implied warranty of
++  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++  GNU General Public License for more details.
++
++  You should have received a copy of the GNU General Public License
++  along with this program; see the file COPYING.  If not, write to
++  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
++  Boston, MA 02110-1301, USA.
++
++*/
++
++#ifndef BCM43xx_MAIN_H_
++#define BCM43xx_MAIN_H_
++
++#include "bcm43xx.h"
++
++#ifdef CONFIG_BCM947XX
++#define atoi(str) simple_strtoul(((str != NULL) ? str : ""), NULL, 0)
++
++static inline void e_aton(char *str, char *dest)
++{
++      int i = 0;
++      u16 *d = (u16 *) dest;
++
++      for (;;) {
++              dest[i++] = (char) simple_strtoul(str, NULL, 16);
++              str += 2;
++              if (!*str++ || i == 6)
++                      break;
++      }
++      for (i = 0; i < 3; i++)
++              d[i] = cpu_to_be16(d[i]);
++}
++#endif
++
++#define P4D_BYT3S(magic, nr_bytes)    u8 __p4dding##magic[nr_bytes]
++#define P4D_BYTES(line, nr_bytes)     P4D_BYT3S(line, nr_bytes)
++/* Magic helper macro to pad structures. Ignore those above. It's magic. */
++#define PAD_BYTES(nr_bytes)           P4D_BYTES( __LINE__ , (nr_bytes))
++
++
++/* Lightweight function to convert a frequency (in Mhz) to a channel number. */
++static inline
++u8 bcm43xx_freq_to_channel_a(int freq)
++{
++      return ((freq - 5000) / 5);
++}
++static inline
++u8 bcm43xx_freq_to_channel_bg(int freq)
++{
++      u8 channel;
++
++      if (freq == 2484)
++              channel = 14;
++      else
++              channel = (freq - 2407) / 5;
++
++      return channel;
++}
++static inline
++u8 bcm43xx_freq_to_channel(struct bcm43xx_private *bcm,
++                         int freq)
++{
++      if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_A)
++              return bcm43xx_freq_to_channel_a(freq);
++      return bcm43xx_freq_to_channel_bg(freq);
++}
++
++/* Lightweight function to convert a channel number to a frequency (in Mhz). */
++static inline
++int bcm43xx_channel_to_freq_a(u8 channel)
++{
++      return (5000 + (5 * channel));
++}
++static inline
++int bcm43xx_channel_to_freq_bg(u8 channel)
++{
++      int freq;
++
++      if (channel == 14)
++              freq = 2484;
++      else
++              freq = 2407 + (5 * channel);
++
++      return freq;
++}
++static inline
++int bcm43xx_channel_to_freq(struct bcm43xx_private *bcm,
++                          u8 channel)
++{
++      if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_A)
++              return bcm43xx_channel_to_freq_a(channel);
++      return bcm43xx_channel_to_freq_bg(channel);
++}
++
++/* Lightweight function to check if a channel number is valid.
++ * Note that this does _NOT_ check for geographical restrictions!
++ */
++static inline
++int bcm43xx_is_valid_channel_a(u8 channel)
++{
++      return (channel <= 200);
++}
++static inline
++int bcm43xx_is_valid_channel_bg(u8 channel)
++{
++      return (channel >= 1 && channel <= 14);
++}
++static inline
++int bcm43xx_is_valid_channel(struct bcm43xx_private *bcm,
++                           u8 channel)
++{
++      if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_A)
++              return bcm43xx_is_valid_channel_a(channel);
++      return bcm43xx_is_valid_channel_bg(channel);
++}
++
++static inline
++int bcm43xx_is_cck_rate(int rate)
++{
++      return (rate == BCM43xx_CCK_RATE_1MB ||
++              rate == BCM43xx_CCK_RATE_2MB ||
++              rate == BCM43xx_CCK_RATE_5MB ||
++              rate == BCM43xx_CCK_RATE_11MB);
++}
++
++void bcm43xx_tsf_read(struct bcm43xx_private *bcm, u64 *tsf);
++void bcm43xx_tsf_write(struct bcm43xx_private *bcm, u64 tsf);
++
++void bcm43xx_set_iwmode(struct bcm43xx_private *bcm,
++                      int iw_mode);
++
++u32 bcm43xx_shm_read32(struct bcm43xx_private *bcm,
++                     u16 routing, u16 offset);
++u16 bcm43xx_shm_read16(struct bcm43xx_private *bcm,
++                     u16 routing, u16 offset);
++void bcm43xx_shm_write32(struct bcm43xx_private *bcm,
++                       u16 routing, u16 offset,
++                       u32 value);
++void bcm43xx_shm_write16(struct bcm43xx_private *bcm,
++                       u16 routing, u16 offset,
++                       u16 value);
++
++void bcm43xx_dummy_transmission(struct bcm43xx_private *bcm);
++
++int bcm43xx_switch_core(struct bcm43xx_private *bcm, struct bcm43xx_coreinfo *new_core);
++
++void bcm43xx_wireless_core_reset(struct bcm43xx_private *bcm, int connect_phy);
++
++void bcm43xx_mac_suspend(struct bcm43xx_private *bcm);
++void bcm43xx_mac_enable(struct bcm43xx_private *bcm);
++
++void bcm43xx_controller_restart(struct bcm43xx_private *bcm, const char *reason);
++
++int bcm43xx_sprom_read(struct bcm43xx_private *bcm, u16 *sprom);
++int bcm43xx_sprom_write(struct bcm43xx_private *bcm, const u16 *sprom);
++
++#endif /* BCM43xx_MAIN_H_ */
+diff -Nur linux-2.6.16/drivers/net/wireless/bcm43xx-d80211/bcm43xx_phy.c linux-2.6.16-bcm43xx/drivers/net/wireless/bcm43xx-d80211/bcm43xx_phy.c
+--- linux-2.6.16/drivers/net/wireless/bcm43xx-d80211/bcm43xx_phy.c     1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.16-bcm43xx/drivers/net/wireless/bcm43xx-d80211/bcm43xx_phy.c     2006-03-28 22:16:14.000000000 +0200
+@@ -0,0 +1,2347 @@
++/*
++
++  Broadcom BCM43xx wireless driver
++
++  Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
++                     Stefano Brivio <st3@riseup.net>
++                     Michael Buesch <mbuesch@freenet.de>
++                     Danny van Dyk <kugelfang@gentoo.org>
++                     Andreas Jaggi <andreas.jaggi@waterwave.ch>
++
++  Some parts of the code in this file are derived from the ipw2200
++  driver  Copyright(c) 2003 - 2004 Intel Corporation.
++
++  This program is free software; you can redistribute it and/or modify
++  it under the terms of the GNU General Public License as published by
++  the Free Software Foundation; either version 2 of the License, or
++  (at your option) any later version.
++
++  This program is distributed in the hope that it will be useful,
++  but WITHOUT ANY WARRANTY; without even the implied warranty of
++  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++  GNU General Public License for more details.
++
++  You should have received a copy of the GNU General Public License
++  along with this program; see the file COPYING.  If not, write to
++  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
++  Boston, MA 02110-1301, USA.
++
++*/
++
++#include <linux/delay.h>
++#include <linux/pci.h>
++#include <linux/types.h>
++
++#include "bcm43xx.h"
++#include "bcm43xx_phy.h"
++#include "bcm43xx_main.h"
++#include "bcm43xx_radio.h"
++#include "bcm43xx_ilt.h"
++#include "bcm43xx_power.h"
++
++
++static const s8 bcm43xx_tssi2dbm_b_table[] = {
++      0x4D, 0x4C, 0x4B, 0x4A,
++      0x4A, 0x49, 0x48, 0x47,
++      0x47, 0x46, 0x45, 0x45,
++      0x44, 0x43, 0x42, 0x42,
++      0x41, 0x40, 0x3F, 0x3E,
++      0x3D, 0x3C, 0x3B, 0x3A,
++      0x39, 0x38, 0x37, 0x36,
++      0x35, 0x34, 0x32, 0x31,
++      0x30, 0x2F, 0x2D, 0x2C,
++      0x2B, 0x29, 0x28, 0x26,
++      0x25, 0x23, 0x21, 0x1F,
++      0x1D, 0x1A, 0x17, 0x14,
++      0x10, 0x0C, 0x06, 0x00,
++        -7,   -7,   -7,   -7,
++        -7,   -7,   -7,   -7,
++        -7,   -7,   -7,   -7,
++};
++
++static const s8 bcm43xx_tssi2dbm_g_table[] = {
++       77,  77,  77,  76,
++       76,  76,  75,  75,
++       74,  74,  73,  73,
++       73,  72,  72,  71,
++       71,  70,  70,  69,
++       68,  68,  67,  67,
++       66,  65,  65,  64,
++       63,  63,  62,  61,
++       60,  59,  58,  57,
++       56,  55,  54,  53,
++       52,  50,  49,  47,
++       45,  43,  40,  37,
++       33,  28,  22,  14,
++        5,  -7, -20, -20,
++      -20, -20, -20, -20,
++      -20, -20, -20, -20,
++};
++
++static void bcm43xx_phy_initg(struct bcm43xx_private *bcm);
++
++
++void bcm43xx_raw_phy_lock(struct bcm43xx_private *bcm)
++{
++      struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
++
++      assert(irqs_disabled());
++      if (bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD) == 0x00000000) {
++              phy->is_locked = 0;
++              return;
++      }
++      if (bcm->current_core->rev < 3) {
++              bcm43xx_mac_suspend(bcm);
++              spin_lock(&phy->lock);
++      } else {
++              if (bcm->iw_mode != IW_MODE_MASTER)
++                      bcm43xx_power_saving_ctl_bits(bcm, -1, 1);
++      }
++      phy->is_locked = 1;
++}
++
++void bcm43xx_raw_phy_unlock(struct bcm43xx_private *bcm)
++{
++      struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
++
++      assert(irqs_disabled());
++      if (bcm->current_core->rev < 3) {
++              if (phy->is_locked) {
++                      spin_unlock(&phy->lock);
++                      bcm43xx_mac_enable(bcm);
++              }
++      } else {
++              if (bcm->iw_mode != IW_MODE_MASTER)
++                      bcm43xx_power_saving_ctl_bits(bcm, -1, -1);
++      }
++      phy->is_locked = 0;
++}
++
++u16 bcm43xx_phy_read(struct bcm43xx_private *bcm, u16 offset)
++{
++      bcm43xx_write16(bcm, BCM43xx_MMIO_PHY_CONTROL, offset);
++      return bcm43xx_read16(bcm, BCM43xx_MMIO_PHY_DATA);
++}
++
++void bcm43xx_phy_write(struct bcm43xx_private *bcm, u16 offset, u16 val)
++{
++      bcm43xx_write16(bcm, BCM43xx_MMIO_PHY_CONTROL, offset);
++      mmiowb();
++      bcm43xx_write16(bcm, BCM43xx_MMIO_PHY_DATA, val);
++}
++
++void bcm43xx_phy_calibrate(struct bcm43xx_private *bcm)
++{
++      struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
++      unsigned long flags;
++
++      bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* Dummy read. */
++      if (phy->calibrated)
++              return;
++      if (phy->type == BCM43xx_PHYTYPE_G && phy->rev == 1) {
++              /* We do not want to be preempted while calibrating
++               * the hardware.
++               */
++              local_irq_save(flags);
++
++              bcm43xx_wireless_core_reset(bcm, 0);
++              bcm43xx_phy_initg(bcm);
++              bcm43xx_wireless_core_reset(bcm, 1);
++
++              local_irq_restore(flags);
++      }
++      phy->calibrated = 1;
++}
++
++/* Connect the PHY 
++ * http://bcm-specs.sipsolutions.net/SetPHY
++ */
++int bcm43xx_phy_connect(struct bcm43xx_private *bcm, int connect)
++{
++      struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
++      u32 flags;
++
++      if (bcm->current_core->rev < 5)
++              goto out;
++
++      flags = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
++      if (connect) {
++              if (!(flags & 0x00010000))
++                      return -ENODEV;
++              flags = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
++              flags |= (0x800 << 18);
++              bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, flags);
++      } else {
++              if (!(flags & 0x00020000))
++                      return -ENODEV;
++              flags = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
++              flags &= ~(0x800 << 18);
++              bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, flags);
++      }
++out:
++      phy->connected = connect;
++      if (connect)
++              dprintk(KERN_INFO PFX "PHY connected\n");
++      else
++              dprintk(KERN_INFO PFX "PHY disconnected\n");
++
++      return 0;
++}
++
++/* intialize B PHY power control
++ * as described in http://bcm-specs.sipsolutions.net/InitPowerControl
++ */
++static void bcm43xx_phy_init_pctl(struct bcm43xx_private *bcm)
++{
++      struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
++      struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
++      u16 saved_batt = 0, saved_ratt = 0, saved_txctl1 = 0;
++      int must_reset_txpower = 0;
++
++      assert(phy->type != BCM43xx_PHYTYPE_A);
++      if ((bcm->board_vendor == PCI_VENDOR_ID_BROADCOM) &&
++          (bcm->board_type == 0x0416))
++              return;
++
++      bcm43xx_write16(bcm, 0x03E6, bcm43xx_read16(bcm, 0x03E6) & 0xFFDF);
++      bcm43xx_phy_write(bcm, 0x0028, 0x8018);
++
++      if (phy->type == BCM43xx_PHYTYPE_G) {
++              if (!phy->connected)
++                      return;
++              bcm43xx_phy_write(bcm, 0x047A, 0xC111);
++      }
++      if (phy->savedpctlreg != 0xFFFF)
++              return;
++
++      if (phy->type == BCM43xx_PHYTYPE_B &&
++          phy->rev >= 2 &&
++          radio->version == 0x2050) {
++              bcm43xx_radio_write16(bcm, 0x0076,
++                                    bcm43xx_radio_read16(bcm, 0x0076) | 0x0084);
++      } else {
++              saved_batt = radio->baseband_atten;
++              saved_ratt = radio->radio_atten;
++              saved_txctl1 = radio->txctl1;
++              if ((radio->revision >= 6) && (radio->revision <= 8)
++                  && /*FIXME: incomplete specs for 5 < revision < 9 */ 0)
++                      bcm43xx_radio_set_txpower_bg(bcm, 0xB, 0x1F, 0);
++              else
++                      bcm43xx_radio_set_txpower_bg(bcm, 0xB, 9, 0);
++              must_reset_txpower = 1;
++      }
++      bcm43xx_dummy_transmission(bcm);
++
++      phy->savedpctlreg = bcm43xx_phy_read(bcm, BCM43xx_PHY_G_PCTL);
++
++      if (must_reset_txpower)
++              bcm43xx_radio_set_txpower_bg(bcm, saved_batt, saved_ratt, saved_txctl1);
++      else
++              bcm43xx_radio_write16(bcm, 0x0076, bcm43xx_radio_read16(bcm, 0x0076) & 0xFF7B);
++      bcm43xx_radio_clear_tssi(bcm);
++}
++
++static void bcm43xx_phy_agcsetup(struct bcm43xx_private *bcm)
++{
++      struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
++      u16 offset = 0x0000;
++
++      if (phy->rev == 1)
++              offset = 0x4C00;
++
++      bcm43xx_ilt_write(bcm, offset, 0x00FE);
++      bcm43xx_ilt_write(bcm, offset + 1, 0x000D);
++      bcm43xx_ilt_write(bcm, offset + 2, 0x0013);
++      bcm43xx_ilt_write(bcm, offset + 3, 0x0019);
++
++      if (phy->rev == 1) {
++              bcm43xx_ilt_write(bcm, 0x1800, 0x2710);
++              bcm43xx_ilt_write(bcm, 0x1801, 0x9B83);
++              bcm43xx_ilt_write(bcm, 0x1802, 0x9B83);
++              bcm43xx_ilt_write(bcm, 0x1803, 0x0F8D);
++              bcm43xx_phy_write(bcm, 0x0455, 0x0004);
++      }
++
++      bcm43xx_phy_write(bcm, 0x04A5, (bcm43xx_phy_read(bcm, 0x04A5) & 0x00FF) | 0x5700);
++      bcm43xx_phy_write(bcm, 0x041A, (bcm43xx_phy_read(bcm, 0x041A) & 0xFF80) | 0x000F);
++      bcm43xx_phy_write(bcm, 0x041A, (bcm43xx_phy_read(bcm, 0x041A) & 0xC07F) | 0x2B80);
++      bcm43xx_phy_write(bcm, 0x048C, (bcm43xx_phy_read(bcm, 0x048C) & 0xF0FF) | 0x0300);
++
++      bcm43xx_radio_write16(bcm, 0x007A, bcm43xx_radio_read16(bcm, 0x007A) | 0x0008);
++
++      bcm43xx_phy_write(bcm, 0x04A0, (bcm43xx_phy_read(bcm, 0x04A0) & 0xFFF0) | 0x0008);
++      bcm43xx_phy_write(bcm, 0x04A1, (bcm43xx_phy_read(bcm, 0x04A1) & 0xF0FF) | 0x0600);
++      bcm43xx_phy_write(bcm, 0x04A2, (bcm43xx_phy_read(bcm, 0x04A2) & 0xF0FF) | 0x0700);
++