ar71xx: Allow to set the RXDV, RXD, TXD, TXE delays for QCA955x
authorJohn Crispin <john@openwrt.org>
Wed, 16 Mar 2016 09:27:08 +0000 (09:27 +0000)
committerJohn Crispin <john@openwrt.org>
Wed, 16 Mar 2016 09:27:08 +0000 (09:27 +0000)
Some u-boot versions for QCA955x change the delays based on the link speed
during boot. This usually breaks the support of other linkspeeds when
OpenWrt is booted. It also conflicts with the
at803x_platform_data::fixup_rgmii_tx_delay. OpenWrt has to set its own
values in QCA955X_GMAC_REG_ETH_CFG.

The default RGMII values from the Atheros u-boot are currently used to
preset the existing mach files. These may have to be adjusted for boards
using different values but which are not currently set them explicitely in
OpenWrt.

Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>
Cc: Gabor Juhos <juhosg@openwrt.org>
Cc: Imre Kaloz <kaloz@openwrt.org>
Cc: Christian Beier <cb@shoutrlabs.com>
Cc: Chris R Blake <chrisrblake93@gmail.com>
Cc: Benjamin Berg <benjamin@sipsolutions.net>
Cc: Heiner Kallweit <hkallweit1@gmail.com>
Cc: Cezary Jackiewicz <cezary.jackiewicz@gmail.com>
Cc: Matthias Schiffer <mschiffer@universe-factory.net>
Cc: Dirk Neukirchen <dirkneukirchen@web.de>
Cc: Christian Mehlis <christian@m3hlis.de>
Cc: Luka Perkov <luka@openwrt.org>
Cc: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 49029

19 files changed:
target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
target/linux/ar71xx/files/arch/mips/ath79/dev-eth.h
target/linux/ar71xx/files/arch/mips/ath79/mach-archer-c7.c
target/linux/ar71xx/files/arch/mips/ath79/mach-epg5000.c
target/linux/ar71xx/files/arch/mips/ath79/mach-esr1750.c
target/linux/ar71xx/files/arch/mips/ath79/mach-esr900.c
target/linux/ar71xx/files/arch/mips/ath79/mach-f9k1115v2.c
target/linux/ar71xx/files/arch/mips/ath79/mach-mr1750.c
target/linux/ar71xx/files/arch/mips/ath79/mach-mr18.c
target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c
target/linux/ar71xx/files/arch/mips/ath79/mach-nbg6716.c
target/linux/ar71xx/files/arch/mips/ath79/mach-rb922.c
target/linux/ar71xx/files/arch/mips/ath79/mach-tew-823dru.c
target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr1043nd-v2.c
target/linux/ar71xx/files/arch/mips/ath79/mach-wlr8100.c
target/linux/ar71xx/files/arch/mips/ath79/mach-wpj558.c
target/linux/ar71xx/files/arch/mips/ath79/mach-wzr-450hp2.c
target/linux/ar71xx/patches-4.1/609-MIPS-ath79-ap136-fixes.patch
target/linux/ar71xx/patches-4.4/609-MIPS-ath79-ap136-fixes.patch

index 2f2825f..6445023 100644 (file)
@@ -830,7 +830,9 @@ void __init ath79_setup_ar934x_eth_rx_delay(unsigned int rxd,
        iounmap(base);
 }
 
-void __init ath79_setup_qca955x_eth_cfg(u32 mask)
+void __init ath79_setup_qca955x_eth_cfg(u32 mask,
+                                       unsigned int rxd, unsigned int rxdv,
+                                       unsigned int txd, unsigned int txe)
 {
        void __iomem *base;
        u32 t, m;
@@ -845,6 +847,10 @@ void __init ath79_setup_qca955x_eth_cfg(u32 mask)
            QCA955X_ETH_CFG_RMII_GE0 |
            QCA955X_ETH_CFG_MII_CNTL_SPEED |
            QCA955X_ETH_CFG_RMII_GE0_MASTER;
+       m |= QCA955X_ETH_CFG_RXD_DELAY_MASK << QCA955X_ETH_CFG_RXD_DELAY_SHIFT;
+       m |= QCA955X_ETH_CFG_RDV_DELAY_MASK << QCA955X_ETH_CFG_RDV_DELAY_SHIFT;
+       m |= QCA955X_ETH_CFG_TXD_DELAY_MASK << QCA955X_ETH_CFG_TXD_DELAY_SHIFT;
+       m |= QCA955X_ETH_CFG_TXE_DELAY_MASK << QCA955X_ETH_CFG_TXE_DELAY_SHIFT;
 
        base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
 
@@ -852,6 +858,10 @@ void __init ath79_setup_qca955x_eth_cfg(u32 mask)
 
        t &= ~m;
        t |= mask;
+       t |= rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT;
+       t |= rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT;
+       t |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT;
+       t |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT;
 
        __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
 
index 5a226e4..3908750 100644 (file)
@@ -48,6 +48,7 @@ void ath79_register_mdio(unsigned int id, u32 phy_mask);
 void ath79_setup_ar933x_phy4_switch(bool mac, bool mdio);
 void ath79_setup_ar934x_eth_cfg(u32 mask);
 void ath79_setup_ar934x_eth_rx_delay(unsigned int rxd, unsigned int rxdv);
-void ath79_setup_qca955x_eth_cfg(u32 mask);
+void ath79_setup_qca955x_eth_cfg(u32 mask, unsigned int rxd, unsigned int rxdv,
+                                unsigned int txd, unsigned int txe);
 
 #endif /* _ATH79_DEV_ETH_H */
index fc12513..ca882cd 100644 (file)
@@ -211,7 +211,7 @@ static void __init common_setup(bool pcie_slot)
                                    ARRAY_SIZE(archer_c7_mdio0_info));
        ath79_register_mdio(0, 0x0);
 
-       ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
+       ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
 
        /* GMAC0 is connected to the RMGII interface */
        ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
index 3d60afc..d89d4c4 100644 (file)
@@ -149,7 +149,7 @@ static void __init epg5000_setup(void)
 
        ath79_register_usb();
 
-       ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
+       ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
 
        ath79_register_mdio(0, 0x0);
 
index 2a34b3a..ef8abb8 100644 (file)
@@ -148,7 +148,7 @@ static void __init esr1750_setup(void)
 
        ath79_register_usb();
 
-       ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
+       ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
 
        ath79_register_mdio(0, 0x0);
 
index aa2e7f7..dd07248 100644 (file)
@@ -170,7 +170,7 @@ static void __init esr900_setup(void)
 
        ath79_register_wmac(art + ESR900_WMAC_CALDATA_OFFSET, wlan0_mac);
 
-       ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
+       ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
 
        ath79_register_mdio(0, 0x0);
 
index 69d005d..c1f5679 100644 (file)
@@ -152,7 +152,7 @@ static void __init f9k1115v2_setup(void)
        mdiobus_register_board_info(f9k1115v2_mdio0_info,
                                    ARRAY_SIZE(f9k1115v2_mdio0_info));
 
-       ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
+       ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
 
        ath79_init_mac(ath79_eth0_data.mac_addr,
                       art + F9K1115V2_WAN_MAC_OFFSET, 0);
index 8ace02f..8db2915 100644 (file)
@@ -113,7 +113,7 @@ static void __init mr1750_setup(void)
        ath79_register_wmac(art + MR1750_WMAC_CALDATA_OFFSET, mac);
        ath79_register_pci();
 
-       ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
+       ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
        ath79_register_mdio(0, 0x0);
 
        ath79_init_mac(ath79_eth0_data.mac_addr, art + MR1750_MAC0_OFFSET, 0);
index a24cb3f..215dd55 100644 (file)
@@ -253,9 +253,8 @@ static void __init mr18_setup(void)
        res = mr18_extract_sgmii_res_cal();
        if (res >= 0) {
                /* Setup SoC Eth Config */
-               ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN |
-                       (3 << QCA955X_ETH_CFG_RXD_DELAY_SHIFT) |
-                       (3 << QCA955X_ETH_CFG_RDV_DELAY_SHIFT));
+               ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0,
+                                           0);
 
                /* MDIO Interface */
                ath79_register_mdio(0, 0x0);
index 9c3164d..1eb33b6 100644 (file)
@@ -123,7 +123,7 @@ static void __init mr900_setup(void)
        }
        pdata->use_eeprom = true;
 
-       ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
+       ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
        ath79_register_mdio(0, 0x0);
 
        ath79_init_mac(ath79_eth0_data.mac_addr, art + MR900_MAC0_OFFSET, 0);
index c28a8a5..3555c9b 100644 (file)
@@ -287,7 +287,7 @@ static void __init nbg6716_common_setup(u32 leds_num, struct gpio_led* leds,
 
        ath79_register_wmac(art + NBG6716_WMAC_CALDATA_OFFSET, tmpmac);
 
-       ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
+       ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
 
        ath79_register_mdio(0, 0x0);
 
index c88c522..986bfd2 100644 (file)
@@ -203,7 +203,7 @@ static void __init rb922gs_setup(void)
 
        rb922gs_nand_init();
 
-       ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
+       ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
 
        ath79_register_mdio(0, 0x0);
 
index cf863ac..05a344f 100644 (file)
@@ -155,7 +155,7 @@ static void __init tew_823dru_setup(void)
                        ARRAY_SIZE(tew_823dru_mdio0_info));
        ath79_register_mdio(0, 0x0);
 
-       ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
+       ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
 
        /* GMAC0 is connected to the RMGII interface */
        ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
index abdbde0..73808ab 100644 (file)
@@ -183,7 +183,7 @@ static void __init tl_wr1043nd_v2_setup(void)
                                    ARRAY_SIZE(wr1043nd_v2_mdio0_info));
        ath79_register_mdio(0, 0x0);
 
-       ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
+       ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
 
        /* GMAC0 is connected to the RMGII interface */
        ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
index 88022e7..a4e4872 100644 (file)
@@ -152,7 +152,7 @@ static void __init wlr8100_common_setup(void)
 
        ath79_register_wmac(art + WLR8100_WMAC_CALDATA_OFFSET, NULL);
 
-       ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
+       ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
 
        ath79_register_mdio(0, 0x0);
 
index c7b120d..954976e 100644 (file)
@@ -156,7 +156,7 @@ static void __init wpj558_setup(void)
        ath79_init_mac(ath79_eth0_data.mac_addr, art + WPJ558_MAC_OFFSET, 0);
        ath79_init_mac(ath79_eth1_data.mac_addr, art + WPJ558_MAC_OFFSET, 0);
 
-       ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
+       ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
 
        /* GMAC0 is connected to an AR8327 switch */
        ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
index 428876f..77c7cec 100644 (file)
@@ -193,7 +193,7 @@ static void __init wzr_450hp2_setup(void)
                                    ARRAY_SIZE(wzr_450hp2_mdio0_info));
        ath79_register_mdio(0, 0x0);
 
-       ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
+       ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
 
        /* GMAC0 is connected to the RMGII interface */
        ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
index 4d7902e..f13cd9e 100644 (file)
 +
 +      ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL);
 +
-+      ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
++      ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
  
 -static int ap136_pci_plat_dev_init(struct pci_dev *dev)
 +      ath79_register_mdio(0, 0x0);
index 4d7902e..f13cd9e 100644 (file)
 +
 +      ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL);
 +
-+      ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
++      ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
  
 -static int ap136_pci_plat_dev_init(struct pci_dev *dev)
 +      ath79_register_mdio(0, 0x0);