Migrate rt2x00 to the compat-wireless version
authorFlorian Fainelli <florian@openwrt.org>
Mon, 7 Apr 2008 07:29:37 +0000 (07:29 +0000)
committerFlorian Fainelli <florian@openwrt.org>
Mon, 7 Apr 2008 07:29:37 +0000 (07:29 +0000)
SVN-Revision: 10753

35 files changed:
package/mac80211/Makefile
package/rt2x00/Makefile [deleted file]
package/rt2x00/src/COPYING [deleted file]
package/rt2x00/src/Makefile [deleted file]
package/rt2x00/src/README [deleted file]
package/rt2x00/src/THANKS [deleted file]
package/rt2x00/src/rt2400pci.c [deleted file]
package/rt2x00/src/rt2400pci.h [deleted file]
package/rt2x00/src/rt2500pci.c [deleted file]
package/rt2x00/src/rt2500pci.h [deleted file]
package/rt2x00/src/rt2500usb.c [deleted file]
package/rt2x00/src/rt2500usb.h [deleted file]
package/rt2x00/src/rt2x00.h [deleted file]
package/rt2x00/src/rt2x00_compat.h [deleted file]
package/rt2x00/src/rt2x00config.c [deleted file]
package/rt2x00/src/rt2x00debug.c [deleted file]
package/rt2x00/src/rt2x00debug.h [deleted file]
package/rt2x00/src/rt2x00dev.c [deleted file]
package/rt2x00/src/rt2x00dev.h [deleted file]
package/rt2x00/src/rt2x00firmware.c [deleted file]
package/rt2x00/src/rt2x00firmware.h [deleted file]
package/rt2x00/src/rt2x00lib.h [deleted file]
package/rt2x00/src/rt2x00mac.c [deleted file]
package/rt2x00/src/rt2x00pci.c [deleted file]
package/rt2x00/src/rt2x00pci.h [deleted file]
package/rt2x00/src/rt2x00reg.h [deleted file]
package/rt2x00/src/rt2x00rfkill.c [deleted file]
package/rt2x00/src/rt2x00rfkill.h [deleted file]
package/rt2x00/src/rt2x00ring.h [deleted file]
package/rt2x00/src/rt2x00usb.c [deleted file]
package/rt2x00/src/rt2x00usb.h [deleted file]
package/rt2x00/src/rt61pci.c [deleted file]
package/rt2x00/src/rt61pci.h [deleted file]
package/rt2x00/src/rt73usb.c [deleted file]
package/rt2x00/src/rt73usb.h [deleted file]

index b8008d7..12a177b 100644 (file)
@@ -33,12 +33,128 @@ define KernelPackage/mac80211/description
 Linux 802.11 Wireless Networking Stack
 endef
 
-CONFOPTS:=MAC80211 CFG80211 NL80211 MAC80211_RC_DEFAULT_PID MAC80211_RC_PID
+# Ralink rt2x00 drivers
+RT61FW:=RT61_Firmware_V1.2.zip
+RT71FW:=RT71W_Firmware_V1.8.zip
+
+define Download/rt61
+  FILE:=$(RT61FW)
+  URL:=http://www.ralinktech.com.tw/data/
+  MD5SUM:=d4c690c93b470bc9a681297c2adc6281
+endef
+$(eval $(call Download,rt61))
+
+define Download/rt71w
+  FILE:=$(RT71FW)
+  URL:=http://www.ralinktech.com.tw/data/
+  MD5SUM:=1e7a5dc574e0268574fcda3fd5cf52f7
+endef
+$(eval $(call Download,rt71w))
+
+define KernelPackage/rt2x00/Default
+  SUBMENU:=Wireless Drivers
+  TITLE:=Ralink Drivers for RT2x00 cards
+  DEPENDS:=@LINUX_2_6_24 @!TARGET_atheros @!TARGET_uml
+endef
+
+define KernelPackage/rt2x00-lib
+$(call KernelPackage/rt2x00/Default)
+  DEPENDS+= @PCI_SUPPORT||USB_SUPPORT +kmod-mac80211
+  TITLE+= (LIB)
+  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/rt2x00/rt2x00lib.$(LINUX_KMOD_SUFFIX)
+  AUTOLOAD:=$(call AutoLoad,25,blkcipher ecb arc4 rt2x00lib)
+endef
+
+define KernelPackage/rt2x00-pci
+$(call KernelPackage/rt2x00/Default)
+  DEPENDS+= @PCI_SUPPORT +kmod-rt2x00-lib +kmod-eeprom-93cx6
+  TITLE+= (PCI)
+  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/rt2x00/rt2x00pci.$(LINUX_KMOD_SUFFIX)
+  AUTOLOAD:=$(call AutoLoad,26,rt2x00pci)
+endef
+
+define KernelPackage/rt2x00-usb
+$(call KernelPackage/rt2x00/Default)
+  DEPENDS+= @USB_SUPPORT +kmod-rt2x00-lib +kmod-usb-core
+  TITLE+= (USB)
+  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/rt2x00/rt2x00usb.$(LINUX_KMOD_SUFFIX)
+  AUTOLOAD:=$(call AutoLoad,26,rt2x00usb)
+endef
+
+define KernelPackage/rt2400-pci
+$(call KernelPackage/rt2x00/Default)
+  DEPENDS+= @PCI_SUPPORT +kmod-rt2x00-pci
+  TITLE+= (RT2400 PCI)
+  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/rt2x00/rt2400pci.$(LINUX_KMOD_SUFFIX)
+  AUTOLOAD:=$(call AutoLoad,27,rt2400pci)
+endef
+
+define KernelPackage/rt2500-pci
+$(call KernelPackage/rt2x00/Default)
+  DEPENDS+= @PCI_SUPPORT +kmod-rt2x00-pci
+  TITLE+= (RT2500 PCI)
+  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/rt2x00/rt2500pci.$(LINUX_KMOD_SUFFIX)
+  AUTOLOAD:=$(call AutoLoad,27,rt2500pci)
+endef
+
+define KernelPackage/rt2500-usb
+$(call KernelPackage/rt2x00/Default)
+  DEPENDS+= @USB_SUPPORT +kmod-rt2x00-usb +kmod-crc-itu-t
+  TITLE+= (RT2500 USB)
+  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/rt2x00/rt2500usb.$(LINUX_KMOD_SUFFIX)
+  AUTOLOAD:=$(call AutoLoad,27,rt2500usb)
+endef
+
+define KernelPackage/rt61-pci
+$(call KernelPackage/rt2x00/Default)
+  DEPENDS+= @PCI_SUPPORT +kmod-rt2x00-pci +kmod-crc-itu-t
+  TITLE+= (RT2x61 PCI)
+  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/rt2x00/rt61pci.$(LINUX_KMOD_SUFFIX)
+  AUTOLOAD:=$(call AutoLoad,27,rt61pci)
+endef
+
+define KernelPackage/rt73-usb
+  $(call KernelPackage/rt2x00/Default)
+  DEPENDS+= @USB_SUPPORT +kmod-rt2x00-usb
+  TITLE+= (RT73 USB)
+  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/rt2x00/rt73usb.$(LINUX_KMOD_SUFFIX)
+  AUTOLOAD:=$(call AutoLoad,27,rt73usb)
+endef
+
+RT2X00_CONFOPTS:=CONFIG_RT2X00=y \
+               CONFIG_RT2X00_DEBUG=y \
+               CONFIG_RT2X00_LIB_FIRMWARE=y \
+               CONFIG_RT2X00_LIB_LEDS=y
+
+ifneq ($(CONFIG_PACKAGE_kmod-rt2x00-pci),)
+  RT2X00_CONFOPTS+= CONFIG_RT2X00_LIB_PCI=y
+endif
+ifneq ($(CONFIG_PACKAGE_kmod-rt2x00-usb),)
+  RT2X00_CONFOPTS+= CONFIG_RT2X00_LIB_USB=y
+endif
+ifneq ($(CONFIG_PACKAGE_kmod-rt2400-pci),)
+  RT2X00_CONFOPTS+= CONFIG_RT2400PCI=y
+endif
+ifneq ($(CONFIG_PACKAGE_kmod-rt2500-pci),)
+  RT2X00_CONFOPTS+= CONFIG_RT2500PCI=y
+endif
+ifneq ($(CONFIG_PACKAGE_kmod-rt2500-usb),)
+  RT2X00_CONFOPTS+= CONFIG_RT2500USB=y
+endif
+ifneq ($(CONFIG_PACKAGE_kmod-rt61-pci),)
+  RT2X00_CONFOPTS+= CONFIG_RT61PCI=y
+endif
+ifneq ($(CONFIG_PACKAGE_kmod-rt73-usb),)
+  RT2X00_CONFOPTS+= CONFIG_RT73USB=y
+endif
+
+
+CONFOPTS:=MAC80211 CFG80211 NL80211 MAC80211_RC_DEFAULT_PID MAC80211_RC_PID \
 
 BUILDFLAGS:= \
        $(foreach opt,$(CONFOPTS),-DCONFIG_$(opt)) \
        $(if $(CONFIG_LEDS_TRIGGERS), -DCONFIG_MAC80211_LEDS -DCONFIG_LEDS_TRIGGERS) \
-       -D__CONFIG_MAC80211_RC_DEFAULT=pid
+       -D__CONFIG_MAC80211_RC_DEFAULT=pid \
 
 MAKE_OPTS:= \
        CROSS_COMPILE="$(TARGET_CROSS)" \
@@ -56,6 +172,8 @@ define Build/Prepare
        mkdir -p $(PKG_BUILD_DIR)
        $(PKG_UNPACK)
        $(if $(QUILT),touch $(PKG_BUILD_DIR)/.quilt_used)
+       unzip -jod $(PKG_BUILD_DIR) $(DL_DIR)/$(RT61FW)
+       unzip -jod $(PKG_BUILD_DIR) $(DL_DIR)/$(RT71FW)
 endef
 
 define Build/Compile
@@ -72,4 +190,23 @@ define KernelPackage/mac80211/install
        $(INSTALL_DATA) ./files/lib/wifi/mac80211.sh $(1)/lib/wifi
 endef
 
+define KernelPackage/rt61-pci/install
+       $(INSTALL_DIR) $(1)/lib/firmware
+       $(INSTALL_DATA) $(PKG_BUILD_DIR)/rt2?61*.bin $(1)/lib/firmware/
+endef
+
+define KernelPackage/rt73-usb/install
+       $(INSTALL_DIR) $(1)/lib/firmware
+       $(INSTALL_DATA) $(PKG_BUILD_DIR)/rt73.bin $(1)/lib/firmware/
+endef
+
+
 $(eval $(call KernelPackage,mac80211))
+$(eval $(call KernelPackage,rt2x00-lib))
+$(eval $(call KernelPackage,rt2x00-pci))
+$(eval $(call KernelPackage,rt2x00-usb))
+$(eval $(call KernelPackage,rt2400-pci))
+$(eval $(call KernelPackage,rt2500-pci))
+$(eval $(call KernelPackage,rt2500-usb))
+$(eval $(call KernelPackage,rt61-pci))
+$(eval $(call KernelPackage,rt73-usb))
diff --git a/package/rt2x00/Makefile b/package/rt2x00/Makefile
deleted file mode 100644 (file)
index 940ef9b..0000000
+++ /dev/null
@@ -1,180 +0,0 @@
-# 
-# Copyright (C) 2007 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-# $Id: $
-
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/kernel.mk
-
-PKG_NAME:=rt2x00
-PKG_VERSION:=$(KERNEL_VERSION)
-
-include $(INCLUDE_DIR)/package.mk
-
-
-RT61FW:=RT61_Firmware_V1.2.zip
-RT71FW:=RT71W_Firmware_V1.8.zip
-
-define Download/rt61
-  FILE:=$(RT61FW)
-  URL:=http://www.ralinktech.com.tw/data/
-  MD5SUM:=d4c690c93b470bc9a681297c2adc6281
-endef
-$(eval $(call Download,rt61))
-
-define Download/rt71w
-  FILE:=$(RT71FW)
-  URL:=http://www.ralinktech.com.tw/data/
-  MD5SUM:=1e7a5dc574e0268574fcda3fd5cf52f7
-endef
-$(eval $(call Download,rt71w))
-
-# XXX: remove @!TARGET_* later when we have PCI & USB support properly detected on all targets
-define KernelPackage/rt2x00/Default
-  SUBMENU:=Wireless Drivers
-  TITLE:=Ralink Drivers for RT2x00 cards
-  DEPENDS:=@LINUX_2_6_24 @!TARGET_atheros @!TARGET_uml
-endef
-
-define KernelPackage/rt2x00-lib
-$(call KernelPackage/rt2x00/Default)
-  DEPENDS+= @PCI_SUPPORT||USB_SUPPORT +kmod-mac80211
-  TITLE+= (LIB)
-  FILES:=$(PKG_BUILD_DIR)/rt2x00lib.$(LINUX_KMOD_SUFFIX)
-  AUTOLOAD:=$(call AutoLoad,25,blkcipher ecb arc4 rt2x00lib)
-endef
-
-define KernelPackage/rt2x00-pci
-$(call KernelPackage/rt2x00/Default)
-  DEPENDS+= @PCI_SUPPORT +kmod-rt2x00-lib +kmod-eeprom-93cx6
-  TITLE+= (PCI)
-  FILES:=$(PKG_BUILD_DIR)/rt2x00pci.$(LINUX_KMOD_SUFFIX)
-  AUTOLOAD:=$(call AutoLoad,26,rt2x00pci)
-endef
-
-define KernelPackage/rt2x00-usb
-$(call KernelPackage/rt2x00/Default)
-  DEPENDS+= @USB_SUPPORT +kmod-rt2x00-lib +kmod-usb-core
-  TITLE+= (USB)
-  FILES:=$(PKG_BUILD_DIR)/rt2x00usb.$(LINUX_KMOD_SUFFIX)
-  AUTOLOAD:=$(call AutoLoad,26,rt2x00usb)
-endef
-
-define KernelPackage/rt2400-pci
-$(call KernelPackage/rt2x00/Default)
-  DEPENDS+= @PCI_SUPPORT +kmod-rt2x00-pci
-  TITLE+= (RT2400 PCI)
-  FILES:=$(PKG_BUILD_DIR)/rt2400pci.$(LINUX_KMOD_SUFFIX)
-  AUTOLOAD:=$(call AutoLoad,27,rt2400pci)
-endef
-
-define KernelPackage/rt2500-pci
-$(call KernelPackage/rt2x00/Default)
-  DEPENDS+= @PCI_SUPPORT +kmod-rt2x00-pci
-  TITLE+= (RT2500 PCI)
-  FILES:=$(PKG_BUILD_DIR)/rt2500pci.$(LINUX_KMOD_SUFFIX)
-  AUTOLOAD:=$(call AutoLoad,27,rt2500pci)
-endef
-
-define KernelPackage/rt2500-usb
-$(call KernelPackage/rt2x00/Default)
-  DEPENDS+= @USB_SUPPORT +kmod-rt2x00-usb +kmod-crc-itu-t
-  TITLE+= (RT2500 USB)
-  FILES:=$(PKG_BUILD_DIR)/rt2500usb.$(LINUX_KMOD_SUFFIX)
-  AUTOLOAD:=$(call AutoLoad,27,rt2500usb)
-endef
-
-define KernelPackage/rt61-pci
-$(call KernelPackage/rt2x00/Default)
-  DEPENDS+= @PCI_SUPPORT +kmod-rt2x00-pci +kmod-crc-itu-t
-  TITLE+= (RT2x61 PCI)
-  FILES:=$(PKG_BUILD_DIR)/rt61pci.$(LINUX_KMOD_SUFFIX)
-  AUTOLOAD:=$(call AutoLoad,27,rt61pci)
-endef
-
-define KernelPackage/rt73-usb
-  $(call KernelPackage/rt2x00/Default)
-  DEPENDS+= @USB_SUPPORT +kmod-rt2x00-usb
-  TITLE+= (RT73 USB)
-  FILES:=$(PKG_BUILD_DIR)/rt73usb.$(LINUX_KMOD_SUFFIX)
-  AUTOLOAD:=$(call AutoLoad,27,rt73usb)
-endef
-
-$(STAMP_PREPARED): $(DL_DIR)/$(PKG_FW6X_NAME) $(DL_DIR)/$(PKG_FW7X_NAME)
-
-PKG_EXTRA_KCONFIG:= \
-       CONFIG_MAC80211=y \
-       CONFIG_RT2X00=y \
-       CONFIG_RT2X00_DEBUG=y \
-       CONFIG_RT2X00_LIB_FIRMWARE=y \
-
-ifneq ($(CONFIG_PACKAGE_kmod-rt2x00-pci),)
-  PKG_EXTRA_KCONFIG+= CONFIG_RT2X00PCI=y
-endif
-ifneq ($(CONFIG_PACKAGE_kmod-rt2x00-usb),)
-  PKG_EXTRA_KCONFIG+= CONFIG_RT2X00USB=y
-endif
-ifneq ($(CONFIG_PACKAGE_kmod-rt2400-pci),)
-  PKG_EXTRA_KCONFIG+= CONFIG_RT2400PCI=y
-endif
-ifneq ($(CONFIG_PACKAGE_kmod-rt2500-pci),)
-  PKG_EXTRA_KCONFIG+= CONFIG_RT2500PCI=y
-endif
-ifneq ($(CONFIG_PACKAGE_kmod-rt2500-usb),)
-  PKG_EXTRA_KCONFIG+= CONFIG_RT2500USB=y
-endif
-ifneq ($(CONFIG_PACKAGE_kmod-rt61-pci),)
-  PKG_EXTRA_KCONFIG+= CONFIG_RT61PCI=y
-endif
-ifneq ($(CONFIG_PACKAGE_kmod-rt73-usb),)
-  PKG_EXTRA_KCONFIG+= CONFIG_RT73USB=y
-endif
-
-PKG_EXTRA_CFLAGS:= \
-       -I$(STAGING_DIR)/usr/include/mac80211 \
-       $(patsubst CONFIG_%, -DCONFIG_%=1, $(patsubst %=m,%,$(filter %=m,$(PKG_EXTRA_KCONFIG)))) \
-       $(patsubst CONFIG_%, -DCONFIG_%=1, $(patsubst %=y,%,$(filter %=y,$(PKG_EXTRA_KCONFIG)))) \
-
-define Build/Prepare
-       $(call Build/Prepare/Default)
-       $(CP) src/* $(PKG_BUILD_DIR)/
-       unzip -jod $(PKG_BUILD_DIR) $(DL_DIR)/$(RT61FW)
-       unzip -jod $(PKG_BUILD_DIR) $(DL_DIR)/$(RT71FW)
-endef
-
-define Build/Configure
-       touch $(PKG_BUILD_DIR)/rt2x00_config.h
-endef
-
-define Build/Compile
-       $(MAKE) -C "$(LINUX_DIR)" \
-               ARCH="$(LINUX_KARCH)" \
-               CROSS_COMPILE="$(TARGET_CROSS)" \
-               SUBDIRS="$(PKG_BUILD_DIR)" \
-               $(PKG_EXTRA_KCONFIG) \
-               EXTRA_CFLAGS="$(PKG_EXTRA_CFLAGS)" \
-               V="$(V)" \
-               modules
-endef
-
-define KernelPackage/rt61-pci/install
-       $(INSTALL_DIR) $(1)/lib/firmware
-       $(INSTALL_DATA) $(PKG_BUILD_DIR)/rt2?61*.bin $(1)/lib/firmware/
-endef
-
-define KernelPackage/rt73-usb/install
-       $(INSTALL_DIR) $(1)/lib/firmware
-       $(INSTALL_DATA) $(PKG_BUILD_DIR)/rt73.bin $(1)/lib/firmware/
-endef
-
-$(eval $(call KernelPackage,rt2x00-lib))
-$(eval $(call KernelPackage,rt2x00-pci))
-$(eval $(call KernelPackage,rt2x00-usb))
-$(eval $(call KernelPackage,rt2400-pci))
-$(eval $(call KernelPackage,rt2500-pci))
-$(eval $(call KernelPackage,rt2500-usb))
-$(eval $(call KernelPackage,rt61-pci))
-$(eval $(call KernelPackage,rt73-usb))
diff --git a/package/rt2x00/src/COPYING b/package/rt2x00/src/COPYING
deleted file mode 100644 (file)
index 5b6e7c6..0000000
+++ /dev/null
@@ -1,340 +0,0 @@
-                   GNU GENERAL PUBLIC LICENSE
-                      Version 2, June 1991
-
- Copyright (C) 1989, 1991 Free Software Foundation, Inc.
-                       59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- Everyone is permitted to copy and distribute verbatim copies
- of this license document, but changing it is not allowed.
-
-                           Preamble
-
-  The licenses for most software are designed to take away your
-freedom to share and change it.  By contrast, the GNU General Public
-License is intended to guarantee your freedom to share and change free
-software--to make sure the software is free for all its users.  This
-General Public License applies to most of the Free Software
-Foundation's software and to any other program whose authors commit to
-using it.  (Some other Free Software Foundation software is covered by
-the GNU Library General Public License instead.)  You can apply it to
-your programs, too.
-
-  When we speak of free software, we are referring to freedom, not
-price.  Our General Public Licenses are designed to make sure that you
-have the freedom to distribute copies of free software (and charge for
-this service if you wish), that you receive source code or can get it
-if you want it, that you can change the software or use pieces of it
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-anyone to deny you these rights or to ask you to surrender the rights.
-These restrictions translate to certain responsibilities for you if you
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-(2) offer you this license which gives you legal permission to copy,
-distribute and/or modify the software.
-
-  Also, for each author's protection and ours, we want to make certain
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-
-  The precise terms and conditions for copying, distribution and
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-\f
-                   GNU GENERAL PUBLIC LICENSE
-   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
-
-  0. This License applies to any program or other work which contains
-a notice placed by the copyright holder saying it may be distributed
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-means either the Program or any derivative work under copyright law:
-that is to say, a work containing the Program or a portion of it,
-either verbatim or with modifications and/or translated into another
-language.  (Hereinafter, translation is included without limitation in
-the term "modification".)  Each licensee is addressed as "you".
-
-Activities other than copying, distribution and modification are not
-covered by this License; they are outside its scope.  The act of
-running the Program is not restricted, and the output from the Program
-is covered only if its contents constitute a work based on the
-Program (independent of having been made by running the Program).
-Whether that is true depends on what the Program does.
-
-  1. You may copy and distribute verbatim copies of the Program's
-source code as you receive it, in any medium, provided that you
-conspicuously and appropriately publish on each copy an appropriate
-copyright notice and disclaimer of warranty; keep intact all the
-notices that refer to this License and to the absence of any warranty;
-and give any other recipients of the Program a copy of this License
-along with the Program.
-
-You may charge a fee for the physical act of transferring a copy, and
-you may at your option offer warranty protection in exchange for a fee.
-
-  2. You may modify your copy or copies of the Program or any portion
-of it, thus forming a work based on the Program, and copy and
-distribute such modifications or work under the terms of Section 1
-above, provided that you also meet all of these conditions:
-
-    a) You must cause the modified files to carry prominent notices
-    stating that you changed the files and the date of any change.
-
-    b) You must cause any work that you distribute or publish, that in
-    whole or in part contains or is derived from the Program or any
-    part thereof, to be licensed as a whole at no charge to all third
-    parties under the terms of this License.
-
-    c) If the modified program normally reads commands interactively
-    when run, you must cause it, when started running for such
-    interactive use in the most ordinary way, to print or display an
-    announcement including an appropriate copyright notice and a
-    notice that there is no warranty (or else, saying that you provide
-    a warranty) and that users may redistribute the program under
-    these conditions, and telling the user how to view a copy of this
-    License.  (Exception: if the Program itself is interactive but
-    does not normally print such an announcement, your work based on
-    the Program is not required to print an announcement.)
-\f
-These requirements apply to the modified work as a whole.  If
-identifiable sections of that work are not derived from the Program,
-and can be reasonably considered independent and separate works in
-themselves, then this License, and its terms, do not apply to those
-sections when you distribute them as separate works.  But when you
-distribute the same sections as part of a whole which is a work based
-on the Program, the distribution of the whole must be on the terms of
-this License, whose permissions for other licensees extend to the
-entire whole, and thus to each and every part regardless of who wrote it.
-
-Thus, it is not the intent of this section to claim rights or contest
-your rights to work written entirely by you; rather, the intent is to
-exercise the right to control the distribution of derivative or
-collective works based on the Program.
-
-In addition, mere aggregation of another work not based on the Program
-with the Program (or with a work based on the Program) on a volume of
-a storage or distribution medium does not bring the other work under
-the scope of this License.
-
-  3. You may copy and distribute the Program (or a work based on it,
-under Section 2) in object code or executable form under the terms of
-Sections 1 and 2 above provided that you also do one of the following:
-
-    a) Accompany it with the complete corresponding machine-readable
-    source code, which must be distributed under the terms of Sections
-    1 and 2 above on a medium customarily used for software interchange; or,
-
-    b) Accompany it with a written offer, valid for at least three
-    years, to give any third party, for a charge no more than your
-    cost of physically performing source distribution, a complete
-    machine-readable copy of the corresponding source code, to be
-    distributed under the terms of Sections 1 and 2 above on a medium
-    customarily used for software interchange; or,
-
-    c) Accompany it with the information you received as to the offer
-    to distribute corresponding source code.  (This alternative is
-    allowed only for noncommercial distribution and only if you
-    received the program in object code or executable form with such
-    an offer, in accord with Subsection b above.)
-
-The source code for a work means the preferred form of the work for
-making modifications to it.  For an executable work, complete source
-code means all the source code for all modules it contains, plus any
-associated interface definition files, plus the scripts used to
-control compilation and installation of the executable.  However, as a
-special exception, the source code distributed need not include
-anything that is normally distributed (in either source or binary
-form) with the major components (compiler, kernel, and so on) of the
-operating system on which the executable runs, unless that component
-itself accompanies the executable.
-
-If distribution of executable or object code is made by offering
-access to copy from a designated place, then offering equivalent
-access to copy the source code from the same place counts as
-distribution of the source code, even though third parties are not
-compelled to copy the source along with the object code.
-\f
-  4. You may not copy, modify, sublicense, or distribute the Program
-except as expressly provided under this License.  Any attempt
-otherwise to copy, modify, sublicense or distribute the Program is
-void, and will automatically terminate your rights under this License.
-However, parties who have received copies, or rights, from you under
-this License will not have their licenses terminated so long as such
-parties remain in full compliance.
-
-  5. You are not required to accept this License, since you have not
-signed it.  However, nothing else grants you permission to modify or
-distribute the Program or its derivative works.  These actions are
-prohibited by law if you do not accept this License.  Therefore, by
-modifying or distributing the Program (or any work based on the
-Program), you indicate your acceptance of this License to do so, and
-all its terms and conditions for copying, distributing or modifying
-the Program or works based on it.
-
-  6. Each time you redistribute the Program (or any work based on the
-Program), the recipient automatically receives a license from the
-original licensor to copy, distribute or modify the Program subject to
-these terms and conditions.  You may not impose any further
-restrictions on the recipients' exercise of the rights granted herein.
-You are not responsible for enforcing compliance by third parties to
-this License.
-
-  7. If, as a consequence of a court judgment or allegation of patent
-infringement or for any other reason (not limited to patent issues),
-conditions are imposed on you (whether by court order, agreement or
-otherwise) that contradict the conditions of this License, they do not
-excuse you from the conditions of this License.  If you cannot
-distribute so as to satisfy simultaneously your obligations under this
-License and any other pertinent obligations, then as a consequence you
-may not distribute the Program at all.  For example, if a patent
-license would not permit royalty-free redistribution of the Program by
-all those who receive copies directly or indirectly through you, then
-the only way you could satisfy both it and this License would be to
-refrain entirely from distribution of the Program.
-
-If any portion of this section is held invalid or unenforceable under
-any particular circumstance, the balance of the section is intended to
-apply and the section as a whole is intended to apply in other
-circumstances.
-
-It is not the purpose of this section to induce you to infringe any
-patents or other property right claims or to contest validity of any
-such claims; this section has the sole purpose of protecting the
-integrity of the free software distribution system, which is
-implemented by public license practices.  Many people have made
-generous contributions to the wide range of software distributed
-through that system in reliance on consistent application of that
-system; it is up to the author/donor to decide if he or she is willing
-to distribute software through any other system and a licensee cannot
-impose that choice.
-
-This section is intended to make thoroughly clear what is believed to
-be a consequence of the rest of this License.
-\f
-  8. If the distribution and/or use of the Program is restricted in
-certain countries either by patents or by copyrighted interfaces, the
-original copyright holder who places the Program under this License
-may add an explicit geographical distribution limitation excluding
-those countries, so that distribution is permitted only in or among
-countries not thus excluded.  In such case, this License incorporates
-the limitation as if written in the body of this License.
-
-  9. The Free Software Foundation may publish revised and/or new versions
-of the General Public License from time to time.  Such new versions will
-be similar in spirit to the present version, but may differ in detail to
-address new problems or concerns.
-
-Each version is given a distinguishing version number.  If the Program
-specifies a version number of this License which applies to it and "any
-later version", you have the option of following the terms and conditions
-either of that version or of any later version published by the Free
-Software Foundation.  If the Program does not specify a version number of
-this License, you may choose any version ever published by the Free Software
-Foundation.
-
-  10. If you wish to incorporate parts of the Program into other free
-programs whose distribution conditions are different, write to the author
-to ask for permission.  For software which is copyrighted by the Free
-Software Foundation, write to the Free Software Foundation; we sometimes
-make exceptions for this.  Our decision will be guided by the two goals
-of preserving the free status of all derivatives of our free software and
-of promoting the sharing and reuse of software generally.
-
-                           NO WARRANTY
-
-  11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
-FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW.  EXCEPT WHEN
-OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
-PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
-OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.  THE ENTIRE RISK AS
-TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU.  SHOULD THE
-PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
-REPAIR OR CORRECTION.
-
-  12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
-WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
-REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
-INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
-OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
-TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
-YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
-PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES.
-
-                    END OF TERMS AND CONDITIONS
-\f
-           How to Apply These Terms to Your New Programs
-
-  If you develop a new program, and you want it to be of the greatest
-possible use to the public, the best way to achieve this is to make it
-free software which everyone can redistribute and change under these terms.
-
-  To do so, attach the following notices to the program.  It is safest
-to attach them to the start of each source file to most effectively
-convey the exclusion of warranty; and each file should have at least
-the "copyright" line and a pointer to where the full notice is found.
-
-    <one line to give the program's name and a brief idea of what it does.>
-    Copyright (C) <year>  <name of author>
-
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-
-Also add information on how to contact you by electronic and paper mail.
-
-If the program is interactive, make it output a short notice like this
-when it starts in an interactive mode:
-
-    Gnomovision version 69, Copyright (C) year name of author
-    Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
-    This is free software, and you are welcome to redistribute it
-    under certain conditions; type `show c' for details.
-
-The hypothetical commands `show w' and `show c' should show the appropriate
-parts of the General Public License.  Of course, the commands you use may
-be called something other than `show w' and `show c'; they could even be
-mouse-clicks or menu items--whatever suits your program.
-
-You should also get your employer (if you work as a programmer) or your
-school, if any, to sign a "copyright disclaimer" for the program, if
-necessary.  Here is a sample; alter the names:
-
-  Yoyodyne, Inc., hereby disclaims all copyright interest in the program
-  `Gnomovision' (which makes passes at compilers) written by James Hacker.
-
-  <signature of Ty Coon>, 1 April 1989
-  Ty Coon, President of Vice
-
-This General Public License does not permit incorporating your program into
-proprietary programs.  If your program is a subroutine library, you may
-consider it more useful to permit linking proprietary applications with the
-library.  If this is what you want to do, use the GNU Library General
-Public License instead of this License.
diff --git a/package/rt2x00/src/Makefile b/package/rt2x00/src/Makefile
deleted file mode 100644 (file)
index 3aeb405..0000000
+++ /dev/null
@@ -1,150 +0,0 @@
-#      Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
-#      <http://rt2x00.serialmonkey.com>
-#
-#      This program is free software; you can redistribute it and/or modify
-#      it under the terms of the GNU General Public License as published by
-#      the Free Software Foundation; either version 2 of the License, or
-#      (at your option) any later version.
-#
-#      This program is distributed in the hope that it will be useful,
-#      but WITHOUT ANY WARRANTY; without even the implied warranty of
-#      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-#      GNU General Public License for more details.
-#
-#      You should have received a copy of the GNU General Public License
-#      along with this program; if not, write to the
-#      Free Software Foundation, Inc.,
-#      59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
-
-#      Module: Makefile
-#      Abstract: Makefile for rt2x00 kernel module
-
-#
-# Set the enviroment variables.
-#
-ifndef SUBDIRS
-       SUBDIRS=$(shell pwd)
-endif
-
-ifdef KERNDIR
-       KERNEL_SOURCES := $(KERNDIR)
-else
-       KERNEL_SOURCES := /lib/modules/$(shell uname -r)/build
-endif
-
-ifdef KERNOUT
-       KERNEL_OUTPUT := KBUILD_OUTPUT=$(KERNOUT)
-else
-       KERNEL_OUTPUT :=
-endif
-
-#
-# Determine if and with what options the rt2x00 drivers should be build
-#
-rt2x00lib-objs := rt2x00dev.o rt2x00mac.o rt2x00config.o rt2x00firmware.o
-
-ifeq ($(CONFIG_RT2X00),y)
-       obj-m += rt2x00lib.o
-
-ifeq ($(CONFIG_RT2X00PCI),y)
-       obj-m += rt2x00pci.o
-endif
-
-ifeq ($(CONFIG_RT2X00USB),y)
-       obj-m += rt2x00usb.o
-endif
-
-ifeq ($(CONFIG_RT2X00_LIB_DEBUGFS),y)
-       rt2x00lib-objs += rt2x00debug.o
-endif
-
-ifeq ($(CONFIG_RT2400PCI),y)
-       obj-m += rt2400pci.o
-ifeq ($(CONFIG_RT2400PCI_RFKILL),y)
-       rt2x00lib-objs += rt2x00rfkill.o
-       EXTRA_CFLAGS += -DCONFIG_RT2X00_LIB_RFKILL
-endif
-endif
-
-ifeq ($(CONFIG_RT2500PCI),y)
-       obj-m += rt2500pci.o
-ifeq ($(CONFIG_RT2500PCI_RFKILL),y)
-       rt2x00lib-objs += rt2x00rfkill.o
-       EXTRA_CFLAGS += -DCONFIG_RT2X00_LIB_RFKILL
-endif
-endif
-
-ifeq ($(CONFIG_RT2500USB),y)
-       obj-m += rt2500usb.o
-endif
-
-ifeq ($(CONFIG_RT61PCI),y)
-       EXTRA_CFLAGS += -DCONFIG_RT2X00_LIB_FIRMWARE
-       rt2x00lib-objs += rt2x00firmware.o
-       obj-m += rt61pci.o
-ifeq ($(CONFIG_RT61PCI_RFKILL),y)
-       rt2x00lib-objs += rt2x00rfkill.o
-       EXTRA_CFLAGS += -DCONFIG_RT2X00_LIB_RFKILL
-endif
-endif
-
-ifeq ($(CONFIG_RT73USB),y)
-       EXTRA_CFLAGS += -DCONFIG_RT2X00_LIB_FIRMWARE
-       rt2x00lib-objs += rt2x00firmware.o
-       obj-m += rt73usb.o
-endif
-
-endif
-
-MAKEFLAGS += --no-print-directory
-EXTRA_CFLAGS := -include $(SUBDIRS)/rt2x00_compat.h $(CFLAGS)
-
-all: default
-
-config_header:
-       @if [ ! -f "rt2x00_config.h" ] || [ "rt2x00_config.h" -ot "config" ]; \
-       then \
-               awk -F = > rt2x00_config.h < config '/^CONFIG.*$\/ \
-               { \
-                       if($$2 == "y") { \
-                               print "#ifndef " $$1; \
-                               print "#define " $$1; \
-                               print "#endif"; \
-                               print "" \
-                       } else { \
-                               print "#undef " $$1; \
-                               print ""; \
-                       } \
-               }'; \
-       fi
-
-default: config_header
-       @$(MAKE) -C $(KERNEL_SOURCES) SUBDIRS=$(SUBDIRS) $(KERNEL_OUTPUT) \
-               modules
-
-sparse: config_header
-       @$(MAKE) -C $(KERNEL_SOURCES) SUBDIRS=$(SUBDIRS) $(KERNEL_OUTPUT) \
-               modules C=1 CF=-D__CHECK_ENDIAN__
-
-install: config_header
-       @$(MAKE) -C $(KERNEL_SOURCES) SUBDIRS=$(SUBDIRS) $(KERNEL_OUTPUT) \
-               INSTALL_MOD_DIR=rt2x00 $(KERNEL_OUTPUT) modules_install
-       /sbin/depmod -a
-
-clean:
-       @rm -f rt2x00_config.h
-       @rm -f Modules.symvers Module.symvers
-       @for folder in $(EXTMODDIRS); \
-       do \
-               rm -f $${folder}/*.o \
-               rm -f $${folder}/*.ko \
-               rm -f $${folder}/*.s \
-               rm -f $${folder}/*.mod.c \
-               rm -f $${folder}/.*.cmd \
-               rm -f $${folder}/.*.flags \
-               rm -f $${folder}/.*.o.d \
-               rm -f $${folder}/.*.s.d \
-               rm -f $${folder}/.#* \
-               rm -f $${folder}/*~ \
-               rm -fr $${folder}/.tmp_versions; \
-       done
diff --git a/package/rt2x00/src/README b/package/rt2x00/src/README
deleted file mode 100644 (file)
index 7f3f448..0000000
+++ /dev/null
@@ -1,548 +0,0 @@
-===============================================================================
- Installation and configuration instructions for the rt2x00 Modules
-===============================================================================
-
-===============================================================================
- Table of contents:
-========================
-
- - 1: Minimal requirements
-   - 1.1: kernel
-   - 1.2: gcc
-   - 1.3: make
- - 2: Hardware
-   - 2.1: Chipsets
-   - 2.2: RF button
- -  3: Module building & Installation
-   - 3.1: Introduction
-   - 3.2: Configure
-   - 3.3: Build
-   - 3.4: Installation
- - 4: Firmware
-   - 4.1: Firmware files
-   - 4.2: Firmware installation
-   - 4.3: Firmware requirements
- - 5: Module loading
-   - 5.1: Module load order
-   - 5.2: Module load options
- - 6: Interfaces
-   - 6.1: Wireless interfaces
-   - 6.2: Input interface
- - 7: Interface configuration
-   - 7.1: Minimal configuration
-   - 7.2: Configuration tools
- - 8: Distribution specific notes
-   - 8.1: Debian & derivatives
-   - 8.2: Fedora
-   - 8.3: Gentoo
-   - 8.4: Mandriva
- - 9: Problems & Troubleshooting
-   - 9.1: Debug information
-   - 9.2: Debugfs
-   - 9.3: Bug reporting
- - 10: Problems & Workarounds
-   - 10.1: udev interface naming
-   - 10.2: BUG - ifdown & ifup radio failure
- - 11: TODO list
- - 12: Contact us
-
-
-===============================================================================
- 1: Minimal requirements:
-=======================================
-
-===================
- 1.1: kernel
-=========
-
- - The minimal required kernel version is 2.6.22-rc1
-
- - It is important that the installed kernel sources match
-   the running kernel. Unless you are crosscompiling and you
-   know what you are doing.
-
- - Depending on what rt2x00 components will be built,
-   some kernel configuration options are mandatory.
-   It does however not matter if these options are compiled
-   into the kernel or compiled as module.
-
-       Kernel config option    Required for component
-       ------------------------------------------------------------------
-       # CONFIG_NET_RADIO      all
-       # CONFIG_MAC80211       all
-       # CONFIG_WLAN_80211     all
-       # CONFIG_PCI            rt2400pci, rt2500pci, rt61pci
-       # CONFIG_USB            rt2500usb, rt73usb
-       # CONFIG_HOTPLUG        rt61pci, rt73usb
-       # CONFIG_FW_LOADER      rt61pci, rt73usb
-       # CONFIG_CRC_ITU_T      rt61pci, rt73usb
-       # CONFIG_DEBUG_FS       rt2x00 (optional, only for debug)
-       # CONFIG_RFKILL         rt2400pci, rt2500pci, rt61pci (optional,
-                                                       only for button support)
-
-===================
- 1.2: GCC
-=========
-
- - For building the rt2x00 components the same gcc version is required
-   as was used to build your target kernel.
-
-===================
- 1.3: make
-=========
-
- - The program 'make' needs to be installed on the system. There are no
-   further special requirements for this program.
-
-===============================================================================
- 2: Hardware
-=======================================
-
-===================
- 2.1: Chipsets
-=========
-
- Support for each Ralink wireless chipset has been split into separate drivers.
-
-       # rt2400pci
-               - chipset: rt2400
-               - supports: rt2460
-               - bus type: PCI/PCMCIA/miniPCI
-       # rt2500pci
-               - chipset: rt2500
-               - supports: rt2560
-               - bus type: PCI/PCMCIA/miniPCI
-       # rt2500usb
-               - chipset: rt2570
-               - supports: rt2570
-               - bus type: USB
-       # rt61pci
-               - chipset: rt61 (or rt2600)
-               - supports: rt2561, rt2561s, rt2661
-               - bus type: PCI/PCMCIA/miniPCI
-       # rt73usb
-               - chipset: rt73
-               - supports: rt2571(w), rt2573, rt2671
-               - bus type: USB
-
-===================
- 2.2: RF button
-=========
-
- On some occasions the Ralink chipset has been built into a laptop.
- If that is the case, there usually is a hardware button that controls the
- radio of the wireless interface.
- If you have such a hardware device, make sure you enable hardware button
- support for your device in the configuration before building the rt2x00
- components.
- Note: This feature requires the enabling of the rfkill driver in the kernel.
-
-===============================================================================
- 3: Module building & Installation
-=======================================
-
-===================
- 3.1: Introduction
-=========
-
- The following steps in this chapter concerning module building and
- installation need to be performed for each kernel. This means that
- after each kernel upgrade the modules need to be rebuild and
- reinstalled in order to make them work with the new kernel.
-
-===================
- 3.2: Configure
-=========
-
- Before starting to build the rt2x00 components it is recommended to look into
- the 'config' file first. In this file you can configure which components of
- rt2x00 should be built. And even more importantly, you can configure with
- what options the components will be built.
- To build all the rt2x00 drivers (with debug capabilities enabled) no changes
- in the configuration file are required. For most users this would be
- sufficient to start working with rt2x00.
-
-===================
- 3.3: Build
-=========
-
- To build all rt2x00 components which were enabled in the configuration file
- simply run (root privileges not required):
-
-       # $ make
-
- All modules (.ko files) will be created in the current directory.
-
-===================
- 3.4: Installation
-=========
-
- All rt2x00 modules can be installed by doing (with root privileges):
-
-        # $ make install
-
- With this command all rt2x00 modules (including rfkill and d80211) will be
- created in a newly created folder named 'rt2x00' inside the kernel modules
- directory (usually '/lib/modules/$(uname -r)/').
-
-
-==============================================================================
- 4: Firmware
-=======================================
-
-===================
- 4.1: Firmware files
-=========
-
- rt61pci and rt73usb require firmware to be available while loading the module.
- The following firmware files are available for each driver:
-
-       # rt61pci
-               - rt2561.bin
-               - rt2561s.bin
-               - rt2661.bin
-
-       # rt73usb
-               - rt73.bin
-
-===================
- 4.2: Firmware installation
-=========
-
- The latest firmware files are available in a separate .zip archive and can be
- downloaded from the support page on the Ralink website at
- http://www.ralinktech.com.
- Note that by a high level of logic, Ralink has named their firmware for rt73
- chipsets "rt71W" with a comment that it is for the rt2571W and rt2671 devices.
- For rt61pci 3 seperate firmware files are available, which one is used depends
- on which RT chip is on the device. Usually it is best to install all files.
- To install the firmware the firmware files need to be manually copied to the
- systems firmware folder (usually '/lib/firmware/') the exact folder depends
- on the distribution. When in doubt consult the distributions documentation.
-
-===================
- 4.3: Firmware requirements
-=========
-
- To load firmware when the module is loaded the hotplug daemon should be
- running. Make sure you either enable hotplugging manually before loading the
- module, or make sure hotplugging is enabled during the system boot process.
-
-
-==============================================================================
- 5: Module loading
-=======================================
-
-===================
- 5.1: Module load order
-=========
-
- When the modules have been properly installed by following the installation
- instructions from the previous section, the module handlers (i.e. modprobe)
- will automaticly resolve all module dependencies when loading the device
- specific driver.
-
- When loading the modules manually with insmod, you should load them in the
- following order:
-
-       # eeprom_93cx6.ko (optional, only required for pci devices)
-       # rt2x00lib.ko
-       # rt2x00pci.ko (optional, only required for pci devices)
-       # rt2x00usb.ko (optional, only required for usb devices)
-       # rt2400pci.ko (optional, only required for rt2400 support)
-       # rt2500pci.ko (optional, only required for rt2500 support)
-       # rt2500usb.ko (optional, only required for rt2570 support)
-       # rt61pci.ko (optional, only required for rt61 support)
-       # rt73usb.ko (optional, only required for rt73 support)
-
-===================
- 5.2: Module load options
-=========
-
- None.
-
-
-==============================================================================
- 6: Interfaces
-=======================================
-
-===================
- 6.1: Wireless interfaces
-=========
-
- After loading the modules two interfaces will now be visible in ifconfig and
- iwconfig, namely wmaster0 and wlan0. The first device is the so called master
- device which is can be used by some userspace tools, but normally can be
- ignored by the user. The second interface wlan0 is the client interface which
- the user can configure.
- With rt2x00 it is possible to run multiple client interfaces with
- only a single device. 1 client interface can run in adhoc, managed or master
- mode while a second interface can run in monitor mode at the same time.
- More client interfaces can be added by issuing the following command
- (with root privileges):
-
-       # $ echo -n <name> > /sys/class/ieee80211/<dev>/add_iface
-
- where the variable <name> is the name of the client interface that should be
- added (i.e. wlan1), and <dev> is the physical device where the new client
- interface should be attached to (i.e. phy0).
-
-===================
- 6.2: Input interface
-=========
-
- When the rfkill driver is being used a new input device with the name of the
- device specific module where the button belongs to will have been created.
- Whenever the user presses the hardware button the rfkill driver will
- automatically make sure the hardware radio is being disabled or enabled
- accordingly. When the user has opened the input device the radio will
- not be automatically controlled, but instead the input device will
- report all button events (KEY_RFKILL) to userspace where the user
- could have setup script to do all the work that has to be executed.
- This means that while the input device is opened, the user is responsible
- for the correct behaviour.
-
-
-==============================================================================
- 7: Interface configuration
-=======================================
-
-===================
- 7.1: Minimal configuration
-=========
-
- - After loading the modules the interface should be configured to start
-   an association or work in monitor mode. The following steps are required
-   for a minimal configuration to associate with a non-encrypted access point.
-
- - Before bringing the client interface up, the working mode should be set:
-
-       # $ iwconfig wlan0 mode managed
-
- - Configuration parts like essid and channel can be set before or after the
-   client interface has been brought up.
-
- - It is usually a good idea to set the essid:
-
-       # $ iwconfig wlan0 essid myessid
-
- - In some situations the device also requires the channel to be manually set:
-
-       # $ iwconfig wlan0 channel mychannel
-
- - To bring the client interface up:
-
-       # $ ifconfig wlan0 up
-
- - After the client interface has been brought up, scanning can be performed
-   to check if the desired AP is being detected.
-
-       # $ iwlist wlan0 scan
-
- - To start an association attempt, the AP address should be set:
-
-       # $ iwconfig wlan0 ap mybssid
-
-===================
- 7.2: Configuration tools
-=========
-
- To configure the interface several tools are possible, the most basic tools
- are the wireless-tools that provide the iwconfig, iwpriv and iwlist commands.
- For WPA connections the wireless-tools are not sufficient, to configure the
- interface for WPA wireless network wpa_supplicant is required.
- For master mode functionality it is possible to only use the wireless-tools,
- but it is recommended to use hostapd instead. This tool offers the best
- functionality.
- For all configuration tools (wireless-tools, wpa_supplicant and hostapd) are
- manuals and howto's present in the manpages or on the internet. It is adviced
- to have at least read the manpages before using the tools for a better
- understanding on configuring the interface.
-
-
-==============================================================================
- 8: Distribution specific notes
-=======================================
-
-===================
- 8.1: Debian & derivatives
-=========
-
- In some instances installing the rt2x00 drivers on debian will result
- in the problem that the files are being copied into the wrong folder,
- which results in the fact that the driver cannot be loaded.
- Installing the drivers should be done manually in this case,
- please refer to the distributions documentation regarding the proper
- location of the kernel modules.
-
-===================
- 8.2: Fedora
-=========
-
- Although rt2x00 contains many backward compatibility fixes to ensure
- that all rt2x00 components will be able to compile and run on all
- systems that meet the minimal requirements, this does not work in all
- situations when the Fedora kernels are being used.
- The problem lies in the fact that Fedora (like most other distributions)
- heavily patch their kernel for better stability and more features.
- Unlike the other distributions however, Fedora does not pay attention to
- compatibility for external kernel drivers. This means that compiling rt2x00
- while using a Fedora kernel will result in compile errors regarding unknown
- fields in structures or problems with function arguments.
- For rt2x00 it is impossible to make all checks to support all Fedora kernel
- releases. This means that when rt2x00 compilation is failing while using a
- Fedora kernel we cannot give support for the compilation steps.
- We recommend the user to complain to the Fedora developers when this problem
- occurs.
- If the user has managed to compile rt2x00 for a Fedora kernel we will
- give support for possible problems while working with rt2x00. So the only
- part we do not support is the building of rt2x00.
- Please note that when you have edited the rt2x00 code to make it compile,
- it is advised to state those changes in bugreports while reporting other
- problems with rt2x00.
-
-===================
- 8.3: Gentoo
-=========
-
- rt2x00 can also be found in portage, both the beta releases and the cvs tree.
- Because rt2x00 is still experimental these ebuild are still masked, this means
- that before you can emerge them they first have to be unmasked.
- Gentoo provides various instructions on how this can be done on their website.
-
-===================
- 8.4: Mandriva
-=========
-
- In some instances installing the rt2x00 drivers on Mandriva will result
- in the problem that the files are being copied into the wrong folder,
- which results in the fact that the driver cannot be loaded.
- Installing the drivers should be done manually in this case,
- please refer to the distributions documentation regarding the proper
- location of the kernel modules.
-
-
-==============================================================================
- 9: Problems & Troubleshooting
-=======================================
-
-===================
- 9.1: Debug information
-=========
-
- When reporting problems make sure the driver has been compiled with debug
- enabled.
- If you have done so, the debug output can be found in the output
- of 'dmesg' and also in /var/log/messages and /var/log/syslog.
-
-===================
- 9.2: Debugfs
-=========
-
- rt2x00 provides several debugfs entries which can be used to help
- provide more information about the interface.
- To see the rt2x00 debugfs entries, debugfs should first be mounted,
- to do this you should issue the following command:
-
-        # $ mount -t debugfs none /debug
-
- Where /debug is the directy on which the debugfs entries should appear,
- make sure this directory exists when mounting debugfs.
- With the debugfs folder, the rt2x00 folder with the rt2x00 debugfs entries
- will be created. Within the rt2x00 folder, each physical device will be
- represented by a folder named after the interface which belongs to this
- device. Within the folder the following files can be found:
-
-       # register
-               - This file contains the register contents of the interface.
-       # eeprom
-               - This file contains the eeprom contents of the interface.
-
-===================
- 9.3: Bug reporting
-=========
-
- When reporting a bug or problem with the rt2x00 module,
- make sure you report the following information:
-       # How to reproduce
-       # RT2x00 debug output, usually found in /var/log/messages
-       # Module version
-       # Wireless card chipset, model and manufacturer
-       # Kernel version (i.e. 2.6.17)
-       # Hardware architecture (i.e. x86, AMD64, Sparc)
-       # rt2x00 code changes done by the user
-       # Anything else you may think will help us resolve the issue
-
-
-==============================================================================
- 10: Problems & Workarounds
-=======================================
-
-===================
- 10.1: udev interface naming
-=========
-
- In some cases when loading the rt2x00 drivers the interface names are
- different from the names used in this README. This is usually caused by the
- udev handler who has set some rules regarding the interface. These rules
- are usually set up by the distribution and have been created especially for
- for the legacy driver and their strange behavior.
- To change the rules udev applies to your interface you should edit the udev
- rules stored in /etc/udev/rules.d/ (exact location might be different
- depending on distribution).
- When editing this file, search for the line that contains something like this:
-
-       # ACTION=="add", SUBSYSTEM=="net", DRIVERS=="?*",
-       #       SYSFS{address}=="<mac address>", NAME="<interface>"
-       (line has been wrapped due to max line length limit)
-
- Where <mac address> is the hardware address of your wireless networkcard,
- and <interface> is the interface name the interface takes as soon as the
- rt2x00 modules are loaded.
- This line should be changed to look like:
-
-       # ACTION=="add", SUBSYSTEM=="net", DRIVERS=="?*",
-       #       SYSFS{address}=="<mac address>", SYSFS{type}=="801",
-       #       NAME="wmaster0"
-       # ACTION=="add", SUBSYSTEM=="net", DRIVERS=="?*",
-       #       SYSFS{address}=="<mac address>", NAME="wlan0"
-       (the 2 lines have been wrapped due to max line length limit)
-
- Where <mac address> is the hardware address of your wireless networkcard,
- and thus should be the same as on the original line.
-
-===================
- 10.2: BUG - ifdown & ifup radio failure
-=========
-
- It is a known issue (and BUG) that the driver will fail to correctly resume
- its radio operations after the interface has been brought down and up again.
- It is still unknown what the cause for this issue could be, besides the fact
- that for some reason the device's registers have been incorrectly initialized.
- This issue also has impact on the device status after a suspend/resume
- operation. There is no known workaround for this yet.
-
-
-==============================================================================
- 11: TODO list
-=======================================
- See http://rt2x00.serialmonkey.com/wiki/index.php/Rt2x00_beta
-
-==============================================================================
- 12: Contact us
-=======================================
-
- - Website
-       # http://rt2x00.serialmonkey.com/
-       # http://rt2x00.serialmonkey.com/wiki/index.php/Rt2x00_beta
-
- - Forums:
-       # http://rt2x00.serialmonkey.com/phpBB2/
-
- - Mailing list:
-       # general: rt2400-general@lists.sourceforge.net
-       # developers: rt2400-devel@lists.sourceforge.net
-
- - Sourceforge:
-       # http://sourceforge.net/projects/rt2400
-
diff --git a/package/rt2x00/src/THANKS b/package/rt2x00/src/THANKS
deleted file mode 100644 (file)
index 81b88d2..0000000
+++ /dev/null
@@ -1,54 +0,0 @@
-A big thanks to all the developers, testers and supporters of
-the rt2x00 Linux source code.
-
-Thanks to the projects main developers:
-* Mark Wallis - mwallis@serialmonkey.com
-* Ivo van Doorn - IvDoorn@gmail.com
-* Luis Correia - lfcorreia@users.sf.net
-* Robin Cornelius - robin.cornelius@gmail.com
-* Gertjan van Wingerde - gwingerde@kpnplanet.nl
-* Romain - spy84464@hotmail.com
-
-Special thanks to the contributors of this project:
-* Adisorn Ermongkonchai - moo7822-wlan@yahoo.com
-* Amir Shalem - amir@boom.org.il
-* Bernd Petrovitsch - bernd@firmix.at
-* Bruno - bruno123@users.sf.net
-* Chris Houston - chris.houston@atterotech.com
-* Defekt - defekt@liquid-nexus.net
-* Edvard - eaglenest@users.sourceforge.net
-* Flavio Stanchina - flavio@stanchina.net
-* Gregor Glomm - gg@seh.de
-* Heikki Pernu - heikki.pernu@nekonet.fi
-* Jerzy Kozera - nordom@tlen.pl
-* Joachim Glei├čner - jg@suse.de
-* John Coppens - john@jcoppens.com
-* Jonathan Hudson
-* KrissN - krissn@op.pl
-* Luca Tettamanti - kronos.it@gmail.com
-* Magnus Damm - magnus.damm@gmail.com
-* Mags
-* Mathias Klien - ma_klein@gmx.de
-* Meelis Roos - mroos@linux.ee
-* Michal Ludvig - michal@logix.cz
-* Miguel - miguel.marte2@verizon.net
-* Mike Skinner
-* Olivier Cornu - o.cornu@gmail.com
-* Paul Hampson - Paul.Hampson@anu.edu.au
-* Philippe Rousselot - amazilia@users.sourceforge.net
-* Remco - remco@d-compu.dyndns.org
-* Sergey Vlasov - vsu@altlinux.ru
-* Stephen Warren - SWarren@nvidia.com
-* Stuart Rackham - srackham@methods.co.nz
-* Thor Harald Johansen - thorhajo@gmail.com
-* Tor Petterson - 2r@manowar.dk
-
-Special thanks:
-* Ralink - http://www.ralinktech.com.tw
-  For releasing their rt2400/rt2500/rt2570 drivers under the GPL,
-  and their assistance in providing documentation to help development.
-* Minitar - www.minitar.com
-  For working together with Ralink on releasing the
-  rt2400/rt2500/rt2570 drivers under the GPL.
-* All the people that have assisted with the rt2400/rt2500/rt2570 source
-  and hence progressed the rt2x00 along the way.
diff --git a/package/rt2x00/src/rt2400pci.c b/package/rt2x00/src/rt2400pci.c
deleted file mode 100644 (file)
index 31c1dd2..0000000
+++ /dev/null
@@ -1,1664 +0,0 @@
-/*
-       Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
-       <http://rt2x00.serialmonkey.com>
-
-       This program is free software; you can redistribute it and/or modify
-       it under the terms of the GNU General Public License as published by
-       the Free Software Foundation; either version 2 of the License, or
-       (at your option) any later version.
-
-       This program is distributed in the hope that it will be useful,
-       but WITHOUT ANY WARRANTY; without even the implied warranty of
-       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-       GNU General Public License for more details.
-
-       You should have received a copy of the GNU General Public License
-       along with this program; if not, write to the
-       Free Software Foundation, Inc.,
-       59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-/*
-       Module: rt2400pci
-       Abstract: rt2400pci device specific routines.
-       Supported chipsets: RT2460.
- */
-
-/*
- * Set enviroment defines for rt2x00.h
- */
-#define DRV_NAME "rt2400pci"
-
-#include <linux/delay.h>
-#include <linux/etherdevice.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/pci.h>
-#include <linux/eeprom_93cx6.h>
-
-#include "rt2x00.h"
-#include "rt2x00pci.h"
-#include "rt2400pci.h"
-
-/*
- * Register access.
- * All access to the CSR registers will go through the methods
- * rt2x00pci_register_read and rt2x00pci_register_write.
- * BBP and RF register require indirect register access,
- * and use the CSR registers BBPCSR and RFCSR to achieve this.
- * These indirect registers work with busy bits,
- * and we will try maximal REGISTER_BUSY_COUNT times to access
- * the register while taking a REGISTER_BUSY_DELAY us delay
- * between each attampt. When the busy bit is still set at that time,
- * the access attempt is considered to have failed,
- * and we will print an error.
- */
-static u32 rt2400pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
-{
-       u32 reg;
-       unsigned int i;
-
-       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
-               rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
-               if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
-                       break;
-               udelay(REGISTER_BUSY_DELAY);
-       }
-
-       return reg;
-}
-
-static void rt2400pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
-                               const unsigned int word, const u8 value)
-{
-       u32 reg;
-
-       /*
-        * Wait until the BBP becomes ready.
-        */
-       reg = rt2400pci_bbp_check(rt2x00dev);
-       if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
-               ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
-               return;
-       }
-
-       /*
-        * Write the data into the BBP.
-        */
-       reg = 0;
-       rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
-       rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
-       rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
-       rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
-
-       rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
-}
-
-static void rt2400pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
-                              const unsigned int word, u8 *value)
-{
-       u32 reg;
-
-       /*
-        * Wait until the BBP becomes ready.
-        */
-       reg = rt2400pci_bbp_check(rt2x00dev);
-       if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
-               ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
-               return;
-       }
-
-       /*
-        * Write the request into the BBP.
-        */
-       reg = 0;
-       rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
-       rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
-       rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
-
-       rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
-
-       /*
-        * Wait until the BBP becomes ready.
-        */
-       reg = rt2400pci_bbp_check(rt2x00dev);
-       if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
-               ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
-               *value = 0xff;
-               return;
-       }
-
-       *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
-}
-
-static void rt2400pci_rf_write(const struct rt2x00_dev *rt2x00dev,
-                              const unsigned int word, const u32 value)
-{
-       u32 reg;
-       unsigned int i;
-
-       if (!word)
-               return;
-
-       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
-               rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
-               if (!rt2x00_get_field32(reg, RFCSR_BUSY))
-                       goto rf_write;
-               udelay(REGISTER_BUSY_DELAY);
-       }
-
-       ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
-       return;
-
-rf_write:
-       reg = 0;
-       rt2x00_set_field32(&reg, RFCSR_VALUE, value);
-       rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
-       rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
-       rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
-
-       rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
-       rt2x00_rf_write(rt2x00dev, word, value);
-}
-
-static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
-{
-       struct rt2x00_dev *rt2x00dev = eeprom->data;
-       u32 reg;
-
-       rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
-
-       eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
-       eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
-       eeprom->reg_data_clock =
-           !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
-       eeprom->reg_chip_select =
-           !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
-}
-
-static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
-{
-       struct rt2x00_dev *rt2x00dev = eeprom->data;
-       u32 reg = 0;
-
-       rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
-       rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
-       rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
-                          !!eeprom->reg_data_clock);
-       rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
-                          !!eeprom->reg_chip_select);
-
-       rt2x00pci_register_write(rt2x00dev, CSR21, reg);
-}
-
-#ifdef CONFIG_RT2X00_LIB_DEBUGFS
-#define CSR_OFFSET(__word)     ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
-
-static void rt2400pci_read_csr(const struct rt2x00_dev *rt2x00dev,
-                              const unsigned int word, u32 *data)
-{
-       rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
-}
-
-static void rt2400pci_write_csr(const struct rt2x00_dev *rt2x00dev,
-                               const unsigned int word, u32 data)
-{
-       rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
-}
-
-static const struct rt2x00debug rt2400pci_rt2x00debug = {
-       .owner  = THIS_MODULE,
-       .csr    = {
-               .read           = rt2400pci_read_csr,
-               .write          = rt2400pci_write_csr,
-               .word_size      = sizeof(u32),
-               .word_count     = CSR_REG_SIZE / sizeof(u32),
-       },
-       .eeprom = {
-               .read           = rt2x00_eeprom_read,
-               .write          = rt2x00_eeprom_write,
-               .word_size      = sizeof(u16),
-               .word_count     = EEPROM_SIZE / sizeof(u16),
-       },
-       .bbp    = {
-               .read           = rt2400pci_bbp_read,
-               .write          = rt2400pci_bbp_write,
-               .word_size      = sizeof(u8),
-               .word_count     = BBP_SIZE / sizeof(u8),
-       },
-       .rf     = {
-               .read           = rt2x00_rf_read,
-               .write          = rt2400pci_rf_write,
-               .word_size      = sizeof(u32),
-               .word_count     = RF_SIZE / sizeof(u32),
-       },
-};
-#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
-
-#ifdef CONFIG_RT2400PCI_RFKILL
-static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
-{
-       u32 reg;
-
-       rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
-       return rt2x00_get_field32(reg, GPIOCSR_BIT0);
-}
-#else
-#define rt2400pci_rfkill_poll  NULL
-#endif /* CONFIG_RT2400PCI_RFKILL */
-
-/*
- * Configuration handlers.
- */
-static void rt2400pci_config_mac_addr(struct rt2x00_dev *rt2x00dev,
-                                     __le32 *mac)
-{
-       rt2x00pci_register_multiwrite(rt2x00dev, CSR3, mac,
-                                     (2 * sizeof(__le32)));
-}
-
-static void rt2400pci_config_bssid(struct rt2x00_dev *rt2x00dev,
-                                  __le32 *bssid)
-{
-       rt2x00pci_register_multiwrite(rt2x00dev, CSR5, bssid,
-                                     (2 * sizeof(__le32)));
-}
-
-static void rt2400pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
-                                 const int tsf_sync)
-{
-       u32 reg;
-
-       rt2x00pci_register_write(rt2x00dev, CSR14, 0);
-
-       /*
-        * Enable beacon config
-        */
-       rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
-       rt2x00_set_field32(&reg, BCNCSR1_PRELOAD,
-                          PREAMBLE + get_duration(IEEE80211_HEADER, 20));
-       rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
-
-       /*
-        * Enable synchronisation.
-        */
-       rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
-       rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
-       rt2x00_set_field32(&reg, CSR14_TBCN, 1);
-       rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
-       rt2x00_set_field32(&reg, CSR14_TSF_SYNC, tsf_sync);
-       rt2x00pci_register_write(rt2x00dev, CSR14, reg);
-}
-
-static void rt2400pci_config_preamble(struct rt2x00_dev *rt2x00dev,
-                                     const int short_preamble,
-                                     const int ack_timeout,
-                                     const int ack_consume_time)
-{
-       int preamble_mask;
-       u32 reg;
-
-       /*
-        * When short preamble is enabled, we should set bit 0x08
-        */
-       preamble_mask = short_preamble << 3;
-
-       rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
-       rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, ack_timeout);
-       rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, ack_consume_time);
-       rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
-
-       rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
-       rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble_mask);
-       rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
-       rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
-       rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
-
-       rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
-       rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
-       rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
-       rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
-       rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
-
-       rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
-       rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
-       rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
-       rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
-       rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
-
-       rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
-       rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
-       rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
-       rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
-       rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
-}
-
-static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
-                                    const int basic_rate_mask)
-{
-       rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
-}
-
-static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
-                                    struct rf_channel *rf)
-{
-       /*
-        * Switch on tuning bits.
-        */
-       rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
-       rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
-
-       rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
-       rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
-       rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
-
-       /*
-        * RF2420 chipset don't need any additional actions.
-        */
-       if (rt2x00_rf(&rt2x00dev->chip, RF2420))
-               return;
-
-       /*
-        * For the RT2421 chipsets we need to write an invalid
-        * reference clock rate to activate auto_tune.
-        * After that we set the value back to the correct channel.
-        */
-       rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
-       rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
-       rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
-
-       msleep(1);
-
-       rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
-       rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
-       rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
-
-       msleep(1);
-
-       /*
-        * Switch off tuning bits.
-        */
-       rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
-       rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
-
-       rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
-       rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
-
-       /*
-        * Clear false CRC during channel switch.
-        */
-       rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
-}
-
-static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
-{
-       rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
-}
-
-static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
-                                    int antenna_tx, int antenna_rx)
-{
-       u8 r1;
-       u8 r4;
-
-       rt2400pci_bbp_read(rt2x00dev, 4, &r4);
-       rt2400pci_bbp_read(rt2x00dev, 1, &r1);
-
-       /*
-        * Configure the TX antenna.
-        */
-       switch (antenna_tx) {
-       case ANTENNA_SW_DIVERSITY:
-       case ANTENNA_HW_DIVERSITY:
-               rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
-               break;
-       case ANTENNA_A:
-               rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
-               break;
-       case ANTENNA_B:
-               rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
-               break;
-       }
-
-       /*
-        * Configure the RX antenna.
-        */
-       switch (antenna_rx) {
-       case ANTENNA_SW_DIVERSITY:
-       case ANTENNA_HW_DIVERSITY:
-               rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
-               break;
-       case ANTENNA_A:
-               rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
-               break;
-       case ANTENNA_B:
-               rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
-               break;
-       }
-
-       rt2400pci_bbp_write(rt2x00dev, 4, r4);
-       rt2400pci_bbp_write(rt2x00dev, 1, r1);
-}
-
-static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
-                                     struct rt2x00lib_conf *libconf)
-{
-       u32 reg;
-
-       rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
-       rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
-       rt2x00pci_register_write(rt2x00dev, CSR11, reg);
-
-       rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
-       rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
-       rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
-       rt2x00pci_register_write(rt2x00dev, CSR18, reg);
-
-       rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
-       rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
-       rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
-       rt2x00pci_register_write(rt2x00dev, CSR19, reg);
-
-       rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
-       rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
-       rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
-       rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
-
-       rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
-       rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
-                          libconf->conf->beacon_int * 16);
-       rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
-                          libconf->conf->beacon_int * 16);
-       rt2x00pci_register_write(rt2x00dev, CSR12, reg);
-}
-
-static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
-                            const unsigned int flags,
-                            struct rt2x00lib_conf *libconf)
-{
-       if (flags & CONFIG_UPDATE_PHYMODE)
-               rt2400pci_config_phymode(rt2x00dev, libconf->basic_rates);
-       if (flags & CONFIG_UPDATE_CHANNEL)
-               rt2400pci_config_channel(rt2x00dev, &libconf->rf);
-       if (flags & CONFIG_UPDATE_TXPOWER)
-               rt2400pci_config_txpower(rt2x00dev,
-                                        libconf->conf->power_level);
-       if (flags & CONFIG_UPDATE_ANTENNA)
-               rt2400pci_config_antenna(rt2x00dev,
-                                        libconf->conf->antenna_sel_tx,
-                                        libconf->conf->antenna_sel_rx);
-       if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
-               rt2400pci_config_duration(rt2x00dev, libconf);
-}
-
-static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
-                               struct ieee80211_tx_queue_params *params)
-{
-       u32 reg;
-
-       rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
-       rt2x00_set_field32(&reg, CSR11_CWMIN, params->cw_min);
-       rt2x00_set_field32(&reg, CSR11_CWMAX, params->cw_max);
-       rt2x00pci_register_write(rt2x00dev, CSR11, reg);
-}
-
-/*
- * LED functions.
- */
-static void rt2400pci_enable_led(struct rt2x00_dev *rt2x00dev)
-{
-       u32 reg;
-
-       rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
-
-       rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
-       rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
-
-       if (rt2x00dev->led_mode == LED_MODE_TXRX_ACTIVITY) {
-               rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
-               rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
-       } else if (rt2x00dev->led_mode == LED_MODE_ASUS) {
-               rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
-               rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
-       } else {
-               rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
-               rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
-       }
-
-       rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
-}
-
-static void rt2400pci_disable_led(struct rt2x00_dev *rt2x00dev)
-{
-       u32 reg;
-
-       rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
-       rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
-       rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
-       rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
-}
-
-/*
- * Link tuning
- */
-static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev)
-{
-       u32 reg;
-       u8 bbp;
-
-       /*
-        * Update FCS error count from register.
-        */
-       rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
-       rt2x00dev->link.rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
-
-       /*
-        * Update False CCA count from register.
-        */
-       rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
-       rt2x00dev->link.false_cca = bbp;
-}
-
-static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
-{
-       rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
-       rt2x00dev->link.vgc_level = 0x08;
-}
-
-static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
-{
-       u8 reg;
-
-       /*
-        * The link tuner should not run longer then 60 seconds,
-        * and should run once every 2 seconds.
-        */
-       if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
-               return;
-
-       /*
-        * Base r13 link tuning on the false cca count.
-        */
-       rt2400pci_bbp_read(rt2x00dev, 13, &reg);
-
-       if (rt2x00dev->link.false_cca > 512 && reg < 0x20) {
-               rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
-               rt2x00dev->link.vgc_level = reg;
-       } else if (rt2x00dev->link.false_cca < 100 && reg > 0x08) {
-               rt2400pci_bbp_write(rt2x00dev, 13, --reg);
-               rt2x00dev->link.vgc_level = reg;
-       }
-}
-
-/*
- * Initialization functions.
- */
-static void rt2400pci_init_rxring(struct rt2x00_dev *rt2x00dev)
-{
-       struct data_ring *ring = rt2x00dev->rx;
-       struct data_desc *rxd;
-       unsigned int i;
-       u32 word;
-
-       memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
-
-       for (i = 0; i < ring->stats.limit; i++) {
-               rxd = ring->entry[i].priv;
-
-               rt2x00_desc_read(rxd, 2, &word);
-               rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,
-                                  ring->data_size);
-               rt2x00_desc_write(rxd, 2, word);
-
-               rt2x00_desc_read(rxd, 1, &word);
-               rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS,
-                                  ring->entry[i].data_dma);
-               rt2x00_desc_write(rxd, 1, word);
-
-               rt2x00_desc_read(rxd, 0, &word);
-               rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
-               rt2x00_desc_write(rxd, 0, word);
-       }
-
-       rt2x00_ring_index_clear(rt2x00dev->rx);
-}
-
-static void rt2400pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
-{
-       struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
-       struct data_desc *txd;
-       unsigned int i;
-       u32 word;
-
-       memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
-
-       for (i = 0; i < ring->stats.limit; i++) {
-               txd = ring->entry[i].priv;
-
-               rt2x00_desc_read(txd, 1, &word);
-               rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS,
-                                  ring->entry[i].data_dma);
-               rt2x00_desc_write(txd, 1, word);
-
-               rt2x00_desc_read(txd, 2, &word);
-               rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH,
-                                  ring->data_size);
-               rt2x00_desc_write(txd, 2, word);
-
-               rt2x00_desc_read(txd, 0, &word);
-               rt2x00_set_field32(&word, TXD_W0_VALID, 0);
-               rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
-               rt2x00_desc_write(txd, 0, word);
-       }
-
-       rt2x00_ring_index_clear(ring);
-}
-
-static int rt2400pci_init_rings(struct rt2x00_dev *rt2x00dev)
-{
-       u32 reg;
-
-       /*
-        * Initialize rings.
-        */
-       rt2400pci_init_rxring(rt2x00dev);
-       rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
-       rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
-       rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
-       rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
-
-       /*
-        * Initialize registers.
-        */
-       rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
-       rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE,
-                          rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size);
-       rt2x00_set_field32(&reg, TXCSR2_NUM_TXD,
-                          rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
-       rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM,
-                          rt2x00dev->bcn[1].stats.limit);
-       rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO,
-                          rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
-       rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
-
-       rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
-       rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
-                          rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
-       rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
-
-       rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
-       rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
-                          rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
-       rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
-
-       rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
-       rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
-                          rt2x00dev->bcn[1].data_dma);
-       rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
-
-       rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
-       rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
-                          rt2x00dev->bcn[0].data_dma);
-       rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
-
-       rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
-       rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
-       rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->stats.limit);
-       rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
-
-       rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
-       rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
-                          rt2x00dev->rx->data_dma);
-       rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
-
-       return 0;
-}
-
-static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
-{
-       u32 reg;
-
-       rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
-       rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
-       rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
-       rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
-
-       rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
-       rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
-       rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
-       rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
-       rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
-
-       rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
-       rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
-                          (rt2x00dev->rx->data_size / 128));
-       rt2x00pci_register_write(rt2x00dev, CSR9, reg);
-
-       rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
-
-       rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
-       rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
-       rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
-       rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
-       rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
-       rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
-
-       rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
-       rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
-       rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
-       rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
-       rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
-       rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
-       rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
-       rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
-
-       rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
-
-       if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
-               return -EBUSY;
-
-       rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
-       rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
-
-       rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
-       rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
-       rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
-
-       rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
-       rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
-       rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
-       rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
-       rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
-       rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
-
-       rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
-       rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
-       rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
-       rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
-       rt2x00pci_register_write(rt2x00dev, CSR1, reg);
-
-       rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
-       rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
-       rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
-       rt2x00pci_register_write(rt2x00dev, CSR1, reg);
-
-       /*
-        * We must clear the FCS and FIFO error count.
-        * These registers are cleared on read,
-        * so we may pass a useless variable to store the value.
-        */
-       rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
-       rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
-
-       return 0;
-}
-
-static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
-{
-       unsigned int i;
-       u16 eeprom;
-       u8 reg_id;
-       u8 value;
-
-       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
-               rt2400pci_bbp_read(rt2x00dev, 0, &value);
-               if ((value != 0xff) && (value != 0x00))
-                       goto continue_csr_init;
-               NOTICE(rt2x00dev, "Waiting for BBP register.\n");
-               udelay(REGISTER_BUSY_DELAY);
-       }
-
-       ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
-       return -EACCES;
-
-continue_csr_init:
-       rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
-       rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
-       rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
-       rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
-       rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
-       rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
-       rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
-       rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
-       rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
-       rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
-       rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
-       rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
-       rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
-       rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
-
-       DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
-       for (i = 0; i < EEPROM_BBP_SIZE; i++) {
-               rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
-
-               if (eeprom != 0xffff && eeprom != 0x0000) {
-                       reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
-                       value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
-                       DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
-                             reg_id, value);
-                       rt2400pci_bbp_write(rt2x00dev, reg_id, value);
-               }
-       }
-       DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
-
-       return 0;
-}
-
-/*
- * Device state switch handlers.
- */
-static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
-                               enum dev_state state)
-{
-       u32 reg;
-
-       rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
-       rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
-                          state == STATE_RADIO_RX_OFF);
-       rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
-}
-
-static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
-                                enum dev_state state)
-{
-       int mask = (state == STATE_RADIO_IRQ_OFF);
-       u32 reg;
-
-       /*
-        * When interrupts are being enabled, the interrupt registers
-        * should clear the register to assure a clean state.
-        */
-       if (state == STATE_RADIO_IRQ_ON) {
-               rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
-               rt2x00pci_register_write(rt2x00dev, CSR7, reg);
-       }
-
-       /*
-        * Only toggle the interrupts bits we are going to use.
-        * Non-checked interrupt bits are disabled by default.
-        */
-       rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
-       rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
-       rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
-       rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
-       rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
-       rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
-       rt2x00pci_register_write(rt2x00dev, CSR8, reg);
-}
-
-static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
-{
-       /*
-        * Initialize all registers.
-        */
-       if (rt2400pci_init_rings(rt2x00dev) ||
-           rt2400pci_init_registers(rt2x00dev) ||
-           rt2400pci_init_bbp(rt2x00dev)) {
-               ERROR(rt2x00dev, "Register initialization failed.\n");
-               return -EIO;
-       }
-
-       /*
-        * Enable interrupts.
-        */
-       rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
-
-       /*
-        * Enable LED
-        */
-       rt2400pci_enable_led(rt2x00dev);
-
-       return 0;
-}
-
-static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
-{
-       u32 reg;
-
-       /*
-        * Disable LED
-        */
-       rt2400pci_disable_led(rt2x00dev);
-
-       rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
-
-       /*
-        * Disable synchronisation.
-        */
-       rt2x00pci_register_write(rt2x00dev, CSR14, 0);
-
-       /*
-        * Cancel RX and TX.
-        */
-       rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
-       rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
-       rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
-
-       /*
-        * Disable interrupts.
-        */
-       rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
-}
-
-static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
-                              enum dev_state state)
-{
-       u32 reg;
-       unsigned int i;
-       char put_to_sleep;
-       char bbp_state;
-       char rf_state;
-
-       put_to_sleep = (state != STATE_AWAKE);
-
-       rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
-       rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
-       rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
-       rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
-       rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
-       rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
-
-       /*
-        * Device is not guaranteed to be in the requested state yet.
-        * We must wait until the register indicates that the
-        * device has entered the correct state.
-        */
-       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
-               rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
-               bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
-               rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
-               if (bbp_state == state && rf_state == state)
-                       return 0;
-               msleep(10);
-       }
-
-       NOTICE(rt2x00dev, "Device failed to enter state %d, "
-              "current device state: bbp %d and rf %d.\n",
-              state, bbp_state, rf_state);
-
-       return -EBUSY;
-}
-
-static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
-                                     enum dev_state state)
-{
-       int retval = 0;
-
-       switch (state) {
-       case STATE_RADIO_ON:
-               retval = rt2400pci_enable_radio(rt2x00dev);
-               break;
-       case STATE_RADIO_OFF:
-               rt2400pci_disable_radio(rt2x00dev);
-               break;
-       case STATE_RADIO_RX_ON:
-       case STATE_RADIO_RX_OFF:
-               rt2400pci_toggle_rx(rt2x00dev, state);
-               break;
-       case STATE_DEEP_SLEEP:
-       case STATE_SLEEP:
-       case STATE_STANDBY:
-       case STATE_AWAKE:
-               retval = rt2400pci_set_state(rt2x00dev, state);
-               break;
-       default:
-               retval = -ENOTSUPP;
-               break;
-       }
-
-       return retval;
-}
-
-/*
- * TX descriptor initialization
- */
-static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
-                                   struct data_desc *txd,
-                                   struct txdata_entry_desc *desc,
-                                   struct ieee80211_hdr *ieee80211hdr,
-                                   unsigned int length,
-                                   struct ieee80211_tx_control *control)
-{
-       u32 word;
-       u32 signal = 0;
-       u32 service = 0;
-       u32 length_high = 0;
-       u32 length_low = 0;
-
-       /*
-        * The PLCP values should be treated as if they
-        * were BBP values.
-        */
-       rt2x00_set_field32(&signal, BBPCSR_VALUE, desc->signal);
-       rt2x00_set_field32(&signal, BBPCSR_REGNUM, 5);
-       rt2x00_set_field32(&signal, BBPCSR_BUSY, 1);
-
-       rt2x00_set_field32(&service, BBPCSR_VALUE, desc->service);
-       rt2x00_set_field32(&service, BBPCSR_REGNUM, 6);
-       rt2x00_set_field32(&service, BBPCSR_BUSY, 1);
-
-       rt2x00_set_field32(&length_high, BBPCSR_VALUE, desc->length_high);
-       rt2x00_set_field32(&length_high, BBPCSR_REGNUM, 7);
-       rt2x00_set_field32(&length_high, BBPCSR_BUSY, 1);
-
-       rt2x00_set_field32(&length_low, BBPCSR_VALUE, desc->length_low);
-       rt2x00_set_field32(&length_low, BBPCSR_REGNUM, 8);
-       rt2x00_set_field32(&length_low, BBPCSR_BUSY, 1);
-
-       /*
-        * Start writing the descriptor words.
-        */
-       rt2x00_desc_read(txd, 2, &word);
-       rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, length);
-       rt2x00_desc_write(txd, 2, word);
-
-       rt2x00_desc_read(txd, 3, &word);
-       rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, signal);
-       rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, service);
-       rt2x00_desc_write(txd, 3, word);
-
-       rt2x00_desc_read(txd, 4, &word);
-       rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, length_low);
-       rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, length_high);
-       rt2x00_desc_write(txd, 4, word);
-
-       rt2x00_desc_read(txd, 0, &word);
-       rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
-       rt2x00_set_field32(&word, TXD_W0_VALID, 1);
-       rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
-                          test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
-       rt2x00_set_field32(&word, TXD_W0_ACK,
-                          !(control->flags & IEEE80211_TXCTL_NO_ACK));
-       rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
-                          test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
-       rt2x00_set_field32(&word, TXD_W0_RTS,
-                          test_bit(ENTRY_TXD_RTS_FRAME, &desc->flags));
-       rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
-       rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
-                          !!(control->flags &
-                             IEEE80211_TXCTL_LONG_RETRY_LIMIT));
-       rt2x00_desc_write(txd, 0, word);
-}
-
-/*
- * TX data initialization
- */
-static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
-                                   unsigned int queue)
-{
-       u32 reg;
-
-       if (queue == IEEE80211_TX_QUEUE_BEACON) {
-               rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
-               if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
-                       rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
-                       rt2x00pci_register_write(rt2x00dev, CSR14, reg);
-               }
-               return;
-       }
-
-       rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
-       if (queue == IEEE80211_TX_QUEUE_DATA0)
-               rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
-       else if (queue == IEEE80211_TX_QUEUE_DATA1)
-               rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
-       else if (queue == IEEE80211_TX_QUEUE_AFTER_BEACON)
-               rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
-       rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
-}
-
-/*
- * RX control handlers
- */
-static void rt2400pci_fill_rxdone(struct data_entry *entry,
-                                 struct rxdata_entry_desc *desc)
-{
-       struct data_desc *rxd = entry->priv;
-       u32 word0;
-       u32 word2;
-
-       rt2x00_desc_read(rxd, 0, &word0);
-       rt2x00_desc_read(rxd, 2, &word2);
-
-       desc->flags = 0;
-       if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
-               desc->flags |= RX_FLAG_FAILED_FCS_CRC;
-       if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
-               desc->flags |= RX_FLAG_FAILED_PLCP_CRC;
-
-       /*
-        * Obtain the status about this packet.
-        */
-       desc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
-       desc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
-           entry->ring->rt2x00dev->rssi_offset;
-       desc->ofdm = 0;
-       desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
-}
-
-/*
- * Interrupt functions.
- */
-static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue)
-{
-       struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
-       struct data_entry *entry;
-       struct data_desc *txd;
-       u32 word;
-       int tx_status;
-       int retry;
-
-       while (!rt2x00_ring_empty(ring)) {
-               entry = rt2x00_get_data_entry_done(ring);
-               txd = entry->priv;
-               rt2x00_desc_read(txd, 0, &word);
-
-               if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
-                   !rt2x00_get_field32(word, TXD_W0_VALID))
-                       break;
-
-               /*
-                * Obtain the status about this packet.
-                */
-               tx_status = rt2x00_get_field32(word, TXD_W0_RESULT);
-               retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
-
-               rt2x00lib_txdone(entry, tx_status, retry);
-
-               /*
-                * Make this entry available for reuse.
-                */
-               entry->flags = 0;
-               rt2x00_set_field32(&word, TXD_W0_VALID, 0);
-               rt2x00_desc_write(txd, 0, word);
-               rt2x00_ring_index_done_inc(ring);
-       }
-
-       /*
-        * If the data ring was full before the txdone handler
-        * we must make sure the packet queue in the mac80211 stack
-        * is reenabled when the txdone handler has finished.
-        */
-       entry = ring->entry;
-       if (!rt2x00_ring_full(ring))
-               ieee80211_wake_queue(rt2x00dev->hw,
-                                    entry->tx_status.control.queue);
-}
-
-static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
-{
-       struct rt2x00_dev *rt2x00dev = dev_instance;
-       u32 reg;
-
-       /*
-        * Get the interrupt sources & saved to local variable.
-        * Write register value back to clear pending interrupts.
-        */
-       rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
-       rt2x00pci_register_write(rt2x00dev, CSR7, reg);
-
-       if (!reg)
-               return IRQ_NONE;
-
-       if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
-               return IRQ_HANDLED;
-
-       /*
-        * Handle interrupts, walk through all bits
-        * and run the tasks, the bits are checked in order of
-        * priority.
-        */
-
-       /*
-        * 1 - Beacon timer expired interrupt.
-        */
-       if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
-               rt2x00lib_beacondone(rt2x00dev);
-
-       /*
-        * 2 - Rx ring done interrupt.
-        */
-       if (rt2x00_get_field32(reg, CSR7_RXDONE))
-               rt2x00pci_rxdone(rt2x00dev);
-
-       /*
-        * 3 - Atim ring transmit done interrupt.
-        */
-       if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
-               rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
-
-       /*
-        * 4 - Priority ring transmit done interrupt.
-        */
-       if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
-               rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
-
-       /*
-        * 5 - Tx ring transmit done interrupt.
-        */
-       if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
-               rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
-
-       return IRQ_HANDLED;
-}
-
-/*
- * Device probe functions.
- */
-static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
-{
-       struct eeprom_93cx6 eeprom;
-       u32 reg;
-       u16 word;
-       u8 *mac;
-
-       rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
-
-       eeprom.data = rt2x00dev;
-       eeprom.register_read = rt2400pci_eepromregister_read;
-       eeprom.register_write = rt2400pci_eepromregister_write;
-       eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
-           PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
-       eeprom.reg_data_in = 0;
-       eeprom.reg_data_out = 0;
-       eeprom.reg_data_clock = 0;
-       eeprom.reg_chip_select = 0;
-
-       eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
-                              EEPROM_SIZE / sizeof(u16));
-
-       /*
-        * Start validation of the data that has been read.
-        */
-       mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
-       if (!is_valid_ether_addr(mac)) {
-               DECLARE_MAC_BUF(macbuf);
-
-               random_ether_addr(mac);
-               EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
-       }
-
-       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
-       if (word == 0xffff) {
-               ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
-               return -EINVAL;
-       }
-
-       return 0;
-}
-
-static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
-{
-       u32 reg;
-       u16 value;
-       u16 eeprom;
-
-       /*
-        * Read EEPROM word for configuration.
-        */
-       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
-
-       /*
-        * Identify RF chipset.
-        */
-       value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
-       rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
-       rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
-
-       if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
-           !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
-               ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
-               return -ENODEV;
-       }
-
-       /*
-        * Identify default antenna configuration.
-        */
-       rt2x00dev->hw->conf.antenna_sel_tx =
-           rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
-       rt2x00dev->hw->conf.antenna_sel_rx =
-           rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
-
-       /*
-        * Store led mode, for correct led behaviour.
-        */
-       rt2x00dev->led_mode =
-           rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
-
-       /*
-        * Detect if this device has an hardware controlled radio.
-        */
-#ifdef CONFIG_RT2400PCI_RFKILL
-       if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
-               __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
-#endif /* CONFIG_RT2400PCI_RFKILL */
-
-       /*
-        * Check if the BBP tuning should be enabled.
-        */
-       if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
-               __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
-
-       return 0;
-}
-
-/*
- * RF value list for RF2420 & RF2421
- * Supports: 2.4 GHz
- */
-static const struct rf_channel rf_vals_bg[] = {
-       { 1,  0x00022058, 0x000c1fda, 0x00000101, 0 },
-       { 2,  0x00022058, 0x000c1fee, 0x00000101, 0 },
-       { 3,  0x00022058, 0x000c2002, 0x00000101, 0 },
-       { 4,  0x00022058, 0x000c2016, 0x00000101, 0 },
-       { 5,  0x00022058, 0x000c202a, 0x00000101, 0 },
-       { 6,  0x00022058, 0x000c203e, 0x00000101, 0 },
-       { 7,  0x00022058, 0x000c2052, 0x00000101, 0 },
-       { 8,  0x00022058, 0x000c2066, 0x00000101, 0 },
-       { 9,  0x00022058, 0x000c207a, 0x00000101, 0 },
-       { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
-       { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
-       { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
-       { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
-       { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
-};
-
-static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
-{
-       struct hw_mode_spec *spec = &rt2x00dev->spec;
-       u8 *txpower;
-       unsigned int i;
-
-       /*
-        * Initialize all hw fields.
-        */
-       rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
-       rt2x00dev->hw->extra_tx_headroom = 0;
-       rt2x00dev->hw->max_signal = MAX_SIGNAL;
-       rt2x00dev->hw->max_rssi = MAX_RX_SSI;
-       rt2x00dev->hw->queues = 2;
-
-       SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
-       SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
-                               rt2x00_eeprom_addr(rt2x00dev,
-                                                  EEPROM_MAC_ADDR_0));
-
-       /*
-        * Convert tx_power array in eeprom.
-        */
-       txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
-       for (i = 0; i < 14; i++)
-               txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
-
-       /*
-        * Initialize hw_mode information.
-        */
-       spec->num_modes = 1;
-       spec->num_rates = 4;
-       spec->tx_power_a = NULL;
-       spec->tx_power_bg = txpower;
-       spec->tx_power_default = DEFAULT_TXPOWER;
-
-       spec->num_channels = ARRAY_SIZE(rf_vals_bg);
-       spec->channels = rf_vals_bg;
-}
-
-static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
-{
-       int retval;
-
-       /*
-        * Allocate eeprom data.
-        */
-       retval = rt2400pci_validate_eeprom(rt2x00dev);
-       if (retval)
-               return retval;
-
-       retval = rt2400pci_init_eeprom(rt2x00dev);
-       if (retval)
-               return retval;
-
-       /*
-        * Initialize hw specifications.
-        */
-       rt2400pci_probe_hw_mode(rt2x00dev);
-
-       /*
-        * This device requires the beacon ring
-        */
-       __set_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags);
-
-       /*
-        * Set the rssi offset.
-        */
-       rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
-
-       return 0;
-}
-
-/*
- * IEEE80211 stack callback functions.
- */
-static void rt2400pci_configure_filter(struct ieee80211_hw *hw,
-                                      unsigned int changed_flags,
-                                      unsigned int *total_flags,
-                                      int mc_count,
-                                      struct dev_addr_list *mc_list)
-{
-       struct rt2x00_dev *rt2x00dev = hw->priv;
-       struct interface *intf = &rt2x00dev->interface;
-       u32 reg;
-
-       /*
-        * Mask off any flags we are going to ignore from
-        * the total_flags field.
-        */
-       *total_flags &=
-           FIF_ALLMULTI |
-           FIF_FCSFAIL |
-           FIF_PLCPFAIL |
-           FIF_CONTROL |
-           FIF_OTHER_BSS |
-           FIF_PROMISC_IN_BSS;
-
-       /*
-        * Apply some rules to the filters:
-        * - Some filters imply different filters to be set.
-        * - Some things we can't filter out at all.
-        * - Some filters are set based on interface type.
-        */
-       *total_flags |= FIF_ALLMULTI;
-       if (*total_flags & FIF_OTHER_BSS ||
-           *total_flags & FIF_PROMISC_IN_BSS)
-               *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
-       if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
-               *total_flags |= FIF_PROMISC_IN_BSS;
-
-       /*
-        * Check if there is any work left for us.
-        */
-       if (intf->filter == *total_flags)
-               return;
-       intf->filter = *total_flags;
-
-       /*
-        * Start configuration steps.
-        * Note that the version error will always be dropped
-        * since there is no filter for it at this time.
-        */
-       rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
-       rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
-                          !(*total_flags & FIF_FCSFAIL));
-       rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
-                          !(*total_flags & FIF_PLCPFAIL));
-       rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
-                          !(*total_flags & FIF_CONTROL));
-       rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
-                          !(*total_flags & FIF_PROMISC_IN_BSS));
-       rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
-                          !(*total_flags & FIF_PROMISC_IN_BSS));
-       rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
-       rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
-}
-
-static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
-                                    u32 short_retry, u32 long_retry)
-{
-       struct rt2x00_dev *rt2x00dev = hw->priv;
-       u32 reg;
-
-       rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
-       rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
-       rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
-       rt2x00pci_register_write(rt2x00dev, CSR11, reg);
-
-       return 0;
-}
-
-static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
-                            int queue,
-                            const struct ieee80211_tx_queue_params *params)
-{
-       struct rt2x00_dev *rt2x00dev = hw->priv;
-
-       /*
-        * We don't support variating cw_min and cw_max variables
-        * per queue. So by default we only configure the TX queue,
-        * and ignore all other configurations.
-        */
-       if (queue != IEEE80211_TX_QUEUE_DATA0)
-               return -EINVAL;
-
-       if (rt2x00mac_conf_tx(hw, queue, params))
-               return -EINVAL;
-
-       /*
-        * Write configuration to register.
-        */
-       rt2400pci_config_cw(rt2x00dev, &rt2x00dev->tx->tx_params);
-
-       return 0;
-}
-
-static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
-{
-       struct rt2x00_dev *rt2x00dev = hw->priv;
-       u64 tsf;
-       u32 reg;
-
-       rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
-       tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
-       rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
-       tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
-
-       return tsf;
-}
-
-static void rt2400pci_reset_tsf(struct ieee80211_hw *hw)
-{
-       struct rt2x00_dev *rt2x00dev = hw->priv;
-
-       rt2x00pci_register_write(rt2x00dev, CSR16, 0);
-       rt2x00pci_register_write(rt2x00dev, CSR17, 0);
-}
-
-static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
-{
-       struct rt2x00_dev *rt2x00dev = hw->priv;
-       u32 reg;
-
-       rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
-       return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
-}
-
-static const struct ieee80211_ops rt2400pci_mac80211_ops = {
-       .tx                     = rt2x00mac_tx,
-       .start                  = rt2x00mac_start,
-       .stop                   = rt2x00mac_stop,
-       .add_interface          = rt2x00mac_add_interface,
-       .remove_interface       = rt2x00mac_remove_interface,
-       .config                 = rt2x00mac_config,
-       .config_interface       = rt2x00mac_config_interface,
-       .configure_filter       = rt2400pci_configure_filter,
-       .get_stats              = rt2x00mac_get_stats,
-       .set_retry_limit        = rt2400pci_set_retry_limit,
-       .erp_ie_changed         = rt2x00mac_erp_ie_changed,
-       .conf_tx                = rt2400pci_conf_tx,
-       .get_tx_stats           = rt2x00mac_get_tx_stats,
-       .get_tsf                = rt2400pci_get_tsf,
-       .reset_tsf              = rt2400pci_reset_tsf,
-       .beacon_update          = rt2x00pci_beacon_update,
-       .tx_last_beacon         = rt2400pci_tx_last_beacon,
-};
-
-static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
-       .irq_handler            = rt2400pci_interrupt,
-       .probe_hw               = rt2400pci_probe_hw,
-       .initialize             = rt2x00pci_initialize,
-       .uninitialize           = rt2x00pci_uninitialize,
-       .set_device_state       = rt2400pci_set_device_state,
-       .rfkill_poll            = rt2400pci_rfkill_poll,
-       .link_stats             = rt2400pci_link_stats,
-       .reset_tuner            = rt2400pci_reset_tuner,
-       .link_tuner             = rt2400pci_link_tuner,
-       .write_tx_desc          = rt2400pci_write_tx_desc,
-       .write_tx_data          = rt2x00pci_write_tx_data,
-       .kick_tx_queue          = rt2400pci_kick_tx_queue,
-       .fill_rxdone            = rt2400pci_fill_rxdone,
-       .config_mac_addr        = rt2400pci_config_mac_addr,
-       .config_bssid           = rt2400pci_config_bssid,
-       .config_type            = rt2400pci_config_type,
-       .config_preamble        = rt2400pci_config_preamble,
-       .config                 = rt2400pci_config,
-};
-
-static const struct rt2x00_ops rt2400pci_ops = {
-       .name           = DRV_NAME,
-       .rxd_size       = RXD_DESC_SIZE,
-       .txd_size       = TXD_DESC_SIZE,
-       .eeprom_size    = EEPROM_SIZE,
-       .rf_size        = RF_SIZE,
-       .lib            = &rt2400pci_rt2x00_ops,
-       .hw             = &rt2400pci_mac80211_ops,
-#ifdef CONFIG_RT2X00_LIB_DEBUGFS
-       .debugfs        = &rt2400pci_rt2x00debug,
-#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
-};
-
-/*
- * RT2400pci module information.
- */
-static struct pci_device_id rt2400pci_device_table[] = {
-       { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
-       { 0, }
-};
-
-MODULE_AUTHOR(DRV_PROJECT);
-MODULE_VERSION(DRV_VERSION);
-MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
-MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
-MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
-MODULE_LICENSE("GPL");
-
-static struct pci_driver rt2400pci_driver = {
-       .name           = DRV_NAME,
-       .id_table       = rt2400pci_device_table,
-       .probe          = rt2x00pci_probe,
-       .remove         = __devexit_p(rt2x00pci_remove),
-       .suspend        = rt2x00pci_suspend,
-       .resume         = rt2x00pci_resume,
-};
-
-static int __init rt2400pci_init(void)
-{
-       return pci_register_driver(&rt2400pci_driver);
-}
-
-static void __exit rt2400pci_exit(void)
-{
-       pci_unregister_driver(&rt2400pci_driver);
-}
-
-module_init(rt2400pci_init);
-module_exit(rt2400pci_exit);
diff --git a/package/rt2x00/src/rt2400pci.h b/package/rt2x00/src/rt2400pci.h
deleted file mode 100644 (file)
index ae22501..0000000
+++ /dev/null
@@ -1,943 +0,0 @@
-/*
-       Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
-       <http://rt2x00.serialmonkey.com>
-
-       This program is free software; you can redistribute it and/or modify
-       it under the terms of the GNU General Public License as published by
-       the Free Software Foundation; either version 2 of the License, or
-       (at your option) any later version.
-
-       This program is distributed in the hope that it will be useful,
-       but WITHOUT ANY WARRANTY; without even the implied warranty of
-       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-       GNU General Public License for more details.
-
-       You should have received a copy of the GNU General Public License
-       along with this program; if not, write to the
-       Free Software Foundation, Inc.,
-       59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-/*
-       Module: rt2400pci
-       Abstract: Data structures and registers for the rt2400pci module.
-       Supported chipsets: RT2460.
- */
-
-#ifndef RT2400PCI_H
-#define RT2400PCI_H
-
-/*
- * RF chip defines.
- */
-#define RF2420                         0x0000
-#define RF2421                         0x0001
-
-/*
- * Signal information.
- * Defaul offset is required for RSSI <-> dBm conversion.
- */
-#define MAX_SIGNAL                     100
-#define MAX_RX_SSI                     -1
-#define DEFAULT_RSSI_OFFSET            100
-
-/*
- * Register layout information.
- */
-#define CSR_REG_BASE                   0x0000
-#define CSR_REG_SIZE                   0x014c
-#define EEPROM_BASE                    0x0000
-#define EEPROM_SIZE                    0x0100
-#define BBP_SIZE                       0x0020
-#define RF_SIZE                                0x0010
-
-/*
- * Control/Status Registers(CSR).
- * Some values are set in TU, whereas 1 TU == 1024 us.
- */
-
-/*
- * CSR0: ASIC revision number.
- */
-#define CSR0                           0x0000
-
-/*
- * CSR1: System control register.
- * SOFT_RESET: Software reset, 1: reset, 0: normal.
- * BBP_RESET: Hardware reset, 1: reset, 0, release.
- * HOST_READY: Host ready after initialization.
- */
-#define CSR1                           0x0004
-#define CSR1_SOFT_RESET                        FIELD32(0x00000001)
-#define CSR1_BBP_RESET                 FIELD32(0x00000002)
-#define CSR1_HOST_READY                        FIELD32(0x00000004)
-
-/*
- * CSR2: System admin status register (invalid).
- */
-#define CSR2                           0x0008
-
-/*
- * CSR3: STA MAC address register 0.
- */
-#define CSR3                           0x000c
-#define CSR3_BYTE0                     FIELD32(0x000000ff)
-#define CSR3_BYTE1                     FIELD32(0x0000ff00)
-#define CSR3_BYTE2                     FIELD32(0x00ff0000)
-#define CSR3_BYTE3                     FIELD32(0xff000000)
-
-/*
- * CSR4: STA MAC address register 1.
- */
-#define CSR4                           0x0010
-#define CSR4_BYTE4                     FIELD32(0x000000ff)
-#define CSR4_BYTE5                     FIELD32(0x0000ff00)
-
-/*
- * CSR5: BSSID register 0.
- */
-#define CSR5                           0x0014
-#define CSR5_BYTE0                     FIELD32(0x000000ff)
-#define CSR5_BYTE1                     FIELD32(0x0000ff00)
-#define CSR5_BYTE2                     FIELD32(0x00ff0000)
-#define CSR5_BYTE3                     FIELD32(0xff000000)
-
-/*
- * CSR6: BSSID register 1.
- */
-#define CSR6                           0x0018
-#define CSR6_BYTE4                     FIELD32(0x000000ff)
-#define CSR6_BYTE5                     FIELD32(0x0000ff00)
-
-/*
- * CSR7: Interrupt source register.
- * Write 1 to clear interrupt.
- * TBCN_EXPIRE: Beacon timer expired interrupt.
- * TWAKE_EXPIRE: Wakeup timer expired interrupt.
- * TATIMW_EXPIRE: Timer of atim window expired interrupt.
- * TXDONE_TXRING: Tx ring transmit done interrupt.
- * TXDONE_ATIMRING: Atim ring transmit done interrupt.
- * TXDONE_PRIORING: Priority ring transmit done interrupt.
- * RXDONE: Receive done interrupt.
- */
-#define CSR7                           0x001c
-#define CSR7_TBCN_EXPIRE               FIELD32(0x00000001)
-#define CSR7_TWAKE_EXPIRE              FIELD32(0x00000002)
-#define CSR7_TATIMW_EXPIRE             FIELD32(0x00000004)
-#define CSR7_TXDONE_TXRING             FIELD32(0x00000008)
-#define CSR7_TXDONE_ATIMRING           FIELD32(0x00000010)
-#define CSR7_TXDONE_PRIORING           FIELD32(0x00000020)
-#define CSR7_RXDONE                    FIELD32(0x00000040)
-
-/*
- * CSR8: Interrupt mask register.
- * Write 1 to mask interrupt.
- * TBCN_EXPIRE: Beacon timer expired interrupt.
- * TWAKE_EXPIRE: Wakeup timer expired interrupt.
- * TATIMW_EXPIRE: Timer of atim window expired interrupt.
- * TXDONE_TXRING: Tx ring transmit done interrupt.
- * TXDONE_ATIMRING: Atim ring transmit done interrupt.
- * TXDONE_PRIORING: Priority ring transmit done interrupt.
- * RXDONE: Receive done interrupt.
- */
-#define CSR8                           0x0020
-#define CSR8_TBCN_EXPIRE               FIELD32(0x00000001)
-#define CSR8_TWAKE_EXPIRE              FIELD32(0x00000002)
-#define CSR8_TATIMW_EXPIRE             FIELD32(0x00000004)
-#define CSR8_TXDONE_TXRING             FIELD32(0x00000008)
-#define CSR8_TXDONE_ATIMRING           FIELD32(0x00000010)
-#define CSR8_TXDONE_PRIORING           FIELD32(0x00000020)
-#define CSR8_RXDONE                    FIELD32(0x00000040)
-
-/*
- * CSR9: Maximum frame length register.
- * MAX_FRAME_UNIT: Maximum frame length in 128b unit, default: 12.
- */
-#define CSR9                           0x0024
-#define CSR9_MAX_FRAME_UNIT            FIELD32(0x00000f80)
-
-/*
- * CSR11: Back-off control register.
- * CWMIN: CWmin. Default cwmin is 31 (2^5 - 1).
- * CWMAX: CWmax. Default cwmax is 1023 (2^10 - 1).
- * SLOT_TIME: Slot time, default is 20us for 802.11b.
- * LONG_RETRY: Long retry count.
- * SHORT_RETRY: Short retry count.
- */
-#define CSR11                          0x002c
-#define CSR11_CWMIN                    FIELD32(0x0000000f)
-#define CSR11_CWMAX                    FIELD32(0x000000f0)
-#define CSR11_SLOT_TIME                        FIELD32(0x00001f00)
-#define CSR11_LONG_RETRY               FIELD32(0x00ff0000)
-#define CSR11_SHORT_RETRY              FIELD32(0xff000000)
-
-/*
- * CSR12: Synchronization configuration register 0.
- * All units in 1/16 TU.
- * BEACON_INTERVAL: Beacon interval, default is 100 TU.
- * CFPMAX_DURATION: Cfp maximum duration, default is 100 TU.
- */
-#define CSR12                          0x0030
-#define CSR12_BEACON_INTERVAL          FIELD32(0x0000ffff)
-#define CSR12_CFP_MAX_DURATION         FIELD32(0xffff0000)
-
-/*
- * CSR13: Synchronization configuration register 1.
- * All units in 1/16 TU.
- * ATIMW_DURATION: Atim window duration.
- * CFP_PERIOD: Cfp period, default is 0 TU.
- */
-#define CSR13                          0x0034
-#define CSR13_ATIMW_DURATION           FIELD32(0x0000ffff)
-#define CSR13_CFP_PERIOD               FIELD32(0x00ff0000)
-
-/*
- * CSR14: Synchronization control register.
- * TSF_COUNT: Enable tsf auto counting.
- * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
- * TBCN: Enable tbcn with reload value.
- * TCFP: Enable tcfp & cfp / cp switching.
- * TATIMW: Enable tatimw & atim window switching.
- * BEACON_GEN: Enable beacon generator.
- * CFP_COUNT_PRELOAD: Cfp count preload value.
- * TBCM_PRELOAD: Tbcn preload value in units of 64us.
- */
-#define CSR14                          0x0038
-#define CSR14_TSF_COUNT                        FIELD32(0x00000001)
-#define CSR14_TSF_SYNC                 FIELD32(0x00000006)
-#define CSR14_TBCN                     FIELD32(0x00000008)
-#define CSR14_TCFP                     FIELD32(0x00000010)
-#define CSR14_TATIMW                   FIELD32(0x00000020)
-#define CSR14_BEACON_GEN               FIELD32(0x00000040)
-#define CSR14_CFP_COUNT_PRELOAD                FIELD32(0x0000ff00)
-#define CSR14_TBCM_PRELOAD             FIELD32(0xffff0000)
-
-/*
- * CSR15: Synchronization status register.
- * CFP: ASIC is in contention-free period.
- * ATIMW: ASIC is in ATIM window.
- * BEACON_SENT: Beacon is send.
- */
-#define CSR15                          0x003c
-#define CSR15_CFP                      FIELD32(0x00000001)
-#define CSR15_ATIMW                    FIELD32(0x00000002)
-#define CSR15_BEACON_SENT              FIELD32(0x00000004)
-
-/*
- * CSR16: TSF timer register 0.
- */
-#define CSR16                          0x0040
-#define CSR16_LOW_TSFTIMER             FIELD32(0xffffffff)
-
-/*
- * CSR17: TSF timer register 1.
- */
-#define CSR17                          0x0044
-#define CSR17_HIGH_TSFTIMER            FIELD32(0xffffffff)
-
-/*
- * CSR18: IFS timer register 0.
- * SIFS: Sifs, default is 10 us.
- * PIFS: Pifs, default is 30 us.
- */
-#define CSR18                          0x0048
-#define CSR18_SIFS                     FIELD32(0x0000ffff)
-#define CSR18_PIFS                     FIELD32(0xffff0000)
-
-/*
- * CSR19: IFS timer register 1.
- * DIFS: Difs, default is 50 us.
- * EIFS: Eifs, default is 364 us.
- */
-#define CSR19                          0x004c
-#define CSR19_DIFS                     FIELD32(0x0000ffff)
-#define CSR19_EIFS                     FIELD32(0xffff0000)
-
-/*
- * CSR20: Wakeup timer register.
- * DELAY_AFTER_TBCN: Delay after tbcn expired in units of 1/16 TU.
- * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
- * AUTOWAKE: Enable auto wakeup / sleep mechanism.
- */
-#define CSR20                          0x0050
-#define CSR20_DELAY_AFTER_TBCN         FIELD32(0x0000ffff)
-#define CSR20_TBCN_BEFORE_WAKEUP       FIELD32(0x00ff0000)
-#define CSR20_AUTOWAKE                 FIELD32(0x01000000)
-
-/*
- * CSR21: EEPROM control register.
- * RELOAD: Write 1 to reload eeprom content.
- * TYPE_93C46: 1: 93c46, 0:93c66.
- */
-#define CSR21                          0x0054
-#define CSR21_RELOAD                   FIELD32(0x00000001)
-#define CSR21_EEPROM_DATA_CLOCK                FIELD32(0x00000002)
-#define CSR21_EEPROM_CHIP_SELECT       FIELD32(0x00000004)
-#define CSR21_EEPROM_DATA_IN           FIELD32(0x00000008)
-#define CSR21_EEPROM_DATA_OUT          FIELD32(0x00000010)
-#define CSR21_TYPE_93C46               FIELD32(0x00000020)
-
-/*
- * CSR22: CFP control register.
- * CFP_DURATION_REMAIN: Cfp duration remain, in units of TU.
- * RELOAD_CFP_DURATION: Write 1 to reload cfp duration remain.
- */
-#define CSR22                          0x0058
-#define CSR22_CFP_DURATION_REMAIN      FIELD32(0x0000ffff)
-#define CSR22_RELOAD_CFP_DURATION      FIELD32(0x00010000)
-
-/*
- * Transmit related CSRs.
- * Some values are set in TU, whereas 1 TU == 1024 us.
- */
-
-/*
- * TXCSR0: TX Control Register.
- * KICK_TX: Kick tx ring.
- * KICK_ATIM: Kick atim ring.
- * KICK_PRIO: Kick priority ring.
- * ABORT: Abort all transmit related ring operation.
- */
-#define TXCSR0                         0x0060
-#define TXCSR0_KICK_TX                 FIELD32(0x00000001)
-#define TXCSR0_KICK_ATIM               FIELD32(0x00000002)
-#define TXCSR0_KICK_PRIO               FIELD32(0x00000004)
-#define TXCSR0_ABORT                   FIELD32(0x00000008)
-
-/*
- * TXCSR1: TX Configuration Register.
- * ACK_TIMEOUT: Ack timeout, default = sifs + 2*slottime + acktime @ 1mbps.
- * ACK_CONSUME_TIME: Ack consume time, default = sifs + acktime @ 1mbps.
- * TSF_OFFSET: Insert tsf offset.
- * AUTORESPONDER: Enable auto responder which include ack & cts.
- */
-#define TXCSR1                         0x0064
-#define TXCSR1_ACK_TIMEOUT             FIELD32(0x000001ff)
-#define TXCSR1_ACK_CONSUME_TIME                FIELD32(0x0003fe00)
-#define TXCSR1_TSF_OFFSET              FIELD32(0x00fc0000)
-#define TXCSR1_AUTORESPONDER           FIELD32(0x01000000)
-
-/*
- * TXCSR2: Tx descriptor configuration register.
- * TXD_SIZE: Tx descriptor size, default is 48.
- * NUM_TXD: Number of tx entries in ring.
- * NUM_ATIM: Number of atim entries in ring.
- * NUM_PRIO: Number of priority entries in ring.
- */
-#define TXCSR2                         0x0068
-#define TXCSR2_TXD_SIZE                        FIELD32(0x000000ff)
-#define TXCSR2_NUM_TXD                 FIELD32(0x0000ff00)
-#define TXCSR2_NUM_ATIM                        FIELD32(0x00ff0000)
-#define TXCSR2_NUM_PRIO                        FIELD32(0xff000000)
-
-/*
- * TXCSR3: TX Ring Base address register.
- */
-#define TXCSR3                         0x006c
-#define TXCSR3_TX_RING_REGISTER                FIELD32(0xffffffff)
-
-/*
- * TXCSR4: TX Atim Ring Base address register.
- */
-#define TXCSR4                         0x0070
-#define TXCSR4_ATIM_RING_REGISTER      FIELD32(0xffffffff)
-
-/*
- * TXCSR5: TX Prio Ring Base address register.
- */
-#define TXCSR5                         0x0074
-#define TXCSR5_PRIO_RING_REGISTER      FIELD32(0xffffffff)
-
-/*
- * TXCSR6: Beacon Base address register.
- */
-#define TXCSR6                         0x0078
-#define TXCSR6_BEACON_RING_REGISTER    FIELD32(0xffffffff)
-
-/*
- * TXCSR7: Auto responder control register.
- * AR_POWERMANAGEMENT: Auto responder power management bit.
- */
-#define TXCSR7                         0x007c
-#define TXCSR7_AR_POWERMANAGEMENT      FIELD32(0x00000001)
-
-/*
- * Receive related CSRs.
- * Some values are set in TU, whereas 1 TU == 1024 us.
- */
-
-/*
- * RXCSR0: RX Control Register.
- * DISABLE_RX: Disable rx engine.
- * DROP_CRC: Drop crc error.
- * DROP_PHYSICAL: Drop physical error.
- * DROP_CONTROL: Drop control frame.
- * DROP_NOT_TO_ME: Drop not to me unicast frame.
- * DROP_TODS: Drop frame tods bit is true.
- * DROP_VERSION_ERROR: Drop version error frame.
- * PASS_CRC: Pass all packets with crc attached.
- */
-#define RXCSR0                         0x0080
-#define RXCSR0_DISABLE_RX              FIELD32(0x00000001)
-#define RXCSR0_DROP_CRC                        FIELD32(0x00000002)
-#define RXCSR0_DROP_PHYSICAL           FIELD32(0x00000004)
-#define RXCSR0_DROP_CONTROL            FIELD32(0x00000008)
-#define RXCSR0_DROP_NOT_TO_ME          FIELD32(0x00000010)
-#define RXCSR0_DROP_TODS               FIELD32(0x00000020)
-#define RXCSR0_DROP_VERSION_ERROR      FIELD32(0x00000040)
-#define RXCSR0_PASS_CRC                        FIELD32(0x00000080)
-
-/*
- * RXCSR1: RX descriptor configuration register.
- * RXD_SIZE: Rx descriptor size, default is 32b.
- * NUM_RXD: Number of rx entries in ring.
- */
-#define RXCSR1                         0x0084
-#define RXCSR1_RXD_SIZE                        FIELD32(0x000000ff)
-#define RXCSR1_NUM_RXD                 FIELD32(0x0000ff00)
-
-/*
- * RXCSR2: RX Ring base address register.
- */
-#define RXCSR2                         0x0088
-#define RXCSR2_RX_RING_REGISTER                FIELD32(0xffffffff)
-
-/*
- * RXCSR3: BBP ID register for Rx operation.
- * BBP_ID#: BBP register # id.
- * BBP_ID#_VALID: BBP register # id is valid or not.
- */
-#define RXCSR3                         0x0090
-#define RXCSR3_BBP_ID0                 FIELD32(0x0000007f)
-#define RXCSR3_BBP_ID0_VALID           FIELD32(0x00000080)
-#define RXCSR3_BBP_ID1                 FIELD32(0x00007f00)
-#define RXCSR3_BBP_ID1_VALID           FIELD32(0x00008000)
-#define RXCSR3_BBP_ID2                 FIELD32(0x007f0000)
-#define RXCSR3_BBP_ID2_VALID           FIELD32(0x00800000)
-#define RXCSR3_BBP_ID3                 FIELD32(0x7f000000)
-#define RXCSR3_BBP_ID3_VALID           FIELD32(0x80000000)
-
-/*
- * RXCSR4: BBP ID register for Rx operation.
- * BBP_ID#: BBP register # id.
- * BBP_ID#_VALID: BBP register # id is valid or not.
- */
-#define RXCSR4                         0x0094
-#define RXCSR4_BBP_ID4                 FIELD32(0x0000007f)
-#define RXCSR4_BBP_ID4_VALID           FIELD32(0x00000080)
-#define RXCSR4_BBP_ID5                 FIELD32(0x00007f00)
-#define RXCSR4_BBP_ID5_VALID           FIELD32(0x00008000)
-
-/*
- * ARCSR0: Auto Responder PLCP config register 0.
- * ARCSR0_AR_BBP_DATA#: Auto responder BBP register # data.
- * ARCSR0_AR_BBP_ID#: Auto responder BBP register # Id.
- */
-#define ARCSR0                         0x0098
-#define ARCSR0_AR_BBP_DATA0            FIELD32(0x000000ff)
-#define ARCSR0_AR_BBP_ID0              FIELD32(0x0000ff00)
-#define ARCSR0_AR_BBP_DATA1            FIELD32(0x00ff0000)
-#define ARCSR0_AR_BBP_ID1              FIELD32(0xff000000)
-
-/*
- * ARCSR1: Auto Responder PLCP config register 1.
- * ARCSR0_AR_BBP_DATA#: Auto responder BBP register # data.
- * ARCSR0_AR_BBP_ID#: Auto responder BBP register # Id.
- */
-#define ARCSR1                         0x009c
-#define ARCSR1_AR_BBP_DATA2            FIELD32(0x000000ff)
-#define ARCSR1_AR_BBP_ID2              FIELD32(0x0000ff00)
-#define ARCSR1_AR_BBP_DATA3            FIELD32(0x00ff0000)
-#define ARCSR1_AR_BBP_ID3              FIELD32(0xff000000)
-
-/*
- * Miscellaneous Registers.
- * Some values are set in TU, whereas 1 TU == 1024 us.
- */
-
-/*
- * PCICSR: PCI control register.
- * BIG_ENDIAN: 1: big endian, 0: little endian.
- * RX_TRESHOLD: Rx threshold in dw to start pci access
- * 0: 16dw (default), 1: 8dw, 2: 4dw, 3: 32dw.
- * TX_TRESHOLD: Tx threshold in dw to start pci access
- * 0: 0dw (default), 1: 1dw, 2: 4dw, 3: forward.
- * BURST_LENTH: Pci burst length 0: 4dw (default, 1: 8dw, 2: 16dw, 3:32dw.
- * ENABLE_CLK: Enable clk_run, pci clock can't going down to non-operational.
- */
-#define PCICSR                         0x008c
-#define PCICSR_BIG_ENDIAN              FIELD32(0x00000001)
-#define PCICSR_RX_TRESHOLD             FIELD32(0x00000006)
-#define PCICSR_TX_TRESHOLD             FIELD32(0x00000018)
-#define PCICSR_BURST_LENTH             FIELD32(0x00000060)
-#define PCICSR_ENABLE_CLK              FIELD32(0x00000080)
-
-/*
- * CNT0: FCS error count.
- * FCS_ERROR: FCS error count, cleared when read.
- */
-#define CNT0                           0x00a0
-#define CNT0_FCS_ERROR                 FIELD32(0x0000ffff)
-
-/*
- * Statistic Register.
- * CNT1: PLCP error count.
- * CNT2: Long error count.
- * CNT3: CCA false alarm count.
- * CNT4: Rx FIFO overflow count.
- * CNT5: Tx FIFO underrun count.
- */
-#define TIMECSR2                       0x00a8
-#define CNT1                           0x00ac
-#define CNT2                           0x00b0
-#define TIMECSR3                       0x00b4
-#define CNT3                           0x00b8
-#define CNT4                           0x00bc
-#define CNT5                           0x00c0
-
-/*
- * Baseband Control Register.
- */
-
-/*
- * PWRCSR0: Power mode configuration register.
- */
-#define PWRCSR0                                0x00c4
-
-/*
- * Power state transition time registers.
- */
-#define PSCSR0                         0x00c8
-#define PSCSR1                         0x00cc
-#define PSCSR2                         0x00d0
-#define PSCSR3                         0x00d4
-
-/*
- * PWRCSR1: Manual power control / status register.
- * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
- * SET_STATE: Set state. Write 1 to trigger, self cleared.
- * BBP_DESIRE_STATE: BBP desired state.
- * RF_DESIRE_STATE: RF desired state.
- * BBP_CURR_STATE: BBP current state.
- * RF_CURR_STATE: RF current state.
- * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared.
- */
-#define PWRCSR1                                0x00d8
-#define PWRCSR1_SET_STATE              FIELD32(0x00000001)
-#define PWRCSR1_BBP_DESIRE_STATE       FIELD32(0x00000006)
-#define PWRCSR1_RF_DESIRE_STATE                FIELD32(0x00000018)
-#define PWRCSR1_BBP_CURR_STATE         FIELD32(0x00000060)
-#define PWRCSR1_RF_CURR_STATE          FIELD32(0x00000180)
-#define PWRCSR1_PUT_TO_SLEEP           FIELD32(0x00000200)
-
-/*
- * TIMECSR: Timer control register.
- * US_COUNT: 1 us timer count in units of clock cycles.
- * US_64_COUNT: 64 us timer count in units of 1 us timer.
- * BEACON_EXPECT: Beacon expect window.
- */
-#define TIMECSR                                0x00dc
-#define TIMECSR_US_COUNT               FIELD32(0x000000ff)
-#define TIMECSR_US_64_COUNT            FIELD32(0x0000ff00)
-#define TIMECSR_BEACON_EXPECT          FIELD32(0x00070000)
-
-/*
- * MACCSR0: MAC configuration register 0.
- */
-#define MACCSR0                                0x00e0
-
-/*
- * MACCSR1: MAC configuration register 1.
- * KICK_RX: Kick one-shot rx in one-shot rx mode.
- * ONESHOT_RXMODE: Enable one-shot rx mode for debugging.
- * BBPRX_RESET_MODE: Ralink bbp rx reset mode.
- * AUTO_TXBBP: Auto tx logic access bbp control register.
- * AUTO_RXBBP: Auto rx logic access bbp control register.
- * LOOPBACK: Loopback mode. 0: normal, 1: internal, 2: external, 3:rsvd.
- * INTERSIL_IF: Intersil if calibration pin.
- */
-#define MACCSR1                                0x00e4
-#define MACCSR1_KICK_RX                        FIELD32(0x00000001)
-#define MACCSR1_ONESHOT_RXMODE         FIELD32(0x00000002)
-#define MACCSR1_BBPRX_RESET_MODE       FIELD32(0x00000004)
-#define MACCSR1_AUTO_TXBBP             FIELD32(0x00000008)
-#define MACCSR1_AUTO_RXBBP             FIELD32(0x00000010)
-#define MACCSR1_LOOPBACK               FIELD32(0x00000060)
-#define MACCSR1_INTERSIL_IF            FIELD32(0x00000080)
-
-/*
- * RALINKCSR: Ralink Rx auto-reset BBCR.
- * AR_BBP_DATA#: Auto reset BBP register # data.
- * AR_BBP_ID#: Auto reset BBP register # id.
- */
-#define RALINKCSR                      0x00e8
-#define RALINKCSR_AR_BBP_DATA0         FIELD32(0x000000ff)
-#define RALINKCSR_AR_BBP_ID0           FIELD32(0x0000ff00)
-#define RALINKCSR_AR_BBP_DATA1         FIELD32(0x00ff0000)
-#define RALINKCSR_AR_BBP_ID1           FIELD32(0xff000000)
-
-/*
- * BCNCSR: Beacon interval control register.
- * CHANGE: Write one to change beacon interval.
- * DELTATIME: The delta time value.
- * NUM_BEACON: Number of beacon according to mode.
- * MODE: Please refer to asic specs.
- * PLUS: Plus or minus delta time value.
- */
-#define BCNCSR                         0x00ec
-#define BCNCSR_CHANGE                  FIELD32(0x00000001)
-#define BCNCSR_DELTATIME               FIELD32(0x0000001e)
-#define BCNCSR_NUM_BEACON              FIELD32(0x00001fe0)
-#define BCNCSR_MODE                    FIELD32(0x00006000)
-#define BCNCSR_PLUS                    FIELD32(0x00008000)
-
-/*
- * BBP / RF / IF Control Register.
- */
-
-/*
- * BBPCSR: BBP serial control register.
- * VALUE: Register value to program into BBP.
- * REGNUM: Selected BBP register.
- * BUSY: 1: asic is busy execute BBP programming.
- * WRITE_CONTROL: 1: write BBP, 0: read BBP.
- */
-#define BBPCSR                         0x00f0
-#define BBPCSR_VALUE                   FIELD32(0x000000ff)
-#define BBPCSR_REGNUM                  FIELD32(0x00007f00)
-#define BBPCSR_BUSY                    FIELD32(0x00008000)
-#define BBPCSR_WRITE_CONTROL           FIELD32(0x00010000)
-
-/*
- * RFCSR: RF serial control register.
- * VALUE: Register value + id to program into rf/if.
- * NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22).
- * IF_SELECT: Chip to program: 0: rf, 1: if.
- * PLL_LD: Rf pll_ld status.
- * BUSY: 1: asic is busy execute rf programming.
- */
-#define RFCSR                          0x00f4
-#define RFCSR_VALUE                    FIELD32(0x00ffffff)
-#define RFCSR_NUMBER_OF_BITS           FIELD32(0x1f000000)
-#define RFCSR_IF_SELECT                        FIELD32(0x20000000)
-#define RFCSR_PLL_LD                   FIELD32(0x40000000)
-#define RFCSR_BUSY                     FIELD32(0x80000000)
-
-/*
- * LEDCSR: LED control register.
- * ON_PERIOD: On period, default 70ms.
- * OFF_PERIOD: Off period, default 30ms.
- * LINK: 0: linkoff, 1: linkup.
- * ACTIVITY: 0: idle, 1: active.
- */
-#define LEDCSR                         0x00f8
-#define LEDCSR_ON_PERIOD               FIELD32(0x000000ff)
-#define LEDCSR_OFF_PERIOD              FIELD32(0x0000ff00)
-#define LEDCSR_LINK                    FIELD32(0x00010000)
-#define LEDCSR_ACTIVITY                        FIELD32(0x00020000)
-
-/*
- * ASIC pointer information.
- * RXPTR: Current RX ring address.
- * TXPTR: Current Tx ring address.
- * PRIPTR: Current Priority ring address.
- * ATIMPTR: Current ATIM ring address.
- */
-#define RXPTR                          0x0100
-#define TXPTR                          0x0104
-#define PRIPTR                         0x0108
-#define ATIMPTR                                0x010c
-
-/*
- * GPIO and others.
- */
-
-/*
- * GPIOCSR: GPIO control register.
- */
-#define GPIOCSR                                0x0120
-#define GPIOCSR_BIT0                   FIELD32(0x00000001)
-#define GPIOCSR_BIT1                   FIELD32(0x00000002)
-#define GPIOCSR_BIT2                   FIELD32(0x00000004)
-#define GPIOCSR_BIT3                   FIELD32(0x00000008)
-#define GPIOCSR_BIT4                   FIELD32(0x00000010)
-#define GPIOCSR_BIT5                   FIELD32(0x00000020)
-#define GPIOCSR_BIT6                   FIELD32(0x00000040)
-#define GPIOCSR_BIT7                   FIELD32(0x00000080)
-
-/*
- * BBPPCSR: BBP Pin control register.
- */
-#define BBPPCSR                                0x0124
-
-/*
- * BCNCSR1: Tx BEACON offset time control register.
- * PRELOAD: Beacon timer offset in units of usec.
- */
-#define BCNCSR1                                0x0130
-#define BCNCSR1_PRELOAD                        FIELD32(0x0000ffff)
-
-/*
- * MACCSR2: TX_PE to RX_PE turn-around time control register
- * DELAY: RX_PE low width, in units of pci clock cycle.
- */
-#define MACCSR2                                0x0134
-#define MACCSR2_DELAY                  FIELD32(0x000000ff)
-
-/*
- * ARCSR2: 1 Mbps ACK/CTS PLCP.
- */
-#define ARCSR2                         0x013c
-#define ARCSR2_SIGNAL                  FIELD32(0x000000ff)
-#define ARCSR2_SERVICE                 FIELD32(0x0000ff00)
-#define ARCSR2_LENGTH_LOW              FIELD32(0x00ff0000)
-#define ARCSR2_LENGTH                  FIELD32(0xffff0000)
-
-/*
- * ARCSR3: 2 Mbps ACK/CTS PLCP.
- */
-#define ARCSR3                         0x0140
-#define ARCSR3_SIGNAL                  FIELD32(0x000000ff)
-#define ARCSR3_SERVICE                 FIELD32(0x0000ff00)
-#define ARCSR3_LENGTH                  FIELD32(0xffff0000)
-
-/*
- * ARCSR4: 5.5 Mbps ACK/CTS PLCP.
- */
-#define ARCSR4                         0x0144
-#define ARCSR4_SIGNAL                  FIELD32(0x000000ff)
-#define ARCSR4_SERVICE                 FIELD32(0x0000ff00)
-#define ARCSR4_LENGTH                  FIELD32(0xffff0000)
-
-/*
- * ARCSR5: 11 Mbps ACK/CTS PLCP.
- */
-#define ARCSR5                         0x0148
-#define ARCSR5_SIGNAL                  FIELD32(0x000000ff)
-#define ARCSR5_SERVICE                 FIELD32(0x0000ff00)
-#define ARCSR5_LENGTH                  FIELD32(0xffff0000)
-
-/*
- * BBP registers.
- * The wordsize of the BBP is 8 bits.
- */
-
-/*
- * R1: TX antenna control
- */
-#define BBP_R1_TX_ANTENNA              FIELD8(0x03)
-
-/*
- * R4: RX antenna control
- */
-#define BBP_R4_RX_ANTENNA              FIELD8(0x06)
-
-/*
- * RF registers
- */
-
-/*
- * RF 1
- */
-#define RF1_TUNER                      FIELD32(0x00020000)
-
-/*
- * RF 3
- */
-#define RF3_TUNER                      FIELD32(0x00000100)
-#define RF3_TXPOWER                    FIELD32(0x00003e00)
-
-/*
- * EEPROM content.
- * The wordsize of the EEPROM is 16 bits.
- */
-
-/*
- * HW MAC address.
- */
-#define EEPROM_MAC_ADDR_0              0x0002
-#define EEPROM_MAC_ADDR_BYTE0          FIELD16(0x00ff)
-#define EEPROM_MAC_ADDR_BYTE1          FIELD16(0xff00)
-#define EEPROM_MAC_ADDR1               0x0003
-#define EEPROM_MAC_ADDR_BYTE2          FIELD16(0x00ff)
-#define EEPROM_MAC_ADDR_BYTE3          FIELD16(0xff00)
-#define EEPROM_MAC_ADDR_2              0x0004
-#define EEPROM_MAC_ADDR_BYTE4          FIELD16(0x00ff)
-#define EEPROM_MAC_ADDR_BYTE5          FIELD16(0xff00)
-
-/*
- * EEPROM antenna.
- * ANTENNA_NUM: Number of antenna's.
- * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
- * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
- * RF_TYPE: Rf_type of this adapter.
- * LED_MODE: 0: default, 1: TX/RX activity,2: Single (ignore link), 3: rsvd.
- * RX_AGCVGC: 0: disable, 1:enable BBP R13 tuning.
- * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
- */
-#define EEPROM_ANTENNA                 0x0b
-#define EEPROM_ANTENNA_NUM             FIELD16(0x0003)
-#define EEPROM_ANTENNA_TX_DEFAULT      FIELD16(0x000c)
-#define EEPROM_ANTENNA_RX_DEFAULT      FIELD16(0x0030)
-#define EEPROM_ANTENNA_RF_TYPE         FIELD16(0x0040)
-#define EEPROM_ANTENNA_LED_MODE                FIELD16(0x0180)
-#define EEPROM_ANTENNA_RX_AGCVGC_TUNING        FIELD16(0x0200)
-#define EEPROM_ANTENNA_HARDWARE_RADIO  FIELD16(0x0400)
-
-/*
- * EEPROM BBP.
- */
-#define EEPROM_BBP_START               0x0c
-#define EEPROM_BBP_SIZE                        7
-#define EEPROM_BBP_VALUE               FIELD16(0x00ff)
-#define EEPROM_BBP_REG_ID              FIELD16(0xff00)
-
-/*
- * EEPROM TXPOWER
- */
-#define EEPROM_TXPOWER_START           0x13
-#define EEPROM_TXPOWER_SIZE            7
-#define EEPROM_TXPOWER_1               FIELD16(0x00ff)
-#define EEPROM_TXPOWER_2               FIELD16(0xff00)
-
-/*
- * DMA descriptor defines.
- */
-#define TXD_DESC_SIZE                  ( 8 * sizeof(struct data_desc) )
-#define RXD_DESC_SIZE                  ( 8 * sizeof(struct data_desc) )
-
-/*
- * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
- */
-
-/*
- * Word0
- */
-#define TXD_W0_OWNER_NIC               FIELD32(0x00000001)
-#define TXD_W0_VALID                   FIELD32(0x00000002)
-#define TXD_W0_RESULT                  FIELD32(0x0000001c)
-#define TXD_W0_RETRY_COUNT             FIELD32(0x000000e0)
-#define TXD_W0_MORE_FRAG               FIELD32(0x00000100)
-#define TXD_W0_ACK                     FIELD32(0x00000200)
-#define TXD_W0_TIMESTAMP               FIELD32(0x00000400)
-#define TXD_W0_RTS                     FIELD32(0x00000800)
-#define TXD_W0_IFS                     FIELD32(0x00006000)
-#define TXD_W0_RETRY_MODE              FIELD32(0x00008000)
-#define TXD_W0_AGC                     FIELD32(0x00ff0000)
-#define TXD_W0_R2                      FIELD32(0xff000000)
-
-/*
- * Word1
- */
-#define TXD_W1_BUFFER_ADDRESS          FIELD32(0xffffffff)
-
-/*
- * Word2
- */
-#define TXD_W2_BUFFER_LENGTH           FIELD32(0x0000ffff)
-#define TXD_W2_DATABYTE_COUNT          FIELD32(0xffff0000)
-
-/*
- * Word3 & 4: PLCP information
- */
-#define TXD_W3_PLCP_SIGNAL             FIELD32(0x0000ffff)
-#define TXD_W3_PLCP_SERVICE            FIELD32(0xffff0000)
-#define TXD_W4_PLCP_LENGTH_LOW         FIELD32(0x0000ffff)
-#define TXD_W4_PLCP_LENGTH_HIGH                FIELD32(0xffff0000)
-
-/*
- * Word5
- */
-#define TXD_W5_BBCR4                   FIELD32(0x0000ffff)
-#define TXD_W5_AGC_REG                 FIELD32(0x007f0000)
-#define TXD_W5_AGC_REG_VALID           FIELD32(0x00800000)
-#define TXD_W5_XXX_REG                 FIELD32(0x7f000000)
-#define TXD_W5_XXX_REG_VALID           FIELD32(0x80000000)
-
-/*
- * Word6
- */
-#define TXD_W6_SK_BUFF                 FIELD32(0xffffffff)
-
-/*
- * Word7
- */
-#define TXD_W7_RESERVED                        FIELD32(0xffffffff)
-
-/*
- * RX descriptor format for RX Ring.
- */
-
-/*
- * Word0
- */
-#define RXD_W0_OWNER_NIC               FIELD32(0x00000001)
-#define RXD_W0_UNICAST_TO_ME           FIELD32(0x00000002)
-#define RXD_W0_MULTICAST               FIELD32(0x00000004)
-#define RXD_W0_BROADCAST               FIELD32(0x00000008)
-#define RXD_W0_MY_BSS                  FIELD32(0x00000010)
-#define RXD_W0_CRC_ERROR               FIELD32(0x00000020)
-#define RXD_W0_PHYSICAL_ERROR          FIELD32(0x00000080)
-#define RXD_W0_DATABYTE_COUNT          FIELD32(0xffff0000)
-
-/*
- * Word1
- */
-#define RXD_W1_BUFFER_ADDRESS          FIELD32(0xffffffff)
-
-/*
- * Word2
- */
-#define RXD_W2_BUFFER_LENGTH           FIELD32(0x0000ffff)
-#define RXD_W2_SIGNAL                  FIELD32(0x00ff0000)
-#define RXD_W2_RSSI                    FIELD32(0xff000000)
-
-/*
- * Word3
- */
-#define RXD_W3_BBR2                    FIELD32(0x000000ff)
-#define RXD_W3_BBR3                    FIELD32(0x0000ff00)
-#define RXD_W3_BBR4                    FIELD32(0x00ff0000)
-#define RXD_W3_BBR5                    FIELD32(0xff000000)
-
-/*
- * Word4
- */
-#define RXD_W4_RX_END_TIME             FIELD32(0xffffffff)
-
-/*
- * Word5 & 6 & 7: Reserved
- */
-#define RXD_W5_RESERVED                        FIELD32(0xffffffff)
-#define RXD_W6_RESERVED                        FIELD32(0xffffffff)
-#define RXD_W7_RESERVED                        FIELD32(0xffffffff)
-
-/*
- * Macro's for converting txpower from EEPROM to dscape value
- * and from dscape value to register value.
- * NOTE: Logics in rt2400pci for txpower are reversed
- * compared to the other rt2x00 drivers. A higher txpower
- * value means that the txpower must be lowered. This is
- * important when converting the value coming from the
- * dscape stack to the rt2400 acceptable value.
- */
-#define MIN_TXPOWER    31
-#define MAX_TXPOWER    62
-#define DEFAULT_TXPOWER        39
-
-#define TXPOWER_FROM_DEV(__txpower)                                    \
-({                                                                     \
-       ((__txpower) > MAX_TXPOWER) ? DEFAULT_TXPOWER - MIN_TXPOWER :   \
-       ((__txpower) < MIN_TXPOWER) ? DEFAULT_TXPOWER - MIN_TXPOWER :   \
-       (((__txpower) - MAX_TXPOWER) + MIN_TXPOWER);                    \
-})
-
-#define TXPOWER_TO_DEV(__txpower)                      \
-({                                                     \
-       (__txpower) += MIN_TXPOWER;                     \
-       ((__txpower) <= MIN_TXPOWER) ? MAX_TXPOWER :    \
-       (((__txpower) >= MAX_TXPOWER) ? MIN_TXPOWER :   \
-       (MAX_TXPOWER - ((__txpower) - MIN_TXPOWER)));   \
-})
-
-#endif /* RT2400PCI_H */
diff --git a/package/rt2x00/src/rt2500pci.c b/package/rt2x00/src/rt2500pci.c
deleted file mode 100644 (file)
index 702321c..0000000
+++ /dev/null
@@ -1,1971 +0,0 @@
-/*
-       Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
-       <http://rt2x00.serialmonkey.com>
-
-       This program is free software; you can redistribute it and/or modify
-       it under the terms of the GNU General Public License as published by
-       the Free Software Foundation; either version 2 of the License, or
-       (at your option) any later version.
-
-       This program is distributed in the hope that it will be useful,
-       but WITHOUT ANY WARRANTY; without even the implied warranty of
-       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-       GNU General Public License for more details.
-
-       You should have received a copy of the GNU General Public License
-       along with this program; if not, write to the
-       Free Software Foundation, Inc.,
-       59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-/*
-       Module: rt2500pci
-       Abstract: rt2500pci device specific routines.
-       Supported chipsets: RT2560.
- */
-
-/*
- * Set enviroment defines for rt2x00.h
- */
-#define DRV_NAME "rt2500pci"
-
-#include <linux/delay.h>
-#include <linux/etherdevice.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/pci.h>
-#include <linux/eeprom_93cx6.h>
-
-#include "rt2x00.h"
-#include "rt2x00pci.h"
-#include "rt2500pci.h"
-
-/*
- * Register access.
- * All access to the CSR registers will go through the methods
- * rt2x00pci_register_read and rt2x00pci_register_write.
- * BBP and RF register require indirect register access,
- * and use the CSR registers BBPCSR and RFCSR to achieve this.
- * These indirect registers work with busy bits,
- * and we will try maximal REGISTER_BUSY_COUNT times to access
- * the register while taking a REGISTER_BUSY_DELAY us delay
- * between each attampt. When the busy bit is still set at that time,
- * the access attempt is considered to have failed,
- * and we will print an error.
- */
-static u32 rt2500pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
-{
-       u32 reg;
-       unsigned int i;
-
-       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
-               rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
-               if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
-                       break;
-               udelay(REGISTER_BUSY_DELAY);
-       }
-
-       return reg;
-}
-
-static void rt2500pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
-                               const unsigned int word, const u8 value)
-{
-       u32 reg;
-
-       /*
-        * Wait until the BBP becomes ready.
-        */
-       reg = rt2500pci_bbp_check(rt2x00dev);
-       if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
-               ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
-               return;
-       }
-
-       /*
-        * Write the data into the BBP.
-        */
-       reg = 0;
-       rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
-       rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
-       rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
-       rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
-
-       rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
-}
-
-static void rt2500pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
-                              const unsigned int word, u8 *value)
-{
-       u32 reg;
-
-       /*
-        * Wait until the BBP becomes ready.
-        */
-       reg = rt2500pci_bbp_check(rt2x00dev);
-       if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
-               ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
-               return;
-       }
-
-       /*
-        * Write the request into the BBP.
-        */
-       reg = 0;
-       rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
-       rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
-       rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
-
-       rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
-
-       /*
-        * Wait until the BBP becomes ready.
-        */
-       reg = rt2500pci_bbp_check(rt2x00dev);
-       if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
-               ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
-               *value = 0xff;
-               return;
-       }
-
-       *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
-}
-
-static void rt2500pci_rf_write(const struct rt2x00_dev *rt2x00dev,
-                              const unsigned int word, const u32 value)
-{
-       u32 reg;
-       unsigned int i;
-
-       if (!word)
-               return;
-
-       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
-               rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
-               if (!rt2x00_get_field32(reg, RFCSR_BUSY))
-                       goto rf_write;
-               udelay(REGISTER_BUSY_DELAY);
-       }
-
-       ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
-       return;
-
-rf_write:
-       reg = 0;
-       rt2x00_set_field32(&reg, RFCSR_VALUE, value);
-       rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
-       rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
-       rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
-
-       rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
-       rt2x00_rf_write(rt2x00dev, word, value);
-}
-
-static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
-{
-       struct rt2x00_dev *rt2x00dev = eeprom->data;
-       u32 reg;
-
-       rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
-
-       eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
-       eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
-       eeprom->reg_data_clock =
-           !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
-       eeprom->reg_chip_select =
-           !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
-}
-
-static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
-{
-       struct rt2x00_dev *rt2x00dev = eeprom->data;
-       u32 reg = 0;
-
-       rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
-       rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
-       rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
-                          !!eeprom->reg_data_clock);
-       rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
-                          !!eeprom->reg_chip_select);
-
-       rt2x00pci_register_write(rt2x00dev, CSR21, reg);
-}
-
-#ifdef CONFIG_RT2X00_LIB_DEBUGFS
-#define CSR_OFFSET(__word)     ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
-
-static void rt2500pci_read_csr(const struct rt2x00_dev *rt2x00dev,
-                              const unsigned int word, u32 *data)
-{
-       rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
-}
-
-static void rt2500pci_write_csr(const struct rt2x00_dev *rt2x00dev,
-                               const unsigned int word, u32 data)
-{
-       rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
-}
-
-static const struct rt2x00debug rt2500pci_rt2x00debug = {
-       .owner  = THIS_MODULE,
-       .csr    = {
-               .read           = rt2500pci_read_csr,
-               .write          = rt2500pci_write_csr,
-               .word_size      = sizeof(u32),
-               .word_count     = CSR_REG_SIZE / sizeof(u32),
-       },
-       .eeprom = {
-               .read           = rt2x00_eeprom_read,
-               .write          = rt2x00_eeprom_write,
-               .word_size      = sizeof(u16),
-               .word_count     = EEPROM_SIZE / sizeof(u16),
-       },
-       .bbp    = {
-               .read           = rt2500pci_bbp_read,
-               .write          = rt2500pci_bbp_write,
-               .word_size      = sizeof(u8),
-               .word_count     = BBP_SIZE / sizeof(u8),
-       },
-       .rf     = {
-               .read           = rt2x00_rf_read,
-               .write          = rt2500pci_rf_write,
-               .word_size      = sizeof(u32),
-               .word_count     = RF_SIZE / sizeof(u32),
-       },
-};
-#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
-
-#ifdef CONFIG_RT2500PCI_RFKILL
-static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
-{
-       u32 reg;
-
-       rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
-       return rt2x00_get_field32(reg, GPIOCSR_BIT0);
-}
-#else
-#define rt2500pci_rfkill_poll  NULL
-#endif /* CONFIG_RT2500PCI_RFKILL */
-
-/*
- * Configuration handlers.
- */
-static void rt2500pci_config_mac_addr(struct rt2x00_dev *rt2x00dev,
-                                     __le32 *mac)
-{
-       rt2x00pci_register_multiwrite(rt2x00dev, CSR3, mac,
-                                     (2 * sizeof(__le32)));
-}
-
-static void rt2500pci_config_bssid(struct rt2x00_dev *rt2x00dev,
-                                  __le32 *bssid)
-{
-       rt2x00pci_register_multiwrite(rt2x00dev, CSR5, bssid,
-                                     (2 * sizeof(__le32)));
-}
-
-static void rt2500pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
-                                 const int tsf_sync)
-{
-       u32 reg;
-
-       rt2x00pci_register_write(rt2x00dev, CSR14, 0);
-
-       /*
-        * Enable beacon config
-        */
-       rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
-       rt2x00_set_field32(&reg, BCNCSR1_PRELOAD,
-                          PREAMBLE + get_duration(IEEE80211_HEADER, 20));
-       rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN,
-                          rt2x00lib_get_ring(rt2x00dev,
-                                             IEEE80211_TX_QUEUE_BEACON)
-                          ->tx_params.cw_min);
-       rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
-
-       /*
-        * Enable synchronisation.
-        */
-       rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
-       rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
-       rt2x00_set_field32(&reg, CSR14_TBCN, 1);
-       rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
-       rt2x00_set_field32(&reg, CSR14_TSF_SYNC, tsf_sync);
-       rt2x00pci_register_write(rt2x00dev, CSR14, reg);
-}
-
-static void rt2500pci_config_preamble(struct rt2x00_dev *rt2x00dev,
-                                     const int short_preamble,
-                                     const int ack_timeout,
-                                     const int ack_consume_time)
-{
-       int preamble_mask;
-       u32 reg;
-
-       /*
-        * When short preamble is enabled, we should set bit 0x08
-        */
-       preamble_mask = short_preamble << 3;
-
-       rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
-       rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, ack_timeout);
-       rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, ack_consume_time);
-       rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
-
-       rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
-       rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble_mask);
-       rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
-       rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
-       rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
-
-       rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
-       rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
-       rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
-       rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
-       rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
-
-       rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
-       rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
-       rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
-       rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
-       rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
-
-       rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
-       rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
-       rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
-       rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
-       rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
-}
-
-static void rt2500pci_config_phymode(struct rt2x00_dev *rt2x00dev,
-                                    const int basic_rate_mask)
-{
-       rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
-}
-
-static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
-                                    struct rf_channel *rf, const int txpower)
-{
-       u8 r70;
-
-       /*
-        * Set TXpower.
-        */
-       rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
-
-       /*
-        * Switch on tuning bits.
-        * For RT2523 devices we do not need to update the R1 register.
-        */
-       if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
-               rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
-       rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
-
-       /*
-        * For RT2525 we should first set the channel to half band higher.
-        */
-       if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
-               static const u32 vals[] = {
-                       0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
-                       0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
-                       0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
-                       0x00080d2e, 0x00080d3a
-               };
-
-               rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
-               rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
-               rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
-               if (rf->rf4)
-                       rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
-       }
-
-       rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
-       rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
-       rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
-       if (rf->rf4)
-               rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
-
-       /*
-        * Channel 14 requires the Japan filter bit to be set.
-        */
-       r70 = 0x46;
-       rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
-       rt2500pci_bbp_write(rt2x00dev, 70, r70);
-
-       msleep(1);
-
-       /*
-        * Switch off tuning bits.
-        * For RT2523 devices we do not need to update the R1 register.
-        */
-       if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
-               rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
-               rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
-       }
-
-       rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
-       rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
-
-       /*
-        * Clear false CRC during channel switch.
-        */
-       rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
-}
-
-static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
-                                    const int txpower)
-{
-       u32 rf3;
-
-       rt2x00_rf_read(rt2x00dev, 3, &rf3);
-       rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
-       rt2500pci_rf_write(rt2x00dev, 3, rf3);
-}
-
-static void rt2500pci_config_antenna(struct rt2x00_dev *rt2x00dev,
-                                    const int antenna_tx, const int antenna_rx)
-{
-       u32 reg;
-       u8 r14;
-       u8 r2;
-
-       rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
-       rt2500pci_bbp_read(rt2x00dev, 14, &r14);
-       rt2500pci_bbp_read(rt2x00dev, 2, &r2);
-
-       /*
-        * Configure the TX antenna.
-        */
-       switch (antenna_tx) {
-       case ANTENNA_SW_DIVERSITY:
-       case ANTENNA_HW_DIVERSITY:
-               rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
-               rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
-               rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
-               break;
-       case ANTENNA_A:
-               rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
-               rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
-               rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
-               break;
-       case ANTENNA_B:
-               rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
-               rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
-               rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
-               break;
-       }
-
-       /*
-        * Configure the RX antenna.
-        */
-       switch (antenna_rx) {
-       case ANTENNA_SW_DIVERSITY:
-       case ANTENNA_HW_DIVERSITY:
-               rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
-               break;
-       case ANTENNA_A:
-               rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
-               break;
-       case ANTENNA_B:
-               rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
-               break;
-       }
-
-       /*
-        * RT2525E and RT5222 need to flip TX I/Q
-        */
-       if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
-           rt2x00_rf(&rt2x00dev->chip, RF5222)) {
-               rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
-               rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
-               rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
-
-               /*
-                * RT2525E does not need RX I/Q Flip.
-                */
-               if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
-                       rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
-       } else {
-               rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
-               rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
-       }
-
-       rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
-       rt2500pci_bbp_write(rt2x00dev, 14, r14);
-       rt2500pci_bbp_write(rt2x00dev, 2, r2);
-}
-
-static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
-                                     struct rt2x00lib_conf *libconf)
-{
-       u32 reg;
-
-       rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
-       rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
-       rt2x00pci_register_write(rt2x00dev, CSR11, reg);
-
-       rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
-       rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
-       rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
-       rt2x00pci_register_write(rt2x00dev, CSR18, reg);
-
-       rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
-       rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
-       rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
-       rt2x00pci_register_write(rt2x00dev, CSR19, reg);
-
-       rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
-       rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
-       rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
-       rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
-
-       rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
-       rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
-                          libconf->conf->beacon_int * 16);
-       rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
-                          libconf->conf->beacon_int * 16);
-       rt2x00pci_register_write(rt2x00dev, CSR12, reg);
-}
-
-static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
-                            const unsigned int flags,
-                            struct rt2x00lib_conf *libconf)
-{
-       if (flags & CONFIG_UPDATE_PHYMODE)
-               rt2500pci_config_phymode(rt2x00dev, libconf->basic_rates);
-       if (flags & CONFIG_UPDATE_CHANNEL)
-               rt2500pci_config_channel(rt2x00dev, &libconf->rf,
-                                        libconf->conf->power_level);
-       if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
-               rt2500pci_config_txpower(rt2x00dev,
-                                        libconf->conf->power_level);
-       if (flags & CONFIG_UPDATE_ANTENNA)
-               rt2500pci_config_antenna(rt2x00dev,
-                                        libconf->conf->antenna_sel_tx,
-                                        libconf->conf->antenna_sel_rx);
-       if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
-               rt2500pci_config_duration(rt2x00dev, libconf);
-}
-
-/*
- * LED functions.
- */
-static void rt2500pci_enable_led(struct rt2x00_dev *rt2x00dev)
-{
-       u32 reg;
-
-       rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
-
-       rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
-       rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
-
-       if (rt2x00dev->led_mode == LED_MODE_TXRX_ACTIVITY) {
-               rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
-               rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
-       } else if (rt2x00dev->led_mode == LED_MODE_ASUS) {
-               rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
-               rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
-       } else {
-               rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
-               rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
-       }
-
-       rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
-}
-
-static void rt2500pci_disable_led(struct rt2x00_dev *rt2x00dev)
-{
-       u32 reg;
-
-       rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
-       rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
-       rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
-       rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
-}
-
-/*
- * Link tuning
- */
-static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev)
-{
-       u32 reg;
-
-       /*
-        * Update FCS error count from register.
-        */
-       rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
-       rt2x00dev->link.rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
-
-       /*
-        * Update False CCA count from register.
-        */
-       rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
-       rt2x00dev->link.false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
-}
-
-static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
-{
-       rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
-       rt2x00dev->link.vgc_level = 0x48;
-}
-
-static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
-{
-       int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
-       u8 r17;
-
-       /*
-        * To prevent collisions with MAC ASIC on chipsets
-        * up to version C the link tuning should halt after 20
-        * seconds.
-        */
-       if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
-           rt2x00dev->link.count > 20)
-               return;
-
-       rt2500pci_bbp_read(rt2x00dev, 17, &r17);
-
-       /*
-        * Chipset versions C and lower should directly continue
-        * to the dynamic CCA tuning.
-        */
-       if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D)
-               goto dynamic_cca_tune;
-
-       /*
-        * A too low RSSI will cause too much false CCA which will
-        * then corrupt the R17 tuning. To remidy this the tuning should
-        * be stopped (While making sure the R17 value will not exceed limits)
-        */
-       if (rssi < -80 && rt2x00dev->link.count > 20) {
-               if (r17 >= 0x41) {
-                       r17 = rt2x00dev->link.vgc_level;
-                       rt2500pci_bbp_write(rt2x00dev, 17, r17);
-               }
-               return;
-       }
-
-       /*
-        * Special big-R17 for short distance
-        */
-       if (rssi >= -58) {
-               if (r17 != 0x50)
-                       rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
-               return;
-       }
-
-       /*
-        * Special mid-R17 for middle distance
-        */
-       if (rssi >= -74) {
-               if (r17 != 0x41)
-                       rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
-               return;
-       }
-
-       /*
-        * Leave short or middle distance condition, restore r17
-        * to the dynamic tuning range.
-        */
-       if (r17 >= 0x41) {
-               rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
-               return;
-       }
-
-dynamic_cca_tune:
-
-       /*
-        * R17 is inside the dynamic tuning range,
-        * start tuning the link based on the false cca counter.
-        */
-       if (rt2x00dev->link.false_cca > 512 && r17 < 0x40) {
-               rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
-               rt2x00dev->link.vgc_level = r17;
-       } else if (rt2x00dev->link.false_cca < 100 && r17 > 0x32) {
-               rt2500pci_bbp_write(rt2x00dev, 17, --r17);
-               rt2x00dev->link.vgc_level = r17;
-       }
-}
-
-/*
- * Initialization functions.
- */
-static void rt2500pci_init_rxring(struct rt2x00_dev *rt2x00dev)
-{
-       struct data_ring *ring = rt2x00dev->rx;
-       struct data_desc *rxd;
-       unsigned int i;
-       u32 word;
-
-       memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
-
-       for (i = 0; i < ring->stats.limit; i++) {
-               rxd = ring->entry[i].priv;
-
-               rt2x00_desc_read(rxd, 1, &word);
-               rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS,
-                                  ring->entry[i].data_dma);
-               rt2x00_desc_write(rxd, 1, word);
-
-               rt2x00_desc_read(rxd, 0, &word);
-               rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
-               rt2x00_desc_write(rxd, 0, word);
-       }
-
-       rt2x00_ring_index_clear(rt2x00dev->rx);
-}
-
-static void rt2500pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
-{
-       struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
-       struct data_desc *txd;
-       unsigned int i;
-       u32 word;
-
-       memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
-
-       for (i = 0; i < ring->stats.limit; i++) {
-               txd = ring->entry[i].priv;
-
-               rt2x00_desc_read(txd, 1, &word);
-               rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS,
-                                  ring->entry[i].data_dma);
-               rt2x00_desc_write(txd, 1, word);
-
-               rt2x00_desc_read(txd, 0, &word);
-               rt2x00_set_field32(&word, TXD_W0_VALID, 0);
-               rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
-               rt2x00_desc_write(txd, 0, word);
-       }
-
-       rt2x00_ring_index_clear(ring);
-}
-
-static int rt2500pci_init_rings(struct rt2x00_dev *rt2x00dev)
-{
-       u32 reg;
-
-       /*
-        * Initialize rings.
-        */
-       rt2500pci_init_rxring(rt2x00dev);
-       rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
-       rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
-       rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
-       rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
-
-       /*
-        * Initialize registers.
-        */
-       rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
-       rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE,
-                          rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size);
-       rt2x00_set_field32(&reg, TXCSR2_NUM_TXD,
-                          rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
-       rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM,
-                          rt2x00dev->bcn[1].stats.limit);
-       rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO,
-                          rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
-       rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
-
-       rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
-       rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
-                          rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
-       rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
-
-       rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
-       rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
-                          rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
-       rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
-
-       rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
-       rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
-                          rt2x00dev->bcn[1].data_dma);
-       rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
-
-       rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
-       rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
-                          rt2x00dev->bcn[0].data_dma);
-       rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
-
-       rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
-       rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
-       rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->stats.limit);
-       rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
-
-       rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
-       rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
-                          rt2x00dev->rx->data_dma);
-       rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
-
-       return 0;
-}
-
-static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
-{
-       u32 reg;
-
-       rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
-       rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
-       rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
-       rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
-
-       rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
-       rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
-       rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
-       rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
-       rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
-
-       rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
-       rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
-                          rt2x00dev->rx->data_size / 128);
-       rt2x00pci_register_write(rt2x00dev, CSR9, reg);
-
-       /*
-        * Always use CWmin and CWmax set in descriptor.
-        */
-       rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
-       rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
-       rt2x00pci_register_write(rt2x00dev, CSR11, reg);
-
-       rt2x00pci_register_write(rt2x00dev, CNT3, 0);
-
-       rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
-       rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
-       rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
-       rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
-       rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
-       rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
-       rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
-       rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
-       rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
-       rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
-
-       rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
-       rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
-       rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
-       rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
-       rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
-       rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
-
-       rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
-       rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
-       rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
-       rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
-       rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
-       rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
-
-       rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
-       rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
-       rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
-       rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
-       rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
-       rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
-
-       rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
-       rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
-       rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
-       rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
-       rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
-       rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
-       rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
-       rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
-       rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
-       rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
-
-       rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
-       rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
-       rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
-       rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
-       rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
-       rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
-       rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
-       rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
-       rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
-
-       rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
-
-       rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
-       rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
-
-       if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
-               return -EBUSY;
-
-       rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
-       rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
-
-       rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
-       rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
-       rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
-
-       rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
-       rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
-       rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
-       rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
-       rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
-       rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
-       rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
-       rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
-
-       rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
-
-       rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
-
-       rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
-       rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
-       rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
-       rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
-       rt2x00pci_register_write(rt2x00dev, CSR1, reg);
-
-       rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
-       rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
-       rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
-       rt2x00pci_register_write(rt2x00dev, CSR1, reg);
-
-       /*
-        * We must clear the FCS and FIFO error count.
-        * These registers are cleared on read,
-        * so we may pass a useless variable to store the value.
-        */
-       rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
-       rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
-
-       return 0;
-}
-
-static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
-{
-       unsigned int i;
-       u16 eeprom;
-       u8 reg_id;
-       u8 value;
-
-       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
-               rt2500pci_bbp_read(rt2x00dev, 0, &value);
-               if ((value != 0xff) && (value != 0x00))
-                       goto continue_csr_init;
-               NOTICE(rt2x00dev, "Waiting for BBP register.\n");
-               udelay(REGISTER_BUSY_DELAY);
-       }
-
-       ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
-       return -EACCES;
-
-continue_csr_init:
-       rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
-       rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
-       rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
-       rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
-       rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
-       rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
-       rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
-       rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
-       rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
-       rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
-       rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
-       rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
-       rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
-       rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
-       rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
-       rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
-       rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
-       rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
-       rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
-       rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
-       rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
-       rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
-       rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
-       rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
-       rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
-       rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
-       rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
-       rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
-       rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
-       rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
-
-       DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
-       for (i = 0; i < EEPROM_BBP_SIZE; i++) {
-               rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
-
-               if (eeprom != 0xffff && eeprom != 0x0000) {
-                       reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
-                       value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
-                       DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
-                             reg_id, value);
-                       rt2500pci_bbp_write(rt2x00dev, reg_id, value);
-               }
-       }
-       DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
-
-       return 0;
-}
-
-/*
- * Device state switch handlers.
- */
-static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
-                               enum dev_state state)
-{
-       u32 reg;
-
-       rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
-       rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
-                          state == STATE_RADIO_RX_OFF);
-       rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
-}
-
-static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
-                                enum dev_state state)
-{
-       int mask = (state == STATE_RADIO_IRQ_OFF);
-       u32 reg;
-
-       /*
-        * When interrupts are being enabled, the interrupt registers
-        * should clear the register to assure a clean state.
-        */
-       if (state == STATE_RADIO_IRQ_ON) {
-               rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
-               rt2x00pci_register_write(rt2x00dev, CSR7, reg);
-       }
-
-       /*
-        * Only toggle the interrupts bits we are going to use.
-        * Non-checked interrupt bits are disabled by default.
-        */
-       rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
-       rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
-       rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
-       rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
-       rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
-       rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
-       rt2x00pci_register_write(rt2x00dev, CSR8, reg);
-}
-
-static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
-{
-       /*
-        * Initialize all registers.
-        */
-       if (rt2500pci_init_rings(rt2x00dev) ||
-           rt2500pci_init_registers(rt2x00dev) ||
-           rt2500pci_init_bbp(rt2x00dev)) {
-               ERROR(rt2x00dev, "Register initialization failed.\n");
-               return -EIO;
-       }
-
-       /*
-        * Enable interrupts.
-        */
-       rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
-
-       /*
-        * Enable LED
-        */
-       rt2500pci_enable_led(rt2x00dev);
-
-       return 0;
-}
-
-static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
-{
-       u32 reg;
-
-       /*
-        * Disable LED
-        */
-       rt2500pci_disable_led(rt2x00dev);
-
-       rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
-
-       /*
-        * Disable synchronisation.
-        */
-       rt2x00pci_register_write(rt2x00dev, CSR14, 0);
-
-       /*
-        * Cancel RX and TX.
-        */
-       rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
-       rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
-       rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
-
-       /*
-        * Disable interrupts.
-        */
-       rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
-}
-
-static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
-                              enum dev_state state)
-{
-       u32 reg;
-       unsigned int i;
-       char put_to_sleep;
-       char bbp_state;
-       char rf_state;
-
-       put_to_sleep = (state != STATE_AWAKE);
-
-       rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
-       rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
-       rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
-       rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
-       rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
-       rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
-
-       /*
-        * Device is not guaranteed to be in the requested state yet.
-        * We must wait until the register indicates that the
-        * device has entered the correct state.
-        */
-       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
-               rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
-               bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
-               rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
-               if (bbp_state == state && rf_state == state)
-                       return 0;
-               msleep(10);
-       }
-
-       NOTICE(rt2x00dev, "Device failed to enter state %d, "
-              "current device state: bbp %d and rf %d.\n",
-              state, bbp_state, rf_state);
-
-       return -EBUSY;
-}
-
-static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
-                                     enum dev_state state)
-{
-       int retval = 0;
-
-       switch (state) {
-       case STATE_RADIO_ON:
-               retval = rt2500pci_enable_radio(rt2x00dev);
-               break;
-       case STATE_RADIO_OFF:
-               rt2500pci_disable_radio(rt2x00dev);
-               break;
-       case STATE_RADIO_RX_ON:
-       case STATE_RADIO_RX_OFF:
-               rt2500pci_toggle_rx(rt2x00dev, state);
-               break;
-       case STATE_DEEP_SLEEP:
-       case STATE_SLEEP:
-       case STATE_STANDBY:
-       case STATE_AWAKE:
-               retval = rt2500pci_set_state(rt2x00dev, state);
-               break;
-       default:
-               retval = -ENOTSUPP;
-               break;
-       }
-
-       return retval;
-}
-
-/*
- * TX descriptor initialization
- */
-static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
-                                   struct data_desc *txd,
-                                   struct txdata_entry_desc *desc,
-                                   struct ieee80211_hdr *ieee80211hdr,
-                                   unsigned int length,
-                                   struct ieee80211_tx_control *control)
-{
-       u32 word;
-
-       /*
-        * Start writing the descriptor words.
-        */
-       rt2x00_desc_read(txd, 2, &word);
-       rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
-       rt2x00_set_field32(&word, TXD_W2_AIFS, desc->aifs);
-       rt2x00_set_field32(&word, TXD_W2_CWMIN, desc->cw_min);
-       rt2x00_set_field32(&word, TXD_W2_CWMAX, desc->cw_max);
-       rt2x00_desc_write(txd, 2, word);
-
-       rt2x00_desc_read(txd, 3, &word);
-       rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, desc->signal);
-       rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, desc->service);
-       rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, desc->length_low);
-       rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, desc->length_high);
-       rt2x00_desc_write(txd, 3, word);
-
-       rt2x00_desc_read(txd, 10, &word);
-       rt2x00_set_field32(&word, TXD_W10_RTS,
-                          test_bit(ENTRY_TXD_RTS_FRAME, &desc->flags));
-       rt2x00_desc_write(txd, 10, word);
-
-       rt2x00_desc_read(txd, 0, &word);
-       rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
-       rt2x00_set_field32(&word, TXD_W0_VALID, 1);
-       rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
-                          test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
-       rt2x00_set_field32(&word, TXD_W0_ACK,
-                          !(control->flags & IEEE80211_TXCTL_NO_ACK));
-       rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
-                          test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
-       rt2x00_set_field32(&word, TXD_W0_OFDM,
-                          test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
-       rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
-       rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
-       rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
-                          !!(control->flags &
-                             IEEE80211_TXCTL_LONG_RETRY_LIMIT));
-       rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
-       rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
-       rt2x00_desc_write(txd, 0, word);
-}
-
-/*
- * TX data initialization
- */
-static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
-                                   unsigned int queue)
-{
-       u32 reg;
-
-       if (queue == IEEE80211_TX_QUEUE_BEACON) {
-               rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
-               if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
-                       rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
-                       rt2x00pci_register_write(rt2x00dev, CSR14, reg);
-               }
-               return;
-       }
-
-       rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
-       if (queue == IEEE80211_TX_QUEUE_DATA0)
-               rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
-       else if (queue == IEEE80211_TX_QUEUE_DATA1)
-               rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
-       else if (queue == IEEE80211_TX_QUEUE_AFTER_BEACON)
-               rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
-       rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
-}
-
-/*
- * RX control handlers
- */
-static void rt2500pci_fill_rxdone(struct data_entry *entry,
-                                 struct rxdata_entry_desc *desc)
-{
-       struct data_desc *rxd = entry->priv;
-       u32 word0;
-       u32 word2;
-
-       rt2x00_desc_read(rxd, 0, &word0);
-       rt2x00_desc_read(rxd, 2, &word2);
-
-       desc->flags = 0;
-       if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
-               desc->flags |= RX_FLAG_FAILED_FCS_CRC;
-       if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
-               desc->flags |= RX_FLAG_FAILED_PLCP_CRC;
-
-       desc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
-       desc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
-           entry->ring->rt2x00dev->rssi_offset;
-       desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
-       desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
-}
-
-/*
- * Interrupt functions.
- */
-static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue)
-{
-       struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
-       struct data_entry *entry;
-       struct data_desc *txd;
-       u32 word;
-       int tx_status;
-       int retry;
-
-       while (!rt2x00_ring_empty(ring)) {
-               entry = rt2x00_get_data_entry_done(ring);
-               txd = entry->priv;
-               rt2x00_desc_read(txd, 0, &word);
-
-               if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
-                   !rt2x00_get_field32(word, TXD_W0_VALID))
-                       break;
-
-               /*
-                * Obtain the status about this packet.
-                */
-               tx_status = rt2x00_get_field32(word, TXD_W0_RESULT);
-               retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
-
-               rt2x00lib_txdone(entry, tx_status, retry);
-
-               /*
-                * Make this entry available for reuse.
-                */
-               entry->flags = 0;
-               rt2x00_set_field32(&word, TXD_W0_VALID, 0);
-               rt2x00_desc_write(txd, 0, word);
-               rt2x00_ring_index_done_inc(ring);
-       }
-
-       /*
-        * If the data ring was full before the txdone handler
-        * we must make sure the packet queue in the mac80211 stack
-        * is reenabled when the txdone handler has finished.
-        */
-       entry = ring->entry;
-       if (!rt2x00_ring_full(ring))
-               ieee80211_wake_queue(rt2x00dev->hw,
-                                    entry->tx_status.control.queue);
-}
-
-static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
-{
-       struct rt2x00_dev *rt2x00dev = dev_instance;
-       u32 reg;
-
-       /*
-        * Get the interrupt sources & saved to local variable.
-        * Write register value back to clear pending interrupts.
-        */
-       rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
-       rt2x00pci_register_write(rt2x00dev, CSR7, reg);
-
-       if (!reg)
-               return IRQ_NONE;
-
-       if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
-               return IRQ_HANDLED;
-
-       /*
-        * Handle interrupts, walk through all bits
-        * and run the tasks, the bits are checked in order of
-        * priority.
-        */
-
-       /*
-        * 1 - Beacon timer expired interrupt.
-        */
-       if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
-               rt2x00lib_beacondone(rt2x00dev);
-
-       /*
-        * 2 - Rx ring done interrupt.
-        */
-       if (rt2x00_get_field32(reg, CSR7_RXDONE))
-               rt2x00pci_rxdone(rt2x00dev);
-
-       /*
-        * 3 - Atim ring transmit done interrupt.
-        */
-       if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
-               rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
-
-       /*
-        * 4 - Priority ring transmit done interrupt.
-        */
-       if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
-               rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
-
-       /*
-        * 5 - Tx ring transmit done interrupt.
-        */
-       if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
-               rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
-
-       return IRQ_HANDLED;
-}
-
-/*
- * Device probe functions.
- */
-static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
-{
-       struct eeprom_93cx6 eeprom;
-       u32 reg;
-       u16 word;
-       u8 *mac;
-
-       rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
-
-       eeprom.data = rt2x00dev;
-       eeprom.register_read = rt2500pci_eepromregister_read;
-       eeprom.register_write = rt2500pci_eepromregister_write;
-       eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
-           PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
-       eeprom.reg_data_in = 0;
-       eeprom.reg_data_out = 0;
-       eeprom.reg_data_clock = 0;
-       eeprom.reg_chip_select = 0;
-
-       eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
-                              EEPROM_SIZE / sizeof(u16));
-
-       /*
-        * Start validation of the data that has been read.
-        */
-       mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
-       if (!is_valid_ether_addr(mac)) {
-               DECLARE_MAC_BUF(macbuf);
-
-               random_ether_addr(mac);
-               EEPROM(rt2x00dev, "MAC: %s\n",
-                      print_mac(macbuf, mac));
-       }
-
-       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
-       if (word == 0xffff) {
-               rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
-               rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, 0);
-               rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, 0);
-               rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE, 0);
-               rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
-               rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
-               rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
-               rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
-               EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
-       }
-
-       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
-       if (word == 0xffff) {
-               rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
-               rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
-               rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
-               rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
-               EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
-       }
-
-       rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
-       if (word == 0xffff) {
-               rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
-                                  DEFAULT_RSSI_OFFSET);
-               rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
-               EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
-       }
-
-       return 0;
-}
-
-static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
-{
-       u32 reg;
-       u16 value;
-       u16 eeprom;
-
-       /*
-        * Read EEPROM word for configuration.
-        */
-       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
-
-       /*
-        * Identify RF chipset.
-        */
-       value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
-       rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
-       rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
-
-       if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
-           !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
-           !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
-           !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
-           !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
-           !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
-               ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
-               return -ENODEV;
-       }
-
-       /*
-        * Identify default antenna configuration.
-        */
-       rt2x00dev->hw->conf.antenna_sel_tx =
-           rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
-       rt2x00dev->hw->conf.antenna_sel_rx =
-           rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
-
-       /*
-        * Store led mode, for correct led behaviour.
-        */
-       rt2x00dev->led_mode =
-           rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
-
-       /*
-        * Detect if this device has an hardware controlled radio.
-        */
-#ifdef CONFIG_RT2500PCI_RFKILL
-       if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
-               __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
-#endif /* CONFIG_RT2500PCI_RFKILL */
-
-       /*
-        * Check if the BBP tuning should be enabled.
-        */
-       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
-
-       if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
-               __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
-
-       /*
-        * Read the RSSI <-> dBm offset information.
-        */
-       rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
-       rt2x00dev->rssi_offset =
-           rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
-
-       return 0;
-}
-
-/*
- * RF value list for RF2522
- * Supports: 2.4 GHz
- */
-static const struct rf_channel rf_vals_bg_2522[] = {
-       { 1,  0x00002050, 0x000c1fda, 0x00000101, 0 },
-       { 2,  0x00002050, 0x000c1fee, 0x00000101, 0 },
-       { 3,  0x00002050, 0x000c2002, 0x00000101, 0 },
-       { 4,  0x00002050, 0x000c2016, 0x00000101, 0 },
-       { 5,  0x00002050, 0x000c202a, 0x00000101, 0 },
-       { 6,  0x00002050, 0x000c203e, 0x00000101, 0 },
-       { 7,  0x00002050, 0x000c2052, 0x00000101, 0 },
-       { 8,  0x00002050, 0x000c2066, 0x00000101, 0 },
-       { 9,  0x00002050, 0x000c207a, 0x00000101, 0 },
-       { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
-       { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
-       { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
-       { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
-       { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
-};
-
-/*
- * RF value list for RF2523
- * Supports: 2.4 GHz
- */
-static const struct rf_channel rf_vals_bg_2523[] = {
-       { 1,  0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
-       { 2,  0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
-       { 3,  0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
-       { 4,  0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
-       { 5,  0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
-       { 6,  0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
-       { 7,  0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
-       { 8,  0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
-       { 9,  0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
-       { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
-       { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
-       { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
-       { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
-       { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
-};
-
-/*
- * RF value list for RF2524
- * Supports: 2.4 GHz
- */
-static const struct rf_channel rf_vals_bg_2524[] = {
-       { 1,  0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
-       { 2,  0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
-       { 3,  0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
-       { 4,  0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
-       { 5,  0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
-       { 6,  0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
-       { 7,  0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
-       { 8,  0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
-       { 9,  0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
-       { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
-       { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
-       { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
-       { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
-       { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
-};
-
-/*
- * RF value list for RF2525
- * Supports: 2.4 GHz
- */
-static const struct rf_channel rf_vals_bg_2525[] = {
-       { 1,  0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
-       { 2,  0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
-       { 3,  0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
-       { 4,  0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
-       { 5,  0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
-       { 6,  0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
-       { 7,  0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
-       { 8,  0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
-       { 9,  0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
-       { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
-       { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
-       { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
-       { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
-       { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
-};
-
-/*
- * RF value list for RF2525e
- * Supports: 2.4 GHz
- */
-static const struct rf_channel rf_vals_bg_2525e[] = {
-       { 1,  0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
-       { 2,  0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
-       { 3,  0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
-       { 4,  0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
-       { 5,  0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
-       { 6,  0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
-       { 7,  0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
-       { 8,  0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
-       { 9,  0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
-       { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
-       { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
-       { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
-       { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
-       { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
-};
-
-/*
- * RF value list for RF5222
- * Supports: 2.4 GHz & 5.2 GHz
- */
-static const struct rf_channel rf_vals_5222[] = {
-       { 1,  0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
-       { 2,  0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
-       { 3,  0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
-       { 4,  0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
-       { 5,  0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
-       { 6,  0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
-       { 7,  0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
-       { 8,  0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
-       { 9,  0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
-       { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
-       { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
-       { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
-       { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
-       { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
-
-       /* 802.11 UNI / HyperLan 2 */
-       { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
-       { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
-       { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
-       { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
-       { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
-       { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
-       { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
-       { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
-
-       /* 802.11 HyperLan 2 */
-       { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
-       { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
-       { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
-       { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
-       { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
-       { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
-       { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
-       { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
-       { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
-       { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
-
-       /* 802.11 UNII */
-       { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
-       { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
-       { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
-       { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
-       { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
-};
-
-static void rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
-{
-       struct hw_mode_spec *spec = &rt2x00dev->spec;
-       u8 *txpower;
-       unsigned int i;
-
-       /*
-        * Initialize all hw fields.
-        */
-       rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
-       rt2x00dev->hw->extra_tx_headroom = 0;
-       rt2x00dev->hw->max_signal = MAX_SIGNAL;
-       rt2x00dev->hw->max_rssi = MAX_RX_SSI;
-       rt2x00dev->hw->queues = 2;
-
-       SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
-       SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
-                               rt2x00_eeprom_addr(rt2x00dev,
-                                                  EEPROM_MAC_ADDR_0));
-
-       /*
-        * Convert tx_power array in eeprom.
-        */
-       txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
-       for (i = 0; i < 14; i++)
-               txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
-
-       /*
-        * Initialize hw_mode information.
-        */
-       spec->num_modes = 2;
-       spec->num_rates = 12;
-       spec->tx_power_a = NULL;
-       spec->tx_power_bg = txpower;
-       spec->tx_power_default = DEFAULT_TXPOWER;
-
-       if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
-               spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
-               spec->channels = rf_vals_bg_2522;
-       } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
-               spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
-               spec->channels = rf_vals_bg_2523;
-       } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
-               spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
-               spec->channels = rf_vals_bg_2524;
-       } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
-               spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
-               spec->channels = rf_vals_bg_2525;
-       } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
-               spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
-               spec->channels = rf_vals_bg_2525e;
-       } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
-               spec->num_channels = ARRAY_SIZE(rf_vals_5222);
-               spec->channels = rf_vals_5222;
-               spec->num_modes = 3;
-       }
-}
-
-static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
-{
-       int retval;
-
-       /*
-        * Allocate eeprom data.
-        */
-       retval = rt2500pci_validate_eeprom(rt2x00dev);
-       if (retval)
-               return retval;
-
-       retval = rt2500pci_init_eeprom(rt2x00dev);
-       if (retval)
-               return retval;
-
-       /*
-        * Initialize hw specifications.
-        */
-       rt2500pci_probe_hw_mode(rt2x00dev);
-
-       /*
-        * This device requires the beacon ring
-        */
-       __set_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags);
-
-       /*
-        * Set the rssi offset.
-        */
-       rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
-
-       return 0;
-}
-
-/*
- * IEEE80211 stack callback functions.
- */
-static void rt2500pci_configure_filter(struct ieee80211_hw *hw,
-                                      unsigned int changed_flags,
-                                      unsigned int *total_flags,
-                                      int mc_count,
-                                      struct dev_addr_list *mc_list)
-{
-       struct rt2x00_dev *rt2x00dev = hw->priv;
-       struct interface *intf = &rt2x00dev->interface;
-       u32 reg;
-
-       /*
-        * Mask off any flags we are going to ignore from
-        * the total_flags field.
-        */
-       *total_flags &=
-           FIF_ALLMULTI |
-           FIF_FCSFAIL |
-           FIF_PLCPFAIL |
-           FIF_CONTROL |
-           FIF_OTHER_BSS |
-           FIF_PROMISC_IN_BSS;
-
-       /*
-        * Apply some rules to the filters:
-        * - Some filters imply different filters to be set.
-        * - Some things we can't filter out at all.
-        * - Some filters are set based on interface type.
-        */
-       if (mc_count)
-               *total_flags |= FIF_ALLMULTI;
-       if (*total_flags & FIF_OTHER_BSS ||
-           *total_flags & FIF_PROMISC_IN_BSS)
-               *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
-       if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
-               *total_flags |= FIF_PROMISC_IN_BSS;
-
-       /*
-        * Check if there is any work left for us.
-        */
-       if (intf->filter == *total_flags)
-               return;
-       intf->filter = *total_flags;
-
-       /*
-        * Start configuration steps.
-        * Note that the version error will always be dropped
-        * and broadcast frames will always be accepted since
-        * there is no filter for it at this time.
-        */
-       rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
-       rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
-                          !(*total_flags & FIF_FCSFAIL));
-       rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
-                          !(*total_flags & FIF_PLCPFAIL));
-       rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
-                          !(*total_flags & FIF_CONTROL));
-       rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
-                          !(*total_flags & FIF_PROMISC_IN_BSS));
-       rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
-                          !(*total_flags & FIF_PROMISC_IN_BSS));
-       rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
-       rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
-                          !(*total_flags & FIF_ALLMULTI));
-       rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
-       rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
-}
-
-static int rt2500pci_set_retry_limit(struct ieee80211_hw *hw,
-                                    u32 short_retry, u32 long_retry)
-{
-       struct rt2x00_dev *rt2x00dev = hw->priv;
-       u32 reg;
-
-       rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
-       rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
-       rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
-       rt2x00pci_register_write(rt2x00dev, CSR11, reg);
-
-       return 0;
-}
-
-static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
-{
-       struct rt2x00_dev *rt2x00dev = hw->priv;
-       u64 tsf;
-       u32 reg;
-
-       rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
-       tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
-       rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
-       tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
-
-       return tsf;
-}
-
-static void rt2500pci_reset_tsf(struct ieee80211_hw *hw)
-{
-       struct rt2x00_dev *rt2x00dev = hw->priv;
-
-       rt2x00pci_register_write(rt2x00dev, CSR16, 0);
-       rt2x00pci_register_write(rt2x00dev, CSR17, 0);
-}
-
-static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
-{
-       struct rt2x00_dev *rt2x00dev = hw->priv;
-       u32 reg;
-
-       rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
-       return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
-}
-
-static const struct ieee80211_ops rt2500pci_mac80211_ops = {
-       .tx                     = rt2x00mac_tx,
-       .start                  = rt2x00mac_start,
-       .stop                   = rt2x00mac_stop,
-       .add_interface          = rt2x00mac_add_interface,
-       .remove_interface       = rt2x00mac_remove_interface,
-       .config                 = rt2x00mac_config,
-       .config_interface       = rt2x00mac_config_interface,
-       .configure_filter       = rt2500pci_configure_filter,
-       .get_stats              = rt2x00mac_get_stats,
-       .set_retry_limit        = rt2500pci_set_retry_limit,
-       .erp_ie_changed         = rt2x00mac_erp_ie_changed,
-       .conf_tx                = rt2x00mac_conf_tx,
-       .get_tx_stats           = rt2x00mac_get_tx_stats,
-       .get_tsf                = rt2500pci_get_tsf,
-       .reset_tsf              = rt2500pci_reset_tsf,
-       .beacon_update          = rt2x00pci_beacon_update,
-       .tx_last_beacon         = rt2500pci_tx_last_beacon,
-};
-
-static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
-       .irq_handler            = rt2500pci_interrupt,
-       .probe_hw               = rt2500pci_probe_hw,
-       .initialize             = rt2x00pci_initialize,
-       .uninitialize           = rt2x00pci_uninitialize,
-       .set_device_state       = rt2500pci_set_device_state,
-       .rfkill_poll            = rt2500pci_rfkill_poll,
-       .link_stats             = rt2500pci_link_stats,
-       .reset_tuner            = rt2500pci_reset_tuner,
-       .link_tuner             = rt2500pci_link_tuner,
-       .write_tx_desc          = rt2500pci_write_tx_desc,
-       .write_tx_data          = rt2x00pci_write_tx_data,
-       .kick_tx_queue          = rt2500pci_kick_tx_queue,
-       .fill_rxdone            = rt2500pci_fill_rxdone,
-       .config_mac_addr        = rt2500pci_config_mac_addr,
-       .config_bssid           = rt2500pci_config_bssid,
-       .config_type            = rt2500pci_config_type,
-       .config_preamble        = rt2500pci_config_preamble,
-       .config                 = rt2500pci_config,
-};
-
-static const struct rt2x00_ops rt2500pci_ops = {
-       .name           = DRV_NAME,
-       .rxd_size       = RXD_DESC_SIZE,
-       .txd_size       = TXD_DESC_SIZE,
-       .eeprom_size    = EEPROM_SIZE,
-       .rf_size        = RF_SIZE,
-       .lib            = &rt2500pci_rt2x00_ops,
-       .hw             = &rt2500pci_mac80211_ops,
-#ifdef CONFIG_RT2X00_LIB_DEBUGFS
-       .debugfs        = &rt2500pci_rt2x00debug,
-#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
-};
-
-/*
- * RT2500pci module information.
- */
-static struct pci_device_id rt2500pci_device_table[] = {
-       { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
-       { 0, }
-};
-
-MODULE_AUTHOR(DRV_PROJECT);
-MODULE_VERSION(DRV_VERSION);
-MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
-MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
-MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
-MODULE_LICENSE("GPL");
-
-static struct pci_driver rt2500pci_driver = {
-       .name           = DRV_NAME,
-       .id_table       = rt2500pci_device_table,
-       .probe          = rt2x00pci_probe,
-       .remove         = __devexit_p(rt2x00pci_remove),
-       .suspend        = rt2x00pci_suspend,
-       .resume         = rt2x00pci_resume,
-};
-
-static int __init rt2500pci_init(void)
-{
-       return pci_register_driver(&rt2500pci_driver);
-}
-
-static void __exit rt2500pci_exit(void)
-{
-       pci_unregister_driver(&rt2500pci_driver);
-}
-
-module_init(rt2500pci_init);
-module_exit(rt2500pci_exit);
diff --git a/package/rt2x00/src/rt2500pci.h b/package/rt2x00/src/rt2500pci.h
deleted file mode 100644 (file)
index d92aa56..0000000
+++ /dev/null
@@ -1,1236 +0,0 @@
-/*
-       Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
-       <http://rt2x00.serialmonkey.com>
-
-       This program is free software; you can redistribute it and/or modify
-       it under the terms of the GNU General Public License as published by
-       the Free Software Foundation; either version 2 of the License, or
-       (at your option) any later version.
-
-       This program is distributed in the hope that it will be useful,
-       but WITHOUT ANY WARRANTY; without even the implied warranty of
-       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-       GNU General Public License for more details.
-
-       You should have received a copy of the GNU General Public License
-       along with this program; if not, write to the
-       Free Software Foundation, Inc.,
-       59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-/*
-       Module: rt2500pci
-       Abstract: Data structures and registers for the rt2500pci module.
-       Supported chipsets: RT2560.
- */
-
-#ifndef RT2500PCI_H
-#define RT2500PCI_H
-
-/*
- * RF chip defines.
- */
-#define RF2522                         0x0000
-#define RF2523                         0x0001
-#define RF2524                         0x0002
-#define RF2525                         0x0003
-#define RF2525E                                0x0004
-#define RF5222                         0x0010
-
-/*
- * RT2560 version
- */
-#define RT2560_VERSION_B               2
-#define RT2560_VERSION_C               3
-#define RT2560_VERSION_D               4
-
-/*
- * Signal information.
- * Defaul offset is required for RSSI <-> dBm conversion.
- */
-#define MAX_SIGNAL                     100
-#define MAX_RX_SSI                     -1
-#define DEFAULT_RSSI_OFFSET            121
-
-/*
- * Register layout information.
- */
-#define CSR_REG_BASE                   0x0000
-#define CSR_REG_SIZE                   0x0174
-#define EEPROM_BASE                    0x0000
-#define EEPROM_SIZE                    0x0200
-#define BBP_SIZE                       0x0040
-#define RF_SIZE                                0x0014
-
-/*
- * Control/Status Registers(CSR).
- * Some values are set in TU, whereas 1 TU == 1024 us.
- */
-
-/*
- * CSR0: ASIC revision number.
- */
-#define CSR0                           0x0000
-
-/*
- * CSR1: System control register.
- * SOFT_RESET: Software reset, 1: reset, 0: normal.
- * BBP_RESET: Hardware reset, 1: reset, 0, release.
- * HOST_READY: Host ready after initialization.
- */
-#define CSR1                           0x0004
-#define CSR1_SOFT_RESET                        FIELD32(0x00000001)
-#define CSR1_BBP_RESET                 FIELD32(0x00000002)
-#define CSR1_HOST_READY                        FIELD32(0x00000004)
-
-/*
- * CSR2: System admin status register (invalid).
- */
-#define CSR2                           0x0008
-
-/*
- * CSR3: STA MAC address register 0.
- */
-#define CSR3                           0x000c
-#define CSR3_BYTE0                     FIELD32(0x000000ff)
-#define CSR3_BYTE1                     FIELD32(0x0000ff00)
-#define CSR3_BYTE2                     FIELD32(0x00ff0000)
-#define CSR3_BYTE3                     FIELD32(0xff000000)
-
-/*
- * CSR4: STA MAC address register 1.
- */
-#define CSR4                           0x0010
-#define CSR4_BYTE4                     FIELD32(0x000000ff)
-#define CSR4_BYTE5                     FIELD32(0x0000ff00)
-
-/*
- * CSR5: BSSID register 0.
- */
-#define CSR5                           0x0014
-#define CSR5_BYTE0                     FIELD32(0x000000ff)
-#define CSR5_BYTE1                     FIELD32(0x0000ff00)
-#define CSR5_BYTE2                     FIELD32(0x00ff0000)
-#define CSR5_BYTE3                     FIELD32(0xff000000)
-
-/*
- * CSR6: BSSID register 1.
- */
-#define CSR6                           0x0018
-#define CSR6_BYTE4                     FIELD32(0x000000ff)
-#define CSR6_BYTE5                     FIELD32(0x0000ff00)
-
-/*
- * CSR7: Interrupt source register.
- * Write 1 to clear.
- * TBCN_EXPIRE: Beacon timer expired interrupt.
- * TWAKE_EXPIRE: Wakeup timer expired interrupt.
- * TATIMW_EXPIRE: Timer of atim window expired interrupt.
- * TXDONE_TXRING: Tx ring transmit done interrupt.
- * TXDONE_ATIMRING: Atim ring transmit done interrupt.
- * TXDONE_PRIORING: Priority ring transmit done interrupt.
- * RXDONE: Receive done interrupt.
- * DECRYPTION_DONE: Decryption done interrupt.
- * ENCRYPTION_DONE: Encryption done interrupt.
- * UART1_TX_TRESHOLD: UART1 TX reaches threshold.
- * UART1_RX_TRESHOLD: UART1 RX reaches threshold.
- * UART1_IDLE_TRESHOLD: UART1 IDLE over threshold.
- * UART1_TX_BUFF_ERROR: UART1 TX buffer error.
- * UART1_RX_BUFF_ERROR: UART1 RX buffer error.
- * UART2_TX_TRESHOLD: UART2 TX reaches threshold.
- * UART2_RX_TRESHOLD: UART2 RX reaches threshold.
- * UART2_IDLE_TRESHOLD: UART2 IDLE over threshold.
- * UART2_TX_BUFF_ERROR: UART2 TX buffer error.
- * UART2_RX_BUFF_ERROR: UART2 RX buffer error.
- * TIMER_CSR3_EXPIRE: TIMECSR3 timer expired (802.1H quiet period).
-
- */
-#define CSR7                           0x001c
-#define CSR7_TBCN_EXPIRE               FIELD32(0x00000001)
-#define CSR7_TWAKE_EXPIRE              FIELD32(0x00000002)
-#define CSR7_TATIMW_EXPIRE             FIELD32(0x00000004)
-#define CSR7_TXDONE_TXRING             FIELD32(0x00000008)
-#define CSR7_TXDONE_ATIMRING           FIELD32(0x00000010)
-#define CSR7_TXDONE_PRIORING           FIELD32(0x00000020)
-#define CSR7_RXDONE                    FIELD32(0x00000040)
-#define CSR7_DECRYPTION_DONE           FIELD32(0x00000080)
-#define CSR7_ENCRYPTION_DONE           FIELD32(0x00000100)
-#define CSR7_UART1_TX_TRESHOLD         FIELD32(0x00000200)
-#define CSR7_UART1_RX_TRESHOLD         FIELD32(0x00000400)
-#define CSR7_UART1_IDLE_TRESHOLD       FIELD32(0x00000800)
-#define CSR7_UART1_TX_BUFF_ERROR       FIELD32(0x00001000)
-#define CSR7_UART1_RX_BUFF_ERROR       FIELD32(0x00002000)
-#define CSR7_UART2_TX_TRESHOLD         FIELD32(0x00004000)
-#define CSR7_UART2_RX_TRESHOLD         FIELD32(0x00008000)
-#define CSR7_UART2_IDLE_TRESHOLD       FIELD32(0x00010000)
-#define CSR7_UART2_TX_BUFF_ERROR       FIELD32(0x00020000)
-#define CSR7_UART2_RX_BUFF_ERROR       FIELD32(0x00040000)
-#define CSR7_TIMER_CSR3_EXPIRE         FIELD32(0x00080000)
-
-/*
- * CSR8: Interrupt mask register.
- * Write 1 to mask interrupt.
- * TBCN_EXPIRE: Beacon timer expired interrupt.
- * TWAKE_EXPIRE: Wakeup timer expired interrupt.
- * TATIMW_EXPIRE: Timer of atim window expired interrupt.
- * TXDONE_TXRING: Tx ring transmit done interrupt.
- * TXDONE_ATIMRING: Atim ring transmit done interrupt.
- * TXDONE_PRIORING: Priority ring transmit done interrupt.
- * RXDONE: Receive done interrupt.
- * DECRYPTION_DONE: Decryption done interrupt.
- * ENCRYPTION_DONE: Encryption done interrupt.
- * UART1_TX_TRESHOLD: UART1 TX reaches threshold.
- * UART1_RX_TRESHOLD: UART1 RX reaches threshold.
- * UART1_IDLE_TRESHOLD: UART1 IDLE over threshold.
- * UART1_TX_BUFF_ERROR: UART1 TX buffer error.
- * UART1_RX_BUFF_ERROR: UART1 RX buffer error.
- * UART2_TX_TRESHOLD: UART2 TX reaches threshold.
- * UART2_RX_TRESHOLD: UART2 RX reaches threshold.
- * UART2_IDLE_TRESHOLD: UART2 IDLE over threshold.
- * UART2_TX_BUFF_ERROR: UART2 TX buffer error.
- * UART2_RX_BUFF_ERROR: UART2 RX buffer error.
- * TIMER_CSR3_EXPIRE: TIMECSR3 timer expired (802.1H quiet period).
- */
-#define CSR8                           0x0020
-#define CSR8_TBCN_EXPIRE               FIELD32(0x00000001)
-#define CSR8_TWAKE_EXPIRE              FIELD32(0x00000002)
-#define CSR8_TATIMW_EXPIRE             FIELD32(0x00000004)
-#define CSR8_TXDONE_TXRING             FIELD32(0x00000008)
-#define CSR8_TXDONE_ATIMRING           FIELD32(0x00000010)
-#define CSR8_TXDONE_PRIORING           FIELD32(0x00000020)
-#define CSR8_RXDONE                    FIELD32(0x00000040)
-#define CSR8_DECRYPTION_DONE           FIELD32(0x00000080)
-#define CSR8_ENCRYPTION_DONE           FIELD32(0x00000100)
-#define CSR8_UART1_TX_TRESHOLD         FIELD32(0x00000200)
-#define CSR8_UART1_RX_TRESHOLD         FIELD32(0x00000400)
-#define CSR8_UART1_IDLE_TRESHOLD       FIELD32(0x00000800)
-#define CSR8_UART1_TX_BUFF_ERROR       FIELD32(0x00001000)
-#define CSR8_UART1_RX_BUFF_ERROR       FIELD32(0x00002000)
-#define CSR8_UART2_TX_TRESHOLD         FIELD32(0x00004000)
-#define CSR8_UART2_RX_TRESHOLD         FIELD32(0x00008000)
-#define CSR8_UART2_IDLE_TRESHOLD       FIELD32(0x00010000)
-#define CSR8_UART2_TX_BUFF_ERROR       FIELD32(0x00020000)
-#define CSR8_UART2_RX_BUFF_ERROR       FIELD32(0x00040000)
-#define CSR8_TIMER_CSR3_EXPIRE         FIELD32(0x00080000)
-
-/*
- * CSR9: Maximum frame length register.
- * MAX_FRAME_UNIT: Maximum frame length in 128b unit, default: 12.
- */
-#define CSR9                           0x0024
-#define CSR9_MAX_FRAME_UNIT            FIELD32(0x00000f80)
-
-/*
- * SECCSR0: WEP control register.
- * KICK_DECRYPT: Kick decryption engine, self-clear.
- * ONE_SHOT: 0: ring mode, 1: One shot only mode.
- * DESC_ADDRESS: Descriptor physical address of frame.
- */
-#define SECCSR0                                0x0028
-#define SECCSR0_KICK_DECRYPT           FIELD32(0x00000001)
-#define SECCSR0_ONE_SHOT               FIELD32(0x00000002)
-#define SECCSR0_DESC_ADDRESS           FIELD32(0xfffffffc)
-
-/*
- * CSR11: Back-off control register.
- * CWMIN: CWmin. Default cwmin is 31 (2^5 - 1).
- * CWMAX: CWmax. Default cwmax is 1023 (2^10 - 1).
- * SLOT_TIME: Slot time, default is 20us for 802.11b
- * CW_SELECT: CWmin/CWmax selection, 1: Register, 0: TXD.
- * LONG_RETRY: Long retry count.
- * SHORT_RETRY: Short retry count.
- */
-#define CSR11                          0x002c
-#define CSR11_CWMIN                    FIELD32(0x0000000f)
-#define CSR11_CWMAX                    FIELD32(0x000000f0)
-#define CSR11_SLOT_TIME                        FIELD32(0x00001f00)
-#define CSR11_CW_SELECT                        FIELD32(0x00002000)
-#define CSR11_LONG_RETRY               FIELD32(0x00ff0000)
-#define CSR11_SHORT_RETRY              FIELD32(0xff000000)
-
-/*
- * CSR12: Synchronization configuration register 0.
- * All units in 1/16 TU.
- * BEACON_INTERVAL: Beacon interval, default is 100 TU.
- * CFP_MAX_DURATION: Cfp maximum duration, default is 100 TU.
- */
-#define CSR12                          0x0030
-#define CSR12_BEACON_INTERVAL          FIELD32(0x0000ffff)
-#define CSR12_CFP_MAX_DURATION         FIELD32(0xffff0000)
-
-/*
- * CSR13: Synchronization configuration register 1.
- * All units in 1/16 TU.
- * ATIMW_DURATION: Atim window duration.
- * CFP_PERIOD: Cfp period, default is 0 TU.
- */
-#define CSR13                          0x0034
-#define CSR13_ATIMW_DURATION           FIELD32(0x0000ffff)
-#define CSR13_CFP_PERIOD               FIELD32(0x00ff0000)
-
-/*
- * CSR14: Synchronization control register.
- * TSF_COUNT: Enable tsf auto counting.
- * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
- * TBCN: Enable tbcn with reload value.
- * TCFP: Enable tcfp & cfp / cp switching.
- * TATIMW: Enable tatimw & atim window switching.
- * BEACON_GEN: Enable beacon generator.
- * CFP_COUNT_PRELOAD: Cfp count preload value.
- * TBCM_PRELOAD: Tbcn preload value in units of 64us.
- */
-#define CSR14                          0x0038
-#define CSR14_TSF_COUNT                        FIELD32(0x00000001)
-#define CSR14_TSF_SYNC                 FIELD32(0x00000006)
-#define CSR14_TBCN                     FIELD32(0x00000008)
-#define CSR14_TCFP                     FIELD32(0x00000010)
-#define CSR14_TATIMW                   FIELD32(0x00000020)
-#define CSR14_BEACON_GEN               FIELD32(0x00000040)
-#define CSR14_CFP_COUNT_PRELOAD                FIELD32(0x0000ff00)
-#define CSR14_TBCM_PRELOAD             FIELD32(0xffff0000)
-
-/*
- * CSR15: Synchronization status register.
- * CFP: ASIC is in contention-free period.
- * ATIMW: ASIC is in ATIM window.
- * BEACON_SENT: Beacon is send.
- */
-#define CSR15                          0x003c
-#define CSR15_CFP                      FIELD32(0x00000001)
-#define CSR15_ATIMW                    FIELD32(0x00000002)
-#define CSR15_BEACON_SENT              FIELD32(0x00000004)
-
-/*
- * CSR16: TSF timer register 0.
- */
-#define CSR16                          0x0040
-#define CSR16_LOW_TSFTIMER             FIELD32(0xffffffff)
-
-/*
- * CSR17: TSF timer register 1.
- */
-#define CSR17                          0x0044
-#define CSR17_HIGH_TSFTIMER            FIELD32(0xffffffff)
-
-/*
- * CSR18: IFS timer register 0.
- * SIFS: Sifs, default is 10 us.
- * PIFS: Pifs, default is 30 us.
- */
-#define CSR18                          0x0048
-#define CSR18_SIFS                     FIELD32(0x000001ff)
-#define CSR18_PIFS                     FIELD32(0x001f0000)
-
-/*
- * CSR19: IFS timer register 1.
- * DIFS: Difs, default is 50 us.
- * EIFS: Eifs, default is 364 us.
- */
-#define CSR19                          0x004c
-#define CSR19_DIFS                     FIELD32(0x0000ffff)
-#define CSR19_EIFS                     FIELD32(0xffff0000)
-
-/*
- * CSR20: Wakeup timer register.
- * DELAY_AFTER_TBCN: Delay after tbcn expired in units of 1/16 TU.
- * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
- * AUTOWAKE: Enable auto wakeup / sleep mechanism.
- */
-#define CSR20                          0x0050
-#define CSR20_DELAY_AFTER_TBCN         FIELD32(0x0000ffff)
-#define CSR20_TBCN_BEFORE_WAKEUP       FIELD32(0x00ff0000)
-#define CSR20_AUTOWAKE                 FIELD32(0x01000000)
-
-/*
- * CSR21: EEPROM control register.
- * RELOAD: Write 1 to reload eeprom content.
- * TYPE_93C46: 1: 93c46, 0:93c66.
- */
-#define CSR21                          0x0054
-#define CSR21_RELOAD                   FIELD32(0x00000001)
-#define CSR21_EEPROM_DATA_CLOCK                FIELD32(0x00000002)
-#define CSR21_EEPROM_CHIP_SELECT       FIELD32(0x00000004)
-#define CSR21_EEPROM_DATA_IN           FIELD32(0x00000008)
-#define CSR21_EEPROM_DATA_OUT          FIELD32(0x00000010)
-#define CSR21_TYPE_93C46               FIELD32(0x00000020)
-
-/*
- * CSR22: CFP control register.
- * CFP_DURATION_REMAIN: Cfp duration remain, in units of TU.
- * RELOAD_CFP_DURATION: Write 1 to reload cfp duration remain.
- */
-#define CSR22                          0x0058
-#define CSR22_CFP_DURATION_REMAIN      FIELD32(0x0000ffff)
-#define CSR22_RELOAD_CFP_DURATION      FIELD32(0x00010000)
-
-/*
- * Transmit related CSRs.
- * Some values are set in TU, whereas 1 TU == 1024 us.
- */
-
-/*
- * TXCSR0: TX Control Register.
- * KICK_TX: Kick tx ring.
- * KICK_ATIM: Kick atim ring.
- * KICK_PRIO: Kick priority ring.
- * ABORT: Abort all transmit related ring operation.
- */
-#define TXCSR0                         0x0060
-#define TXCSR0_KICK_TX                 FIELD32(0x00000001)
-#define TXCSR0_KICK_ATIM               FIELD32(0x00000002)
-#define TXCSR0_KICK_PRIO               FIELD32(0x00000004)
-#define TXCSR0_ABORT                   FIELD32(0x00000008)
-
-/*
- * TXCSR1: TX Configuration Register.
- * ACK_TIMEOUT: Ack timeout, default = sifs + 2*slottime + acktime @ 1mbps.
- * ACK_CONSUME_TIME: Ack consume time, default = sifs + acktime @ 1mbps.
- * TSF_OFFSET: Insert tsf offset.
- * AUTORESPONDER: Enable auto responder which include ack & cts.
- */
-#define TXCSR1                         0x0064
-#define TXCSR1_ACK_TIMEOUT             FIELD32(0x000001ff)
-#define TXCSR1_ACK_CONSUME_TIME                FIELD32(0x0003fe00)
-#define TXCSR1_TSF_OFFSET              FIELD32(0x00fc0000)
-#define TXCSR1_AUTORESPONDER           FIELD32(0x01000000)
-
-/*
- * TXCSR2: Tx descriptor configuration register.
- * TXD_SIZE: Tx descriptor size, default is 48.
- * NUM_TXD: Number of tx entries in ring.
- * NUM_ATIM: Number of atim entries in ring.
- * NUM_PRIO: Number of priority entries in ring.
- */
-#define TXCSR2                         0x0068
-#define TXCSR2_TXD_SIZE                        FIELD32(0x000000ff)
-#define TXCSR2_NUM_TXD                 FIELD32(0x0000ff00)
-#define TXCSR2_NUM_ATIM                        FIELD32(0x00ff0000)
-#define TXCSR2_NUM_PRIO                        FIELD32(0xff000000)
-
-/*
- * TXCSR3: TX Ring Base address register.
- */
-#define TXCSR3                         0x006c
-#define TXCSR3_TX_RING_REGISTER                FIELD32(0xffffffff)
-
-/*
- * TXCSR4: TX Atim Ring Base address register.
- */
-#define TXCSR4                         0x0070
-#define TXCSR4_ATIM_RING_REGISTER      FIELD32(0xffffffff)
-
-/*
- * TXCSR5: TX Prio Ring Base address register.
- */
-#define TXCSR5                         0x0074
-#define TXCSR5_PRIO_RING_REGISTER      FIELD32(0xffffffff)
-
-/*
- * TXCSR6: Beacon Base address register.
- */
-#define TXCSR6                         0x0078
-#define TXCSR6_BEACON_RING_REGISTER    FIELD32(0xffffffff)
-
-/*
- * TXCSR7: Auto responder control register.
- * AR_POWERMANAGEMENT: Auto responder power management bit.
- */
-#define TXCSR7                         0x007c
-#define TXCSR7_AR_POWERMANAGEMENT      FIELD32(0x00000001)
-
-/*
- * TXCSR8: CCK Tx BBP register.
- */
-#define TXCSR8                         0x0098
-#define TXCSR8_BBP_ID0                 FIELD32(0x0000007f)
-#define TXCSR8_BBP_ID0_VALID           FIELD32(0x00000080)
-#define TXCSR8_BBP_ID1                 FIELD32(0x00007f00)
-#define TXCSR8_BBP_ID1_VALID           FIELD32(0x00008000)
-#define TXCSR8_BBP_ID2                 FIELD32(0x007f0000)
-#define TXCSR8_BBP_ID2_VALID           FIELD32(0x00800000)
-#define TXCSR8_BBP_ID3                 FIELD32(0x7f000000)
-#define TXCSR8_BBP_ID3_VALID           FIELD32(0x80000000)
-
-/*
- * TXCSR9: OFDM TX BBP registers
- * OFDM_SIGNAL: BBP rate field address for OFDM.
- * OFDM_SERVICE: BBP service field address for OFDM.
- * OFDM_LENGTH_LOW: BBP length low byte address for OFDM.
- * OFDM_LENGTH_HIGH: BBP length high byte address for OFDM.
- */
-#define TXCSR9                         0x0094
-#define TXCSR9_OFDM_RATE               FIELD32(0x000000ff)
-#define TXCSR9_OFDM_SERVICE            FIELD32(0x0000ff00)
-#define TXCSR9_OFDM_LENGTH_LOW         FIELD32(0x00ff0000)
-#define TXCSR9_OFDM_LENGTH_HIGH                FIELD32(0xff000000)
-
-/*
- * Receive related CSRs.
- * Some values are set in TU, whereas 1 TU == 1024 us.
- */
-
-/*
- * RXCSR0: RX Control Register.
- * DISABLE_RX: Disable rx engine.
- * DROP_CRC: Drop crc error.
- * DROP_PHYSICAL: Drop physical error.
- * DROP_CONTROL: Drop control frame.
- * DROP_NOT_TO_ME: Drop not to me unicast frame.
- * DROP_TODS: Drop frame tods bit is true.
- * DROP_VERSION_ERROR: Drop version error frame.
- * PASS_CRC: Pass all packets with crc attached.
- * PASS_CRC: Pass all packets with crc attached.
- * PASS_PLCP: Pass all packets with 4 bytes PLCP attached.
- * DROP_MCAST: Drop multicast frames.
- * DROP_BCAST: Drop broadcast frames.
- * ENABLE_QOS: Accept QOS data frame and parse QOS field.
- */
-#define RXCSR0                         0x0080
-#define RXCSR0_DISABLE_RX              FIELD32(0x00000001)
-#define RXCSR0_DROP_CRC                        FIELD32(0x00000002)
-#define RXCSR0_DROP_PHYSICAL           FIELD32(0x00000004)
-#define RXCSR0_DROP_CONTROL            FIELD32(0x00000008)
-#define RXCSR0_DROP_NOT_TO_ME          FIELD32(0x00000010)
-#define RXCSR0_DROP_TODS               FIELD32(0x00000020)
-#define RXCSR0_DROP_VERSION_ERROR      FIELD32(0x00000040)
-#define RXCSR0_PASS_CRC                        FIELD32(0x00000080)
-#define RXCSR0_PASS_PLCP               FIELD32(0x00000100)
-#define RXCSR0_DROP_MCAST              FIELD32(0x00000200)
-#define RXCSR0_DROP_BCAST              FIELD32(0x00000400)
-#define RXCSR0_ENABLE_QOS              FIELD32(0x00000800)
-
-/*
- * RXCSR1: RX descriptor configuration register.
- * RXD_SIZE: Rx descriptor size, default is 32b.
- * NUM_RXD: Number of rx entries in ring.
- */
-#define RXCSR1                         0x0084
-#define RXCSR1_RXD_SIZE                        FIELD32(0x000000ff)
-#define RXCSR1_NUM_RXD                 FIELD32(0x0000ff00)
-
-/*
- * RXCSR2: RX Ring base address register.
- */
-#define RXCSR2                         0x0088
-#define RXCSR2_RX_RING_REGISTER                FIELD32(0xffffffff)
-
-/*
- * RXCSR3: BBP ID register for Rx operation.
- * BBP_ID#: BBP register # id.
- * BBP_ID#_VALID: BBP register # id is valid or not.
- */
-#define RXCSR3                         0x0090
-#define RXCSR3_BBP_ID0                 FIELD32(0x0000007f)
-#define RXCSR3_BBP_ID0_VALID           FIELD32(0x00000080)
-#define RXCSR3_BBP_ID1                 FIELD32(0x00007f00)
-#define RXCSR3_BBP_ID1_VALID           FIELD32(0x00008000)
-#define RXCSR3_BBP_ID2                 FIELD32(0x007f0000)
-#define RXCSR3_BBP_ID2_VALID           FIELD32(0x00800000)
-#define RXCSR3_BBP_ID3                 FIELD32(0x7f000000)
-#define RXCSR3_BBP_ID3_VALID           FIELD32(0x80000000)
-
-/*
- * ARCSR1: Auto Responder PLCP config register 1.
- * AR_BBP_DATA#: Auto responder BBP register # data.
- * AR_BBP_ID#: Auto responder BBP register # Id.
- */
-#define ARCSR1                         0x009c
-#define ARCSR1_AR_BBP_DATA2            FIELD32(0x000000ff)
-#define ARCSR1_AR_BBP_ID2              FIELD32(0x0000ff00)
-#define ARCSR1_AR_BBP_DATA3            FIELD32(0x00ff0000)
-#define ARCSR1_AR_BBP_ID3              FIELD32(0xff000000)
-
-/*
- * Miscellaneous Registers.
- * Some values are set in TU, whereas 1 TU == 1024 us.
-
- */
-
-/*
- * PCICSR: PCI control register.
- * BIG_ENDIAN: 1: big endian, 0: little endian.
- * RX_TRESHOLD: Rx threshold in dw to start pci access
- * 0: 16dw (default), 1: 8dw, 2: 4dw, 3: 32dw.
- * TX_TRESHOLD: Tx threshold in dw to start pci access
- * 0: 0dw (default), 1: 1dw, 2: 4dw, 3: forward.
- * BURST_LENTH: Pci burst length 0: 4dw (default, 1: 8dw, 2: 16dw, 3:32dw.
- * ENABLE_CLK: Enable clk_run, pci clock can't going down to non-operational.
- * READ_MULTIPLE: Enable memory read multiple.
- * WRITE_INVALID: Enable memory write & invalid.
- */
-#define PCICSR                         0x008c
-#define PCICSR_BIG_ENDIAN              FIELD32(0x00000001)
-#define PCICSR_RX_TRESHOLD             FIELD32(0x00000006)
-#define PCICSR_TX_TRESHOLD             FIELD32(0x00000018)
-#define PCICSR_BURST_LENTH             FIELD32(0x00000060)
-#define PCICSR_ENABLE_CLK              FIELD32(0x00000080)
-#define PCICSR_READ_MULTIPLE           FIELD32(0x00000100)
-#define PCICSR_WRITE_INVALID           FIELD32(0x00000200)
-
-/*
- * CNT0: FCS error count.
- * FCS_ERROR: FCS error count, cleared when read.
- */
-#define CNT0                           0x00a0
-#define CNT0_FCS_ERROR                 FIELD32(0x0000ffff)
-
-/*
- * Statistic Register.
- * CNT1: PLCP error count.
- * CNT2: Long error count.
- */
-#define TIMECSR2                       0x00a8
-#define CNT1                           0x00ac
-#define CNT2                           0x00b0
-#define TIMECSR3                       0x00b4
-
-/*
- * CNT3: CCA false alarm count.
- */
-#define CNT3                           0x00b8
-#define CNT3_FALSE_CCA                 FIELD32(0x0000ffff)
-
-/*
- * Statistic Register.
- * CNT4: Rx FIFO overflow count.
- * CNT5: Tx FIFO underrun count.
- */
-#define CNT4                           0x00bc
-#define CNT5                           0x00c0
-
-/*
- * Baseband Control Register.
- */
-
-/*
- * PWRCSR0: Power mode configuration register.
- */
-#define PWRCSR0                                0x00c4
-
-/*
- * Power state transition time registers.
- */
-#define PSCSR0                         0x00c8
-#define PSCSR1                         0x00cc
-#define PSCSR2                         0x00d0
-#define PSCSR3                         0x00d4
-
-/*
- * PWRCSR1: Manual power control / status register.
- * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
- * SET_STATE: Set state. Write 1 to trigger, self cleared.
- * BBP_DESIRE_STATE: BBP desired state.
- * RF_DESIRE_STATE: RF desired state.
- * BBP_CURR_STATE: BBP current state.
- * RF_CURR_STATE: RF current state.
- * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared.
- */
-#define PWRCSR1                                0x00d8
-#define PWRCSR1_SET_STATE              FIELD32(0x00000001)
-#define PWRCSR1_BBP_DESIRE_STATE       FIELD32(0x00000006)
-#define PWRCSR1_RF_DESIRE_STATE                FIELD32(0x00000018)
-#define PWRCSR1_BBP_CURR_STATE         FIELD32(0x00000060)
-#define PWRCSR1_RF_CURR_STATE          FIELD32(0x00000180)
-#define PWRCSR1_PUT_TO_SLEEP           FIELD32(0x00000200)
-
-/*
- * TIMECSR: Timer control register.
- * US_COUNT: 1 us timer count in units of clock cycles.
- * US_64_COUNT: 64 us timer count in units of 1 us timer.
- * BEACON_EXPECT: Beacon expect window.
- */
-#define TIMECSR                                0x00dc
-#define TIMECSR_US_COUNT               FIELD32(0x000000ff)
-#define TIMECSR_US_64_COUNT            FIELD32(0x0000ff00)
-#define TIMECSR_BEACON_EXPECT          FIELD32(0x00070000)
-
-/*
- * MACCSR0: MAC configuration register 0.
- */
-#define MACCSR0                                0x00e0
-
-/*
- * MACCSR1: MAC configuration register 1.
- * KICK_RX: Kick one-shot rx in one-shot rx mode.
- * ONESHOT_RXMODE: Enable one-shot rx mode for debugging.
- * BBPRX_RESET_MODE: Ralink bbp rx reset mode.
- * AUTO_TXBBP: Auto tx logic access bbp control register.
- * AUTO_RXBBP: Auto rx logic access bbp control register.
- * LOOPBACK: Loopback mode. 0: normal, 1: internal, 2: external, 3:rsvd.
- * INTERSIL_IF: Intersil if calibration pin.
- */
-#define MACCSR1                                0x00e4
-#define MACCSR1_KICK_RX                        FIELD32(0x00000001)
-#define MACCSR1_ONESHOT_RXMODE         FIELD32(0x00000002)
-#define MACCSR1_BBPRX_RESET_MODE       FIELD32(0x00000004)
-#define MACCSR1_AUTO_TXBBP             FIELD32(0x00000008)
-#define MACCSR1_AUTO_RXBBP             FIELD32(0x00000010)
-#define MACCSR1_LOOPBACK               FIELD32(0x00000060)
-#define MACCSR1_INTERSIL_IF            FIELD32(0x00000080)
-
-/*
- * RALINKCSR: Ralink Rx auto-reset BBCR.
- * AR_BBP_DATA#: Auto reset BBP register # data.
- * AR_BBP_ID#: Auto reset BBP register # id.
- */
-#define RALINKCSR                      0x00e8
-#define RALINKCSR_AR_BBP_DATA0         FIELD32(0x000000ff)
-#define RALINKCSR_AR_BBP_ID0           FIELD32(0x00007f00)
-#define RALINKCSR_AR_BBP_VALID0                FIELD32(0x00008000)
-#define RALINKCSR_AR_BBP_DATA1         FIELD32(0x00ff0000)
-#define RALINKCSR_AR_BBP_ID1           FIELD32(0x7f000000)
-#define RALINKCSR_AR_BBP_VALID1                FIELD32(0x80000000)
-
-/*
- * BCNCSR: Beacon interval control register.
- * CHANGE: Write one to change beacon interval.
- * DELTATIME: The delta time value.
- * NUM_BEACON: Number of beacon according to mode.
- * MODE: Please refer to asic specs.
- * PLUS: Plus or minus delta time value.
- */
-#define BCNCSR                         0x00ec
-#define BCNCSR_CHANGE                  FIELD32(0x00000001)
-#define BCNCSR_DELTATIME               FIELD32(0x0000001e)
-#define BCNCSR_NUM_BEACON              FIELD32(0x00001fe0)
-#define BCNCSR_MODE                    FIELD32(0x00006000)
-#define BCNCSR_PLUS                    FIELD32(0x00008000)
-
-/*
- * BBP / RF / IF Control Register.
- */
-
-/*
- * BBPCSR: BBP serial control register.
- * VALUE: Register value to program into BBP.
- * REGNUM: Selected BBP register.
- * BUSY: 1: asic is busy execute BBP programming.
- * WRITE_CONTROL: 1: write BBP, 0: read BBP.
- */
-#define BBPCSR                         0x00f0
-#define BBPCSR_VALUE                   FIELD32(0x000000ff)
-#define BBPCSR_REGNUM                  FIELD32(0x00007f00)
-#define BBPCSR_BUSY                    FIELD32(0x00008000)
-#define BBPCSR_WRITE_CONTROL           FIELD32(0x00010000)
-
-/*
- * RFCSR: RF serial control register.
- * VALUE: Register value + id to program into rf/if.
- * NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22).
- * IF_SELECT: Chip to program: 0: rf, 1: if.
- * PLL_LD: Rf pll_ld status.
- * BUSY: 1: asic is busy execute rf programming.
- */
-#define RFCSR                          0x00f4
-#define RFCSR_VALUE                    FIELD32(0x00ffffff)
-#define RFCSR_NUMBER_OF_BITS           FIELD32(0x1f000000)
-#define RFCSR_IF_SELECT                        FIELD32(0x20000000)
-#define RFCSR_PLL_LD                   FIELD32(0x40000000)
-#define RFCSR_BUSY                     FIELD32(0x80000000)
-
-/*
- * LEDCSR: LED control register.
- * ON_PERIOD: On period, default 70ms.
- * OFF_PERIOD: Off period, default 30ms.
- * LINK: 0: linkoff, 1: linkup.
- * ACTIVITY: 0: idle, 1: active.
- * LINK_POLARITY: 0: active low, 1: active high.
- * ACTIVITY_POLARITY: 0: active low, 1: active high.
- * LED_DEFAULT: LED state for "enable" 0: ON, 1: OFF.
- */
-#define LEDCSR                         0x00f8
-#define LEDCSR_ON_PERIOD               FIELD32(0x000000ff)
-#define LEDCSR_OFF_PERIOD              FIELD32(0x0000ff00)
-#define LEDCSR_LINK                    FIELD32(0x00010000)
-#define LEDCSR_ACTIVITY                        FIELD32(0x00020000)
-#define LEDCSR_LINK_POLARITY           FIELD32(0x00040000)
-#define LEDCSR_ACTIVITY_POLARITY       FIELD32(0x00080000)
-#define LEDCSR_LED_DEFAULT             FIELD32(0x00100000)
-
-/*
- * AES control register.
- */
-#define SECCSR3                                0x00fc
-
-/*
- * ASIC pointer information.
- * RXPTR: Current RX ring address.
- * TXPTR: Current Tx ring address.
- * PRIPTR: Current Priority ring address.
- * ATIMPTR: Current ATIM ring address.
- */
-#define RXPTR                          0x0100
-#define TXPTR                          0x0104
-#define PRIPTR                         0x0108
-#define ATIMPTR                                0x010c
-
-/*
- * TXACKCSR0: TX ACK timeout.
- */
-#define TXACKCSR0                      0x0110
-
-/*
- * ACK timeout count registers.
- * ACKCNT0: TX ACK timeout count.
- * ACKCNT1: RX ACK timeout count.
- */
-#define ACKCNT0                                0x0114
-#define ACKCNT1                                0x0118
-
-/*
- * GPIO and others.
- */
-
-/*
- * GPIOCSR: GPIO control register.
- */
-#define GPIOCSR                                0x0120
-#define GPIOCSR_BIT0                   FIELD32(0x00000001)
-#define GPIOCSR_BIT1                   FIELD32(0x00000002)
-#define GPIOCSR_BIT2                   FIELD32(0x00000004)
-#define GPIOCSR_BIT3                   FIELD32(0x00000008)
-#define GPIOCSR_BIT4                   FIELD32(0x00000010)
-#define GPIOCSR_BIT5                   FIELD32(0x00000020)
-#define GPIOCSR_BIT6                   FIELD32(0x00000040)
-#define GPIOCSR_BIT7                   FIELD32(0x00000080)
-#define GPIOCSR_DIR0                   FIELD32(0x00000100)
-#define GPIOCSR_DIR1                   FIELD32(0x00000200)
-#define GPIOCSR_DIR2                   FIELD32(0x00000400)
-#define GPIOCSR_DIR3                   FIELD32(0x00000800)
-#define GPIOCSR_DIR4                   FIELD32(0x00001000)
-#define GPIOCSR_DIR5                   FIELD32(0x00002000)
-#define GPIOCSR_DIR6                   FIELD32(0x00004000)
-#define GPIOCSR_DIR7                   FIELD32(0x00008000)
-
-/*
- * FIFO pointer registers.
- * FIFOCSR0: TX FIFO pointer.
- * FIFOCSR1: RX FIFO pointer.
- */
-#define FIFOCSR0                       0x0128
-#define FIFOCSR1                       0x012c
-
-/*
- * BCNCSR1: Tx BEACON offset time control register.
- * PRELOAD: Beacon timer offset in units of usec.
- * BEACON_CWMIN: 2^CwMin.
- */
-#define BCNCSR1                                0x0130
-#define BCNCSR1_PRELOAD                        FIELD32(0x0000ffff)
-#define BCNCSR1_BEACON_CWMIN           FIELD32(0x000f0000)
-
-/*
- * MACCSR2: TX_PE to RX_PE turn-around time control register
- * DELAY: RX_PE low width, in units of pci clock cycle.
- */
-#define MACCSR2                                0x0134
-#define MACCSR2_DELAY                  FIELD32(0x000000ff)
-
-/*
- * TESTCSR: TEST mode selection register.
- */
-#define TESTCSR                                0x0138
-
-/*
- * ARCSR2: 1 Mbps ACK/CTS PLCP.
- */
-#define ARCSR2                         0x013c
-#define ARCSR2_SIGNAL                  FIELD32(0x000000ff)
-#define ARCSR2_SERVICE                 FIELD32(0x0000ff00)
-#define ARCSR2_LENGTH                  FIELD32(0xffff0000)
-
-/*
- * ARCSR3: 2 Mbps ACK/CTS PLCP.
- */
-#define ARCSR3                         0x0140
-#define ARCSR3_SIGNAL                  FIELD32(0x000000ff)
-#define ARCSR3_SERVICE                 FIELD32(0x0000ff00)
-#define ARCSR3_LENGTH                  FIELD32(0xffff0000)
-
-/*
- * ARCSR4: 5.5 Mbps ACK/CTS PLCP.
- */
-#define ARCSR4                         0x0144
-#define ARCSR4_SIGNAL                  FIELD32(0x000000ff)
-#define ARCSR4_SERVICE                 FIELD32(0x0000ff00)
-#define ARCSR4_LENGTH                  FIELD32(0xffff0000)
-
-/*
- * ARCSR5: 11 Mbps ACK/CTS PLCP.
- */
-#define ARCSR5                         0x0148
-#define ARCSR5_SIGNAL                  FIELD32(0x000000ff)
-#define ARCSR5_SERVICE                 FIELD32(0x0000ff00)
-#define ARCSR5_LENGTH                  FIELD32(0xffff0000)
-
-/*
- * ARTCSR0: CCK ACK/CTS payload consumed time for 1/2/5.5/11 mbps.
- */
-#define ARTCSR0                                0x014c
-#define ARTCSR0_ACK_CTS_11MBS          FIELD32(0x000000ff)
-#define ARTCSR0_ACK_CTS_5_5MBS         FIELD32(0x0000ff00)
-#define ARTCSR0_ACK_CTS_2MBS           FIELD32(0x00ff0000)
-#define ARTCSR0_ACK_CTS_1MBS           FIELD32(0xff000000)
-
-
-/*
- * ARTCSR1: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps.
- */
-#define ARTCSR1                                0x0150
-#define ARTCSR1_ACK_CTS_6MBS           FIELD32(0x000000ff)
-#define ARTCSR1_ACK_CTS_9MBS           FIELD32(0x0000ff00)
-#define ARTCSR1_ACK_CTS_12MBS          FIELD32(0x00ff0000)
-#define ARTCSR1_ACK_CTS_18MBS          FIELD32(0xff000000)
-
-/*
- * ARTCSR2: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps.
- */
-#define ARTCSR2                                0x0154
-#define ARTCSR2_ACK_CTS_24MBS          FIELD32(0x000000ff)
-#define ARTCSR2_ACK_CTS_36MBS          FIELD32(0x0000ff00)
-#define ARTCSR2_ACK_CTS_48MBS          FIELD32(0x00ff0000)
-#define ARTCSR2_ACK_CTS_54MBS          FIELD32(0xff000000)
-
-/*
- * SECCSR1_RT2509: WEP control register.
- * KICK_ENCRYPT: Kick encryption engine, self-clear.
- * ONE_SHOT: 0: ring mode, 1: One shot only mode.
- * DESC_ADDRESS: Descriptor physical address of frame.
- */
-#define SECCSR1                                0x0158
-#define SECCSR1_KICK_ENCRYPT           FIELD32(0x00000001)
-#define SECCSR1_ONE_SHOT               FIELD32(0x00000002)
-#define SECCSR1_DESC_ADDRESS           FIELD32(0xfffffffc)
-
-/*
- * BBPCSR1: BBP TX configuration.
- */
-#define BBPCSR1                                0x015c
-#define BBPCSR1_CCK                    FIELD32(0x00000003)
-#define BBPCSR1_CCK_FLIP               FIELD32(0x00000004)
-#define BBPCSR1_OFDM                   FIELD32(0x00030000)
-#define BBPCSR1_OFDM_FLIP              FIELD32(0x00040000)
-
-/*
- * Dual band configuration registers.
- * DBANDCSR0: Dual band configuration register 0.
- * DBANDCSR1: Dual band configuration register 1.
- */
-#define DBANDCSR0                      0x0160
-#define DBANDCSR1                      0x0164
-
-/*
- * BBPPCSR: BBP Pin control register.
- */
-#define BBPPCSR                                0x0168
-
-/*
- * MAC special debug mode selection registers.
- * DBGSEL0: MAC special debug mode selection register 0.
- * DBGSEL1: MAC special debug mode selection register 1.
- */
-#define DBGSEL0                                0x016c
-#define DBGSEL1                                0x0170
-
-/*
- * BISTCSR: BBP BIST register.
- */
-#define BISTCSR                                0x0174
-
-/*
- * Multicast filter registers.
- * MCAST0: Multicast filter register 0.
- * MCAST1: Multicast filter register 1.
- */
-#define MCAST0                         0x0178
-#define MCAST1                         0x017c
-
-/*
- * UART registers.
- * UARTCSR0: UART1 TX register.
- * UARTCSR1: UART1 RX register.
- * UARTCSR3: UART1 frame control register.
- * UARTCSR4: UART1 buffer control register.
- * UART2CSR0: UART2 TX register.
- * UART2CSR1: UART2 RX register.
- * UART2CSR3: UART2 frame control register.
- * UART2CSR4: UART2 buffer control register.
- */
-#define UARTCSR0                       0x0180
-#define UARTCSR1                       0x0184
-#define UARTCSR3                       0x0188
-#define UARTCSR4                       0x018c
-#define UART2CSR0                      0x0190
-#define UART2CSR1                      0x0194
-#define UART2CSR3                      0x0198
-#define UART2CSR4                      0x019c
-
-/*
- * BBP registers.
- * The wordsize of the BBP is 8 bits.
- */
-
-/*
- * R2: TX antenna control
- */
-#define BBP_R2_TX_ANTENNA              FIELD8(0x03)
-#define BBP_R2_TX_IQ_FLIP              FIELD8(0x04)
-
-/*
- * R14: RX antenna control
- */
-#define BBP_R14_RX_ANTENNA             FIELD8(0x03)
-#define BBP_R14_RX_IQ_FLIP             FIELD8(0x04)
-
-/*
- * BBP_R70
- */
-#define BBP_R70_JAPAN_FILTER           FIELD8(0x08)
-
-/*
- * RF registers
- */
-
-/*
- * RF 1
- */
-#define RF1_TUNER                      FIELD32(0x00020000)
-
-/*
- * RF 3
- */
-#define RF3_TUNER                      FIELD32(0x00000100)
-#define RF3_TXPOWER                    FIELD32(0x00003e00)
-
-/*
- * EEPROM content.
- * The wordsize of the EEPROM is 16 bits.
- */
-
-/*
- * HW MAC address.
- */
-#define EEPROM_MAC_ADDR_0              0x0002
-#define EEPROM_MAC_ADDR_BYTE0          FIELD16(0x00ff)
-#define EEPROM_MAC_ADDR_BYTE1          FIELD16(0xff00)
-#define EEPROM_MAC_ADDR1               0x0003
-#define EEPROM_MAC_ADDR_BYTE2          FIELD16(0x00ff)
-#define EEPROM_MAC_ADDR_BYTE3          FIELD16(0xff00)
-#define EEPROM_MAC_ADDR_2              0x0004
-#define EEPROM_MAC_ADDR_BYTE4          FIELD16(0x00ff)
-#define EEPROM_MAC_ADDR_BYTE5          FIELD16(0xff00)
-
-/*
- * EEPROM antenna.
- * ANTENNA_NUM: Number of antenna's.
- * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
- * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
- * LED_MODE: 0: default, 1: TX/RX activity,2: Single (ignore link), 3: rsvd.
- * DYN_TXAGC: Dynamic TX AGC control.
- * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
- * RF_TYPE: Rf_type of this adapter.
- */
-#define EEPROM_ANTENNA                 0x10
-#define EEPROM_ANTENNA_NUM             FIELD16(0x0003)
-#define EEPROM_ANTENNA_TX_DEFAULT      FIELD16(0x000c)
-#define EEPROM_ANTENNA_RX_DEFAULT      FIELD16(0x0030)
-#define EEPROM_ANTENNA_LED_MODE                FIELD16(0x01c0)
-#define EEPROM_ANTENNA_DYN_TXAGC       FIELD16(0x0200)
-#define EEPROM_ANTENNA_HARDWARE_RADIO  FIELD16(0x0400)
-#define EEPROM_ANTENNA_RF_TYPE         FIELD16(0xf800)
-
-/*
- * EEPROM NIC config.
- * CARDBUS_ACCEL: 0: enable, 1: disable.
- * DYN_BBP_TUNE: 0: enable, 1: disable.
- * CCK_TX_POWER: CCK TX power compensation.
- */
-#define EEPROM_NIC                     0x11
-#define EEPROM_NIC_CARDBUS_ACCEL       FIELD16(0x0001)
-#define EEPROM_NIC_DYN_BBP_TUNE                FIELD16(0x0002)
-#define EEPROM_NIC_CCK_TX_POWER                FIELD16(0x000c)
-
-/*
- * EEPROM geography.
- * GEO: Default geography setting for device.
- */
-#define EEPROM_GEOGRAPHY               0x12
-#define EEPROM_GEOGRAPHY_GEO           FIELD16(0x0f00)
-
-/*
- * EEPROM BBP.
- */
-#define EEPROM_BBP_START               0x13
-#define EEPROM_BBP_SIZE                        16
-#define EEPROM_BBP_VALUE               FIELD16(0x00ff)
-#define EEPROM_BBP_REG_ID              FIELD16(0xff00)
-
-/*
- * EEPROM TXPOWER
- */
-#define EEPROM_TXPOWER_START           0x23
-#define EEPROM_TXPOWER_SIZE            7
-#define EEPROM_TXPOWER_1               FIELD16(0x00ff)
-#define EEPROM_TXPOWER_2               FIELD16(0xff00)
-
-/*
- * RSSI <-> dBm offset calibration
- */
-#define EEPROM_CALIBRATE_OFFSET                0x3e
-#define EEPROM_CALIBRATE_OFFSET_RSSI   FIELD16(0x00ff)
-
-/*
- * DMA descriptor defines.
- */
-#define TXD_DESC_SIZE                  ( 11 * sizeof(struct data_desc) )
-#define RXD_DESC_SIZE                  ( 11 * sizeof(struct data_desc) )
-
-/*
- * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
- */
-
-/*
- * Word0
- */
-#define TXD_W0_OWNER_NIC               FIELD32(0x00000001)
-#define TXD_W0_VALID                   FIELD32(0x00000002)
-#define TXD_W0_RESULT                  FIELD32(0x0000001c)
-#define TXD_W0_RETRY_COUNT             FIELD32(0x000000e0)
-#define TXD_W0_MORE_FRAG               FIELD32(0x00000100)
-#define TXD_W0_ACK                     FIELD32(0x00000200)
-#define TXD_W0_TIMESTAMP               FIELD32(0x00000400)
-#define TXD_W0_OFDM                    FIELD32(0x00000800)
-#define TXD_W0_CIPHER_OWNER            FIELD32(0x00001000)
-#define TXD_W0_IFS                     FIELD32(0x00006000)
-#define TXD_W0_RETRY_MODE              FIELD32(0x00008000)
-#define TXD_W0_DATABYTE_COUNT          FIELD32(0x0fff0000)
-#define TXD_W0_CIPHER_ALG              FIELD32(0xe0000000)
-
-/*
- * Word1
- */
-#define TXD_W1_BUFFER_ADDRESS          FIELD32(0xffffffff)
-
-/*
- * Word2
- */
-#define TXD_W2_IV_OFFSET               FIELD32(0x0000003f)
-#define TXD_W2_AIFS                    FIELD32(0x000000c0)
-#define TXD_W2_CWMIN                   FIELD32(0x00000f00)
-#define TXD_W2_CWMAX                   FIELD32(0x0000f000)
-
-/*
- * Word3: PLCP information
- */
-#define TXD_W3_PLCP_SIGNAL             FIELD32(0x000000ff)
-#define TXD_W3_PLCP_SERVICE            FIELD32(0x0000ff00)
-#define TXD_W3_PLCP_LENGTH_LOW         FIELD32(0x00ff0000)
-#define TXD_W3_PLCP_LENGTH_HIGH                FIELD32(0xff000000)
-
-/*
- * Word4
- */
-#define TXD_W4_IV                      FIELD32(0xffffffff)
-
-/*
- * Word5
- */
-#define TXD_W5_EIV                     FIELD32(0xffffffff)
-
-/*
- * Word6-9: Key
- */
-#define TXD_W6_KEY                     FIELD32(0xffffffff)
-#define TXD_W7_KEY                     FIELD32(0xffffffff)
-#define TXD_W8_KEY                     FIELD32(0xffffffff)
-#define TXD_W9_KEY                     FIELD32(0xffffffff)
-
-/*
- * Word10
- */
-#define TXD_W10_RTS                    FIELD32(0x00000001)
-#define TXD_W10_TX_RATE                        FIELD32(0x000000fe)
-
-/*
- * RX descriptor format for RX Ring.
- */
-
-/*
- * Word0
- */
-#define RXD_W0_OWNER_NIC               FIELD32(0x00000001)
-#define RXD_W0_UNICAST_TO_ME           FIELD32(0x00000002)
-#define RXD_W0_MULTICAST               FIELD32(0x00000004)
-#define RXD_W0_BROADCAST               FIELD32(0x00000008)
-#define RXD_W0_MY_BSS                  FIELD32(0x00000010)
-#define RXD_W0_CRC_ERROR               FIELD32(0x00000020)
-#define RXD_W0_OFDM                    FIELD32(0x00000040)
-#define RXD_W0_PHYSICAL_ERROR          FIELD32(0x00000080)
-#define RXD_W0_CIPHER_OWNER            FIELD32(0x00000100)
-#define RXD_W0_ICV_ERROR               FIELD32(0x00000200)
-#define RXD_W0_IV_OFFSET               FIELD32(0x0000fc00)
-#define RXD_W0_DATABYTE_COUNT          FIELD32(0x0fff0000)
-#define RXD_W0_CIPHER_ALG              FIELD32(0xe0000000)
-
-/*
- * Word1
- */
-#define RXD_W1_BUFFER_ADDRESS          FIELD32(0xffffffff)
-
-/*
- * Word2
- */
-#define RXD_W2_SIGNAL                  FIELD32(0x000000ff)
-#define RXD_W2_RSSI                    FIELD32(0x0000ff00)
-#define RXD_W2_TA                      FIELD32(0xffff0000)
-
-/*
- * Word3
- */
-#define RXD_W3_TA                      FIELD32(0xffffffff)
-
-/*
- * Word4
- */
-#define RXD_W4_IV                      FIELD32(0xffffffff)
-
-/*
- * Word5
- */
-#define RXD_W5_EIV                     FIELD32(0xffffffff)
-
-/*
- * Word6-9: Key
- */
-#define RXD_W6_KEY                     FIELD32(0xffffffff)
-#define RXD_W7_KEY                     FIELD32(0xffffffff)
-#define RXD_W8_KEY                     FIELD32(0xffffffff)
-#define RXD_W9_KEY                     FIELD32(0xffffffff)
-
-/*
- * Word10
- */
-#define RXD_W10_DROP                   FIELD32(0x00000001)
-
-/*
- * Macro's for converting txpower from EEPROM to dscape value
- * and from dscape value to register value.
- */
-#define MIN_TXPOWER    0
-#define MAX_TXPOWER    31
-#define DEFAULT_TXPOWER        24
-
-#define TXPOWER_FROM_DEV(__txpower)            \
-({                                             \
-       ((__txpower) > MAX_TXPOWER) ?           \
-               DEFAULT_TXPOWER : (__txpower);  \
-})
-
-#define TXPOWER_TO_DEV(__txpower)                      \
-({                                                     \
-       ((__txpower) <= MIN_TXPOWER) ? MIN_TXPOWER :    \
-       (((__txpower) >= MAX_TXPOWER) ? MAX_TXPOWER :   \
-       (__txpower));                                   \
-})
-
-#endif /* RT2500PCI_H */
diff --git a/package/rt2x00/src/rt2500usb.c b/package/rt2x00/src/rt2500usb.c
deleted file mode 100644 (file)
index 18b1f91..0000000
+++ /dev/null
@@ -1,1831 +0,0 @@
-/*
-       Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
-       <http://rt2x00.serialmonkey.com>
-
-       This program is free software; you can redistribute it and/or modify
-       it under the terms of the GNU General Public License as published by
-       the Free Software Foundation; either version 2 of the License, or
-       (at your option) any later version.
-
-       This program is distributed in the hope that it will be useful,
-       but WITHOUT ANY WARRANTY; without even the implied warranty of
-       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-       GNU General Public License for more details.
-
-       You should have received a copy of the GNU General Public License
-       along with this program; if not, write to the
-       Free Software Foundation, Inc.,
-       59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-/*
-       Module: rt2500usb
-       Abstract: rt2500usb device specific routines.
-       Supported chipsets: RT2570.
- */
-
-/*
- * Set enviroment defines for rt2x00.h
- */
-#define DRV_NAME "rt2500usb"
-
-#include <linux/delay.h>
-#include <linux/etherdevice.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/usb.h>
-
-#include "rt2x00.h"
-#include "rt2x00usb.h"
-#include "rt2500usb.h"
-
-/*
- * Register access.
- * All access to the CSR registers will go through the methods
- * rt2500usb_register_read and rt2500usb_register_write.
- * BBP and RF register require indirect register access,
- * and use the CSR registers BBPCSR and RFCSR to achieve this.
- * These indirect registers work with busy bits,
- * and we will try maximal REGISTER_BUSY_COUNT times to access
- * the register while taking a REGISTER_BUSY_DELAY us delay
- * between each attampt. When the busy bit is still set at that time,
- * the access attempt is considered to have failed,
- * and we will print an error.
- */
-static inline void rt2500usb_register_read(const struct rt2x00_dev *rt2x00dev,
-                                          const unsigned int offset,
-                                          u16 *value)
-{
-       __le16 reg;
-       rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
-                                     USB_VENDOR_REQUEST_IN, offset,
-                                     &reg, sizeof(u16), REGISTER_TIMEOUT);
-       *value = le16_to_cpu(reg);
-}
-
-static inline void rt2500usb_register_multiread(const struct rt2x00_dev
-                                               *rt2x00dev,
-                                               const unsigned int offset,
-                                               void *value, const u16 length)
-{
-       int timeout = REGISTER_TIMEOUT * (length / sizeof(u16));
-       rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
-                                     USB_VENDOR_REQUEST_IN, offset,
-                                     value, length, timeout);
-}
-
-static inline void rt2500usb_register_write(const struct rt2x00_dev *rt2x00dev,
-                                           const unsigned int offset,
-                                           u16 value)
-{
-       __le16 reg = cpu_to_le16(value);
-       rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
-                                     USB_VENDOR_REQUEST_OUT, offset,
-                                     &reg, sizeof(u16), REGISTER_TIMEOUT);
-}
-
-static inline void rt2500usb_register_multiwrite(const struct rt2x00_dev
-                                                *rt2x00dev,
-                                                const unsigned int offset,
-                                                void *value, const u16 length)
-{
-       int timeout = REGISTER_TIMEOUT * (length / sizeof(u16));
-       rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
-                                     USB_VENDOR_REQUEST_OUT, offset,
-                                     value, length, timeout);
-}
-
-static u16 rt2500usb_bbp_check(const struct rt2x00_dev *rt2x00dev)
-{
-       u16 reg;
-       unsigned int i;
-
-       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
-               rt2500usb_register_read(rt2x00dev, PHY_CSR8, &reg);
-               if (!rt2x00_get_field16(reg, PHY_CSR8_BUSY))
-                       break;
-               udelay(REGISTER_BUSY_DELAY);
-       }
-
-       return reg;
-}
-
-static void rt2500usb_bbp_write(const struct rt2x00_dev *rt2x00dev,
-                               const unsigned int word, const u8 value)
-{
-       u16 reg;
-
-       /*
-        * Wait until the BBP becomes ready.
-        */
-       reg = rt2500usb_bbp_check(rt2x00dev);
-       if (rt2x00_get_field16(reg, PHY_CSR8_BUSY)) {
-               ERROR(rt2x00dev, "PHY_CSR8 register busy. Write failed.\n");
-               return;
-       }
-
-       /*
-        * Write the data into the BBP.
-        */
-       reg = 0;
-       rt2x00_set_field16(&reg, PHY_CSR7_DATA, value);
-       rt2x00_set_field16(&reg, PHY_CSR7_REG_ID, word);
-       rt2x00_set_field16(&reg, PHY_CSR7_READ_CONTROL, 0);
-
-       rt2500usb_register_write(rt2x00dev, PHY_CSR7, reg);
-}
-
-static void rt2500usb_bbp_read(const struct rt2x00_dev *rt2x00dev,
-                              const unsigned int word, u8 *value)
-{
-       u16 reg;
-
-       /*
-        * Wait until the BBP becomes ready.
-        */
-       reg = rt2500usb_bbp_check(rt2x00dev);
-       if (rt2x00_get_field16(reg, PHY_CSR8_BUSY)) {
-               ERROR(rt2x00dev, "PHY_CSR8 register busy. Read failed.\n");
-               return;
-       }
-
-       /*
-        * Write the request into the BBP.
-        */
-       reg = 0;
-       rt2x00_set_field16(&reg, PHY_CSR7_REG_ID, word);
-       rt2x00_set_field16(&reg, PHY_CSR7_READ_CONTROL, 1);
-
-       rt2500usb_register_write(rt2x00dev, PHY_CSR7, reg);
-
-       /*
-        * Wait until the BBP becomes ready.
-        */
-       reg = rt2500usb_bbp_check(rt2x00dev);
-       if (rt2x00_get_field16(reg, PHY_CSR8_BUSY)) {
-               ERROR(rt2x00dev, "PHY_CSR8 register busy. Read failed.\n");
-               *value = 0xff;
-               return;
-       }
-
-       rt2500usb_register_read(rt2x00dev, PHY_CSR7, &reg);
-       *value = rt2x00_get_field16(reg, PHY_CSR7_DATA);
-}
-
-static void rt2500usb_rf_write(const struct rt2x00_dev *rt2x00dev,
-                              const unsigned int word, const u32 value)
-{
-       u16 reg;
-       unsigned int i;
-
-       if (!word)
-               return;
-
-       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
-               rt2500usb_register_read(rt2x00dev, PHY_CSR10, &reg);
-               if (!rt2x00_get_field16(reg, PHY_CSR10_RF_BUSY))
-                       goto rf_write;
-               udelay(REGISTER_BUSY_DELAY);
-       }
-
-       ERROR(rt2x00dev, "PHY_CSR10 register busy. Write failed.\n");
-       return;
-
-rf_write:
-       reg = 0;
-       rt2x00_set_field16(&reg, PHY_CSR9_RF_VALUE, value);
-       rt2500usb_register_write(rt2x00dev, PHY_CSR9, reg);
-
-       reg = 0;
-       rt2x00_set_field16(&reg, PHY_CSR10_RF_VALUE, value >> 16);
-       rt2x00_set_field16(&reg, PHY_CSR10_RF_NUMBER_OF_BITS, 20);
-       rt2x00_set_field16(&reg, PHY_CSR10_RF_IF_SELECT, 0);
-       rt2x00_set_field16(&reg, PHY_CSR10_RF_BUSY, 1);
-
-       rt2500usb_register_write(rt2x00dev, PHY_CSR10, reg);
-       rt2x00_rf_write(rt2x00dev, word, value);
-}
-
-#ifdef CONFIG_RT2X00_LIB_DEBUGFS
-#define CSR_OFFSET(__word)     ( CSR_REG_BASE + ((__word) * sizeof(u16)) )
-
-static void rt2500usb_read_csr(const struct rt2x00_dev *rt2x00dev,
-                              const unsigned int word, u32 *data)
-{
-       rt2500usb_register_read(rt2x00dev, CSR_OFFSET(word), (u16 *) data);
-}
-
-static void rt2500usb_write_csr(const struct rt2x00_dev *rt2x00dev,
-                               const unsigned int word, u32 data)
-{
-       rt2500usb_register_write(rt2x00dev, CSR_OFFSET(word), data);
-}
-
-static const struct rt2x00debug rt2500usb_rt2x00debug = {
-       .owner  = THIS_MODULE,
-       .csr    = {
-               .read           = rt2500usb_read_csr,
-               .write          = rt2500usb_write_csr,
-               .word_size      = sizeof(u16),
-               .word_count     = CSR_REG_SIZE / sizeof(u16),
-       },
-       .eeprom = {
-               .read           = rt2x00_eeprom_read,
-               .write          = rt2x00_eeprom_write,
-               .word_size      = sizeof(u16),
-               .word_count     = EEPROM_SIZE / sizeof(u16),
-       },
-       .bbp    = {
-               .read           = rt2500usb_bbp_read,
-               .write          = rt2500usb_bbp_write,
-               .word_size      = sizeof(u8),
-               .word_count     = BBP_SIZE / sizeof(u8),
-       },
-       .rf     = {
-               .read           = rt2x00_rf_read,
-               .write          = rt2500usb_rf_write,
-               .word_size      = sizeof(u32),
-               .word_count     = RF_SIZE / sizeof(u32),
-       },
-};
-#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
-
-/*
- * Configuration handlers.
- */
-static void rt2500usb_config_mac_addr(struct rt2x00_dev *rt2x00dev,
-                                     __le32 *mac)
-{
-       rt2500usb_register_multiwrite(rt2x00dev, MAC_CSR2, mac,
-                                     (3 * sizeof(__le16)));
-}
-
-static void rt2500usb_config_bssid(struct rt2x00_dev *rt2x00dev,
-                                  __le32 *bssid)
-{
-       rt2500usb_register_multiwrite(rt2x00dev, MAC_CSR5, bssid,
-                                     (3 * sizeof(__le16)));
-}
-
-static void rt2500usb_config_type(struct rt2x00_dev *rt2x00dev, const int type,
-                                 const int tsf_sync)
-{
-       u16 reg;
-
-       rt2500usb_register_write(rt2x00dev, TXRX_CSR19, 0);
-
-       /*
-        * Enable beacon config
-        */
-       rt2500usb_register_read(rt2x00dev, TXRX_CSR20, &reg);
-       rt2x00_set_field16(&reg, TXRX_CSR20_OFFSET,
-                          (PREAMBLE + get_duration(IEEE80211_HEADER, 20)) >> 6);
-       if (type == IEEE80211_IF_TYPE_STA)
-               rt2x00_set_field16(&reg, TXRX_CSR20_BCN_EXPECT_WINDOW, 0);
-       else
-               rt2x00_set_field16(&reg, TXRX_CSR20_BCN_EXPECT_WINDOW, 2);
-       rt2500usb_register_write(rt2x00dev, TXRX_CSR20, reg);
-
-       /*
-        * Enable synchronisation.
-        */
-       rt2500usb_register_read(rt2x00dev, TXRX_CSR18, &reg);
-       rt2x00_set_field16(&reg, TXRX_CSR18_OFFSET, 0);
-       rt2500usb_register_write(rt2x00dev, TXRX_CSR18, reg);
-
-       rt2500usb_register_read(rt2x00dev, TXRX_CSR19, &reg);
-       rt2x00_set_field16(&reg, TXRX_CSR19_TSF_COUNT, 1);
-       rt2x00_set_field16(&reg, TXRX_CSR19_TBCN, 1);
-       rt2x00_set_field16(&reg, TXRX_CSR19_BEACON_GEN, 0);
-       rt2x00_set_field16(&reg, TXRX_CSR19_TSF_SYNC, tsf_sync);
-       rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
-}
-
-static void rt2500usb_config_preamble(struct rt2x00_dev *rt2x00dev,
-                                     const int short_preamble,
-                                     const int ack_timeout,
-                                     const int ack_consume_time)
-{
-       u16 reg;
-
-       /*
-        * When in atomic context, reschedule and let rt2x00lib
-        * call this function again.
-        */
-       if (in_atomic()) {
-               queue_work(rt2x00dev->hw->workqueue, &rt2x00dev->config_work);
-               return;
-       }
-
-       rt2500usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
-       rt2x00_set_field16(&reg, TXRX_CSR1_ACK_TIMEOUT, ack_timeout);
-       rt2500usb_register_write(rt2x00dev, TXRX_CSR1, reg);
-
-       rt2500usb_register_read(rt2x00dev, TXRX_CSR10, &reg);
-       rt2x00_set_field16(&reg, TXRX_CSR10_AUTORESPOND_PREAMBLE,
-                          !!short_preamble);
-       rt2500usb_register_write(rt2x00dev, TXRX_CSR10, reg);
-}
-
-static void rt2500usb_config_phymode(struct rt2x00_dev *rt2x00dev,
-                                    const int phymode,
-                                    const int basic_rate_mask)
-{
-       rt2500usb_register_write(rt2x00dev, TXRX_CSR11, basic_rate_mask);
-
-       if (phymode == HWMODE_B) {
-               rt2500usb_register_write(rt2x00dev, MAC_CSR11, 0x000b);
-               rt2500usb_register_write(rt2x00dev, MAC_CSR12, 0x0040);
-       } else {
-               rt2500usb_register_write(rt2x00dev, MAC_CSR11, 0x0005);
-               rt2500usb_register_write(rt2x00dev, MAC_CSR12, 0x016c);
-       }
-}
-
-static void rt2500usb_config_channel(struct rt2x00_dev *rt2x00dev,
-                                    struct rf_channel *rf, const int txpower)
-{
-       /*
-        * Set TXpower.
-        */
-       rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
-
-       /*
-        * For RT2525E we should first set the channel to half band higher.
-        */
-       if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
-               static const u32 vals[] = {
-                       0x000008aa, 0x000008ae, 0x000008ae, 0x000008b2,
-                       0x000008b2, 0x000008b6, 0x000008b6, 0x000008ba,
-                       0x000008ba, 0x000008be, 0x000008b7, 0x00000902,
-                       0x00000902, 0x00000906
-               };
-
-               rt2500usb_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
-               if (rf->rf4)
-                       rt2500usb_rf_write(rt2x00dev, 4, rf->rf4);
-       }
-
-       rt2500usb_rf_write(rt2x00dev, 1, rf->rf1);
-       rt2500usb_rf_write(rt2x00dev, 2, rf->rf2);
-       rt2500usb_rf_write(rt2x00dev, 3, rf->rf3);
-       if (rf->rf4)
-               rt2500usb_rf_write(rt2x00dev, 4, rf->rf4);
-}
-
-static void rt2500usb_config_txpower(struct rt2x00_dev *rt2x00dev,
-                                    const int txpower)
-{
-       u32 rf3;
-
-       rt2x00_rf_read(rt2x00dev, 3, &rf3);
-       rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
-       rt2500usb_rf_write(rt2x00dev, 3, rf3);
-}
-
-static void rt2500usb_config_antenna(struct rt2x00_dev *rt2x00dev,
-                                    const int antenna_tx, const int antenna_rx)
-{
-       u8 r2;
-       u8 r14;
-       u16 csr5;
-       u16 csr6;
-
-       rt2500usb_bbp_read(rt2x00dev, 2, &r2);
-       rt2500usb_bbp_read(rt2x00dev, 14, &r14);
-       rt2500usb_register_read(rt2x00dev, PHY_CSR5, &csr5);
-       rt2500usb_register_read(rt2x00dev, PHY_CSR6, &csr6);
-
-       /*
-        * Configure the TX antenna.
-        */
-       switch (antenna_tx) {
-       case ANTENNA_SW_DIVERSITY:
-       case ANTENNA_HW_DIVERSITY:
-               rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 1);
-               rt2x00_set_field16(&csr5, PHY_CSR5_CCK, 1);
-               rt2x00_set_field16(&csr6, PHY_CSR6_OFDM, 1);
-               break;
-       case ANTENNA_A:
-               rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
-               rt2x00_set_field16(&csr5, PHY_CSR5_CCK, 0);
-               rt2x00_set_field16(&csr6, PHY_CSR6_OFDM, 0);
-               break;
-       case ANTENNA_B:
-               rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
-               rt2x00_set_field16(&csr5, PHY_CSR5_CCK, 2);
-               rt2x00_set_field16(&csr6, PHY_CSR6_OFDM, 2);
-               break;
-       }
-
-       /*
-        * Configure the RX antenna.
-        */
-       switch (antenna_rx) {
-       case ANTENNA_SW_DIVERSITY:
-       case ANTENNA_HW_DIVERSITY:
-               rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 1);
-               break;
-       case ANTENNA_A:
-               rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
-               break;
-       case ANTENNA_B:
-               rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
-               break;
-       }
-
-       /*
-        * RT2525E and RT5222 need to flip TX I/Q
-        */
-       if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
-           rt2x00_rf(&rt2x00dev->chip, RF5222)) {
-               rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
-               rt2x00_set_field16(&csr5, PHY_CSR5_CCK_FLIP, 1);
-               rt2x00_set_field16(&csr6, PHY_CSR6_OFDM_FLIP, 1);
-
-               /*
-                * RT2525E does not need RX I/Q Flip.
-                */
-               if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
-                       rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
-       } else {
-               rt2x00_set_field16(&csr5, PHY_CSR5_CCK_FLIP, 0);
-               rt2x00_set_field16(&csr6, PHY_CSR6_OFDM_FLIP, 0);
-       }
-
-       rt2500usb_bbp_write(rt2x00dev, 2, r2);
-       rt2500usb_bbp_write(rt2x00dev, 14, r14);
-       rt2500usb_register_write(rt2x00dev, PHY_CSR5, csr5);
-       rt2500usb_register_write(rt2x00dev, PHY_CSR6, csr6);
-}
-
-static void rt2500usb_config_duration(struct rt2x00_dev *rt2x00dev,
-                                     struct rt2x00lib_conf *libconf)
-{
-       u16 reg;
-
-       rt2500usb_register_write(rt2x00dev, MAC_CSR10, libconf->slot_time);
-
-       rt2500usb_register_read(rt2x00dev, TXRX_CSR18, &reg);
-       rt2x00_set_field16(&reg, TXRX_CSR18_INTERVAL,
-                          libconf->conf->beacon_int * 4);
-       rt2500usb_register_write(rt2x00dev, TXRX_CSR18, reg);
-}
-
-static void rt2500usb_config(struct rt2x00_dev *rt2x00dev,
-                            const unsigned int flags,
-                            struct rt2x00lib_conf *libconf)
-{
-       if (flags & CONFIG_UPDATE_PHYMODE)
-               rt2500usb_config_phymode(rt2x00dev, libconf->phymode,
-                                        libconf->basic_rates);
-       if (flags & CONFIG_UPDATE_CHANNEL)
-               rt2500usb_config_channel(rt2x00dev, &libconf->rf,
-                                        libconf->conf->power_level);
-       if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
-               rt2500usb_config_txpower(rt2x00dev,
-                                        libconf->conf->power_level);
-       if (flags & CONFIG_UPDATE_ANTENNA)
-               rt2500usb_config_antenna(rt2x00dev,
-                                        libconf->conf->antenna_sel_tx,
-                                        libconf->conf->antenna_sel_rx);
-       if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
-               rt2500usb_config_duration(rt2x00dev, libconf);
-}
-
-/*
- * LED functions.
- */
-static void rt2500usb_enable_led(struct rt2x00_dev *rt2x00dev)
-{
-       u16 reg;
-
-       rt2500usb_register_read(rt2x00dev, MAC_CSR21, &reg);
-       rt2x00_set_field16(&reg, MAC_CSR21_ON_PERIOD, 70);
-       rt2x00_set_field16(&reg, MAC_CSR21_OFF_PERIOD, 30);
-       rt2500usb_register_write(rt2x00dev, MAC_CSR21, reg);
-
-       rt2500usb_register_read(rt2x00dev, MAC_CSR20, &reg);
-
-       if (rt2x00dev->led_mode == LED_MODE_TXRX_ACTIVITY) {
-               rt2x00_set_field16(&reg, MAC_CSR20_LINK, 1);
-               rt2x00_set_field16(&reg, MAC_CSR20_ACTIVITY, 0);
-       } else if (rt2x00dev->led_mode == LED_MODE_ASUS) {
-               rt2x00_set_field16(&reg, MAC_CSR20_LINK, 0);
-               rt2x00_set_field16(&reg, MAC_CSR20_ACTIVITY, 1);
-       } else {
-               rt2x00_set_field16(&reg, MAC_CSR20_LINK, 1);
-               rt2x00_set_field16(&reg, MAC_CSR20_ACTIVITY, 1);
-       }
-
-       rt2500usb_register_write(rt2x00dev, MAC_CSR20, reg);
-}
-
-static void rt2500usb_disable_led(struct rt2x00_dev *rt2x00dev)
-{
-       u16 reg;
-
-       rt2500usb_register_read(rt2x00dev, MAC_CSR20, &reg);
-       rt2x00_set_field16(&reg, MAC_CSR20_LINK, 0);
-       rt2x00_set_field16(&reg, MAC_CSR20_ACTIVITY, 0);
-       rt2500usb_register_write(rt2x00dev, MAC_CSR20, reg);
-}
-
-/*
- * Link tuning
- */
-static void rt2500usb_link_stats(struct rt2x00_dev *rt2x00dev)
-{
-       u16 reg;
-
-       /*
-        * Update FCS error count from register.
-        */
-       rt2500usb_register_read(rt2x00dev, STA_CSR0, &reg);
-       rt2x00dev->link.rx_failed = rt2x00_get_field16(reg, STA_CSR0_FCS_ERROR);
-
-       /*
-        * Update False CCA count from register.
-        */
-       rt2500usb_register_read(rt2x00dev, STA_CSR3, &reg);
-       rt2x00dev->link.false_cca =
-           rt2x00_get_field16(reg, STA_CSR3_FALSE_CCA_ERROR);
-}
-
-static void rt2500usb_reset_tuner(struct rt2x00_dev *rt2x00dev)
-{
-       u16 eeprom;
-       u16 value;
-
-       rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R24, &eeprom);
-       value = rt2x00_get_field16(eeprom, EEPROM_BBPTUNE_R24_LOW);
-       rt2500usb_bbp_write(rt2x00dev, 24, value);
-
-       rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R25, &eeprom);
-       value = rt2x00_get_field16(eeprom, EEPROM_BBPTUNE_R25_LOW);
-       rt2500usb_bbp_write(rt2x00dev, 25, value);
-
-       rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R61, &eeprom);
-       value = rt2x00_get_field16(eeprom, EEPROM_BBPTUNE_R61_LOW);
-       rt2500usb_bbp_write(rt2x00dev, 61, value);
-
-       rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_VGC, &eeprom);
-       value = rt2x00_get_field16(eeprom, EEPROM_BBPTUNE_VGCUPPER);
-       rt2500usb_bbp_write(rt2x00dev, 17, value);
-
-       rt2x00dev->link.vgc_level = value;
-}
-
-static void rt2500usb_link_tuner(struct rt2x00_dev *rt2x00dev)
-{
-       int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
-       u16 bbp_thresh;
-       u16 vgc_bound;
-       u16 sens;
-       u16 r24;
-       u16 r25;
-       u16 r61;
-       u16 r17_sens;
-       u8 r17;
-       u8 up_bound;
-       u8 low_bound;
-
-       /*
-        * Determine the BBP tuning threshold and correctly
-        * set BBP 24, 25 and 61.
-        */
-       rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE, &bbp_thresh);
-       bbp_thresh = rt2x00_get_field16(bbp_thresh, EEPROM_BBPTUNE_THRESHOLD);
-
-       rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R24, &r24);
-       rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R25, &r25);
-       rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R61, &r61);
-
-       if ((rssi + bbp_thresh) > 0) {
-               r24 = rt2x00_get_field16(r24, EEPROM_BBPTUNE_R24_HIGH);
-               r25 = rt2x00_get_field16(r25, EEPROM_BBPTUNE_R25_HIGH);
-               r61 = rt2x00_get_field16(r61, EEPROM_BBPTUNE_R61_HIGH);
-       } else {
-               r24 = rt2x00_get_field16(r24, EEPROM_BBPTUNE_R24_LOW);
-               r25 = rt2x00_get_field16(r25, EEPROM_BBPTUNE_R25_LOW);
-               r61 = rt2x00_get_field16(r61, EEPROM_BBPTUNE_R61_LOW);
-       }
-
-       rt2500usb_bbp_write(rt2x00dev, 24, r24);
-       rt2500usb_bbp_write(rt2x00dev, 25, r25);
-       rt2500usb_bbp_write(rt2x00dev, 61, r61);
-
-       /*
-        * Read current r17 value, as well as the sensitivity values
-        * for the r17 register.
-        */
-       rt2500usb_bbp_read(rt2x00dev, 17, &r17);
-       rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R17, &r17_sens);
-
-       /*
-        * A too low RSSI will cause too much false CCA which will
-        * then corrupt the R17 tuning. To remidy this the tuning should
-        * be stopped (While making sure the R17 value will not exceed limits)
-        */
-       if (rssi >= -40) {
-               if (r17 != 0x60)
-                       rt2500usb_bbp_write(rt2x00dev, 17, 0x60);
-               return;
-       }
-
-       /*
-        * Special big-R17 for short distance
-        */
-       if (rssi >= -58) {
-               sens = rt2x00_get_field16(r17_sens, EEPROM_BBPTUNE_R17_LOW);
-               if (r17 != sens)
-                       rt2500usb_bbp_write(rt2x00dev, 17, sens);
-               return;
-       }
-
-       /*
-        * Special mid-R17 for middle distance
-        */
-       if (rssi >= -74) {
-               sens = rt2x00_get_field16(r17_sens, EEPROM_BBPTUNE_R17_HIGH);
-               if (r17 != sens)
-                       rt2500usb_bbp_write(rt2x00dev, 17, sens);
-               return;
-       }
-
-       /*
-        * Leave short or middle distance condition, restore r17
-        * to the dynamic tuning range.
-        */
-       rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_VGC, &vgc_bound);
-       vgc_bound = rt2x00_get_field16(vgc_bound, EEPROM_BBPTUNE_VGCUPPER);
-
-       low_bound = 0x32;
-       if (rssi >= -77)
-               up_bound = vgc_bound;
-       else
-               up_bound = vgc_bound - (-77 - rssi);
-
-       if (up_bound < low_bound)
-               up_bound = low_bound;
-
-       if (r17 > up_bound) {
-               rt2500usb_bbp_write(rt2x00dev, 17, up_bound);
-               rt2x00dev->link.vgc_level = up_bound;
-       } else if (rt2x00dev->link.false_cca > 512 && r17 < up_bound) {
-               rt2500usb_bbp_write(rt2x00dev, 17, ++r17);
-               rt2x00dev->link.vgc_level = r17;
-       } else if (rt2x00dev->link.false_cca < 100 && r17 > low_bound) {
-               rt2500usb_bbp_write(rt2x00dev, 17, --r17);
-               rt2x00dev->link.vgc_level = r17;
-       }
-}
-
-/*
- * Initialization functions.
- */
-static int rt2500usb_init_registers(struct rt2x00_dev *rt2x00dev)
-{
-       u16 reg;
-
-       rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0x0001,
-                                   USB_MODE_TEST, REGISTER_TIMEOUT);
-       rt2x00usb_vendor_request_sw(rt2x00dev, USB_SINGLE_WRITE, 0x0308,
-                                   0x00f0, REGISTER_TIMEOUT);
-
-       rt2500usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
-       rt2x00_set_field16(&reg, TXRX_CSR2_DISABLE_RX, 1);
-       rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg);
-
-       rt2500usb_register_write(rt2x00dev, MAC_CSR13, 0x1111);
-       rt2500usb_register_write(rt2x00dev, MAC_CSR14, 0x1e11);
-
-       rt2500usb_register_read(rt2x00dev, MAC_CSR1, &reg);
-       rt2x00_set_field16(&reg, MAC_CSR1_SOFT_RESET, 1);
-       rt2x00_set_field16(&reg, MAC_CSR1_BBP_RESET, 1);
-       rt2x00_set_field16(&reg, MAC_CSR1_HOST_READY, 0);
-       rt2500usb_register_write(rt2x00dev, MAC_CSR1, reg);
-
-       rt2500usb_register_read(rt2x00dev, MAC_CSR1, &reg);
-       rt2x00_set_field16(&reg, MAC_CSR1_SOFT_RESET, 0);
-       rt2x00_set_field16(&reg, MAC_CSR1_BBP_RESET, 0);
-       rt2x00_set_field16(&reg, MAC_CSR1_HOST_READY, 0);
-       rt2500usb_register_write(rt2x00dev, MAC_CSR1, reg);
-
-       rt2500usb_register_read(rt2x00dev, TXRX_CSR5, &reg);
-       rt2x00_set_field16(&reg, TXRX_CSR5_BBP_ID0, 13);
-       rt2x00_set_field16(&reg, TXRX_CSR5_BBP_ID0_VALID, 1);
-       rt2x00_set_field16(&reg, TXRX_CSR5_BBP_ID1, 12);
-       rt2x00_set_field16(&reg, TXRX_CSR5_BBP_ID1_VALID, 1);
-       rt2500usb_register_write(rt2x00dev, TXRX_CSR5, reg);
-
-       rt2500usb_register_read(rt2x00dev, TXRX_CSR6, &reg);
-       rt2x00_set_field16(&reg, TXRX_CSR6_BBP_ID0, 10);
-       rt2x00_set_field16(&reg, TXRX_CSR6_BBP_ID0_VALID, 1);
-       rt2x00_set_field16(&reg, TXRX_CSR6_BBP_ID1, 11);
-       rt2x00_set_field16(&reg, TXRX_CSR6_BBP_ID1_VALID, 1);
-       rt2500usb_register_write(rt2x00dev, TXRX_CSR6, reg);
-
-       rt2500usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
-       rt2x00_set_field16(&reg, TXRX_CSR7_BBP_ID0, 7);
-       rt2x00_set_field16(&reg, TXRX_CSR7_BBP_ID0_VALID, 1);
-       rt2x00_set_field16(&reg, TXRX_CSR7_BBP_ID1, 6);
-       rt2x00_set_field16(&reg, TXRX_CSR7_BBP_ID1_VALID, 1);
-       rt2500usb_register_write(rt2x00dev, TXRX_CSR7, reg);
-
-       rt2500usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
-       rt2x00_set_field16(&reg, TXRX_CSR8_BBP_ID0, 5);
-       rt2x00_set_field16(&reg, TXRX_CSR8_BBP_ID0_VALID, 1);
-       rt2x00_set_field16(&reg, TXRX_CSR8_BBP_ID1, 0);
-       rt2x00_set_field16(&reg, TXRX_CSR8_BBP_ID1_VALID, 0);
-       rt2500usb_register_write(rt2x00dev, TXRX_CSR8, reg);
-
-       rt2500usb_register_write(rt2x00dev, TXRX_CSR21, 0xe78f);
-       rt2500usb_register_write(rt2x00dev, MAC_CSR9, 0xff1d);
-
-       if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
-               return -EBUSY;
-
-       rt2500usb_register_read(rt2x00dev, MAC_CSR1, &reg);
-       rt2x00_set_field16(&reg, MAC_CSR1_SOFT_RESET, 0);
-       rt2x00_set_field16(&reg, MAC_CSR1_BBP_RESET, 0);
-       rt2x00_set_field16(&reg, MAC_CSR1_HOST_READY, 1);
-       rt2500usb_register_write(rt2x00dev, MAC_CSR1, reg);
-
-       if (rt2x00_rev(&rt2x00dev->chip) >= RT2570_VERSION_C) {
-               rt2500usb_register_read(rt2x00dev, PHY_CSR2, &reg);
-               reg &= ~0x0002;
-       } else {
-               reg = 0x3002;
-       }
-       rt2500usb_register_write(rt2x00dev, PHY_CSR2, reg);
-
-       rt2500usb_register_write(rt2x00dev, MAC_CSR11, 0x0002);
-       rt2500usb_register_write(rt2x00dev, MAC_CSR22, 0x0053);
-       rt2500usb_register_write(rt2x00dev, MAC_CSR15, 0x01ee);
-       rt2500usb_register_write(rt2x00dev, MAC_CSR16, 0x0000);
-
-       rt2500usb_register_read(rt2x00dev, MAC_CSR8, &reg);
-       rt2x00_set_field16(&reg, MAC_CSR8_MAX_FRAME_UNIT,
-                          rt2x00dev->rx->data_size);
-       rt2500usb_register_write(rt2x00dev, MAC_CSR8, reg);
-
-       rt2500usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
-       rt2x00_set_field16(&reg, TXRX_CSR0_IV_OFFSET, IEEE80211_HEADER);
-       rt2x00_set_field16(&reg, TXRX_CSR0_KEY_ID, 0xff);
-       rt2500usb_register_write(rt2x00dev, TXRX_CSR0, reg);
-
-       rt2500usb_register_read(rt2x00dev, MAC_CSR18, &reg);
-       rt2x00_set_field16(&reg, MAC_CSR18_DELAY_AFTER_BEACON, 90);
-       rt2500usb_register_write(rt2x00dev, MAC_CSR18, reg);
-
-       rt2500usb_register_read(rt2x00dev, PHY_CSR4, &reg);
-       rt2x00_set_field16(&reg, PHY_CSR4_LOW_RF_LE, 1);
-       rt2500usb_register_write(rt2x00dev, PHY_CSR4, reg);
-
-       rt2500usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
-       rt2x00_set_field16(&reg, TXRX_CSR1_AUTO_SEQUENCE, 1);
-       rt2500usb_register_write(rt2x00dev, TXRX_CSR1, reg);
-
-       return 0;
-}
-
-static int rt2500usb_init_bbp(struct rt2x00_dev *rt2x00dev)
-{
-       unsigned int i;
-       u16 eeprom;
-       u8 value;
-       u8 reg_id;
-
-       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
-               rt2500usb_bbp_read(rt2x00dev, 0, &value);
-               if ((value != 0xff) && (value != 0x00))
-                       goto continue_csr_init;
-               NOTICE(rt2x00dev, "Waiting for BBP register.\n");
-               udelay(REGISTER_BUSY_DELAY);
-       }
-
-       ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
-       return -EACCES;
-
-continue_csr_init:
-       rt2500usb_bbp_write(rt2x00dev, 3, 0x02);
-       rt2500usb_bbp_write(rt2x00dev, 4, 0x19);
-       rt2500usb_bbp_write(rt2x00dev, 14, 0x1c);
-       rt2500usb_bbp_write(rt2x00dev, 15, 0x30);
-       rt2500usb_bbp_write(rt2x00dev, 16, 0xac);
-       rt2500usb_bbp_write(rt2x00dev, 18, 0x18);
-       rt2500usb_bbp_write(rt2x00dev, 19, 0xff);
-       rt2500usb_bbp_write(rt2x00dev, 20, 0x1e);
-       rt2500usb_bbp_write(rt2x00dev, 21, 0x08);
-       rt2500usb_bbp_write(rt2x00dev, 22, 0x08);
-       rt2500usb_bbp_write(rt2x00dev, 23, 0x08);
-       rt2500usb_bbp_write(rt2x00dev, 24, 0x80);
-       rt2500usb_bbp_write(rt2x00dev, 25, 0x50);
-       rt2500usb_bbp_write(rt2x00dev, 26, 0x08);
-       rt2500usb_bbp_write(rt2x00dev, 27, 0x23);
-       rt2500usb_bbp_write(rt2x00dev, 30, 0x10);
-       rt2500usb_bbp_write(rt2x00dev, 31, 0x2b);
-       rt2500usb_bbp_write(rt2x00dev, 32, 0xb9);
-       rt2500usb_bbp_write(rt2x00dev, 34, 0x12);
-       rt2500usb_bbp_write(rt2x00dev, 35, 0x50);
-       rt2500usb_bbp_write(rt2x00dev, 39, 0xc4);
-       rt2500usb_bbp_write(rt2x00dev, 40, 0x02);
-       rt2500usb_bbp_write(rt2x00dev, 41, 0x60);
-       rt2500usb_bbp_write(rt2x00dev, 53, 0x10);
-       rt2500usb_bbp_write(rt2x00dev, 54, 0x18);
-       rt2500usb_bbp_write(rt2x00dev, 56, 0x08);
-       rt2500usb_bbp_write(rt2x00dev, 57, 0x10);
-       rt2500usb_bbp_write(rt2x00dev, 58, 0x08);
-       rt2500usb_bbp_write(rt2x00dev, 61, 0x60);
-       rt2500usb_bbp_write(rt2x00dev, 62, 0x10);
-       rt2500usb_bbp_write(rt2x00dev, 75, 0xff);
-
-       DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
-       for (i = 0; i < EEPROM_BBP_SIZE; i++) {
-               rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
-
-               if (eeprom != 0xffff && eeprom != 0x0000) {
-                       reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
-                       value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
-                       DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
-                             reg_id, value);
-                       rt2500usb_bbp_write(rt2x00dev, reg_id, value);
-               }
-       }
-       DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
-
-       return 0;
-}
-
-/*
- * Device state switch handlers.
- */
-static void rt2500usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
-                               enum dev_state state)
-{
-       u16 reg;
-
-       rt2500usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
-       rt2x00_set_field16(&reg, TXRX_CSR2_DISABLE_RX,
-                          state == STATE_RADIO_RX_OFF);
-       rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg);
-}
-
-static int rt2500usb_enable_radio(struct rt2x00_dev *rt2x00dev)
-{
-       /*
-        * Initialize all registers.
-        */
-       if (rt2500usb_init_registers(rt2x00dev) ||
-           rt2500usb_init_bbp(rt2x00dev)) {
-               ERROR(rt2x00dev, "Register initialization failed.\n");
-               return -EIO;
-       }
-
-       rt2x00usb_enable_radio(rt2x00dev);
-
-       /*
-        * Enable LED
-        */
-       rt2500usb_enable_led(rt2x00dev);
-
-       return 0;
-}
-
-static void rt2500usb_disable_radio(struct rt2x00_dev *rt2x00dev)
-{
-       /*
-        * Disable LED
-        */
-       rt2500usb_disable_led(rt2x00dev);
-
-       rt2500usb_register_write(rt2x00dev, MAC_CSR13, 0x2121);
-       rt2500usb_register_write(rt2x00dev, MAC_CSR14, 0x2121);
-
-       /*
-        * Disable synchronisation.
-        */
-       rt2500usb_register_write(rt2x00dev, TXRX_CSR19, 0);
-
-       rt2x00usb_disable_radio(rt2x00dev);
-}
-
-static int rt2500usb_set_state(struct rt2x00_dev *rt2x00dev,
-                              enum dev_state state)
-{
-       u16 reg;
-       u16 reg2;
-       unsigned int i;
-       char put_to_sleep;
-       char bbp_state;
-       char rf_state;
-
-       put_to_sleep = (state != STATE_AWAKE);
-
-       reg = 0;
-       rt2x00_set_field16(&reg, MAC_CSR17_BBP_DESIRE_STATE, state);
-       rt2x00_set_field16(&reg, MAC_CSR17_RF_DESIRE_STATE, state);
-       rt2x00_set_field16(&reg, MAC_CSR17_PUT_TO_SLEEP, put_to_sleep);
-       rt2500usb_register_write(rt2x00dev, MAC_CSR17, reg);
-       rt2x00_set_field16(&reg, MAC_CSR17_SET_STATE, 1);
-       rt2500usb_register_write(rt2x00dev, MAC_CSR17, reg);
-
-       /*
-        * Device is not guaranteed to be in the requested state yet.
-        * We must wait until the register indicates that the
-        * device has entered the correct state.
-        */
-       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
-               rt2500usb_register_read(rt2x00dev, MAC_CSR17, &reg2);
-               bbp_state = rt2x00_get_field16(reg2, MAC_CSR17_BBP_CURR_STATE);
-               rf_state = rt2x00_get_field16(reg2, MAC_CSR17_RF_CURR_STATE);
-               if (bbp_state == state && rf_state == state)
-                       return 0;
-               rt2500usb_register_write(rt2x00dev, MAC_CSR17, reg);
-               msleep(30);
-       }
-
-       NOTICE(rt2x00dev, "Device failed to enter state %d, "
-              "current device state: bbp %d and rf %d.\n",
-              state, bbp_state, rf_state);
-
-       return -EBUSY;
-}
-
-static int rt2500usb_set_device_state(struct rt2x00_dev *rt2x00dev,
-                                     enum dev_state state)
-{
-       int retval = 0;
-
-       switch (state) {
-       case STATE_RADIO_ON:
-               retval = rt2500usb_enable_radio(rt2x00dev);
-               break;
-       case STATE_RADIO_OFF:
-               rt2500usb_disable_radio(rt2x00dev);
-               break;
-       case STATE_RADIO_RX_ON:
-       case STATE_RADIO_RX_OFF:
-               rt2500usb_toggle_rx(rt2x00dev, state);
-               break;
-       case STATE_DEEP_SLEEP:
-       case STATE_SLEEP:
-       case STATE_STANDBY:
-       case STATE_AWAKE:
-               retval = rt2500usb_set_state(rt2x00dev, state);
-               break;
-       default:
-               retval = -ENOTSUPP;
-               break;
-       }
-
-       return retval;
-}
-
-/*
- * TX descriptor initialization
- */
-static void rt2500usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
-                                   struct data_desc *txd,
-                                   struct txdata_entry_desc *desc,
-                                   struct ieee80211_hdr *ieee80211hdr,
-                                   unsigned int length,
-                                   struct ieee80211_tx_control *control)
-{
-       u32 word;
-
-       /*
-        * Start writing the descriptor words.
-        */
-       rt2x00_desc_read(txd, 1, &word);
-       rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
-       rt2x00_set_field32(&word, TXD_W1_AIFS, desc->aifs);
-       rt2x00_set_field32(&word, TXD_W1_CWMIN, desc->cw_min);
-       rt2x00_set_field32(&word, TXD_W1_CWMAX, desc->cw_max);
-       rt2x00_desc_write(txd, 1, word);
-
-       rt2x00_desc_read(txd, 2, &word);
-       rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, desc->signal);
-       rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, desc->service);
-       rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, desc->length_low);
-       rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, desc->length_high);
-       rt2x00_desc_write(txd, 2, word);
-
-       rt2x00_desc_read(txd, 0, &word);
-       rt2x00_set_field32(&word, TXD_W0_RETRY_LIMIT, control->retry_limit);
-       rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
-                          test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
-       rt2x00_set_field32(&word, TXD_W0_ACK,
-                          !(control->flags & IEEE80211_TXCTL_NO_ACK));
-       rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
-                          test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
-       rt2x00_set_field32(&word, TXD_W0_OFDM,
-                          test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
-       rt2x00_set_field32(&word, TXD_W0_NEW_SEQ,
-                          !!(control->flags & IEEE80211_TXCTL_FIRST_FRAGMENT));
-       rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
-       rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
-       rt2x00_set_field32(&word, TXD_W0_CIPHER, CIPHER_NONE);
-       rt2x00_desc_write(txd, 0, word);
-}
-
-static int rt2500usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
-                                    struct sk_buff *skb)
-{
-       int length;
-
-       /*
-        * The length _must_ be a multiple of 2,
-        * but it must _not_ be a multiple of the USB packet size.
-        */
-       length = roundup(skb->len, 2);
-       length += (2 * !(length % rt2x00dev->usb_maxpacket));
-
-       return length;
-}
-
-/*
- * TX data initialization
- */
-static void rt2500usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
-                                   unsigned int queue)
-{
-       u16 reg;
-
-       if (queue != IEEE80211_TX_QUEUE_BEACON)
-               return;
-
-       rt2500usb_register_read(rt2x00dev, TXRX_CSR19, &reg);
-       if (!rt2x00_get_field16(reg, TXRX_CSR19_BEACON_GEN)) {
-               rt2x00_set_field16(&reg, TXRX_CSR19_BEACON_GEN, 1);
-               /*
-                * Beacon generation will fail initially.
-                * To prevent this we need to register the TXRX_CSR19
-                * register several times.
-                */
-               rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
-               rt2500usb_register_write(rt2x00dev, TXRX_CSR19, 0);
-               rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
-               rt2500usb_register_write(rt2x00dev, TXRX_CSR19, 0);
-               rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
-       }
-}
-
-/*
- * RX control handlers
- */
-static void rt2500usb_fill_rxdone(struct data_entry *entry,
-                                 struct rxdata_entry_desc *desc)
-{
-       struct urb *urb = entry->priv;
-       struct data_desc *rxd = (struct data_desc *)(entry->skb->data +
-                                                    (urb->actual_length -
-                                                     entry->ring->desc_size));
-       u32 word0;
-       u32 word1;
-
-       rt2x00_desc_read(rxd, 0, &word0);
-       rt2x00_desc_read(rxd, 1, &word1);
-
-       desc->flags = 0;
-       if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
-               desc->flags |= RX_FLAG_FAILED_FCS_CRC;
-       if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
-               desc->flags |= RX_FLAG_FAILED_PLCP_CRC;
-
-       /*
-        * Obtain the status about this packet.
-        */
-       desc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
-       desc->rssi = rt2x00_get_field32(word1, RXD_W1_RSSI) -
-           entry->ring->rt2x00dev->rssi_offset;
-       desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
-       desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
-
-       return;
-}
-
-/*
- * Interrupt functions.
- */
-static void rt2500usb_beacondone(struct urb *urb)
-{
-       struct data_entry *entry = (struct data_entry *)urb->context;
-       struct data_ring *ring = entry->ring;
-
-       if (!test_bit(DEVICE_ENABLED_RADIO, &ring->rt2x00dev->flags))
-               return;
-
-       /*
-        * Check if this was the guardian beacon,
-        * if that was the case we need to send the real beacon now.
-        * Otherwise we should free the sk_buffer, the device
-        * should be doing the rest of the work now.
-        */
-       if (ring->index == 1) {
-               rt2x00_ring_index_done_inc(ring);
-               entry = rt2x00_get_data_entry(ring);
-               usb_submit_urb(entry->priv, GFP_ATOMIC);
-               rt2x00_ring_index_inc(ring);
-       } else if (ring->index_done == 1) {
-               entry = rt2x00_get_data_entry_done(ring);
-               if (entry->skb) {
-                       dev_kfree_skb(entry->skb);
-                       entry->skb = NULL;
-               }
-               rt2x00_ring_index_done_inc(ring);
-       }
-}
-
-/*
- * Device probe functions.
- */
-static int rt2500usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
-{
-       u16 word;
-       u8 *mac;
-
-       rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
-
-       /*
-        * Start validation of the data that has been read.
-        */
-       mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
-       if (!is_valid_ether_addr(mac)) {
-               DECLARE_MAC_BUF(macbuf);
-
-               random_ether_addr(mac);
-               EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
-       }
-
-       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
-       if (word == 0xffff) {
-               rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
-               rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, 0);
-               rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, 0);
-               rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE, 0);
-               rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
-               rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
-               rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
-               rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
-               EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
-       }
-
-       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
-       if (word == 0xffff) {
-               rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
-               rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
-               rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
-               rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
-               EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
-       }
-
-       rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
-       if (word == 0xffff) {
-               rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
-                                  DEFAULT_RSSI_OFFSET);
-               rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
-               EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
-       }
-
-       rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE, &word);
-       if (word == 0xffff) {
-               rt2x00_set_field16(&word, EEPROM_BBPTUNE_THRESHOLD, 45);
-               rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE, word);
-               EEPROM(rt2x00dev, "BBPtune: 0x%04x\n", word);
-       }
-
-       rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_VGC, &word);
-       if (word == 0xffff) {
-               rt2x00_set_field16(&word, EEPROM_BBPTUNE_VGCUPPER, 0x40);
-               rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_VGC, word);
-               EEPROM(rt2x00dev, "BBPtune vgc: 0x%04x\n", word);
-       }
-
-       rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R17, &word);
-       if (word == 0xffff) {
-               rt2x00_set_field16(&word, EEPROM_BBPTUNE_R17_LOW, 0x48);
-               rt2x00_set_field16(&word, EEPROM_BBPTUNE_R17_HIGH, 0x41);
-               rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_R17, word);
-               EEPROM(rt2x00dev, "BBPtune r17: 0x%04x\n", word);
-       }
-
-       rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R24, &word);
-       if (word == 0xffff) {
-               rt2x00_set_field16(&word, EEPROM_BBPTUNE_R24_LOW, 0x40);
-               rt2x00_set_field16(&word, EEPROM_BBPTUNE_R24_HIGH, 0x80);
-               rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_R24, word);
-               EEPROM(rt2x00dev, "BBPtune r24: 0x%04x\n", word);
-       }
-
-       rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R25, &word);
-       if (word == 0xffff) {
-               rt2x00_set_field16(&word, EEPROM_BBPTUNE_R25_LOW, 0x40);
-               rt2x00_set_field16(&word, EEPROM_BBPTUNE_R25_HIGH, 0x50);
-               rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_R25, word);
-               EEPROM(rt2x00dev, "BBPtune r25: 0x%04x\n", word);
-       }
-
-       rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R61, &word);
-       if (word == 0xffff) {
-               rt2x00_set_field16(&word, EEPROM_BBPTUNE_R61_LOW, 0x60);
-               rt2x00_set_field16(&word, EEPROM_BBPTUNE_R61_HIGH, 0x6d);
-               rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_R61, word);
-               EEPROM(rt2x00dev, "BBPtune r61: 0x%04x\n", word);
-       }
-
-       return 0;
-}
-
-static int rt2500usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
-{
-       u16 reg;
-       u16 value;
-       u16 eeprom;
-
-       /*
-        * Read EEPROM word for configuration.
-        */
-       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
-
-       /*
-        * Identify RF chipset.
-        */
-       value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
-       rt2500usb_register_read(rt2x00dev, MAC_CSR0, &reg);
-       rt2x00_set_chip(rt2x00dev, RT2570, value, reg);
-
-       if (!rt2x00_check_rev(&rt2x00dev->chip, 0)) {
-               ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
-               return -ENODEV;
-       }
-
-       if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
-           !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
-           !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
-           !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
-           !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
-           !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
-               ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
-               return -ENODEV;
-       }
-
-       /*
-        * Identify default antenna configuration.
-        */
-       rt2x00dev->hw->conf.antenna_sel_tx =
-           rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
-       rt2x00dev->hw->conf.antenna_sel_rx =
-           rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
-
-       /*
-        * Store led mode, for correct led behaviour.
-        */
-       rt2x00dev->led_mode =
-           rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
-
-       /*
-        * Check if the BBP tuning should be disabled.
-        */
-       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
-       if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
-               __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
-
-       /*
-        * Read the RSSI <-> dBm offset information.
-        */
-       rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
-       rt2x00dev->rssi_offset =
-           rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
-
-       return 0;
-}
-
-/*
- * RF value list for RF2522
- * Supports: 2.4 GHz
- */
-static const struct rf_channel rf_vals_bg_2522[] = {
-       { 1,  0x00002050, 0x000c1fda, 0x00000101, 0 },
-       { 2,  0x00002050, 0x000c1fee, 0x00000101, 0 },
-       { 3,  0x00002050, 0x000c2002, 0x00000101, 0 },
-       { 4,  0x00002050, 0x000c2016, 0x00000101, 0 },
-       { 5,  0x00002050, 0x000c202a, 0x00000101, 0 },
-       { 6,  0x00002050, 0x000c203e, 0x00000101, 0 },
-       { 7,  0x00002050, 0x000c2052, 0x00000101, 0 },
-       { 8,  0x00002050, 0x000c2066, 0x00000101, 0 },
-       { 9,  0x00002050, 0x000c207a, 0x00000101, 0 },
-       { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
-       { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
-       { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
-       { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
-       { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
-};
-
-/*
- * RF value list for RF2523
- * Supports: 2.4 GHz
- */
-static const struct rf_channel rf_vals_bg_2523[] = {
-       { 1,  0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
-       { 2,  0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
-       { 3,  0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
-       { 4,  0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
-       { 5,  0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
-       { 6,  0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
-       { 7,  0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
-       { 8,  0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
-       { 9,  0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
-       { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
-       { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
-       { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
-       { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
-       { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
-};
-
-/*
- * RF value list for RF2524
- * Supports: 2.4 GHz
- */
-static const struct rf_channel rf_vals_bg_2524[] = {
-       { 1,  0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
-       { 2,  0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
-       { 3,  0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
-       { 4,  0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
-       { 5,  0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
-       { 6,  0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
-       { 7,  0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
-       { 8,  0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
-       { 9,  0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
-       { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
-       { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
-       { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
-       { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
-       { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
-};
-
-/*
- * RF value list for RF2525
- * Supports: 2.4 GHz
- */
-static const struct rf_channel rf_vals_bg_2525[] = {
-       { 1,  0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
-       { 2,  0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
-       { 3,  0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
-       { 4,  0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
-       { 5,  0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
-       { 6,  0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
-       { 7,  0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
-       { 8,  0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
-       { 9,  0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
-       { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
-       { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
-       { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
-       { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
-       { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
-};
-
-/*
- * RF value list for RF2525e
- * Supports: 2.4 GHz
- */
-static const struct rf_channel rf_vals_bg_2525e[] = {
-       { 1,  0x00022010, 0x0000089a, 0x00060111, 0x00000e1b },
-       { 2,  0x00022010, 0x0000089e, 0x00060111, 0x00000e07 },
-       { 3,  0x00022010, 0x0000089e, 0x00060111, 0x00000e1b },
-       { 4,  0x00022010, 0x000008a2, 0x00060111, 0x00000e07 },
-       { 5,  0x00022010, 0x000008a2, 0x00060111, 0x00000e1b },
-       { 6,  0x00022010, 0x000008a6, 0x00060111, 0x00000e07 },
-       { 7,  0x00022010, 0x000008a6, 0x00060111, 0x00000e1b },
-       { 8,  0x00022010, 0x000008aa, 0x00060111, 0x00000e07 },
-       { 9,  0x00022010, 0x000008aa, 0x00060111, 0x00000e1b },
-       { 10, 0x00022010, 0x000008ae, 0x00060111, 0x00000e07 },
-       { 11, 0x00022010, 0x000008ae, 0x00060111, 0x00000e1b },
-       { 12, 0x00022010, 0x000008b2, 0x00060111, 0x00000e07 },
-       { 13, 0x00022010, 0x000008b2, 0x00060111, 0x00000e1b },
-       { 14, 0x00022010, 0x000008b6, 0x00060111, 0x00000e23 },
-};
-
-/*
- * RF value list for RF5222
- * Supports: 2.4 GHz & 5.2 GHz
- */
-static const struct rf_channel rf_vals_5222[] = {
-       { 1,  0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
-       { 2,  0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
-       { 3,  0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
-       { 4,  0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
-       { 5,  0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
-       { 6,  0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
-       { 7,  0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
-       { 8,  0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
-       { 9,  0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
-       { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
-       { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
-       { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
-       { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
-       { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
-
-       /* 802.11 UNI / HyperLan 2 */
-       { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
-       { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
-       { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
-       { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
-       { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
-       { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
-       { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
-       { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
-
-       /* 802.11 HyperLan 2 */
-       { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
-       { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
-       { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
-       { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
-       { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
-       { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
-       { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
-       { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
-       { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
-       { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
-
-       /* 802.11 UNII */
-       { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
-       { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
-       { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
-       { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
-       { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
-};
-
-static void rt2500usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
-{
-       struct hw_mode_spec *spec = &rt2x00dev->spec;
-       u8 *txpower;
-       unsigned int i;
-
-       /*
-        * Initialize all hw fields.
-        */
-       rt2x00dev->hw->flags =
-           IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
-           IEEE80211_HW_RX_INCLUDES_FCS |
-           IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
-       rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
-       rt2x00dev->hw->max_signal = MAX_SIGNAL;
-       rt2x00dev->hw->max_rssi = MAX_RX_SSI;
-       rt2x00dev->hw->queues = 2;
-
-       SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_usb(rt2x00dev)->dev);
-       SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
-                               rt2x00_eeprom_addr(rt2x00dev,
-                                                  EEPROM_MAC_ADDR_0));
-
-       /*
-        * Convert tx_power array in eeprom.
-        */
-       txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
-       for (i = 0; i < 14; i++)
-               txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
-
-       /*
-        * Initialize hw_mode information.
-        */
-       spec->num_modes = 2;
-       spec->num_rates = 12;
-       spec->tx_power_a = NULL;
-       spec->tx_power_bg = txpower;
-       spec->tx_power_default = DEFAULT_TXPOWER;
-
-       if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
-               spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
-               spec->channels = rf_vals_bg_2522;
-       } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
-               spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
-               spec->channels = rf_vals_bg_2523;
-       } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
-               spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
-               spec->channels = rf_vals_bg_2524;
-       } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
-               spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
-               spec->channels = rf_vals_bg_2525;
-       } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
-               spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
-               spec->channels = rf_vals_bg_2525e;
-       } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
-               spec->num_channels = ARRAY_SIZE(rf_vals_5222);
-               spec->channels = rf_vals_5222;
-               spec->num_modes = 3;
-       }
-}
-
-static int rt2500usb_probe_hw(struct rt2x00_dev *rt2x00dev)
-{
-       int retval;
-
-       /*
-        * Allocate eeprom data.
-        */
-       retval = rt2500usb_validate_eeprom(rt2x00dev);
-       if (retval)
-               return retval;
-
-       retval = rt2500usb_init_eeprom(rt2x00dev);
-       if (retval)
-               return retval;
-
-       /*
-        * Initialize hw specifications.
-        */
-       rt2500usb_probe_hw_mode(rt2x00dev);
-
-       /*
-        * This device requires the beacon ring
-        */
-       __set_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags);
-
-       /*
-        * Set the rssi offset.
-        */
-       rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
-
-       return 0;
-}
-
-/*
- * IEEE80211 stack callback functions.
- */
-static void rt2500usb_configure_filter(struct ieee80211_hw *hw,
-                                      unsigned int changed_flags,
-                                      unsigned int *total_flags,
-                                      int mc_count,
-                                      struct dev_addr_list *mc_list)
-{
-       struct rt2x00_dev *rt2x00dev = hw->priv;
-       struct interface *intf = &rt2x00dev->interface;
-       u16 reg;
-
-       /*
-        * Mask off any flags we are going to ignore from
-        * the total_flags field.
-        */
-       *total_flags &=
-           FIF_ALLMULTI |
-           FIF_FCSFAIL |
-           FIF_PLCPFAIL |
-           FIF_CONTROL |
-           FIF_OTHER_BSS |
-           FIF_PROMISC_IN_BSS;
-
-       /*
-        * Apply some rules to the filters:
-        * - Some filters imply different filters to be set.
-        * - Some things we can't filter out at all.
-        * - Some filters are set based on interface type.
-        */
-       if (mc_count)
-               *total_flags |= FIF_ALLMULTI;
-       if (*total_flags & FIF_OTHER_BSS ||
-           *total_flags & FIF_PROMISC_IN_BSS)
-               *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
-       if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
-               *total_flags |= FIF_PROMISC_IN_BSS;
-
-       /*
-        * Check if there is any work left for us.
-        */
-       if (intf->filter == *total_flags)
-               return;
-       intf->filter = *total_flags;
-
-       /*
-        * When in atomic context, reschedule and let rt2x00lib
-        * call this function again.
-        */
-       if (in_atomic()) {
-               queue_work(rt2x00dev->hw->workqueue, &rt2x00dev->filter_work);
-               return;
-       }
-
-       /*
-        * Start configuration steps.
-        * Note that the version error will always be dropped
-        * and broadcast frames will always be accepted since
-        * there is no filter for it at this time.
-        */
-       rt2500usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
-       rt2x00_set_field16(&reg, TXRX_CSR2_DROP_CRC,
-                          !(*total_flags & FIF_FCSFAIL));
-       rt2x00_set_field16(&reg, TXRX_CSR2_DROP_PHYSICAL,
-                          !(*total_flags & FIF_PLCPFAIL));
-       rt2x00_set_field16(&reg, TXRX_CSR2_DROP_CONTROL,
-                          !(*total_flags & FIF_CONTROL));
-       rt2x00_set_field16(&reg, TXRX_CSR2_DROP_NOT_TO_ME,
-                          !(*total_flags & FIF_PROMISC_IN_BSS));
-       rt2x00_set_field16(&reg, TXRX_CSR2_DROP_TODS,
-                          !(*total_flags & FIF_PROMISC_IN_BSS));
-       rt2x00_set_field16(&reg, TXRX_CSR2_DROP_VERSION_ERROR, 1);
-       rt2x00_set_field16(&reg, TXRX_CSR2_DROP_MULTICAST,
-                          !(*total_flags & FIF_ALLMULTI));
-       rt2x00_set_field16(&reg, TXRX_CSR2_DROP_BROADCAST, 0);
-       rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg);
-}
-
-static int rt2500usb_beacon_update(struct ieee80211_hw *hw,
-                                  struct sk_buff *skb,
-                                  struct ieee80211_tx_control *control)
-{
-       struct rt2x00_dev *rt2x00dev = hw->priv;
-       struct usb_device *usb_dev =
-           interface_to_usbdev(rt2x00dev_usb(rt2x00dev));
-       struct data_ring *ring =
-           rt2x00lib_get_ring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
-       struct data_entry *beacon;
-       struct data_entry *guardian;
-       int pipe = usb_sndbulkpipe(usb_dev, 1);
-       int length;
-
-       /*
-        * Just in case the ieee80211 doesn't set this,
-        * but we need this queue set for the descriptor
-        * initialization.
-        */
-       control->queue = IEEE80211_TX_QUEUE_BEACON;
-
-       /*
-        * Obtain 2 entries, one for the guardian byte,
-        * the second for the actual beacon.
-        */
-       guardian = rt2x00_get_data_entry(ring);
-       rt2x00_ring_index_inc(ring);
-       beacon = rt2x00_get_data_entry(ring);
-
-       /*
-        * First we create the beacon.
-        */
-       skb_push(skb, ring->desc_size);
-       memset(skb->data, 0, ring->desc_size);
-
-       rt2x00lib_write_tx_desc(rt2x00dev, (struct data_desc *)skb->data,
-                               (struct ieee80211_hdr *)(skb->data +
-                                                        ring->desc_size),
-                               skb->len - ring->desc_size, control);
-
-       length = rt2500usb_get_tx_data_len(rt2x00dev, skb);
-
-       usb_fill_bulk_urb(beacon->priv, usb_dev, pipe,
-                         skb->data, length, rt2500usb_beacondone, beacon);
-
-       beacon->skb = skb;
-
-       /*
-        * Second we need to create the guardian byte.
-        * We only need a single byte, so lets recycle
-        * the 'flags' field we are not using for beacons.
-        */
-       guardian->flags = 0;
-       usb_fill_bulk_urb(guardian->priv, usb_dev, pipe,
-                         &guardian->flags, 1, rt2500usb_beacondone, guardian);
-
-       /*
-        * Send out the guardian byte.
-        */
-       usb_submit_urb(guardian->priv, GFP_ATOMIC);
-
-       /*
-        * Enable beacon generation.
-        */
-       rt2500usb_kick_tx_queue(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
-
-       return 0;
-}
-
-static const struct ieee80211_ops rt2500usb_mac80211_ops = {
-       .tx                     = rt2x00mac_tx,
-       .start                  = rt2x00mac_start,
-       .stop                   = rt2x00mac_stop,
-       .add_interface          = rt2x00mac_add_interface,
-       .remove_interface       = rt2x00mac_remove_interface,
-       .config                 = rt2x00mac_config,
-       .config_interface       = rt2x00mac_config_interface,
-       .configure_filter       = rt2500usb_configure_filter,
-       .get_stats              = rt2x00mac_get_stats,
-       .erp_ie_changed         = rt2x00mac_erp_ie_changed,
-       .conf_tx                = rt2x00mac_conf_tx,
-       .get_tx_stats           = rt2x00mac_get_tx_stats,
-       .beacon_update          = rt2500usb_beacon_update,
-};
-
-static const struct rt2x00lib_ops rt2500usb_rt2x00_ops = {
-       .probe_hw               = rt2500usb_probe_hw,
-       .initialize             = rt2x00usb_initialize,
-       .uninitialize           = rt2x00usb_uninitialize,
-       .set_device_state       = rt2500usb_set_device_state,
-       .link_stats             = rt2500usb_link_stats,
-       .reset_tuner            = rt2500usb_reset_tuner,
-       .link_tuner             = rt2500usb_link_tuner,
-       .write_tx_desc          = rt2500usb_write_tx_desc,
-       .write_tx_data          = rt2x00usb_write_tx_data,
-       .get_tx_data_len        = rt2500usb_get_tx_data_len,
-       .kick_tx_queue          = rt2500usb_kick_tx_queue,
-       .fill_rxdone            = rt2500usb_fill_rxdone,
-       .config_mac_addr        = rt2500usb_config_mac_addr,
-       .config_bssid           = rt2500usb_config_bssid,
-       .config_type            = rt2500usb_config_type,
-       .config_preamble        = rt2500usb_config_preamble,
-       .config                 = rt2500usb_config,
-};
-
-static const struct rt2x00_ops rt2500usb_ops = {
-       .name           = DRV_NAME,
-       .rxd_size       = RXD_DESC_SIZE,
-       .txd_size       = TXD_DESC_SIZE,
-       .eeprom_size    = EEPROM_SIZE,
-       .rf_size        = RF_SIZE,
-       .lib            = &rt2500usb_rt2x00_ops,
-       .hw             = &rt2500usb_mac80211_ops,