ar71xx: fix AR934X_EHCI_SIZE
authorGabor Juhos <juhosg@openwrt.org>
Thu, 2 Aug 2012 11:25:46 +0000 (11:25 +0000)
committerGabor Juhos <juhosg@openwrt.org>
Thu, 2 Aug 2012 11:25:46 +0000 (11:25 +0000)
SVN-Revision: 32947

target/linux/ar71xx/patches-3.3/134-MIPS-ath79-add-USB-platform-setup-code-for-AR934X.patch
target/linux/ar71xx/patches-3.3/167-MIPS-ath79-add-USB-controller-registration-code-for-.patch
target/linux/ar71xx/patches-3.3/168-MIPS-ath79-add-WMAC-registration-code-for-the-QCA955.patch
target/linux/ar71xx/patches-3.3/170-MIPS-ath79-add-PCI-controller-registration-code-for-.patch

index 2a287ec..c77de28 100644 (file)
@@ -60,7 +60,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  #define AR934X_WMAC_BASE      (AR71XX_APB_BASE + 0x00100000)
  #define AR934X_WMAC_SIZE      0x20000
 +#define AR934X_EHCI_BASE      0x1b000000
-+#define AR934X_EHCI_SIZE      0x1000
++#define AR934X_EHCI_SIZE      0x200
  
  /*
   * DDR_CTRL block
index c6b7814..386d57c 100644 (file)
@@ -82,7 +82,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 @@ -92,6 +92,10 @@
  #define AR934X_EHCI_BASE      0x1b000000
- #define AR934X_EHCI_SIZE      0x1000
+ #define AR934X_EHCI_SIZE      0x200
  
 +#define QCA955X_EHCI0_BASE    0x1b000000
 +#define QCA955X_EHCI1_BASE    0x1b400000
index f5dabad..6ff1034 100644 (file)
@@ -61,7 +61,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 @@ -92,6 +92,8 @@
  #define AR934X_EHCI_BASE      0x1b000000
- #define AR934X_EHCI_SIZE      0x1000
+ #define AR934X_EHCI_SIZE      0x200
  
 +#define QCA955X_WMAC_BASE     (AR71XX_APB_BASE + 0x00100000)
 +#define QCA955X_WMAC_SIZE     0x20000
index ccf25ed..c503a0d 100644 (file)
@@ -83,7 +83,7 @@ Subject: [PATCH 26/34] MIPS: ath79: add PCI controller registration code for the
 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 @@ -92,6 +92,19 @@
  #define AR934X_EHCI_BASE      0x1b000000
- #define AR934X_EHCI_SIZE      0x1000
+ #define AR934X_EHCI_SIZE      0x200
  
 +#define QCA955X_PCI_MEM_BASE0 0x10000000
 +#define QCA955X_PCI_MEM_BASE1 0x12000000