ar71xx: override fifo_cfg[123] values on AR7240
authorGabor Juhos <juhosg@openwrt.org>
Mon, 30 Nov 2009 13:53:39 +0000 (13:53 +0000)
committerGabor Juhos <juhosg@openwrt.org>
Mon, 30 Nov 2009 13:53:39 +0000 (13:53 +0000)
SVN-Revision: 18614

target/linux/ar71xx/files/arch/mips/ar71xx/mach-tl-wr741nd.c
target/linux/ar71xx/files/arch/mips/ar71xx/mach-ubnt.c
target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/platform.h
target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_main.c
target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_phy.c

index 10f7e8e..1d13ce9 100644 (file)
@@ -151,12 +151,18 @@ static void __init tl_wr741nd_setup(void)
        ar71xx_eth0_data.phy_mask = 0x0;
        ar71xx_eth0_data.speed = SPEED_100;
        ar71xx_eth0_data.duplex = DUPLEX_FULL;
+       ar71xx_eth0_data.fifo_cfg1 = 0x0fff0000;
+       ar71xx_eth0_data.fifo_cfg2 = 0x00001fff;
+       ar71xx_eth0_data.fifo_cfg3 = 0x008001ff;
 
        /* LAN ports */
        ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
        ar71xx_eth1_data.phy_mask = 0x0;
        ar71xx_eth1_data.speed = SPEED_1000;
        ar71xx_eth1_data.duplex = DUPLEX_FULL;
+       ar71xx_eth1_data.fifo_cfg1 = 0x0fff0000;
+       ar71xx_eth1_data.fifo_cfg2 = 0x00001fff;
+       ar71xx_eth1_data.fifo_cfg3 = 0x008001ff;
 
        ar71xx_add_device_eth(1);
        ar71xx_add_device_eth(0);
index 9b70f8d..371ac0f 100644 (file)
@@ -292,9 +292,11 @@ static void __init ubnt_m_setup(void)
 
        ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
        ar71xx_eth0_data.phy_mask = 0;
-
        ar71xx_eth0_data.speed = SPEED_100;
        ar71xx_eth0_data.duplex = DUPLEX_FULL;
+       ar71xx_eth0_data.fifo_cfg1 = 0x0010ffff;
+       ar71xx_eth0_data.fifo_cfg2 = 0x015500aa;
+       ar71xx_eth0_data.fifo_cfg3 = 0x01f00140;
 
        ar71xx_add_device_eth(0);
 
@@ -325,9 +327,11 @@ static void __init ubnt_nano_m_setup(void)
 
        ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
        ar71xx_eth1_data.phy_mask = 0;
-
        ar71xx_eth1_data.speed = SPEED_1000;
        ar71xx_eth1_data.duplex = DUPLEX_FULL;
+       ar71xx_eth1_data.fifo_cfg1 = 0x0010ffff;
+       ar71xx_eth1_data.fifo_cfg2 = 0x015500aa;
+       ar71xx_eth1_data.fifo_cfg3 = 0x01f00140;
 
        ar71xx_add_device_eth(1);
 }
index 52f41f4..baded8b 100644 (file)
@@ -33,6 +33,10 @@ struct ag71xx_platform_data {
 
        void            (* ddr_flush)(void);
        void            (* set_pll)(int speed);
+
+       u32             fifo_cfg1;
+       u32             fifo_cfg2;
+       u32             fifo_cfg3;
 };
 
 struct ag71xx_mdio_platform_data {
index 9442047..72d2acc 100644 (file)
@@ -402,8 +402,13 @@ static void ag71xx_hw_init(struct ag71xx *ag)
 
        /* setup FIFO configuration registers */
        ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
-       ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
-       ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
+       if (pdata->is_ar724x) {
+               ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
+               ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
+       } else {
+               ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
+               ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
+       }
        ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
        ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
 
index 6fe4d40..176edda 100644 (file)
@@ -72,8 +72,12 @@ static void ag71xx_phy_link_update(struct ag71xx *ag)
                return;
        }
 
-       ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3,
-                       pdata->is_ar91xx ? 0x780fff : 0x008001ff);
+       if (pdata->is_ar91xx)
+               ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff);
+       else if (pdata->is_ar724x)
+               ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3);
+       else
+               ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
 
        if (pdata->set_pll)
                pdata->set_pll(ag->speed);