define KernelPackage/leds-adm5120
SUBMENU:=$(OTHER_MENU)
TITLE:=ADM5120 LED support
- DEPENDS:=@TARGET_adm5120 +kmod-leds-gpio
+ DEPENDS:=@TARGET_adm5120 +kmod-leds-gpio @LINUX_2_6_25
KCONFIG:=CONFIG_LEDS_ADM5120
FILES:=$(LINUX_DIR)/drivers/leds/leds-adm5120.$(LINUX_KMOD_SUFFIX)
AUTOLOAD:=$(call AutoLoad,59,leds-adm5120)
BOARD:=adm5120
BOARDNAME:=Infineon/ADMtek ADM5120
-LINUX_VERSION:=2.6.25.12
+#LINUX_VERSION:=2.6.25.12
+LINUX_VERSION:=2.6.26
SUBTARGETS:=router_le router_be
INITRAMFS_EXTRA_FILES:=
--- /dev/null
+if ADM5120
+
+menu "ADM5120 Board selection"
+
+config ADM5120_MACH_CAS_771
+ bool "Cellvision CAS-771 support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_SOC_BGA
+ select ADM5120_OEM_CELLVISION
+ default y
+
+config ADM5120_MACH_NP27G
+ bool "Compex NP27G support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_SOC_BGA
+ select ADM5120_OEM_COMPEX
+ default y
+
+config ADM5120_MACH_NP28G
+ bool "Compex NP28G support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_SOC_BGA
+ select ADM5120_OEM_COMPEX
+ default y
+
+config ADM5120_MACH_WP54
+ bool "Compex WP54 family support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_SOC_BGA
+ select ADM5120_OEM_COMPEX
+ default y
+
+config ADM5120_MACH_BR_6104K
+ bool "Edimax BR-6104K support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_OEM_EDIMAX
+ default y
+
+config ADM5120_MACH_BR_6104KP
+ bool "Edimax BR-6104KP support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_OEM_EDIMAX
+ default y
+
+config ADM5120_MACH_BR_61X4WG
+ bool "Edimax BR-6104WG/6114WG support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_SOC_BGA
+ select ADM5120_OEM_EDIMAX
+ default y
+
+config ADM5120_MACH_EASY5120_RT
+ bool "Infineon EASY 5120-RT Reference Board support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_SOC_BGA
+ select ADM5120_OEM_INFINEON
+ default y
+
+config ADM5120_MACH_EASY5120_WVOIP
+ bool "Infineon EASY 5120-WVoIP Reference Board support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_SOC_BGA
+ select ADM5120_OEM_INFINEON
+ default y
+
+config ADM5120_MACH_EASY5120P_ATA
+ bool "Infineon EASY 5120P-ATA Reference Board support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_OEM_INFINEON
+ default y
+
+config ADM5120_MACH_EASY83000
+ bool "Infineon EASY 83000 Reference Board support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_OEM_INFINEON
+ default y
+
+config ADM5120_MACH_RB_11X
+ bool "MikroTik RouterBOARD 111/112 support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_SOC_BGA
+ select ADM5120_OEM_MIKROTIK
+ default y
+
+config ADM5120_MACH_RB_133
+ bool "MikroTik RouterBOARD 133 support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_SOC_BGA
+ select ADM5120_OEM_MIKROTIK
+ default y
+
+config ADM5120_MACH_RB_133C
+ bool "MikroTik RouterBOARD 133C support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_SOC_BGA
+ select ADM5120_OEM_MIKROTIK
+ default y
+
+config ADM5120_MACH_RB_150
+ bool "MikroTik RouterBOARD 150 support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_OEM_MIKROTIK
+ default y
+
+config ADM5120_MACH_RB_153
+ bool "MikroTik RouterBOARD 153 support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_SOC_BGA
+ select ADM5120_OEM_MIKROTIK
+ default y
+
+config ADM5120_MACH_RB_192
+ bool "MikroTik RouterBOARD 192 support"
+ depends on CPU_LITTLE_ENDIAN
+ select ADM5120_SOC_BGA
+ select ADM5120_OEM_MIKROTIK
+ default y
+
+config ADM5120_MACH_P_334WT
+ bool "ZyXEL Prestige 334WT"
+ depends on CPU_BIG_ENDIAN
+ select ADM5120_SOC_BGA
+ select ADM5120_OEM_ZYXEL
+ default y
+
+config ADM5120_MACH_P_335
+ bool "ZyXEL Prestige 335/335WT"
+ depends on CPU_BIG_ENDIAN
+ select ADM5120_SOC_BGA
+ select ADM5120_OEM_ZYXEL
+ default y
+
+endmenu
+
+config ADM5120_SOC_BGA
+ select HW_HAS_PCI
+ def_bool n
+
+config ADM5120_OEM_CELLVISION
+ def_bool n
+
+config ADM5120_OEM_COMPEX
+ def_bool n
+
+config ADM5120_OEM_EDIMAX
+ def_bool n
+
+config ADM5120_OEM_INFINEON
+ def_bool n
+
+config ADM5120_OEM_MIKROTIK
+ def_bool n
+
+config ADM5120_OEM_ZYXEL
+ def_bool n
+
+config ARM_AMBA
+ def_bool y
+
+endif
--- /dev/null
+obj-y += cellvision.o
\ No newline at end of file
--- /dev/null
+/*
+ * Cellvision/SparkLAN boards
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+
+#include <asm/bootinfo.h>
+
+#include <asm/mach-adm5120/adm5120_info.h>
+#include <asm/mach-adm5120/adm5120_board.h>
+#include <asm/mach-adm5120/adm5120_platform.h>
+#include <asm/mach-adm5120/adm5120_irq.h>
+
+#define CELLVISION_GPIO_FLASH_A20 ADM5120_GPIO_PIN5
+#define CELLVISION_GPIO_DEV_MASK (1 << CELLVISION_GPIO_FLASH_A20)
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition cas6xx_partitions[] = {
+ {
+ .name = "admboot",
+ .offset = 0,
+ .size = 32*1024,
+ .mask_flags = MTD_WRITEABLE,
+ } , {
+ .name = "config",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 32*1024,
+ } , {
+ .name = "nvfs1",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 64*1024,
+ } , {
+ .name = "nvfs2",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 64*1024,
+ } , {
+ .name = "firmware",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+
+static struct mtd_partition cas7xx_partitions[] = {
+ {
+ .name = "admboot",
+ .offset = 0,
+ .size = 32*1024,
+ .mask_flags = MTD_WRITEABLE,
+ } , {
+ .name = "config",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 32*1024,
+ } , {
+ .name = "nvfs",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 128*1024,
+ } , {
+ .name = "firmware",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+#endif /* CONFIG_MTD_PARTITIONS */
+
+static struct adm5120_pci_irq cas771_pci_irqs[] __initdata = {
+ PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0),
+ PCIIRQ(3, 0, 1, ADM5120_IRQ_PCI1),
+ PCIIRQ(3, 2, 3, ADM5120_IRQ_PCI2)
+};
+
+static struct gpio_led cas771_gpio_leds[] __initdata = {
+ GPIO_LED_STD(ADM5120_GPIO_PIN0, "cam_flash", NULL),
+ /* GPIO PIN3 is the reset */
+ GPIO_LED_STD(ADM5120_GPIO_PIN6, "access", NULL),
+ GPIO_LED_STD(ADM5120_GPIO_P0L1, "status", NULL),
+ GPIO_LED_STD(ADM5120_GPIO_P0L2, "diag", NULL),
+};
+
+static void switch_bank_gpio5(unsigned bank)
+{
+ switch (bank) {
+ case 0:
+ gpio_set_value(CELLVISION_GPIO_FLASH_A20, 0);
+ break;
+ case 1:
+ gpio_set_value(CELLVISION_GPIO_FLASH_A20, 1);
+ break;
+ }
+}
+
+static void __init cellvision_generic_setup(void)
+{
+ /* setup flash A20 line */
+ gpio_request(CELLVISION_GPIO_FLASH_A20, NULL);
+ gpio_direction_output(CELLVISION_GPIO_FLASH_A20, 0);
+
+ adm5120_flash0_data.switch_bank = switch_bank_gpio5;
+ adm5120_add_device_flash(0);
+}
+
+static void __init cas6xx_setup(void)
+{
+#ifdef CONFIG_MTD_PARTITIONS
+ adm5120_flash0_data.nr_parts = ARRAY_SIZE(cas6xx_partitions);
+ adm5120_flash0_data.parts = cas6xx_partitions;
+#endif /* CONFIG_MTD_PARTITIONS */
+ cellvision_generic_setup();
+
+ adm5120_add_device_switch(1, NULL);
+}
+
+ADM5120_BOARD(MACH_ADM5120_CAS630, "Cellvision CAS-630/630W", cas6xx_setup);
+ADM5120_BOARD(MACH_ADM5120_CAS670, "Cellvision CAS-670/670W", cas6xx_setup);
+
+static void __init cas7xx_setup(void)
+{
+#ifdef CONFIG_MTD_PARTITIONS
+ adm5120_flash0_data.nr_parts = ARRAY_SIZE(cas7xx_partitions);
+ adm5120_flash0_data.parts = cas7xx_partitions;
+#endif /* CONFIG_MTD_PARTITIONS */
+
+ adm5120_add_device_switch(1, NULL);
+}
+
+ADM5120_BOARD(MACH_ADM5120_CAS700, "Cellvision CAS-700/700W", cas7xx_setup);
+ADM5120_BOARD(MACH_ADM5120_CAS790, "Cellvision CAS-790", cas7xx_setup);
+ADM5120_BOARD(MACH_ADM5120_CAS861, "Cellvision CAS-861/861W", cas7xx_setup);
+
+static void __init cas771_setup(void)
+{
+ cas7xx_setup();
+ adm5120_add_device_gpio_leds(ARRAY_SIZE(cas771_gpio_leds),
+ cas771_gpio_leds);
+ adm5120_pci_set_irq_map(ARRAY_SIZE(cas771_pci_irqs), cas771_pci_irqs);
+}
+
+ADM5120_BOARD(MACH_ADM5120_CAS771, "Cellvision CAS-771/771W", cas771_setup);
+
+static u8 nfs_vlans[6] __initdata = { /* TODO: not tested */
+ 0x41, 0x42, 0x44, 0x48, 0x50, 0x00
+};
+
+static void __init nfs_setup(void)
+{
+#ifdef CONFIG_MTD_PARTITIONS
+ adm5120_flash0_data.nr_parts = ARRAY_SIZE(cas6xx_partitions);
+ adm5120_flash0_data.parts = cas6xx_partitions;
+#endif /* CONFIG_MTD_PARTITIONS */
+
+ cellvision_generic_setup();
+ adm5120_add_device_switch(5, nfs_vlans);
+
+ /* TODO: add PCI IRQ map */
+}
+
+ADM5120_BOARD(MACH_ADM5120_NFS101U, "Cellvision NFS-101U/101WU", nfs_setup);
--- /dev/null
+#
+# Makefile for the Infineon/ADMtek ADM5120 SoC specific parts of the kernel
+#
+
+obj-y := adm5120.o setup.o prom.o irq.o memory.o board.o clock.o \
+ gpio.o platform.o
--- /dev/null
+/*
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+
+#include <asm/bootinfo.h>
+#include <asm/addrspace.h>
+
+#include <asm/mach-adm5120/adm5120_info.h>
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <asm/mach-adm5120/adm5120_switch.h>
+
+unsigned int adm5120_product_code;
+unsigned int adm5120_revision;
+unsigned int adm5120_package;
+unsigned int adm5120_nand_boot;
+unsigned long adm5120_speed;
+
+/*
+ * CPU settings detection
+ */
+#define CODE_GET_PC(c) ((c) & CODE_PC_MASK)
+#define CODE_GET_REV(c) (((c) >> CODE_REV_SHIFT) & CODE_REV_MASK)
+#define CODE_GET_PK(c) (((c) >> CODE_PK_SHIFT) & CODE_PK_MASK)
+#define CODE_GET_CLKS(c) (((c) >> CODE_CLKS_SHIFT) & CODE_CLKS_MASK)
+#define CODE_GET_NAB(c) (((c) & CODE_NAB) != 0)
+
+void adm5120_ndelay(u32 ns)
+{
+ u32 t;
+
+ SW_WRITE_REG(SWITCH_REG_TIMER, TIMER_PERIOD_DEFAULT);
+ SW_WRITE_REG(SWITCH_REG_TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM));
+
+ t = (ns+640) / 640;
+ t &= TIMER_PERIOD_MASK;
+ SW_WRITE_REG(SWITCH_REG_TIMER, t | TIMER_TE);
+
+ /* wait until the timer expires */
+ do {
+ t = SW_READ_REG(SWITCH_REG_TIMER_INT);
+ } while ((t & TIMER_INT_TOS) == 0);
+
+ /* leave the timer disabled */
+ SW_WRITE_REG(SWITCH_REG_TIMER, TIMER_PERIOD_DEFAULT);
+ SW_WRITE_REG(SWITCH_REG_TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM));
+}
+
+void __init adm5120_soc_init(void)
+{
+ u32 code;
+ u32 clks;
+
+ code = SW_READ_REG(SWITCH_REG_CODE);
+
+ adm5120_product_code = CODE_GET_PC(code);
+ adm5120_revision = CODE_GET_REV(code);
+ adm5120_package = (CODE_GET_PK(code) == CODE_PK_BGA) ?
+ ADM5120_PACKAGE_BGA : ADM5120_PACKAGE_PQFP;
+ adm5120_nand_boot = CODE_GET_NAB(code);
+
+ clks = CODE_GET_CLKS(code);
+ adm5120_speed = ADM5120_SPEED_175;
+ if (clks & 1)
+ adm5120_speed += 25000000;
+ if (clks & 2)
+ adm5120_speed += 50000000;
+}
--- /dev/null
+/*
+ * ADM5120 generic board code
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+
+#include <asm/bootinfo.h>
+
+#include <asm/mach-adm5120/adm5120_info.h>
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <asm/mach-adm5120/adm5120_irq.h>
+#include <asm/mach-adm5120/adm5120_board.h>
+#include <asm/mach-adm5120/adm5120_platform.h>
+
+#define PFX "ADM5120: "
+
+static struct list_head adm5120_boards __initdata =
+ LIST_HEAD_INIT(adm5120_boards);
+
+static char adm5120_board_name[ADM5120_BOARD_NAMELEN] = "Unknown board";
+
+const char *get_system_type(void)
+{
+ return adm5120_board_name;
+}
+
+static struct adm5120_board * __init adm5120_board_find(unsigned long machtype)
+{
+ struct list_head *this;
+
+ list_for_each(this, &adm5120_boards) {
+ struct adm5120_board *board;
+
+ board = list_entry(this, struct adm5120_board, list);
+ if (board->mach_type == machtype)
+ return board;
+ }
+
+ return NULL;
+}
+
+static int __init adm5120_board_setup(void)
+{
+ struct adm5120_board *board;
+
+ board = adm5120_board_find(mips_machtype);
+ if (board == NULL)
+ panic(PFX "no board registered for machtype %lu\n",
+ mips_machtype);
+
+ if (board->name[0])
+ memcpy(adm5120_board_name, board->name, ADM5120_BOARD_NAMELEN);
+
+ printk(KERN_INFO PFX "board is '%s'\n", board->name);
+
+ adm5120_gpio_init();
+
+ adm5120_add_device_uart(0);
+ adm5120_add_device_uart(1);
+
+ if (board->board_setup)
+ board->board_setup();
+
+ return 0;
+}
+arch_initcall(adm5120_board_setup);
+
+void __init adm5120_board_register(struct adm5120_board *board)
+{
+ list_add_tail(&board->list, &adm5120_boards);
+}
+
+static void __init adm5120_generic_board_setup(void)
+{
+ adm5120_add_device_flash(0);
+ adm5120_add_device_switch(6, NULL);
+}
+
+ADM5120_BOARD(MACH_ADM5120_GENERIC, "Generic ADM5120 board",
+ adm5120_generic_board_setup);
--- /dev/null
+/*
+ * ADM5120 minimal CLK API implementation
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This file was based on the CLK API implementation in:
+ * arch/mips/tx4938/toshiba_rbtx4938/setup.c
+ * Copyright (C) 2000-2001 Toshiba Corporation
+ * 2003-2005 (c) MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+
+#include <asm/mach-adm5120/adm5120_defs.h>
+
+struct clk {
+ unsigned long rate;
+};
+
+static struct clk uart_clk = {
+ .rate = ADM5120_UART_CLOCK
+};
+
+struct clk *clk_get(struct device *dev, const char *id)
+{
+ if (!strcmp(id, "UARTCLK"))
+ return &uart_clk;
+
+ return ERR_PTR(-ENOENT);
+}
+EXPORT_SYMBOL(clk_get);
+
+int clk_enable(struct clk *clk)
+{
+ return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_disable);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+ return clk->rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+void clk_put(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_put);
--- /dev/null
+/*
+ * ADM5120 generic GPIO API support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/autoconf.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <asm/addrspace.h>
+#include <linux/gpio.h>
+
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <asm/mach-adm5120/adm5120_info.h>
+#include <asm/mach-adm5120/adm5120_switch.h>
+#include <asm/mach-adm5120/adm5120_irq.h>
+
+#define GPIO_READ(r) __raw_readl((r))
+#define GPIO_WRITE(v, r) __raw_writel((v), (r))
+#define GPIO_REG(r) (void __iomem *)(KSEG1ADDR(ADM5120_SWITCH_BASE)+r)
+
+struct adm5120_gpio_line {
+ u32 flags;
+ const char *label;
+ int irq;
+};
+
+#define GPIO_FLAG_VALID 0x01
+#define GPIO_FLAG_USED 0x02
+
+struct led_desc {
+ void __iomem *reg; /* LED register address */
+ u8 iv_shift; /* shift amount for input bit */
+ u8 mode_shift; /* shift amount for mode bits */
+};
+
+#define LED_DESC(p, l) { \
+ .reg = GPIO_REG(SWITCH_REG_PORT0_LED+((p) * 4)), \
+ .iv_shift = LED0_IV_SHIFT + (l), \
+ .mode_shift = (l) * 4 \
+ }
+
+static struct led_desc led_table[15] = {
+ LED_DESC(0, 0), LED_DESC(0, 1), LED_DESC(0, 2),
+ LED_DESC(1, 0), LED_DESC(1, 1), LED_DESC(1, 2),
+ LED_DESC(2, 0), LED_DESC(2, 1), LED_DESC(2, 2),
+ LED_DESC(3, 0), LED_DESC(3, 1), LED_DESC(3, 2),
+ LED_DESC(4, 0), LED_DESC(4, 1), LED_DESC(4, 2)
+};
+
+static struct adm5120_gpio_line adm5120_gpio_map[ADM5120_GPIO_COUNT];
+
+static u32 gpio_conf2;
+
+/*-------------------------------------------------------------------------*/
+
+static inline int gpio_is_invalid(unsigned gpio)
+{
+ if ((gpio > ADM5120_GPIO_MAX) ||
+ (adm5120_gpio_map[gpio].flags & GPIO_FLAG_VALID) == 0)
+ return 1;
+
+ return 0;
+}
+
+static inline int gpio_is_used(unsigned gpio)
+{
+ return ((adm5120_gpio_map[gpio].flags & GPIO_FLAG_USED) != 0);
+}
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * Helpers for GPIO lines in GPIO_CONF0 register
+ */
+#define PIN_IM(p) ((1 << GPIO_CONF0_IM_SHIFT) << p)
+#define PIN_IV(p) ((1 << GPIO_CONF0_IV_SHIFT) << p)
+#define PIN_OE(p) ((1 << GPIO_CONF0_OE_SHIFT) << p)
+#define PIN_OV(p) ((1 << GPIO_CONF0_OV_SHIFT) << p)
+
+static inline int pins_direction_input(unsigned pin)
+{
+ void __iomem **reg;
+ u32 t;
+
+ reg = GPIO_REG(SWITCH_REG_GPIO_CONF0);
+
+ t = GPIO_READ(reg);
+ t &= ~(PIN_OE(pin));
+ t |= PIN_IM(pin);
+ GPIO_WRITE(t, reg);
+
+ return 0;
+}
+
+static inline int pins_direction_output(unsigned pin, int value)
+{
+ void __iomem **reg;
+ u32 t;
+
+ reg = GPIO_REG(SWITCH_REG_GPIO_CONF0);
+
+ t = GPIO_READ(reg);
+ t &= ~(PIN_IM(pin) | PIN_OV(pin));
+ t |= PIN_OE(pin);
+
+ if (value)
+ t |= PIN_OV(pin);
+
+ GPIO_WRITE(t, reg);
+
+ return 0;
+}
+
+static inline int pins_get_value(unsigned pin)
+{
+ void __iomem **reg;
+ u32 t;
+
+ reg = GPIO_REG(SWITCH_REG_GPIO_CONF0);
+
+ t = GPIO_READ(reg);
+ if ((t & PIN_IM(pin)) != 0)
+ t &= PIN_IV(pin);
+ else
+ t &= PIN_OV(pin);
+
+ return (t) ? 1 : 0;
+}
+
+static inline void pins_set_value(unsigned pin, int value)
+{
+ void __iomem **reg;
+ u32 t;
+
+ reg = GPIO_REG(SWITCH_REG_GPIO_CONF0);
+
+ t = GPIO_READ(reg);
+ if (value == 0)
+ t &= ~(PIN_OV(pin));
+ else
+ t |= PIN_OV(pin);
+
+ GPIO_WRITE(t, reg);
+}
+
+/*
+ * Helpers for GPIO lines in PORTx_LED registers
+ */
+static inline int leds_direction_input(unsigned led)
+{
+ void __iomem **reg;
+ u32 t;
+
+ reg = led_table[led].reg;
+ t = GPIO_READ(reg);
+ t &= ~(LED_MODE_MASK << led_table[led].mode_shift);
+ GPIO_WRITE(t, reg);
+
+ return 0;
+}
+
+static inline int leds_direction_output(unsigned led, int value)
+{
+ void __iomem **reg;
+ u32 t, s;
+
+ reg = led_table[led].reg;
+ s = led_table[led].mode_shift;
+
+ t = GPIO_READ(reg);
+ t &= ~(LED_MODE_MASK << s);
+
+ switch (value) {
+ case ADM5120_GPIO_LOW:
+ t |= (LED_MODE_OUT_LOW << s);
+ break;
+ case ADM5120_GPIO_FLASH:
+ case ADM5120_GPIO_LINK:
+ case ADM5120_GPIO_SPEED:
+ case ADM5120_GPIO_DUPLEX:
+ case ADM5120_GPIO_ACT:
+ case ADM5120_GPIO_COLL:
+ case ADM5120_GPIO_LINK_ACT:
+ case ADM5120_GPIO_DUPLEX_COLL:
+ case ADM5120_GPIO_10M_ACT:
+ case ADM5120_GPIO_100M_ACT:
+ t |= ((value & LED_MODE_MASK) << s);
+ break;
+ default:
+ t |= (LED_MODE_OUT_HIGH << s);
+ break;
+ }
+
+ GPIO_WRITE(t, reg);
+
+ return 0;
+}
+
+static inline int leds_get_value(unsigned led)
+{
+ void __iomem **reg;
+ u32 t, m;
+
+ reg = led_table[led].reg;
+
+ t = GPIO_READ(reg);
+ m = (t >> led_table[led].mode_shift) & LED_MODE_MASK;
+ if (m == LED_MODE_INPUT)
+ return (t >> led_table[led].iv_shift) & 1;
+
+ if (m == LED_MODE_OUT_LOW)
+ return 0;
+
+ return 1;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * Main GPIO support routines
+ */
+int adm5120_gpio_direction_input(unsigned gpio)
+{
+ if (gpio_is_invalid(gpio))
+ return -EINVAL;
+
+ if (gpio < ADM5120_GPIO_P0L0)
+ return pins_direction_input(gpio);
+
+ gpio -= ADM5120_GPIO_P0L0;
+ return leds_direction_input(gpio);
+}
+EXPORT_SYMBOL(adm5120_gpio_direction_input);
+
+int adm5120_gpio_direction_output(unsigned gpio, int value)
+{
+ if (gpio_is_invalid(gpio))
+ return -EINVAL;
+
+ if (gpio < ADM5120_GPIO_P0L0)
+ return pins_direction_output(gpio, value);
+
+ gpio -= ADM5120_GPIO_P0L0;
+ return leds_direction_output(gpio, value);
+}
+EXPORT_SYMBOL(adm5120_gpio_direction_output);
+
+int adm5120_gpio_get_value(unsigned gpio)
+{
+ if (gpio < ADM5120_GPIO_P0L0)
+ return pins_get_value(gpio);
+
+ gpio -= ADM5120_GPIO_P0L0;
+ return leds_get_value(gpio);
+}
+EXPORT_SYMBOL(adm5120_gpio_get_value);
+
+void adm5120_gpio_set_value(unsigned gpio, int value)
+{
+ if (gpio < ADM5120_GPIO_P0L0) {
+ pins_set_value(gpio, value);
+ return;
+ }
+
+ gpio -= ADM5120_GPIO_P0L0;
+ leds_direction_output(gpio, value);
+}
+EXPORT_SYMBOL(adm5120_gpio_set_value);
+
+int adm5120_gpio_request(unsigned gpio, const char *label)
+{
+ if (gpio_is_invalid(gpio))
+ return -EINVAL;
+
+ if (gpio_is_used(gpio))
+ return -EBUSY;
+
+ adm5120_gpio_map[gpio].flags |= GPIO_FLAG_USED;
+ adm5120_gpio_map[gpio].label = label;
+
+ return 0;
+}
+EXPORT_SYMBOL(adm5120_gpio_request);
+
+void adm5120_gpio_free(unsigned gpio)
+{
+ if (gpio_is_invalid(gpio))
+ return;
+
+ adm5120_gpio_map[gpio].flags &= ~GPIO_FLAG_USED;
+ adm5120_gpio_map[gpio].label = NULL;
+}
+EXPORT_SYMBOL(adm5120_gpio_free);
+
+int adm5120_gpio_to_irq(unsigned gpio)
+{
+ if (gpio > ADM5120_GPIO_MAX)
+ return -EINVAL;
+
+ return adm5120_gpio_map[gpio].irq;
+}
+EXPORT_SYMBOL(adm5120_gpio_to_irq);
+
+int adm5120_irq_to_gpio(unsigned irq)
+{
+ int i;
+
+ for (i = 0; i < ADM5120_GPIO_COUNT; i++)
+ if (adm5120_gpio_map[i].irq == irq)
+ return i;
+
+ return -EINVAL;
+}
+EXPORT_SYMBOL(adm5120_irq_to_gpio);
+
+/*-------------------------------------------------------------------------*/
+
+void __init adm5120_gpio_csx0_enable(void)
+{
+ gpio_conf2 |= GPIO_CONF2_CSX0;
+ SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2);
+
+ adm5120_gpio_map[ADM5120_GPIO_PIN1].flags &= ~GPIO_FLAG_VALID;
+ adm5120_gpio_map[ADM5120_GPIO_PIN2].irq = ADM5120_IRQ_GPIO2;
+}
+
+void __init adm5120_gpio_csx1_enable(void)
+{
+ gpio_conf2 |= GPIO_CONF2_CSX1;
+ SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2);
+
+ adm5120_gpio_map[ADM5120_GPIO_PIN3].flags &= ~GPIO_FLAG_VALID;
+ if (adm5120_package_bga())
+ adm5120_gpio_map[ADM5120_GPIO_PIN4].irq = ADM5120_IRQ_GPIO4;
+}
+
+void __init adm5120_gpio_ew_enable(void)
+{
+ gpio_conf2 |= GPIO_CONF2_EW;
+ SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2);
+
+ adm5120_gpio_map[ADM5120_GPIO_PIN0].flags &= ~GPIO_FLAG_VALID;
+}
+
+void __init adm5120_gpio_init(void)
+{
+ int i;
+
+ gpio_conf2 = 0;
+ SW_WRITE_REG(SWITCH_REG_GPIO_CONF2, gpio_conf2);
+
+ for (i = 0; i < ADM5120_GPIO_COUNT; i++)
+ adm5120_gpio_map[i].flags = GPIO_FLAG_VALID;
+
+ if (adm5120_package_pqfp()) {
+ adm5120_gpio_map[ADM5120_GPIO_PIN4].flags &= ~GPIO_FLAG_VALID;
+ adm5120_gpio_map[ADM5120_GPIO_PIN5].flags &= ~GPIO_FLAG_VALID;
+ adm5120_gpio_map[ADM5120_GPIO_PIN6].flags &= ~GPIO_FLAG_VALID;
+ adm5120_gpio_map[ADM5120_GPIO_PIN7].flags &= ~GPIO_FLAG_VALID;
+ }
+}
--- /dev/null
+/*
+ * ADM5120 specific interrupt handlers
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+
+#include <asm/irq.h>
+#include <asm/irq_cpu.h>
+#include <asm/mipsregs.h>
+#include <asm/bitops.h>
+
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <asm/mach-adm5120/adm5120_irq.h>
+
+static void adm5120_intc_irq_unmask(unsigned int irq);
+static void adm5120_intc_irq_mask(unsigned int irq);
+static int adm5120_intc_irq_set_type(unsigned int irq, unsigned int flow_type);
+
+static inline void intc_write_reg(unsigned int reg, u32 val)
+{
+ void __iomem *base = (void __iomem *)KSEG1ADDR(ADM5120_INTC_BASE);
+
+ __raw_writel(val, base + reg);
+}
+
+static inline u32 intc_read_reg(unsigned int reg)
+{
+ void __iomem *base = (void __iomem *)KSEG1ADDR(ADM5120_INTC_BASE);
+
+ return __raw_readl(base + reg);
+}
+
+static struct irq_chip adm5120_intc_irq_chip = {
+ .name = "INTC",
+ .unmask = adm5120_intc_irq_unmask,
+ .mask = adm5120_intc_irq_mask,
+ .mask_ack = adm5120_intc_irq_mask,
+ .set_type = adm5120_intc_irq_set_type
+};
+
+static struct irqaction adm5120_intc_irq_action = {
+ .handler = no_action,
+ .name = "cascade [INTC]"
+};
+
+static void adm5120_intc_irq_unmask(unsigned int irq)
+{
+ irq -= ADM5120_INTC_IRQ_BASE;
+ intc_write_reg(INTC_REG_IRQ_ENABLE, 1 << irq);
+}
+
+static void adm5120_intc_irq_mask(unsigned int irq)
+{
+ irq -= ADM5120_INTC_IRQ_BASE;
+ intc_write_reg(INTC_REG_IRQ_DISABLE, 1 << irq);
+}
+
+static int adm5120_intc_irq_set_type(unsigned int irq, unsigned int flow_type)
+{
+ unsigned int sense;
+ unsigned long mode;
+ int err = 0;
+
+ sense = flow_type & (IRQ_TYPE_SENSE_MASK);
+ switch (sense) {
+ case IRQ_TYPE_NONE:
+ case IRQ_TYPE_LEVEL_HIGH:
+ break;
+ case IRQ_TYPE_LEVEL_LOW:
+ switch (irq) {
+ case ADM5120_IRQ_GPIO2:
+ case ADM5120_IRQ_GPIO4:
+ break;
+ default:
+ err = -EINVAL;
+ break;
+ }
+ break;
+ default:
+ err = -EINVAL;
+ break;
+ }
+
+ if (err)
+ return err;
+
+ switch (irq) {
+ case ADM5120_IRQ_GPIO2:
+ case ADM5120_IRQ_GPIO4:
+ mode = intc_read_reg(INTC_REG_INT_MODE);
+ if (sense == IRQ_TYPE_LEVEL_LOW)
+ mode |= (1 << (irq - ADM5120_INTC_IRQ_BASE));
+ else
+ mode &= ~(1 << (irq - ADM5120_INTC_IRQ_BASE));
+
+ intc_write_reg(INTC_REG_INT_MODE, mode);
+ /* fallthrough */
+ default:
+ irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
+ irq_desc[irq].status |= sense;
+ break;
+ }
+
+ return 0;
+}
+
+static void adm5120_intc_irq_dispatch(void)
+{
+ unsigned long status;
+ int irq;
+
+ /* dispatch only one IRQ at a time */
+ status = intc_read_reg(INTC_REG_IRQ_STATUS) & INTC_INT_ALL;
+
+ if (status) {
+ irq = ADM5120_INTC_IRQ_BASE + fls(status) - 1;
+ do_IRQ(irq);
+ } else
+ spurious_interrupt();
+}
+
+asmlinkage void plat_irq_dispatch(void)
+{
+ unsigned long pending;
+
+ pending = read_c0_status() & read_c0_cause() & ST0_IM;
+
+ if (pending & STATUSF_IP7)
+ do_IRQ(ADM5120_IRQ_COUNTER);
+ else if (pending & STATUSF_IP2)
+ adm5120_intc_irq_dispatch();
+ else
+ spurious_interrupt();
+}
+
+#define INTC_IRQ_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED)
+static void __init adm5120_intc_irq_init(void)
+{
+ int i;
+
+ /* disable all interrupts */
+ intc_write_reg(INTC_REG_IRQ_DISABLE, INTC_INT_ALL);
+
+ /* setup all interrupts to generate IRQ instead of FIQ */
+ intc_write_reg(INTC_REG_INT_MODE, 0);
+
+ /* set active level for all external interrupts to HIGH */
+ intc_write_reg(INTC_REG_INT_LEVEL, 0);
+
+ /* disable usage of the TEST_SOURCE register */
+ intc_write_reg(INTC_REG_IRQ_SOURCE_SELECT, 0);
+
+ for (i = ADM5120_INTC_IRQ_BASE;
+ i <= ADM5120_INTC_IRQ_BASE + INTC_IRQ_LAST;
+ i++) {
+ irq_desc[i].status = INTC_IRQ_STATUS;
+ set_irq_chip_and_handler(i, &adm5120_intc_irq_chip,
+ handle_level_irq);
+ }
+
+ setup_irq(ADM5120_IRQ_INTC, &adm5120_intc_irq_action);
+}
+
+void __init arch_init_irq(void) {
+ mips_cpu_irq_init();
+ adm5120_intc_irq_init();
+}
--- /dev/null
+/*
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include <asm/bootinfo.h>
+#include <asm/addrspace.h>
+
+#include <asm/mach-adm5120/adm5120_info.h>
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <asm/mach-adm5120/adm5120_switch.h>
+#include <asm/mach-adm5120/adm5120_mpmc.h>
+
+#ifdef DEBUG
+# define mem_dbg(f, a...) printk(KERN_INFO "mem_detect: " f, ## a)
+#else
+# define mem_dbg(f, a...)
+#endif
+
+unsigned long adm5120_memsize;
+
+#define MEM_READL(a) __raw_readl((void __iomem *)(a))
+#define MEM_WRITEL(a, v) __raw_writel((v), (void __iomem *)(a))
+
+static int __init mem_check_pattern(u8 *addr, unsigned long offs)
+{
+ u32 *p1 = (u32 *)addr;
+ u32 *p2 = (u32 *)(addr+offs);
+ u32 t, u, v;
+
+ /* save original value */
+ t = MEM_READL(p1);
+
+ u = MEM_READL(p2);
+ if (t != u)
+ return 0;
+
+ v = 0x55555555;
+ if (u == v)
+ v = 0xAAAAAAAA;
+
+ mem_dbg("write 0x%08X to 0x%08lX\n", v, (unsigned long)p1);
+
+ MEM_WRITEL(p1, v);
+ adm5120_ndelay(1000);
+ u = MEM_READL(p2);
+
+ mem_dbg("pattern at 0x%08lX is 0x%08X\n", (unsigned long)p2, u);
+
+ /* restore original value */
+ MEM_WRITEL(p1, t);
+
+ return (v == u);
+}
+
+static void __init adm5120_detect_memsize(void)
+{
+ u32 memctrl;
+ u32 size, maxsize;
+ u8 *p;
+
+ memctrl = SW_READ_REG(SWITCH_REG_MEMCTRL);
+ switch (memctrl & MEMCTRL_SDRS_MASK) {
+ case MEMCTRL_SDRS_4M:
+ maxsize = 4 << 20;
+ break;
+ case MEMCTRL_SDRS_8M:
+ maxsize = 8 << 20;
+ break;
+ case MEMCTRL_SDRS_16M:
+ maxsize = 16 << 20;
+ break;
+ default:
+ maxsize = 64 << 20;
+ break;
+ }
+
+ mem_dbg("checking for %uMB chip in 1st bank\n", maxsize >> 20);
+
+ /* detect size of the 1st SDRAM bank */
+ p = (u8 *)KSEG1ADDR(0);
+ for (size = 2<<20; size <= (maxsize >> 1); size <<= 1) {
+ if (mem_check_pattern(p, size)) {
+ /* mirrored address */
+ mem_dbg("mirrored data found at offset 0x%08X\n", size);
+ break;
+ }
+ }
+
+ mem_dbg("chip size in 1st bank is %uMB\n", size >> 20);
+ adm5120_memsize = size;
+
+ if (size != maxsize)
+ /* 2nd bank is not supported */
+ goto out;
+
+ if ((memctrl & MEMCTRL_SDR1_ENABLE) == 0)
+ /* 2nd bank is disabled */
+ goto out;
+
+ /*
+ * some bootloaders enable 2nd bank, even if the 2nd SDRAM chip
+ * are missing.
+ */
+ mem_dbg("check presence of 2nd bank\n");
+
+ p = (u8 *)KSEG1ADDR(maxsize+size-4);
+ if (mem_check_pattern(p, 0))
+ adm5120_memsize += size;
+
+ if (maxsize != size) {
+ /* adjusting MECTRL register */
+ memctrl &= ~(MEMCTRL_SDRS_MASK);
+ switch (size>>20) {
+ case 4:
+ memctrl |= MEMCTRL_SDRS_4M;
+ break;
+ case 8:
+ memctrl |= MEMCTRL_SDRS_8M;
+ break;
+ case 16:
+ memctrl |= MEMCTRL_SDRS_16M;
+ break;
+ default:
+ memctrl |= MEMCTRL_SDRS_64M;
+ break;
+ }
+ SW_WRITE_REG(SWITCH_REG_MEMCTRL, memctrl);
+ }
+
+out:
+ mem_dbg("%dx%uMB memory found\n", (adm5120_memsize == size) ? 1 : 2 ,
+ size>>20);
+}
+
+void __init adm5120_mem_init(void)
+{
+ adm5120_detect_memsize();
+ add_memory_region(0, adm5120_memsize, BOOT_MEM_RAM);
+}
--- /dev/null
+/*
+ * ADM5120 generic platform devices
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+
+#include <asm/bootinfo.h>
+
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <asm/mach-adm5120/adm5120_info.h>
+#include <asm/mach-adm5120/adm5120_irq.h>
+#include <asm/mach-adm5120/adm5120_switch.h>
+#include <asm/mach-adm5120/adm5120_nand.h>
+#include <asm/mach-adm5120/adm5120_platform.h>
+
+#if 1
+/*
+ * TODO:remove global adm5120_eth* variables when the switch driver will be
+ * converted into a real platform driver
+ */
+unsigned int adm5120_eth_num_ports = 6;
+EXPORT_SYMBOL_GPL(adm5120_eth_num_ports);
+
+unsigned char adm5120_eth_macs[6][6] = {
+ {'\00', 'A', 'D', 'M', '\x51', '\x20' },
+ {'\00', 'A', 'D', 'M', '\x51', '\x21' },
+ {'\00', 'A', 'D', 'M', '\x51', '\x22' },
+ {'\00', 'A', 'D', 'M', '\x51', '\x23' },
+ {'\00', 'A', 'D', 'M', '\x51', '\x24' },
+ {'\00', 'A', 'D', 'M', '\x51', '\x25' }
+};
+EXPORT_SYMBOL_GPL(adm5120_eth_macs);
+
+unsigned char adm5120_eth_vlans[6] = {
+ 0x41, 0x42, 0x44, 0x48, 0x50, 0x60
+};
+EXPORT_SYMBOL_GPL(adm5120_eth_vlans);
+#endif
+
+/*
+ * Built-in ethernet switch
+ */
+struct resource adm5120_switch_resources[] = {
+ [0] = {
+ .start = ADM5120_SWITCH_BASE,
+ .end = ADM5120_SWITCH_BASE+ADM5120_SWITCH_SIZE-1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = ADM5120_IRQ_SWITCH,
+ .end = ADM5120_IRQ_SWITCH,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct adm5120_switch_platform_data adm5120_switch_data;
+struct platform_device adm5120_switch_device = {
+ .name = "adm5120-switch",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(adm5120_switch_resources),
+ .resource = adm5120_switch_resources,
+ .dev.platform_data = &adm5120_switch_data,
+};
+
+void __init adm5120_add_device_switch(unsigned num_ports, u8 *vlan_map)
+{
+ if (num_ports > 0)
+ adm5120_eth_num_ports = num_ports;
+
+ if (vlan_map)
+ memcpy(adm5120_eth_vlans, vlan_map, sizeof(adm5120_eth_vlans));
+
+ platform_device_register(&adm5120_switch_device);
+}
+
+/*
+ * USB Host Controller
+ */
+struct resource adm5120_hcd_resources[] = {
+ [0] = {
+ .start = ADM5120_USBC_BASE,
+ .end = ADM5120_USBC_BASE+ADM5120_USBC_SIZE-1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = ADM5120_IRQ_USBC,
+ .end = ADM5120_IRQ_USBC,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static u64 adm5120_hcd_dma_mask = DMA_BIT_MASK(24);
+struct platform_device adm5120_hcd_device = {
+ .name = "adm5120-hcd",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(adm5120_hcd_resources),
+ .resource = adm5120_hcd_resources,
+ .dev = {
+ .dma_mask = &adm5120_hcd_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(24),
+ }
+};
+
+void __init adm5120_add_device_usb(void)
+{
+ platform_device_register(&adm5120_hcd_device);
+}
+
+/*
+ * NOR flash devices
+ */
+struct adm5120_flash_platform_data adm5120_flash0_data;
+struct platform_device adm5120_flash0_device = {
+ .name = "adm5120-flash",
+ .id = 0,
+ .dev.platform_data = &adm5120_flash0_data,
+};
+
+struct adm5120_flash_platform_data adm5120_flash1_data;
+struct platform_device adm5120_flash1_device = {
+ .name = "adm5120-flash",
+ .id = 1,
+ .dev.platform_data = &adm5120_flash1_data,
+};
+
+void __init adm5120_add_device_flash(unsigned id)
+{
+ struct platform_device *pdev;
+
+ switch (id) {
+ case 0:
+ pdev = &adm5120_flash0_device;
+ break;
+ case 1:
+ pdev = &adm5120_flash1_device;
+ break;
+ default:
+ pdev = NULL;
+ break;
+ }
+
+ if (pdev)
+ platform_device_register(pdev);
+}
+
+/*
+ * built-in UARTs
+ */
+static void adm5120_uart_set_mctrl(struct amba_device *dev, void __iomem *base,
+ unsigned int mctrl)
+{
+}
+
+struct amba_pl010_data adm5120_uart0_data = {
+ .set_mctrl = adm5120_uart_set_mctrl
+};
+
+struct amba_device adm5120_uart0_device = {
+ .dev = {
+ .bus_id = "APB:UART0",
+ .platform_data = &adm5120_uart0_data,
+ },
+ .res = {
+ .start = ADM5120_UART0_BASE,
+ .end = ADM5120_UART0_BASE + ADM5120_UART_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = { ADM5120_IRQ_UART0, -1 },
+ .periphid = 0x0041010,
+};
+
+struct amba_pl010_data adm5120_uart1_data = {
+ .set_mctrl = adm5120_uart_set_mctrl
+};
+
+struct amba_device adm5120_uart1_device = {
+ .dev = {
+ .bus_id = "APB:UART1",
+ .platform_data = &adm5120_uart1_data,
+ },
+ .res = {
+ .start = ADM5120_UART1_BASE,
+ .end = ADM5120_UART1_BASE + ADM5120_UART_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = { ADM5120_IRQ_UART1, -1 },
+ .periphid = 0x0041010,
+};
+
+void __init adm5120_add_device_uart(unsigned id)
+{
+ struct amba_device *dev;
+
+ switch (id) {
+ case 0:
+ dev = &adm5120_uart0_device;
+ break;
+ case 1:
+ dev = &adm5120_uart1_device;
+ break;
+ default:
+ dev = NULL;
+ break;
+ }
+
+ if (dev)
+ amba_device_register(dev, &iomem_resource);
+}
+
+/*
+ * GPIO buttons
+ */
+#define ADM5120_BUTTON_INTERVAL 20
+struct gpio_buttons_platform_data adm5120_gpio_buttons_data = {
+ .poll_interval = ADM5120_BUTTON_INTERVAL,
+};
+
+struct platform_device adm5120_gpio_buttons_device = {
+ .name = "gpio-buttons",
+ .id = -1,
+ .dev.platform_data = &adm5120_gpio_buttons_data,
+};
+
+void __init adm5120_add_device_gpio_buttons(unsigned nbuttons,
+ struct gpio_button *buttons)
+{
+ struct gpio_button *p;
+
+ p = kmalloc(nbuttons * sizeof(*p), GFP_KERNEL);
+ if (!p)
+ return;
+
+ memcpy(p, buttons, nbuttons * sizeof(*p));
+ adm5120_gpio_buttons_data.nbuttons = nbuttons;
+ adm5120_gpio_buttons_data.buttons = p;
+
+ platform_device_register(&adm5120_gpio_buttons_device);
+}
+
+/*
+ * GPIO LEDS
+ */
+struct gpio_led_platform_data adm5120_gpio_leds_data;
+struct platform_device adm5120_gpio_leds_device = {
+ .name = "leds-gpio",
+ .id = -1,
+ .dev.platform_data = &adm5120_gpio_leds_data,
+};
+
+void __init adm5120_add_device_gpio_leds(unsigned num_leds,
+ struct gpio_led *leds)
+{
+ struct gpio_led *p;
+
+ p = kmalloc(num_leds * sizeof(*p), GFP_KERNEL);
+ if (!p)
+ return;
+
+ memcpy(p, leds, num_leds * sizeof(*p));
+ adm5120_gpio_leds_data.num_leds = num_leds;
+ adm5120_gpio_leds_data.leds = p;
+
+ platform_device_register(&adm5120_gpio_leds_device);
+}
+
+/*
+ * GPIO device
+ */
+static struct resource adm5120_gpio_resource[] __initdata = {
+ {
+ .start = 0x3fffff,
+ },
+};
+
+void __init adm5120_add_device_gpio(u32 disable_mask)
+{
+ if (adm5120_package_pqfp())
+ disable_mask |= 0xf0;
+
+ adm5120_gpio_resource[0].start &= ~disable_mask;
+ platform_device_register_simple("GPIODEV", -1,
+ adm5120_gpio_resource,
+ ARRAY_SIZE(adm5120_gpio_resource));
+}
+
+/*
+ * NAND flash
+ */
+struct resource adm5120_nand_resources[] = {
+ [0] = {
+ .start = ADM5120_NAND_BASE,
+ .end = ADM5120_NAND_BASE + ADM5120_NAND_SIZE-1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static int adm5120_nand_ready(struct mtd_info *mtd)
+{
+ return ((adm5120_nand_get_status() & ADM5120_NAND_STATUS_READY) != 0);
+}
+
+static void adm5120_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
+ unsigned int ctrl)
+{
+ if (ctrl & NAND_CTRL_CHANGE) {
+ adm5120_nand_set_cle(ctrl & NAND_CLE);
+ adm5120_nand_set_ale(ctrl & NAND_ALE);
+ adm5120_nand_set_cen(ctrl & NAND_NCE);
+ }
+
+ if (cmd != NAND_CMD_NONE)
+ NAND_WRITE_REG(NAND_REG_DATA, cmd);
+}
+
+void __init adm5120_add_device_nand(struct platform_nand_data *pdata)
+{
+ struct platform_device *pdev;
+ int err;
+
+ pdev = platform_device_alloc("gen_nand", -1);
+ if (!pdev)
+ goto err_out;
+
+ err = platform_device_add_resources(pdev, adm5120_nand_resources,
+ ARRAY_SIZE(adm5120_nand_resources));
+ if (err)
+ goto err_put;
+
+ err = platform_device_add_data(pdev, pdata, sizeof(*pdata));
+ if (err)
+ goto err_put;
+
+ pdata = pdev->dev.platform_data;
+ pdata->ctrl.dev_ready = adm5120_nand_ready;
+ pdata->ctrl.cmd_ctrl = adm5120_nand_cmd_ctrl;
+
+ err = platform_device_add(pdev);
+ if (err)
+ goto err_put;
+
+ return;
+
+err_put:
+ platform_device_put(pdev);
+err_out:
+ return;
+}
--- /dev/null
+/*
+ * ADM5120 specific prom routines
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/io.h>
+
+#include <asm/bootinfo.h>
+#include <asm/addrspace.h>
+
+#include <asm/mach-adm5120/adm5120_info.h>
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <asm/mach-adm5120/adm5120_uart.h>
+
+#include <prom/cfe.h>
+#include <prom/generic.h>
+#include <prom/routerboot.h>
+#include <prom/myloader.h>
+#include <prom/zynos.h>
+
+unsigned int adm5120_prom_type = ADM5120_PROM_GENERIC;
+
+struct board_desc {
+ unsigned long mach_type;
+ char *name;
+};
+
+#define DEFBOARD(n, mt) { .mach_type = (mt), .name = (n)}
+static struct board_desc common_boards[] __initdata = {
+ /* Cellvision/SparkLAN boards */
+ DEFBOARD("CAS-630", MACH_ADM5120_CAS630),
+ DEFBOARD("CAS-670", MACH_ADM5120_CAS670),
+ DEFBOARD("CAS-700", MACH_ADM5120_CAS700),
+ DEFBOARD("CAS-771", MACH_ADM5120_CAS771),
+ DEFBOARD("CAS-790", MACH_ADM5120_CAS790),
+ DEFBOARD("CAS-861", MACH_ADM5120_CAS861),
+ DEFBOARD("NFS-101U", MACH_ADM5120_NFS101U),
+ /* Compex boards */
+ DEFBOARD("WP54G-WRT", MACH_ADM5120_WP54G_WRT),
+ /* Edimax boards */
+ DEFBOARD("BR-6104K", MACH_ADM5120_BR6104K),
+ DEFBOARD("BR-6104KP", MACH_ADM5120_BR6104KP),
+ DEFBOARD("BR-6104WG", MACH_ADM5120_BR61X4WG),
+ DEFBOARD("BR-6114WG", MACH_ADM5120_BR61X4WG),
+ /* Infineon boards */
+ DEFBOARD("EASY 5120P-ATA", MACH_ADM5120_EASY5120PATA),
+ DEFBOARD("EASY 5120-RT", MACH_ADM5120_EASY5120RT),
+ DEFBOARD("EASY 5120-WVoIP", MACH_ADM5120_EASY5120WVOIP),
+ DEFBOARD("EASY 83000", MACH_ADM5120_EASY83000),
+ /* Mikrotik RouterBOARDs */
+ DEFBOARD("111", MACH_ADM5120_RB_11X),
+ DEFBOARD("112", MACH_ADM5120_RB_11X),
+ DEFBOARD("133", MACH_ADM5120_RB_133),
+ DEFBOARD("133C", MACH_ADM5120_RB_133C),
+ DEFBOARD("133C3", MACH_ADM5120_RB_133C),
+ DEFBOARD("150", MACH_ADM5120_RB_153), /* it's intentional */
+ DEFBOARD("153", MACH_ADM5120_RB_153),
+ DEFBOARD("192", MACH_ADM5120_RB_192),
+ DEFBOARD("miniROUTER", MACH_ADM5120_RB_150),
+};
+
+static unsigned long __init find_machtype_byname(char *name)
+{
+ unsigned long ret;
+ int i;
+
+ ret = MACH_ADM5120_GENERIC;
+ if (name == NULL)
+ goto out;
+
+ if (*name == '\0')
+ goto out;
+
+ for (i = 0; i < ARRAY_SIZE(common_boards); i++) {
+ if (strcmp(common_boards[i].name, name) == 0) {
+ ret = common_boards[i].mach_type;
+ break;
+ }
+ }
+
+out:
+ return ret;
+}
+
+static unsigned long __init detect_machtype_routerboot(void)
+{
+ char *name;
+
+ name = routerboot_get_boardname();
+ return find_machtype_byname(name);
+}
+
+static unsigned long __init detect_machtype_generic(void)
+{
+ char *name;
+
+ name = generic_prom_getenv("board_name");
+ return find_machtype_byname(name);
+}
+
+unsigned long __init detect_machtype_cfe(void)
+{
+ char *name;
+
+ name = cfe_getenv("BOARD_NAME");
+ return find_machtype_byname(name);
+}
+
+static struct {
+ unsigned long mach_type;
+ u16 vendor_id;
+ u16 board_id;
+} zynos_boards[] __initdata = {
+#define ZYNOS_BOARD(vi, bi, mt) \
+ {.vendor_id = (vi), .board_id = (bi), .mach_type = (mt)}
+
+#define ZYXEL_BOARD(bi, mt) ZYNOS_BOARD(ZYNOS_VENDOR_ID_ZYXEL, bi, mt)
+#define DLINK_BOARD(bi, mt) ZYNOS_BOARD(ZYNOS_VENDOR_ID_DLINK, bi, mt)
+#define LUCENT_BOARD(bi, mt) ZYNOS_BOARD(ZYNOS_VENDOR_ID_LUCENT, bi, mt)
+ ZYXEL_BOARD(ZYNOS_BOARD_HS100, MACH_ADM5120_HS100),
+ ZYXEL_BOARD(ZYNOS_BOARD_P334U, MACH_ADM5120_P334U),
+ ZYXEL_BOARD(ZYNOS_BOARD_P334W, MACH_ADM5120_P334W),
+ ZYXEL_BOARD(ZYNOS_BOARD_P334WH, MACH_ADM5120_P334WH),
+ ZYXEL_BOARD(ZYNOS_BOARD_P334WHD, MACH_ADM5120_P334WHD),
+ ZYXEL_BOARD(ZYNOS_BOARD_P334WT, MACH_ADM5120_P334WT),
+ ZYXEL_BOARD(ZYNOS_BOARD_P334WT_ALT, MACH_ADM5120_P334WT),
+ ZYXEL_BOARD(ZYNOS_BOARD_P335, MACH_ADM5120_P335),
+ ZYXEL_BOARD(ZYNOS_BOARD_P335PLUS, MACH_ADM5120_P335PLUS),
+ ZYXEL_BOARD(ZYNOS_BOARD_P335U, MACH_ADM5120_P335U)
+};
+
+static unsigned long __init detect_machtype_bootbase(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(zynos_boards); i++) {
+ if (zynos_boards[i].vendor_id == bootbase_info.vendor_id &&
+ zynos_boards[i].board_id == bootbase_info.board_id) {
+ return zynos_boards[i].mach_type;
+ break;
+ }
+ }
+
+ printk(KERN_WARNING "Unknown ZyXEL model (%u)\n",
+ bootbase_info.board_id);
+ return MACH_ADM5120_GENERIC;
+}
+
+static struct {
+ unsigned long mach_type;
+ u16 vid;
+ u16 did;
+ u16 svid;
+ u16 sdid;
+} mylo_boards[] __initdata = {
+#define MYLO_BOARD(v, d, sv, sd, mt) \
+ {.vid = (v), .did = (d), .svid = (sv), .sdid = (sd), .mach_type = (mt)}
+#define COMPEX_BOARD(d, mt) \
+ MYLO_BOARD(VENID_COMPEX, (d), VENID_COMPEX, (d), (mt))
+
+ COMPEX_BOARD(DEVID_COMPEX_NP27G, MACH_ADM5120_NP27G),
+ COMPEX_BOARD(DEVID_COMPEX_NP28G, MACH_ADM5120_NP28G),
+ COMPEX_BOARD(DEVID_COMPEX_NP28GHS, MACH_ADM5120_NP28GHS),
+ COMPEX_BOARD(DEVID_COMPEX_WP54G, MACH_ADM5120_WP54),
+ COMPEX_BOARD(DEVID_COMPEX_WP54Gv1C, MACH_ADM5120_WP54Gv1C),
+ COMPEX_BOARD(DEVID_COMPEX_WP54AG, MACH_ADM5120_WP54),
+ COMPEX_BOARD(DEVID_COMPEX_WPP54G, MACH_ADM5120_WP54),
+ COMPEX_BOARD(DEVID_COMPEX_WPP54AG, MACH_ADM5120_WP54),
+};
+
+static unsigned long __init detect_machtype_myloader(void)
+{
+ unsigned long ret;
+ int i;
+
+ ret = MACH_ADM5120_GENERIC;
+ for (i = 0; i < ARRAY_SIZE(mylo_boards); i++) {
+ if (mylo_boards[i].vid == myloader_info.vid &&
+ mylo_boards[i].did == myloader_info.did &&
+ mylo_boards[i].svid == myloader_info.svid &&
+ mylo_boards[i].sdid == myloader_info.sdid) {
+ ret = mylo_boards[i].mach_type;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+static void __init prom_detect_machtype(void)
+{
+ if (bootbase_present()) {
+ adm5120_prom_type = ADM5120_PROM_BOOTBASE;
+ mips_machtype = detect_machtype_bootbase();
+ return;
+ }
+
+ if (cfe_present()) {
+ adm5120_prom_type = ADM5120_PROM_CFE;
+ mips_machtype = detect_machtype_cfe();
+ return;
+ }
+
+ if (myloader_present()) {
+ adm5120_prom_type = ADM5120_PROM_MYLOADER;
+ mips_machtype = detect_machtype_myloader();
+ return;
+ }
+
+ if (routerboot_present()) {
+ adm5120_prom_type = ADM5120_PROM_ROUTERBOOT;
+ mips_machtype = detect_machtype_routerboot();
+ return;
+ }
+
+ if (generic_prom_present()) {
+ adm5120_prom_type = ADM5120_PROM_GENERIC;
+ mips_machtype = detect_machtype_generic();
+ return;
+ }
+
+ mips_machtype = MACH_ADM5120_GENERIC;
+}
+
+/* TODO: this is an ugly hack for RouterBOARDS */
+extern char _image_cmdline;
+static void __init prom_init_cmdline(void)
+{
+ char *cmd;
+
+ /* init command line, register a default kernel command line */
+ cmd = &_image_cmdline + 8;
+ if (strlen(cmd) > 0)
+ strcpy(arcs_cmdline, cmd);
+ else
+ strcpy(arcs_cmdline, CONFIG_CMDLINE);
+
+}
+
+#define UART_READ(r) \
+ __raw_readl((void __iomem *)(KSEG1ADDR(ADM5120_UART0_BASE)+(r)))
+#define UART_WRITE(r, v) \
+ __raw_writel((v), (void __iomem *)(KSEG1ADDR(ADM5120_UART0_BASE)+(r)))
+
+void __init prom_putchar(char ch)
+{
+ while ((UART_READ(UART_REG_FLAG) & UART_FLAG_TXFE) == 0);
+ UART_WRITE(UART_REG_DATA, ch);
+ while ((UART_READ(UART_REG_FLAG) & UART_FLAG_TXFE) == 0);
+}
+
+void __init prom_init(void)
+{
+ prom_detect_machtype();
+
+ prom_init_cmdline();
+}
+
+void __init prom_free_prom_memory(void)
+{
+ /* We do not have to prom memory to free */
+}
--- /dev/null
+/*
+ * ADM5120 specific setup
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This code was based on the ADM5120 specific port of the Linux 2.6.10 kernel
+ * done by Jeroen Vreeken
+ * Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org)
+ *
+ * Jeroen's code was based on the Linux 2.4.xx source codes found in various
+ * tarballs released by Edimax for it's ADM5120 based devices
+ * Copyright (C) ADMtek Incorporated
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include <asm/reboot.h>
+#include <asm/time.h>
+
+#include <asm/mach-adm5120/adm5120_info.h>
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <asm/mach-adm5120/adm5120_switch.h>
+#include <asm/mach-adm5120/adm5120_board.h>
+
+void (*adm5120_board_reset)(void);
+
+static char *prom_names[ADM5120_PROM_LAST+1] __initdata = {
+ [ADM5120_PROM_GENERIC] = "Generic",
+ [ADM5120_PROM_CFE] = "CFE",
+ [ADM5120_PROM_UBOOT] = "U-Boot",
+ [ADM5120_PROM_MYLOADER] = "MyLoader",
+ [ADM5120_PROM_ROUTERBOOT] = "RouterBOOT",
+ [ADM5120_PROM_BOOTBASE] = "Bootbase"
+};
+
+static void __init adm5120_report(void)
+{
+ printk(KERN_INFO "SoC : ADM%04X%s revision %d, running "
+ "at %ldMHz\n",
+ adm5120_product_code,
+ adm5120_package_bga() ? "" : "P",
+ adm5120_revision, (adm5120_speed / 1000000));
+ printk(KERN_INFO "Bootdev : %s flash\n",
+ adm5120_nand_boot ? "NAND":"NOR");
+ printk(KERN_INFO "Prom : %s\n", prom_names[adm5120_prom_type]);
+}
+
+static void adm5120_restart(char *command)
+{
+ /* TODO: stop switch before reset */
+
+ if (adm5120_board_reset)
+ adm5120_board_reset();
+
+ SW_WRITE_REG(SWITCH_REG_SOFT_RESET, 1);
+}
+
+static void adm5120_halt(void)
+{
+ local_irq_disable();
+
+ while (1) {
+ if (cpu_wait)
+ cpu_wait();
+ };
+}
+
+void __init plat_time_init(void)
+{
+ mips_hpt_frequency = adm5120_speed / 2;
+}
+
+void __init plat_mem_setup(void)
+{
+ adm5120_soc_init();
+ adm5120_mem_init();
+ adm5120_report();
+
+ _machine_restart = adm5120_restart;
+ _machine_halt = adm5120_halt;
+ pm_power_off = adm5120_halt;
+
+ set_io_port_base(KSEG1);
+}
--- /dev/null
+obj-y += compex.o
+
+obj-$(CONFIG_ADM5120_MACH_NP27G) += np27g.o
+obj-$(CONFIG_ADM5120_MACH_NP28G) += np28g.o
+obj-$(CONFIG_ADM5120_MACH_WP54) += wp54.o
--- /dev/null
+/*
+ * Compex boards
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/bootinfo.h>
+#include <linux/gpio.h>
+
+#include <asm/mach-adm5120/adm5120_info.h>
+#include <asm/mach-adm5120/adm5120_board.h>
+#include <asm/mach-adm5120/adm5120_platform.h>
+#include <asm/mach-adm5120/adm5120_irq.h>
+
+#define COMPEX_GPIO_DEV_MASK (1 << ADM5120_GPIO_PIN5)
+
+static void switch_bank_gpio5(unsigned bank)
+{
+ switch (bank) {
+ case 0:
+ gpio_set_value(ADM5120_GPIO_PIN5, 0);
+ break;
+ case 1:
+ gpio_set_value(ADM5120_GPIO_PIN5, 1);
+ break;
+ }
+}
+
+void __init compex_generic_setup(void)
+{
+ gpio_request(ADM5120_GPIO_PIN5, NULL); /* for flash A20 line */
+ gpio_direction_output(ADM5120_GPIO_PIN5, 0);
+
+ adm5120_flash0_data.switch_bank = switch_bank_gpio5;
+ adm5120_add_device_flash(0);
+
+ adm5120_add_device_gpio(COMPEX_GPIO_DEV_MASK);
+}
--- /dev/null
+/*
+ * Compex boards
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/bootinfo.h>
+#include <linux/gpio.h>
+
+#include <asm/mach-adm5120/adm5120_info.h>
+#include <asm/mach-adm5120/adm5120_board.h>
+#include <asm/mach-adm5120/adm5120_platform.h>
+#include <asm/mach-adm5120/adm5120_irq.h>
+
+extern void compex_generic_setup(void) __init;
--- /dev/null
+/*
+ * Compex NP27G board support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "compex.h"
+
+static u8 np27g_vlans[6] __initdata = {
+ /* FIXME: untested */
+ 0x41, 0x42, 0x44, 0x48, 0x50, 0x00
+};
+
+static void __init np27g_setup(void)
+{
+ compex_generic_setup();
+ adm5120_add_device_switch(5, np27g_vlans);
+ adm5120_add_device_usb();
+
+ /* TODO: add PCI IRQ map */
+}
+
+ADM5120_BOARD(MACH_ADM5120_NP27G, "Compex NetPassage 27G", np27g_setup);
--- /dev/null
+/*
+ * Compex NP28G board support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "compex.h"
+
+static struct adm5120_pci_irq np28g_pci_irqs[] __initdata = {
+ PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0),
+ PCIIRQ(3, 0, 1, ADM5120_IRQ_PCI0),
+ PCIIRQ(3, 1, 2, ADM5120_IRQ_PCI1),
+ PCIIRQ(3, 2, 3, ADM5120_IRQ_PCI2)
+};
+
+static struct gpio_led np28g_gpio_leds[] __initdata = {
+ GPIO_LED_INV(ADM5120_GPIO_PIN2, "diag", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_PIN3, "power", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_PIN6, "wan_cond", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_PIN7, "wifi", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L2, "usb1", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan1", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L2, "usb2", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan2", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L2, "usb3", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P3L2, "usb4", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P4L0, "wan", NULL),
+};
+
+static u8 np28g_vlans[6] __initdata = {
+ 0x50, 0x42, 0x44, 0x48, 0x00, 0x00
+};
+
+static void np28g_reset(void)
+{
+ gpio_set_value(ADM5120_GPIO_PIN4, 0);
+}
+
+static void __init np28g_setup(void)
+{
+ compex_generic_setup();
+
+ /* setup reset line */
+ gpio_request(ADM5120_GPIO_PIN4, NULL);
+ gpio_direction_output(ADM5120_GPIO_PIN4, 1);
+ adm5120_board_reset = np28g_reset;
+
+ adm5120_add_device_switch(4, np28g_vlans);
+ adm5120_add_device_usb();
+
+ adm5120_add_device_gpio_leds(ARRAY_SIZE(np28g_gpio_leds),
+ np28g_gpio_leds);
+
+ adm5120_pci_set_irq_map(ARRAY_SIZE(np28g_pci_irqs), np28g_pci_irqs);
+}
+
+ADM5120_BOARD(MACH_ADM5120_NP28G, "Compex NetPassage 28G", np28g_setup);
--- /dev/null
+/*
+ * Compex WP54 board support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "compex.h"
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition wp54g_wrt_partitions[] = {
+ {
+ .name = "cfe",
+ .offset = 0,
+ .size = 0x050000,
+ .mask_flags = MTD_WRITEABLE,
+ } , {
+ .name = "trx",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 0x3A0000,
+ } , {
+ .name = "nvram",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 0x010000,
+ }
+};
+#endif /* CONFIG_MTD_PARTITIONS */
+
+static struct adm5120_pci_irq wp54_pci_irqs[] __initdata = {
+ PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0),
+};
+
+static struct gpio_button wp54_gpio_buttons[] __initdata = {
+ {
+ .desc = "reset_button",
+ .type = EV_KEY,
+ .code = BTN_0,
+ .threshold = 5,
+ .gpio = ADM5120_GPIO_PIN2,
+ }
+};
+
+static struct gpio_led wp54_gpio_leds[] __initdata = {
+ GPIO_LED_INV(ADM5120_GPIO_PIN2, "diag", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_PIN6, "wlan", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_PIN7, "wan", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan1", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan2", NULL),
+};
+
+static u8 wp54_vlans[6] __initdata = {
+ 0x41, 0x42, 0x00, 0x00, 0x00, 0x00
+};
+
+static void wp54_reset(void)
+{
+ gpio_set_value(ADM5120_GPIO_PIN3, 0);
+}
+
+static void __init wp54_setup(void)
+{
+ compex_generic_setup();
+
+ /* setup reset line */
+ gpio_request(ADM5120_GPIO_PIN3, NULL);
+ gpio_direction_output(ADM5120_GPIO_PIN3, 1);
+ adm5120_board_reset = wp54_reset;
+
+ adm5120_add_device_switch(2, wp54_vlans);
+ adm5120_add_device_gpio_buttons(ARRAY_SIZE(wp54_gpio_buttons),
+ wp54_gpio_buttons);
+ adm5120_add_device_gpio_leds(ARRAY_SIZE(wp54_gpio_leds),
+ wp54_gpio_leds);
+
+ adm5120_pci_set_irq_map(ARRAY_SIZE(wp54_pci_irqs), wp54_pci_irqs);
+}
+
+ADM5120_BOARD(MACH_ADM5120_WP54, "Compex WP54 family", wp54_setup);
+
+static void __init wp54_wrt_setup(void)
+{
+#ifdef CONFIG_MTD_PARTITIONS
+ adm5120_flash0_data.nr_parts = ARRAY_SIZE(wp54g_wrt_partitions);
+ adm5120_flash0_data.parts = wp54g_wrt_partitions;
+#endif
+
+ wp54_setup();
+}
+
+ADM5120_BOARD(MACH_ADM5120_WP54G_WRT, "Compex WP54G-WRT", wp54_wrt_setup);
--- /dev/null
+obj-y := br-61xx.o
+
+obj-$(CONFIG_ADM5120_MACH_BR_6104K) += br-6104k.o
+obj-$(CONFIG_ADM5120_MACH_BR_6104KP) += br-6104kp.o
+obj-$(CONFIG_ADM5120_MACH_BR_61X4WG) += br-61x4wg.o
--- /dev/null
+/*
+ * Edimax BR-6104K board support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "br-61xx.h"
+
+static struct gpio_led br6104k_gpio_leds[] __initdata = {
+ GPIO_LED_STD(ADM5120_GPIO_PIN0, "power", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L1, "wan_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L0, "wan_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan1_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan1_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan2_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan2_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P3L1, "lan3_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P4L1, "lan4_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P4L0, "lan4_lnkact", NULL),
+};
+
+static void __init br6104k_setup(void)
+{
+ br61xx_generic_setup();
+ adm5120_add_device_gpio_leds(ARRAY_SIZE(br6104k_gpio_leds),
+ br6104k_gpio_leds);
+}
+
+ADM5120_BOARD(MACH_ADM5120_BR6104K, "Edimax BR-6104K", br6104k_setup);
--- /dev/null
+/*
+ * Edimax BR-6104KP board support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "br-61xx.h"
+
+static struct gpio_led br6104kp_gpio_leds[] __initdata = {
+ GPIO_LED_STD(ADM5120_GPIO_PIN0, "power", NULL),
+ GPIO_LED_STD(ADM5120_GPIO_PIN1, "usb1", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_PIN3, "usb2", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L1, "wan_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L0, "wan_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan1_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan1_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan2_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan2_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P3L1, "lan3_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P4L1, "lan4_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P4L0, "lan4_lnkact", NULL),
+};
+
+static void __init br6104kp_setup(void)
+{
+ br61xx_generic_setup();
+ adm5120_add_device_gpio_leds(ARRAY_SIZE(br6104kp_gpio_leds),
+ br6104kp_gpio_leds);
+ adm5120_add_device_usb();
+}
+
+ADM5120_BOARD(MACH_ADM5120_BR6104KP, "Edimax BR-6104KP", br6104kp_setup);
--- /dev/null
+/*
+ * Edimax BR-6104Wg/6114WG board support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "br-61xx.h"
+
+static struct adm5120_pci_irq br61x4wg_pci_irqs[] __initdata = {
+ PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0),
+};
+
+static struct gpio_led br61x4wg_gpio_leds[] __initdata = {
+ GPIO_LED_STD(ADM5120_GPIO_PIN0, "power", NULL),
+ GPIO_LED_STD(ADM5120_GPIO_PIN5, "wlan", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L1, "wan_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L0, "wan_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan1_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan1_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan2_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan2_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P3L1, "lan3_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P4L1, "lan4_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P4L0, "lan4_lnkact", NULL),
+};
+
+static void __init br61x4wg_setup(void)
+{
+ br61xx_generic_setup();
+ adm5120_add_device_gpio_leds(ARRAY_SIZE(br61x4wg_gpio_leds),
+ br61x4wg_gpio_leds);
+ adm5120_pci_set_irq_map(ARRAY_SIZE(br61x4wg_pci_irqs),
+ br61x4wg_pci_irqs);
+}
+
+ADM5120_BOARD(MACH_ADM5120_BR61X4WG, "Edimax BR-6104WG/6114WG", br61x4wg_setup);
--- /dev/null
+/*
+ * Edimax BR-61xx support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "br-61xx.h"
+
+#define BR61XX_GPIO_DEV_MASK 0
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition br61xx_partitions[] = {
+ {
+ .name = "admboot",
+ .offset = 0,
+ .size = 32*1024,
+ .mask_flags = MTD_WRITEABLE,
+ } , {
+ .name = "config",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 32*1024,
+ } , {
+ .name = "firmware",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+#endif /* CONFIG_MTD_PARTITIONS */
+
+static struct gpio_button br61xx_gpio_buttons[] __initdata = {
+ {
+ .desc = "reset_button",
+ .type = EV_KEY,
+ .code = BTN_0,
+ .threshold = 5,
+ .gpio = ADM5120_GPIO_PIN2,
+ }
+};
+
+static u8 br61xx_vlans[6] __initdata = {
+ 0x41, 0x42, 0x44, 0x48, 0x50, 0x00
+};
+
+void __init br61xx_generic_setup(void)
+{
+
+#ifdef CONFIG_MTD_PARTITIONS
+ adm5120_flash0_data.nr_parts = ARRAY_SIZE(br61xx_partitions);
+ adm5120_flash0_data.parts = br61xx_partitions;
+#endif /* CONFIG_MTD_PARTITIONS */
+ adm5120_add_device_flash(0);
+
+ adm5120_add_device_gpio(BR61XX_GPIO_DEV_MASK);
+ adm5120_add_device_switch(5, br61xx_vlans);
+ adm5120_add_device_gpio_buttons(ARRAY_SIZE(br61xx_gpio_buttons),
+ br61xx_gpio_buttons);
+
+ /* TODO: setup mac addresses */
+}
--- /dev/null
+/*
+ * Edimax BR-61xx board support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+
+#include <asm/bootinfo.h>
+
+#include <asm/mach-adm5120/adm5120_board.h>
+#include <asm/mach-adm5120/adm5120_irq.h>
+#include <asm/mach-adm5120/adm5120_platform.h>
+
+extern void __init br61xx_generic_setup(void) __init;
--- /dev/null
+obj-y += infineon.o
+
+obj-$(CONFIG_ADM5120_MACH_EASY5120_RT) += easy5120-rt.o
+obj-$(CONFIG_ADM5120_MACH_EASY5120_WVOIP) += easy5120-wvoip.o
+obj-$(CONFIG_ADM5120_MACH_EASY5120P_ATA) += easy5120p-ata.o
+obj-$(CONFIG_ADM5120_MACH_EASY83000) += easy83000.o
--- /dev/null
+/*
+ * Infineon EASY 5120-RT Reference Board support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "infineon.h"
+
+static struct gpio_led easy5120_rt_gpio_leds[] __initdata = {
+ GPIO_LED_INV(ADM5120_GPIO_PIN6, "user", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan0_led1", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L1, "lan0_led2", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan1_led1", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan1_led2", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan2_led1", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan2_led2", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3_led1", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P3L1, "lan3_led2", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P4L0, "wan", NULL),
+};
+
+static struct adm5120_pci_irq easy5120_rt_pci_irqs[] __initdata = {
+ PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0),
+};
+
+static u8 easy5120_rt_vlans[6] __initdata = {
+ 0x41, 0x42, 0x44, 0x48, 0x50, 0x00
+};
+
+static void __init easy5120_rt_setup(void)
+{
+ easy_setup_bga();
+
+ adm5120_add_device_switch(5, easy5120_rt_vlans);
+ adm5120_add_device_usb();
+ adm5120_add_device_gpio_leds(ARRAY_SIZE(easy5120_rt_gpio_leds),
+ easy5120_rt_gpio_leds);
+ adm5120_pci_set_irq_map(ARRAY_SIZE(easy5120_rt_pci_irqs),
+ easy5120_rt_pci_irqs);
+}
+
+ADM5120_BOARD(MACH_ADM5120_EASY5120RT,
+ "Infineon EASY 5120-RT Reference Board",
+ easy5120_rt_setup);
--- /dev/null
+/*
+ * Infineon EASY 5120-WVoIP Reference Board support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "infineon.h"
+
+static void __init easy5120wvoip_setup(void)
+{
+ easy_setup_bga();
+ adm5120_add_device_switch(6, NULL);
+
+ /* TODO: add VINETIC2 device */
+ /* TODO: setup PCI IRQ map */
+}
+
+ADM5120_BOARD(MACH_ADM5120_EASY5120WVOIP,
+ "Infineon EASY 5120-WVoIP Reference Board",
+ easy5120wvoip_setup);
--- /dev/null
+/*
+ * Infineon EASY 5120P-ATA Reference Board support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "infineon.h"
+
+static void __init easy5120pata_setup(void)
+{
+ easy_setup_pqfp();
+
+ adm5120_add_device_switch(6, NULL);
+}
+
+ADM5120_BOARD(MACH_ADM5120_EASY5120PATA,
+ "Infineon EASY 5120P-ATA Reference Board",
+ easy5120pata_setup);
--- /dev/null
+/*
+ * Infineon EASY 83000 Reference Board support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "infineon.h"
+
+static void __init easy83000_setup(void)
+{
+ easy_setup_pqfp();
+ adm5120_add_device_switch(6, NULL);
+
+ /* TODO: add VINAX device */
+}
+
+ADM5120_BOARD(MACH_ADM5120_EASY83000,
+ "Infineon EASY 83000 Reference Board",
+ easy83000_setup);
--- /dev/null
+/*
+ * Infineon Reference Boards
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "infineon.h"
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition easy_partitions[] = {
+ {
+ .name = "admboot",
+ .offset = 0,
+ .size = 64*1024,
+ .mask_flags = MTD_WRITEABLE,
+ } , {
+ .name = "boardcfg",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 64*1024,
+ } , {
+ .name = "firmware",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+#endif /* CONFIG_MTD_PARTITIONS */
+
+static void switch_bank_gpio3(unsigned bank)
+{
+ switch (bank) {
+ case 0:
+ gpio_set_value(ADM5120_GPIO_PIN3, 0);
+ break;
+ case 1:
+ gpio_set_value(ADM5120_GPIO_PIN3, 1);
+ break;
+ }
+}
+
+void __init easy_setup_pqfp(void)
+{
+ /* setup flash A20 line */
+ gpio_request(ADM5120_GPIO_PIN3, NULL);
+ gpio_direction_output(ADM5120_GPIO_PIN3, 0);
+ adm5120_flash0_data.switch_bank = switch_bank_gpio3;
+
+#ifdef CONFIG_MTD_PARTITIONS
+ adm5120_flash0_data.nr_parts = ARRAY_SIZE(easy_partitions);
+ adm5120_flash0_data.parts = easy_partitions;
+#endif /* CONFIG_MTD_PARTITIONS */
+
+ adm5120_add_device_flash(0);
+}
+
+static void switch_bank_gpio5(unsigned bank)
+{
+ switch (bank) {
+ case 0:
+ gpio_set_value(ADM5120_GPIO_PIN5, 0);
+ break;
+ case 1:
+ gpio_set_value(ADM5120_GPIO_PIN5, 1);
+ break;
+ }
+}
+
+void __init easy_setup_bga(void)
+{
+ /* setup flash A20 line */
+ gpio_request(ADM5120_GPIO_PIN5, NULL);
+ gpio_direction_output(ADM5120_GPIO_PIN5, 0);
+ adm5120_flash0_data.switch_bank = switch_bank_gpio5;
+
+#ifdef CONFIG_MTD_PARTITIONS
+ adm5120_flash0_data.nr_parts = ARRAY_SIZE(easy_partitions);
+ adm5120_flash0_data.parts = easy_partitions;
+#endif /* CONFIG_MTD_PARTITIONS */
+
+ adm5120_add_device_flash(0);
+}
--- /dev/null
+/*
+ * Infineon Reference Boards
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/bootinfo.h>
+#include <linux/gpio.h>
+
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <asm/mach-adm5120/adm5120_irq.h>
+#include <asm/mach-adm5120/adm5120_board.h>
+#include <asm/mach-adm5120/adm5120_platform.h>
+#include <asm/mach-adm5120/adm5120_info.h>
+
+extern void easy_setup_pqfp(void) __init;
+extern void easy_setup_bga(void) __init;
--- /dev/null
+obj-y += rb-1xx.o
+
+obj-${CONFIG_ADM5120_MACH_RB_11X} += rb-11x.o
+obj-${CONFIG_ADM5120_MACH_RB_133} += rb-133.o
+obj-${CONFIG_ADM5120_MACH_RB_133C} += rb-133c.o
+obj-${CONFIG_ADM5120_MACH_RB_150} += rb-150.o
+obj-${CONFIG_ADM5120_MACH_RB_153} += rb-153.o
+obj-${CONFIG_ADM5120_MACH_RB_192} += rb-192.o
--- /dev/null
+/*
+ * Mikrotik RouterBOARD 111/112 support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "rb-1xx.h"
+
+static struct gpio_led rb11x_gpio_leds[] __initdata = {
+ GPIO_LED_STD(ADM5120_GPIO_PIN3, "user", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L1, "lan_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan_lnkact", NULL),
+};
+
+static u8 rb11x_vlans[6] __initdata = {
+ 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+static void __init rb11x_setup(void)
+{
+ rb1xx_generic_setup();
+ rb1xx_add_device_nand();
+
+ adm5120_add_device_switch(1, rb11x_vlans);
+ adm5120_add_device_gpio(0);
+ adm5120_add_device_gpio_leds(ARRAY_SIZE(rb11x_gpio_leds),
+ rb11x_gpio_leds);
+}
+
+ADM5120_BOARD(MACH_ADM5120_RB_11X, "Mikrotik RouterBOARD 111/112", rb11x_setup);
--- /dev/null
+/*
+ * Mikrotik RouterBOARD 133 support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "rb-1xx.h"
+
+static struct gpio_led rb133_gpio_leds[] __initdata = {
+ GPIO_LED_STD(ADM5120_GPIO_PIN6, "power", NULL),
+ GPIO_LED_STD(ADM5120_GPIO_PIN5, "user", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan1_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan1_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan2_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan2_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L1, "lan3_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan3_lnkact", NULL),
+};
+
+static u8 rb133_vlans[6] __initdata = {
+ 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+static void __init rb133_setup(void)
+{
+ rb1xx_generic_setup();
+ rb1xx_add_device_nand();
+
+ adm5120_add_device_switch(3, rb133_vlans);
+ adm5120_add_device_gpio(0);
+ adm5120_add_device_gpio_leds(ARRAY_SIZE(rb133_gpio_leds),
+ rb133_gpio_leds);
+}
+
+ADM5120_BOARD(MACH_ADM5120_RB_133, "Mikrotik RouterBOARD 133", rb133_setup);
--- /dev/null
+/*
+ * Mikrotik RouterBOARD 133C support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "rb-1xx.h"
+
+static struct gpio_led rb133c_gpio_leds[] __initdata = {
+ GPIO_LED_STD(ADM5120_GPIO_PIN6, "power", NULL),
+ GPIO_LED_STD(ADM5120_GPIO_PIN5, "user", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan1_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan1_lnkact", NULL),
+};
+
+static u8 rb133c_vlans[6] __initdata = {
+ 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+static void __init rb133c_setup(void)
+{
+ rb1xx_generic_setup();
+ rb1xx_add_device_nand();
+
+ adm5120_add_device_switch(1, rb133c_vlans);
+ adm5120_add_device_gpio(0);
+ adm5120_add_device_gpio_leds(ARRAY_SIZE(rb133c_gpio_leds),
+ rb133c_gpio_leds);
+}
+
+ADM5120_BOARD(MACH_ADM5120_RB_133C, "Mikrotik RouterBOARD 133C", rb133c_setup);
--- /dev/null
+/*
+ * Mikrotik RouterBOARD 150 support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "rb-1xx.h"
+
+#define RB150_NAND_BASE 0x1FC80000
+#define RB150_NAND_SIZE 1
+
+#define RB150_GPIO_NAND_READY ADM5120_GPIO_PIN0
+#define RB150_GPIO_NAND_NCE ADM5120_GPIO_PIN1
+#define RB150_GPIO_NAND_CLE ADM5120_GPIO_P2L2
+#define RB150_GPIO_NAND_ALE ADM5120_GPIO_P3L2
+#define RB150_GPIO_RESET_BUTTON ADM5120_GPIO_PIN1 /* FIXME */
+
+#define RB150_GPIO_DEV_MASK ( 1 << RB150_GPIO_NAND_READY \
+ | 1 << RB150_GPIO_NAND_NCE \
+ | 1 << RB150_GPIO_NAND_CLE \
+ | 1 << RB150_GPIO_NAND_ALE)
+
+#define RB150_NAND_DELAY 100
+
+#define RB150_NAND_WRITE(v) \
+ writeb((v), (void __iomem *)KSEG1ADDR(RB150_NAND_BASE))
+
+static struct resource rb150_nand_resources[] __initdata = {
+ [0] = {
+ .start = RB150_NAND_BASE,
+ .end = RB150_NAND_BASE + RB150_NAND_SIZE-1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct gpio_led rb150_gpio_leds[] __initdata = {
+ GPIO_LED_STD(ADM5120_GPIO_P0L2, "user", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L1, "lan1_led1", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan1_led2", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan5_led1", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan5_led2", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan4_led1", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan4_led2", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P3L1, "lan3_led1", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3_led2", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P4L1, "lan2_led1", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P4L0, "lan2_led2", NULL),
+};
+
+static u8 rb150_vlans[6] __initdata = {
+ 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+static int rb150_nand_dev_ready(struct mtd_info *mtd)
+{
+ return gpio_get_value(RB150_GPIO_NAND_READY);
+}
+
+static void rb150_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
+ unsigned int ctrl)
+{
+ if (ctrl & NAND_CTRL_CHANGE) {
+ gpio_set_value(RB150_GPIO_NAND_CLE, (ctrl & NAND_CLE) ? 1 : 0);
+ gpio_set_value(RB150_GPIO_NAND_ALE, (ctrl & NAND_ALE) ? 1 : 0);
+ gpio_set_value(RB150_GPIO_NAND_NCE, (ctrl & NAND_NCE) ? 0 : 1);
+ }
+
+ udelay(RB150_NAND_DELAY);
+
+ if (cmd != NAND_CMD_NONE)
+ RB150_NAND_WRITE(cmd);
+}
+
+static void __init rb150_add_device_nand(void)
+{
+ struct platform_device *pdev;
+ int err;
+
+ /* setup GPIO pins for NAND flash chip */
+ gpio_request(RB150_GPIO_NAND_READY, "nand-ready");
+ gpio_direction_input(RB150_GPIO_NAND_READY);
+ gpio_request(RB150_GPIO_NAND_NCE, "nand-nce");
+ gpio_direction_output(RB150_GPIO_NAND_NCE, 1);
+ gpio_request(RB150_GPIO_NAND_CLE, "nand-cle");
+ gpio_direction_output(RB150_GPIO_NAND_CLE, 0);
+ gpio_request(RB150_GPIO_NAND_ALE, "nand-ale");
+ gpio_direction_output(RB150_GPIO_NAND_ALE, 0);
+
+ pdev = platform_device_alloc("gen_nand", -1);
+ if (!pdev)
+ goto err_out;
+
+ err = platform_device_add_resources(pdev, rb150_nand_resources,
+ ARRAY_SIZE(rb150_nand_resources));
+ if (err)
+ goto err_put;
+
+
+ rb1xx_nand_data.ctrl.cmd_ctrl = rb150_nand_cmd_ctrl;
+ rb1xx_nand_data.ctrl.dev_ready = rb150_nand_dev_ready;
+
+ err = platform_device_add_data(pdev, &rb1xx_nand_data,
+ sizeof(rb1xx_nand_data));
+ if (err)
+ goto err_put;
+
+ err = platform_device_add(pdev);
+ if (err)
+ goto err_put;
+
+ return;
+
+err_put:
+ platform_device_put(pdev);
+err_out:
+ return;
+}
+
+static void __init rb150_setup(void)
+{
+ rb1xx_gpio_buttons[0].gpio = RB150_GPIO_RESET_BUTTON;
+ rb1xx_generic_setup();
+ rb150_add_device_nand();
+
+ adm5120_add_device_gpio(RB150_GPIO_DEV_MASK);
+ adm5120_add_device_gpio_leds(ARRAY_SIZE(rb150_gpio_leds),
+ rb150_gpio_leds);
+ adm5120_add_device_switch(5, rb150_vlans);
+}
+
+ADM5120_BOARD(MACH_ADM5120_RB_150, "Mikrotik RouterBOARD 150", rb150_setup);
--- /dev/null
+/*
+ * Mikrotik RouterBOARD 153 support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "rb-1xx.h"
+
+#define RB153_GPIO_DEV_MASK ( 1 << ADM5120_GPIO_PIN0 \
+ | 1 << ADM5120_GPIO_PIN3 \
+ | 1 << ADM5120_GPIO_PIN4 )
+
+static struct resource rb153_cf_resources[] __initdata = {
+ {
+ .name = "cf_membase",
+ .start = ADM5120_EXTIO1_BASE,
+ .end = ADM5120_EXTIO1_BASE + ADM5120_EXTIO1_SIZE-1 ,
+ .flags = IORESOURCE_MEM
+ }, {
+ .name = "cf_irq",
+ .start = ADM5120_IRQ_GPIO4,
+ .end = ADM5120_IRQ_GPIO4,
+ .flags = IORESOURCE_IRQ
+ }
+};
+
+static struct gpio_led rb153_gpio_leds[] __initdata = {
+ GPIO_LED_STD(ADM5120_GPIO_PIN5, "user", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L1, "lan1_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan1_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L1, "lan5_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan5_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L1, "lan4_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan4_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P3L1, "lan3_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan3_lnkact", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P4L1, "lan2_speed", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P4L0, "lan2_lnkact", NULL),
+};
+
+static u8 rb153_vlans[6] __initdata = {
+ 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+static void __init rb153_add_device_cf(void)
+{
+ /* enable CSX1:INTX1 on GPIO[3:4] for the CF slot */
+ adm5120_gpio_csx1_enable();
+
+ /* enable the wait state pin GPIO[0] for external I/O control */
+ adm5120_gpio_ew_enable();
+
+ platform_device_register_simple("pata-rb153-cf", -1,
+ rb153_cf_resources, ARRAY_SIZE(rb153_cf_resources));
+}
+
+static void __init rb153_setup(void)
+{
+ rb1xx_generic_setup();
+ rb1xx_add_device_nand();
+ rb153_add_device_cf();
+
+ adm5120_add_device_gpio(RB153_GPIO_DEV_MASK);
+ adm5120_add_device_gpio_leds(ARRAY_SIZE(rb153_gpio_leds),
+ rb153_gpio_leds);
+ adm5120_add_device_switch(5, rb153_vlans);
+}
+
+ADM5120_BOARD(MACH_ADM5120_RB_153, "Mikrotik RouterBOARD 153", rb153_setup);
--- /dev/null
+/*
+ * Mikrotik RouterBOARD 192 support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "rb-1xx.h"
+
+static u8 rb192_vlans[6] __initdata = {
+ 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+static void __init rb192_setup(void)
+{
+ rb1xx_generic_setup();
+ rb1xx_add_device_nand();
+
+ adm5120_add_device_gpio(0);
+ adm5120_add_device_switch(6, rb192_vlans);
+}
+
+ADM5120_BOARD(MACH_ADM5120_RB_192, "Mikrotik RouterBOARD 192", rb192_setup);
--- /dev/null
+/*
+ * Mikrotik RouterBOARD 1xx series support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * NAND initialization code was based on a driver for Linux 2.6.19+ which
+ * was derived from the driver for Linux 2.4.xx published by Mikrotik for
+ * their RouterBoard 1xx and 5xx series boards.
+ * Copyright (C) 2007 David Goodenough <david.goodenough@linkchoose.co.uk>
+ * Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "rb-1xx.h"
+
+#define RB1XX_NAND_CHIP_DELAY 25
+
+static struct adm5120_pci_irq rb1xx_pci_irqs[] __initdata = {
+ PCIIRQ(1, 0, 1, ADM5120_IRQ_PCI0),
+ PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI1),
+ PCIIRQ(3, 0, 1, ADM5120_IRQ_PCI2)
+};
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition rb1xx_nor_parts[] = {
+ {
+ .name = "booter",
+ .offset = 0,
+ .size = 64*1024,
+ .mask_flags = MTD_WRITEABLE,
+ } , {
+ .name = "firmware",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+
+static struct mtd_partition rb1xx_nand_parts[] = {
+ {
+ .name = "kernel",
+ .offset = 0,
+ .size = 4 * 1024 * 1024,
+ } , {
+ .name = "rootfs",
+ .offset = MTDPART_OFS_NXTBLK,
+ .size = MTDPART_SIZ_FULL
+ }
+};
+#endif /* CONFIG_MTD_PARTITIONS */
+
+/*
+ * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader
+ * will not be able to find the kernel that we load. So set the oobinfo
+ * when creating the partitions
+ */
+static struct nand_ecclayout rb1xx_nand_ecclayout = {
+ .eccbytes = 6,
+ .eccpos = { 8, 9, 10, 13, 14, 15 },
+ .oobavail = 9,
+ .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
+};
+
+/*--------------------------------------------------------------------------*/
+
+static int rb1xx_nand_fixup(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd->priv;
+
+ if (mtd->writesize == 512)
+ chip->ecc.layout = &rb1xx_nand_ecclayout;
+
+ return 0;
+}
+
+struct platform_nand_data rb1xx_nand_data __initdata = {
+ .chip = {
+ .nr_chips = 1,
+#ifdef CONFIG_MTD_PARTITIONS
+ .nr_partitions = ARRAY_SIZE(rb1xx_nand_parts),
+ .partitions = rb1xx_nand_parts,
+#endif /* CONFIG_MTD_PARTITIONS */
+ .chip_delay = RB1XX_NAND_CHIP_DELAY,
+ .options = NAND_NO_AUTOINCR,
+ .chip_fixup = rb1xx_nand_fixup,
+ },
+};
+
+struct gpio_button rb1xx_gpio_buttons[] __initdata = {
+ {
+ .desc = "reset_button",
+ .type = EV_KEY,
+ .code = BTN_0,
+ .threshold = 5,
+ .gpio = ADM5120_GPIO_PIN7,
+ }
+};
+
+static void __init rb1xx_mac_setup(void)
+{
+ int i, j;
+
+ if (!rb_hs.mac_base)
+ return;
+
+ for (i = 0; i < 6; i++) {
+ for (j = 0; j < 5; j++)
+ adm5120_eth_macs[i][j] = rb_hs.mac_base[j];
+ adm5120_eth_macs[i][5] = rb_hs.mac_base[5]+i;
+ }
+}
+
+void __init rb1xx_add_device_flash(void)
+{
+ /* setup data for flash0 device */
+#ifdef CONFIG_MTD_PARTITIONS
+ adm5120_flash0_data.nr_parts = ARRAY_SIZE(rb1xx_nor_parts);
+ adm5120_flash0_data.parts = rb1xx_nor_parts;
+#endif /* CONFIG_MTD_PARTITIONS */
+ adm5120_flash0_data.window_size = 128*1024;
+
+ adm5120_add_device_flash(0);
+}
+
+void __init rb1xx_add_device_nand(void)
+{
+ /* enable NAND flash interface */
+ adm5120_nand_enable();
+
+ /* initialize NAND chip */
+ adm5120_nand_set_spn(1);
+ adm5120_nand_set_wpn(0);
+
+ adm5120_add_device_nand(&rb1xx_nand_data);
+}
+
+void __init rb1xx_generic_setup(void)
+{
+ if (adm5120_package_bga())
+ adm5120_pci_set_irq_map(ARRAY_SIZE(rb1xx_pci_irqs),
+ rb1xx_pci_irqs);
+
+ adm5120_add_device_gpio_buttons(ARRAY_SIZE(rb1xx_gpio_buttons),
+ rb1xx_gpio_buttons);
+
+ rb1xx_add_device_flash();
+ rb1xx_mac_setup();
+}
--- /dev/null
+/*
+ * Mikrotik RouterBOARD 1xx series support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+
+#include <asm/bootinfo.h>
+
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <asm/mach-adm5120/adm5120_irq.h>
+#include <asm/mach-adm5120/adm5120_nand.h>
+#include <asm/mach-adm5120/adm5120_board.h>
+#include <asm/mach-adm5120/adm5120_platform.h>
+#include <asm/mach-adm5120/adm5120_info.h>
+
+#include <prom/routerboot.h>
+
+extern struct platform_nand_data rb1xx_nand_data __initdata;
+extern struct gpio_button rb1xx_gpio_buttons[] __initdata;
+
+extern void rb1xx_add_device_flash(void) __init;
+extern void rb1xx_add_device_nand(void) __init;
+extern void rb1xx_generic_setup(void) __init;
--- /dev/null
+#
+# Makefile for the ADMtek ADM5120 SoC specific parts of the kernel
+#
+
+lib-y += bootbase.o
+lib-y += cfe.o
+lib-y += generic.o
+lib-y += myloader.o
+lib-y += routerboot.o
--- /dev/null
+/*
+ * ZyXEL's Bootbase specific prom routines
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/types.h>
+#include <linux/autoconf.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/string.h>
+
+#include <asm/bootinfo.h>
+#include <asm/addrspace.h>
+#include <asm/byteorder.h>
+
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <prom/zynos.h>
+#include "prom_read.h"
+
+#define ZYNOS_INFO_ADDR KSEG1ADDR(ADM5120_SRAM0_BASE+0x3F90)
+#define ZYNOS_HDBG_ADDR KSEG1ADDR(ADM5120_SRAM0_BASE+0x4000)
+#define BOOTEXT_ADDR_MIN KSEG1ADDR(ADM5120_SRAM0_BASE)
+#define BOOTEXT_ADDR_MAX (BOOTEXT_ADDR_MIN + (2*1024*1024))
+
+static int bootbase_found;
+static struct zynos_board_info *board_info;
+
+struct bootbase_info bootbase_info;
+
+static inline int bootbase_dbgarea_present(u8 *data)
+{
+ u32 t;
+
+ t = prom_read_be32(data+5);
+ if (t != ZYNOS_MAGIC_DBGAREA1)
+ return 0;
+
+ t = prom_read_be32(data+9);
+ if (t != ZYNOS_MAGIC_DBGAREA2)
+ return 0;
+
+ return 1;
+}
+
+static inline u32 bootbase_get_bootext_addr(void)
+{
+ return prom_read_be32(&board_info->bootext_addr);
+}
+
+static inline u16 bootbase_get_vendor_id(void)
+{
+#define CHECK_VENDOR(n) (strnicmp(board_info->vendor, (n), strlen(n)) == 0)
+ unsigned char vendor[ZYNOS_NAME_LEN];
+ int i;
+
+ for (i = 0; i < ZYNOS_NAME_LEN; i++)
+ vendor[i] = board_info->vendor[i];
+
+ if CHECK_VENDOR(ZYNOS_VENDOR_ZYXEL)
+ return ZYNOS_VENDOR_ID_ZYXEL;
+
+ if CHECK_VENDOR(ZYNOS_VENDOR_DLINK)
+ return ZYNOS_VENDOR_ID_DLINK;
+
+ if CHECK_VENDOR(ZYNOS_VENDOR_LUCENT)
+ return ZYNOS_VENDOR_ID_LUCENT;
+
+ if CHECK_VENDOR(ZYNOS_VENDOR_NETGEAR)
+ return ZYNOS_VENDOR_ID_NETGEAR;
+
+ return ZYNOS_VENDOR_ID_OTHER;
+}
+
+static inline u16 bootbase_get_board_id(void)
+{
+ return prom_read_be16(&board_info->board_id);
+}
+
+int __init bootbase_present(void)
+{
+ u32 t;
+
+ if (bootbase_found)
+ goto out;
+
+ /* check presence of the dbgarea */
+ if (bootbase_dbgarea_present((u8 *)ZYNOS_HDBG_ADDR) == 0)
+ goto out;
+
+ board_info = (struct zynos_board_info *)(ZYNOS_INFO_ADDR);
+
+ /* check for a valid BootExt address */
+ t = bootbase_get_bootext_addr();
+ if ((t < BOOTEXT_ADDR_MIN) || (t > BOOTEXT_ADDR_MAX))
+ goto out;
+
+ bootbase_info.vendor_id = bootbase_get_vendor_id();
+ bootbase_info.board_id = bootbase_get_board_id();
+
+ bootbase_found = 1;
+
+out:
+ return bootbase_found;
+}
+
--- /dev/null
+/*
+ * Broadcom's CFE specific prom routines
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+
+#include <asm/bootinfo.h>
+#include <asm/addrspace.h>
+
+#include <prom/cfe.h>
+#include "prom_read.h"
+
+/*
+ * CFE based boards
+ */
+#define CFE_EPTSEAL 0x43464531 /* CFE1 is the magic number to recognize CFE
+from other bootloaders */
+
+static int cfe_found;
+
+static u32 cfe_handle;
+static u32 cfe_entry;
+static u32 cfe_seal;
+
+int __init cfe_present(void)
+{
+ /*
+ * This method only works, when we are booted directly from the CFE.
+ */
+ u32 a1 = (u32) fw_arg1;
+
+ if (cfe_found)
+ return 1;
+
+ cfe_handle = (u32) fw_arg0;
+ cfe_entry = (u32) fw_arg2;
+ cfe_seal = (u32) fw_arg3;
+
+ /* Check for CFE by finding the CFE magic number */
+ if (cfe_seal != CFE_EPTSEAL)
+ return 0;
+
+ /* cfe_a1_val must be 0, because only one CPU present in the ADM5120 */
+ if (a1 != 0)
+ return 0;
+
+ /* The cfe_handle, and the cfe_entry must be kernel mode addresses */
+ if ((cfe_handle < KSEG0) || (cfe_entry < KSEG0))
+ return 0;
+
+ cfe_found = 1;
+ return 1;
+}
+
+char *cfe_getenv(char *envname)
+{
+ if (cfe_found == 0)
+ return NULL;
+
+ return NULL;
+}
--- /dev/null
+/*
+ * Generic PROM routines
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/string.h>
+
+#include <asm/bootinfo.h>
+
+#include <prom/generic.h>
+
+static int *_prom_argc;
+static char **_prom_argv;
+static char **_prom_envp;
+
+char *generic_prom_getenv(char *envname)
+{
+ char **env;
+ char *ret;
+
+ ret = NULL;
+ for (env = _prom_envp; *env != NULL; env++) {
+ if (strcmp(envname, *env++) == 0) {
+ ret = *env;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+int generic_prom_present(void)
+{
+ _prom_argc = (int *)fw_arg0;
+ _prom_argv = (char **)fw_arg1;
+ _prom_envp = (char **)fw_arg2;
+
+ return 1;
+}
--- /dev/null
+/*
+ * Compex's MyLoader specific prom routines
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/types.h>
+#include <linux/autoconf.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/string.h>
+
+#include <asm/bootinfo.h>
+#include <asm/addrspace.h>
+#include <asm/byteorder.h>
+
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <prom/myloader.h>
+#include "prom_read.h"
+
+#define SYS_PARAMS_ADDR KSEG1ADDR(ADM5120_SRAM0_BASE+0x0F000)
+#define BOARD_PARAMS_ADDR KSEG1ADDR(ADM5120_SRAM0_BASE+0x0F800)
+#define PART_TABLE_ADDR KSEG1ADDR(ADM5120_SRAM0_BASE+0x10000)
+
+static int myloader_found;
+
+struct myloader_info myloader_info;
+
+int __init myloader_present(void)
+{
+ struct mylo_system_params *sysp;
+ struct mylo_board_params *boardp;
+ struct mylo_partition_table *parts;
+
+ if (myloader_found)
+ goto out;
+
+ sysp = (struct mylo_system_params *)(SYS_PARAMS_ADDR);
+ boardp = (struct mylo_board_params *)(BOARD_PARAMS_ADDR);
+ parts = (struct mylo_partition_table *)(PART_TABLE_ADDR);
+
+ /* Check for some magic numbers */
+ if ((le32_to_cpu(sysp->magic) != MYLO_MAGIC_SYS_PARAMS) ||
+ (le32_to_cpu(boardp->magic) != MYLO_MAGIC_BOARD_PARAMS) ||
+ (le32_to_cpu(parts->magic) != MYLO_MAGIC_PARTITIONS))
+ goto out;
+
+ myloader_info.vid = le32_to_cpu(sysp->vid);
+ myloader_info.did = le32_to_cpu(sysp->did);
+ myloader_info.svid = le32_to_cpu(sysp->svid);
+ myloader_info.sdid = le32_to_cpu(sysp->sdid);
+
+ myloader_found = 1;
+
+out:
+ return myloader_found;
+}
--- /dev/null
+/*
+ * Generic prom definitions
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#ifndef _ADM5120_PROM_H_
+#define _ADM5120_PROM_H_
+
+/*
+ * Helper routines
+ */
+static inline u16 prom_read_le16(void *buf)
+{
+ u8 *p = buf;
+
+ return ((u16)p[0] + ((u16)p[1] << 8));
+}
+
+static inline u32 prom_read_le32(void *buf)
+{
+ u8 *p = buf;
+
+ return ((u32)p[0] + ((u32)p[1] << 8) + ((u32)p[2] << 16) +
+ ((u32)p[3] << 24));
+}
+
+static inline u16 prom_read_be16(void *buf)
+{
+ u8 *p = buf;
+
+ return (((u16)p[0] << 8) + (u16)p[1]);
+}
+
+static inline u32 prom_read_be32(void *buf)
+{
+ u8 *p = buf;
+
+ return (((u32)p[0] << 24) + ((u32)p[1] << 16) + ((u32)p[2] << 8) +
+ ((u32)p[3]));
+}
+
+#endif /* _ADM5120_PROM_H_ */
+
+
--- /dev/null
+/*
+ * Mikrotik's RouterBOOT specific prom routines
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/types.h>
+#include <linux/autoconf.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/string.h>
+#include <linux/module.h>
+
+#include <asm/bootinfo.h>
+#include <asm/addrspace.h>
+
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <prom/routerboot.h>
+#include "prom_read.h"
+
+struct rb_hard_settings rb_hs;
+static int rb_found;
+
+static int __init routerboot_load_hs(u8 *buf, u16 buflen)
+{
+ u16 id, len;
+
+ memset(&rb_hs, 0, sizeof(rb_hs));
+
+ if (buflen < 4)
+ return -1;
+
+ if (prom_read_le32(buf) != RB_MAGIC_HARD)
+ return -1;
+
+ /* skip magic value */
+ buf += 4;
+ buflen -= 4;
+
+ while (buflen > 2) {
+ id = prom_read_le16(buf);
+ buf += 2;
+ buflen -= 2;
+ if (id == RB_ID_TERMINATOR || buflen < 2)
+ break;
+
+ len = prom_read_le16(buf);
+ buf += 2;
+ buflen -= 2;
+
+ if (buflen < len)
+ break;
+
+ switch (id) {
+ case RB_ID_BIOS_VERSION:
+ rb_hs.bios_ver = (char *)buf;
+ break;
+ case RB_ID_BOARD_NAME:
+ rb_hs.name = (char *)buf;
+ break;
+ case RB_ID_MEMORY_SIZE:
+ rb_hs.mem_size = prom_read_le32(buf);
+ break;
+ case RB_ID_MAC_ADDRESS_COUNT:
+ rb_hs.mac_count = prom_read_le32(buf);
+ break;
+ case RB_ID_MAC_ADDRESS_PACK:
+ if ((len / RB_MAC_SIZE) > 0)
+ rb_hs.mac_base = buf;
+ break;
+ }
+
+ buf += len;
+ buflen -= len;
+
+ }
+
+ return 0;
+}
+
+#define RB_BS_OFFS 0x14
+#define RB_OFFS_MAX (128*1024)
+
+int __init routerboot_present(void)
+{
+ struct rb_bios_settings *bs;
+ u8 *base;
+ u32 off, len;
+
+ if (rb_found)
+ goto out;
+
+ base = (u8 *)KSEG1ADDR(ADM5120_SRAM0_BASE);
+ bs = (struct rb_bios_settings *)(base + RB_BS_OFFS);
+
+ off = prom_read_le32(&bs->hs_offs);
+ len = prom_read_le32(&bs->hs_size);
+ if (off > RB_OFFS_MAX)
+ goto out;
+
+ if (routerboot_load_hs(base+off, len) != 0)
+ goto out;
+
+ rb_found = 1;
+
+out:
+ return rb_found;
+}
+
+char *routerboot_get_boardname(void)
+{
+ if (rb_found == 0)
+ return NULL;
+
+ return rb_hs.name;
+}
--- /dev/null
+obj-y += p-33x.o
+
+obj-${CONFIG_ADM5120_MACH_P_334WT} += p-334wt.o
+obj-${CONFIG_ADM5120_MACH_P_335} += p-335.o
\ No newline at end of file
--- /dev/null
+/*
+ * ZyXEL Prestige P-334WT support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "p-33x.h"
+
+static struct gpio_led p334wt_gpio_leds[] __initdata = {
+ GPIO_LED_INV(ADM5120_GPIO_PIN2, "power", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P3L0, "lan1", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L0, "lan2", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L0, "lan3", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P0L0, "lan4", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P4L0, "wan", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P4L2, "wlan", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P2L2, "otist", NULL),
+ GPIO_LED_INV(ADM5120_GPIO_P1L2, "hidden", NULL),
+};
+
+static void __init p334wt_setup(void)
+{
+ p33x_generic_setup();
+ adm5120_add_device_gpio_leds(ARRAY_SIZE(p334wt_gpio_leds),
+ p334wt_gpio_leds);
+}
+
+ADM5120_BOARD(MACH_ADM5120_P334WT, "ZyXEL Prestige 334WT", p334wt_setup);
--- /dev/null
+/*
+ * ZyXEL Prestige P-335/335WT support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "p-33x.h"
+
+static void __init p335_setup(void)
+{
+ p33x_generic_setup();
+ adm5120_add_device_usb();
+}
+
+ADM5120_BOARD(MACH_ADM5120_P335, "ZyXEL Prestige 335/335WT", p335_setup);
--- /dev/null
+/*
+ * ZyXEL Prestige P-33x boards support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include "p-33x.h"
+
+#define P33X_GPIO_FLASH_A20 ADM5120_GPIO_PIN5
+#define P33X_GPIO_DEV_MASK (1 << P33X_GPIO_FLASH_A20)
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition p33x_partitions[] = {
+ {
+ .name = "bootbase",
+ .offset = 0,
+ .size = 16*1024,
+ .mask_flags = MTD_WRITEABLE,
+ } , {
+ .name = "rom",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 16*1024,
+ } , {
+ .name = "bootext",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 96*1024,
+ .mask_flags = MTD_WRITEABLE,
+ } , {
+ .name = "trx",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ } , {
+ .name = "firmware",
+ .offset = 32*1024,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+#endif /* CONFIG_MTD_PARTITIONS */
+
+static struct adm5120_pci_irq p33x_pci_irqs[] __initdata = {
+ PCIIRQ(2, 0, 1, ADM5120_IRQ_PCI0),
+};
+
+static u8 p33x_vlans[6] __initdata = {
+ /* FIXME: untested */
+ 0x50, 0x48, 0x44, 0x42, 0x41, 0x00
+};
+
+static void switch_bank_gpio5(unsigned bank)
+{
+ switch (bank) {
+ case 0:
+ gpio_set_value(P33X_GPIO_FLASH_A20, 0);
+ break;
+ case 1:
+ gpio_set_value(P33X_GPIO_FLASH_A20, 1);
+ break;
+ }
+}
+
+void __init p33x_generic_setup(void)
+{
+ /* setup data for flash0 device */
+ gpio_request(P33X_GPIO_FLASH_A20, NULL); /* for flash A20 line */
+ gpio_direction_output(P33X_GPIO_FLASH_A20, 0);
+ adm5120_flash0_data.switch_bank = switch_bank_gpio5;
+#ifdef CONFIG_MTD_PARTITIONS
+ adm5120_flash0_data.nr_parts = ARRAY_SIZE(p33x_partitions);
+ adm5120_flash0_data.parts = p33x_partitions;
+#endif /* CONFIG_MTD_PARTITIONS */
+ adm5120_add_device_flash(0);
+
+ adm5120_add_device_gpio(P33X_GPIO_DEV_MASK);
+ adm5120_add_device_switch(5, p33x_vlans);
+
+ adm5120_pci_set_irq_map(ARRAY_SIZE(p33x_pci_irqs), p33x_pci_irqs);
+}
--- /dev/null
+/*
+ * ZyXEL Prestige P-33x boards support
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/bootinfo.h>
+#include <linux/gpio.h>
+
+#include <asm/mach-adm5120/adm5120_board.h>
+#include <asm/mach-adm5120/adm5120_platform.h>
+#include <asm/mach-adm5120/adm5120_irq.h>
+
+extern void p33x_generic_setup(void) __init;
\ No newline at end of file
--- /dev/null
+/*
+ * ADM5120 PCI Host Controller driver
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This code was based on the ADM5120 specific port of the Linux 2.6.10 kernel
+ * done by Jeroen Vreeken
+ * Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org)
+ *
+ * Jeroen's code was based on the Linux 2.4.xx source codes found in various
+ * tarballs released by Edimax for it's ADM5120 based devices
+ * Copyright (C) ADMtek Incorporated
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+
+#include <linux/pci.h>
+#include <linux/pci_ids.h>
+#include <linux/pci_regs.h>
+
+#include <asm/delay.h>
+#include <asm/bootinfo.h>
+
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <asm/mach-adm5120/adm5120_info.h>
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <asm/mach-adm5120/adm5120_platform.h>
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define DBG(f, a...) printk(KERN_DEBUG f, ## a)
+#else
+#define DBG(f, a...) do {} while (0)
+#endif
+
+#define PCI_ENABLE 0x80000000
+
+/* -------------------------------------------------------------------------*/
+
+static unsigned int adm5120_pci_nr_irqs __initdata;
+static struct adm5120_pci_irq *adm5120_pci_irq_map __initdata;
+
+static spinlock_t pci_lock = SPIN_LOCK_UNLOCKED;
+
+/* -------------------------------------------------------------------------*/
+
+static inline void write_cfgaddr(u32 addr)
+{
+ __raw_writel((addr | PCI_ENABLE),
+ (void __iomem *)(KSEG1ADDR(ADM5120_PCICFG_ADDR)));
+}
+
+static inline void write_cfgdata(u32 data)
+{
+ __raw_writel(data, (void __iomem *)KSEG1ADDR(ADM5120_PCICFG_DATA));
+}
+
+static inline u32 read_cfgdata(void)
+{
+ return __raw_readl((void __iomem *)KSEG1ADDR(ADM5120_PCICFG_DATA));
+}
+
+static inline u32 mkaddr(struct pci_bus *bus, unsigned int devfn, int where)
+{
+ return (((bus->number & 0xFF) << 16) | ((devfn & 0xFF) << 8) | \
+ (where & 0xFC));
+}
+
+/* -------------------------------------------------------------------------*/
+
+static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
+ int size, u32 *val)
+{
+ unsigned long flags;
+ u32 data;
+
+ spin_lock_irqsave(&pci_lock, flags);
+
+ write_cfgaddr(mkaddr(bus, devfn, where));
+ data = read_cfgdata();
+
+ DBG("PCI: cfg_read %02u.%02u.%01u/%02X:%01d, cfg:0x%08X",
+ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
+ where, size, data);
+
+ switch (size) {
+ case 1:
+ if (where & 1)
+ data >>= 8;
+ if (where & 2)
+ data >>= 16;
+ data &= 0xFF;
+ break;
+ case 2:
+ if (where & 2)
+ data >>= 16;
+ data &= 0xFFFF;
+ break;
+ }
+
+ *val = data;
+ DBG(", 0x%08X returned\n", data);
+
+ spin_unlock_irqrestore(&pci_lock, flags);
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
+ int size, u32 val)
+{
+ unsigned long flags;
+ u32 data;
+ int s;
+
+ spin_lock_irqsave(&pci_lock, flags);
+
+ write_cfgaddr(mkaddr(bus, devfn, where));
+ data = read_cfgdata();
+
+ DBG("PCI: cfg_write %02u.%02u.%01u/%02X:%01d, cfg:0x%08X",
+ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
+ where, size, data);
+
+ switch (size) {
+ case 1:
+ s = ((where & 3) << 3);
+ data &= ~(0xFF << s);
+ data |= ((val & 0xFF) << s);
+ break;
+ case 2:
+ s = ((where & 2) << 4);
+ data &= ~(0xFFFF << s);
+ data |= ((val & 0xFFFF) << s);
+ break;
+ case 4:
+ data = val;
+ break;
+ }
+
+ write_cfgdata(data);
+ DBG(", 0x%08X written\n", data);
+
+ spin_unlock_irqrestore(&pci_lock, flags);
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+struct pci_ops adm5120_pci_ops = {
+ .read = pci_config_read,
+ .write = pci_config_write,
+};
+
+/* -------------------------------------------------------------------------*/
+
+static void adm5120_pci_fixup(struct pci_dev *dev)
+{
+ if (dev->devfn != 0)
+ return;
+
+ /* setup COMMAND register */
+ pci_write_config_word(dev, PCI_COMMAND,
+ (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
+
+ /* setup CACHE_LINE_SIZE register */
+ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4);
+
+ /* setup BARS */
+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0);
+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
+}
+
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADMTEK, PCI_DEVICE_ID_ADMTEK_ADM5120,
+ adm5120_pci_fixup);
+
+/* -------------------------------------------------------------------------*/
+
+void __init adm5120_pci_set_irq_map(unsigned int nr_irqs,
+ struct adm5120_pci_irq *map)
+{
+ adm5120_pci_nr_irqs = nr_irqs;
+ adm5120_pci_irq_map = map;
+}
+
+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+ int irq = -1;
+ int i;
+
+ if ((!adm5120_pci_nr_irqs) || (!adm5120_pci_irq_map)) {
+ printk(KERN_ALERT "PCI: pci_irq_map is not initialized\n");
+ goto out;
+ }
+
+ if (slot < 1 || slot > 3) {
+ printk(KERN_ALERT "PCI: slot number %u is not supported\n",
+ slot);
+ goto out;
+ }
+
+ for (i = 0; i < adm5120_pci_nr_irqs; i++) {
+ if ((adm5120_pci_irq_map[i].slot == slot)
+ && (adm5120_pci_irq_map[i].func == PCI_FUNC(dev->devfn))
+ && (adm5120_pci_irq_map[i].pin == pin)) {
+ irq = adm5120_pci_irq_map[i].irq;
+ break;
+ }
+ }
+
+ if (irq < 0) {
+ printk(KERN_ALERT "PCI: no irq found for %s pin:%u\n",
+ pci_name((struct pci_dev *)dev), pin);
+ } else {
+ printk(KERN_INFO "PCI: mapping irq for %s pin:%u, irq:%d\n",
+ pci_name((struct pci_dev *)dev), pin, irq);
+ }
+
+out:
+ return irq;
+}
+
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+ return 0;
+}
+
+/* -------------------------------------------------------------------------*/
+
+static struct resource pci_io_resource = {
+ .name = "ADM5120 PCI I/O",
+ .start = ADM5120_PCIIO_BASE,
+ .end = ADM5120_PCICFG_ADDR-1,
+ .flags = IORESOURCE_IO
+};
+
+static struct resource pci_mem_resource = {
+ .name = "ADM5120 PCI MEM",
+ .start = ADM5120_PCIMEM_BASE,
+ .end = ADM5120_PCIIO_BASE-1,
+ .flags = IORESOURCE_MEM
+};
+
+static struct pci_controller adm5120_controller = {
+ .pci_ops = &adm5120_pci_ops,
+ .io_resource = &pci_io_resource,
+ .mem_resource = &pci_mem_resource,
+};
+
+static int __init adm5120_pci_setup(void)
+{
+ if (adm5120_package_pqfp()) {
+ printk(KERN_INFO "PCI: not available on ADM5120P\n");
+ return -1;
+ }
+
+ /* Avoid ISA compat ranges. */
+ PCIBIOS_MIN_IO = 0x00000000;
+ PCIBIOS_MIN_MEM = 0x00000000;
+
+ /* Set I/O resource limits. */
+ ioport_resource.end = 0x1fffffff;
+ iomem_resource.end = 0xffffffff;
+
+ register_pci_controller(&adm5120_controller);
+ return 0;
+}
+
+arch_initcall(adm5120_pci_setup);
--- /dev/null
+/*
+ * A low-level PATA driver to handle a Compact Flash connected on the
+ * Mikrotik's RouterBoard 153 board.
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This file was based on: drivers/ata/pata_ixp4xx_cf.c
+ * Copyright (C) 2006-07 Tower Technologies
+ * Author: Alessandro Zummo <a.zummo@towertech.it>
+ *
+ * Also was based on the driver for Linux 2.4.xx published by Mikrotik for
+ * their RouterBoard 1xx and 5xx series devices. The original Mikrotik code
+ * seems not to have a license.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+
+#include <linux/libata.h>
+#include <scsi/scsi_host.h>
+
+#define DRV_NAME "pata-rb153-cf"
+#define DRV_VERSION "0.5.0"
+#define DRV_DESC "PATA driver for RouterBOARD 153 Compact Flash"
+
+#define RB153_CF_MAXPORTS 1
+#define RB153_CF_IO_DELAY 100
+
+#define RB153_CF_REG_CMD 0x0800
+#define RB153_CF_REG_CTRL 0x080E
+#define RB153_CF_REG_DATA 0x0C00
+
+struct rb153_cf_info {
+ void __iomem *iobase;
+ unsigned int gpio_line;
+ int frozen;
+ unsigned int irq;
+};
+
+static inline void rb153_pata_finish_io(struct ata_port *ap)
+{
+ struct rb153_cf_info *info = ap->host->private_data;
+
+ /* FIXME: Keep previous delay. If this is merely a fence then
+ * ata_sff_sync might be sufficient. */
+ ata_sff_dma_pause(ap);
+ ndelay(RB153_CF_IO_DELAY);
+
+ set_irq_type(info->irq, IRQ_TYPE_LEVEL_HIGH);
+}
+
+static void rb153_pata_exec_command(struct ata_port *ap,
+ const struct ata_taskfile *tf)
+{
+ writeb(tf->command, ap->ioaddr.command_addr);
+ rb153_pata_finish_io(ap);
+}
+
+static unsigned int rb153_pata_data_xfer(struct ata_device *adev,
+ unsigned char *buf,
+ unsigned int buflen,
+ int write_data)
+{
+ void __iomem *ioaddr = adev->link->ap->ioaddr.data_addr;
+ unsigned int t;
+
+ t = buflen;
+ if (write_data) {
+ for (; t > 0; t--, buf++)
+ writeb(*buf, ioaddr);
+ } else {
+ for (; t > 0; t--, buf++)
+ *buf = readb(ioaddr);
+ }
+
+ rb153_pata_finish_io(adev->link->ap);
+ return buflen;
+}
+
+static void rb153_pata_freeze(struct ata_port *ap)
+{
+ struct rb153_cf_info *info = ap->host->private_data;
+
+ info->frozen = 1;
+}
+
+static void rb153_pata_thaw(struct ata_port *ap)
+{
+ struct rb153_cf_info *info = ap->host->private_data;
+
+ info->frozen = 0;
+}
+
+static irqreturn_t rb153_pata_irq_handler(int irq, void *dev_instance)
+{
+ struct ata_host *ah = dev_instance;
+ struct rb153_cf_info *info = ah->private_data;
+
+ if (gpio_get_value(info->gpio_line)) {
+ set_irq_type(info->irq, IRQ_TYPE_LEVEL_LOW);
+ if (!info->frozen)
+ ata_sff_interrupt(irq, dev_instance);
+ } else {
+ set_irq_type(info->irq, IRQ_TYPE_LEVEL_HIGH);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static struct ata_port_operations rb153_pata_port_ops = {
+ .inherits = &ata_sff_port_ops,
+ .sff_exec_command = rb153_pata_exec_command,
+ .sff_data_xfer = rb153_pata_data_xfer,
+ .freeze = rb153_pata_freeze,
+ .thaw = rb153_pata_thaw,
+};
+
+static struct scsi_host_template rb153_pata_sht = {
+ ATA_PIO_SHT(DRV_NAME),
+};
+
+static void rb153_pata_setup_port(struct ata_host *ah)
+{
+ struct rb153_cf_info *info = ah->private_data;
+ struct ata_port *ap;
+
+ ap = ah->ports[0];
+
+ ap->ops = &rb153_pata_port_ops;
+ ap->pio_mask = 0x1f; /* PIO4 */
+ ap->flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO;
+
+ ap->ioaddr.cmd_addr = info->iobase + RB153_CF_REG_CMD;
+ ap->ioaddr.ctl_addr = info->iobase + RB153_CF_REG_CTRL;
+ ap->ioaddr.altstatus_addr = info->iobase + RB153_CF_REG_CTRL;
+
+ ata_sff_std_ports(&ap->ioaddr);
+
+ ap->ioaddr.data_addr = info->iobase + RB153_CF_REG_DATA;
+}
+
+static __devinit int rb153_pata_driver_probe(struct platform_device *pdev)
+{
+ unsigned int irq;
+ int gpio;
+ struct resource *res;
+ struct ata_host *ah;
+ struct rb153_cf_info *info;
+ int ret;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(&pdev->dev, "no IOMEM resource found\n");
+ return -EINVAL;
+ }
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq <= 0) {
+ dev_err(&pdev->dev, "no IRQ resource found\n");
+ return -ENOENT;
+ }
+
+ gpio = irq_to_gpio(irq);
+ if (gpio < 0) {
+ dev_err(&pdev->dev, "no GPIO found for irq%d\n", irq);
+ return -ENOENT;
+ }
+
+ ret = gpio_request(gpio, DRV_NAME);
+ if (ret) {
+ dev_err(&pdev->dev, "GPIO request failed\n");
+ return ret;
+ }
+
+ ah = ata_host_alloc(&pdev->dev, RB153_CF_MAXPORTS);
+ if (!ah)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, ah);
+
+ info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
+ if (!info)
+ return -ENOMEM;
+
+ ah->private_data = info;
+ info->gpio_line = gpio;
+ info->irq = irq;
+
+ info->iobase = devm_ioremap_nocache(&pdev->dev, res->start,
+ res->end - res->start + 1);
+ if (!info->iobase)
+ return -ENOMEM;
+
+ ret = gpio_direction_input(gpio);
+ if (ret) {
+ dev_err(&pdev->dev, "unable to set GPIO direction, err=%d\n",
+ ret);
+ goto err_free_gpio;
+ }
+
+ rb153_pata_setup_port(ah);
+
+ ret = ata_host_activate(ah, irq, rb153_pata_irq_handler,
+ IRQF_TRIGGER_LOW, &rb153_pata_sht);
+ if (ret)
+ goto err_free_gpio;
+
+ return 0;
+
+err_free_gpio:
+ gpio_free(gpio);
+
+ return ret;
+}
+
+static __devexit int rb153_pata_driver_remove(struct platform_device *pdev)
+{
+ struct ata_host *ah = platform_get_drvdata(pdev);
+ struct rb153_cf_info *info = ah->private_data;
+
+ ata_host_detach(ah);
+ gpio_free(info->gpio_line);
+
+ return 0;
+}
+
+static struct platform_driver rb153_pata_platform_driver = {
+ .probe = rb153_pata_driver_probe,
+ .remove = __devexit_p(rb153_pata_driver_remove),
+ .driver = {
+ .name = DRV_NAME,
+ .owner = THIS_MODULE,
+ },
+};
+
+/* ------------------------------------------------------------------------ */
+
+#define DRV_INFO DRV_DESC " version " DRV_VERSION
+
+static int __init rb153_pata_module_init(void)
+{
+ printk(KERN_INFO DRV_INFO "\n");
+
+ return platform_driver_register(&rb153_pata_platform_driver);
+}
+
+static void __exit rb153_pata_module_exit(void)
+{
+ platform_driver_unregister(&rb153_pata_platform_driver);
+}
+
+MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
+MODULE_DESCRIPTION(DRV_DESC);
+MODULE_VERSION(DRV_VERSION);
+MODULE_LICENSE("GPL v2");
+
+module_init(rb153_pata_module_init);
+module_exit(rb153_pata_module_exit);
--- /dev/null
+/*
+ * LED ADM5120 Switch Port State Trigger
+ *
+ * Copyright (C) 2007 Bernhard Held <bernhard at bernhardheld.de>
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This file was based on: drivers/leds/ledtrig-timer.c
+ * Copyright 2005-2006 Openedhand Ltd.
+ * Author: Richard Purdie
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/device.h>
+
+#include <linux/gpio.h>
+
+#include "leds.h"
+
+#define DRV_NAME "port_state"
+#define DRV_DESC "LED ADM5120 Switch Port State Trigger"
+
+struct port_state {
+ char *name;
+ unsigned int value;
+};
+
+#define PORT_STATE(n,v) {.name = (n), .value = (v)}
+
+static struct port_state port_states[] = {
+ PORT_STATE("off", LED_OFF),
+ PORT_STATE("on", LED_FULL),
+ PORT_STATE("flash", ADM5120_GPIO_FLASH),
+ PORT_STATE("link", ADM5120_GPIO_LINK),
+ PORT_STATE("speed", ADM5120_GPIO_SPEED),
+ PORT_STATE("duplex", ADM5120_GPIO_DUPLEX),
+ PORT_STATE("act", ADM5120_GPIO_ACT),
+ PORT_STATE("coll", ADM5120_GPIO_COLL),
+ PORT_STATE("link_act", ADM5120_GPIO_LINK_ACT),
+ PORT_STATE("duplex_coll", ADM5120_GPIO_DUPLEX_COLL),
+ PORT_STATE("10M_act", ADM5120_GPIO_10M_ACT),
+ PORT_STATE("100M_act", ADM5120_GPIO_100M_ACT),
+};
+
+static ssize_t led_port_state_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct led_classdev *led_cdev = dev_get_drvdata(dev);
+ struct port_state *state = led_cdev->trigger_data;
+ int len = 0;
+ int i;
+
+ *buf = '\0';
+ for (i = 0; i < ARRAY_SIZE(port_states); i++) {
+ if (&port_states[i] == state)
+ len += sprintf(buf+len, "[%s] ", port_states[i].name);
+ else
+ len += sprintf(buf+len, "%s ", port_states[i].name);
+ }
+ len += sprintf(buf+len, "\n");
+
+ return len;
+}
+
+static ssize_t led_port_state_store(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t size)
+{
+ struct led_classdev *led_cdev = dev_get_drvdata(dev);
+ size_t len;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(port_states); i++) {
+ len = strlen(port_states[i].name);
+ if (strncmp(port_states[i].name, buf, len) != 0)
+ continue;
+
+ if (buf[len] != '\0' && buf[len] != '\n')
+ continue;
+
+ led_cdev->trigger_data = &port_states[i];
+ led_set_brightness(led_cdev, port_states[i].value);
+ return size;
+ }
+
+ return -EINVAL;
+}
+
+static DEVICE_ATTR(port_state, 0644, led_port_state_show,
+ led_port_state_store);
+
+static void adm5120_switch_trig_activate(struct led_classdev *led_cdev)
+{
+ struct port_state *state = port_states;
+ int rc;
+
+ led_cdev->trigger_data = state;
+
+ rc = device_create_file(led_cdev->dev, &dev_attr_port_state);
+ if (rc)
+ goto err;
+
+ led_set_brightness(led_cdev, state->value);
+
+ return;
+err:
+ led_cdev->trigger_data = NULL;
+}
+
+static void adm5120_switch_trig_deactivate(struct led_classdev *led_cdev)
+{
+ struct port_state *state = led_cdev->trigger_data;
+
+ if (!state)
+ return;
+
+ device_remove_file(led_cdev->dev, &dev_attr_port_state);
+
+}
+
+static struct led_trigger adm5120_switch_led_trigger = {
+ .name = DRV_NAME,
+ .activate = adm5120_switch_trig_activate,
+ .deactivate = adm5120_switch_trig_deactivate,
+};
+
+static int __init adm5120_switch_trig_init(void)
+{
+ led_trigger_register(&adm5120_switch_led_trigger);
+ return 0;
+}
+
+static void __exit adm5120_switch_trig_exit(void)
+{
+ led_trigger_unregister(&adm5120_switch_led_trigger);
+}
+
+module_init(adm5120_switch_trig_init);
+module_exit(adm5120_switch_trig_exit);
+
+MODULE_AUTHOR("Bernhard Held <bernhard at bernhardheld.de>, "
+ "Gabor Juhos <juhosg@openwrt.org>");
+MODULE_DESCRIPTION(DRV_DESC);
+MODULE_LICENSE("GPL v2");
--- /dev/null
+/*
+ * Platform driver for NOR flash devices on ADM5120 based boards
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This file was derived from: drivers/mtd/map/physmap.c
+ * Copyright (C) 2003 MontaVista Software Inc.
+ * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <asm/mach-adm5120/adm5120_switch.h>
+#include <asm/mach-adm5120/adm5120_mpmc.h>
+#include <asm/mach-adm5120/adm5120_platform.h>
+
+#define DRV_NAME "adm5120-flash"
+#define DRV_DESC "ADM5120 flash MAP driver"
+#define MAX_PARSED_PARTS 8
+
+#ifdef ADM5120_FLASH_DEBUG
+#define MAP_DBG(m, f, a...) printk(KERN_INFO "%s: " f, (m->name) , ## a)
+#else
+#define MAP_DBG(m, f, a...) do {} while (0)
+#endif
+#define MAP_ERR(m, f, a...) printk(KERN_ERR "%s: " f, (m->name) , ## a)
+#define MAP_INFO(m, f, a...) printk(KERN_INFO "%s: " f, (m->name) , ## a)
+
+struct adm5120_map_info {
+ struct map_info map;
+ void (*switch_bank)(unsigned);
+ unsigned long window_size;
+};
+
+struct adm5120_flash_info {
+ struct mtd_info *mtd;
+ struct resource *res;
+ struct platform_device *dev;
+ struct adm5120_map_info amap;
+#ifdef CONFIG_MTD_PARTITIONS
+ int nr_parts;
+ struct mtd_partition *parts[MAX_PARSED_PARTS];
+#endif
+};
+
+struct flash_desc {
+ u32 phys;
+ u32 srs_shift;
+};
+
+/*
+ * Globals
+ */
+static DEFINE_SPINLOCK(adm5120_flash_spin);
+#define FLASH_LOCK() spin_lock(&adm5120_flash_spin)
+#define FLASH_UNLOCK() spin_unlock(&adm5120_flash_spin)
+
+static u32 flash_bankwidths[4] = { 1, 2, 4, 0 };
+
+static u32 flash_sizes[8] = {
+ 0, 512*1024, 1024*1024, 2*1024*1024,
+ 4*1024*1024, 0, 0, 0
+};
+
+static struct flash_desc flash_descs[2] = {
+ {
+ .phys = ADM5120_SRAM0_BASE,
+ .srs_shift = MEMCTRL_SRS0_SHIFT,
+ }, {
+ .phys = ADM5120_SRAM1_BASE,
+ .srs_shift = MEMCTRL_SRS1_SHIFT,
+ }
+};
+
+static const char *probe_types[] = {
+ "cfi_probe",
+ "jedec_probe",
+ "map_rom",
+ NULL
+};
+
+#ifdef CONFIG_MTD_PARTITIONS
+static const char *parse_types[] = {
+ "cmdlinepart",
+#ifdef CONFIG_MTD_REDBOOT_PARTS
+ "RedBoot",
+#endif
+#ifdef CONFIG_MTD_MYLOADER_PARTS
+ "MyLoader",
+#endif
+};
+#endif
+
+#define BANK_SIZE (2<<20)
+#define BANK_SIZE_MAX (4<<20)
+#define BANK_OFFS_MASK (BANK_SIZE-1)
+#define BANK_START_MASK (~BANK_OFFS_MASK)
+
+static inline struct adm5120_map_info *map_to_amap(struct map_info *map)
+{
+ return (struct adm5120_map_info *)map;
+}
+
+static void adm5120_flash_switchbank(struct map_info *map,
+ unsigned long ofs)
+{
+ struct adm5120_map_info *amap = map_to_amap(map);
+ unsigned bank;
+
+ if (amap->switch_bank == NULL)
+ return;
+
+ bank = (ofs & BANK_START_MASK) >> 21;
+ if (bank > 1)
+ BUG();
+
+ MAP_DBG(map, "switching to bank %u, ofs=%lX\n", bank, ofs);
+ amap->switch_bank(bank);
+}
+
+static map_word adm5120_flash_read(struct map_info *map, unsigned long ofs)
+{
+ struct adm5120_map_info *amap = map_to_amap(map);
+ map_word ret;
+
+ MAP_DBG(map, "reading from ofs %lX\n", ofs);
+
+ if (ofs >= amap->window_size)
+ return map_word_ff(map);
+
+ FLASH_LOCK();
+ adm5120_flash_switchbank(map, ofs);
+ ret = inline_map_read(map, (ofs & (amap->window_size-1)));
+ FLASH_UNLOCK();
+
+ return ret;
+}
+
+static void adm5120_flash_write(struct map_info *map, const map_word datum,
+ unsigned long ofs)
+{
+ struct adm5120_map_info *amap = map_to_amap(map);
+
+ MAP_DBG(map, "writing to ofs %lX\n", ofs);
+
+ if (ofs > amap->window_size)
+ return;
+
+ FLASH_LOCK();
+ adm5120_flash_switchbank(map, ofs);
+ inline_map_write(map, datum, (ofs & (amap->window_size-1)));
+ FLASH_UNLOCK();
+}
+
+static void adm5120_flash_copy_from(struct map_info *map, void *to,
+ unsigned long from, ssize_t len)
+{
+ struct adm5120_map_info *amap = map_to_amap(map);
+ char *p;
+ ssize_t t;
+
+ MAP_DBG(map, "copy_from, to=%lX, from=%lX, len=%lX\n",
+ (unsigned long)to, from, (unsigned long)len);
+
+ if (from > amap->window_size)
+ return;
+
+ p = (char *)to;
+ while (len > 0) {
+ t = len;
+ if ((from < BANK_SIZE) && ((from+len) > BANK_SIZE))
+ t = BANK_SIZE-from;
+
+ FLASH_LOCK();
+ MAP_DBG(map, "copying %lu byte(s) from %lX to %lX\n",
+ (unsigned long)t, (from & (amap->window_size-1)),
+ (unsigned long)p);
+ adm5120_flash_switchbank(map, from);
+ inline_map_copy_from(map, p, (from & (amap->window_size-1)), t);
+ FLASH_UNLOCK();
+ p += t;
+ from += t;
+ len -= t;
+ }
+}
+
+static int adm5120_flash_initres(struct adm5120_flash_info *info)
+{
+ struct map_info *map = &info->amap.map;
+ int err = 0;
+
+ info->res = request_mem_region(map->phys, info->amap.window_size,
+ map->name);
+ if (info->res == NULL) {
+ MAP_ERR(map, "could not reserve memory region\n");
+ err = -ENOMEM;
+ goto out;
+ }
+
+ map->virt = ioremap_nocache(map->phys, info->amap.window_size);
+ if (map->virt == NULL) {
+ MAP_ERR(map, "failed to ioremap flash region\n");
+ err = -ENOMEM;
+ goto out;
+ }
+
+out:
+ return err;
+}
+
+static int adm5120_flash_initinfo(struct adm5120_flash_info *info,
+ struct platform_device *dev)
+{
+ struct map_info *map = &info->amap.map;
+ struct adm5120_flash_platform_data *pdata = dev->dev.platform_data;
+ struct flash_desc *fdesc;
+ u32 t = 0;
+
+ map->name = dev->dev.bus_id;
+
+ if (dev->id > 1) {
+ MAP_ERR(map, "invalid flash id\n");
+ goto err_out;
+ }
+
+ fdesc = &flash_descs[dev->id];
+
+ if (pdata)
+ info->amap.window_size = pdata->window_size;
+
+ if (info->amap.window_size == 0) {
+ /* get memory window size */
+ t = SW_READ_REG(SWITCH_REG_MEMCTRL) >> fdesc->srs_shift;
+ t &= MEMCTRL_SRS_MASK;
+ info->amap.window_size = flash_sizes[t];
+ }
+
+ if (info->amap.window_size == 0) {
+ MAP_ERR(map, "unable to determine window size\n");
+ goto err_out;
+ }
+
+ /* get flash bus width */
+ switch (dev->id) {
+ case 0:
+ t = MPMC_READ_REG(SC1) & SC_MW_MASK;
+ break;
+ case 1:
+ t = MPMC_READ_REG(SC0) & SC_MW_MASK;
+ break;
+ }
+ map->bankwidth = flash_bankwidths[t];
+ if (map->bankwidth == 0) {
+ MAP_ERR(map, "invalid bus width detected\n");
+ goto err_out;
+ }
+
+ map->phys = fdesc->phys;
+ map->size = BANK_SIZE_MAX;
+
+ simple_map_init(map);
+ map->read = adm5120_flash_read;
+ map->write = adm5120_flash_write;
+ map->copy_from = adm5120_flash_copy_from;
+
+ if (pdata) {
+ map->set_vpp = pdata->set_vpp;
+ info->amap.switch_bank = pdata->switch_bank;
+ }
+
+ info->dev = dev;
+
+ MAP_INFO(map, "probing at 0x%lX, size:%ldKiB, width:%d bits\n",
+ (unsigned long)map->phys,
+ (unsigned long)info->amap.window_size >> 10,
+ map->bankwidth*8);
+
+ return 0;
+
+err_out:
+ return -ENODEV;
+}
+
+static void adm5120_flash_initbanks(struct adm5120_flash_info *info)
+{
+ struct map_info *map = &info->amap.map;
+
+ if (info->mtd->size <= BANK_SIZE)
+ /* no bank switching needed */
+ return;
+
+ if (info->amap.switch_bank) {
+ info->amap.window_size = info->mtd->size;
+ return;
+ }
+
+ MAP_ERR(map, "reduce visibility from %ldKiB to %ldKiB\n",
+ (unsigned long)map->size >> 10,
+ (unsigned long)info->mtd->size >> 10);
+
+ info->mtd->size = info->amap.window_size;
+}
+
+#ifdef CONFIG_MTD_PARTITIONS
+static int adm5120_flash_initparts(struct adm5120_flash_info *info)
+{
+ struct adm5120_flash_platform_data *pdata;
+ struct map_info *map = &info->amap.map;
+ int num_parsers;
+ const char *parser[2];
+ int err = 0;
+ int nr_parts;
+ int i;
+
+ info->nr_parts = 0;
+
+ pdata = info->dev->dev.platform_data;
+ if (pdata == NULL)
+ goto out;
+
+ if (pdata->nr_parts) {
+ MAP_INFO(map, "adding static partitions\n");
+ err = add_mtd_partitions(info->mtd, pdata->parts,
+ pdata->nr_parts);
+ if (err == 0) {
+ info->nr_parts += pdata->nr_parts;
+ goto out;
+ }
+ }
+
+ num_parsers = ARRAY_SIZE(parse_types);
+ if (num_parsers > MAX_PARSED_PARTS)
+ num_parsers = MAX_PARSED_PARTS;
+
+ parser[1] = NULL;
+ for (i = 0; i < num_parsers; i++) {
+ parser[0] = parse_types[i];
+
+ MAP_INFO(map, "parsing \"%s\" partitions\n",
+ parser[0]);
+ nr_parts = parse_mtd_partitions(info->mtd, parser,
+ &info->parts[i], 0);
+
+ if (nr_parts <= 0)
+ continue;
+
+ MAP_INFO(map, "adding \"%s\" partitions\n",
+ parser[0]);
+
+ err = add_mtd_partitions(info->mtd, info->parts[i], nr_parts);
+ if (err)
+ break;
+
+ info->nr_parts += nr_parts;
+ }
+out:
+ return err;
+}
+#else
+static int adm5120_flash_initparts(struct adm5120_flash_info *info)
+{
+ return 0;
+}
+#endif /* CONFIG_MTD_PARTITIONS */
+
+#ifdef CONFIG_MTD_PARTITIONS
+static void adm5120_flash_remove_mtd(struct adm5120_flash_info *info)
+{
+ int i;
+
+ if (info->nr_parts) {
+ del_mtd_partitions(info->mtd);
+ for (i = 0; i < MAX_PARSED_PARTS; i++)
+ if (info->parts[i] != NULL)
+ kfree(info->parts[i]);
+ } else {
+ del_mtd_device(info->mtd);
+ }
+}
+#else
+static void adm5120_flash_remove_mtd(struct adm5120_flash_info *info)
+{
+ del_mtd_device(info->mtd);
+}
+#endif
+
+static int adm5120_flash_remove(struct platform_device *dev)
+{
+ struct adm5120_flash_info *info;
+
+ info = platform_get_drvdata(dev);
+ if (info == NULL)
+ return 0;
+
+ platform_set_drvdata(dev, NULL);
+
+ if (info->mtd != NULL) {
+ adm5120_flash_remove_mtd(info);
+ map_destroy(info->mtd);
+ }
+
+ if (info->amap.map.virt != NULL)
+ iounmap(info->amap.map.virt);
+
+ if (info->res != NULL) {
+ release_resource(info->res);
+ kfree(info->res);
+ }
+
+ return 0;
+}
+
+static int adm5120_flash_probe(struct platform_device *dev)
+{
+ struct adm5120_flash_info *info;
+ struct map_info *map;
+ const char **probe_type;
+ int err;
+
+ info = kzalloc(sizeof(*info), GFP_KERNEL);
+ if (info == NULL) {
+ err = -ENOMEM;
+ goto err_out;
+ }
+
+ platform_set_drvdata(dev, info);
+
+ err = adm5120_flash_initinfo(info, dev);
+ if (err)
+ goto err_out;
+
+ err = adm5120_flash_initres(info);
+ if (err)
+ goto err_out;
+
+ map = &info->amap.map;
+ for (probe_type = probe_types; info->mtd == NULL && *probe_type != NULL;
+ probe_type++)
+ info->mtd = do_map_probe(*probe_type, map);
+
+ if (info->mtd == NULL) {
+ MAP_ERR(map, "map_probe failed\n");
+ err = -ENXIO;
+ goto err_out;
+ }
+
+ adm5120_flash_initbanks(info);
+
+ if (info->mtd->size < info->amap.window_size) {
+ /* readjust resources */
+ iounmap(map->virt);
+ release_resource(info->res);
+ kfree(info->res);
+
+ info->amap.window_size = info->mtd->size;
+ map->size = info->mtd->size;
+ MAP_INFO(map, "reducing map size to %ldKiB\n",
+ (unsigned long)map->size >> 10);
+ err = adm5120_flash_initres(info);
+ if (err)
+ goto err_out;
+ }
+
+ MAP_INFO(map, "found at 0x%lX, size:%ldKiB, width:%d bits\n",
+ (unsigned long)map->phys, (unsigned long)info->mtd->size >> 10,
+ map->bankwidth*8);
+
+ info->mtd->owner = THIS_MODULE;
+
+ err = adm5120_flash_initparts(info);
+ if (err)
+ goto err_out;
+
+ if (info->nr_parts == 0) {
+ MAP_INFO(map, "no partitions available, registering "
+ "whole flash\n");
+ add_mtd_device(info->mtd);
+ }
+
+ return 0;
+
+err_out:
+ adm5120_flash_remove(dev);
+ return err;
+}
+
+#ifdef CONFIG_PM
+static int adm5120_flash_suspend(struct platform_device *dev,
+ pm_message_t state)
+{
+ struct adm5120_flash_info *info = platform_get_drvdata(dev);
+ int ret = 0;
+
+ if (info)
+ ret = info->mtd->suspend(info->mtd);
+
+ return ret;
+}
+
+static int adm5120_flash_resume(struct platform_device *dev)
+{
+ struct adm5120_flash_info *info = platform_get_drvdata(dev);
+
+ if (info)
+ info->mtd->resume(info->mtd);
+
+ return 0;
+}
+
+static void adm5120_flash_shutdown(struct platform_device *dev)
+{
+ struct adm5120_flash_info *info = platform_get_drvdata(dev);
+
+ if (info && info->mtd->suspend(info->mtd) == 0)
+ info->mtd->resume(info->mtd);
+}
+#endif
+
+static struct platform_driver adm5120_flash_driver = {
+ .probe = adm5120_flash_probe,
+ .remove = adm5120_flash_remove,
+#ifdef CONFIG_PM
+ .suspend = adm5120_flash_suspend,
+ .resume = adm5120_flash_resume,
+ .shutdown = adm5120_flash_shutdown,
+#endif
+ .driver = {
+ .name = DRV_NAME,
+ },
+};
+
+static int __init adm5120_flash_init(void)
+{
+ int err;
+
+ err = platform_driver_register(&adm5120_flash_driver);
+
+ return err;
+}
+
+static void __exit adm5120_flash_exit(void)
+{
+ platform_driver_unregister(&adm5120_flash_driver);
+}
+
+module_init(adm5120_flash_init);
+module_exit(adm5120_flash_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
+MODULE_DESCRIPTION(DRV_DESC);
--- /dev/null
+/*
+ * Parse MyLoader-style flash partition tables and produce a Linux partition
+ * array to match.
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This file was based on drivers/mtd/redboot.c
+ * Author: Red Hat, Inc. - David Woodhouse <dwmw2@cambridge.redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/vmalloc.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <linux/byteorder/generic.h>
+
+#include <prom/myloader.h>
+
+#define NAME_LEN_MAX 20
+#define NAME_MYLOADER "MyLoader"
+#define NAME_PARTITION_TABLE "Partition Table"
+#define BLOCK_LEN_MIN 0x10000
+
+int parse_myloader_partitions(struct mtd_info *master,
+ struct mtd_partition **pparts,
+ unsigned long origin)
+{
+ struct mylo_partition_table *tab;
+ struct mylo_partition *part;
+ struct mtd_partition *mtd_parts;
+ struct mtd_partition *mtd_part;
+ int num_parts;
+ int ret, i;
+ size_t retlen;
+ char *names;
+ unsigned long offset;
+ unsigned long blocklen;
+
+ tab = vmalloc(sizeof(*tab));
+ if (!tab) {
+ return -ENOMEM;
+ goto out;
+ }
+
+ blocklen = master->erasesize;
+ if (blocklen < BLOCK_LEN_MIN)
+ blocklen = BLOCK_LEN_MIN;
+
+ /* Partition Table is always located on the second erase block */
+ offset = blocklen;
+ printk(KERN_NOTICE "%s: searching for MyLoader partition table at "
+ "offset 0x%lx\n", master->name, offset);
+
+ ret = master->read(master, offset, sizeof(*tab), &retlen, (void *)tab);
+ if (ret)
+ goto out;
+
+ if (retlen != sizeof(*tab)) {
+ ret = -EIO;
+ goto out_free_buf;
+ }
+
+ /* Check for Partition Table magic number */
+ if (tab->magic != le32_to_cpu(MYLO_MAGIC_PARTITIONS)) {
+ printk(KERN_NOTICE "%s: no MyLoader partition table found\n",
+ master->name);
+ ret = 0;
+ goto out_free_buf;
+ }
+
+ /* The MyLoader and the Partition Table is always present */
+ num_parts = 2;
+
+ /* Detect number of used partitions */
+ for (i = 0; i < MYLO_MAX_PARTITIONS; i++) {
+ part = &tab->partitions[i];
+
+ if (le16_to_cpu(part->type) == PARTITION_TYPE_FREE)
+ continue;
+
+ num_parts++;
+ }
+
+ mtd_parts = kzalloc((num_parts * sizeof(*mtd_part) +
+ num_parts * NAME_LEN_MAX), GFP_KERNEL);
+
+ if (!mtd_parts) {
+ ret = -ENOMEM;
+ goto out_free_buf;
+ }
+
+ mtd_part = mtd_parts;
+ names = (char *)&mtd_parts[num_parts];
+
+ strncpy(names, NAME_MYLOADER, NAME_LEN_MAX-1);
+ mtd_part->name = names;
+ mtd_part->offset = 0;
+ mtd_part->size = blocklen;
+ mtd_part->mask_flags = MTD_WRITEABLE;
+ mtd_part++;
+ names += NAME_LEN_MAX;
+
+ strncpy(names, NAME_PARTITION_TABLE, NAME_LEN_MAX-1);
+ mtd_part->name = names;
+ mtd_part->offset = blocklen;
+ mtd_part->size = blocklen;
+ mtd_part->mask_flags = MTD_WRITEABLE;
+ mtd_part++;
+ names += NAME_LEN_MAX;
+
+ for (i = 0; i < MYLO_MAX_PARTITIONS; i++) {
+ part = &tab->partitions[i];
+
+ if (le16_to_cpu(part->type) == PARTITION_TYPE_FREE)
+ continue;
+
+ sprintf(names, "partition%d", i);
+ mtd_part->offset = le32_to_cpu(part->addr);
+ mtd_part->size = le32_to_cpu(part->size);
+ mtd_part->name = names;
+ mtd_part++;
+ names += NAME_LEN_MAX;
+ }
+
+ *pparts = mtd_parts;
+ ret = num_parts;
+
+out_free_buf:
+ vfree(tab);
+out:
+ return ret;
+}
+
+static struct mtd_part_parser mylo_mtd_parser = {
+ .owner = THIS_MODULE,
+ .parse_fn = parse_myloader_partitions,
+ .name = NAME_MYLOADER,
+};
+
+static int __init mylo_mtd_parser_init(void)
+{
+ return register_mtd_parser(&mylo_mtd_parser);
+}
+
+static void __exit mylo_mtd_parser_exit(void)
+{
+ deregister_mtd_parser(&mylo_mtd_parser);
+}
+
+module_init(mylo_mtd_parser_init);
+module_exit(mylo_mtd_parser_exit);
+
+MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
+MODULE_DESCRIPTION("Parsing code for MyLoader partition tables");
+MODULE_LICENSE("GPL v2");
--- /dev/null
+/*
+ * Copyright (C) Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/list.h>
+#include <linux/kmod.h>
+#include <linux/root_dev.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <linux/byteorder/generic.h>
+
+#define PFX "trxsplit: "
+
+#define TRX_MAGIC 0x30524448 /* "HDR0" */
+#define TRX_VERSION 1
+#define TRX_MAX_LEN 0x3A0000
+#define TRX_NO_HEADER 0x1 /* do not write TRX header */
+#define TRX_GZ_FILES 0x2 /* contains individual gzip files */
+#define TRX_MAX_OFFSET 3
+#define TRX_MIN_KERNEL_SIZE 256*1024
+
+struct trx_header {
+ u32 magic; /* "HDR0" */
+ u32 len; /* Length of file including header */
+ u32 crc32; /* 32-bit CRC from flag_version to end of file */
+ u32 flag_version; /* 0:15 flags, 16:31 version */
+ u32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions */
+};
+
+#define TRX_ALIGN 0x1000
+
+static int trx_nr_parts;
+static unsigned long trx_offset;
+static struct mtd_info *trx_mtd;
+static struct mtd_partition trx_parts[TRX_MAX_OFFSET];
+static struct trx_header trx_hdr;
+
+static int trxsplit_refresh_partitions(struct mtd_info *mtd);
+
+static int trxsplit_checktrx(struct mtd_info *mtd, unsigned long offset)
+{
+ size_t retlen;
+ int err;
+
+ err = mtd->read(mtd, offset, sizeof(trx_hdr), &retlen,
+ (void *)&trx_hdr);
+ if (err) {
+ printk(KERN_ALERT PFX "unable to read from '%s'\n", mtd->name);
+ goto err_out;
+ }
+
+ if (retlen != sizeof(trx_hdr)) {
+ printk(KERN_ALERT PFX "reading failed on '%s'\n", mtd->name);
+ goto err_out;
+ }
+
+ trx_hdr.magic = le32_to_cpu(trx_hdr.magic);
+ trx_hdr.len = le32_to_cpu(trx_hdr.len);
+ trx_hdr.crc32 = le32_to_cpu(trx_hdr.crc32);
+ trx_hdr.flag_version = le32_to_cpu(trx_hdr.flag_version);
+ trx_hdr.offsets[0] = le32_to_cpu(trx_hdr.offsets[0]);
+ trx_hdr.offsets[1] = le32_to_cpu(trx_hdr.offsets[1]);
+ trx_hdr.offsets[2] = le32_to_cpu(trx_hdr.offsets[2]);
+
+ /* sanity checks */
+ if (trx_hdr.magic != TRX_MAGIC)
+ goto err_out;
+
+ if (trx_hdr.len > mtd->size - offset)
+ goto err_out;
+
+ /* TODO: add crc32 checking too? */
+
+ return 0;
+
+err_out:
+ return -1;
+}
+
+static void trxsplit_findtrx(struct mtd_info *mtd)
+{
+ unsigned long offset;
+ int err;
+
+ printk(KERN_INFO PFX "searching TRX header in '%s'\n", mtd->name);
+
+ err = 0;
+ for (offset = 0; offset < mtd->size; offset += TRX_ALIGN) {
+ err = trxsplit_checktrx(mtd, offset);
+ if (err == 0)
+ break;
+ }
+
+ if (err)
+ return;
+
+ printk(KERN_INFO PFX "TRX header found at 0x%lX\n", offset);
+
+ trx_mtd = mtd;
+ trx_offset = offset;
+}
+
+static void trxsplit_create_partitions(struct mtd_info *mtd)
+{
+ struct mtd_partition *part = trx_parts;
+ int err;
+ int i;
+
+ for (i = 0; i < TRX_MAX_OFFSET; i++) {
+ part = &trx_parts[i];
+ if (trx_hdr.offsets[i] == 0)
+ continue;
+ part->offset = trx_offset + trx_hdr.offsets[i];
+ trx_nr_parts++;
+ }
+
+ for (i = 0; i < trx_nr_parts-1; i++)
+ trx_parts[i].size = trx_parts[i+1].offset - trx_parts[i].offset;
+
+ trx_parts[i].size = mtd->size - trx_parts[i].offset;
+
+ i = 0;
+ part = &trx_parts[i];
+ if (part->size < TRX_MIN_KERNEL_SIZE) {
+ part->name = "loader";
+ i++;
+ }
+
+ part = &trx_parts[i];
+ part->name = "kernel";
+ i++;
+
+ part = &trx_parts[i];
+ part->name = "rootfs";
+
+ err = add_mtd_partitions(mtd, trx_parts, trx_nr_parts);
+ if (err) {
+ printk(KERN_ALERT PFX "adding TRX partitions failed\n");
+ return;
+ }
+
+ mtd->refresh_device = trxsplit_refresh_partitions;
+}
+
+static int trxsplit_refresh_partitions(struct mtd_info *mtd)
+{
+ printk(KERN_INFO PFX "refreshing TRX partitions in '%s' (%d,%d)\n",
+ mtd->name, MTD_BLOCK_MAJOR, mtd->index);
+
+ /* remove old partitions */
+ del_mtd_partitions(mtd);
+
+ trxsplit_findtrx(mtd);
+ if (!trx_mtd)
+ goto err;
+
+ trxsplit_create_partitions(trx_mtd);
+ return 1;
+
+err:
+ return 0;
+}
+
+static void __init trxsplit_add_mtd(struct mtd_info *mtd)
+{
+ if (mtd->type != MTD_NORFLASH) {
+ printk(KERN_INFO PFX "'%s' is not a NOR flash, skipped\n",
+ mtd->name);
+ return;
+ }
+
+ if (!trx_mtd)
+ trxsplit_findtrx(mtd);
+}
+
+static void __init trxsplit_remove_mtd(struct mtd_info *mtd)
+{
+ /* nothing to do */
+}
+
+static struct mtd_notifier trxsplit_notifier __initdata = {
+ .add = trxsplit_add_mtd,
+ .remove = trxsplit_remove_mtd,
+};
+
+static void __init trxsplit_scan(void)
+{
+ register_mtd_user(&trxsplit_notifier);
+ unregister_mtd_user(&trxsplit_notifier);
+}
+
+static int __init trxsplit_init(void)
+{
+ trxsplit_scan();
+
+ if (trx_mtd) {
+ printk(KERN_INFO PFX "creating TRX partitions in '%s' "
+ "(%d,%d)\n", trx_mtd->name, MTD_BLOCK_MAJOR,
+ trx_mtd->index);
+ trxsplit_create_partitions(trx_mtd);
+ }
+
+ return 0;
+}
+
+late_initcall(trxsplit_init);
--- /dev/null
+/*
+ * ADM5120 built-in ethernet switch driver
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This code was based on a driver for Linux 2.6.xx by Jeroen Vreeken.
+ * Copyright Jeroen Vreeken (pe1rxq@amsat.org), 2005
+ * NAPI extension for the Jeroen's driver
+ * Copyright Thomas Langer (Thomas.Langer@infineon.com), 2007
+ * Copyright Friedrich Beckmann (Friedrich.Beckmann@infineon.com), 2007
+ * Inspiration for the Jeroen's driver came from the ADMtek 2.4 driver.
+ * Copyright ADMtek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/spinlock.h>
+#include <linux/platform_device.h>
+
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+
+#include <linux/io.h>
+#include <linux/irq.h>
+
+#include <asm/mipsregs.h>
+
+#include <asm/mach-adm5120/adm5120_info.h>
+#include <asm/mach-adm5120/adm5120_defs.h>
+#include <asm/mach-adm5120/adm5120_irq.h>
+#include <asm/mach-adm5120/adm5120_switch.h>
+
+#include "adm5120sw.h"
+
+#define DRV_NAME "adm5120-switch"
+#define DRV_DESC "ADM5120 built-in ethernet switch driver"
+#define DRV_VERSION "0.1.1"
+
+#define CONFIG_ADM5120_SWITCH_NAPI 1
+#undef CONFIG_ADM5120_SWITCH_DEBUG
+
+/* ------------------------------------------------------------------------ */
+
+#ifdef CONFIG_ADM5120_SWITCH_DEBUG
+#define SW_DBG(f, a...) printk(KERN_DBG "%s: " f, DRV_NAME , ## a)
+#else
+#define SW_DBG(f, a...) do {} while (0)
+#endif
+#define SW_ERR(f, a...) printk(KERN_ERR "%s: " f, DRV_NAME , ## a)
+#define SW_INFO(f, a...) printk(KERN_INFO "%s: " f, DRV_NAME , ## a)
+
+#define SWITCH_NUM_PORTS 6
+#define ETH_CSUM_LEN 4
+
+#define RX_MAX_PKTLEN 1550
+#define RX_RING_SIZE 64
+
+#define TX_RING_SIZE 32
+#define TX_QUEUE_LEN 28 /* Limit ring entries actually used. */
+#define TX_TIMEOUT HZ*400
+
+#define RX_DESCS_SIZE (RX_RING_SIZE * sizeof(struct dma_desc *))
+#define RX_SKBS_SIZE (RX_RING_SIZE * sizeof(struct sk_buff *))
+#define TX_DESCS_SIZE (TX_RING_SIZE * sizeof(struct dma_desc *))
+#define TX_SKBS_SIZE (TX_RING_SIZE * sizeof(struct sk_buff *))
+
+#define SKB_ALLOC_LEN (RX_MAX_PKTLEN + 32)
+#define SKB_RESERVE_LEN (NET_IP_ALIGN + NET_SKB_PAD)
+
+#define SWITCH_INTS_HIGH (SWITCH_INT_SHD | SWITCH_INT_RHD | SWITCH_INT_HDF)
+#define SWITCH_INTS_LOW (SWITCH_INT_SLD | SWITCH_INT_RLD | SWITCH_INT_LDF)
+#define SWITCH_INTS_ERR (SWITCH_INT_RDE | SWITCH_INT_SDE | SWITCH_INT_CPUH)
+#define SWITCH_INTS_Q (SWITCH_INT_P0QF | SWITCH_INT_P1QF | SWITCH_INT_P2QF | \
+ SWITCH_INT_P3QF | SWITCH_INT_P4QF | SWITCH_INT_P5QF | \
+ SWITCH_INT_CPQF | SWITCH_INT_GQF)
+
+#define SWITCH_INTS_ALL (SWITCH_INTS_HIGH | SWITCH_INTS_LOW | \
+ SWITCH_INTS_ERR | SWITCH_INTS_Q | \
+ SWITCH_INT_MD | SWITCH_INT_PSC)
+
+#define SWITCH_INTS_USED (SWITCH_INTS_LOW | SWITCH_INT_PSC)
+#define SWITCH_INTS_POLL (SWITCH_INT_RLD | SWITCH_INT_LDF | SWITCH_INT_SLD)
+
+/* ------------------------------------------------------------------------ */
+
+struct adm5120_if_priv {
+ struct net_device *dev;
+
+ unsigned int vlan_no;
+ unsigned int port_mask;
+
+#ifdef CONFIG_ADM5120_SWITCH_NAPI
+ struct napi_struct napi;
+#endif
+};
+
+struct dma_desc {
+ __u32 buf1;
+#define DESC_OWN (1UL << 31) /* Owned by the switch */
+#define DESC_EOR (1UL << 28) /* End of Ring */
+#define DESC_ADDR_MASK 0x1FFFFFF
+#define DESC_ADDR(x) ((__u32)(x) & DESC_ADDR_MASK)
+ __u32 buf2;
+#define DESC_BUF2_EN (1UL << 31) /* Buffer 2 enable */
+ __u32 buflen;
+ __u32 misc;
+/* definitions for tx/rx descriptors */
+#define DESC_PKTLEN_SHIFT 16
+#define DESC_PKTLEN_MASK 0x7FF
+/* tx descriptor specific part */
+#define DESC_CSUM (1UL << 31) /* Append checksum */
+#define DESC_DSTPORT_SHIFT 8
+#define DESC_DSTPORT_MASK 0x3F
+#define DESC_VLAN_MASK 0x3F
+/* rx descriptor specific part */
+#define DESC_SRCPORT_SHIFT 12
+#define DESC_SRCPORT_MASK 0x7
+#define DESC_DA_MASK 0x3
+#define DESC_DA_SHIFT 4
+#define DESC_IPCSUM_FAIL (1UL << 3) /* IP checksum fail */
+#define DESC_VLAN_TAG (1UL << 2) /* VLAN tag present */
+#define DESC_TYPE_MASK 0x3 /* mask for Packet type */
+#define DESC_TYPE_IP 0x0 /* IP packet */
+#define DESC_TYPE_PPPoE 0x1 /* PPPoE packet */
+} __attribute__ ((aligned(16)));
+
+/* ------------------------------------------------------------------------ */
+
+static int adm5120_nrdevs;
+
+static struct net_device *adm5120_devs[SWITCH_NUM_PORTS];
+/* Lookup table port -> device */
+static struct net_device *adm5120_port[SWITCH_NUM_PORTS];
+
+static struct dma_desc *txl_descs;
+static struct dma_desc *rxl_descs;
+
+static dma_addr_t txl_descs_dma;
+static dma_addr_t rxl_descs_dma;
+
+static struct sk_buff **txl_skbuff;
+static struct sk_buff **rxl_skbuff;
+
+static unsigned int cur_rxl, dirty_rxl; /* producer/consumer ring indices */
+static unsigned int cur_txl, dirty_txl;
+
+static unsigned int sw_used;
+
+static spinlock_t tx_lock = SPIN_LOCK_UNLOCKED;
+
+/* ------------------------------------------------------------------------ */
+
+static inline u32 sw_read_reg(u32 reg)
+{
+ return __raw_readl((void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE)+reg);
+}
+
+static inline void sw_write_reg(u32 reg, u32 val)
+{
+ __raw_writel(val, (void __iomem *)KSEG1ADDR(ADM5120_SWITCH_BASE)+reg);
+}
+
+static inline void sw_int_mask(u32 mask)
+{
+ u32 t;
+
+ t = sw_read_reg(SWITCH_REG_INT_MASK);
+ t |= mask;
+ sw_write_reg(SWITCH_REG_INT_MASK, t);
+}
+
+static inline void sw_int_unmask(u32 mask)
+{
+ u32 t;
+
+ t = sw_read_reg(SWITCH_REG_INT_MASK);
+ t &= ~mask;
+ sw_write_reg(SWITCH_REG_INT_MASK, t);
+}
+
+static inline void sw_int_ack(u32 mask)
+{
+ sw_write_reg(SWITCH_REG_INT_STATUS, mask);
+}
+
+static inline u32 sw_int_status(void)
+{
+ u32 t;
+
+ t = sw_read_reg(SWITCH_REG_INT_STATUS);
+ t &= ~sw_read_reg(SWITCH_REG_INT_MASK);
+ return t;
+}
+
+static inline u32 desc_get_srcport(struct dma_desc *desc)
+{
+ return (desc->misc >> DESC_SRCPORT_SHIFT) & DESC_SRCPORT_MASK;
+}
+
+static inline u32 desc_get_pktlen(struct dma_desc *desc)
+{
+ return (desc->misc >> DESC_PKTLEN_SHIFT) & DESC_PKTLEN_MASK;
+}
+
+static inline int desc_ipcsum_fail(struct dma_desc *desc)
+{
+ return ((desc->misc & DESC_IPCSUM_FAIL) != 0);
+}
+
+/* ------------------------------------------------------------------------ */
+
+static void sw_dump_desc(char *label, struct dma_desc *desc, int tx)
+{
+ u32 t;
+
+ SW_DBG("%s %s desc/%p\n", label, tx ? "tx" : "rx", desc);
+
+ t = desc->buf1;
+ SW_DBG(" buf1 %08X addr=%08X; len=%08X %s%s\n", t,
+ t & DESC_ADDR_MASK,
+ desc->buflen,
+ (t & DESC_OWN) ? "SWITCH" : "CPU",
+ (t & DESC_EOR) ? " RE" : "");
+
+ t = desc->buf2;
+ SW_DBG(" buf2 %08X addr=%08X%s\n", desc->buf2,
+ t & DESC_ADDR_MASK,
+ (t & DESC_BUF2_EN) ? " EN" : "" );
+
+ t = desc->misc;
+ if (tx)
+ SW_DBG(" misc %08X%s pktlen=%04X ports=%02X vlan=%02X\n", t,
+ (t & DESC_CSUM) ? " CSUM" : "",
+ (t >> DESC_PKTLEN_SHIFT) & DESC_PKTLEN_MASK,
+ (t >> DESC_DSTPORT_SHIFT) & DESC_DSTPORT_MASK,
+ t & DESC_VLAN_MASK);
+ else
+ SW_DBG(" misc %08X pktlen=%04X port=%d DA=%d%s%s type=%d\n",
+ t,
+ (t >> DESC_PKTLEN_SHIFT) & DESC_PKTLEN_MASK,
+ (t >> DESC_SRCPORT_SHIFT) & DESC_SRCPORT_MASK,
+ (t >> DESC_DA_SHIFT) & DESC_DA_MASK,
+ (t & DESC_IPCSUM_FAIL) ? " IPCF" : "",
+ (t & DESC_VLAN_TAG) ? " VLAN" : "",
+ (t & DESC_TYPE_MASK));
+}
+
+static void sw_dump_intr_mask(char *label, u32 mask)
+{
+ SW_DBG("%s %08X%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
+ label, mask,
+ (mask & SWITCH_INT_SHD) ? " SHD" : "",
+ (mask & SWITCH_INT_SLD) ? " SLD" : "",
+ (mask & SWITCH_INT_RHD) ? " RHD" : "",
+ (mask & SWITCH_INT_RLD) ? " RLD" : "",
+ (mask & SWITCH_INT_HDF) ? " HDF" : "",
+ (mask & SWITCH_INT_LDF) ? " LDF" : "",
+ (mask & SWITCH_INT_P0QF) ? " P0QF" : "",
+ (mask & SWITCH_INT_P1QF) ? " P1QF" : "",
+ (mask & SWITCH_INT_P2QF) ? " P2QF" : "",
+ (mask & SWITCH_INT_P3QF) ? " P3QF" : "",
+ (mask & SWITCH_INT_P4QF) ? " P4QF" : "",
+ (mask & SWITCH_INT_CPQF) ? " CPQF" : "",
+ (mask & SWITCH_INT_GQF) ? " GQF" : "",
+ (mask & SWITCH_INT_MD) ? " MD" : "",
+ (mask & SWITCH_INT_BCS) ? " BCS" : "",
+ (mask & SWITCH_INT_PSC) ? " PSC" : "",
+ (mask & SWITCH_INT_ID) ? " ID" : "",
+ (mask & SWITCH_INT_W0TE) ? " W0TE" : "",
+ (mask & SWITCH_INT_W1TE) ? " W1TE" : "",
+ (mask & SWITCH_INT_RDE) ? " RDE" : "",
+ (mask & SWITCH_INT_SDE) ? " SDE" : "",
+ (mask & SWITCH_INT_CPUH) ? " CPUH" : "");
+}
+
+static void sw_dump_regs(void)
+{
+ u32 t;
+
+ t = sw_read_reg(SWITCH_REG_PHY_STATUS);
+ SW_DBG("phy_status: %08X\n", t);
+
+ t = sw_read_reg(SWITCH_REG_CPUP_CONF);
+ SW_DBG("cpup_conf: %08X%s%s%s\n", t,
+ (t & CPUP_CONF_DCPUP) ? " DCPUP" : "",
+ (t & CPUP_CONF_CRCP) ? " CRCP" : "",
+ (t & CPUP_CONF_BTM) ? " BTM" : "");
+
+ t = sw_read_reg(SWITCH_REG_PORT_CONF0);
+ SW_DBG("port_conf0: %08X\n", t);
+ t = sw_read_reg(SWITCH_REG_PORT_CONF1);
+ SW_DBG("port_conf1: %08X\n", t);
+ t = sw_read_reg(SWITCH_REG_PORT_CONF2);
+ SW_DBG("port_conf2: %08X\n", t);
+
+ t = sw_read_reg(SWITCH_REG_VLAN_G1);
+ SW_DBG("vlan g1: %08X\n", t);
+ t = sw_read_reg(SWITCH_REG_VLAN_G2);
+ SW_DBG("vlan g2: %08X\n", t);
+
+ t = sw_read_reg(SWITCH_REG_BW_CNTL0);
+ SW_DBG("bw_cntl0: %08X\n", t);
+ t = sw_read_reg(SWITCH_REG_BW_CNTL1);
+ SW_DBG("bw_cntl1: %08X\n", t);
+
+ t = sw_read_reg(SWITCH_REG_PHY_CNTL0);
+ SW_DBG("phy_cntl0: %08X\n", t);
+ t = sw_read_reg(SWITCH_REG_PHY_CNTL1);
+ SW_DBG("phy_cntl1: %08X\n", t);
+ t = sw_read_reg(SWITCH_REG_PHY_CNTL2);
+ SW_DBG("phy_cntl2: %08X\n", t);
+ t = sw_read_reg(SWITCH_REG_PHY_CNTL3);
+ SW_DBG("phy_cntl3: %08X\n", t);
+ t = sw_read_reg(SWITCH_REG_PHY_CNTL4);
+ SW_DBG("phy_cntl4: %08X\n", t);
+
+ t = sw_read_reg(SWITCH_REG_INT_STATUS);
+ sw_dump_intr_mask("int_status: ", t);
+
+ t = sw_read_reg(SWITCH_REG_INT_MASK);
+ sw_dump_intr_mask("int_mask: ", t);
+
+ t = sw_read_reg(SWITCH_REG_SHDA);
+ SW_DBG("shda: %08X\n", t);
+ t = sw_read_reg(SWITCH_REG_SLDA);
+ SW_DBG("slda: %08X\n", t);
+ t = sw_read_reg(SWITCH_REG_RHDA);
+ SW_DBG("rhda: %08X\n", t);
+ t = sw_read_reg(SWITCH_REG_RLDA);
+ SW_DBG("rlda: %08X\n", t);
+}
+
+/* ------------------------------------------------------------------------ */
+
+static inline void adm5120_rx_dma_update(struct dma_desc *desc,
+ struct sk_buff *skb, int end)
+{
+ desc->misc = 0;
+ desc->buf2 = 0;
+ desc->buflen = RX_MAX_PKTLEN;
+ desc->buf1 = DESC_ADDR(skb->data) |
+ DESC_OWN | (end ? DESC_EOR : 0);
+}
+
+static void adm5120_switch_rx_refill(void)
+{
+ unsigned int entry;
+
+ for (; cur_rxl - dirty_rxl > 0; dirty_rxl++) {
+ struct dma_desc *desc;
+ struct sk_buff *skb;
+
+ entry = dirty_rxl % RX_RING_SIZE;
+ desc = &rxl_descs[entry];
+
+ skb = rxl_skbuff[entry];
+ if (skb == NULL) {
+ skb = alloc_skb(SKB_ALLOC_LEN, GFP_ATOMIC);
+ if (skb) {
+ skb_reserve(skb, SKB_RESERVE_LEN);
+ rxl_skbuff[entry] = skb;
+ } else {
+ SW_ERR("no memory for skb\n");
+ desc->buflen = 0;
+ desc->buf2 = 0;
+ desc->misc = 0;
+ desc->buf1 = (desc->buf1 & DESC_EOR) | DESC_OWN;
+ break;
+ }
+ }
+
+ desc->buf2 = 0;
+ desc->buflen = RX_MAX_PKTLEN;
+ desc->misc = 0;
+ desc->buf1 = (desc->buf1 & DESC_EOR) | DESC_OWN |
+ DESC_ADDR(skb->data);
+ }
+}
+
+static int adm5120_switch_rx(int limit)
+{
+ unsigned int done = 0;
+
+ SW_DBG("rx start, limit=%d, cur_rxl=%u, dirty_rxl=%u\n",
+ limit, cur_rxl, dirty_rxl);
+
+ while (done < limit) {
+ int entry = cur_rxl % RX_RING_SIZE;
+ struct dma_desc *desc = &rxl_descs[entry];
+ struct net_device *rdev;
+ unsigned int port;
+
+ if (desc->buf1 & DESC_OWN)
+ break;
+
+ if (dirty_rxl + RX_RING_SIZE == cur_rxl)
+ break;
+
+ port = desc_get_srcport(desc);
+ rdev = adm5120_port[port];
+
+ SW_DBG("rx descriptor %u, desc=%p, skb=%p\n", entry, desc,
+ rxl_skbuff[entry]);
+
+ if ((rdev) && netif_running(rdev)) {
+ struct sk_buff *skb = rxl_skbuff[entry];
+ int pktlen;
+
+ pktlen = desc_get_pktlen(desc);
+ pktlen -= ETH_CSUM_LEN;
+
+ if ((pktlen == 0) || desc_ipcsum_fail(desc)) {
+ rdev->stats.rx_errors++;
+ if (pktlen == 0)
+ rdev->stats.rx_length_errors++;
+ if (desc_ipcsum_fail(desc))
+ rdev->stats.rx_crc_errors++;
+ SW_DBG("rx error, recycling skb %u\n", entry);
+ } else {
+ skb_put(skb, pktlen);
+
+ skb->dev = rdev;
+ skb->protocol = eth_type_trans(skb, rdev);
+ skb->ip_summed = CHECKSUM_UNNECESSARY;
+
+ dma_cache_wback_inv((unsigned long)skb->data,
+ skb->len);
+
+#ifdef CONFIG_ADM5120_SWITCH_NAPI
+ netif_receive_skb(skb);
+#else
+ netif_rx(skb);
+#endif
+
+ rdev->last_rx = jiffies;
+ rdev->stats.rx_packets++;
+ rdev->stats.rx_bytes += pktlen;
+
+ rxl_skbuff[entry] = NULL;
+ done++;
+ }
+ } else {
+ SW_DBG("no rx device, recycling skb %u\n", entry);
+ }
+
+ cur_rxl++;
+ if (cur_rxl - dirty_rxl > RX_RING_SIZE / 4)
+ adm5120_switch_rx_refill();
+ }
+
+ adm5120_switch_rx_refill();
+
+ SW_DBG("rx finished, cur_rxl=%u, dirty_rxl=%u, processed %d\n",
+ cur_rxl, dirty_rxl, done);
+
+ return done;
+}
+
+static void adm5120_switch_tx(void)
+{
+ unsigned int entry;
+
+ spin_lock(&tx_lock);
+ entry = dirty_txl % TX_RING_SIZE;
+ while (dirty_txl != cur_txl) {
+ struct dma_desc *desc = &txl_descs[entry];
+ struct sk_buff *skb = txl_skbuff[entry];
+
+ if (desc->buf1 & DESC_OWN)
+ break;
+
+ if (netif_running(skb->dev)) {
+ skb->dev->stats.tx_bytes += skb->len;
+ skb->dev->stats.tx_packets++;
+ }
+
+ dev_kfree_skb_irq(skb);
+ txl_skbuff[entry] = NULL;
+ entry = (++dirty_txl) % TX_RING_SIZE;
+ }
+
+ if ((cur_txl - dirty_txl) < TX_QUEUE_LEN - 4) {
+ int i;
+ for (i = 0; i < SWITCH_NUM_PORTS; i++) {
+ if (!adm5120_devs[i])
+ continue;
+ netif_wake_queue(adm5120_devs[i]);
+ }
+ }
+ spin_unlock(&tx_lock);
+}
+
+#ifdef CONFIG_ADM5120_SWITCH_NAPI
+static int adm5120_if_poll(struct napi_struct *napi, int limit)
+{
+ struct adm5120_if_priv *priv = container_of(napi,
+ struct adm5120_if_priv, napi);
+ struct net_device *dev = priv->dev;
+ int done;
+ u32 status;
+
+ sw_int_ack(SWITCH_INTS_POLL);
+
+ SW_DBG("%s: processing TX ring\n", dev->name);
+ adm5120_switch_tx();
+
+ SW_DBG("%s: processing RX ring\n", dev->name);
+ done = adm5120_switch_rx(limit);
+
+ status = sw_int_status() & SWITCH_INTS_POLL;
+ if ((done < limit) && (!status)) {
+ SW_DBG("disable polling mode for %s\n", dev->name);
+ netif_rx_complete(dev, napi);
+ sw_int_unmask(SWITCH_INTS_POLL);
+ return 0;
+ }
+
+ SW_DBG("%s still in polling mode, done=%d, status=%x\n",
+ dev->name, done, status);
+ return 1;
+}
+#endif /* CONFIG_ADM5120_SWITCH_NAPI */
+
+
+static irqreturn_t adm5120_switch_irq(int irq, void *dev_id)
+{
+ u32 status;
+
+ status = sw_int_status();
+ status &= SWITCH_INTS_ALL;
+ if (!status)
+ return IRQ_NONE;
+
+#ifdef CONFIG_ADM5120_SWITCH_NAPI
+ sw_int_ack(status & ~SWITCH_INTS_POLL);
+
+ if (status & SWITCH_INTS_POLL) {
+ struct net_device *dev = dev_id;
+ struct adm5120_if_priv *priv = netdev_priv(dev);
+
+ sw_dump_intr_mask("poll ints", status);
+ SW_DBG("enable polling mode for %s\n", dev->name);
+ sw_int_mask(SWITCH_INTS_POLL);
+ netif_rx_schedule(dev, &priv->napi);
+ }
+#else
+ sw_int_ack(status);
+
+ if (status & (SWITCH_INT_RLD | SWITCH_INT_LDF)) {
+ adm5120_switch_rx(RX_RING_SIZE);
+ }
+
+ if (status & SWITCH_INT_SLD) {
+ adm5120_switch_tx();
+ }
+#endif
+
+ return IRQ_HANDLED;
+}
+
+static void adm5120_set_bw(char *matrix)
+{
+ unsigned long val;
+
+ /* Port 0 to 3 are set using the bandwidth control 0 register */
+ val = matrix[0] + (matrix[1]<<8) + (matrix[2]<<16) + (matrix[3]<<24);
+ sw_write_reg(SWITCH_REG_BW_CNTL0, val);
+
+ /* Port 4 and 5 are set using the bandwidth control 1 register */
+ val = matrix[4];
+ if (matrix[5] == 1)
+ sw_write_reg(SWITCH_REG_BW_CNTL1, val | 0x80000000);
+ else
+ sw_write_reg(SWITCH_REG_BW_CNTL1, val & ~0x8000000);
+
+ SW_DBG("D: ctl0 0x%ux, ctl1 0x%ux\n", sw_read_reg(SWITCH_REG_BW_CNTL0),
+ sw_read_reg(SWITCH_REG_BW_CNTL1));
+}
+
+static void adm5120_switch_tx_ring_reset(struct dma_desc *desc,
+ struct sk_buff **skbl, int num)
+{
+ memset(desc, 0, num * sizeof(*desc));
+ desc[num-1].buf1 |= DESC_EOR;
+ memset(skbl, 0, sizeof(struct skb*)*num);
+
+ cur_txl = 0;
+ dirty_txl = 0;
+}
+
+static void adm5120_switch_rx_ring_reset(struct dma_desc *desc,
+ struct sk_buff **skbl, int num)
+{
+ int i;
+
+ memset(desc, 0, num * sizeof(*desc));
+ for (i = 0; i < num; i++) {
+ skbl[i] = dev_alloc_skb(SKB_ALLOC_LEN);
+ if (!skbl[i]) {
+ i = num;
+ break;
+ }
+ skb_reserve(skbl[i], SKB_RESERVE_LEN);
+ adm5120_rx_dma_update(&desc[i], skbl[i], (num-1==i));
+ }
+
+ cur_rxl = 0;
+ dirty_rxl = 0;
+}
+
+static int adm5120_switch_tx_ring_alloc(void)
+{
+ int err;
+
+ txl_descs = dma_alloc_coherent(NULL, TX_DESCS_SIZE, &txl_descs_dma,
+ GFP_ATOMIC);
+ if (!txl_descs) {
+ err = -ENOMEM;
+ goto err;
+ }
+
+ txl_skbuff = kzalloc(TX_SKBS_SIZE, GFP_KERNEL);
+ if (!txl_skbuff) {
+ err = -ENOMEM;
+ goto err;
+ }
+
+ return 0;
+
+err:
+ return err;
+}
+
+static void adm5120_switch_tx_ring_free(void)
+{
+ int i;
+
+ if (txl_skbuff) {
+ for (i = 0; i < TX_RING_SIZE; i++)
+ if (txl_skbuff[i])
+ kfree_skb(txl_skbuff[i]);
+ kfree(txl_skbuff);
+ }
+
+ if (txl_descs)
+ dma_free_coherent(NULL, TX_DESCS_SIZE, txl_descs,
+ txl_descs_dma);
+}
+
+static int adm5120_switch_rx_ring_alloc(void)
+{
+ int err;
+ int i;
+
+ /* init RX ring */
+ rxl_descs = dma_alloc_coherent(NULL, RX_DESCS_SIZE, &rxl_descs_dma,
+ GFP_ATOMIC);
+ if (!rxl_descs) {
+ err = -ENOMEM;
+ goto err;
+ }
+
+ rxl_skbuff = kzalloc(RX_SKBS_SIZE, GFP_KERNEL);
+ if (!rxl_skbuff) {
+ err = -ENOMEM;
+ goto err;
+ }
+
+ for (i = 0; i < RX_RING_SIZE; i++) {
+ struct sk_buff *skb;
+ skb = alloc_skb(SKB_ALLOC_LEN, GFP_ATOMIC);
+ if (!skb) {
+ err = -ENOMEM;
+ goto err;
+ }
+ rxl_skbuff[i] = skb;
+ skb_reserve(skb, SKB_RESERVE_LEN);
+ }
+
+ return 0;
+
+err:
+ return err;
+}
+
+static void adm5120_switch_rx_ring_free(void)
+{
+ int i;
+
+ if (rxl_skbuff) {
+ for (i = 0; i < RX_RING_SIZE; i++)
+ if (rxl_skbuff[i])
+ kfree_skb(rxl_skbuff[i]);
+ kfree(rxl_skbuff);
+ }
+
+ if (rxl_descs)
+ dma_free_coherent(NULL, RX_DESCS_SIZE, rxl_descs,
+ rxl_descs_dma);
+}
+
+static void adm5120_write_mac(struct net_device *dev)
+{
+ struct adm5120_if_priv *priv = netdev_priv(dev);
+ unsigned char *mac = dev->dev_addr;
+ u32 t;
+
+ t = mac[2] | (mac[3] << MAC_WT1_MAC3_SHIFT) |
+ (mac[4] << MAC_WT1_MAC4_SHIFT) | (mac[5] << MAC_WT1_MAC5_SHIFT);
+ sw_write_reg(SWITCH_REG_MAC_WT1, t);
+
+ t = (mac[0] << MAC_WT0_MAC0_SHIFT) | (mac[1] << MAC_WT0_MAC1_SHIFT) |
+ MAC_WT0_MAWC | MAC_WT0_WVE | (priv->vlan_no<<3);
+
+ sw_write_reg(SWITCH_REG_MAC_WT0, t);
+
+ while (!(sw_read_reg(SWITCH_REG_MAC_WT0) & MAC_WT0_MWD));
+}
+
+static void adm5120_set_vlan(char *matrix)
+{
+ unsigned long val;
+ int vlan_port, port;
+
+ val = matrix[0] + (matrix[1]<<8) + (matrix[2]<<16) + (matrix[3]<<24);
+ sw_write_reg(SWITCH_REG_VLAN_G1, val);
+ val = matrix[4] + (matrix[5]<<8);
+ sw_write_reg(SWITCH_REG_VLAN_G2, val);
+
+ /* Now set/update the port vs. device lookup table */
+ for (port=0; port<SWITCH_NUM_PORTS; port++) {
+ for (vlan_port=0; vlan_port<SWITCH_NUM_PORTS && !(matrix[vlan_port] & (0x00000001 << port)); vlan_port++);
+ if (vlan_port <SWITCH_NUM_PORTS)
+ adm5120_port[port] = adm5120_devs[vlan_port];
+ else
+ adm5120_port[port] = NULL;
+ }
+}
+
+static void adm5120_switch_set_vlan_mac(unsigned int vlan, unsigned char *mac)
+{
+ u32 t;
+
+ t = mac[2] | (mac[3] << MAC_WT1_MAC3_SHIFT)
+ | (mac[4] << MAC_WT1_MAC4_SHIFT)
+ | (mac[5] << MAC_WT1_MAC5_SHIFT);
+ sw_write_reg(SWITCH_REG_MAC_WT1, t);
+
+ t = (mac[0] << MAC_WT0_MAC0_SHIFT) | (mac[1] << MAC_WT0_MAC1_SHIFT) |
+ MAC_WT0_MAWC | MAC_WT0_WVE | (vlan << MAC_WT0_WVN_SHIFT) |
+ (MAC_WT0_WAF_STATIC << MAC_WT0_WAF_SHIFT);
+ sw_write_reg(SWITCH_REG_MAC_WT0, t);
+
+ do {
+ t = sw_read_reg(SWITCH_REG_MAC_WT0);
+ } while ((t & MAC_WT0_MWD) == 0);
+}
+
+static void adm5120_switch_set_vlan_ports(unsigned int vlan, u32 ports)
+{
+ unsigned int reg;
+ u32 t;
+
+ if (vlan < 4)
+ reg = SWITCH_REG_VLAN_G1;
+ else {
+ vlan -= 4;
+ reg = SWITCH_REG_VLAN_G2;
+ }
+
+ t = sw_read_reg(reg);
+ t &= ~(0xFF << (vlan*8));
+ t |= (ports << (vlan*8));
+ sw_write_reg(reg, t);
+}
+
+/* ------------------------------------------------------------------------ */
+
+#ifdef CONFIG_ADM5120_SWITCH_NAPI
+static inline void adm5120_if_napi_enable(struct net_device *dev)
+{
+ struct adm5120_if_priv *priv = netdev_priv(dev);
+ napi_enable(&priv->napi);
+}
+
+static inline void adm5120_if_napi_disable(struct net_device *dev)
+{
+ struct adm5120_if_priv *priv = netdev_priv(dev);
+ napi_disable(&priv->napi);
+}
+#else
+static inline void adm5120_if_napi_enable(struct net_device *dev) {}
+static inline void adm5120_if_napi_disable(struct net_device *dev) {}
+#endif /* CONFIG_ADM5120_SWITCH_NAPI */
+
+static int adm5120_if_open(struct net_device *dev)
+{
+ u32 t;
+ int err;
+ int i;
+
+ adm5120_if_napi_enable(dev);
+
+ err = request_irq(dev->irq, adm5120_switch_irq,
+ (IRQF_SHARED | IRQF_DISABLED), dev->name, dev);
+ if (err) {
+ SW_ERR("unable to get irq for %s\n", dev->name);
+ goto err;
+ }
+
+ if (!sw_used++)
+ /* enable interrupts on first open */
+ sw_int_unmask(SWITCH_INTS_USED);
+
+ /* enable (additional) port */
+ t = sw_read_reg(SWITCH_REG_PORT_CONF0);
+ for (i = 0; i < SWITCH_NUM_PORTS; i++) {
+ if (dev == adm5120_devs[i])
+ t &= ~adm5120_eth_vlans[i];
+ }
+ sw_write_reg(SWITCH_REG_PORT_CONF0, t);
+
+ netif_start_queue(dev);
+
+ return 0;
+
+err:
+ adm5120_if_napi_disable(dev);
+ return err;
+}
+
+static int adm5120_if_stop(struct net_device *dev)
+{
+ u32 t;
+ int i;
+
+ netif_stop_queue(dev);
+ adm5120_if_napi_disable(dev);
+
+ /* disable port if not assigned to other devices */
+ t = sw_read_reg(SWITCH_REG_PORT_CONF0);
+ t |= SWITCH_PORTS_NOCPU;
+ for (i = 0; i < SWITCH_NUM_PORTS; i++) {
+ if ((dev != adm5120_devs[i]) && netif_running(adm5120_devs[i]))
+ t &= ~adm5120_eth_vlans[i];
+ }
+ sw_write_reg(SWITCH_REG_PORT_CONF0, t);
+
+ if (!--sw_used)
+ sw_int_mask(SWITCH_INTS_USED);
+
+ free_irq(dev->irq, dev);
+
+ return 0;
+}
+
+static int adm5120_if_hard_start_xmit(struct sk_buff *skb,
+ struct net_device *dev)
+{
+ struct dma_desc *desc;
+ struct adm5120_if_priv *priv = netdev_priv(dev);
+ unsigned int entry;
+ unsigned long data;
+ int i;
+
+ /* lock switch irq */
+ spin_lock_irq(&tx_lock);
+
+ /* calculate the next TX descriptor entry. */
+ entry = cur_txl % TX_RING_SIZE;
+
+ desc = &txl_descs[entry];
+ if (desc->buf1 & DESC_OWN) {
+ /* We want to write a packet but the TX queue is still
+ * occupied by the DMA. We are faster than the DMA... */
+ SW_DBG("%s unable to transmit, packet dopped\n", dev->name);
+ dev_kfree_skb(skb);
+ dev->stats.tx_dropped++;
+ return 0;
+ }
+
+ txl_skbuff[entry] = skb;
+ data = (desc->buf1 & DESC_EOR);
+ data |= DESC_ADDR(skb->data);
+
+ desc->misc =
+ ((skb->len<ETH_ZLEN?ETH_ZLEN:skb->len) << DESC_PKTLEN_SHIFT) |
+ (0x1 << priv->vlan_no);
+
+ desc->buflen = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
+
+ desc->buf1 = data | DESC_OWN;
+ sw_write_reg(SWITCH_REG_SEND_TRIG, SEND_TRIG_STL);
+
+ cur_txl++;
+ if (cur_txl == dirty_txl + TX_QUEUE_LEN) {
+ for (i = 0; i < SWITCH_NUM_PORTS; i++) {
+ if (!adm5120_devs[i])
+ continue;
+ netif_stop_queue(adm5120_devs[i]);
+ }
+ }
+
+ dev->trans_start = jiffies;
+
+ spin_unlock_irq(&tx_lock);
+
+ return 0;
+}
+
+static void adm5120_if_tx_timeout(struct net_device *dev)
+{
+ SW_INFO("TX timeout on %s\n",dev->name);
+}
+
+static void adm5120_if_set_multicast_list(struct net_device *dev)
+{
+ struct adm5120_if_priv *priv = netdev_priv(dev);
+ u32 ports;
+ u32 t;
+
+ ports = adm5120_eth_vlans[priv->vlan_no] & SWITCH_PORTS_NOCPU;
+
+ t = sw_read_reg(SWITCH_REG_CPUP_CONF);
+ if (dev->flags & IFF_PROMISC)
+ /* enable unknown packets */
+ t &= ~(ports << CPUP_CONF_DUNP_SHIFT);
+ else
+ /* disable unknown packets */
+ t |= (ports << CPUP_CONF_DUNP_SHIFT);
+
+ if (dev->flags & IFF_PROMISC || dev->flags & IFF_ALLMULTI ||
+ dev->mc_count)
+ /* enable multicast packets */
+ t &= ~(ports << CPUP_CONF_DMCP_SHIFT);
+ else
+ /* disable multicast packets */
+ t |= (ports << CPUP_CONF_DMCP_SHIFT);
+
+ /* If there is any port configured to be in promiscuous mode, then the */
+ /* Bridge Test Mode has to be activated. This will result in */
+ /* transporting also packets learned in another VLAN to be forwarded */
+ /* to the CPU. */
+ /* The difficult scenario is when we want to build a bridge on the CPU.*/
+ /* Assume we have port0 and the CPU port in VLAN0 and port1 and the */
+ /* CPU port in VLAN1. Now we build a bridge on the CPU between */
+ /* VLAN0 and VLAN1. Both ports of the VLANs are set in promisc mode. */
+ /* Now assume a packet with ethernet source address 99 enters port 0 */
+ /* It will be forwarded to the CPU because it is unknown. Then the */
+ /* bridge in the CPU will send it to VLAN1 and it goes out at port 1. */
+ /* When now a packet with ethernet destination address 99 comes in at */
+ /* port 1 in VLAN1, then the switch has learned that this address is */
+ /* located at port 0 in VLAN0. Therefore the switch will drop */
+ /* this packet. In order to avoid this and to send the packet still */
+ /* to the CPU, the Bridge Test Mode has to be activated. */
+
+ /* Check if there is any vlan in promisc mode. */
+ if (t & (SWITCH_PORTS_NOCPU << CPUP_CONF_DUNP_SHIFT))
+ t &= ~CPUP_CONF_BTM; /* Disable Bridge Testing Mode */
+ else
+ t |= CPUP_CONF_BTM; /* Enable Bridge Testing Mode */
+
+ sw_write_reg(SWITCH_REG_CPUP_CONF, t);
+
+}
+
+static int adm5120_if_set_mac_address(struct net_device *dev, void *p)
+{
+ struct sockaddr *addr = p;
+
+ memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
+ adm5120_write_mac(dev);
+ return 0;
+}
+
+static int adm5120_if_do_ioctl(struct net_device *dev, struct ifreq *rq,
+ int cmd)
+{
+ int err;
+ struct adm5120_sw_info info;
+ struct adm5120_if_priv *priv = netdev_priv(dev);
+
+ switch(cmd) {
+ case SIOCGADMINFO:
+ info.magic = 0x5120;
+ info.ports = adm5120_nrdevs;
+ info.vlan = priv->vlan_no;
+ err = copy_to_user(rq->ifr_data, &info, sizeof(info));
+ if (err)
+ return -EFAULT;
+ break;
+ case SIOCSMATRIX:
+ if (!capable(CAP_NET_ADMIN))
+ return -EPERM;
+ err = copy_from_user(adm5120_eth_vlans, rq->ifr_data,
+ sizeof(adm5120_eth_vlans));
+ if (err)
+ return -EFAULT;
+ adm5120_set_vlan(adm5120_eth_vlans);
+ break;
+ case SIOCGMATRIX:
+ err = copy_to_user(rq->ifr_data, adm5120_eth_vlans,
+ sizeof(adm5120_eth_vlans));
+ if (err)
+ return -EFAULT;
+ break;
+ default:
+ return -EOPNOTSUPP;
+ }
+ return 0;
+}
+
+static struct net_device *adm5120_if_alloc(void)
+{
+ struct net_device *dev;
+ struct adm5120_if_priv *priv;
+
+ dev = alloc_etherdev(sizeof(*priv));
+ if (!dev)
+ return NULL;
+
+ priv = netdev_priv(dev);
+ priv->dev = dev;
+
+ dev->irq = ADM5120_IRQ_SWITCH;
+ dev->open = adm5120_if_open;
+ dev->hard_start_xmit = adm5120_if_hard_start_xmit;
+ dev->stop = adm5120_if_stop;
+ dev->set_multicast_list = adm5120_if_set_multicast_list;
+ dev->do_ioctl = adm5120_if_do_ioctl;
+ dev->tx_timeout = adm5120_if_tx_timeout;
+ dev->watchdog_timeo = TX_TIMEOUT;
+ dev->set_mac_address = adm5120_if_set_mac_address;
+
+#ifdef CONFIG_ADM5120_SWITCH_NAPI
+ netif_napi_add(dev, &priv->napi, adm5120_if_poll, 64);
+#endif
+
+ return dev;
+}
+
+/* ------------------------------------------------------------------------ */
+
+static void adm5120_switch_cleanup(void)
+{
+ int i;
+
+ /* disable interrupts */
+ sw_int_mask(SWITCH_INTS_ALL);
+
+ for (i = 0; i < SWITCH_NUM_PORTS; i++) {
+ struct net_device *dev = adm5120_devs[i];
+ if (dev) {
+ unregister_netdev(dev);
+ free_netdev(dev);
+ }
+ }
+
+ adm5120_switch_tx_ring_free();
+ adm5120_switch_rx_ring_free();
+}
+
+static int __init adm5120_switch_probe(struct platform_device *pdev)
+{
+ u32 t;
+ int i, err;
+
+ adm5120_nrdevs = adm5120_eth_num_ports;
+
+ t = CPUP_CONF_DCPUP | CPUP_CONF_CRCP |
+ SWITCH_PORTS_NOCPU << CPUP_CONF_DUNP_SHIFT |
+ SWITCH_PORTS_NOCPU << CPUP_CONF_DMCP_SHIFT ;
+ sw_write_reg(SWITCH_REG_CPUP_CONF, t);
+
+ t = (SWITCH_PORTS_NOCPU << PORT_CONF0_EMCP_SHIFT) |
+ (SWITCH_PORTS_NOCPU << PORT_CONF0_BP_SHIFT) |
+ (SWITCH_PORTS_NOCPU);
+ sw_write_reg(SWITCH_REG_PORT_CONF0, t);
+
+ /* setup ports to Autoneg/100M/Full duplex/Auto MDIX */
+ t = SWITCH_PORTS_PHY |
+ (SWITCH_PORTS_PHY << PHY_CNTL2_SC_SHIFT) |
+ (SWITCH_PORTS_PHY << PHY_CNTL2_DC_SHIFT) |
+ (SWITCH_PORTS_PHY << PHY_CNTL2_PHYR_SHIFT) |
+ (SWITCH_PORTS_PHY << PHY_CNTL2_AMDIX_SHIFT) |
+ PHY_CNTL2_RMAE;
+ sw_write_reg(SWITCH_REG_PHY_CNTL2, t);
+
+ t = sw_read_reg(SWITCH_REG_PHY_CNTL3);
+ t |= PHY_CNTL3_RNT;
+ sw_write_reg(SWITCH_REG_PHY_CNTL3, t);
+
+ /* Force all the packets from all ports are low priority */
+ sw_write_reg(SWITCH_REG_PRI_CNTL, 0);
+
+ sw_int_mask(SWITCH_INTS_ALL);
+ sw_int_ack(SWITCH_INTS_ALL);
+
+ err = adm5120_switch_rx_ring_alloc();
+ if (err)
+ goto err;
+
+ err = adm5120_switch_tx_ring_alloc();
+ if (err)
+ goto err;
+
+ adm5120_switch_tx_ring_reset(txl_descs, txl_skbuff, TX_RING_SIZE);
+ adm5120_switch_rx_ring_reset(rxl_descs, rxl_skbuff, RX_RING_SIZE);
+
+ sw_write_reg(SWITCH_REG_SHDA, 0);
+ sw_write_reg(SWITCH_REG_SLDA, KSEG1ADDR(txl_descs));
+ sw_write_reg(SWITCH_REG_RHDA, 0);
+ sw_write_reg(SWITCH_REG_RLDA, KSEG1ADDR(rxl_descs));
+
+ for (i = 0; i < SWITCH_NUM_PORTS; i++) {
+ struct net_device *dev;
+ struct adm5120_if_priv *priv;
+
+ dev = adm5120_if_alloc();
+ if (!dev) {
+ err = -ENOMEM;
+ goto err;
+ }
+
+ adm5120_devs[i] = dev;
+ priv = netdev_priv(dev);
+
+ priv->vlan_no = i;
+ priv->port_mask = adm5120_eth_vlans[i];
+
+ memcpy(dev->dev_addr, adm5120_eth_macs[i], 6);
+ adm5120_write_mac(dev);
+
+ err = register_netdev(dev);
+ if (err) {
+ SW_INFO("%s register failed, error=%d\n",
+ dev->name, err);
+ goto err;
+ }
+ }
+
+ /* setup vlan/port mapping after devs are filled up */
+ adm5120_set_vlan(adm5120_eth_vlans);
+
+ /* enable CPU port */
+ t = sw_read_reg(SWITCH_REG_CPUP_CONF);
+ t &= ~CPUP_CONF_DCPUP;
+ sw_write_reg(SWITCH_REG_CPUP_CONF, t);
+
+ return 0;
+
+err:
+ adm5120_switch_cleanup();
+
+ SW_ERR("init failed\n");
+ return err;
+}
+
+static int adm5120_switch_remove(struct platform_device *dev)
+{
+ adm5120_switch_cleanup();
+ return 0;
+}
+
+static struct platform_driver adm5120_switch_driver = {
+ .probe = adm5120_switch_probe,
+ .remove = adm5120_switch_remove,
+ .driver = {
+ .name = DRV_NAME,
+ },
+};
+
+/* -------------------------------------------------------------------------- */
+
+static int __init adm5120_switch_mod_init(void)
+{
+ int err;
+
+ pr_info(DRV_DESC " version " DRV_VERSION "\n");
+ err = platform_driver_register(&adm5120_switch_driver);
+
+ return err;
+}
+
+static void __exit adm5120_switch_mod_exit(void)
+{
+ platform_driver_unregister(&adm5120_switch_driver);
+}
+
+module_init(adm5120_switch_mod_init);
+module_exit(adm5120_switch_mod_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
+MODULE_DESCRIPTION(DRV_DESC);
+MODULE_VERSION(DRV_VERSION);
--- /dev/null
+/*
+ * Defines for ADM5120 built in ethernet switch driver
+ *
+ * Copyright Jeroen Vreeken (pe1rxq@amsat.org), 2005
+ *
+ * Values come from ADM5120 datasheet and original ADMtek 2.4 driver,
+ * Copyright ADMtek Inc.
+ */
+
+#ifndef _INCLUDE_ADM5120SW_H_
+#define _INCLUDE_ADM5120SW_H_
+
+#define SIOCSMATRIX SIOCDEVPRIVATE
+#define SIOCGMATRIX SIOCDEVPRIVATE+1
+#define SIOCGADMINFO SIOCDEVPRIVATE+2
+
+struct adm5120_sw_info {
+ u16 magic;
+ u16 ports;
+ u16 vlan;
+};
+
+#endif /* _INCLUDE_ADM5120SW_H_ */
--- /dev/null
+/*
+ * ADM5120 HCD (Host Controller Driver) for USB
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This file was derived from: drivers/usb/host/ohci-dbg.c
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+/*-------------------------------------------------------------------------*/
+
+static inline char *ed_typestring(int ed_type)
+{
+ switch (ed_type) {
+ case PIPE_CONTROL:
+ return "ctrl";
+ case PIPE_BULK:
+ return "bulk";
+ case PIPE_INTERRUPT:
+ return "intr";
+ case PIPE_ISOCHRONOUS:
+ return "isoc";
+ }
+ return "(bad ed_type)";
+}
+
+static inline char *ed_statestring(int state)
+{
+ switch (state) {
+ case ED_IDLE:
+ return "IDLE";
+ case ED_UNLINK:
+ return "UNLINK";
+ case ED_OPER:
+ return "OPER";
+ }
+ return "?STATE";
+}
+
+static inline char *pipestring(int pipe)
+{
+ return ed_typestring(usb_pipetype(pipe));
+}
+
+static inline char *td_pidstring(u32 info)
+{
+ switch (info & TD_DP) {
+ case TD_DP_SETUP:
+ return "SETUP";
+ case TD_DP_IN:
+ return "IN";
+ case TD_DP_OUT:
+ return "OUT";
+ }
+ return "?PID";
+}
+
+static inline char *td_togglestring(u32 info)
+{
+ switch (info & TD_T) {
+ case TD_T_DATA0:
+ return "DATA0";
+ case TD_T_DATA1:
+ return "DATA1";
+ case TD_T_CARRY:
+ return "CARRY";
+ }
+ return "?TOGGLE";
+}
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef DEBUG
+
+/* debug| print the main components of an URB
+ * small: 0) header + data packets 1) just header
+ */
+static void __attribute__((unused))
+urb_print(struct admhcd *ahcd, struct urb *urb, char *str, int small, int status)
+{
+ unsigned int pipe = urb->pipe;
+
+ if (!urb->dev || !urb->dev->bus) {
+ admhc_dbg(ahcd, "%s URB: no dev", str);
+ return;
+ }
+
+#ifndef ADMHC_VERBOSE_DEBUG
+ if (status != 0)
+#endif
+ admhc_dbg(ahcd, "URB-%s %p dev=%d ep=%d%s-%s flags=%x len=%d/%d "
+ "stat=%d\n",
+ str,
+ urb,
+ usb_pipedevice (pipe),
+ usb_pipeendpoint (pipe),
+ usb_pipeout(pipe)? "out" : "in",
+ pipestring(pipe),
+ urb->transfer_flags,
+ urb->actual_length,
+ urb->transfer_buffer_length,
+ status);
+
+#ifdef ADMHC_VERBOSE_DEBUG
+ if (!small) {
+ int i, len;
+
+ if (usb_pipecontrol(pipe)) {
+ admhc_dbg(ahcd, "setup(8):");
+ for (i = 0; i < 8 ; i++)
+ printk (" %02x", ((__u8 *) urb->setup_packet) [i]);
+ printk ("\n");
+ }
+ if (urb->transfer_buffer_length > 0 && urb->transfer_buffer) {
+ admhc_dbg(ahcd, "data(%d/%d):",
+ urb->actual_length,
+ urb->transfer_buffer_length);
+ len = usb_pipeout(pipe)?
+ urb->transfer_buffer_length: urb->actual_length;
+ for (i = 0; i < 16 && i < len; i++)
+ printk(" %02x", ((__u8 *)urb->transfer_buffer)[i]);
+ printk("%s stat:%d\n", i < len? "...": "", status);
+ }
+ }
+#endif /* ADMHC_VERBOSE_DEBUG */
+}
+
+#define admhc_dbg_sw(ahcd, next, size, format, arg...) \
+ do { \
+ if (next) { \
+ unsigned s_len; \
+ s_len = scnprintf(*next, *size, format, ## arg ); \
+ *size -= s_len; *next += s_len; \
+ } else \
+ admhc_dbg(ahcd,format, ## arg ); \
+ } while (0);
+
+
+static void admhc_dump_intr_mask(struct admhcd *ahcd, char *label, u32 mask,
+ char **next, unsigned *size)
+{
+ admhc_dbg_sw(ahcd, next, size, "%s 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s\n",
+ label,
+ mask,
+ (mask & ADMHC_INTR_INTA) ? " INTA" : "",
+ (mask & ADMHC_INTR_FATI) ? " FATI" : "",
+ (mask & ADMHC_INTR_SWI) ? " SWI" : "",
+ (mask & ADMHC_INTR_TDC) ? " TDC" : "",
+ (mask & ADMHC_INTR_FNO) ? " FNO" : "",
+ (mask & ADMHC_INTR_SO) ? " SO" : "",
+ (mask & ADMHC_INTR_INSM) ? " INSM" : "",
+ (mask & ADMHC_INTR_BABI) ? " BABI" : "",
+ (mask & ADMHC_INTR_7) ? " !7!" : "",
+ (mask & ADMHC_INTR_6) ? " !6!" : "",
+ (mask & ADMHC_INTR_RESI) ? " RESI" : "",
+ (mask & ADMHC_INTR_SOFI) ? " SOFI" : ""
+ );
+}
+
+static void maybe_print_eds(struct admhcd *ahcd, char *label, u32 value,
+ char **next, unsigned *size)
+{
+ if (value)
+ admhc_dbg_sw(ahcd, next, size, "%s %08x\n", label, value);
+}
+
+static char *buss2string (int state)
+{
+ switch (state) {
+ case ADMHC_BUSS_RESET:
+ return "reset";
+ case ADMHC_BUSS_RESUME:
+ return "resume";
+ case ADMHC_BUSS_OPER:
+ return "operational";
+ case ADMHC_BUSS_SUSPEND:
+ return "suspend";
+ }
+ return "?state";
+}
+
+static void
+admhc_dump_status(struct admhcd *ahcd, char **next, unsigned *size)
+{
+ struct admhcd_regs __iomem *regs = ahcd->regs;
+ u32 temp;
+
+ temp = admhc_readl(ahcd, ®s->gencontrol);
+ admhc_dbg_sw(ahcd, next, size,
+ "gencontrol 0x%08x%s%s%s%s\n",
+ temp,
+ (temp & ADMHC_CTRL_UHFE) ? " UHFE" : "",
+ (temp & ADMHC_CTRL_SIR) ? " SIR" : "",
+ (temp & ADMHC_CTRL_DMAA) ? " DMAA" : "",
+ (temp & ADMHC_CTRL_SR) ? " SR" : ""
+ );
+
+ temp = admhc_readl(ahcd, ®s->host_control);
+ admhc_dbg_sw(ahcd, next, size,
+ "host_control 0x%08x BUSS=%s%s\n",
+ temp,
+ buss2string(temp & ADMHC_HC_BUSS),
+ (temp & ADMHC_HC_DMAE) ? " DMAE" : ""
+ );
+
+ admhc_dump_intr_mask(ahcd, "int_status",
+ admhc_readl(ahcd, ®s->int_status),
+ next, size);
+ admhc_dump_intr_mask(ahcd, "int_enable",
+ admhc_readl(ahcd, ®s->int_enable),
+ next, size);
+
+ maybe_print_eds(ahcd, "hosthead",
+ admhc_readl(ahcd, ®s->hosthead), next, size);
+}
+
+#define dbg_port_sw(hc,num,value,next,size) \
+ admhc_dbg_sw(hc, next, size, \
+ "portstatus [%d] " \
+ "0x%08x%s%s%s%s%s%s%s%s%s%s%s%s\n", \
+ num, temp, \
+ (temp & ADMHC_PS_PRSC) ? " PRSC" : "", \
+ (temp & ADMHC_PS_OCIC) ? " OCIC" : "", \
+ (temp & ADMHC_PS_PSSC) ? " PSSC" : "", \
+ (temp & ADMHC_PS_PESC) ? " PESC" : "", \
+ (temp & ADMHC_PS_CSC) ? " CSC" : "", \
+ \
+ (temp & ADMHC_PS_LSDA) ? " LSDA" : "", \
+ (temp & ADMHC_PS_PPS) ? " PPS" : "", \
+ (temp & ADMHC_PS_PRS) ? " PRS" : "", \
+ (temp & ADMHC_PS_POCI) ? " POCI" : "", \
+ (temp & ADMHC_PS_PSS) ? " PSS" : "", \
+ \
+ (temp & ADMHC_PS_PES) ? " PES" : "", \
+ (temp & ADMHC_PS_CCS) ? " CCS" : "" \
+ );
+
+
+static void
+admhc_dump_roothub(
+ struct admhcd *ahcd,
+ int verbose,
+ char **next,
+ unsigned *size)
+{
+ u32 temp, i;
+
+ temp = admhc_read_rhdesc(ahcd);
+ if (temp == ~(u32)0)
+ return;
+
+ if (verbose) {
+ admhc_dbg_sw(ahcd, next, size,
+ "rhdesc %08x%s%s%s%s%s%s PPCM=%02x%s%s%s%s NUMP=%d(%d)\n",
+ temp,
+ (temp & ADMHC_RH_CRWE) ? " CRWE" : "",
+ (temp & ADMHC_RH_OCIC) ? " OCIC" : "",
+ (temp & ADMHC_RH_LPSC) ? " LPSC" : "",
+ (temp & ADMHC_RH_LPSC) ? " DRWE" : "",
+ (temp & ADMHC_RH_LPSC) ? " OCI" : "",
+ (temp & ADMHC_RH_LPSC) ? " LPS" : "",
+ ((temp & ADMHC_RH_PPCM) >> 16),
+ (temp & ADMHC_RH_NOCP) ? " NOCP" : "",
+ (temp & ADMHC_RH_OCPM) ? " OCPM" : "",
+ (temp & ADMHC_RH_NPS) ? " NPS" : "",
+ (temp & ADMHC_RH_PSM) ? " PSM" : "",
+ (temp & ADMHC_RH_NUMP), ahcd->num_ports
+ );
+ }
+
+ for (i = 0; i < ahcd->num_ports; i++) {
+ temp = admhc_read_portstatus(ahcd, i);
+ dbg_port_sw(ahcd, i, temp, next, size);
+ }
+}
+
+static void admhc_dump(struct admhcd *ahcd, int verbose)
+{
+ admhc_dbg(ahcd, "ADMHC ahcd state\n");
+
+ /* dumps some of the state we know about */
+ admhc_dump_status(ahcd, NULL, NULL);
+ admhc_dbg(ahcd,"current frame #%04x\n",
+ admhc_frame_no(ahcd));
+
+ admhc_dump_roothub(ahcd, verbose, NULL, NULL);
+}
+
+static const char data0[] = "DATA0";
+static const char data1[] = "DATA1";
+
+static void admhc_dump_td(const struct admhcd *ahcd, const char *label,
+ const struct td *td)
+{
+ u32 tmp;
+
+ admhc_dbg(ahcd, "%s td %p; urb %p index %d; hwNextTD %08x\n",
+ label, td,
+ td->urb, td->index,
+ hc32_to_cpup(ahcd, &td->hwNextTD));
+
+ tmp = hc32_to_cpup(ahcd, &td->hwINFO);
+ admhc_dbg(ahcd, " status %08x%s CC=%x EC=%d %s %s ISI=%x FN=%x\n",
+ tmp,
+ (tmp & TD_OWN) ? " OWN" : "",
+ TD_CC_GET(tmp),
+ TD_EC_GET(tmp),
+ td_togglestring(tmp),
+ td_pidstring(tmp),
+ TD_ISI_GET(tmp),
+ TD_FN_GET(tmp));
+
+ tmp = hc32_to_cpup(ahcd, &td->hwCBL);
+ admhc_dbg(ahcd, " dbp %08x; cbl %08x; LEN=%d%s\n",
+ hc32_to_cpup(ahcd, &td->hwDBP),
+ tmp,
+ TD_BL_GET(tmp),
+ (tmp & TD_IE) ? " IE" : "");
+}
+
+/* caller MUST own hcd spinlock if verbose is set! */
+static void __attribute__((unused))
+admhc_dump_ed(const struct admhcd *ahcd, const char *label,
+ const struct ed *ed, int verbose)
+{
+ u32 tmp = hc32_to_cpu(ahcd, ed->hwINFO);
+
+ admhc_dbg(ahcd, "%s ed %p %s type %s; next ed %08x\n",
+ label,
+ ed, ed_statestring(ed->state), ed_typestring(ed->type),
+ hc32_to_cpup(ahcd, &ed->hwNextED));
+
+ admhc_dbg(ahcd, " info %08x MAX=%d%s%s%s%s EP=%d DEV=%d\n", tmp,
+ ED_MPS_GET(tmp),
+ (tmp & ED_ISO) ? " ISO" : "",
+ (tmp & ED_SKIP) ? " SKIP" : "",
+ (tmp & ED_SPEED_FULL) ? " FULL" : " LOW",
+ (tmp & ED_INT) ? " INT" : "",
+ ED_EN_GET(tmp),
+ ED_FA_GET(tmp));
+
+ tmp = hc32_to_cpup(ahcd, &ed->hwHeadP);
+ admhc_dbg(ahcd, " tds: head %08x tail %08x %s%s%s\n",
+ tmp & TD_MASK,
+ hc32_to_cpup (ahcd, &ed->hwTailP),
+ (tmp & ED_C) ? data1 : data0,
+ (tmp & ED_H) ? " HALT" : "",
+ verbose ? " td list follows" : " (not listing)");
+
+ if (verbose) {
+ struct list_head *tmp;
+
+ /* use ed->td_list because HC concurrently modifies
+ * hwNextTD as it accumulates ed_donelist.
+ */
+ list_for_each(tmp, &ed->td_list) {
+ struct td *td;
+ td = list_entry(tmp, struct td, td_list);
+ admhc_dump_td (ahcd, " ->", td);
+ }
+ }
+}
+
+#else /* ifdef DEBUG */
+
+static inline void urb_print(struct admhcd *ahcd, struct urb * urb, char * str,
+ int small) {}
+static inline void admhc_dump_ed(const struct admhcd *ahcd, const char *label,
+ const struct ed *ed, int verbose) {}
+static inline void admhc_dump_td(const struct admhcd *ahcd, const char *label,
+ const struct td *td) {}
+static inline void admhc_dump(struct admhcd *ahcd, int verbose) {}
+
+#undef ADMHC_VERBOSE_DEBUG
+
+#endif /* DEBUG */
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef STUB_DEBUG_FILES
+
+static inline void create_debug_files(struct admhcd *bus) { }
+static inline void remove_debug_files(struct admhcd *bus) { }
+
+#else
+
+static int debug_async_open(struct inode *, struct file *);
+static int debug_periodic_open(struct inode *, struct file *);
+static int debug_registers_open(struct inode *, struct file *);
+static ssize_t debug_output(struct file*, char __user*, size_t, loff_t*);
+static int debug_close(struct inode *, struct file *);
+
+static const struct file_operations debug_async_fops = {
+ .owner = THIS_MODULE,
+ .open = debug_async_open,
+ .read = debug_output,
+ .release = debug_close,
+};
+static const struct file_operations debug_periodic_fops = {
+ .owner = THIS_MODULE,
+ .open = debug_periodic_open,
+ .read = debug_output,
+ .release = debug_close,
+};
+static const struct file_operations debug_registers_fops = {
+ .owner = THIS_MODULE,
+ .open = debug_registers_open,
+ .read = debug_output,
+ .release = debug_close,
+};
+
+static struct dentry *admhc_debug_root;
+
+struct debug_buffer {
+ ssize_t (*fill_func)(struct debug_buffer *); /* fill method */
+ struct device *dev;
+ struct mutex mutex; /* protect filling of buffer */
+ size_t count; /* number of characters filled into buffer */
+ char *page;
+};
+
+static ssize_t
+show_list(struct admhcd *ahcd, char *buf, size_t count, struct ed *ed)
+{
+ unsigned temp;
+ unsigned size = count;
+
+ if (!ed)
+ return 0;
+
+ /* dump a snapshot of the bulk or control schedule */
+ while (ed) {
+ u32 info = hc32_to_cpu(ahcd, ed->hwINFO);
+ u32 headp = hc32_to_cpu(ahcd, ed->hwHeadP);
+ u32 tailp = hc32_to_cpu(ahcd, ed->hwTailP);
+ struct list_head *entry;
+ struct td *td;
+
+ temp = scnprintf(buf, size,
+ "ed/%p %s %s %cs dev%d ep%d %s%smax %d %08x%s%s %s"
+ " h:%08x t:%08x",
+ ed,
+ ed_statestring(ed->state),
+ ed_typestring (ed->type),
+ (info & ED_SPEED_FULL) ? 'f' : 'l',
+ info & ED_FA_MASK,
+ (info >> ED_EN_SHIFT) & ED_EN_MASK,
+ (info & ED_INT) ? "INT " : "",
+ (info & ED_ISO) ? "ISO " : "",
+ (info >> ED_MPS_SHIFT) & ED_MPS_MASK ,
+ info,
+ (info & ED_SKIP) ? " S" : "",
+ (headp & ED_H) ? " H" : "",
+ (headp & ED_C) ? data1 : data0,
+ headp & ED_MASK,tailp);
+ size -= temp;
+ buf += temp;
+
+ list_for_each(entry, &ed->td_list) {
+ u32 dbp, cbl;
+
+ td = list_entry(entry, struct td, td_list);
+ info = hc32_to_cpup (ahcd, &td->hwINFO);
+ dbp = hc32_to_cpup (ahcd, &td->hwDBP);
+ cbl = hc32_to_cpup (ahcd, &td->hwCBL);
+
+ temp = scnprintf(buf, size,
+ "\n\ttd/%p %s %d %s%scc=%x urb %p (%08x,%08x)",
+ td,
+ td_pidstring(info),
+ TD_BL_GET(cbl),
+ (info & TD_OWN) ? "" : "DONE ",
+ (cbl & TD_IE) ? "IE " : "",
+ TD_CC_GET (info), td->urb, info, cbl);
+ size -= temp;
+ buf += temp;
+ }
+
+ temp = scnprintf(buf, size, "\n");
+ size -= temp;
+ buf += temp;
+
+ ed = ed->ed_next;
+ }
+
+ return count - size;
+}
+
+static ssize_t fill_async_buffer(struct debug_buffer *buf)
+{
+ struct usb_bus *bus;
+ struct usb_hcd *hcd;
+ struct admhcd *ahcd;
+ size_t temp;
+ unsigned long flags;
+
+ bus = dev_get_drvdata(buf->dev);
+ hcd = bus_to_hcd(bus);
+ ahcd = hcd_to_admhcd(hcd);
+
+ spin_lock_irqsave(&ahcd->lock, flags);
+ temp = show_list(ahcd, buf->page, PAGE_SIZE, ahcd->ed_head);
+ spin_unlock_irqrestore(&ahcd->lock, flags);
+
+ return temp;
+}
+
+
+#define DBG_SCHED_LIMIT 64
+
+static ssize_t fill_periodic_buffer(struct debug_buffer *buf)
+{
+ struct usb_bus *bus;
+ struct usb_hcd *hcd;
+ struct admhcd *ahcd;
+ struct ed **seen, *ed;
+ unsigned long flags;
+ unsigned temp, size, seen_count;
+ char *next;
+ unsigned i;
+
+ if (!(seen = kmalloc(DBG_SCHED_LIMIT * sizeof *seen, GFP_ATOMIC)))
+ return 0;
+ seen_count = 0;
+
+ bus = dev_get_drvdata(buf->dev);
+ hcd = bus_to_hcd(bus);
+ ahcd = hcd_to_admhcd(hcd);
+ next = buf->page;
+ size = PAGE_SIZE;
+
+ temp = scnprintf(next, size, "size = %d\n", NUM_INTS);
+ size -= temp;
+ next += temp;
+
+ /* dump a snapshot of the periodic schedule (and load) */
+ spin_lock_irqsave(&ahcd->lock, flags);
+ for (i = 0; i < NUM_INTS; i++) {
+ if (!(ed = ahcd->periodic [i]))
+ continue;
+
+ temp = scnprintf(next, size, "%2d [%3d]:", i, ahcd->load [i]);
+ size -= temp;
+ next += temp;
+
+ do {
+ temp = scnprintf(next, size, " ed%d/%p",
+ ed->interval, ed);
+ size -= temp;
+ next += temp;
+ for (temp = 0; temp < seen_count; temp++) {
+ if (seen [temp] == ed)
+ break;
+ }
+
+ /* show more info the first time around */
+ if (temp == seen_count) {
+ u32 info = hc32_to_cpu (ahcd, ed->hwINFO);
+ struct list_head *entry;
+ unsigned qlen = 0;
+
+ /* qlen measured here in TDs, not urbs */
+ list_for_each (entry, &ed->td_list)
+ qlen++;
+ temp = scnprintf(next, size,
+ " (%cs dev%d ep%d%s qlen %u"
+ " max %d %08x%s%s)",
+ (info & ED_SPEED_FULL) ? 'f' : 'l',
+ ED_FA_GET(info),
+ ED_EN_GET(info),
+ (info & ED_ISO) ? "iso" : "int",
+ qlen,
+ ED_MPS_GET(info),
+ info,
+ (info & ED_SKIP) ? " K" : "",
+ (ed->hwHeadP &
+ cpu_to_hc32(ahcd, ED_H)) ?
+ " H" : "");
+ size -= temp;
+ next += temp;
+
+ if (seen_count < DBG_SCHED_LIMIT)
+ seen [seen_count++] = ed;
+
+ ed = ed->ed_next;
+
+ } else {
+ /* we've seen it and what's after */
+ temp = 0;
+ ed = NULL;
+ }
+
+ } while (ed);
+
+ temp = scnprintf(next, size, "\n");
+ size -= temp;
+ next += temp;
+ }
+ spin_unlock_irqrestore(&ahcd->lock, flags);
+ kfree (seen);
+
+ return PAGE_SIZE - size;
+}
+
+
+#undef DBG_SCHED_LIMIT
+
+static ssize_t fill_registers_buffer(struct debug_buffer *buf)
+{
+ struct usb_bus *bus;
+ struct usb_hcd *hcd;
+ struct admhcd *ahcd;
+ struct admhcd_regs __iomem *regs;
+ unsigned long flags;
+ unsigned temp, size;
+ char *next;
+ u32 rdata;
+
+ bus = dev_get_drvdata(buf->dev);
+ hcd = bus_to_hcd(bus);
+ ahcd = hcd_to_admhcd(hcd);
+ regs = ahcd->regs;
+ next = buf->page;
+ size = PAGE_SIZE;
+
+ spin_lock_irqsave(&ahcd->lock, flags);
+
+ /* dump driver info, then registers in spec order */
+
+ admhc_dbg_sw(ahcd, &next, &size,
+ "bus %s, device %s\n"
+ "%s\n"
+ "%s version " DRIVER_VERSION "\n",
+ hcd->self.controller->bus->name,
+ hcd->self.controller->bus_id,
+ hcd->product_desc,
+ hcd_name);
+
+ if (bus->controller->power.power_state.event) {
+ size -= scnprintf(next, size,
+ "SUSPENDED (no register access)\n");
+ goto done;
+ }
+
+ admhc_dump_status(ahcd, &next, &size);
+
+ /* other registers mostly affect frame timings */
+ rdata = admhc_readl(ahcd, ®s->fminterval);
+ temp = scnprintf(next, size,
+ "fmintvl 0x%08x %sFSLDP=0x%04x FI=0x%04x\n",
+ rdata, (rdata & ADMHC_SFI_FIT) ? "FIT " : "",
+ (rdata >> ADMHC_SFI_FSLDP_SHIFT) & ADMHC_SFI_FSLDP_MASK,
+ rdata & ADMHC_SFI_FI_MASK);
+ size -= temp;
+ next += temp;
+
+ rdata = admhc_readl(ahcd, ®s->fmnumber);
+ temp = scnprintf(next, size, "fmnumber 0x%08x %sFR=0x%04x FN=%04x\n",
+ rdata, (rdata & ADMHC_SFN_FRT) ? "FRT " : "",
+ (rdata >> ADMHC_SFN_FR_SHIFT) & ADMHC_SFN_FR_MASK,
+ rdata & ADMHC_SFN_FN_MASK);
+ size -= temp;
+ next += temp;
+
+ /* TODO: use predefined bitmask */
+ rdata = admhc_readl(ahcd, ®s->lsthresh);
+ temp = scnprintf(next, size, "lsthresh 0x%04x\n",
+ rdata & 0x3fff);
+ size -= temp;
+ next += temp;
+
+ temp = scnprintf(next, size, "hub poll timer: %s\n",
+ admhcd_to_hcd(ahcd)->poll_rh ? "ON" : "OFF");
+ size -= temp;
+ next += temp;
+
+ /* roothub */
+ admhc_dump_roothub(ahcd, 1, &next, &size);
+
+done:
+ spin_unlock_irqrestore(&ahcd->lock, flags);
+ return PAGE_SIZE - size;
+}
+
+
+static struct debug_buffer *alloc_buffer(struct device *dev,
+ ssize_t (*fill_func)(struct debug_buffer *))
+{
+ struct debug_buffer *buf;
+
+ buf = kzalloc(sizeof(struct debug_buffer), GFP_KERNEL);
+
+ if (buf) {
+ buf->dev = dev;
+ buf->fill_func = fill_func;
+ mutex_init(&buf->mutex);
+ }
+
+ return buf;
+}
+
+static int fill_buffer(struct debug_buffer *buf)
+{
+ int ret = 0;
+
+ if (!buf->page)
+ buf->page = (char *)get_zeroed_page(GFP_KERNEL);
+
+ if (!buf->page) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ ret = buf->fill_func(buf);
+
+ if (ret >= 0) {
+ buf->count = ret;
+ ret = 0;
+ }
+
+out:
+ return ret;
+}
+
+static ssize_t debug_output(struct file *file, char __user *user_buf,
+ size_t len, loff_t *offset)
+{
+ struct debug_buffer *buf = file->private_data;
+ int ret = 0;
+
+ mutex_lock(&buf->mutex);
+ if (buf->count == 0) {
+ ret = fill_buffer(buf);
+ if (ret != 0) {
+ mutex_unlock(&buf->mutex);
+ goto out;
+ }
+ }
+ mutex_unlock(&buf->mutex);
+
+ ret = simple_read_from_buffer(user_buf, len, offset,
+ buf->page, buf->count);
+
+out:
+ return ret;
+}
+
+static int debug_close(struct inode *inode, struct file *file)
+{
+ struct debug_buffer *buf = file->private_data;
+
+ if (buf) {
+ if (buf->page)
+ free_page((unsigned long)buf->page);
+ kfree(buf);
+ }
+
+ return 0;
+}
+
+static int debug_async_open(struct inode *inode, struct file *file)
+{
+ file->private_data = alloc_buffer(inode->i_private, fill_async_buffer);
+
+ return file->private_data ? 0 : -ENOMEM;
+}
+
+static int debug_periodic_open(struct inode *inode, struct file *file)
+{
+ file->private_data = alloc_buffer(inode->i_private,
+ fill_periodic_buffer);
+
+ return file->private_data ? 0 : -ENOMEM;
+}
+
+static int debug_registers_open(struct inode *inode, struct file *file)
+{
+ file->private_data = alloc_buffer(inode->i_private,
+ fill_registers_buffer);
+
+ return file->private_data ? 0 : -ENOMEM;
+}
+
+static inline void create_debug_files(struct admhcd *ahcd)
+{
+ struct usb_bus *bus = &admhcd_to_hcd(ahcd)->self;
+ struct device *dev = bus->dev;
+
+ ahcd->debug_dir = debugfs_create_dir(bus->bus_name, admhc_debug_root);
+ if (!ahcd->debug_dir)
+ goto dir_error;
+
+ ahcd->debug_async = debugfs_create_file("async", S_IRUGO,
+ ahcd->debug_dir, dev,
+ &debug_async_fops);
+ if (!ahcd->debug_async)
+ goto async_error;
+
+ ahcd->debug_periodic = debugfs_create_file("periodic", S_IRUGO,
+ ahcd->debug_dir, dev,
+ &debug_periodic_fops);
+ if (!ahcd->debug_periodic)
+ goto periodic_error;
+
+ ahcd->debug_registers = debugfs_create_file("registers", S_IRUGO,
+ ahcd->debug_dir, dev,
+ &debug_registers_fops);
+ if (!ahcd->debug_registers)
+ goto registers_error;
+
+ admhc_dbg(ahcd, "created debug files\n");
+ return;
+
+registers_error:
+ debugfs_remove(ahcd->debug_periodic);
+periodic_error:
+ debugfs_remove(ahcd->debug_async);
+async_error:
+ debugfs_remove(ahcd->debug_dir);
+dir_error:
+ ahcd->debug_periodic = NULL;
+ ahcd->debug_async = NULL;
+ ahcd->debug_dir = NULL;
+}
+
+static inline void remove_debug_files(struct admhcd *ahcd)
+{
+ debugfs_remove(ahcd->debug_registers);
+ debugfs_remove(ahcd->debug_periodic);
+ debugfs_remove(ahcd->debug_async);
+ debugfs_remove(ahcd->debug_dir);
+}
+
+#endif
+
+/*-------------------------------------------------------------------------*/
--- /dev/null
+/*
+ * ADM5120 HCD (Host Controller Driver) for USB
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This file was derived from: drivers/usb/host/ohci-au1xxx.c
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
+ * (C) Copyright 2002 Hewlett-Packard Company
+ *
+ * Written by Christopher Hoover <ch@hpl.hp.com>
+ * Based on fragments of previous driver by Rusell King et al.
+ *
+ * Modified for LH7A404 from ahcd-sa1111.c
+ * by Durgesh Pattamatta <pattamattad@sharpsec.com>
+ * Modified for AMD Alchemy Au1xxx
+ * by Matt Porter <mporter@kernel.crashing.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/signal.h>
+
+#include <asm/bootinfo.h>
+#include <asm/mach-adm5120/adm5120_defs.h>
+
+#ifdef DEBUG
+#define HCD_DBG(f, a...) printk(KERN_DEBUG "%s: " f, hcd_name, ## a)
+#else
+#define HCD_DBG(f, a...) do {} while (0)
+#endif
+#define HCD_ERR(f, a...) printk(KERN_ERR "%s: " f, hcd_name, ## a)
+#define HCD_INFO(f, a...) printk(KERN_INFO "%s: " f, hcd_name, ## a)
+
+/*-------------------------------------------------------------------------*/
+
+static int admhc_adm5120_probe(const struct hc_driver *driver,
+ struct platform_device *dev)
+{
+ int retval;
+ struct usb_hcd *hcd;
+ int irq;
+ struct resource *regs;
+
+ /* sanity checks */
+ regs = platform_get_resource(dev, IORESOURCE_MEM, 0);
+ if (!regs) {
+ HCD_DBG("no IOMEM resource found\n");
+ return -ENODEV;
+ }
+
+ irq = platform_get_irq(dev, 0);
+ if (irq < 0) {
+ HCD_DBG("no IRQ resource found\n");
+ return -ENODEV;
+ }
+
+ hcd = usb_create_hcd(driver, &dev->dev, "ADM5120");
+ if (!hcd)
+ return -ENOMEM;
+
+ hcd->rsrc_start = regs->start;
+ hcd->rsrc_len = regs->end - regs->start + 1;
+
+ if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
+ HCD_DBG("request_mem_region failed\n");
+ retval = -EBUSY;
+ goto err_dev;
+ }
+
+ hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
+ if (!hcd->regs) {
+ HCD_DBG("ioremap failed\n");
+ retval = -ENOMEM;
+ goto err_mem;
+ }
+
+ admhc_hcd_init(hcd_to_admhcd(hcd));
+
+ retval = usb_add_hcd(hcd, irq, IRQF_DISABLED);
+ if (retval)
+ goto err_io;
+
+ return 0;
+
+err_io:
+ iounmap(hcd->regs);
+err_mem:
+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+err_dev:
+ usb_put_hcd(hcd);
+ return retval;
+}
+
+
+/* may be called without controller electrically present */
+/* may be called with controller, bus, and devices active */
+
+static void admhc_adm5120_remove(struct usb_hcd *hcd,
+ struct platform_device *dev)
+{
+ usb_remove_hcd(hcd);
+ iounmap(hcd->regs);
+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+ usb_put_hcd(hcd);
+}
+
+/*-------------------------------------------------------------------------*/
+
+static int __devinit
+admhc_adm5120_start(struct usb_hcd *hcd)
+{
+ struct admhcd *ahcd = hcd_to_admhcd (hcd);
+ int ret;
+
+ ret = admhc_init(ahcd);
+ if (ret < 0) {
+ HCD_ERR("unable to init %s\n", hcd->self.bus_name);
+ goto err;
+ }
+
+ ret = admhc_run(ahcd);
+ if (ret < 0) {
+ HCD_ERR("unable to run %s\n", hcd->self.bus_name);
+ goto err_stop;
+ }
+
+ return 0;
+
+err_stop:
+ admhc_stop(hcd);
+err:
+ return ret;
+}
+
+/*-------------------------------------------------------------------------*/
+
+static const struct hc_driver adm5120_hc_driver = {
+ .description = hcd_name,
+ .product_desc = "ADM5120 built-in USB 1.1 Host Controller",
+ .hcd_priv_size = sizeof(struct admhcd),
+
+ /*
+ * generic hardware linkage
+ */
+ .irq = admhc_irq,
+ .flags = HCD_USB11 | HCD_MEMORY,
+
+ /*
+ * basic lifecycle operations
+ */
+ .start = admhc_adm5120_start,
+ .stop = admhc_stop,
+ .shutdown = admhc_shutdown,
+
+ /*
+ * managing i/o requests and associated device resources
+ */
+ .urb_enqueue = admhc_urb_enqueue,
+ .urb_dequeue = admhc_urb_dequeue,
+ .endpoint_disable = admhc_endpoint_disable,
+
+ /*
+ * scheduling support
+ */
+ .get_frame_number = admhc_get_frame_number,
+
+ /*
+ * root hub support
+ */
+ .hub_status_data = admhc_hub_status_data,
+ .hub_control = admhc_hub_control,
+ .hub_irq_enable = admhc_hub_irq_enable,
+#ifdef CONFIG_PM
+ .bus_suspend = admhc_bus_suspend,
+ .bus_resume = admhc_bus_resume,
+#endif
+ .start_port_reset = admhc_start_port_reset,
+};
+
+/*-------------------------------------------------------------------------*/
+
+static int usb_hcd_adm5120_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ ret = admhc_adm5120_probe(&adm5120_hc_driver, pdev);
+
+ return ret;
+}
+
+static int usb_hcd_adm5120_remove(struct platform_device *pdev)
+{
+ struct usb_hcd *hcd = platform_get_drvdata(pdev);
+
+ admhc_adm5120_remove(hcd, pdev);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+/* TODO */
+static int usb_hcd_adm5120_suspend(struct platform_device *dev)
+{
+ struct usb_hcd *hcd = platform_get_drvdata(dev);
+
+ return 0;
+}
+
+static int usb_hcd_adm5120_resume(struct platform_device *dev)
+{
+ struct usb_hcd *hcd = platform_get_drvdata(dev);
+
+ return 0;
+}
+#else
+#define usb_hcd_adm5120_suspend NULL
+#define usb_hcd_adm5120_resume NULL
+#endif /* CONFIG_PM */
+
+static struct platform_driver usb_hcd_adm5120_driver = {
+ .probe = usb_hcd_adm5120_probe,
+ .remove = usb_hcd_adm5120_remove,
+ .shutdown = usb_hcd_platform_shutdown,
+ .suspend = usb_hcd_adm5120_suspend,
+ .resume = usb_hcd_adm5120_resume,
+ .driver = {
+ .name = "adm5120-hcd",
+ .owner = THIS_MODULE,
+ },
+};
+
--- /dev/null
+/*
+ * ADM5120 HCD (Host Controller Driver) for USB
+ *
+ * Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This file was derived from: drivers/usb/host/ohci-hcd.c
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
+ *
+ * [ Initialisation is based on Linus' ]
+ * [ uhci code and gregs ahcd fragments ]
+ * [ (C) Copyright 1999 Linus Torvalds ]
+ * [ (C) Copyright 1999 Gregory P. Smith]
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/ioport.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/timer.h>
+#include <linux/list.h>
+#include <linux/usb.h>
+#include <linux/usb/otg.h>
+#include <linux/dma-mapping.h>
+#include <linux/dmapool.h>
+#include <linux/reboot.h>
+#include <linux/debugfs.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/unaligned.h>
+#include <asm/byteorder.h>
+
+#include "../core/hcd.h"
+#include "../core/hub.h"
+
+#define DRIVER_VERSION "0.25.0"
+#define DRIVER_AUTHOR "Gabor Juhos <juhosg@openwrt.org>"
+#define DRIVER_DESC "ADMtek USB 1.1 Host Controller Driver"
+
+/*-------------------------------------------------------------------------*/
+
+#undef ADMHC_VERBOSE_DEBUG /* not always helpful */
+
+/* For initializing controller (mask in an HCFS mode too) */
+#define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
+
+#define ADMHC_INTR_INIT \
+ ( ADMHC_INTR_MIE | ADMHC_INTR_INSM | ADMHC_INTR_FATI \
+ | ADMHC_INTR_RESI | ADMHC_INTR_TDC | ADMHC_INTR_BABI )
+
+/*-------------------------------------------------------------------------*/
+
+static const char hcd_name [] = "admhc-hcd";
+
+#define STATECHANGE_DELAY msecs_to_jiffies(300)
+
+#include "adm5120.h"
+
+static void admhc_dump(struct admhcd *ahcd, int verbose);
+static int admhc_init(struct admhcd *ahcd);
+static void admhc_stop(struct usb_hcd *hcd);
+
+#include "adm5120-dbg.c"
+#include "adm5120-mem.c"
+#include "adm5120-pm.c"
+#include "adm5120-hub.c"
+#include "adm5120-q.c"
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * queue up an urb for anything except the root hub
+ */
+static int admhc_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
+ gfp_t mem_flags)
+{
+ struct admhcd *ahcd = hcd_to_admhcd(hcd);
+ struct ed *ed;
+ struct urb_priv *urb_priv;
+ unsigned int pipe = urb->pipe;
+ int td_cnt = 0;
+ unsigned long flags;
+ int ret = 0;
+
+#ifdef ADMHC_VERBOSE_DEBUG
+ spin_lock_irqsave(&ahcd->lock, flags);
+ urb_print(ahcd, urb, "ENQEUE", usb_pipein(pipe), -EINPROGRESS);
+ spin_unlock_irqrestore(&ahcd->lock, flags);
+#endif
+
+ /* every endpoint has an ed, locate and maybe (re)initialize it */
+ ed = ed_get(ahcd, urb->ep, urb->dev, pipe, urb->interval);
+ if (!ed)
+ return -ENOMEM;
+
+ /* for the private part of the URB we need the number of TDs */
+ switch (ed->type) {
+ case PIPE_CONTROL:
+ if (urb->transfer_buffer_length > TD_DATALEN_MAX)
+ /* td_submit_urb() doesn't yet handle these */
+ return -EMSGSIZE;
+
+ /* 1 TD for setup, 1 for ACK, plus ... */
+ td_cnt = 2;
+ /* FALLTHROUGH */
+ case PIPE_BULK:
+ /* one TD for every 4096 Bytes (can be upto 8K) */
+ td_cnt += urb->transfer_buffer_length / TD_DATALEN_MAX;
+ /* ... and for any remaining bytes ... */
+ if ((urb->transfer_buffer_length % TD_DATALEN_MAX) != 0)
+ td_cnt++;
+ /* ... and maybe a zero length packet to wrap it up */
+ if (td_cnt == 0)
+ td_cnt++;
+ else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
+ && (urb->transfer_buffer_length
+ % usb_maxpacket(urb->dev, pipe,
+ usb_pipeout (pipe))) == 0)
+ td_cnt++;
+ break;
+ case PIPE_INTERRUPT:
+ /*
+ * for Interrupt IN/OUT transactions, each ED contains
+ * only 1 TD.
+ * TODO: check transfer_buffer_length?
+ */
+ td_cnt = 1;
+ break;
+ case PIPE_ISOCHRONOUS:
+ /* number of packets from URB */
+ td_cnt = urb->number_of_packets;
+ break;
+ }
+
+ urb_priv = urb_priv_alloc(ahcd, td_cnt, mem_flags);
+ if (!urb_priv)
+ return -ENOMEM;
+
+ urb_priv->ed = ed;
+
+ spin_lock_irqsave(&ahcd->lock, flags);
+ /* don't submit to a dead HC */
+ if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
+ ret = -ENODEV;
+ goto fail;
+ }
+ if (!HC_IS_RUNNING(hcd->state)) {
+ ret = -ENODEV;
+ goto fail;
+ }
+
+ ret = usb_hcd_link_urb_to_ep(hcd, urb);
+ if (ret)
+ goto fail;
+
+ /* schedule the ed if needed */
+ if (ed->state == ED_IDLE) {
+ ret = ed_schedule(ahcd, ed);
+ if (ret < 0) {
+ usb_hcd_unlink_urb_from_ep(hcd, urb);
+ goto fail;
+ }
+ if (ed->type == PIPE_ISOCHRONOUS) {
+ u16 frame = admhc_frame_no(ahcd);
+
+ /* delay a few frames before the first TD */
+ frame += max_t (u16, 8, ed->interval);
+ frame &= ~(ed->interval - 1);
+ frame |= ed->branch;
+ urb->start_frame = frame;
+
+ /* yes, only URB_ISO_ASAP is supported, and
+ * urb->start_frame is never used as input.
+ */
+ }
+ } else if (ed->type == PIPE_ISOCHRONOUS)
+ urb->start_frame = ed->last_iso + ed->interval;
+
+ /* fill the TDs and link them to the ed; and
+ * enable that part of the schedule, if needed
+ * and update count of queued periodic urbs
+ */
+ urb->hcpriv = urb_priv;
+ td_submit_urb(ahcd, urb);
+
+#ifdef ADMHC_VERBOSE_DEBUG
+ admhc_dump_ed(ahcd, "admhc_urb_enqueue", urb_priv->ed, 1);
+#endif
+
+fail:
+ if (ret)
+ urb_priv_free(ahcd, urb_priv);
+
+ spin_unlock_irqrestore(&ahcd->lock, flags);
+ return ret;
+}
+
+/*
+ * decouple the URB from the HC queues (TDs, urb_priv);
+ * reporting is always done
+ * asynchronously, and we might be dealing with an urb that's
+ * partially transferred, or an ED with other urbs being unlinked.
+ */
+static int admhc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
+ int status)
+{
+ struct admhcd *ahcd = hcd_to_admhcd(hcd);
+ unsigned long flags;
+ int ret;
+
+ spin_lock_irqsave(&ahcd->lock, flags);
+
+#ifdef ADMHC_VERBOSE_DEBUG
+ urb_print(ahcd, urb, "DEQUEUE", 1, status);
+#endif
+ ret = usb_hcd_check_unlink_urb(hcd, urb, status);
+ if (ret) {
+ /* Do nothing */
+ ;
+ } else if (HC_IS_RUNNING(hcd->state)) {
+ struct urb_priv *urb_priv;
+
+ /* Unless an IRQ completed the unlink while it was being
+ * handed to us, flag it for unlink and giveback, and force
+ * some upcoming INTR_SF to call finish_unlinks()
+ */
+ urb_priv = urb->hcpriv;
+ if (urb_priv) {
+ if (urb_priv->ed->state == ED_OPER)
+ start_ed_unlink(ahcd, urb_priv->ed);
+ }
+ } else {
+ /*
+ * with HC dead, we won't respect hc queue pointers
+ * any more ... just clean up every urb's memory.
+ */
+ if (urb->hcpriv)
+ finish_urb(ahcd, urb, status);
+ }
+ spin_unlock_irqrestore(&ahcd->lock, flags);
+
+ return ret;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* frees config/altsetting state for endpoints,
+ * including ED memory, dummy TD, and bulk/intr data toggle
+ */
+
+static void admhc_endpoint_disable(struct usb_hcd *hcd,
+ struct usb_host_endpoint *ep)
+{
+ struct admhcd *ahcd = hcd_to_admhcd(hcd);
+ unsigned long flags;
+ struct ed *ed = ep->hcpriv;
+ unsigned limit = 1000;
+
+ /* ASSERT: any requests/urbs are being unlinked */
+ /* ASSERT: nobody can be submitting urbs for this any more */
+
+ if (!ed)
+ return;
+
+#ifdef ADMHC_VERBOSE_DEBUG
+ spin_lock_irqsave(&ahcd->lock, flags);
+ admhc_dump_ed(ahcd, "EP-DISABLE", ed, 1);
+ spin_unlock_irqrestore(&ahcd->lock, flags);
+#endif
+
+rescan:
+ spin_lock_irqsave(&ahcd->lock, flags);
+
+ if (!HC_IS_RUNNING(hcd->state)) {
+sanitize:
+ ed->state = ED_IDLE;
+ finish_unlinks(ahcd, 0);
+ }
+
+ switch (ed->state) {
+ case ED_UNLINK: /* wait for hw to finish? */
+ /* major IRQ delivery trouble loses INTR_SOFI too... */
+ if (limit-- == 0) {
+ admhc_warn(ahcd, "IRQ INTR_SOFI lossage\n");
+ goto sanitize;
+ }
+ spin_unlock_irqrestore(&ahcd->lock, flags);
+ schedule_timeout_uninterruptible(1);
+ goto rescan;
+ case ED_IDLE: /* fully unlinked */
+ if (list_empty(&ed->td_list)) {
+ td_free (ahcd, ed->dummy);
+ ed_free (ahcd, ed);
+ break;
+ }
+ /* else FALL THROUGH */
+ default:
+ /* caller was supposed to have unlinked any requests;
+ * that's not our job. can't recover; must leak ed.
+ */
+ admhc_err(ahcd, "leak ed %p (#%02x) state %d%s\n",
+ ed, ep->desc.bEndpointAddress, ed->state,
+ list_empty(&ed->td_list) ? "" : " (has tds)");
+ td_free(ahcd, ed->dummy);
+ break;
+ }
+
+ ep->hcpriv = NULL;
+
+ spin_unlock_irqrestore(&ahcd->lock, flags);
+ return;
+}
+
+static int admhc_get_frame_number(struct usb_hcd *hcd)
+{
+ struct admhcd *ahcd = hcd_to_admhcd(hcd);
+
+ return admhc_frame_no(ahcd);
+}
+
+static void admhc_usb_reset(struct admhcd *ahcd)
+{
+#if 0
+ ahcd->hc_control = admhc_readl(ahcd, &ahcd->regs->control);
+ ahcd->hc_control &= OHCI_CTRL_RWC;
+ admhc_writel(ahcd, ahcd->hc_control, &ahcd->regs->control);
+#else
+ /* FIXME */
+ ahcd->host_control = ADMHC_BUSS_RESET;
+ admhc_writel(ahcd, ahcd->host_control ,&ahcd->regs->host_control);
+#endif
+}
+
+/* admhc_shutdown forcibly disables IRQs and DMA, helping kexec and
+ * other cases where the next software may expect clean state from the
+ * "firmware". this is bus-neutral, unlike shutdown() methods.
+ */
+static void
+admhc_shutdown(struct usb_hcd *hcd)
+{
+ struct admhcd *ahcd;
+
+ ahcd = hcd_to_admhcd(hcd);
+ admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
+ admhc_dma_disable(ahcd);
+ admhc_usb_reset(ahcd);
+ /* flush the writes */
+ admhc_writel_flush(ahcd);
+}
+
+/*-------------------------------------------------------------------------*
+ * HC functions
+ *-------------------------------------------------------------------------*/
+
+static void admhc_eds_cleanup(struct admhcd *ahcd)
+{
+ if (ahcd->ed_tails[PIPE_INTERRUPT]) {
+ ed_free(ahcd, ahcd->ed_tails[PIPE_INTERRUPT]);
+ ahcd->ed_tails[PIPE_INTERRUPT] = NULL;
+ }
+
+ if (ahcd->ed_tails[PIPE_ISOCHRONOUS]) {
+ ed_free(ahcd, ahcd->ed_tails[PIPE_ISOCHRONOUS]);
+ ahcd->ed_tails[PIPE_ISOCHRONOUS] = NULL;
+ }
+
+ if (ahcd->ed_tails[PIPE_CONTROL]) {
+ ed_free(ahcd, ahcd->ed_tails[PIPE_CONTROL]);
+ ahcd->ed_tails[PIPE_CONTROL] = NULL;
+ }
+
+ if (ahcd->ed_tails[PIPE_BULK]) {
+ ed_free(ahcd, ahcd->ed_tails[PIPE_BULK]);
+ ahcd->ed_tails[PIPE_BULK] = NULL;
+ }
+
+ ahcd->ed_head = NULL;
+}
+
+#define ED_DUMMY_INFO (ED_SPEED_FULL | ED_SKIP)
+
+static int admhc_eds_init(struct admhcd *ahcd)
+{
+ struct ed *ed;
+
+ ed = ed_create(ahcd, PIPE_INTERRUPT, ED_DUMMY_INFO);
+ if (!ed)
+ goto err;
+
+ ahcd->ed_tails[PIPE_INTERRUPT] = ed;
+
+ ed = ed_create(ahcd, PIPE_ISOCHRONOUS, ED_DUMMY_INFO);
+ if (!ed)
+ goto err;
+
+ ahcd->ed_tails[PIPE_ISOCHRONOUS] = ed;
+ ed->ed_prev = ahcd->ed_tails[PIPE_INTERRUPT];
+ ahcd->ed_tails[PIPE_INTERRUPT]->ed_next = ed;
+ ahcd->ed_tails[PIPE_INTERRUPT]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
+
+ ed = ed_create(ahcd, PIPE_CONTROL, ED_DUMMY_INFO);
+ if (!ed)
+ goto err;
+
+ ahcd->ed_tails[PIPE_CONTROL] = ed;
+ ed->ed_prev = ahcd->ed_tails[PIPE_ISOCHRONOUS];
+ ahcd->ed_tails[PIPE_ISOCHRONOUS]->ed_next = ed;
+ ahcd->ed_tails[PIPE_ISOCHRONOUS]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
+
+ ed = ed_create(ahcd, PIPE_BULK, ED_DUMMY_INFO);
+ if (!ed)
+ goto err;
+
+ ahcd->ed_tails[PIPE_BULK] = ed;
+ ed->ed_prev = ahcd->ed_tails[PIPE_CONTROL];
+ ahcd->ed_tails[PIPE_CONTROL]->ed_next = ed;
+ ahcd->ed_tails[PIPE_CONTROL]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
+
+ ahcd->ed_head = ahcd->ed_tails[PIPE_INTERRUPT];
+
+#ifdef ADMHC_VERBOSE_DEBUG
+ admhc_dump_ed(ahcd, "ed intr", ahcd->ed_tails[PIPE_INTERRUPT], 1);
+ admhc_dump_ed(ahcd, "ed isoc", ahcd->ed_tails[PIPE_ISOCHRONOUS], 1);
+ admhc_dump_ed(ahcd, "ed ctrl", ahcd->ed_tails[PIPE_CONTROL], 1);
+ admhc_dump_ed(ahcd, "ed bulk", ahcd->ed_tails[PIPE_BULK], 1);
+#endif
+
+ return 0;
+
+err:
+ admhc_eds_cleanup(ahcd);
+ return -ENOMEM;
+}
+
+/* init memory, and kick BIOS/SMM off */
+
+static int admhc_init(struct admhcd *ahcd)
+{
+ struct usb_hcd *hcd = admhcd_to_hcd(ahcd);
+ int ret;
+
+ admhc_disable(ahcd);
+ ahcd->regs = hcd->regs;
+
+ /* Disable HC interrupts */
+ admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
+
+ /* Read the number of ports unless overridden */
+ if (ahcd->num_ports == 0)
+ ahcd->num_ports = admhc_read_rhdesc(ahcd) & ADMHC_RH_NUMP;
+
+ ret = admhc_mem_init(ahcd);
+ if (ret)
+ goto err;
+
+ /* init dummy endpoints */
+ ret = admhc_eds_init(ahcd);
+ if (ret)
+ goto err;
+
+ create_debug_files(ahcd);
+
+ return 0;
+
+err:
+ admhc_stop(hcd);
+ return ret;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* Start an OHCI controller, set the BUS operational
+ * resets USB and controller
+ * enable interrupts
+ */
+static int admhc_run(struct admhcd *ahcd)
+{
+ u32 temp;
+ int first = ahcd->fminterval == 0;
+ struct usb_hcd *hcd = admhcd_to_hcd(ahcd);
+
+ admhc_disable(ahcd);
+
+ /* boot firmware should have set this up (5.1.1.3.1) */
+ if (first) {
+ temp = admhc_readl(ahcd, &ahcd->regs->fminterval);
+ ahcd->fminterval = temp & ADMHC_SFI_FI_MASK;
+ if (ahcd->fminterval != FI)
+ admhc_dbg(ahcd, "fminterval delta %d\n",
+ ahcd->fminterval - FI);
+ ahcd->fminterval |=
+ (FSLDP(ahcd->fminterval) << ADMHC_SFI_FSLDP_SHIFT);
+ /* also: power/overcurrent flags in rhdesc */
+ }
+
+#if 0 /* TODO: not applicable */
+ /* Reset USB nearly "by the book". RemoteWakeupConnected was
+ * saved if boot firmware (BIOS/SMM/...) told us it's connected,
+ * or if bus glue did the same (e.g. for PCI add-in cards with
+ * PCI PM support).
+ */
+ if ((ahcd->hc_control & OHCI_CTRL_RWC) != 0
+ && !device_may_wakeup(hcd->self.controller))
+ device_init_wakeup(hcd->self.controller, 1);
+#endif
+
+ switch (ahcd->host_control & ADMHC_HC_BUSS) {
+ case ADMHC_BUSS_OPER:
+ temp = 0;
+ break;
+ case ADMHC_BUSS_SUSPEND:
+ /* FALLTHROUGH ? */
+ case ADMHC_BUSS_RESUME:
+ ahcd->host_control = ADMHC_BUSS_RESUME;
+ temp = 10 /* msec wait */;
+ break;
+ /* case ADMHC_BUSS_RESET: */
+ default:
+ ahcd->host_control = ADMHC_BUSS_RESET;
+ temp = 50 /* msec wait */;
+ break;
+ }
+ admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control);
+
+ /* flush the writes */
+ admhc_writel_flush(ahcd);
+
+ msleep(temp);
+ temp = admhc_read_rhdesc(ahcd);
+ if (!(temp & ADMHC_RH_NPS)) {
+ /* power down each port */
+ for (temp = 0; temp < ahcd->num_ports; temp++)
+ admhc_write_portstatus(ahcd, temp, ADMHC_PS_CPP);
+ }
+ /* flush those writes */
+ admhc_writel_flush(ahcd);
+
+ /* 2msec timelimit here means no irqs/preempt */
+ spin_lock_irq(&ahcd->lock);
+
+ admhc_writel(ahcd, ADMHC_CTRL_SR, &ahcd->regs->gencontrol);
+ temp = 30; /* ... allow extra time */
+ while ((admhc_readl(ahcd, &ahcd->regs->gencontrol) & ADMHC_CTRL_SR) != 0) {
+ if (--temp == 0) {
+ spin_unlock_irq(&ahcd->lock);
+ admhc_err(ahcd, "USB HC reset timed out!\n");
+ return -1;
+ }
+ udelay(1);
+ }
+
+ /* enable HOST mode, before access any host specific register */
+ admhc_writel(ahcd, ADMHC_CTRL_UHFE, &ahcd->regs->gencontrol);
+
+ /* Tell the controller where the descriptor list is */
+ admhc_writel(ahcd, (u32)ahcd->ed_head->dma, &ahcd->regs->hosthead);
+
+ periodic_reinit(ahcd);
+
+ /* use rhsc irqs after khubd is fully initialized */
+ hcd->poll_rh = 1;
+ hcd->uses_new_polling = 1;
+
+#if 0
+ /* wake on ConnectStatusChange, matching external hubs */
+ admhc_writel(ahcd, RH_HS_DRWE, &ahcd->regs->roothub.status);
+#else
+ /* FIXME roothub_write_status (ahcd, ADMHC_RH_DRWE); */
+#endif
+
+ /* Choose the interrupts we care about now, others later on demand */
+ admhc_intr_ack(ahcd, ~0);
+ admhc_intr_enable(ahcd, ADMHC_INTR_INIT);
+
+ admhc_writel(ahcd, ADMHC_RH_NPS | ADMHC_RH_LPSC, &ahcd->regs->rhdesc);
+
+ /* flush those writes */
+ admhc_writel_flush(ahcd);
+
+ /* start controller operations */
+ ahcd->host_control = ADMHC_BUSS_OPER;
+ admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control);
+
+ temp = 20;
+ while ((admhc_readl(ahcd, &ahcd->regs->host_control)
+ & ADMHC_HC_BUSS) != ADMHC_BUSS_OPER) {
+ if (--temp == 0) {
+ spin_unlock_irq(&ahcd->lock);
+ admhc_err(ahcd, "unable to setup operational mode!\n");
+ return -1;
+ }
+ mdelay(1);
+ }
+
+ hcd->state = HC_STATE_RUNNING;
+
+ ahcd->next_statechange = jiffies + STATECHANGE_DELAY;
+
+#if 0
+ /* FIXME: enabling DMA is always failed here for an unknown reason */
+ admhc_dma_enable(ahcd);
+
+ temp = 200;
+ while ((admhc_readl(ahcd, &ahcd->regs->host_control)
+ & ADMHC_HC_DMAE) != ADMHC_HC_DMAE) {
+ if (--temp == 0) {
+ spin_unlock_irq(&ahcd->lock);
+ admhc_err(ahcd, "unable to enable DMA!\n");
+ admhc_dump(ahcd, 1);
+ return -1;
+ }
+ mdelay(1);
+ }
+
+#endif
+
+ spin_unlock_irq(&ahcd->lock);
+
+ mdelay(ADMHC_POTPGT);
+
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* an interrupt happens */
+
+static irqreturn_t admhc_irq(struct usb_hcd *hcd)
+{
+ struct admhcd *ahcd = hcd_to_admhcd(hcd);
+ struct admhcd_regs __iomem *regs = ahcd->regs;
+ u32 ints;
+
+ ints = admhc_readl(ahcd, ®s->int_status);
+ if ((ints & ADMHC_INTR_INTA) == 0) {
+ /* no unmasked interrupt status is set */
+ return IRQ_NONE;
+ }
+
+ ints &= admhc_readl(ahcd, ®s->int_enable);
+
+ if (ints & ADMHC_INTR_FATI) {
+ /* e.g. due to PCI Master/Target Abort */
+ admhc_disable(ahcd);
+ admhc_err(ahcd, "Fatal Error, controller disabled\n");
+ admhc_dump(ahcd, 1);
+ admhc_usb_reset(ahcd);
+ }
+
+ if (ints & ADMHC_INTR_BABI) {
+ admhc_intr_disable(ahcd, ADMHC_INTR_BABI);
+ admhc_intr_ack(ahcd, ADMHC_INTR_BABI);
+ admhc_err(ahcd, "Babble Detected\n");
+ }
+
+ if (ints & ADMHC_INTR_INSM) {
+ admhc_vdbg(ahcd, "Root Hub Status Change\n");
+ ahcd->next_statechange = jiffies + STATECHANGE_DELAY;
+ admhc_intr_ack(ahcd, ADMHC_INTR_RESI | ADMHC_INTR_INSM);
+
+ /* NOTE: Vendors didn't always make the same implementation
+ * choices for RHSC. Many followed the spec; RHSC triggers
+ * on an edge, like setting and maybe clearing a port status
+ * change bit. With others it's level-triggered, active
+ * until khubd clears all the port status change bits. We'll
+ * always disable it here and rely on polling until khubd
+ * re-enables it.
+ */
+ admhc_intr_disable(ahcd, ADMHC_INTR_INSM);
+ usb_hcd_poll_rh_status(hcd);
+ } else if (ints & ADMHC_INTR_RESI) {
+ /* For connect and disconnect events, we expect the controller
+ * to turn on RHSC along with RD. But for remote wakeup events
+ * this might not happen.
+ */
+ admhc_vdbg(ahcd, "Resume Detect\n");
+ admhc_intr_ack(ahcd, ADMHC_INTR_RESI);
+ hcd->poll_rh = 1;
+ if (ahcd->autostop) {
+ spin_lock(&ahcd->lock);
+ admhc_rh_resume(ahcd);
+ spin_unlock(&ahcd->lock);
+ } else
+ usb_hcd_resume_root_hub(hcd);
+ }
+
+ if (ints & ADMHC_INTR_TDC) {
+ admhc_vdbg(ahcd, "Transfer Descriptor Complete\n");
+ admhc_intr_ack(ahcd, ADMHC_INTR_TDC);
+ if (HC_IS_RUNNING(hcd->state))
+ admhc_intr_disable(ahcd, ADMHC_INTR_TDC);
+ spin_lock(&ahcd->lock);
+ admhc_td_complete(ahcd);
+ spin_unlock(&ahcd->lock);
+ if (HC_IS_RUNNING(hcd->state))
+ admhc_intr_enable(ahcd, ADMHC_INTR_TDC);
+ }
+
+ if (ints & ADMHC_INTR_SO) {
+ /* could track INTR_SO to reduce available PCI/... bandwidth */
+ admhc_vdbg(ahcd, "Schedule Overrun\n");
+ }
+
+#if 1
+ spin_lock(&ahcd->lock);
+ if (ahcd->ed_rm_list)
+ finish_unlinks(ahcd, admhc_frame_no(ahcd));
+
+ if ((ints & ADMHC_INTR_SOFI) != 0 && !ahcd->ed_rm_list
+ &nbs
projects / openwrt / svn-archive / archive.git / commitdiff