--- /dev/null
+CONFIG_AG71XX=y
+CONFIG_AG71XX_AR8216_SUPPORT=y
+# CONFIG_AG71XX_DEBUG is not set
+# CONFIG_AG71XX_DEBUG_FS is not set
+CONFIG_AR8216_PHY=y
+# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ATH79=y
+CONFIG_ATH79_DEV_AP9X_PCI=y
+CONFIG_ATH79_DEV_DSA=y
+CONFIG_ATH79_DEV_ETH=y
+CONFIG_ATH79_DEV_GPIO_BUTTONS=y
+CONFIG_ATH79_DEV_LEDS_GPIO=y
+CONFIG_ATH79_DEV_M25P80=y
+CONFIG_ATH79_DEV_SPI=y
+CONFIG_ATH79_DEV_USB=y
+CONFIG_ATH79_DEV_WMAC=y
+CONFIG_ATH79_MACH_ALFA_AP96=y
+CONFIG_ATH79_MACH_ALFA_NX=y
+CONFIG_ATH79_MACH_ALL0258N=y
+CONFIG_ATH79_MACH_AP121=y
+CONFIG_ATH79_MACH_AP81=y
+CONFIG_ATH79_MACH_AP83=y
+CONFIG_ATH79_MACH_AP96=y
+CONFIG_ATH79_MACH_AW_NR580=y
+CONFIG_ATH79_MACH_DB120=y
+CONFIG_ATH79_MACH_DIR_600_A1=y
+CONFIG_ATH79_MACH_DIR_615_C1=y
+CONFIG_ATH79_MACH_DIR_825_B1=y
+CONFIG_ATH79_MACH_EAP7660D=y
+CONFIG_ATH79_MACH_HORNET_UB=y
+CONFIG_ATH79_MACH_JA76PF=y
+CONFIG_ATH79_MACH_JWAP003=y
+CONFIG_ATH79_MACH_MZK_W04NU=y
+CONFIG_ATH79_MACH_MZK_W300NH=y
+CONFIG_ATH79_MACH_NBG460N=y
+CONFIG_ATH79_MACH_OM2P=y
+CONFIG_ATH79_MACH_PB42=y
+CONFIG_ATH79_MACH_PB44=y
+CONFIG_ATH79_MACH_PB92=y
+CONFIG_ATH79_MACH_RB4XX=y
+CONFIG_ATH79_MACH_RB750=y
+CONFIG_ATH79_MACH_RW2458N=y
+CONFIG_ATH79_MACH_TEW_632BRP=y
+CONFIG_ATH79_MACH_TL_MR3020=y
+CONFIG_ATH79_MACH_TL_MR3X20=y
+CONFIG_ATH79_MACH_TL_WA901ND=y
+CONFIG_ATH79_MACH_TL_WA901ND_V2=y
+CONFIG_ATH79_MACH_TL_WR1043ND=y
+CONFIG_ATH79_MACH_TL_WR2543N=y
+CONFIG_ATH79_MACH_TL_WR703N=y
+CONFIG_ATH79_MACH_TL_WR741ND=y
+CONFIG_ATH79_MACH_TL_WR741ND_V4=y
+CONFIG_ATH79_MACH_TL_WR841N_V1=y
+CONFIG_ATH79_MACH_TL_WR941ND=y
+CONFIG_ATH79_MACH_UBNT=y
+CONFIG_ATH79_MACH_UBNT_XM=y
+CONFIG_ATH79_MACH_WHR_HP_G300N=y
+CONFIG_ATH79_MACH_WNDR3700=y
+CONFIG_ATH79_MACH_WNR2000=y
+CONFIG_ATH79_MACH_WP543=y
+CONFIG_ATH79_MACH_WRT160NL=y
+CONFIG_ATH79_MACH_WRT400N=y
+CONFIG_ATH79_MACH_WZR_HP_AG300H=y
+CONFIG_ATH79_MACH_WZR_HP_G300NH=y
+CONFIG_ATH79_MACH_WZR_HP_G300NH2=y
+CONFIG_ATH79_MACH_WZR_HP_G450H=y
+CONFIG_ATH79_MACH_ZCN_1523H=y
+CONFIG_ATH79_NVRAM=y
+CONFIG_ATH79_PCI_ATH9K_FIXUP=y
+# CONFIG_ATH79_WDT is not set
+CONFIG_BCMA_POSSIBLE=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_CEVT_R4K=y
+CONFIG_CEVT_R4K_LIB=y
+CONFIG_CMDLINE="rootfstype=squashfs,yaffs,jffs2 noinitrd"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CSRC_R4K=y
+CONFIG_CSRC_R4K_LIB=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_NXP_74HC153=y
+CONFIG_GPIO_PCF857X=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IRQ_WORK=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HW_HAS_PCI=y
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_GPIO=y
+# CONFIG_I2C_PXA_PCI is not set
+CONFIG_IMAGE_CMDLINE_HACK=y
+CONFIG_INITRAMFS_ROOT_GID=0
+CONFIG_INITRAMFS_ROOT_UID=0
+CONFIG_INITRAMFS_SOURCE="../../root"
+CONFIG_IP17XX_PHY=y
+CONFIG_IRQ_CPU=y
+CONFIG_IRQ_FORCED_THREADING=y
+# CONFIG_LANTIQ is not set
+# CONFIG_LEDS_GPIO is not set
+# CONFIG_LEDS_RB750 is not set
+# CONFIG_LEDS_WNDR3700_USB is not set
+# CONFIG_M25PXX_USE_FAST_READ is not set
+CONFIG_MARVELL_PHY=y
+CONFIG_MICREL_PHY=y
+# CONFIG_MINIX_FS_NATIVE_ENDIAN is not set
+CONFIG_MIPS=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+CONFIG_MIPS_MACHINE=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MLX4_CORE is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_MYLOADER_PARTS=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-2
+CONFIG_MTD_REDBOOT_PARTS=y
+CONFIG_MTD_TPLINK_PARTS=y
+CONFIG_MTD_WRT160NL_PARTS=y
+CONFIG_MYLOADER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_MV88E6060=y
+CONFIG_NET_DSA_MV88E6063=y
+CONFIG_NET_DSA_TAG_TRAILER=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_PCI=y
+CONFIG_PCI_AR724X=y
+CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PHYLIB=y
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_QUOTACTL is not set
+CONFIG_RTL8306_PHY=y
+CONFIG_RTL8366RB_PHY=y
+CONFIG_RTL8366S_PHY=y
+CONFIG_RTL8366_SMI=y
+CONFIG_RTL8367_PHY=y
+# CONFIG_SCSI_DMA is not set
+CONFIG_SERIAL_8250_NR_UARTS=1
+CONFIG_SERIAL_8250_RUNTIME_UARTS=1
+CONFIG_SERIAL_AR933X=y
+CONFIG_SERIAL_AR933X_CONSOLE=y
+CONFIG_SERIAL_AR933X_NR_UARTS=2
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+CONFIG_SOC_AR71XX=y
+CONFIG_SOC_AR724X=y
+CONFIG_SOC_AR913X=y
+CONFIG_SOC_AR933X=y
+CONFIG_SOC_AR934X=y
+CONFIG_SPI=y
+CONFIG_SPI_AP83=y
+CONFIG_SPI_ATH79=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_GPIO=y
+CONFIG_SPI_MASTER=y
+# CONFIG_SPI_RB4XX is not set
+# CONFIG_SPI_RB4XX_CPLD is not set
+# CONFIG_SPI_VSC7385 is not set
+CONFIG_SWCONFIG=y
+CONFIG_SWCONFIG_LEDS=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_USB_ARCH_HAS_XHCI=y
+CONFIG_USB_SUPPORT=y
+CONFIG_XZ_DEC=y
+CONFIG_ZONE_DMA_FLAG=0
--- /dev/null
+/*
+ * Atheros AP9X reference board PCI initialization
+ *
+ * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/pci.h>
+#include <linux/ath9k_platform.h>
+#include <linux/delay.h>
+
+#include <asm/mach-ath79/ath79.h>
+#include <asm/mach-ath79/pci.h>
+
+#include "dev-ap9x-pci.h"
+#include "pci-ath9k-fixup.h"
+#include "pci.h"
+
+static struct ath9k_platform_data ap9x_wmac0_data = {
+ .led_pin = -1,
+};
+static struct ath9k_platform_data ap9x_wmac1_data = {
+ .led_pin = -1,
+};
+static char ap9x_wmac0_mac[6];
+static char ap9x_wmac1_mac[6];
+
+__init void ap9x_pci_setup_wmac_led_pin(unsigned wmac, int pin)
+{
+ switch (wmac) {
+ case 0:
+ ap9x_wmac0_data.led_pin = pin;
+ break;
+ case 1:
+ ap9x_wmac1_data.led_pin = pin;
+ break;
+ }
+}
+
+__init void ap9x_pci_setup_wmac_gpio(unsigned wmac, u32 mask, u32 val)
+{
+ switch (wmac) {
+ case 0:
+ ap9x_wmac0_data.gpio_mask = mask;
+ ap9x_wmac0_data.gpio_val = val;
+ break;
+ case 1:
+ ap9x_wmac1_data.gpio_mask = mask;
+ ap9x_wmac1_data.gpio_val = val;
+ break;
+ }
+}
+
+__init void ap9x_pci_setup_wmac_leds(unsigned wmac, struct gpio_led *leds,
+ int num_leds)
+{
+ switch (wmac) {
+ case 0:
+ ap9x_wmac0_data.leds = leds;
+ ap9x_wmac0_data.num_leds = num_leds;
+ break;
+ case 1:
+ ap9x_wmac1_data.leds = leds;
+ ap9x_wmac1_data.num_leds = num_leds;
+ break;
+ }
+}
+
+static int ap91_pci_plat_dev_init(struct pci_dev *dev)
+{
+ switch (PCI_SLOT(dev->devfn)) {
+ case 0:
+ dev->dev.platform_data = &ap9x_wmac0_data;
+ break;
+ }
+
+ return 0;
+}
+
+__init void ap91_pci_init(u8 *cal_data, u8 *mac_addr)
+{
+ if (cal_data)
+ memcpy(ap9x_wmac0_data.eeprom_data, cal_data,
+ sizeof(ap9x_wmac0_data.eeprom_data));
+
+ if (mac_addr) {
+ memcpy(ap9x_wmac0_mac, mac_addr, sizeof(ap9x_wmac0_mac));
+ ap9x_wmac0_data.macaddr = ap9x_wmac0_mac;
+ }
+
+ ath79_pci_set_plat_dev_init(ap91_pci_plat_dev_init);
+ ath79_register_pci();
+
+ pci_enable_ath9k_fixup(0, ap9x_wmac0_data.eeprom_data);
+}
+
+static int ap94_pci_plat_dev_init(struct pci_dev *dev)
+{
+ switch (PCI_SLOT(dev->devfn)) {
+ case 17:
+ dev->dev.platform_data = &ap9x_wmac0_data;
+ break;
+
+ case 18:
+ dev->dev.platform_data = &ap9x_wmac1_data;
+ break;
+ }
+
+ return 0;
+}
+
+__init void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0,
+ u8 *cal_data1, u8 *mac_addr1)
+{
+ if (cal_data0)
+ memcpy(ap9x_wmac0_data.eeprom_data, cal_data0,
+ sizeof(ap9x_wmac0_data.eeprom_data));
+
+ if (cal_data1)
+ memcpy(ap9x_wmac1_data.eeprom_data, cal_data1,
+ sizeof(ap9x_wmac1_data.eeprom_data));
+
+ if (mac_addr0) {
+ memcpy(ap9x_wmac0_mac, mac_addr0, sizeof(ap9x_wmac0_mac));
+ ap9x_wmac0_data.macaddr = ap9x_wmac0_mac;
+ }
+
+ if (mac_addr1) {
+ memcpy(ap9x_wmac1_mac, mac_addr1, sizeof(ap9x_wmac1_mac));
+ ap9x_wmac1_data.macaddr = ap9x_wmac1_mac;
+ }
+
+ ath79_pci_set_plat_dev_init(ap94_pci_plat_dev_init);
+ ath79_register_pci();
+
+ pci_enable_ath9k_fixup(17, ap9x_wmac0_data.eeprom_data);
+ pci_enable_ath9k_fixup(18, ap9x_wmac1_data.eeprom_data);
+}
--- /dev/null
+/*
+ * Atheros AP9X reference board PCI initialization
+ *
+ * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef _ATH79_DEV_AP9X_PCI_H
+#define _ATH79_DEV_AP9X_PCI_H
+
+struct gpio_led;
+
+#if defined(CONFIG_ATH79_DEV_AP9X_PCI)
+void ap9x_pci_setup_wmac_led_pin(unsigned wmac, int pin);
+void ap9x_pci_setup_wmac_gpio(unsigned wmac, u32 mask, u32 val);
+void ap9x_pci_setup_wmac_leds(unsigned wmac, struct gpio_led *leds,
+ int num_leds);
+
+void ap91_pci_init(u8 *cal_data, u8 *mac_addr);
+void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0,
+ u8 *cal_data1, u8 *mac_addr1);
+
+#else
+static inline void ap9x_pci_setup_wmac_led_pin(unsigned wmac, int pin) {}
+static inline void ap9x_pci_setup_wmac_gpio(unsigned wmac,
+ u32 mask, u32 val) {}
+static inline void ap9x_pci_setup_wmac_leds(unsigned wmac,
+ struct gpio_led *leds,
+ int num_leds) {}
+
+static inline void ap91_pci_init(u8 *cal_data, u8 *mac_addr) {}
+static inline void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0,
+ u8 *cal_data1, u8 *mac_addr1) {}
+#endif
+
+#endif /* _ATH79_DEV_AP9X_PCI_H */
+
--- /dev/null
+/*
+ * Atheros AR71xx DSA switch device support
+ *
+ * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-dsa.h"
+
+static struct platform_device ar71xx_dsa_switch_device = {
+ .name = "dsa",
+ .id = 0,
+};
+
+void __init ath79_register_dsa(struct device *netdev,
+ struct device *miidev,
+ struct dsa_platform_data *d)
+{
+ int i;
+
+ d->netdev = netdev;
+ for (i = 0; i < d->nr_chips; i++)
+ d->chip[i].mii_bus = miidev;
+
+ ar71xx_dsa_switch_device.dev.platform_data = d;
+ platform_device_register(&ar71xx_dsa_switch_device);
+}
--- /dev/null
+/*
+ * Atheros AR71xx DSA switch device support
+ *
+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef _ATH79_DEV_DSA_H
+#define _ATH79_DEV_DSA_H
+
+#include <net/dsa.h>
+
+void ath79_register_dsa(struct device *netdev,
+ struct device *miidev,
+ struct dsa_platform_data *d);
+
+#endif /* _ATH79_DEV_DSA_H */
--- /dev/null
+/*
+ * Atheros AR71xx SoC platform devices
+ *
+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
+ * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * Parts of this file are based on Atheros 2.6.15 BSP
+ * Parts of this file are based on Atheros 2.6.31 BSP
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/etherdevice.h>
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+
+#include <asm/mach-ath79/ath79.h>
+#include <asm/mach-ath79/ar71xx_regs.h>
+#include <asm/mach-ath79/irq.h>
+
+#include "common.h"
+#include "dev-eth.h"
+
+unsigned char ath79_mac_base[ETH_ALEN] __initdata;
+
+static struct resource ath79_mdio0_resources[] = {
+ {
+ .name = "mdio_base",
+ .flags = IORESOURCE_MEM,
+ .start = AR71XX_GE0_BASE,
+ .end = AR71XX_GE0_BASE + 0x200 - 1,
+ }
+};
+
+static struct ag71xx_mdio_platform_data ath79_mdio0_data;
+
+struct platform_device ath79_mdio0_device = {
+ .name = "ag71xx-mdio",
+ .id = 0,
+ .resource = ath79_mdio0_resources,
+ .num_resources = ARRAY_SIZE(ath79_mdio0_resources),
+ .dev = {
+ .platform_data = &ath79_mdio0_data,
+ },
+};
+
+static struct resource ath79_mdio1_resources[] = {
+ {
+ .name = "mdio_base",
+ .flags = IORESOURCE_MEM,
+ .start = AR71XX_GE1_BASE,
+ .end = AR71XX_GE1_BASE + 0x200 - 1,
+ }
+};
+
+static struct ag71xx_mdio_platform_data ath79_mdio1_data;
+
+struct platform_device ath79_mdio1_device = {
+ .name = "ag71xx-mdio",
+ .id = 1,
+ .resource = ath79_mdio1_resources,
+ .num_resources = ARRAY_SIZE(ath79_mdio1_resources),
+ .dev = {
+ .platform_data = &ath79_mdio1_data,
+ },
+};
+
+static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
+{
+ void __iomem *base;
+ u32 t;
+
+ base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
+
+ t = __raw_readl(base + cfg_reg);
+ t &= ~(3 << shift);
+ t |= (2 << shift);
+ __raw_writel(t, base + cfg_reg);
+ udelay(100);
+
+ __raw_writel(pll_val, base + pll_reg);
+
+ t |= (3 << shift);
+ __raw_writel(t, base + cfg_reg);
+ udelay(100);
+
+ t &= ~(3 << shift);
+ __raw_writel(t, base + cfg_reg);
+ udelay(100);
+
+ printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
+ (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
+
+ iounmap(base);
+}
+
+static void __init ath79_mii_ctrl_set_if(unsigned int reg,
+ unsigned int mii_if)
+{
+ void __iomem *base;
+ u32 t;
+
+ base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
+
+ t = __raw_readl(base + reg);
+ t &= ~(AR71XX_MII_CTRL_IF_MASK);
+ t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
+ __raw_writel(t, base + reg);
+
+ iounmap(base);
+}
+
+static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
+{
+ void __iomem *base;
+ unsigned int mii_speed;
+ u32 t;
+
+ switch (speed) {
+ case SPEED_10:
+ mii_speed = AR71XX_MII_CTRL_SPEED_10;
+ break;
+ case SPEED_100:
+ mii_speed = AR71XX_MII_CTRL_SPEED_100;
+ break;
+ case SPEED_1000:
+ mii_speed = AR71XX_MII_CTRL_SPEED_1000;
+ break;
+ default:
+ BUG();
+ }
+
+ base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
+
+ t = __raw_readl(base + reg);
+ t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
+ t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
+ __raw_writel(t, base + reg);
+
+ iounmap(base);
+}
+
+void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
+{
+ struct platform_device *mdio_dev;
+ struct ag71xx_mdio_platform_data *mdio_data;
+ unsigned int max_id;
+
+ if (ath79_soc == ATH79_SOC_AR9341 ||
+ ath79_soc == ATH79_SOC_AR9342 ||
+ ath79_soc == ATH79_SOC_AR9344)
+ max_id = 1;
+ else
+ max_id = 0;
+
+ if (id > max_id) {
+ printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
+ return;
+ }
+
+ switch (ath79_soc) {
+ case ATH79_SOC_AR7241:
+ case ATH79_SOC_AR9330:
+ case ATH79_SOC_AR9331:
+ mdio_dev = &ath79_mdio1_device;
+ mdio_data = &ath79_mdio1_data;
+ break;
+
+ case ATH79_SOC_AR9341:
+ case ATH79_SOC_AR9342:
+ case ATH79_SOC_AR9344:
+ if (id == 0) {
+ mdio_dev = &ath79_mdio0_device;
+ mdio_data = &ath79_mdio0_data;
+ } else {
+ mdio_dev = &ath79_mdio1_device;
+ mdio_data = &ath79_mdio1_data;
+ }
+ break;
+
+ case ATH79_SOC_AR7242:
+ ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
+ AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
+ AR71XX_ETH0_PLL_SHIFT);
+ /* fall through */
+ default:
+ mdio_dev = &ath79_mdio0_device;
+ mdio_data = &ath79_mdio0_data;
+ break;
+ }
+
+ mdio_data->phy_mask = phy_mask;
+
+ switch (ath79_soc) {
+ case ATH79_SOC_AR7240:
+ case ATH79_SOC_AR7241:
+ case ATH79_SOC_AR9330:
+ case ATH79_SOC_AR9331:
+ mdio_data->is_ar7240 = 1;
+ break;
+
+ case ATH79_SOC_AR9341:
+ case ATH79_SOC_AR9342:
+ case ATH79_SOC_AR9344:
+ if (id == 1)
+ mdio_data->is_ar7240 = 1;
+ break;
+
+ default:
+ break;
+ }
+
+ platform_device_register(mdio_dev);
+}
+
+struct ath79_eth_pll_data ath79_eth0_pll_data;
+struct ath79_eth_pll_data ath79_eth1_pll_data;
+
+static u32 ath79_get_eth_pll(unsigned int mac, int speed)
+{
+ struct ath79_eth_pll_data *pll_data;
+ u32 pll_val;
+
+ switch (mac) {
+ case 0:
+ pll_data = &ath79_eth0_pll_data;
+ break;
+ case 1:
+ pll_data = &ath79_eth1_pll_data;
+ break;
+ default:
+ BUG();
+ }
+
+ switch (speed) {
+ case SPEED_10:
+ pll_val = pll_data->pll_10;
+ break;
+ case SPEED_100:
+ pll_val = pll_data->pll_100;
+ break;
+ case SPEED_1000:
+ pll_val = pll_data->pll_1000;
+ break;
+ default:
+ BUG();
+ }
+
+ return pll_val;
+}
+
+static void ath79_set_speed_ge0(int speed)
+{
+ u32 val = ath79_get_eth_pll(0, speed);
+
+ ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
+ val, AR71XX_ETH0_PLL_SHIFT);
+ ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
+}
+
+static void ath79_set_speed_ge1(int speed)
+{
+ u32 val = ath79_get_eth_pll(1, speed);
+
+ ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
+ val, AR71XX_ETH1_PLL_SHIFT);
+ ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
+}
+
+static void ar724x_set_speed_ge0(int speed)
+{
+ /* TODO */
+}
+
+static void ar724x_set_speed_ge1(int speed)
+{
+ /* TODO */
+}
+
+static void ar7242_set_speed_ge0(int speed)
+{
+ u32 val = ath79_get_eth_pll(0, speed);
+ void __iomem *base;
+
+ base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
+ __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
+ iounmap(base);
+}
+
+static void ar91xx_set_speed_ge0(int speed)
+{
+ u32 val = ath79_get_eth_pll(0, speed);
+
+ ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK,
+ val, AR913X_ETH0_PLL_SHIFT);
+ ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
+}
+
+static void ar91xx_set_speed_ge1(int speed)
+{
+ u32 val = ath79_get_eth_pll(1, speed);
+
+ ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK,
+ val, AR913X_ETH1_PLL_SHIFT);
+ ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
+}
+
+static void ar933x_set_speed_ge0(int speed)
+{
+ /* TODO */
+}
+
+static void ar933x_set_speed_ge1(int speed)
+{
+ /* TODO */
+}
+
+static void ar934x_set_speed_ge0(int speed)
+{
+ /* TODO */
+}
+
+static void ar934x_set_speed_ge1(int speed)
+{
+ /* TODO */
+}
+
+static void ath79_ddr_flush_ge0(void)
+{
+ ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0);
+}
+
+static void ath79_ddr_flush_ge1(void)
+{
+ ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1);
+}
+
+static void ar724x_ddr_flush_ge0(void)
+{
+ ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0);
+}
+
+static void ar724x_ddr_flush_ge1(void)
+{
+ ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1);
+}
+
+static void ar91xx_ddr_flush_ge0(void)
+{
+ ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0);
+}
+
+static void ar91xx_ddr_flush_ge1(void)
+{
+ ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1);
+}
+
+static void ar933x_ddr_flush_ge0(void)
+{
+ ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0);
+}
+
+static void ar933x_ddr_flush_ge1(void)
+{
+ ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1);
+}
+
+static void ar934x_ddr_flush_ge0(void)
+{
+ ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_GE0);
+}
+
+static void ar934x_ddr_flush_ge1(void)
+{
+ ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_GE1);
+}
+
+static struct resource ath79_eth0_resources[] = {
+ {
+ .name = "mac_base",
+ .flags = IORESOURCE_MEM,
+ .start = AR71XX_GE0_BASE,
+ .end = AR71XX_GE0_BASE + 0x200 - 1,
+ }, {
+ .name = "mac_irq",
+ .flags = IORESOURCE_IRQ,
+ .start = ATH79_CPU_IRQ_GE0,
+ .end = ATH79_CPU_IRQ_GE0,
+ },
+};
+
+struct ag71xx_platform_data ath79_eth0_data = {
+ .reset_bit = AR71XX_RESET_GE0_MAC,
+};
+
+struct platform_device ath79_eth0_device = {
+ .name = "ag71xx",
+ .id = 0,
+ .resource = ath79_eth0_resources,
+ .num_resources = ARRAY_SIZE(ath79_eth0_resources),
+ .dev = {
+ .platform_data = &ath79_eth0_data,
+ },
+};
+
+static struct resource ath79_eth1_resources[] = {
+ {
+ .name = "mac_base",
+ .flags = IORESOURCE_MEM,
+ .start = AR71XX_GE1_BASE,
+ .end = AR71XX_GE1_BASE + 0x200 - 1,
+ }, {
+ .name = "mac_irq",
+ .flags = IORESOURCE_IRQ,
+ .start = ATH79_CPU_IRQ_GE1,
+ .end = ATH79_CPU_IRQ_GE1,
+ },
+};
+
+struct ag71xx_platform_data ath79_eth1_data = {
+ .reset_bit = AR71XX_RESET_GE1_MAC,
+};
+
+struct platform_device ath79_eth1_device = {
+ .name = "ag71xx",
+ .id = 1,
+ .resource = ath79_eth1_resources,
+ .num_resources = ARRAY_SIZE(ath79_eth1_resources),
+ .dev = {
+ .platform_data = &ath79_eth1_data,
+ },
+};
+
+struct ag71xx_switch_platform_data ath79_switch_data;
+
+#define AR71XX_PLL_VAL_1000 0x00110000
+#define AR71XX_PLL_VAL_100 0x00001099
+#define AR71XX_PLL_VAL_10 0x00991099
+
+#define AR724X_PLL_VAL_1000 0x00110000
+#define AR724X_PLL_VAL_100 0x00001099
+#define AR724X_PLL_VAL_10 0x00991099
+
+#define AR7242_PLL_VAL_1000 0x16000000
+#define AR7242_PLL_VAL_100 0x00000101
+#define AR7242_PLL_VAL_10 0x00001616
+
+#define AR913X_PLL_VAL_1000 0x1a000000
+#define AR913X_PLL_VAL_100 0x13000a44
+#define AR913X_PLL_VAL_10 0x00441099
+
+#define AR933X_PLL_VAL_1000 0x00110000
+#define AR933X_PLL_VAL_100 0x00001099
+#define AR933X_PLL_VAL_10 0x00991099
+
+#define AR934X_PLL_VAL_1000 0x00110000
+#define AR934X_PLL_VAL_100 0x00001099
+#define AR934X_PLL_VAL_10 0x00991099
+
+static void __init ath79_init_eth_pll_data(unsigned int id)
+{
+ struct ath79_eth_pll_data *pll_data;
+ u32 pll_10, pll_100, pll_1000;
+
+ switch (id) {
+ case 0:
+ pll_data = &ath79_eth0_pll_data;
+ break;
+ case 1:
+ pll_data = &ath79_eth1_pll_data;
+ break;
+ default:
+ BUG();
+ }
+
+ switch (ath79_soc) {
+ case ATH79_SOC_AR7130:
+ case ATH79_SOC_AR7141:
+ case ATH79_SOC_AR7161:
+ pll_10 = AR71XX_PLL_VAL_10;
+ pll_100 = AR71XX_PLL_VAL_100;
+ pll_1000 = AR71XX_PLL_VAL_1000;
+ break;
+
+ case ATH79_SOC_AR7240:
+ case ATH79_SOC_AR7241:
+ pll_10 = AR724X_PLL_VAL_10;
+ pll_100 = AR724X_PLL_VAL_100;
+ pll_1000 = AR724X_PLL_VAL_1000;
+ break;
+
+ case ATH79_SOC_AR7242:
+ pll_10 = AR7242_PLL_VAL_10;
+ pll_100 = AR7242_PLL_VAL_100;
+ pll_1000 = AR7242_PLL_VAL_1000;
+ break;
+
+ case ATH79_SOC_AR9130:
+ case ATH79_SOC_AR9132:
+ pll_10 = AR913X_PLL_VAL_10;
+ pll_100 = AR913X_PLL_VAL_100;
+ pll_1000 = AR913X_PLL_VAL_1000;
+ break;
+
+ case ATH79_SOC_AR9330:
+ case ATH79_SOC_AR9331:
+ pll_10 = AR933X_PLL_VAL_10;
+ pll_100 = AR933X_PLL_VAL_100;
+ pll_1000 = AR933X_PLL_VAL_1000;
+ break;
+
+ case ATH79_SOC_AR9341:
+ case ATH79_SOC_AR9342:
+ case ATH79_SOC_AR9344:
+ pll_10 = AR934X_PLL_VAL_10;
+ pll_100 = AR934X_PLL_VAL_100;
+ pll_1000 = AR934X_PLL_VAL_1000;
+ break;
+
+ default:
+ BUG();
+ }
+
+ if (!pll_data->pll_10)
+ pll_data->pll_10 = pll_10;
+
+ if (!pll_data->pll_100)
+ pll_data->pll_100 = pll_100;
+
+ if (!pll_data->pll_1000)
+ pll_data->pll_1000 = pll_1000;
+}
+
+static int __init ath79_setup_phy_if_mode(unsigned int id,
+ struct ag71xx_platform_data *pdata)
+{
+ unsigned int mii_if;
+
+ switch (id) {
+ case 0:
+ switch (ath79_soc) {
+ case ATH79_SOC_AR7130:
+ case ATH79_SOC_AR7141:
+ case ATH79_SOC_AR7161:
+ case ATH79_SOC_AR9130:
+ case ATH79_SOC_AR9132:
+ switch (pdata->phy_if_mode) {
+ case PHY_INTERFACE_MODE_MII:
+ mii_if = AR71XX_MII0_CTRL_IF_MII;
+ break;
+ case PHY_INTERFACE_MODE_GMII:
+ mii_if = AR71XX_MII0_CTRL_IF_GMII;
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ mii_if = AR71XX_MII0_CTRL_IF_RGMII;
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ mii_if = AR71XX_MII0_CTRL_IF_RMII;
+ break;
+ default:
+ return -EINVAL;
+ }
+ ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if);
+ break;
+
+ case ATH79_SOC_AR7240:
+ case ATH79_SOC_AR7241:
+ case ATH79_SOC_AR9330:
+ case ATH79_SOC_AR9331:
+ pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
+ break;
+
+ case ATH79_SOC_AR7242:
+ /* FIXME */
+
+ case ATH79_SOC_AR9341:
+ case ATH79_SOC_AR9342:
+ case ATH79_SOC_AR9344:
+ switch (pdata->phy_if_mode) {
+ case PHY_INTERFACE_MODE_MII:
+ case PHY_INTERFACE_MODE_GMII:
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RMII:
+ break;
+ default:
+ return -EINVAL;
+ }
+ break;
+
+ default:
+ BUG();
+ }
+ break;
+ case 1:
+ switch (ath79_soc) {
+ case ATH79_SOC_AR7130:
+ case ATH79_SOC_AR7141:
+ case ATH79_SOC_AR7161:
+ case ATH79_SOC_AR9130:
+ case ATH79_SOC_AR9132:
+ switch (pdata->phy_if_mode) {
+ case PHY_INTERFACE_MODE_RMII:
+ mii_if = AR71XX_MII1_CTRL_IF_RMII;
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ mii_if = AR71XX_MII1_CTRL_IF_RGMII;
+ break;
+ default:
+ return -EINVAL;
+ }
+ ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if);
+ break;
+
+ case ATH79_SOC_AR7240:
+ case ATH79_SOC_AR7241:
+ case ATH79_SOC_AR9330:
+ case ATH79_SOC_AR9331:
+ pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
+ break;
+
+ case ATH79_SOC_AR7242:
+ /* FIXME */
+
+ case ATH79_SOC_AR9341:
+ case ATH79_SOC_AR9342:
+ case ATH79_SOC_AR9344:
+ switch (pdata->phy_if_mode) {
+ case PHY_INTERFACE_MODE_MII:
+ case PHY_INTERFACE_MODE_GMII:
+ break;
+ default:
+ return -EINVAL;
+ }
+ break;
+
+ default:
+ BUG();
+ }
+ break;
+ }
+
+ return 0;
+}
+
+static int ath79_eth_instance __initdata;
+void __init ath79_register_eth(unsigned int id)
+{
+ struct platform_device *pdev;
+ struct ag71xx_platform_data *pdata;
+ int err;
+
+ if (id > 1) {
+ printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
+ return;
+ }
+
+ ath79_init_eth_pll_data(id);
+
+ if (id == 0)
+ pdev = &ath79_eth0_device;
+ else
+ pdev = &ath79_eth1_device;
+
+ pdata = pdev->dev.platform_data;
+
+ err = ath79_setup_phy_if_mode(id, pdata);
+ if (err) {
+ printk(KERN_ERR
+ "ar71xx: invalid PHY interface mode for GE%u\n", id);
+ return;
+ }
+
+ switch (ath79_soc) {
+ case ATH79_SOC_AR7130:
+ if (id == 0) {
+ pdata->ddr_flush = ath79_ddr_flush_ge0;
+ pdata->set_speed = ath79_set_speed_ge0;
+ } else {
+ pdata->ddr_flush = ath79_ddr_flush_ge1;
+ pdata->set_speed = ath79_set_speed_ge1;
+ }
+ break;
+
+ case ATH79_SOC_AR7141:
+ case ATH79_SOC_AR7161:
+ if (id == 0) {
+ pdata->ddr_flush = ath79_ddr_flush_ge0;
+ pdata->set_speed = ath79_set_speed_ge0;
+ } else {
+ pdata->ddr_flush = ath79_ddr_flush_ge1;
+ pdata->set_speed = ath79_set_speed_ge1;
+ }
+ pdata->has_gbit = 1;
+ break;
+
+ case ATH79_SOC_AR7242:
+ if (id == 0) {
+ pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
+ AR71XX_RESET_GE0_PHY;
+ pdata->ddr_flush = ar724x_ddr_flush_ge0;
+ pdata->set_speed = ar7242_set_speed_ge0;
+ } else {
+ pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
+ AR71XX_RESET_GE1_PHY;
+ pdata->ddr_flush = ar724x_ddr_flush_ge1;
+ pdata->set_speed = ar724x_set_speed_ge1;
+ }
+ pdata->has_gbit = 1;
+ pdata->is_ar724x = 1;
+
+ if (!pdata->fifo_cfg1)
+ pdata->fifo_cfg1 = 0x0010ffff;
+ if (!pdata->fifo_cfg2)
+ pdata->fifo_cfg2 = 0x015500aa;
+ if (!pdata->fifo_cfg3)
+ pdata->fifo_cfg3 = 0x01f00140;
+ break;
+
+ case ATH79_SOC_AR7241:
+ if (id == 0)
+ pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
+ else
+ pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
+ /* fall through */
+ case ATH79_SOC_AR7240:
+ if (id == 0) {
+ pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
+ pdata->ddr_flush = ar724x_ddr_flush_ge0;
+ pdata->set_speed = ar724x_set_speed_ge0;
+
+ pdata->phy_mask = BIT(4);
+ } else {
+ pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
+ pdata->ddr_flush = ar724x_ddr_flush_ge1;
+ pdata->set_speed = ar724x_set_speed_ge1;
+
+ pdata->speed = SPEED_1000;
+ pdata->duplex = DUPLEX_FULL;
+ pdata->switch_data = &ath79_switch_data;
+ }
+ pdata->has_gbit = 1;
+ pdata->is_ar724x = 1;
+ if (ath79_soc == ATH79_SOC_AR7240)
+ pdata->is_ar7240 = 1;
+
+ if (!pdata->fifo_cfg1)
+ pdata->fifo_cfg1 = 0x0010ffff;
+ if (!pdata->fifo_cfg2)
+ pdata->fifo_cfg2 = 0x015500aa;
+ if (!pdata->fifo_cfg3)
+ pdata->fifo_cfg3 = 0x01f00140;
+ break;
+
+ case ATH79_SOC_AR9130:
+ if (id == 0) {
+ pdata->ddr_flush = ar91xx_ddr_flush_ge0;
+ pdata->set_speed = ar91xx_set_speed_ge0;
+ } else {
+ pdata->ddr_flush = ar91xx_ddr_flush_ge1;
+ pdata->set_speed = ar91xx_set_speed_ge1;
+ }
+ pdata->is_ar91xx = 1;
+ break;
+
+ case ATH79_SOC_AR9132:
+ if (id == 0) {
+ pdata->ddr_flush = ar91xx_ddr_flush_ge0;
+ pdata->set_speed = ar91xx_set_speed_ge0;
+ } else {
+ pdata->ddr_flush = ar91xx_ddr_flush_ge1;
+ pdata->set_speed = ar91xx_set_speed_ge1;
+ }
+ pdata->is_ar91xx = 1;
+ pdata->has_gbit = 1;
+ break;
+
+ case ATH79_SOC_AR9330:
+ case ATH79_SOC_AR9331:
+ if (id == 0) {
+ pdata->reset_bit = AR933X_RESET_GE0_MAC |
+ AR933X_RESET_GE0_MDIO;
+ pdata->ddr_flush = ar933x_ddr_flush_ge0;
+ pdata->set_speed = ar933x_set_speed_ge0;
+
+ pdata->phy_mask = BIT(4);
+ } else {
+ pdata->reset_bit = AR933X_RESET_GE1_MAC |
+ AR933X_RESET_GE1_MDIO;
+ pdata->ddr_flush = ar933x_ddr_flush_ge1;
+ pdata->set_speed = ar933x_set_speed_ge1;
+
+ pdata->speed = SPEED_1000;
+ pdata->duplex = DUPLEX_FULL;
+ pdata->switch_data = &ath79_switch_data;
+ }
+
+ pdata->has_gbit = 1;
+ pdata->is_ar724x = 1;
+
+ if (!pdata->fifo_cfg1)
+ pdata->fifo_cfg1 = 0x0010ffff;
+ if (!pdata->fifo_cfg2)
+ pdata->fifo_cfg2 = 0x015500aa;
+ if (!pdata->fifo_cfg3)
+ pdata->fifo_cfg3 = 0x01f00140;
+ break;
+
+ case ATH79_SOC_AR9341:
+ case ATH79_SOC_AR9342:
+ case ATH79_SOC_AR9344:
+ if (id == 0) {
+ pdata->reset_bit = AR934X_RESET_GE0_MAC |
+ AR934X_RESET_GE0_MDIO;
+ pdata->ddr_flush =ar934x_ddr_flush_ge0;
+ pdata->set_speed = ar934x_set_speed_ge0;
+ } else {
+ pdata->reset_bit = AR934X_RESET_GE1_MAC |
+ AR934X_RESET_GE1_MDIO;
+ pdata->ddr_flush = ar934x_ddr_flush_ge1;
+ pdata->set_speed = ar934x_set_speed_ge1;
+
+ pdata->switch_data = &ath79_switch_data;
+ }
+
+ pdata->has_gbit = 1;
+ pdata->is_ar724x = 1;
+
+ if (!pdata->fifo_cfg1)
+ pdata->fifo_cfg1 = 0x0010ffff;
+ if (!pdata->fifo_cfg2)
+ pdata->fifo_cfg2 = 0x015500aa;
+ if (!pdata->fifo_cfg3)
+ pdata->fifo_cfg3 = 0x01f00140;
+ break;
+
+ default:
+ BUG();
+ }
+
+ switch (pdata->phy_if_mode) {
+ case PHY_INTERFACE_MODE_GMII:
+ case PHY_INTERFACE_MODE_RGMII:
+ if (!pdata->has_gbit) {
+ printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
+ id);
+ return;
+ }
+ /* fallthrough */
+ default:
+ break;
+ }
+
+ if (!is_valid_ether_addr(pdata->mac_addr)) {
+ random_ether_addr(pdata->mac_addr);
+ printk(KERN_DEBUG
+ "ar71xx: using random MAC address for eth%d\n",
+ ath79_eth_instance);
+ }
+
+ if (pdata->mii_bus_dev == NULL) {
+ switch (ath79_soc) {
+ case ATH79_SOC_AR9341:
+ case ATH79_SOC_AR9342:
+ case ATH79_SOC_AR9344:
+ if (id == 0)
+ pdata->mii_bus_dev = &ath79_mdio0_device.dev;
+ else
+ pdata->mii_bus_dev = &ath79_mdio1_device.dev;
+ break;
+
+ case ATH79_SOC_AR7241:
+ case ATH79_SOC_AR9330:
+ case ATH79_SOC_AR9331:
+ pdata->mii_bus_dev = &ath79_mdio1_device.dev;
+ break;
+
+ default:
+ pdata->mii_bus_dev = &ath79_mdio0_device.dev;
+ break;
+ }
+ }
+
+ /* Reset the device */
+ ath79_device_reset_set(pdata->reset_bit);
+ mdelay(100);
+
+ ath79_device_reset_clear(pdata->reset_bit);
+ mdelay(100);
+
+ platform_device_register(pdev);
+ ath79_eth_instance++;
+}
+
+void __init ath79_set_mac_base(unsigned char *mac)
+{
+ memcpy(ath79_mac_base, mac, ETH_ALEN);
+}
+
+void __init ath79_parse_mac_addr(char *mac_str)
+{
+ u8 tmp[ETH_ALEN];
+ int t;
+
+ t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
+ &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
+
+ if (t != ETH_ALEN)
+ t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
+ &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
+
+ if (t == ETH_ALEN)
+ ath79_set_mac_base(tmp);
+ else
+ printk(KERN_DEBUG "ar71xx: failed to parse mac address "
+ "\"%s\"\n", mac_str);
+}
+
+static int __init ath79_ethaddr_setup(char *str)
+{
+ ath79_parse_mac_addr(str);
+ return 1;
+}
+__setup("ethaddr=", ath79_ethaddr_setup);
+
+static int __init ath79_kmac_setup(char *str)
+{
+ ath79_parse_mac_addr(str);
+ return 1;
+}
+__setup("kmac=", ath79_kmac_setup);
+
+void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
+ int offset)
+{
+ int t;
+
+ if (!is_valid_ether_addr(src)) {
+ memset(dst, '\0', ETH_ALEN);
+ return;
+ }
+
+ t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
+ t += offset;
+
+ dst[0] = src[0];
+ dst[1] = src[1];
+ dst[2] = src[2];
+ dst[3] = (t >> 16) & 0xff;
+ dst[4] = (t >> 8) & 0xff;
+ dst[5] = t & 0xff;
+}
+
+void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
+{
+ int i;
+
+ if (!is_valid_ether_addr(src)) {
+ memset(dst, '\0', ETH_ALEN);
+ return;
+ }
+
+ for (i = 0; i < ETH_ALEN; i++)
+ dst[i] = src[i];
+ dst[0] |= 0x02;
+}
--- /dev/null
+/*
+ * Atheros AR71xx SoC device definitions
+ *
+ * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef _ATH79_DEV_ETH_H
+#define _ATH79_DEV_ETH_H
+
+#include <asm/mach-ath79/ag71xx_platform.h>
+
+struct platform_device;
+
+extern unsigned char ath79_mac_base[] __initdata;
+void ath79_parse_mac_addr(char *mac_str);
+void ath79_init_mac(unsigned char *dst, const unsigned char *src,
+ int offset);
+void ath79_init_local_mac(unsigned char *dst, const unsigned char *src);
+
+struct ath79_eth_pll_data {
+ u32 pll_10;
+ u32 pll_100;
+ u32 pll_1000;
+};
+
+extern struct ath79_eth_pll_data ath79_eth0_pll_data;
+extern struct ath79_eth_pll_data ath79_eth1_pll_data;
+
+extern struct ag71xx_platform_data ath79_eth0_data;
+extern struct ag71xx_platform_data ath79_eth1_data;
+extern struct platform_device ath79_eth0_device;
+extern struct platform_device ath79_eth1_device;
+void ath79_register_eth(unsigned int id);
+
+extern struct ag71xx_switch_platform_data ath79_switch_data;
+
+extern struct platform_device ath79_mdio0_device;
+extern struct platform_device ath79_mdio1_device;
+void ath79_register_mdio(unsigned int id, u32 phy_mask);
+
+#endif /* _ATH79_DEV_ETH_H */
--- /dev/null
+/*
+ * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/concat.h>
+
+#include "dev-spi.h"
+#include "dev-m25p80.h"
+
+static struct ath79_spi_controller_data ath79_spi0_cdata =
+{
+ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
+ .cs_line = 0,
+};
+
+static struct ath79_spi_controller_data ath79_spi1_cdata =
+{
+ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
+ .cs_line = 1,
+};
+
+static struct spi_board_info ath79_spi_info[] = {
+ {
+ .bus_num = 0,
+ .chip_select = 0,
+ .max_speed_hz = 25000000,
+ .modalias = "m25p80",
+ .controller_data = &ath79_spi0_cdata,
+ },
+ {
+ .bus_num = 0,
+ .chip_select = 1,
+ .max_speed_hz = 25000000,
+ .modalias = "m25p80",
+ .controller_data = &ath79_spi1_cdata,
+ }
+};
+
+static struct ath79_spi_platform_data ath79_spi_data;
+
+void __init ath79_register_m25p80(struct flash_platform_data *pdata)
+{
+ ath79_spi_data.bus_num = 0;
+ ath79_spi_data.num_chipselect = 1;
+ ath79_spi_info[0].platform_data = pdata;
+ ath79_register_spi(&ath79_spi_data, ath79_spi_info, 1);
+}
+
+static struct flash_platform_data *multi_pdata;
+
+static struct mtd_info *concat_devs[2] = { NULL, NULL };
+static struct work_struct mtd_concat_work;
+
+static void mtd_concat_add_work(struct work_struct *work)
+{
+ struct mtd_info *mtd;
+
+ mtd = mtd_concat_create(concat_devs, ARRAY_SIZE(concat_devs), "flash");
+
+ mtd_device_register(mtd, multi_pdata->parts, multi_pdata->nr_parts);
+}
+
+static void mtd_concat_add(struct mtd_info *mtd)
+{
+ static bool registered = false;
+
+ if (registered)
+ return;
+
+ if (!strcmp(mtd->name, "spi0.0"))
+ concat_devs[0] = mtd;
+ else if (!strcmp(mtd->name, "spi0.1"))
+ concat_devs[1] = mtd;
+ else
+ return;
+
+ if (!concat_devs[0] || !concat_devs[1])
+ return;
+
+ registered = true;
+ INIT_WORK(&mtd_concat_work, mtd_concat_add_work);
+ schedule_work(&mtd_concat_work);
+}
+
+static void mtd_concat_remove(struct mtd_info *mtd)
+{
+}
+
+static void add_mtd_concat_notifier(void)
+{
+ static struct mtd_notifier not = {
+ .add = mtd_concat_add,
+ .remove = mtd_concat_remove,
+ };
+
+ register_mtd_user(¬);
+}
+
+
+void __init ath79_register_m25p80_multi(struct flash_platform_data *pdata)
+{
+ multi_pdata = pdata;
+ add_mtd_concat_notifier();
+ ath79_spi_data.bus_num = 0;
+ ath79_spi_data.num_chipselect = 2;
+ ath79_register_spi(&ath79_spi_data, ath79_spi_info, 2);
+}
--- /dev/null
+/*
+ * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef _ATH79_DEV_M25P80_H
+#define _ATH79_DEV_M25P80_H
+
+#include <linux/spi/flash.h>
+
+void ath79_register_m25p80(struct flash_platform_data *pdata) __init;
+void ath79_register_m25p80_multi(struct flash_platform_data *pdata) __init;
+
+#endif /* _ATH79_DEV_M25P80_H */
--- /dev/null
+/*
+ * ALFA Network AP96 board support
+ *
+ * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/bitops.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/mmc/host.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/mmc_spi.h>
+
+#include <asm/mach-ath79/ath79.h>
+#include <asm/mach-ath79/ar71xx_regs.h>
+
+#include "common.h"
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-spi.h"
+#include "dev-usb.h"
+#include "machtypes.h"
+#include "pci.h"
+
+#define ALFA_AP96_GPIO_PCIE_RESET 2
+#define ALFA_AP96_GPIO_SIM_DETECT 3
+#define ALFA_AP96_GPIO_MICROSD_CD 4
+#define ALFA_AP96_GPIO_PCIE_W_DISABLE 5
+
+#define ALFA_AP96_GPIO_BUTTON_RESET 11
+
+#define ALFA_AP96_KEYS_POLL_INTERVAL 20 /* msecs */
+#define ALFA_AP96_KEYS_DEBOUNCE_INTERVAL (3 * ALFA_AP96_KEYS_POLL_INTERVAL)
+
+static struct gpio_keys_button alfa_ap96_gpio_keys[] __initdata = {
+ {
+ .desc = "Reset button",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = ALFA_AP96_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = ALFA_AP96_GPIO_BUTTON_RESET,
+ .active_low = 1,
+ }
+};
+
+static int alfa_ap96_mmc_get_cd(struct device *dev)
+{
+ return !gpio_get_value(ALFA_AP96_GPIO_MICROSD_CD);
+}
+
+static struct mmc_spi_platform_data alfa_ap96_mmc_data = {
+ .get_cd = alfa_ap96_mmc_get_cd,
+ .caps = MMC_CAP_NEEDS_POLL,
+ .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
+};
+
+static struct ath79_spi_controller_data ap96_spi0_cdata = {
+ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
+ .cs_line = 0,
+};
+
+static struct ath79_spi_controller_data ap96_spi1_cdata = {
+ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
+ .cs_line = 1,
+};
+
+static struct ath79_spi_controller_data ap96_spi2_cdata = {
+ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
+ .cs_line = 2,
+};
+
+static struct spi_board_info alfa_ap96_spi_info[] = {
+ {
+ .bus_num = 0,
+ .chip_select = 0,
+ .max_speed_hz = 25000000,
+ .modalias = "m25p80",
+ .controller_data = &ap96_spi0_cdata
+ }, {
+ .bus_num = 0,
+ .chip_select = 1,
+ .max_speed_hz = 25000000,
+ .modalias = "mmc_spi",
+ .platform_data = &alfa_ap96_mmc_data,
+ .controller_data = &ap96_spi1_cdata
+ }, {
+ .bus_num = 0,
+ .chip_select = 2,
+ .max_speed_hz = 6250000,
+ .modalias = "rtc-pcf2123",
+ .controller_data = &ap96_spi2_cdata
+ },
+};
+
+static struct ath79_spi_platform_data alfa_ap96_spi_data = {
+ .bus_num = 0,
+ .num_chipselect = 3,
+};
+
+static void __init alfa_ap96_gpio_setup(void)
+{
+ ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN |
+ AR71XX_GPIO_FUNC_SPI_CS2_EN);
+
+ gpio_request(ALFA_AP96_GPIO_MICROSD_CD, "microSD CD");
+ gpio_direction_input(ALFA_AP96_GPIO_MICROSD_CD);
+ gpio_request(ALFA_AP96_GPIO_PCIE_RESET, "PCIe reset");
+ gpio_direction_output(ALFA_AP96_GPIO_PCIE_RESET, 1);
+ gpio_request(ALFA_AP96_GPIO_PCIE_W_DISABLE, "PCIe write disable");
+ gpio_direction_output(ALFA_AP96_GPIO_PCIE_W_DISABLE, 1);
+}
+
+#define ALFA_AP96_WAN_PHYMASK BIT(4)
+#define ALFA_AP96_LAN_PHYMASK BIT(5)
+#define ALFA_AP96_MDIO_PHYMASK (ALFA_AP96_LAN_PHYMASK | ALFA_AP96_WAN_PHYMASK)
+
+static void __init alfa_ap96_init(void)
+{
+ alfa_ap96_gpio_setup();
+
+ ath79_register_mdio(0, ~ALFA_AP96_MDIO_PHYMASK);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+ ath79_eth0_data.phy_mask = ALFA_AP96_WAN_PHYMASK;
+ ath79_eth1_pll_data.pll_1000 = 0x110000;
+
+ ath79_register_eth(0);
+
+ ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+ ath79_eth1_data.phy_mask = ALFA_AP96_LAN_PHYMASK;
+ ath79_eth1_pll_data.pll_1000 = 0x110000;
+
+ ath79_register_eth(1);
+
+ ath79_register_pci();
+ ath79_register_spi(&alfa_ap96_spi_data, alfa_ap96_spi_info,
+ ARRAY_SIZE(alfa_ap96_spi_info));
+
+ ath79_register_gpio_keys_polled(-1, ALFA_AP96_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(alfa_ap96_gpio_keys),
+ alfa_ap96_gpio_keys);
+ ath79_register_usb();
+}
+
+MIPS_MACHINE(ATH79_MACH_ALFA_AP96, "ALFA-AP96", "ALFA Network AP96",
+ alfa_ap96_init);
--- /dev/null
+/*
+ * ALFA Network N2/N5 board support
+ *
+ * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach-ath79/ar71xx_regs.h>
+#include <asm/mach-ath79/ath79.h>
+
+#include "common.h"
+#include "dev-eth.h"
+#include "dev-ap9x-pci.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "machtypes.h"
+
+#define ALFA_NX_GPIO_LED_2 17
+#define ALFA_NX_GPIO_LED_3 16
+#define ALFA_NX_GPIO_LED_5 12
+#define ALFA_NX_GPIO_LED_6 8
+#define ALFA_NX_GPIO_LED_7 6
+#define ALFA_NX_GPIO_LED_8 7
+
+#define ALFA_NX_GPIO_BTN_RESET 11
+
+#define ALFA_NX_KEYS_POLL_INTERVAL 20 /* msecs */
+#define ALFA_NX_KEYS_DEBOUNCE_INTERVAL (3 * ALFA_NX_KEYS_POLL_INTERVAL)
+
+#define ALFA_NX_MAC0_OFFSET 0
+#define ALFA_NX_MAC1_OFFSET 6
+#define ALFA_NX_CALDATA_OFFSET 0x1000
+
+static struct mtd_partition alfa_nx_partitions[] = {
+ {
+ .name = "u-boot",
+ .offset = 0,
+ .size = 0x040000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "u-boot-env",
+ .offset = 0x040000,
+ .size = 0x010000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "rootfs",
+ .offset = 0x050000,
+ .size = 0x600000,
+ }, {
+ .name = "kernel",
+ .offset = 0x650000,
+ .size = 0x190000,
+ }, {
+ .name = "nvram",
+ .offset = 0x7e0000,
+ .size = 0x010000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "art",
+ .offset = 0x7f0000,
+ .size = 0x010000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "firmware",
+ .offset = 0x050000,
+ .size = 0x780000,
+ }
+};
+
+static struct flash_platform_data alfa_nx_flash_data = {
+ .parts = alfa_nx_partitions,
+ .nr_parts = ARRAY_SIZE(alfa_nx_partitions),
+};
+
+static struct gpio_keys_button alfa_nx_gpio_keys[] __initdata = {
+ {
+ .desc = "Reset button",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = ALFA_NX_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = ALFA_NX_GPIO_BTN_RESET,
+ .active_low = 1,
+ }
+};
+
+static struct gpio_led alfa_nx_leds_gpio[] __initdata = {
+ {
+ .name = "alfa:green:led_2",
+ .gpio = ALFA_NX_GPIO_LED_2,
+ .active_low = 1,
+ }, {
+ .name = "alfa:green:led_3",
+ .gpio = ALFA_NX_GPIO_LED_3,
+ .active_low = 1,
+ }, {
+ .name = "alfa:red:led_5",
+ .gpio = ALFA_NX_GPIO_LED_5,
+ .active_low = 1,
+ }, {
+ .name = "alfa:amber:led_6",
+ .gpio = ALFA_NX_GPIO_LED_6,
+ .active_low = 1,
+ }, {
+ .name = "alfa:green:led_7",
+ .gpio = ALFA_NX_GPIO_LED_7,
+ .active_low = 1,
+ }, {
+ .name = "alfa:green:led_8",
+ .gpio = ALFA_NX_GPIO_LED_8,
+ .active_low = 1,
+ }
+};
+
+static void __init alfa_nx_setup(void)
+{
+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
+
+ ath79_gpio_function_setup(AR724X_GPIO_FUNC_JTAG_DISABLE,
+ AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
+ AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
+ AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
+ AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
+ AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
+
+ ath79_register_m25p80(&alfa_nx_flash_data);
+
+ ath79_register_leds_gpio(0, ARRAY_SIZE(alfa_nx_leds_gpio),
+ alfa_nx_leds_gpio);
+
+ ath79_register_gpio_keys_polled(-1, ALFA_NX_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(alfa_nx_gpio_keys),
+ alfa_nx_gpio_keys);
+
+ ath79_register_mdio(0, 0x0);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr,
+ art + ALFA_NX_MAC0_OFFSET, 0);
+ ath79_init_mac(ath79_eth1_data.mac_addr,
+ art + ALFA_NX_MAC1_OFFSET, 0);
+
+ /* WAN port */
+ ath79_register_eth(0);
+ /* LAN port */
+ ath79_register_eth(1);
+
+ ap91_pci_init(art + ALFA_NX_CALDATA_OFFSET, NULL);
+}
+
+MIPS_MACHINE(ATH79_MACH_ALFA_NX, "ALFA-NX", "ALFA Network N2/N5",
+ alfa_nx_setup);
--- /dev/null
+/*
+ * Allnet ALL0258N support
+ *
+ * Copyright (C) 2011 Daniel Golle <dgolle@allnet.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-eth.h"
+#include "dev-ap9x-pci.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "machtypes.h"
+
+/* found via /sys/gpio/... try and error */
+#define ALL0258N_GPIO_BTN_RESET 1
+#define ALL0258N_GPIO_LED_RSSIHIGH 13
+#define ALL0258N_GPIO_LED_RSSIMEDIUM 15
+#define ALL0258N_GPIO_LED_RSSILOW 14
+
+/* defaults taken from others machs */
+#define ALL0258N_KEYS_POLL_INTERVAL 20 /* msecs */
+#define ALL0258N_KEYS_DEBOUNCE_INTERVAL (3 * ALL0258N_KEYS_POLL_INTERVAL)
+
+/* showed up in the original firmware's bootlog */
+#define ALL0258N_SEC_PHYMASK BIT(3)
+
+/*
+ * from U-Boot bootargs of original firmware:
+ * mtdparts=ar7240-nor0:256k(u-boot),64k(u-boot-env),320k(custom),1024k(kernel),4928k(rootfs),1536k(failsafe),64k(ART)
+ * we use a more OpenWrt-friendly layout now:
+ * mtdparts=ar7240-nor0:256k(u-boot),64k(u-boot-env),896k(kernel),5376k(rootfs),1536k(failsafe),64k(ART)
+ */
+static struct mtd_partition all0258n_partitions[] = {
+ {
+ .name = "u-boot",
+ .offset = 0,
+ .size = 0x040000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "u-boot-env",
+ .offset = 0x040000,
+ .size = 0x010000,
+ }, {
+ .name = "kernel",
+ .offset = 0x050000,
+ .size = 0x0E0000,
+ }, {
+ .name = "rootfs",
+ .offset = 0x130000,
+ .size = 0x540000,
+ }, {
+ .name = "failsafe",
+ .offset = 0x670000,
+ .size = 0x180000,
+ }, {
+ .name = "firmware",
+ .offset = 0x050000,
+ .size = 0x620000,
+ }, {
+ .name = "art",
+ .offset = 0x7F0000,
+ .size = 0x010000,
+ .mask_flags = MTD_WRITEABLE,
+ }
+};
+
+static struct flash_platform_data all0258n_flash_data = {
+ .parts = all0258n_partitions,
+ .nr_parts = ARRAY_SIZE(all0258n_partitions),
+};
+
+static struct gpio_led all0258n_leds_gpio[] __initdata = {
+ {
+ .name = "all0258n:green:rssihigh",
+ .gpio = ALL0258N_GPIO_LED_RSSIHIGH,
+ .active_low = 1,
+ }, {
+ .name = "all0258n:yellow:rssimedium",
+ .gpio = ALL0258N_GPIO_LED_RSSIMEDIUM,
+ .active_low = 1,
+ }, {
+ .name = "all0258n:red:rssilow",
+ .gpio = ALL0258N_GPIO_LED_RSSILOW,
+ .active_low = 1,
+ }
+};
+
+static struct gpio_keys_button all0258n_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = ALL0258N_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = ALL0258N_GPIO_BTN_RESET,
+ .active_low = 1,
+ }
+};
+
+static void __init all0258n_setup(void)
+{
+ u8 *mac = (u8 *) KSEG1ADDR(0x1f7f0000);
+ u8 *ee = (u8 *) KSEG1ADDR(0x1f7f1000);
+
+ ath79_register_m25p80(&all0258n_flash_data);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(all0258n_leds_gpio),
+ all0258n_leds_gpio);
+
+ ath79_register_gpio_keys_polled(-1, ALL0258N_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(all0258n_gpio_keys),
+ all0258n_gpio_keys);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
+ ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
+
+ ath79_eth1_data.phy_mask = ALL0258N_SEC_PHYMASK;
+
+ ath79_register_mdio(0, 0x0);
+
+ ath79_register_eth(0);
+ ath79_register_eth(1);
+
+ ap91_pci_init(ee, mac);
+}
+
+MIPS_MACHINE(ATH79_MACH_ALL0258N, "ALL0258N", "Allnet ALL0258N",
+ all0258n_setup);
--- /dev/null
+/*
+ * Atheros AP83 board support
+ *
+ * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi_gpio.h>
+#include <linux/spi/vsc7385.h>
+
+#include <asm/mach-ath79/ar71xx_regs.h>
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-usb.h"
+#include "dev-wmac.h"
+#include "machtypes.h"
+
+#define AP83_GPIO_LED_WLAN 6
+#define AP83_GPIO_LED_POWER 14
+#define AP83_GPIO_LED_JUMPSTART 15
+#define AP83_GPIO_BTN_JUMPSTART 12
+#define AP83_GPIO_BTN_RESET 21
+
+#define AP83_050_GPIO_VSC7385_CS 1
+#define AP83_050_GPIO_VSC7385_MISO 3
+#define AP83_050_GPIO_VSC7385_MOSI 16
+#define AP83_050_GPIO_VSC7385_SCK 17
+
+#define AP83_KEYS_POLL_INTERVAL 20 /* msecs */
+#define AP83_KEYS_DEBOUNCE_INTERVAL (3 * AP83_KEYS_POLL_INTERVAL)
+
+static struct mtd_partition ap83_flash_partitions[] = {
+ {
+ .name = "u-boot",
+ .offset = 0,
+ .size = 0x040000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "u-boot-env",
+ .offset = 0x040000,
+ .size = 0x020000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "kernel",
+ .offset = 0x060000,
+ .size = 0x140000,
+ }, {
+ .name = "rootfs",
+ .offset = 0x1a0000,
+ .size = 0x650000,
+ }, {
+ .name = "art",
+ .offset = 0x7f0000,
+ .size = 0x010000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "firmware",
+ .offset = 0x060000,
+ .size = 0x790000,
+ }
+};
+
+static struct physmap_flash_data ap83_flash_data = {
+ .width = 2,
+ .parts = ap83_flash_partitions,
+ .nr_parts = ARRAY_SIZE(ap83_flash_partitions),
+};
+
+static struct resource ap83_flash_resources[] = {
+ [0] = {
+ .start = AR71XX_SPI_BASE,
+ .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device ap83_flash_device = {
+ .name = "ar91xx-flash",
+ .id = -1,
+ .resource = ap83_flash_resources,
+ .num_resources = ARRAY_SIZE(ap83_flash_resources),
+ .dev = {
+ .platform_data = &ap83_flash_data,
+ }
+};
+
+static struct gpio_led ap83_leds_gpio[] __initdata = {
+ {
+ .name = "ap83:green:jumpstart",
+ .gpio = AP83_GPIO_LED_JUMPSTART,
+ .active_low = 0,
+ }, {
+ .name = "ap83:green:power",
+ .gpio = AP83_GPIO_LED_POWER,
+ .active_low = 0,
+ }, {
+ .name = "ap83:green:wlan",
+ .gpio = AP83_GPIO_LED_WLAN,
+ .active_low = 0,
+ },
+};
+
+static struct gpio_keys_button ap83_gpio_keys[] __initdata = {
+ {
+ .desc = "soft_reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = AP83_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = AP83_GPIO_BTN_RESET,
+ .active_low = 1,
+ }, {
+ .desc = "jumpstart",
+ .type = EV_KEY,
+ .code = KEY_WPS_BUTTON,
+ .debounce_interval = AP83_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = AP83_GPIO_BTN_JUMPSTART,
+ .active_low = 1,
+ }
+};
+
+static struct resource ap83_040_spi_resources[] = {
+ [0] = {
+ .start = AR71XX_SPI_BASE,
+ .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device ap83_040_spi_device = {
+ .name = "ap83-spi",
+ .id = 0,
+ .resource = ap83_040_spi_resources,
+ .num_resources = ARRAY_SIZE(ap83_040_spi_resources),
+};
+
+static struct spi_gpio_platform_data ap83_050_spi_data = {
+ .miso = AP83_050_GPIO_VSC7385_MISO,
+ .mosi = AP83_050_GPIO_VSC7385_MOSI,
+ .sck = AP83_050_GPIO_VSC7385_SCK,
+ .num_chipselect = 1,
+};
+
+static struct platform_device ap83_050_spi_device = {
+ .name = "spi_gpio",
+ .id = 0,
+ .dev = {
+ .platform_data = &ap83_050_spi_data,
+ }
+};
+
+static void ap83_vsc7385_reset(void)
+{
+ ath79_device_reset_set(AR71XX_RESET_GE1_PHY);
+ udelay(10);
+ ath79_device_reset_clear(AR71XX_RESET_GE1_PHY);
+ mdelay(50);
+}
+
+static struct vsc7385_platform_data ap83_vsc7385_data = {
+ .reset = ap83_vsc7385_reset,
+ .ucode_name = "vsc7385_ucode_ap83.bin",
+ .mac_cfg = {
+ .tx_ipg = 6,
+ .bit2 = 0,
+ .clk_sel = 3,
+ },
+};
+
+static struct spi_board_info ap83_spi_info[] = {
+ {
+ .bus_num = 0,
+ .chip_select = 0,
+ .max_speed_hz = 25000000,
+ .modalias = "spi-vsc7385",
+ .platform_data = &ap83_vsc7385_data,
+ .controller_data = (void *) AP83_050_GPIO_VSC7385_CS,
+ }
+};
+
+static void __init ap83_generic_setup(void)
+{
+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);
+
+ ath79_register_mdio(0, 0xfffffffe);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, eeprom, 0);
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+ ath79_eth0_data.phy_mask = 0x1;
+
+ ath79_register_eth(0);
+
+ ath79_init_mac(ath79_eth1_data.mac_addr, eeprom, 1);
+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+ ath79_eth1_data.speed = SPEED_1000;
+ ath79_eth1_data.duplex = DUPLEX_FULL;
+
+ ath79_eth1_pll_data.pll_1000 = 0x1f000000;
+
+ ath79_register_eth(1);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(ap83_leds_gpio),
+ ap83_leds_gpio);
+
+ ath79_register_gpio_keys_polled(-1, AP83_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(ap83_gpio_keys),
+ ap83_gpio_keys);
+
+ ath79_register_usb();
+
+ ath79_register_wmac(eeprom, NULL);
+
+ platform_device_register(&ap83_flash_device);
+
+ spi_register_board_info(ap83_spi_info, ARRAY_SIZE(ap83_spi_info));
+}
+
+static void ap83_040_flash_lock(struct platform_device *pdev)
+{
+ ath79_flash_acquire();
+}
+
+static void ap83_040_flash_unlock(struct platform_device *pdev)
+{
+ ath79_flash_release();
+}
+
+static void __init ap83_040_setup(void)
+{
+ ap83_flash_data.lock = ap83_040_flash_lock;
+ ap83_flash_data.unlock = ap83_040_flash_unlock;
+ ap83_generic_setup();
+ platform_device_register(&ap83_040_spi_device);
+}
+
+static void __init ap83_050_setup(void)
+{
+ ap83_generic_setup();
+ platform_device_register(&ap83_050_spi_device);
+}
+
+static void __init ap83_setup(void)
+{
+ u8 *board_id = (u8 *) KSEG1ADDR(0x1fff1244);
+ unsigned int board_version;
+
+ board_version = (unsigned int)(board_id[0] - '0');
+ board_version += ((unsigned int)(board_id[1] - '0')) * 10;
+
+ switch (board_version) {
+ case 40:
+ ap83_040_setup();
+ break;
+ case 50:
+ ap83_050_setup();
+ break;
+ default:
+ printk(KERN_WARNING "AP83-%03u board is not yet supported\n",
+ board_version);
+ }
+}
+
+MIPS_MACHINE(ATH79_MACH_AP83, "AP83", "Atheros AP83", ap83_setup);
--- /dev/null
+/*
+ * Atheros AP96 board support
+ *
+ * Copyright (C) 2009 Marco Porsch
+ * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2010 Atheros Communications
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/delay.h>
+
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-ap9x-pci.h"
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "dev-usb.h"
+#include "machtypes.h"
+
+#define AP96_GPIO_LED_12_GREEN 0
+#define AP96_GPIO_LED_3_GREEN 1
+#define AP96_GPIO_LED_2_GREEN 2
+#define AP96_GPIO_LED_WPS_GREEN 4
+#define AP96_GPIO_LED_5_GREEN 5
+#define AP96_GPIO_LED_4_ORANGE 6
+
+/* Reset button - next to the power connector */
+#define AP96_GPIO_BTN_RESET 3
+/* WPS button - next to a led on right */
+#define AP96_GPIO_BTN_WPS 8
+
+#define AP96_KEYS_POLL_INTERVAL 20 /* msecs */
+#define AP96_KEYS_DEBOUNCE_INTERVAL (3 * AP96_KEYS_POLL_INTERVAL)
+
+#define AP96_WMAC0_MAC_OFFSET 0x120c
+#define AP96_WMAC1_MAC_OFFSET 0x520c
+#define AP96_CALDATA0_OFFSET 0x1000
+#define AP96_CALDATA1_OFFSET 0x5000
+
+static struct mtd_partition ap96_partitions[] = {
+ {
+ .name = "uboot",
+ .offset = 0,
+ .size = 0x030000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "env",
+ .offset = 0x030000,
+ .size = 0x010000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "rootfs",
+ .offset = 0x040000,
+ .size = 0x600000,
+ }, {
+ .name = "uImage",
+ .offset = 0x640000,
+ .size = 0x1b0000,
+ }, {
+ .name = "caldata",
+ .offset = 0x7f0000,
+ .size = 0x010000,
+ .mask_flags = MTD_WRITEABLE,
+ }
+};
+
+static struct flash_platform_data ap96_flash_data = {
+ .parts = ap96_partitions,
+ .nr_parts = ARRAY_SIZE(ap96_partitions),
+};
+
+/*
+ * AP96 has 12 unlabeled leds in the front; these are numbered from 1 to 12
+ * below (from left to right on the board). Led 1 seems to be on whenever the
+ * board is powered. Led 11 shows LAN link activity actity. Led 3 is orange;
+ * others are green.
+ *
+ * In addition, there is one led next to a button on the right side for WPS.
+ */
+static struct gpio_led ap96_leds_gpio[] __initdata = {
+ {
+ .name = "ap96:green:led2",
+ .gpio = AP96_GPIO_LED_2_GREEN,
+ .active_low = 1,
+ }, {
+ .name = "ap96:green:led3",
+ .gpio = AP96_GPIO_LED_3_GREEN,
+ .active_low = 1,
+ }, {
+ .name = "ap96:orange:led4",
+ .gpio = AP96_GPIO_LED_4_ORANGE,
+ .active_low = 1,
+ }, {
+ .name = "ap96:green:led5",
+ .gpio = AP96_GPIO_LED_5_GREEN,
+ .active_low = 1,
+ }, {
+ .name = "ap96:green:led12",
+ .gpio = AP96_GPIO_LED_12_GREEN,
+ .active_low = 1,
+ }, { /* next to a button on right */
+ .name = "ap96:green:wps",
+ .gpio = AP96_GPIO_LED_WPS_GREEN,
+ .active_low = 1,
+ }
+};
+
+static struct gpio_keys_button ap96_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = AP96_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = AP96_GPIO_BTN_RESET,
+ .active_low = 1,
+ }, {
+ .desc = "wps",
+ .type = EV_KEY,
+ .code = KEY_WPS_BUTTON,
+ .debounce_interval = AP96_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = AP96_GPIO_BTN_WPS,
+ .active_low = 1,
+ }
+};
+
+#define AP96_WAN_PHYMASK 0x10
+#define AP96_LAN_PHYMASK 0x0f
+
+static void __init ap96_setup(void)
+{
+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
+
+ ath79_register_mdio(0, ~(AP96_WAN_PHYMASK | AP96_LAN_PHYMASK));
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, art, 0);
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+ ath79_eth0_data.phy_mask = AP96_LAN_PHYMASK;
+ ath79_eth0_data.speed = SPEED_1000;
+ ath79_eth0_data.duplex = DUPLEX_FULL;
+
+ ath79_register_eth(0);
+
+ ath79_init_mac(ath79_eth1_data.mac_addr, art, 1);
+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+ ath79_eth1_data.phy_mask = AP96_WAN_PHYMASK;
+
+ ath79_eth1_pll_data.pll_1000 = 0x1f000000;
+
+ ath79_register_eth(1);
+
+ ath79_register_usb();
+
+ ath79_register_m25p80(&ap96_flash_data);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(ap96_leds_gpio),
+ ap96_leds_gpio);
+
+ ath79_register_gpio_keys_polled(-1, AP96_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(ap96_gpio_keys),
+ ap96_gpio_keys);
+
+ ap94_pci_init(art + AP96_CALDATA0_OFFSET,
+ art + AP96_WMAC0_MAC_OFFSET,
+ art + AP96_CALDATA1_OFFSET,
+ art + AP96_WMAC1_MAC_OFFSET);
+}
+
+MIPS_MACHINE(ATH79_MACH_AP96, "AP96", "Atheros AP96", ap96_setup);
--- /dev/null
+/*
+ * AzureWave AW-NR580 board support
+ *
+ * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-eth.h"
+#include "dev-m25p80.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "machtypes.h"
+#include "pci.h"
+
+#define AW_NR580_GPIO_LED_READY_RED 0
+#define AW_NR580_GPIO_LED_WLAN 1
+#define AW_NR580_GPIO_LED_READY_GREEN 2
+#define AW_NR580_GPIO_LED_WPS_GREEN 4
+#define AW_NR580_GPIO_LED_WPS_AMBER 5
+
+#define AW_NR580_GPIO_BTN_WPS 3
+#define AW_NR580_GPIO_BTN_RESET 11
+
+#define AW_NR580_KEYS_POLL_INTERVAL 20 /* msecs */
+#define AW_NR580_KEYS_DEBOUNCE_INTERVAL (3 * AW_NR580_KEYS_POLL_INTERVAL)
+
+static struct gpio_led aw_nr580_leds_gpio[] __initdata = {
+ {
+ .name = "aw-nr580:red:ready",
+ .gpio = AW_NR580_GPIO_LED_READY_RED,
+ .active_low = 0,
+ }, {
+ .name = "aw-nr580:green:ready",
+ .gpio = AW_NR580_GPIO_LED_READY_GREEN,
+ .active_low = 0,
+ }, {
+ .name = "aw-nr580:green:wps",
+ .gpio = AW_NR580_GPIO_LED_WPS_GREEN,
+ .active_low = 0,
+ }, {
+ .name = "aw-nr580:amber:wps",
+ .gpio = AW_NR580_GPIO_LED_WPS_AMBER,
+ .active_low = 0,
+ }, {
+ .name = "aw-nr580:green:wlan",
+ .gpio = AW_NR580_GPIO_LED_WLAN,
+ .active_low = 0,
+ }
+};
+
+static struct gpio_keys_button aw_nr580_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = AW_NR580_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = AW_NR580_GPIO_BTN_RESET,
+ .active_low = 1,
+ }, {
+ .desc = "wps",
+ .type = EV_KEY,
+ .code = KEY_WPS_BUTTON,
+ .debounce_interval = AW_NR580_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = AW_NR580_GPIO_BTN_WPS,
+ .active_low = 1,
+ }
+};
+
+static const char *aw_nr580_part_probes[] = {
+ "RedBoot",
+ NULL,
+};
+
+static struct flash_platform_data aw_nr580_flash_data = {
+ .part_probes = aw_nr580_part_probes,
+};
+
+static void __init aw_nr580_setup(void)
+{
+ ath79_register_mdio(0, 0x0);
+
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
+ ath79_eth0_data.speed = SPEED_100;
+ ath79_eth0_data.duplex = DUPLEX_FULL;
+
+ ath79_register_eth(0);
+
+ ath79_register_pci();
+
+ ath79_register_m25p80(&aw_nr580_flash_data);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(aw_nr580_leds_gpio),
+ aw_nr580_leds_gpio);
+
+ ath79_register_gpio_keys_polled(-1, AW_NR580_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(aw_nr580_gpio_keys),
+ aw_nr580_gpio_keys);
+}
+
+MIPS_MACHINE(ATH79_MACH_AW_NR580, "AW-NR580", "AzureWave AW-NR580",
+ aw_nr580_setup);
--- /dev/null
+/*
+ * D-Link DIR-600 rev. A1 board support
+ *
+ * Copyright (C) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-ap9x-pci.h"
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "machtypes.h"
+#include "nvram.h"
+
+#define DIR_600_A1_GPIO_LED_WPS 0
+#define DIR_600_A1_GPIO_LED_POWER_AMBER 1
+#define DIR_600_A1_GPIO_LED_POWER_GREEN 6
+
+#define DIR_600_A1_GPIO_BTN_RESET 8
+#define DIR_600_A1_GPIO_BTN_WPS 12
+
+#define DIR_600_A1_KEYS_POLL_INTERVAL 20 /* msecs */
+#define DIR_600_A1_KEYS_DEBOUNCE_INTERVAL (3 * DIR_600_A1_KEYS_POLL_INTERVAL)
+
+#define DIR_600_A1_NVRAM_ADDR 0x1f030000
+#define DIR_600_A1_NVRAM_SIZE 0x10000
+
+static struct mtd_partition dir_600_a1_partitions[] = {
+ {
+ .name = "u-boot",
+ .offset = 0,
+ .size = 0x030000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "nvram",
+ .offset = 0x030000,
+ .size = 0x010000,
+ }, {
+ .name = "kernel",
+ .offset = 0x040000,
+ .size = 0x0e0000,
+ }, {
+ .name = "rootfs",
+ .offset = 0x120000,
+ .size = 0x2c0000,
+ }, {
+ .name = "mac",
+ .offset = 0x3e0000,
+ .size = 0x010000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "art",
+ .offset = 0x3f0000,
+ .size = 0x010000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "firmware",
+ .offset = 0x040000,
+ .size = 0x3a0000,
+ }
+};
+
+static struct flash_platform_data dir_600_a1_flash_data = {
+ .parts = dir_600_a1_partitions,
+ .nr_parts = ARRAY_SIZE(dir_600_a1_partitions),
+};
+
+static struct gpio_led dir_600_a1_leds_gpio[] __initdata = {
+ {
+ .name = "dir-600-a1:green:power",
+ .gpio = DIR_600_A1_GPIO_LED_POWER_GREEN,
+ }, {
+ .name = "dir-600-a1:amber:power",
+ .gpio = DIR_600_A1_GPIO_LED_POWER_AMBER,
+ }, {
+ .name = "dir-600-a1:blue:wps",
+ .gpio = DIR_600_A1_GPIO_LED_WPS,
+ .active_low = 1,
+ }
+};
+
+static struct gpio_keys_button dir_600_a1_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = DIR_600_A1_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = DIR_600_A1_GPIO_BTN_RESET,
+ .active_low = 1,
+ }, {
+ .desc = "wps",
+ .type = EV_KEY,
+ .code = KEY_WPS_BUTTON,
+ .debounce_interval = DIR_600_A1_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = DIR_600_A1_GPIO_BTN_WPS,
+ .active_low = 1,
+ }
+};
+
+static void __init dir_600_a1_setup(void)
+{
+ const char *nvram = (char *) KSEG1ADDR(DIR_600_A1_NVRAM_ADDR);
+ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
+ u8 mac_buff[6];
+ u8 *mac = NULL;
+
+ if (ath79_nvram_parse_mac_addr(nvram, DIR_600_A1_NVRAM_SIZE,
+ "lan_mac=", mac_buff) == 0) {
+ ath79_init_mac(ath79_eth0_data.mac_addr, mac_buff, 0);
+ ath79_init_mac(ath79_eth1_data.mac_addr, mac_buff, 1);
+ mac = mac_buff;
+ }
+
+ ath79_register_m25p80(&dir_600_a1_flash_data);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(dir_600_a1_leds_gpio),
+ dir_600_a1_leds_gpio);
+
+ ath79_register_gpio_keys_polled(-1, DIR_600_A1_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(dir_600_a1_gpio_keys),
+ dir_600_a1_gpio_keys);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
+ ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
+
+ ath79_register_mdio(0, 0x0);
+
+ /* LAN ports */
+ ath79_register_eth(1);
+
+ /* WAN port */
+ ath79_register_eth(0);
+
+ ap91_pci_init(ee, mac);
+}
+
+MIPS_MACHINE(ATH79_MACH_DIR_600_A1, "DIR-600-A1", "D-Link DIR-600 rev. A1",
+ dir_600_a1_setup);
--- /dev/null
+/*
+ * D-Link DIR-615 rev C1 board support
+ *
+ * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "dev-wmac.h"
+#include "machtypes.h"
+#include "nvram.h"
+
+#define DIR_615C1_GPIO_LED_ORANGE_STATUS 1 /* ORANGE:STATUS:TRICOLOR */
+#define DIR_615C1_GPIO_LED_BLUE_WPS 3 /* BLUE:WPS */
+#define DIR_615C1_GPIO_LED_GREEN_WAN 4 /* GREEN:WAN:TRICOLOR */
+#define DIR_615C1_GPIO_LED_GREEN_WANCPU 5 /* GREEN:WAN:CPU:TRICOLOR */
+#define DIR_615C1_GPIO_LED_GREEN_WLAN 6 /* GREEN:WLAN */
+#define DIR_615C1_GPIO_LED_GREEN_STATUS 14 /* GREEN:STATUS:TRICOLOR */
+#define DIR_615C1_GPIO_LED_ORANGE_WAN 15 /* ORANGE:WAN:TRICOLOR */
+
+/* buttons may need refinement */
+
+#define DIR_615C1_GPIO_BTN_WPS 12
+#define DIR_615C1_GPIO_BTN_RESET 21
+
+#define DIR_615C1_KEYS_POLL_INTERVAL 20 /* msecs */
+#define DIR_615C1_KEYS_DEBOUNCE_INTERVAL (3 * DIR_615C1_KEYS_POLL_INTERVAL)
+
+#define DIR_615C1_CONFIG_ADDR 0x1f020000
+#define DIR_615C1_CONFIG_SIZE 0x10000
+
+static struct mtd_partition dir_615c1_partitions[] = {
+ {
+ .name = "u-boot",
+ .offset = 0,
+ .size = 0x020000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "config",
+ .offset = 0x020000,
+ .size = 0x010000,
+ }, {
+ .name = "kernel",
+ .offset = 0x030000,
+ .size = 0x0e0000,
+ }, {
+ .name = "rootfs",
+ .offset = 0x110000,
+ .size = 0x2e0000,
+ }, {
+ .name = "art",
+ .offset = 0x3f0000,
+ .size = 0x010000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "firmware",
+ .offset = 0x030000,
+ .size = 0x3c0000,
+ }
+};
+
+static struct flash_platform_data dir_615c1_flash_data = {
+ .parts = dir_615c1_partitions,
+ .nr_parts = ARRAY_SIZE(dir_615c1_partitions),
+};
+
+static struct gpio_led dir_615c1_leds_gpio[] __initdata = {
+ {
+ .name = "dir-615c1:orange:status",
+ .gpio = DIR_615C1_GPIO_LED_ORANGE_STATUS,
+ .active_low = 1,
+ }, {
+ .name = "dir-615c1:blue:wps",
+ .gpio = DIR_615C1_GPIO_LED_BLUE_WPS,
+ .active_low = 1,
+ }, {
+ .name = "dir-615c1:green:wan",
+ .gpio = DIR_615C1_GPIO_LED_GREEN_WAN,
+ .active_low = 1,
+ }, {
+ .name = "dir-615c1:green:wancpu",
+ .gpio = DIR_615C1_GPIO_LED_GREEN_WANCPU,
+ .active_low = 1,
+ }, {
+ .name = "dir-615c1:green:wlan",
+ .gpio = DIR_615C1_GPIO_LED_GREEN_WLAN,
+ .active_low = 1,
+ }, {
+ .name = "dir-615c1:green:status",
+ .gpio = DIR_615C1_GPIO_LED_GREEN_STATUS,
+ .active_low = 1,
+ }, {
+ .name = "dir-615c1:orange:wan",
+ .gpio = DIR_615C1_GPIO_LED_ORANGE_WAN,
+ .active_low = 1,
+ }
+
+};
+
+static struct gpio_keys_button dir_615c1_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = DIR_615C1_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = DIR_615C1_GPIO_BTN_RESET,
+ }, {
+ .desc = "wps",
+ .type = EV_KEY,
+ .code = KEY_WPS_BUTTON,
+ .debounce_interval = DIR_615C1_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = DIR_615C1_GPIO_BTN_WPS,
+ }
+};
+
+#define DIR_615C1_LAN_PHYMASK BIT(0)
+#define DIR_615C1_WAN_PHYMASK BIT(4)
+#define DIR_615C1_MDIO_MASK (~(DIR_615C1_LAN_PHYMASK | \
+ DIR_615C1_WAN_PHYMASK))
+
+static void __init dir_615c1_setup(void)
+{
+ const char *config = (char *) KSEG1ADDR(DIR_615C1_CONFIG_ADDR);
+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);
+ u8 mac[6];
+ u8 *wlan_mac = NULL;
+
+ if (ath79_nvram_parse_mac_addr(config, DIR_615C1_CONFIG_SIZE,
+ "lan_mac=", mac) == 0) {
+ ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
+ ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
+ wlan_mac = mac;
+ }
+
+ ath79_register_mdio(0, DIR_615C1_MDIO_MASK);
+
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
+ ath79_eth0_data.phy_mask = DIR_615C1_LAN_PHYMASK;
+
+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
+ ath79_eth1_data.phy_mask = DIR_615C1_WAN_PHYMASK;
+
+ ath79_register_eth(0);
+ ath79_register_eth(1);
+
+ ath79_register_m25p80(&dir_615c1_flash_data);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(dir_615c1_leds_gpio),
+ dir_615c1_leds_gpio);
+
+ ath79_register_gpio_keys_polled(-1, DIR_615C1_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(dir_615c1_gpio_keys),
+ dir_615c1_gpio_keys);
+
+ ath79_register_wmac(eeprom, wlan_mac);
+}
+
+MIPS_MACHINE(ATH79_MACH_DIR_615_C1, "DIR-615-C1", "D-Link DIR-615 rev. C1",
+ dir_615c1_setup);
--- /dev/null
+/*
+ * D-Link DIR-825 rev. B1 board support
+ *
+ * Copyright (C) 2009-2011 Lukas Kuna, Evkanet, s.r.o.
+ *
+ * based on mach-wndr3700.c
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/delay.h>
+#include <linux/rtl8366.h>
+
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-eth.h"
+#include "dev-ap9x-pci.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "dev-usb.h"
+#include "machtypes.h"
+
+#define DIR825B1_GPIO_LED_BLUE_USB 0
+#define DIR825B1_GPIO_LED_ORANGE_POWER 1
+#define DIR825B1_GPIO_LED_BLUE_POWER 2
+#define DIR825B1_GPIO_LED_BLUE_WPS 4
+#define DIR825B1_GPIO_LED_ORANGE_PLANET 6
+#define DIR825B1_GPIO_LED_BLUE_PLANET 11
+
+#define DIR825B1_GPIO_BTN_RESET 3
+#define DIR825B1_GPIO_BTN_WPS 8
+
+#define DIR825B1_GPIO_RTL8366_SDA 5
+#define DIR825B1_GPIO_RTL8366_SCK 7
+
+#define DIR825B1_KEYS_POLL_INTERVAL 20 /* msecs */
+#define DIR825B1_KEYS_DEBOUNCE_INTERVAL (3 * DIR825B1_KEYS_POLL_INTERVAL)
+
+#define DIR825B1_CAL_LOCATION_0 0x1f661000
+#define DIR825B1_CAL_LOCATION_1 0x1f665000
+
+#define DIR825B1_MAC_LOCATION_0 0x1f66ffa0
+#define DIR825B1_MAC_LOCATION_1 0x1f66ffb4
+
+static struct mtd_partition dir825b1_partitions[] = {
+ {
+ .name = "uboot",
+ .offset = 0,
+ .size = 0x040000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "config",
+ .offset = 0x040000,
+ .size = 0x010000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "firmware",
+ .offset = 0x050000,
+ .size = 0x610000,
+ }, {
+ .name = "caldata",
+ .offset = 0x660000,
+ .size = 0x010000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "unknown",
+ .offset = 0x670000,
+ .size = 0x190000,
+ .mask_flags = MTD_WRITEABLE,
+ }
+};
+
+static struct flash_platform_data dir825b1_flash_data = {
+ .parts = dir825b1_partitions,
+ .nr_parts = ARRAY_SIZE(dir825b1_partitions),
+};
+
+static struct gpio_led dir825b1_leds_gpio[] __initdata = {
+ {
+ .name = "dir825b1:blue:usb",
+ .gpio = DIR825B1_GPIO_LED_BLUE_USB,
+ .active_low = 1,
+ }, {
+ .name = "dir825b1:orange:power",
+ .gpio = DIR825B1_GPIO_LED_ORANGE_POWER,
+ .active_low = 1,
+ }, {
+ .name = "dir825b1:blue:power",
+ .gpio = DIR825B1_GPIO_LED_BLUE_POWER,
+ .active_low = 1,
+ }, {
+ .name = "dir825b1:blue:wps",
+ .gpio = DIR825B1_GPIO_LED_BLUE_WPS,
+ .active_low = 1,
+ }, {
+ .name = "dir825b1:orange:planet",
+ .gpio = DIR825B1_GPIO_LED_ORANGE_PLANET,
+ .active_low = 1,
+ }, {
+ .name = "dir825b1:blue:planet",
+ .gpio = DIR825B1_GPIO_LED_BLUE_PLANET,
+ .active_low = 1,
+ }
+};
+
+static struct gpio_keys_button dir825b1_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = DIR825B1_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = DIR825B1_GPIO_BTN_RESET,
+ .active_low = 1,
+ }, {
+ .desc = "wps",
+ .type = EV_KEY,
+ .code = KEY_WPS_BUTTON,
+ .debounce_interval = DIR825B1_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = DIR825B1_GPIO_BTN_WPS,
+ .active_low = 1,
+ }
+};
+
+static struct rtl8366_initval dir825b1_rtl8366s_initvals[] = {
+ { .reg = 0x06, .val = 0x0108 },
+};
+
+static struct rtl8366_platform_data dir825b1_rtl8366s_data = {
+ .gpio_sda = DIR825B1_GPIO_RTL8366_SDA,
+ .gpio_sck = DIR825B1_GPIO_RTL8366_SCK,
+ .num_initvals = ARRAY_SIZE(dir825b1_rtl8366s_initvals),
+ .initvals = dir825b1_rtl8366s_initvals,
+};
+
+static struct platform_device dir825b1_rtl8366s_device = {
+ .name = RTL8366S_DRIVER_NAME,
+ .id = -1,
+ .dev = {
+ .platform_data = &dir825b1_rtl8366s_data,
+ }
+};
+
+static void dir825b1_read_ascii_mac(u8 *dest, unsigned int src_addr)
+{
+ int ret;
+ u8 *src = (u8 *)KSEG1ADDR(src_addr);
+
+ ret = sscanf(src, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
+ &dest[0], &dest[1], &dest[2],
+ &dest[3], &dest[4], &dest[5]);
+
+ if (ret != ETH_ALEN)
+ memset(dest, 0, ETH_ALEN);
+}
+
+static void __init dir825b1_setup(void)
+{
+ u8 mac1[ETH_ALEN], mac2[ETH_ALEN];
+
+ dir825b1_read_ascii_mac(mac1, DIR825B1_MAC_LOCATION_0);
+ dir825b1_read_ascii_mac(mac2, DIR825B1_MAC_LOCATION_1);
+
+ ath79_register_mdio(0, 0x0);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 2);
+ ath79_eth0_data.mii_bus_dev = &dir825b1_rtl8366s_device.dev;
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+ ath79_eth0_data.speed = SPEED_1000;
+ ath79_eth0_data.duplex = DUPLEX_FULL;
+ ath79_eth0_pll_data.pll_1000 = 0x11110000;
+
+ ath79_init_mac(ath79_eth1_data.mac_addr, mac1, 3);
+ ath79_eth1_data.mii_bus_dev = &dir825b1_rtl8366s_device.dev;
+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+ ath79_eth1_data.phy_mask = 0x10;
+ ath79_eth1_pll_data.pll_1000 = 0x11110000;
+
+ ath79_register_eth(0);
+ ath79_register_eth(1);
+
+ ath79_register_m25p80(&dir825b1_flash_data);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(dir825b1_leds_gpio),
+ dir825b1_leds_gpio);
+
+ ath79_register_gpio_keys_polled(-1, DIR825B1_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(dir825b1_gpio_keys),
+ dir825b1_gpio_keys);
+
+ ath79_register_usb();
+
+ platform_device_register(&dir825b1_rtl8366s_device);
+
+ ap9x_pci_setup_wmac_led_pin(0, 5);
+ ap9x_pci_setup_wmac_led_pin(1, 5);
+
+ ap94_pci_init((u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_0), mac1,
+ (u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_1), mac2);
+}
+
+MIPS_MACHINE(ATH79_MACH_DIR_825_B1, "DIR-825-B1", "D-Link DIR-825 rev. B1",
+ dir825b1_setup);
--- /dev/null
+/*
+ * Senao EAP7660D board support
+ *
+ * Copyright (C) 2010 Daniel Golle <daniel.golle@gmail.com>
+ * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/pci.h>
+#include <linux/ath5k_platform.h>
+#include <linux/delay.h>
+
+#include <asm/mach-ath79/ath79.h>
+#include <asm/mach-ath79/pci.h>
+
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "machtypes.h"
+#include "pci.h"
+
+#define EAP7660D_KEYS_POLL_INTERVAL 20 /* msecs */
+#define EAP7660D_KEYS_DEBOUNCE_INTERVAL (3 * EAP7660D_KEYS_POLL_INTERVAL)
+
+#define EAP7660D_GPIO_DS4 7
+#define EAP7660D_GPIO_DS5 2
+#define EAP7660D_GPIO_DS7 0
+#define EAP7660D_GPIO_DS8 4
+#define EAP7660D_GPIO_SW1 3
+#define EAP7660D_GPIO_SW3 8
+#define EAP7660D_PHYMASK BIT(20)
+#define EAP7660D_BOARDCONFIG 0x1F7F0000
+#define EAP7660D_GBIC_MAC_OFFSET 0x1000
+#define EAP7660D_WMAC0_MAC_OFFSET 0x1010
+#define EAP7660D_WMAC1_MAC_OFFSET 0x1016
+#define EAP7660D_WMAC0_CALDATA_OFFSET 0x2000
+#define EAP7660D_WMAC1_CALDATA_OFFSET 0x3000
+
+static struct ath5k_platform_data eap7660d_wmac0_data;
+static struct ath5k_platform_data eap7660d_wmac1_data;
+static char eap7660d_wmac0_mac[6];
+static char eap7660d_wmac1_mac[6];
+static u16 eap7660d_wmac0_eeprom[ATH5K_PLAT_EEP_MAX_WORDS];
+static u16 eap7660d_wmac1_eeprom[ATH5K_PLAT_EEP_MAX_WORDS];
+
+#ifdef CONFIG_PCI
+static int eap7660d_pci_plat_dev_init(struct pci_dev *dev)
+{
+ switch (PCI_SLOT(dev->devfn)) {
+ case 17:
+ dev->dev.platform_data = &eap7660d_wmac0_data;
+ break;
+
+ case 18:
+ dev->dev.platform_data = &eap7660d_wmac1_data;
+ break;
+ }
+
+ return 0;
+}
+
+void __init eap7660d_pci_init(u8 *cal_data0, u8 *mac_addr0,
+ u8 *cal_data1, u8 *mac_addr1)
+{
+ if (cal_data0 && *cal_data0 == 0xa55a) {
+ memcpy(eap7660d_wmac0_eeprom, cal_data0,
+ ATH5K_PLAT_EEP_MAX_WORDS);
+ eap7660d_wmac0_data.eeprom_data = eap7660d_wmac0_eeprom;
+ }
+
+ if (cal_data1 && *cal_data1 == 0xa55a) {
+ memcpy(eap7660d_wmac1_eeprom, cal_data1,
+ ATH5K_PLAT_EEP_MAX_WORDS);
+ eap7660d_wmac1_data.eeprom_data = eap7660d_wmac1_eeprom;
+ }
+
+ if (mac_addr0) {
+ memcpy(eap7660d_wmac0_mac, mac_addr0,
+ sizeof(eap7660d_wmac0_mac));
+ eap7660d_wmac0_data.macaddr = eap7660d_wmac0_mac;
+ }
+
+ if (mac_addr1) {
+ memcpy(eap7660d_wmac1_mac, mac_addr1,
+ sizeof(eap7660d_wmac1_mac));
+ eap7660d_wmac1_data.macaddr = eap7660d_wmac1_mac;
+ }
+
+ ath79_pci_set_plat_dev_init(eap7660d_pci_plat_dev_init);
+ ath79_register_pci();
+}
+#else
+static inline void eap7660d_pci_init(u8 *cal_data0, u8 *mac_addr0,
+ u8 *cal_data1, u8 *mac_addr1)
+{
+}
+#endif /* CONFIG_PCI */
+
+static struct gpio_led eap7660d_leds_gpio[] __initdata = {
+ {
+ .name = "eap7660d:green:ds8",
+ .gpio = EAP7660D_GPIO_DS8,
+ .active_low = 0,
+ },
+ {
+ .name = "eap7660d:green:ds5",
+ .gpio = EAP7660D_GPIO_DS5,
+ .active_low = 0,
+ },
+ {
+ .name = "eap7660d:green:ds7",
+ .gpio = EAP7660D_GPIO_DS7,
+ .active_low = 0,
+ },
+ {
+ .name = "eap7660d:green:ds4",
+ .gpio = EAP7660D_GPIO_DS4,
+ .active_low = 0,
+ }
+};
+
+static struct gpio_keys_button eap7660d_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = EAP7660D_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = EAP7660D_GPIO_SW1,
+ .active_low = 1,
+ },
+ {
+ .desc = "wps",
+ .type = EV_KEY,
+ .code = KEY_WPS_BUTTON,
+ .debounce_interval = EAP7660D_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = EAP7660D_GPIO_SW3,
+ .active_low = 1,
+ }
+};
+
+static const char *eap7660d_part_probes[] = {
+ "RedBoot",
+ NULL,
+};
+
+static struct flash_platform_data eap7660d_flash_data = {
+ .part_probes = eap7660d_part_probes,
+};
+
+static void __init eap7660d_setup(void)
+{
+ u8 *boardconfig = (u8 *) KSEG1ADDR(EAP7660D_BOARDCONFIG);
+
+ ath79_register_mdio(0, ~EAP7660D_PHYMASK);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr,
+ boardconfig + EAP7660D_GBIC_MAC_OFFSET, 0);
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+ ath79_eth0_data.phy_mask = EAP7660D_PHYMASK;
+ ath79_register_eth(0);
+ ath79_register_m25p80(&eap7660d_flash_data);
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(eap7660d_leds_gpio),
+ eap7660d_leds_gpio);
+ ath79_register_gpio_keys_polled(-1, EAP7660D_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(eap7660d_gpio_keys),
+ eap7660d_gpio_keys);
+ eap7660d_pci_init(boardconfig + EAP7660D_WMAC0_CALDATA_OFFSET,
+ boardconfig + EAP7660D_WMAC0_MAC_OFFSET,
+ boardconfig + EAP7660D_WMAC1_CALDATA_OFFSET,
+ boardconfig + EAP7660D_WMAC1_MAC_OFFSET);
+};
+
+MIPS_MACHINE(ATH79_MACH_EAP7660D, "EAP7660D", "Senao EAP7660D",
+ eap7660d_setup);
--- /dev/null
+/*
+ * ALFA NETWORKS Hornet-UB board support
+ *
+ * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+
+#include <asm/mach-ath79/ath79.h>
+#include <asm/mach-ath79/ar71xx_regs.h>
+
+#include "common.h"
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "dev-usb.h"
+#include "dev-wmac.h"
+#include "machtypes.h"
+
+#define HORNET_UB_GPIO_LED_WLAN 0
+#define HORNET_UB_GPIO_LED_USB 1
+#define HORNET_UB_GPIO_LED_LAN 13
+#define HORNET_UB_GPIO_LED_WAN 17
+#define HORNET_UB_GPIO_LED_WPS 27
+
+#define HORNET_UB_GPIO_BTN_RESET 11
+#define HORNET_UB_GPIO_BTN_WPS 12
+
+#define HORNET_UB_GPIO_USB_POWER 26
+
+#define HORNET_UB_KEYS_POLL_INTERVAL 20 /* msecs */
+#define HORNET_UB_KEYS_DEBOUNCE_INTERVAL (3 * HORNET_UB_KEYS_POLL_INTERVAL)
+
+#define HORNET_UB_MAC0_OFFSET 0x0000
+#define HORNET_UB_MAC1_OFFSET 0x0006
+#define HORNET_UB_CALDATA_OFFSET 0x1000
+
+static struct gpio_led hornet_ub_leds_gpio[] __initdata = {
+ {
+ .name = "alfa:blue:lan",
+ .gpio = HORNET_UB_GPIO_LED_LAN,
+ .active_low = 0,
+ },
+ {
+ .name = "alfa:blue:usb",
+ .gpio = HORNET_UB_GPIO_LED_USB,
+ .active_low = 0,
+ },
+ {
+ .name = "alfa:blue:wan",
+ .gpio = HORNET_UB_GPIO_LED_WAN,
+ .active_low = 1,
+ },
+ {
+ .name = "alfa:blue:wlan",
+ .gpio = HORNET_UB_GPIO_LED_WLAN,
+ .active_low = 0,
+ },
+ {
+ .name = "alfa:blue:wps",
+ .gpio = HORNET_UB_GPIO_LED_WPS,
+ .active_low = 1,
+ },
+};
+
+static struct gpio_keys_button hornet_ub_gpio_keys[] __initdata = {
+ {
+ .desc = "WPS button",
+ .type = EV_KEY,
+ .code = KEY_WPS_BUTTON,
+ .debounce_interval = HORNET_UB_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = HORNET_UB_GPIO_BTN_WPS,
+ .active_low = 1,
+ },
+ {
+ .desc = "Reset button",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = HORNET_UB_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = HORNET_UB_GPIO_BTN_RESET,
+ .active_low = 0,
+ }
+};
+
+static void __init hornet_ub_gpio_setup(void)
+{
+ u32 t;
+
+ ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
+ AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
+ AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
+ AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
+ AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
+
+ t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
+ t |= AR933X_BOOTSTRAP_MDIO_GPIO_EN;
+ ath79_reset_wr(AR933X_RESET_REG_BOOTSTRAP, t);
+
+ gpio_request(HORNET_UB_GPIO_USB_POWER, "USB power");
+ gpio_direction_output(HORNET_UB_GPIO_USB_POWER, 1);
+}
+
+static void __init hornet_ub_setup(void)
+{
+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
+
+ hornet_ub_gpio_setup();
+
+ ath79_register_m25p80(NULL);
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(hornet_ub_leds_gpio),
+ hornet_ub_leds_gpio);
+ ath79_register_gpio_keys_polled(-1, HORNET_UB_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(hornet_ub_gpio_keys),
+ hornet_ub_gpio_keys);
+
+ ath79_init_mac(ath79_eth1_data.mac_addr,
+ art + HORNET_UB_MAC0_OFFSET, 0);
+ ath79_init_mac(ath79_eth0_data.mac_addr,
+ art + HORNET_UB_MAC1_OFFSET, 0);
+
+ ath79_register_mdio(0, 0x0);
+
+ ath79_register_eth(1);
+ ath79_register_eth(0);
+
+ ath79_register_wmac(art + HORNET_UB_CALDATA_OFFSET, NULL);
+ ath79_register_usb();
+}
+
+MIPS_MACHINE(ATH79_MACH_HORNET_UB, "HORNET-UB", "ALFA NETWORKS Hornet-UB",
+ hornet_ub_setup);
--- /dev/null
+/*
+ * jjPlus JA76PF board support
+ */
+
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "dev-usb.h"
+#include "machtypes.h"
+#include "pci.h"
+
+#define JA76PF_KEYS_POLL_INTERVAL 20 /* msecs */
+#define JA76PF_KEYS_DEBOUNCE_INTERVAL (3 * JA76PF_KEYS_POLL_INTERVAL)
+
+#define JA76PF_GPIO_I2C_SCL 0
+#define JA76PF_GPIO_I2C_SDA 1
+#define JA76PF_GPIO_LED_1 5
+#define JA76PF_GPIO_LED_2 4
+#define JA76PF_GPIO_LED_3 3
+#define JA76PF_GPIO_BTN_RESET 11
+
+static struct gpio_led ja76pf_leds_gpio[] __initdata = {
+ {
+ .name = "ja76pf:green:led1",
+ .gpio = JA76PF_GPIO_LED_1,
+ .active_low = 1,
+ }, {
+ .name = "ja76pf:green:led2",
+ .gpio = JA76PF_GPIO_LED_2,
+ .active_low = 1,
+ }, {
+ .name = "ja76pf:green:led3",
+ .gpio = JA76PF_GPIO_LED_3,
+ .active_low = 1,
+ }
+};
+
+static struct gpio_keys_button ja76pf_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = JA76PF_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = JA76PF_GPIO_BTN_RESET,
+ .active_low = 1,
+ }
+};
+
+static struct i2c_gpio_platform_data ja76pf_i2c_gpio_data = {
+ .sda_pin = JA76PF_GPIO_I2C_SDA,
+ .scl_pin = JA76PF_GPIO_I2C_SCL,
+};
+
+static struct platform_device ja76pf_i2c_gpio_device = {
+ .name = "i2c-gpio",
+ .id = 0,
+ .dev = {
+ .platform_data = &ja76pf_i2c_gpio_data,
+ }
+};
+
+static const char *ja76pf_part_probes[] = {
+ "RedBoot",
+ NULL,
+};
+
+static struct flash_platform_data ja76pf_flash_data = {
+ .part_probes = ja76pf_part_probes,
+};
+
+#define JA76PF_WAN_PHYMASK (1 << 4)
+#define JA76PF_LAN_PHYMASK ((1 << 0) | (1 << 1) | (1 << 2) | (1 < 3))
+#define JA76PF_MDIO_PHYMASK (JA76PF_LAN_PHYMASK | JA76PF_WAN_PHYMASK)
+
+static void __init ja76pf_init(void)
+{
+ ath79_register_m25p80(&ja76pf_flash_data);
+
+ ath79_register_mdio(0, ~JA76PF_MDIO_PHYMASK);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+ ath79_eth0_data.phy_mask = JA76PF_LAN_PHYMASK;
+
+ ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+ ath79_eth1_data.phy_mask = JA76PF_WAN_PHYMASK;
+ ath79_eth1_data.speed = SPEED_1000;
+ ath79_eth1_data.duplex = DUPLEX_FULL;
+
+ ath79_register_eth(0);
+ ath79_register_eth(1);
+
+ platform_device_register(&ja76pf_i2c_gpio_device);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(ja76pf_leds_gpio),
+ ja76pf_leds_gpio);
+
+ ath79_register_gpio_keys_polled(-1, JA76PF_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(ja76pf_gpio_keys),
+ ja76pf_gpio_keys);
+
+ ath79_register_usb();
+ ath79_register_pci();
+}
+
+MIPS_MACHINE(ATH79_MACH_JA76PF, "JA76PF", "jjPlus JA76PF", ja76pf_init);
--- /dev/null
+/*
+ * jjPlus JWAP003 board support
+ *
+ */
+
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-eth.h"
+#include "dev-m25p80.h"
+#include "dev-gpio-buttons.h"
+#include "dev-usb.h"
+#include "machtypes.h"
+#include "pci.h"
+
+#define JWAP003_KEYS_POLL_INTERVAL 20 /* msecs */
+#define JWAP003_KEYS_DEBOUNCE_INTERVAL (3 * JWAP003_KEYS_POLL_INTERVAL)
+
+#define JWAP003_GPIO_WPS 11
+#define JWAP003_GPIO_I2C_SCL 0
+#define JWAP003_GPIO_I2C_SDA 1
+
+static struct gpio_keys_button jwap003_gpio_keys[] __initdata = {
+ {
+ .desc = "wps",
+ .type = EV_KEY,
+ .code = KEY_WPS_BUTTON,
+ .debounce_interval = JWAP003_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = JWAP003_GPIO_WPS,
+ .active_low = 1,
+ }
+};
+
+static struct i2c_gpio_platform_data jwap003_i2c_gpio_data = {
+ .sda_pin = JWAP003_GPIO_I2C_SDA,
+ .scl_pin = JWAP003_GPIO_I2C_SCL,
+};
+
+static struct platform_device jwap003_i2c_gpio_device = {
+ .name = "i2c-gpio",
+ .id = 0,
+ .dev = {
+ .platform_data = &jwap003_i2c_gpio_data,
+ }
+};
+
+static const char *jwap003_part_probes[] = {
+ "RedBoot",
+ NULL,
+};
+
+static struct flash_platform_data jwap003_flash_data = {
+ .part_probes = jwap003_part_probes,
+};
+
+#define JWAP003_WAN_PHYMASK BIT(0)
+#define JWAP003_LAN_PHYMASK BIT(4)
+
+static void __init jwap003_init(void)
+{
+ ath79_register_m25p80(&jwap003_flash_data);
+
+ ath79_register_mdio(0, 0x0);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
+ ath79_eth0_data.phy_mask = JWAP003_WAN_PHYMASK;
+ ath79_eth0_data.speed = SPEED_100;
+ ath79_eth0_data.duplex = DUPLEX_FULL;
+ ath79_eth0_data.has_ar8216 = 1;
+
+ ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
+ ath79_eth1_data.phy_mask = JWAP003_LAN_PHYMASK;
+ ath79_eth1_data.speed = SPEED_100;
+ ath79_eth1_data.duplex = DUPLEX_FULL;
+
+ ath79_register_eth(0);
+ ath79_register_eth(1);
+
+ platform_device_register(&jwap003_i2c_gpio_device);
+
+ ath79_register_usb();
+
+ ath79_register_gpio_keys_polled(-1, JWAP003_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(jwap003_gpio_keys),
+ jwap003_gpio_keys);
+
+ ath79_register_pci();
+}
+
+MIPS_MACHINE(ATH79_MACH_JWAP003, "JWAP003", "jjPlus JWAP003", jwap003_init);
--- /dev/null
+/*
+ * Planex MZK-W04NU board support
+ *
+ * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "dev-usb.h"
+#include "dev-wmac.h"
+#include "machtypes.h"
+
+#define MZK_W04NU_GPIO_LED_USB 0
+#define MZK_W04NU_GPIO_LED_STATUS 1
+#define MZK_W04NU_GPIO_LED_WPS 3
+#define MZK_W04NU_GPIO_LED_WLAN 6
+#define MZK_W04NU_GPIO_LED_AP 15
+#define MZK_W04NU_GPIO_LED_ROUTER 16
+
+#define MZK_W04NU_GPIO_BTN_APROUTER 5
+#define MZK_W04NU_GPIO_BTN_WPS 12
+#define MZK_W04NU_GPIO_BTN_RESET 21
+
+#define MZK_W04NU_KEYS_POLL_INTERVAL 20 /* msecs */
+#define MZK_W04NU_KEYS_DEBOUNCE_INTERVAL (3 * MZK_W04NU_KEYS_POLL_INTERVAL)
+
+static struct mtd_partition mzk_w04nu_partitions[] = {
+ {
+ .name = "u-boot",
+ .offset = 0,
+ .size = 0x040000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "u-boot-env",
+ .offset = 0x040000,
+ .size = 0x010000,
+ }, {
+ .name = "kernel",
+ .offset = 0x050000,
+ .size = 0x160000,
+ }, {
+ .name = "rootfs",
+ .offset = 0x1b0000,
+ .size = 0x630000,
+ }, {
+ .name = "art",
+ .offset = 0x7e0000,
+ .size = 0x020000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "firmware",
+ .offset = 0x050000,
+ .size = 0x790000,
+ }
+};
+
+static struct flash_platform_data mzk_w04nu_flash_data = {
+ .parts = mzk_w04nu_partitions,
+ .nr_parts = ARRAY_SIZE(mzk_w04nu_partitions),
+};
+
+static struct gpio_led mzk_w04nu_leds_gpio[] __initdata = {
+ {
+ .name = "planex:green:status",
+ .gpio = MZK_W04NU_GPIO_LED_STATUS,
+ .active_low = 1,
+ }, {
+ .name = "planex:blue:wps",
+ .gpio = MZK_W04NU_GPIO_LED_WPS,
+ .active_low = 1,
+ }, {
+ .name = "planex:green:wlan",
+ .gpio = MZK_W04NU_GPIO_LED_WLAN,
+ .active_low = 1,
+ }, {
+ .name = "planex:green:usb",
+ .gpio = MZK_W04NU_GPIO_LED_USB,
+ .active_low = 1,
+ }, {
+ .name = "planex:green:ap",
+ .gpio = MZK_W04NU_GPIO_LED_AP,
+ .active_low = 1,
+ }, {
+ .name = "planex:green:router",
+ .gpio = MZK_W04NU_GPIO_LED_ROUTER,
+ .active_low = 1,
+ }
+};
+
+static struct gpio_keys_button mzk_w04nu_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = MZK_W04NU_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = MZK_W04NU_GPIO_BTN_RESET,
+ .active_low = 1,
+ }, {
+ .desc = "wps",
+ .type = EV_KEY,
+ .code = KEY_WPS_BUTTON,
+ .debounce_interval = MZK_W04NU_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = MZK_W04NU_GPIO_BTN_WPS,
+ .active_low = 1,
+ }, {
+ .desc = "aprouter",
+ .type = EV_KEY,
+ .code = BTN_2,
+ .debounce_interval = MZK_W04NU_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = MZK_W04NU_GPIO_BTN_APROUTER,
+ .active_low = 0,
+ }
+};
+
+#define MZK_W04NU_WAN_PHYMASK BIT(4)
+#define MZK_W04NU_MDIO_MASK (~MZK_W04NU_WAN_PHYMASK)
+
+static void __init mzk_w04nu_setup(void)
+{
+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);
+
+ ath79_register_mdio(0, MZK_W04NU_MDIO_MASK);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, eeprom, 0);
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
+ ath79_eth0_data.speed = SPEED_100;
+ ath79_eth0_data.duplex = DUPLEX_FULL;
+ ath79_eth0_data.has_ar8216 = 1;
+
+ ath79_init_mac(ath79_eth1_data.mac_addr, eeprom, 1);
+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
+ ath79_eth1_data.phy_mask = MZK_W04NU_WAN_PHYMASK;
+
+ ath79_register_eth(0);
+ ath79_register_eth(1);
+
+ ath79_register_m25p80(&mzk_w04nu_flash_data);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(mzk_w04nu_leds_gpio),
+ mzk_w04nu_leds_gpio);
+
+ ath79_register_gpio_keys_polled(-1, MZK_W04NU_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(mzk_w04nu_gpio_keys),
+ mzk_w04nu_gpio_keys);
+ ath79_register_usb();
+
+ ath79_register_wmac(eeprom, NULL);
+}
+
+MIPS_MACHINE(ATH79_MACH_MZK_W04NU, "MZK-W04NU", "Planex MZK-W04NU",
+ mzk_w04nu_setup);
--- /dev/null
+/*
+ * Planex MZK-W300NH board support
+ *
+ * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "dev-wmac.h"
+#include "machtypes.h"
+
+#define MZK_W300NH_GPIO_LED_STATUS 1
+#define MZK_W300NH_GPIO_LED_WPS 3
+#define MZK_W300NH_GPIO_LED_WLAN 6
+#define MZK_W300NH_GPIO_LED_AP 15
+#define MZK_W300NH_GPIO_LED_ROUTER 16
+
+#define MZK_W300NH_GPIO_BTN_APROUTER 5
+#define MZK_W300NH_GPIO_BTN_WPS 12
+#define MZK_W300NH_GPIO_BTN_RESET 21
+
+#define MZK_W300NH_KEYS_POLL_INTERVAL 20 /* msecs */
+#define MZK_W300NH_KEYS_DEBOUNCE_INTERVAL (3 * MZK_W300NH_KEYS_POLL_INTERVAL)
+
+static struct mtd_partition mzk_w300nh_partitions[] = {
+ {
+ .name = "u-boot",
+ .offset = 0,
+ .size = 0x040000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "u-boot-env",
+ .offset = 0x040000,
+ .size = 0x010000,
+ }, {
+ .name = "kernel",
+ .offset = 0x050000,
+ .size = 0x160000,
+ }, {
+ .name = "rootfs",
+ .offset = 0x1b0000,
+ .size = 0x630000,
+ }, {
+ .name = "art",
+ .offset = 0x7e0000,
+ .size = 0x020000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "firmware",
+ .offset = 0x050000,
+ .size = 0x790000,
+ }
+};
+
+static struct flash_platform_data mzk_w300nh_flash_data = {
+ .parts = mzk_w300nh_partitions,
+ .nr_parts = ARRAY_SIZE(mzk_w300nh_partitions),
+};
+
+static struct gpio_led mzk_w300nh_leds_gpio[] __initdata = {
+ {
+ .name = "planex:green:status",
+ .gpio = MZK_W300NH_GPIO_LED_STATUS,
+ .active_low = 1,
+ }, {
+ .name = "planex:blue:wps",
+ .gpio = MZK_W300NH_GPIO_LED_WPS,
+ .active_low = 1,
+ }, {
+ .name = "planex:green:wlan",
+ .gpio = MZK_W300NH_GPIO_LED_WLAN,
+ .active_low = 1,
+ }, {
+ .name = "planex:green:ap",
+ .gpio = MZK_W300NH_GPIO_LED_AP,
+ .active_low = 1,
+ }, {
+ .name = "planex:green:router",
+ .gpio = MZK_W300NH_GPIO_LED_ROUTER,
+ .active_low = 1,
+ }
+};
+
+static struct gpio_keys_button mzk_w300nh_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = MZK_W300NH_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = MZK_W300NH_GPIO_BTN_RESET,
+ .active_low = 1,
+ }, {
+ .desc = "wps",
+ .type = EV_KEY,
+ .code = KEY_WPS_BUTTON,
+ .debounce_interval = MZK_W300NH_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = MZK_W300NH_GPIO_BTN_WPS,
+ .active_low = 1,
+ }, {
+ .desc = "aprouter",
+ .type = EV_KEY,
+ .code = BTN_2,
+ .debounce_interval = MZK_W300NH_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = MZK_W300NH_GPIO_BTN_APROUTER,
+ .active_low = 0,
+ }
+};
+
+#define MZK_W300NH_WAN_PHYMASK BIT(4)
+#define MZK_W300NH_MDIO_MASK (~MZK_W300NH_WAN_PHYMASK)
+
+static void __init mzk_w300nh_setup(void)
+{
+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);
+
+ ath79_register_mdio(0, MZK_W300NH_MDIO_MASK);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, eeprom, 0);
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
+ ath79_eth0_data.speed = SPEED_100;
+ ath79_eth0_data.duplex = DUPLEX_FULL;
+ ath79_eth0_data.has_ar8216 = 1;
+
+ ath79_init_mac(ath79_eth1_data.mac_addr, eeprom, 1);
+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
+ ath79_eth1_data.phy_mask = MZK_W300NH_WAN_PHYMASK;
+
+ ath79_register_eth(0);
+ ath79_register_eth(1);
+
+ ath79_register_m25p80(&mzk_w300nh_flash_data);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(mzk_w300nh_leds_gpio),
+ mzk_w300nh_leds_gpio);
+
+ ath79_register_gpio_keys_polled(-1, MZK_W300NH_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(mzk_w300nh_gpio_keys),
+ mzk_w300nh_gpio_keys);
+ ath79_register_wmac(eeprom, NULL);
+}
+
+MIPS_MACHINE(ATH79_MACH_MZK_W300NH, "MZK-W300NH", "Planex MZK-W300NH",
+ mzk_w300nh_setup);
--- /dev/null
+/*
+ * Zyxel NBG 460N/550N/550NH board support
+ *
+ * Copyright (C) 2010 Michael Kurz <michi.kurz@googlemail.com>
+ *
+ * based on mach-tl-wr1043nd.c
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/i2c-algo-bit.h>
+#include <linux/i2c-gpio.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/platform_device.h>
+#include <linux/rtl8366.h>
+
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "dev-wmac.h"
+#include "machtypes.h"
+
+/* LEDs */
+#define NBG460N_GPIO_LED_WPS 3
+#define NBG460N_GPIO_LED_WAN 6
+#define NBG460N_GPIO_LED_POWER 14
+#define NBG460N_GPIO_LED_WLAN 15
+
+/* Buttons */
+#define NBG460N_GPIO_BTN_WPS 12
+#define NBG460N_GPIO_BTN_RESET 21
+
+#define NBG460N_KEYS_POLL_INTERVAL 20 /* msecs */
+#define NBG460N_KEYS_DEBOUNCE_INTERVAL (3 * NBG460N_KEYS_POLL_INTERVAL)
+
+/* RTC chip PCF8563 I2C interface */
+#define NBG460N_GPIO_PCF8563_SDA 8
+#define NBG460N_GPIO_PCF8563_SCK 7
+
+/* Switch configuration I2C interface */
+#define NBG460N_GPIO_RTL8366_SDA 16
+#define NBG460N_GPIO_RTL8366_SCK 18
+
+static struct mtd_partition nbg460n_partitions[] = {
+ {
+ .name = "Bootbase",
+ .offset = 0,
+ .size = 0x010000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "U-Boot Config",
+ .offset = 0x010000,
+ .size = 0x030000,
+ }, {
+ .name = "U-Boot",
+ .offset = 0x040000,
+ .size = 0x030000,
+ }, {
+ .name = "linux",
+ .offset = 0x070000,
+ .size = 0x0e0000,
+ }, {
+ .name = "rootfs",
+ .offset = 0x150000,
+ .size = 0x2a0000,
+ }, {
+ .name = "CalibData",
+ .offset = 0x3f0000,
+ .size = 0x010000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "firmware",
+ .offset = 0x070000,
+ .size = 0x380000,
+ }
+};
+
+static struct flash_platform_data nbg460n_flash_data = {
+ .parts = nbg460n_partitions,
+ .nr_parts = ARRAY_SIZE(nbg460n_partitions),
+};
+
+static struct gpio_led nbg460n_leds_gpio[] __initdata = {
+ {
+ .name = "nbg460n:green:power",
+ .gpio = NBG460N_GPIO_LED_POWER,
+ .active_low = 0,
+ .default_trigger = "default-on",
+ }, {
+ .name = "nbg460n:green:wps",
+ .gpio = NBG460N_GPIO_LED_WPS,
+ .active_low = 0,
+ }, {
+ .name = "nbg460n:green:wlan",
+ .gpio = NBG460N_GPIO_LED_WLAN,
+ .active_low = 0,
+ }, {
+ /* Not really for controlling the LED,
+ when set low the LED blinks uncontrollable */
+ .name = "nbg460n:green:wan",
+ .gpio = NBG460N_GPIO_LED_WAN,
+ .active_low = 0,
+ }
+};
+
+static struct gpio_keys_button nbg460n_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = NBG460N_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = NBG460N_GPIO_BTN_RESET,
+ .active_low = 1,
+ }, {
+ .desc = "wps",
+ .type = EV_KEY,
+ .code = KEY_WPS_BUTTON,
+ .debounce_interval = NBG460N_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = NBG460N_GPIO_BTN_WPS,
+ .active_low = 1,
+ }
+};
+
+static struct i2c_gpio_platform_data nbg460n_i2c_device_platdata = {
+ .sda_pin = NBG460N_GPIO_PCF8563_SDA,
+ .scl_pin = NBG460N_GPIO_PCF8563_SCK,
+ .udelay = 10,
+};
+
+static struct platform_device nbg460n_i2c_device = {
+ .name = "i2c-gpio",
+ .id = -1,
+ .num_resources = 0,
+ .resource = NULL,
+ .dev = {
+ .platform_data = &nbg460n_i2c_device_platdata,
+ },
+};
+
+static struct i2c_board_info nbg460n_i2c_devs[] __initdata = {
+ {
+ I2C_BOARD_INFO("pcf8563", 0x51),
+ },
+};
+
+static void __devinit nbg460n_i2c_init(void)
+{
+ /* The gpio interface */
+ platform_device_register(&nbg460n_i2c_device);
+ /* I2C devices */
+ i2c_register_board_info(0, nbg460n_i2c_devs,
+ ARRAY_SIZE(nbg460n_i2c_devs));
+}
+
+
+static struct rtl8366_platform_data nbg460n_rtl8366s_data = {
+ .gpio_sda = NBG460N_GPIO_RTL8366_SDA,
+ .gpio_sck = NBG460N_GPIO_RTL8366_SCK,
+};
+
+static struct platform_device nbg460n_rtl8366s_device = {
+ .name = RTL8366S_DRIVER_NAME,
+ .id = -1,
+ .dev = {
+ .platform_data = &nbg460n_rtl8366s_data,
+ }
+};
+
+static void __init nbg460n_setup(void)
+{
+ /* end of bootloader sector contains mac address */
+ u8 *mac = (u8 *) KSEG1ADDR(0x1fc0fff8);
+ /* last sector contains wlan calib data */
+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);
+
+ /* LAN Port */
+ ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
+ ath79_eth0_data.mii_bus_dev = &nbg460n_rtl8366s_device.dev;
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+ ath79_eth0_data.speed = SPEED_1000;
+ ath79_eth0_data.duplex = DUPLEX_FULL;
+
+ /* WAN Port */
+ ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
+ ath79_eth1_data.mii_bus_dev = &nbg460n_rtl8366s_device.dev;
+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+ ath79_eth1_data.phy_mask = 0x10;
+
+ ath79_register_eth(0);
+ ath79_register_eth(1);
+
+ /* register the switch phy */
+ platform_device_register(&nbg460n_rtl8366s_device);
+
+ /* register flash */
+ ath79_register_m25p80(&nbg460n_flash_data);
+
+ ath79_register_wmac(eeprom, mac);
+
+ /* register RTC chip */
+ nbg460n_i2c_init();
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(nbg460n_leds_gpio),
+ nbg460n_leds_gpio);
+
+ ath79_register_gpio_keys_polled(-1, NBG460N_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(nbg460n_gpio_keys),
+ nbg460n_gpio_keys);
+}
+
+MIPS_MACHINE(ATH79_MACH_NBG460N, "NBG460N", "Zyxel NBG460N/550N/550NH",
+ nbg460n_setup);
--- /dev/null
+/*
+ * OpenMesh OM2P support
+ *
+ * Copyright (C) 2011 Marek Lindner <marek@open-mesh.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach-ath79/ar71xx_regs.h>
+#include <asm/mach-ath79/ath79.h>
+
+#include "common.h"
+#include "dev-ap9x-pci.h"
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "machtypes.h"
+
+#define OM2P_GPIO_LED_POWER 0
+#define OM2P_GPIO_LED_GREEN 13
+#define OM2P_GPIO_LED_RED 14
+#define OM2P_GPIO_LED_YELLOW 15
+#define OM2P_GPIO_LED_LAN 16
+#define OM2P_GPIO_LED_WAN 17
+#define OM2P_GPIO_BTN_RESET 11
+
+#define OM2P_KEYS_POLL_INTERVAL 20 /* msecs */
+#define OM2P_KEYS_DEBOUNCE_INTERVAL (3 * OM2P_KEYS_POLL_INTERVAL)
+
+#define OM2P_WAN_PHYMASK BIT(4)
+
+static struct flash_platform_data om2p_flash_data = {
+ .type = "s25sl12800",
+ .name = "ar7240-nor0",
+};
+
+static struct gpio_led om2p_leds_gpio[] __initdata = {
+ {
+ .name = "om2p:blue:power",
+ .gpio = OM2P_GPIO_LED_POWER,
+ .active_low = 1,
+ }, {
+ .name = "om2p:red:wifi",
+ .gpio = OM2P_GPIO_LED_RED,
+ .active_low = 1,
+ }, {
+ .name = "om2p:yellow:wifi",
+ .gpio = OM2P_GPIO_LED_YELLOW,
+ .active_low = 1,
+ }, {
+ .name = "om2p:green:wifi",
+ .gpio = OM2P_GPIO_LED_GREEN,
+ .active_low = 1,
+ }, {
+ .name = "om2p:blue:lan",
+ .gpio = OM2P_GPIO_LED_LAN,
+ .active_low = 1,
+ }, {
+ .name = "om2p:blue:wan",
+ .gpio = OM2P_GPIO_LED_WAN,
+ .active_low = 1,
+ }
+};
+
+static struct gpio_keys_button om2p_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = OM2P_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = OM2P_GPIO_BTN_RESET,
+ .active_low = 1,
+ }
+};
+
+static void __init om2p_setup(void)
+{
+ u8 *mac1 = (u8 *)KSEG1ADDR(0x1ffc0000);
+ u8 *mac2 = (u8 *)KSEG1ADDR(0x1ffc0000 + ETH_ALEN);
+ u8 *ee = (u8 *)KSEG1ADDR(0x1ffc1000);
+
+ ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
+ AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
+ AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
+ AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
+ AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
+
+ ath79_register_m25p80(&om2p_flash_data);
+
+ ath79_register_mdio(0, ~OM2P_WAN_PHYMASK);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
+ ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
+
+ ath79_register_eth(0);
+ ath79_register_eth(1);
+
+ ap91_pci_init(ee, NULL);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(om2p_leds_gpio),
+ om2p_leds_gpio);
+
+ ath79_register_gpio_keys_polled(-1, OM2P_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(om2p_gpio_keys),
+ om2p_gpio_keys);
+}
+
+MIPS_MACHINE(ATH79_MACH_OM2P, "OM2P", "OpenMesh OM2P", om2p_setup);
--- /dev/null
+/*
+ * Atheros PB42 board support
+ *
+ * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-m25p80.h"
+#include "dev-usb.h"
+#include "machtypes.h"
+#include "pci.h"
+
+#define PB42_KEYS_POLL_INTERVAL 20 /* msecs */
+#define PB42_KEYS_DEBOUNCE_INTERVAL (3 * PB42_KEYS_POLL_INTERVAL)
+
+#define PB42_GPIO_BTN_SW4 8
+#define PB42_GPIO_BTN_SW5 3
+
+static struct gpio_keys_button pb42_gpio_keys[] __initdata = {
+ {
+ .desc = "sw4",
+ .type = EV_KEY,
+ .code = BTN_0,
+ .debounce_interval = PB42_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = PB42_GPIO_BTN_SW4,
+ .active_low = 1,
+ }, {
+ .desc = "sw5",
+ .type = EV_KEY,
+ .code = BTN_1,
+ .debounce_interval = PB42_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = PB42_GPIO_BTN_SW5,
+ .active_low = 1,
+ }
+};
+
+static const char *pb42_part_probes[] = {
+ "RedBoot",
+ NULL,
+};
+
+static struct flash_platform_data pb42_flash_data = {
+ .part_probes = pb42_part_probes,
+};
+
+#define PB42_WAN_PHYMASK BIT(20)
+#define PB42_LAN_PHYMASK (BIT(16) | BIT(17) | BIT(18) | BIT(19))
+#define PB42_MDIO_PHYMASK (PB42_LAN_PHYMASK | PB42_WAN_PHYMASK)
+
+static void __init pb42_init(void)
+{
+ ath79_register_m25p80(&pb42_flash_data);
+
+ ath79_register_mdio(0, ~PB42_MDIO_PHYMASK);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
+ ath79_eth0_data.phy_mask = PB42_WAN_PHYMASK;
+
+ ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
+ ath79_eth1_data.speed = SPEED_100;
+ ath79_eth1_data.duplex = DUPLEX_FULL;
+
+ ath79_register_eth(0);
+ ath79_register_eth(1);
+
+ ath79_register_gpio_keys_polled(-1, PB42_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(pb42_gpio_keys),
+ pb42_gpio_keys);
+
+ ath79_register_pci();
+}
+
+MIPS_MACHINE(ATH79_MACH_PB42, "PB42", "Atheros PB42", pb42_init);
--- /dev/null
+/*
+ * Atheros PB92 board support
+ *
+ * Copyright (C) 2010 Felix Fietkau <nbd@openwrt.org>
+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-m25p80.h"
+#include "dev-usb.h"
+#include "machtypes.h"
+#include "pci.h"
+
+static struct mtd_partition pb92_partitions[] = {
+ {
+ .name = "u-boot",
+ .offset = 0,
+ .size = 0x040000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "u-boot-env",
+ .offset = 0x040000,
+ .size = 0x010000,
+ }, {
+ .name = "rootfs",
+ .offset = 0x050000,
+ .size = 0x2b0000,
+ }, {
+ .name = "uImage",
+ .offset = 0x300000,
+ .size = 0x0e0000,
+ }, {
+ .name = "ART",
+ .offset = 0x3e0000,
+ .size = 0x020000,
+ .mask_flags = MTD_WRITEABLE,
+ }
+};
+
+static struct flash_platform_data pb92_flash_data = {
+ .parts = pb92_partitions,
+ .nr_parts = ARRAY_SIZE(pb92_partitions),
+};
+
+#define PB92_KEYS_POLL_INTERVAL 20 /* msecs */
+#define PB92_KEYS_DEBOUNCE_INTERVAL (3 * PB92_KEYS_POLL_INTERVAL)
+
+#define PB92_GPIO_BTN_SW4 8
+#define PB92_GPIO_BTN_SW5 3
+
+static struct gpio_keys_button pb92_gpio_keys[] __initdata = {
+ {
+ .desc = "sw4",
+ .type = EV_KEY,
+ .code = BTN_0,
+ .debounce_interval = PB92_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = PB92_GPIO_BTN_SW4,
+ .active_low = 1,
+ }, {
+ .desc = "sw5",
+ .type = EV_KEY,
+ .code = BTN_1,
+ .debounce_interval = PB92_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = PB92_GPIO_BTN_SW5,
+ .active_low = 1,
+ }
+};
+
+static void __init pb92_init(void)
+{
+ u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000);
+
+ ath79_register_m25p80(&pb92_flash_data);
+
+ ath79_register_mdio(0, ~BIT(0));
+ ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+ ath79_eth0_data.speed = SPEED_1000;
+ ath79_eth0_data.duplex = DUPLEX_FULL;
+ ath79_eth0_data.phy_mask = BIT(0);
+
+ ath79_register_eth(0);
+
+ ath79_register_gpio_keys_polled(-1, PB92_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(pb92_gpio_keys),
+ pb92_gpio_keys);
+
+ ath79_register_pci();
+}
+
+MIPS_MACHINE(ATH79_MACH_PB92, "PB92", "Atheros PB92", pb92_init);
--- /dev/null
+/*
+ * MikroTik RouterBOARD 4xx series support
+ *
+ * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/mdio-gpio.h>
+#include <linux/mmc/host.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/mmc_spi.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach-ath79/ar71xx_regs.h>
+#include <asm/mach-ath79/ath79.h>
+#include <asm/mach-ath79/pci.h>
+#include <asm/mach-ath79/rb4xx_cpld.h>
+
+#include "common.h"
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-usb.h"
+#include "machtypes.h"
+#include "pci.h"
+
+#define RB4XX_GPIO_USER_LED 4
+#define RB4XX_GPIO_RESET_SWITCH 7
+
+#define RB4XX_GPIO_CPLD_BASE 32
+#define RB4XX_GPIO_CPLD_LED1 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED1)
+#define RB4XX_GPIO_CPLD_LED2 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED2)
+#define RB4XX_GPIO_CPLD_LED3 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED3)
+#define RB4XX_GPIO_CPLD_LED4 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED4)
+#define RB4XX_GPIO_CPLD_LED5 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED5)
+
+#define RB4XX_KEYS_POLL_INTERVAL 20 /* msecs */
+#define RB4XX_KEYS_DEBOUNCE_INTERVAL (3 * RB4XX_KEYS_POLL_INTERVAL)
+
+static struct gpio_led rb4xx_leds_gpio[] __initdata = {
+ {
+ .name = "rb4xx:yellow:user",
+ .gpio = RB4XX_GPIO_USER_LED,
+ .active_low = 0,
+ }, {
+ .name = "rb4xx:green:led1",
+ .gpio = RB4XX_GPIO_CPLD_LED1,
+ .active_low = 1,
+ }, {
+ .name = "rb4xx:green:led2",
+ .gpio = RB4XX_GPIO_CPLD_LED2,
+ .active_low = 1,
+ }, {
+ .name = "rb4xx:green:led3",
+ .gpio = RB4XX_GPIO_CPLD_LED3,
+ .active_low = 1,
+ }, {
+ .name = "rb4xx:green:led4",
+ .gpio = RB4XX_GPIO_CPLD_LED4,
+ .active_low = 1,
+ }, {
+ .name = "rb4xx:green:led5",
+ .gpio = RB4XX_GPIO_CPLD_LED5,
+ .active_low = 0,
+ },
+};
+
+static struct gpio_keys_button rb4xx_gpio_keys[] __initdata = {
+ {
+ .desc = "reset_switch",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = RB4XX_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = RB4XX_GPIO_RESET_SWITCH,
+ .active_low = 1,
+ }
+};
+
+static struct platform_device rb4xx_nand_device = {
+ .name = "rb4xx-nand",
+ .id = -1,
+};
+
+static struct ath79_pci_irq rb4xx_pci_irqs[] __initdata = {
+ {
+ .slot = 17,
+ .pin = 1,
+ .irq = ATH79_PCI_IRQ(2),
+ }, {
+ .slot = 18,
+ .pin = 1,
+ .irq = ATH79_PCI_IRQ(0),
+ }, {
+ .slot = 18,
+ .pin = 2,
+ .irq = ATH79_PCI_IRQ(1),
+ }, {
+ .slot = 19,
+ .pin = 1,
+ .irq = ATH79_PCI_IRQ(1),
+ }, {
+ .slot = 19,
+ .pin = 1,
+ .irq = ATH79_PCI_IRQ(2),
+ }
+};
+
+static struct mtd_partition rb4xx_partitions[] = {
+ {
+ .name = "routerboot",
+ .offset = 0,
+ .size = 0x0b000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "hard_config",
+ .offset = 0x0b000,
+ .size = 0x01000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "bios",
+ .offset = 0x0d000,
+ .size = 0x02000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "soft_config",
+ .offset = 0x0f000,
+ .size = 0x01000,
+ }
+};
+
+static struct flash_platform_data rb4xx_flash_data = {
+ .type = "pm25lv512",
+ .parts = rb4xx_partitions,
+ .nr_parts = ARRAY_SIZE(rb4xx_partitions),
+};
+
+static struct rb4xx_cpld_platform_data rb4xx_cpld_data = {
+ .gpio_base = RB4XX_GPIO_CPLD_BASE,
+};
+
+static struct mmc_spi_platform_data rb4xx_mmc_data = {
+ .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
+};
+
+static struct spi_board_info rb4xx_spi_info[] = {
+ {
+ .bus_num = 0,
+ .chip_select = 0,
+ .max_speed_hz = 25000000,
+ .modalias = "m25p80",
+ .platform_data = &rb4xx_flash_data,
+ }, {
+ .bus_num = 0,
+ .chip_select = 1,
+ .max_speed_hz = 25000000,
+ .modalias = "spi-rb4xx-cpld",
+ .platform_data = &rb4xx_cpld_data,
+ }
+};
+
+static struct spi_board_info rb4xx_microsd_info[] = {
+ {
+ .bus_num = 0,
+ .chip_select = 2,
+ .max_speed_hz = 25000000,
+ .modalias = "mmc_spi",
+ .platform_data = &rb4xx_mmc_data,
+ }
+};
+
+
+static struct resource rb4xx_spi_resources[] = {
+ {
+ .start = AR71XX_SPI_BASE,
+ .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device rb4xx_spi_device = {
+ .name = "rb4xx-spi",
+ .id = -1,
+ .resource = rb4xx_spi_resources,
+ .num_resources = ARRAY_SIZE(rb4xx_spi_resources),
+};
+
+static void __init rb4xx_generic_setup(void)
+{
+ ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN |
+ AR71XX_GPIO_FUNC_SPI_CS2_EN);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(rb4xx_leds_gpio),
+ rb4xx_leds_gpio);
+
+ ath79_register_gpio_keys_polled(-1, RB4XX_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(rb4xx_gpio_keys),
+ rb4xx_gpio_keys);
+
+ spi_register_board_info(rb4xx_spi_info, ARRAY_SIZE(rb4xx_spi_info));
+ platform_device_register(&rb4xx_spi_device);
+ platform_device_register(&rb4xx_nand_device);
+}
+
+static void __init rb411_setup(void)
+{
+ rb4xx_generic_setup();
+ spi_register_board_info(rb4xx_microsd_info,
+ ARRAY_SIZE(rb4xx_microsd_info));
+
+ ath79_register_mdio(0, 0xfffffffc);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
+ ath79_eth0_data.phy_mask = 0x00000003;
+
+ ath79_register_eth(0);
+
+ ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
+ ath79_register_pci();
+}
+
+MIPS_MACHINE(ATH79_MACH_RB_411, "411", "MikroTik RouterBOARD 411/A/AH",
+ rb411_setup);
+
+static void __init rb411u_setup(void)
+{
+ rb411_setup();
+ ath79_register_usb();
+}
+
+MIPS_MACHINE(ATH79_MACH_RB_411U, "411U", "MikroTik RouterBOARD 411U",
+ rb411u_setup);
+
+#define RB433_LAN_PHYMASK BIT(0)
+#define RB433_WAN_PHYMASK BIT(4)
+#define RB433_MDIO_PHYMASK (RB433_LAN_PHYMASK | RB433_WAN_PHYMASK)
+
+static void __init rb433_setup(void)
+{
+ rb4xx_generic_setup();
+ spi_register_board_info(rb4xx_microsd_info,
+ ARRAY_SIZE(rb4xx_microsd_info));
+
+ ath79_register_mdio(0, ~RB433_MDIO_PHYMASK);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 1);
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
+ ath79_eth0_data.phy_mask = RB433_LAN_PHYMASK;
+
+ ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0);
+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
+ ath79_eth1_data.phy_mask = RB433_WAN_PHYMASK;
+
+ ath79_register_eth(1);
+ ath79_register_eth(0);
+
+ ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
+ ath79_register_pci();
+}
+
+MIPS_MACHINE(ATH79_MACH_RB_433, "433", "MikroTik RouterBOARD 433/AH",
+ rb433_setup);
+
+static void __init rb433u_setup(void)
+{
+ rb433_setup();
+ ath79_register_usb();
+}
+
+MIPS_MACHINE(ATH79_MACH_RB_433U, "433U", "MikroTik RouterBOARD 433UAH",
+ rb433u_setup);
+
+#define RB450_LAN_PHYMASK BIT(0)
+#define RB450_WAN_PHYMASK BIT(4)
+#define RB450_MDIO_PHYMASK (RB450_LAN_PHYMASK | RB450_WAN_PHYMASK)
+
+static void __init rb450_generic_setup(int gige)
+{
+ rb4xx_generic_setup();
+ ath79_register_mdio(0, ~RB450_MDIO_PHYMASK);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 1);
+ ath79_eth0_data.phy_if_mode = (gige) ?
+ PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_MII;
+ ath79_eth0_data.phy_mask = RB450_LAN_PHYMASK;
+
+ ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0);
+ ath79_eth1_data.phy_if_mode = (gige) ?
+ PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_RMII;
+ ath79_eth1_data.phy_mask = RB450_WAN_PHYMASK;
+
+ ath79_register_eth(1);
+ ath79_register_eth(0);
+}
+
+static void __init rb450_setup(void)
+{
+ rb450_generic_setup(0);
+}
+
+MIPS_MACHINE(ATH79_MACH_RB_450, "450", "MikroTik RouterBOARD 450",
+ rb450_setup);
+
+static void __init rb450g_setup(void)
+{
+ rb450_generic_setup(1);
+ spi_register_board_info(rb4xx_microsd_info,
+ ARRAY_SIZE(rb4xx_microsd_info));
+}
+
+MIPS_MACHINE(ATH79_MACH_RB_450G, "450G", "MikroTik RouterBOARD 450G",
+ rb450g_setup);
+
+static void __init rb493_setup(void)
+{
+ rb4xx_generic_setup();
+
+ ath79_register_mdio(0, 0x3fffff00);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
+ ath79_eth0_data.speed = SPEED_100;
+ ath79_eth0_data.duplex = DUPLEX_FULL;
+
+ ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
+ ath79_eth1_data.phy_mask = 0x00000001;
+
+ ath79_register_eth(0);
+ ath79_register_eth(1);
+
+ ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
+ ath79_register_pci();
+}
+
+MIPS_MACHINE(ATH79_MACH_RB_493, "493", "MikroTik RouterBOARD 493/AH",
+ rb493_setup);
+
+#define RB493G_GPIO_MDIO_MDC 7
+#define RB493G_GPIO_MDIO_DATA 8
+
+#define RB493G_MDIO_PHYMASK BIT(0)
+
+static struct mdio_gpio_platform_data rb493g_mdio_data = {
+ .mdc = RB493G_GPIO_MDIO_MDC,
+ .mdio = RB493G_GPIO_MDIO_DATA,
+
+ .phy_mask = ~RB493G_MDIO_PHYMASK,
+};
+
+static struct platform_device rb493g_mdio_device = {
+ .name = "mdio-gpio",
+ .id = -1,
+ .dev = {
+ .platform_data = &rb493g_mdio_data,
+ },
+};
+
+static void __init rb493g_setup(void)
+{
+ ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN |
+ AR71XX_GPIO_FUNC_SPI_CS2_EN);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(rb4xx_leds_gpio),
+ rb4xx_leds_gpio);
+
+ spi_register_board_info(rb4xx_spi_info, ARRAY_SIZE(rb4xx_spi_info));
+ platform_device_register(&rb4xx_spi_device);
+ platform_device_register(&rb4xx_nand_device);
+
+ ath79_register_mdio(0, ~RB493G_MDIO_PHYMASK);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+ ath79_eth0_data.phy_mask = RB493G_MDIO_PHYMASK;
+ ath79_eth0_data.speed = SPEED_1000;
+ ath79_eth0_data.duplex = DUPLEX_FULL;
+
+ ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+ ath79_eth1_data.mii_bus_dev = &rb493g_mdio_device.dev;
+ ath79_eth1_data.phy_mask = RB493G_MDIO_PHYMASK;
+ ath79_eth1_data.speed = SPEED_1000;
+ ath79_eth1_data.duplex = DUPLEX_FULL;
+
+ platform_device_register(&rb493g_mdio_device);
+
+ ath79_register_eth(1);
+ ath79_register_eth(0);
+
+ ath79_register_usb();
+
+ ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
+ ath79_register_pci();
+}
+
+MIPS_MACHINE(ATH79_MACH_RB_493G, "493G", "MikroTik RouterBOARD 493G",
+ rb493g_setup);
--- /dev/null
+/*
+ * MikroTik RouterBOARD 750 support
+ *
+ * Copyright (C) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/export.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach-ath79/ar71xx_regs.h>
+#include <asm/mach-ath79/ath79.h>
+#include <asm/mach-ath79/mach-rb750.h>
+
+#include "common.h"
+#include "dev-eth.h"
+#include "machtypes.h"
+
+static struct rb750_led_data rb750_leds[] = {
+ {
+ .name = "rb750:green:act",
+ .mask = RB750_LED_ACT,
+ .active_low = 1,
+ }, {
+ .name = "rb750:green:port1",
+ .mask = RB750_LED_PORT5,
+ .active_low = 1,
+ }, {
+ .name = "rb750:green:port2",
+ .mask = RB750_LED_PORT4,
+ .active_low = 1,
+ }, {
+ .name = "rb750:green:port3",
+ .mask = RB750_LED_PORT3,
+ .active_low = 1,
+ }, {
+ .name = "rb750:green:port4",
+ .mask = RB750_LED_PORT2,
+ .active_low = 1,
+ }, {
+ .name = "rb750:green:port5",
+ .mask = RB750_LED_PORT1,
+ .active_low = 1,
+ }
+};
+
+static struct rb750_led_platform_data rb750_leds_data = {
+ .num_leds = ARRAY_SIZE(rb750_leds),
+ .leds = rb750_leds,
+};
+
+static struct platform_device rb750_leds_device = {
+ .name = "leds-rb750",
+ .dev = {
+ .platform_data = &rb750_leds_data,
+ }
+};
+
+static struct platform_device rb750_nand_device = {
+ .name = "rb750-nand",
+ .id = -1,
+};
+
+int rb750_latch_change(u32 mask_clr, u32 mask_set)
+{
+ static DEFINE_SPINLOCK(lock);
+ static u32 latch_set = RB750_LED_BITS | RB750_LVC573_LE;
+ static u32 latch_oe;
+ static u32 latch_clr;
+ unsigned long flags;
+ u32 t;
+ int ret = 0;
+
+ spin_lock_irqsave(&lock, flags);
+
+ if ((mask_clr & BIT(31)) != 0 &&
+ (latch_set & RB750_LVC573_LE) == 0) {
+ goto unlock;
+ }
+
+ latch_set = (latch_set | mask_set) & ~mask_clr;
+ latch_clr = (latch_clr | mask_clr) & ~mask_set;
+
+ if (latch_oe == 0)
+ latch_oe = __raw_readl(ath79_gpio_base + AR71XX_GPIO_REG_OE);
+
+ if (likely(latch_set & RB750_LVC573_LE)) {
+ void __iomem *base = ath79_gpio_base;
+
+ t = __raw_readl(base + AR71XX_GPIO_REG_OE);
+ t |= mask_clr | latch_oe | mask_set;
+
+ __raw_writel(t, base + AR71XX_GPIO_REG_OE);
+ __raw_writel(latch_clr, base + AR71XX_GPIO_REG_CLEAR);
+ __raw_writel(latch_set, base + AR71XX_GPIO_REG_SET);
+ } else if (mask_clr & RB750_LVC573_LE) {
+ void __iomem *base = ath79_gpio_base;
+
+ latch_oe = __raw_readl(base + AR71XX_GPIO_REG_OE);
+ __raw_writel(RB750_LVC573_LE, base + AR71XX_GPIO_REG_CLEAR);
+ /* flush write */
+ __raw_readl(base + AR71XX_GPIO_REG_CLEAR);
+ }
+
+ ret = 1;
+
+unlock:
+ spin_unlock_irqrestore(&lock, flags);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(rb750_latch_change);
+
+void rb750_nand_pins_enable(void)
+{
+ ath79_gpio_function_setup(AR724X_GPIO_FUNC_JTAG_DISABLE,
+ AR724X_GPIO_FUNC_SPI_EN);
+}
+EXPORT_SYMBOL_GPL(rb750_nand_pins_enable);
+
+void rb750_nand_pins_disable(void)
+{
+ ath79_gpio_function_setup(AR724X_GPIO_FUNC_SPI_EN,
+ AR724X_GPIO_FUNC_JTAG_DISABLE);
+}
+EXPORT_SYMBOL_GPL(rb750_nand_pins_disable);
+
+static void __init rb750_setup(void)
+{
+ ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
+ AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
+ AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
+ AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
+ AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
+ ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
+
+ ath79_register_mdio(0, 0x0);
+
+ /* LAN ports */
+ ath79_register_eth(1);
+
+ /* WAN port */
+ ath79_register_eth(0);
+
+ platform_device_register(&rb750_leds_device);
+ platform_device_register(&rb750_nand_device);
+}
+
+MIPS_MACHINE(ATH79_MACH_RB_750, "750i", "MikroTik RouterBOARD 750",
+ rb750_setup);
--- /dev/null
+/*
+ * Redwave RW2458N support
+ *
+ * Copyright (C) 2011-2012 Cezary Jackiewicz <cezary@eko.one.pl>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-eth.h"
+#include "dev-ap9x-pci.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "dev-usb.h"
+#include "machtypes.h"
+
+#define RW2458N_GPIO_LED_D3 1
+#define RW2458N_GPIO_LED_D4 0
+#define RW2458N_GPIO_LED_D5 11
+#define RW2458N_GPIO_LED_D6 7
+#define RW2458N_GPIO_BTN_RESET 12
+
+#define RW2458N_KEYS_POLL_INTERVAL 20 /* msecs */
+#define RW2458N_KEYS_DEBOUNCE_INTERVAL (3 * RW2458N_KEYS_POLL_INTERVAL)
+
+static struct gpio_keys_button rw2458n_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = RW2458N_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = RW2458N_GPIO_BTN_RESET,
+ .active_low = 1,
+ }
+};
+
+#define RW2458N_WAN_PHYMASK BIT(4)
+
+static struct gpio_led rw2458n_leds_gpio[] __initdata = {
+ {
+ .name = "rw2458n:green:d3",
+ .gpio = RW2458N_GPIO_LED_D3,
+ .active_low = 1,
+ }, {
+ .name = "rw2458n:green:d4",
+ .gpio = RW2458N_GPIO_LED_D4,
+ .active_low = 1,
+ }, {
+ .name = "rw2458n:green:d5",
+ .gpio = RW2458N_GPIO_LED_D5,
+ .active_low = 1,
+ }, {
+ .name = "rw2458n:green:d6",
+ .gpio = RW2458N_GPIO_LED_D6,
+ .active_low = 1,
+ }
+};
+
+static const char *rw2458n_part_probes[] = {
+ "RedBoot",
+ NULL,
+};
+
+static struct flash_platform_data rw2458n_flash_data = {
+ .part_probes = rw2458n_part_probes,
+};
+
+static void __init rw2458n_setup(void)
+{
+ u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000);
+ u8 *mac2 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN);
+ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
+
+ ath79_register_m25p80(&rw2458n_flash_data);
+
+ ath79_register_mdio(0, ~RW2458N_WAN_PHYMASK);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
+ ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
+
+ ath79_register_eth(0);
+ ath79_register_eth(1);
+
+ ap91_pci_init(ee, NULL);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(rw2458n_leds_gpio),
+ rw2458n_leds_gpio);
+
+ ath79_register_gpio_keys_polled(-1, RW2458N_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(rw2458n_gpio_keys),
+ rw2458n_gpio_keys);
+ ath79_register_usb();
+}
+
+MIPS_MACHINE(ATH79_MACH_RW2458N, "RW2458N", "Redwave RW2458N",
+ rw2458n_setup);
--- /dev/null
+/*
+ * TrendNET TEW-632BRP board support
+ *
+ * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "dev-wmac.h"
+#include "machtypes.h"
+#include "nvram.h"
+
+#define TEW_632BRP_GPIO_LED_STATUS 1
+#define TEW_632BRP_GPIO_LED_WPS 3
+#define TEW_632BRP_GPIO_LED_WLAN 6
+#define TEW_632BRP_GPIO_BTN_WPS 12
+#define TEW_632BRP_GPIO_BTN_RESET 21
+
+#define TEW_632BRP_KEYS_POLL_INTERVAL 20 /* msecs */
+#define TEW_632BRP_KEYS_DEBOUNCE_INTERVAL (3 * TEW_632BRP_KEYS_POLL_INTERVAL)
+
+#define TEW_632BRP_CONFIG_ADDR 0x1f020000
+#define TEW_632BRP_CONFIG_SIZE 0x10000
+
+static struct mtd_partition tew_632brp_partitions[] = {
+ {
+ .name = "u-boot",
+ .offset = 0,
+ .size = 0x020000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "config",
+ .offset = 0x020000,
+ .size = 0x010000,
+ }, {
+ .name = "kernel",
+ .offset = 0x030000,
+ .size = 0x0e0000,
+ }, {
+ .name = "rootfs",
+ .offset = 0x110000,
+ .size = 0x2e0000,
+ }, {
+ .name = "art",
+ .offset = 0x3f0000,
+ .size = 0x010000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "firmware",
+ .offset = 0x030000,
+ .size = 0x3c0000,
+ }
+};
+
+static struct flash_platform_data tew_632brp_flash_data = {
+ .parts = tew_632brp_partitions,
+ .nr_parts = ARRAY_SIZE(tew_632brp_partitions),
+};
+
+static struct gpio_led tew_632brp_leds_gpio[] __initdata = {
+ {
+ .name = "tew-632brp:green:status",
+ .gpio = TEW_632BRP_GPIO_LED_STATUS,
+ .active_low = 1,
+ }, {
+ .name = "tew-632brp:blue:wps",
+ .gpio = TEW_632BRP_GPIO_LED_WPS,
+ .active_low = 1,
+ }, {
+ .name = "tew-632brp:green:wlan",
+ .gpio = TEW_632BRP_GPIO_LED_WLAN,
+ .active_low = 1,
+ }
+};
+
+static struct gpio_keys_button tew_632brp_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = TEW_632BRP_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = TEW_632BRP_GPIO_BTN_RESET,
+ }, {
+ .desc = "wps",
+ .type = EV_KEY,
+ .code = KEY_WPS_BUTTON,
+ .debounce_interval = TEW_632BRP_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = TEW_632BRP_GPIO_BTN_WPS,
+ }
+};
+
+#define TEW_632BRP_LAN_PHYMASK BIT(0)
+#define TEW_632BRP_WAN_PHYMASK BIT(4)
+#define TEW_632BRP_MDIO_MASK (~(TEW_632BRP_LAN_PHYMASK | \
+ TEW_632BRP_WAN_PHYMASK))
+
+static void __init tew_632brp_setup(void)
+{
+ const char *config = (char *) KSEG1ADDR(TEW_632BRP_CONFIG_ADDR);
+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);
+ u8 mac[6];
+ u8 *wlan_mac = NULL;
+
+ if (ath79_nvram_parse_mac_addr(config, TEW_632BRP_CONFIG_SIZE,
+ "lan_mac=", mac) == 0) {
+ ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
+ ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
+ wlan_mac = mac;
+ }
+
+ ath79_register_mdio(0, TEW_632BRP_MDIO_MASK);
+
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
+ ath79_eth0_data.phy_mask = TEW_632BRP_LAN_PHYMASK;
+
+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
+ ath79_eth1_data.phy_mask = TEW_632BRP_WAN_PHYMASK;
+
+ ath79_register_eth(0);
+ ath79_register_eth(1);
+
+ ath79_register_m25p80(&tew_632brp_flash_data);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(tew_632brp_leds_gpio),
+ tew_632brp_leds_gpio);
+
+ ath79_register_gpio_keys_polled(-1, TEW_632BRP_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(tew_632brp_gpio_keys),
+ tew_632brp_gpio_keys);
+
+ ath79_register_wmac(eeprom, wlan_mac);
+}
+
+MIPS_MACHINE(ATH79_MACH_TEW_632BRP, "TEW-632BRP", "TRENDnet TEW-632BRP",
+ tew_632brp_setup);
--- /dev/null
+/*
+ * TP-LINK TL-MR3020 board support
+ *
+ * Copyright (C) 2011 dongyuqi <729650915@qq.com>
+ * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "dev-usb.h"
+#include "dev-wmac.h"
+#include "machtypes.h"
+
+#define TL_MR3020_GPIO_LED_3G 27
+#define TL_MR3020_GPIO_LED_WLAN 0
+#define TL_MR3020_GPIO_LED_LAN 17
+#define TL_MR3020_GPIO_LED_WPS 26
+
+#define TL_MR3020_GPIO_BTN_WPS 11
+#define TL_MR3020_GPIO_BTN_SW1 18
+#define TL_MR3020_GPIO_BTN_SW2 20
+
+#define TL_MR3020_GPIO_USB_POWER 8
+
+#define TL_MR3020_KEYS_POLL_INTERVAL 20 /* msecs */
+#define TL_MR3020_KEYS_DEBOUNCE_INTERVAL (3 * TL_MR3020_KEYS_POLL_INTERVAL)
+
+static const char *tl_mr3020_part_probes[] = {
+ "tp-link",
+ NULL,
+};
+
+static struct flash_platform_data tl_mr3020_flash_data = {
+ .part_probes = tl_mr3020_part_probes,
+};
+
+static struct gpio_led tl_mr3020_leds_gpio[] __initdata = {
+ {
+ .name = "tp-link:green:3g",
+ .gpio = TL_MR3020_GPIO_LED_3G,
+ .active_low = 1,
+ },
+ {
+ .name = "tp-link:green:wlan",
+ .gpio = TL_MR3020_GPIO_LED_WLAN,
+ .active_low = 0,
+ },
+ {
+ .name = "tp-link:green:lan",
+ .gpio = TL_MR3020_GPIO_LED_LAN,
+ .active_low = 1,
+ },
+ {
+ .name = "tp-link:green:wps",
+ .gpio = TL_MR3020_GPIO_LED_WPS,
+ .active_low = 1,
+ },
+};
+
+static struct gpio_keys_button tl_mr3020_gpio_keys[] __initdata = {
+ {
+ .desc = "wps",
+ .type = EV_KEY,
+ .code = KEY_WPS_BUTTON,
+ .debounce_interval = TL_MR3020_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = TL_MR3020_GPIO_BTN_WPS,
+ .active_low = 1,
+ },
+ {
+ .desc = "sw1",
+ .type = EV_KEY,
+ .code = BTN_0,
+ .debounce_interval = TL_MR3020_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = TL_MR3020_GPIO_BTN_SW1,
+ .active_low = 1,
+ },
+ {
+ .desc = "sw2",
+ .type = EV_KEY,
+ .code = BTN_1,
+ .debounce_interval = TL_MR3020_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = TL_MR3020_GPIO_BTN_SW2,
+ .active_low = 1,
+ }
+};
+
+static void __init tl_mr3020_setup(void)
+{
+ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
+ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
+
+ ath79_register_m25p80(&tl_mr3020_flash_data);
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_mr3020_leds_gpio),
+ tl_mr3020_leds_gpio);
+ ath79_register_gpio_keys_polled(-1, TL_MR3020_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(tl_mr3020_gpio_keys),
+ tl_mr3020_gpio_keys);
+
+ gpio_request(TL_MR3020_GPIO_USB_POWER, "USB power");
+ gpio_direction_output(TL_MR3020_GPIO_USB_POWER, 1);
+ ath79_register_usb();
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
+
+ ath79_register_mdio(0, 0x0);
+ ath79_register_eth(0);
+ ath79_register_wmac(ee, mac);
+}
+
+MIPS_MACHINE(ATH79_MACH_TL_MR3020, "TL-MR3020", "TP-LINK TL-MR3020 v1",
+ tl_mr3020_setup);
--- /dev/null
+/*
+ * TP-LINK TL-MR3220/3420 board support
+ *
+ * Copyright (C) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-eth.h"
+#include "dev-ap9x-pci.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "dev-usb.h"
+#include "machtypes.h"
+
+#define TL_MR3X20_GPIO_LED_QSS 0
+#define TL_MR3X20_GPIO_LED_SYSTEM 1
+#define TL_MR3X20_GPIO_LED_3G 8
+
+#define TL_MR3X20_GPIO_BTN_RESET 11
+#define TL_MR3X20_GPIO_BTN_QSS 12
+
+#define TL_MR3X20_GPIO_USB_POWER 6
+
+#define TL_MR3X20_KEYS_POLL_INTERVAL 20 /* msecs */
+#define TL_MR3X20_KEYS_DEBOUNCE_INTERVAL (3 * TL_MR3X20_KEYS_POLL_INTERVAL)
+
+static const char *tl_mr3x20_part_probes[] = {
+ "tp-link",
+ NULL,
+};
+
+static struct flash_platform_data tl_mr3x20_flash_data = {
+ .part_probes = tl_mr3x20_part_probes,
+};
+
+static struct gpio_led tl_mr3x20_leds_gpio[] __initdata = {
+ {
+ .name = "tp-link:green:system",
+ .gpio = TL_MR3X20_GPIO_LED_SYSTEM,
+ .active_low = 1,
+ }, {
+ .name = "tp-link:green:qss",
+ .gpio = TL_MR3X20_GPIO_LED_QSS,
+ .active_low = 1,
+ }, {
+ .name = "tp-link:green:3g",
+ .gpio = TL_MR3X20_GPIO_LED_3G,
+ .active_low = 1,
+ }
+};
+
+static struct gpio_keys_button tl_mr3x20_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = TL_MR3X20_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = TL_MR3X20_GPIO_BTN_RESET,
+ .active_low = 1,
+ }, {
+ .desc = "qss",
+ .type = EV_KEY,
+ .code = KEY_WPS_BUTTON,
+ .debounce_interval = TL_MR3X20_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = TL_MR3X20_GPIO_BTN_QSS,
+ .active_low = 1,
+ }
+};
+
+static void __init tl_ap99_setup(void)
+{
+ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
+ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
+
+ ath79_register_m25p80(&tl_mr3x20_flash_data);
+
+ ath79_register_gpio_keys_polled(-1, TL_MR3X20_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(tl_mr3x20_gpio_keys),
+ tl_mr3x20_gpio_keys);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
+ ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1);
+
+ ath79_register_mdio(0, 0x0);
+
+ /* LAN ports */
+ ath79_register_eth(1);
+ /* WAN port */
+ ath79_register_eth(0);
+
+ ap91_pci_init(ee, mac);
+}
+
+static void __init tl_mr3x20_usb_setup(void)
+{
+ /* enable power for the USB port */
+ gpio_request(TL_MR3X20_GPIO_USB_POWER, "USB power");
+ gpio_direction_output(TL_MR3X20_GPIO_USB_POWER, 1);
+
+ ath79_register_usb();
+}
+
+static void __init tl_mr3220_setup(void)
+{
+ tl_ap99_setup();
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_mr3x20_leds_gpio),
+ tl_mr3x20_leds_gpio);
+ ap9x_pci_setup_wmac_led_pin(0, 1);
+ tl_mr3x20_usb_setup();
+}
+
+MIPS_MACHINE(ATH79_MACH_TL_MR3220, "TL-MR3220", "TP-LINK TL-MR3220",
+ tl_mr3220_setup);
+
+static void __init tl_mr3420_setup(void)
+{
+ tl_ap99_setup();
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_mr3x20_leds_gpio),
+ tl_mr3x20_leds_gpio);
+ ap9x_pci_setup_wmac_led_pin(0, 0);
+ tl_mr3x20_usb_setup();
+}
+
+MIPS_MACHINE(ATH79_MACH_TL_MR3420, "TL-MR3420", "TP-LINK TL-MR3420",
+ tl_mr3420_setup);
+
+static void __init tl_wr841n_v7_setup(void)
+{
+ tl_ap99_setup();
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_mr3x20_leds_gpio) - 1,
+ tl_mr3x20_leds_gpio);
+ ap9x_pci_setup_wmac_led_pin(0, 0);
+}
+
+MIPS_MACHINE(ATH79_MACH_TL_WR841N_V7, "TL-WR841N-v7",
+ "TP-LINK TL-WR841N/ND v7", tl_wr841n_v7_setup);
--- /dev/null
+/*
+ * TP-LINK TL-WA901N/ND v2 board support
+ *
+ * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2010 Pieter Hollants <pieter@hollants.com>
+ * Copyright (C) 2011 Jonathan Bennett <jbscience87@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <asm/mach-ath79/ath79.h>
+#include <asm/mach-ath79/ar71xx_regs.h>
+
+#include "dev-eth.h"
+#include "dev-m25p80.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-wmac.h"
+#include "machtypes.h"
+
+#define TL_WA901ND_V2_GPIO_LED_QSS 4
+#define TL_WA901ND_V2_GPIO_LED_SYSTEM 2
+#define TL_WA901ND_V2_GPIO_LED_WLAN 9
+
+#define TL_WA901ND_V2_GPIO_BTN_RESET 3
+#define TL_WA901ND_V2_GPIO_BTN_QSS 7
+
+#define TL_WA901ND_V2_KEYS_POLL_INTERVAL 20 /* msecs */
+#define TL_WA901ND_V2_KEYS_DEBOUNCE_INTERVAL \
+ (3 * TL_WA901ND_V2_KEYS_POLL_INTERVAL)
+
+static const char *tl_wa901nd_v2_part_probes[] = {
+ "tp-link",
+ NULL,
+};
+
+static struct flash_platform_data tl_wa901nd_v2_flash_data = {
+ .part_probes = tl_wa901nd_v2_part_probes,
+};
+
+static struct gpio_led tl_wa901nd_v2_leds_gpio[] __initdata = {
+ {
+ .name = "tp-link:green:system",
+ .gpio = TL_WA901ND_V2_GPIO_LED_SYSTEM,
+ .active_low = 1,
+ }, {
+ .name = "tp-link:green:qss",
+ .gpio = TL_WA901ND_V2_GPIO_LED_QSS,
+ }, {
+ .name = "tp-link:green:wlan",
+ .gpio = TL_WA901ND_V2_GPIO_LED_WLAN,
+ .active_low = 1,
+ }
+};
+
+static struct gpio_keys_button tl_wa901nd_v2_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = TL_WA901ND_V2_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = TL_WA901ND_V2_GPIO_BTN_RESET,
+ .active_low = 1,
+ }, {
+ .desc = "qss",
+ .type = EV_KEY,
+ .code = KEY_WPS_BUTTON,
+ .debounce_interval = TL_WA901ND_V2_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = TL_WA901ND_V2_GPIO_BTN_QSS,
+ .active_low = 1,
+ }
+};
+
+static void __init tl_wa901nd_v2_setup(void)
+{
+ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
+
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
+ ath79_eth0_data.phy_mask = 0x00001000;
+ ath79_register_mdio(0, 0x0);
+
+ ath79_eth0_data.reset_bit = AR71XX_RESET_GE0_MAC |
+ AR71XX_RESET_GE0_PHY;
+ ath79_register_eth(0);
+
+ ath79_register_m25p80(&tl_wa901nd_v2_flash_data);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa901nd_v2_leds_gpio),
+ tl_wa901nd_v2_leds_gpio);
+
+ ath79_register_gpio_keys_polled(-1, TL_WA901ND_V2_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(tl_wa901nd_v2_gpio_keys),
+ tl_wa901nd_v2_gpio_keys);
+
+ ath79_register_wmac(eeprom, mac);
+}
+
+MIPS_MACHINE(ATH79_MACH_TL_WA901ND_V2, "TL-WA901ND-v2",
+ "TP-LINK TL-WA901ND v2", tl_wa901nd_v2_setup);
--- /dev/null
+/*
+ * TP-LINK TL-WA901N/ND v1 board support
+ *
+ * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2010 Pieter Hollants <pieter@hollants.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <asm/mach-ath79/ar71xx_regs.h>
+#include <asm/mach-ath79/ath79.h>
+
+#include "common.h"
+#include "dev-ap9x-pci.h"
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "machtypes.h"
+
+#define TL_WA901ND_GPIO_LED_QSS 0
+#define TL_WA901ND_GPIO_LED_SYSTEM 1
+#define TL_WA901ND_GPIO_LED_LAN 13
+
+#define TL_WA901ND_GPIO_BTN_RESET 11
+#define TL_WA901ND_GPIO_BTN_QSS 12
+
+#define TL_WA901ND_KEYS_POLL_INTERVAL 20 /* msecs */
+#define TL_WA901ND_KEYS_DEBOUNCE_INTERVAL (3 * TL_WA901ND_KEYS_POLL_INTERVAL)
+
+static const char *tl_wa901nd_part_probes[] = {
+ "tp-link",
+ NULL,
+};
+
+static struct flash_platform_data tl_wa901nd_flash_data = {
+ .part_probes = tl_wa901nd_part_probes,
+};
+
+static struct gpio_led tl_wa901nd_leds_gpio[] __initdata = {
+ {
+ .name = "tp-link:green:lan",
+ .gpio = TL_WA901ND_GPIO_LED_LAN,
+ .active_low = 1,
+ }, {
+ .name = "tp-link:green:system",
+ .gpio = TL_WA901ND_GPIO_LED_SYSTEM,
+ .active_low = 1,
+ }, {
+ .name = "tp-link:green:qss",
+ .gpio = TL_WA901ND_GPIO_LED_QSS,
+ .active_low = 1,
+ }
+};
+
+static struct gpio_keys_button tl_wa901nd_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = BTN_0,
+ .debounce_interval = TL_WA901ND_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = TL_WA901ND_GPIO_BTN_RESET,
+ .active_low = 1,
+ }, {
+ .desc = "qss",
+ .type = EV_KEY,
+ .code = BTN_1,
+ .debounce_interval = TL_WA901ND_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = TL_WA901ND_GPIO_BTN_QSS,
+ .active_low = 1,
+ }
+};
+
+static void __init tl_wa901nd_setup(void)
+{
+ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
+ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
+
+ ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
+ AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
+ AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
+ AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
+ AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
+
+ /*
+ * ath79_eth0 would be the WAN port, but is not connected on
+ * the TL-WA901ND. ath79_eth1 connects to the internal switch chip,
+ * however we have a single LAN port only.
+ */
+ ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
+ ath79_register_mdio(0, 0x0);
+ ath79_register_eth(1);
+
+ ath79_register_m25p80(&tl_wa901nd_flash_data);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wa901nd_leds_gpio),
+ tl_wa901nd_leds_gpio);
+
+ ath79_register_gpio_keys_polled(-1, TL_WA901ND_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(tl_wa901nd_gpio_keys),
+ tl_wa901nd_gpio_keys);
+
+ ap91_pci_init(ee, mac);
+}
+
+MIPS_MACHINE(ATH79_MACH_TL_WA901ND, "TL-WA901ND", "TP-LINK TL-WA901ND",
+ tl_wa901nd_setup);
--- /dev/null
+/*
+ * TP-LINK TL-WR1043N/ND board support
+ *
+ * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/rtl8366.h>
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-eth.h"
+#include "dev-m25p80.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-usb.h"
+#include "dev-wmac.h"
+#include "machtypes.h"
+
+#define TL_WR1043ND_GPIO_LED_USB 1
+#define TL_WR1043ND_GPIO_LED_SYSTEM 2
+#define TL_WR1043ND_GPIO_LED_QSS 5
+#define TL_WR1043ND_GPIO_LED_WLAN 9
+
+#define TL_WR1043ND_GPIO_BTN_RESET 3
+#define TL_WR1043ND_GPIO_BTN_QSS 7
+
+#define TL_WR1043ND_GPIO_RTL8366_SDA 18
+#define TL_WR1043ND_GPIO_RTL8366_SCK 19
+
+#define TL_WR1043ND_KEYS_POLL_INTERVAL 20 /* msecs */
+#define TL_WR1043ND_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR1043ND_KEYS_POLL_INTERVAL)
+
+static const char *tl_wr1043nd_part_probes[] = {
+ "tp-link",
+ NULL,
+};
+
+static struct flash_platform_data tl_wr1043nd_flash_data = {
+ .part_probes = tl_wr1043nd_part_probes,
+};
+
+static struct gpio_led tl_wr1043nd_leds_gpio[] __initdata = {
+ {
+ .name = "tp-link:green:usb",
+ .gpio = TL_WR1043ND_GPIO_LED_USB,
+ .active_low = 1,
+ }, {
+ .name = "tp-link:green:system",
+ .gpio = TL_WR1043ND_GPIO_LED_SYSTEM,
+ .active_low = 1,
+ }, {
+ .name = "tp-link:green:qss",
+ .gpio = TL_WR1043ND_GPIO_LED_QSS,
+ .active_low = 0,
+ }, {
+ .name = "tp-link:green:wlan",
+ .gpio = TL_WR1043ND_GPIO_LED_WLAN,
+ .active_low = 1,
+ }
+};
+
+static struct gpio_keys_button tl_wr1043nd_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = TL_WR1043ND_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = TL_WR1043ND_GPIO_BTN_RESET,
+ .active_low = 1,
+ }, {
+ .desc = "qss",
+ .type = EV_KEY,
+ .code = KEY_WPS_BUTTON,
+ .debounce_interval = TL_WR1043ND_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = TL_WR1043ND_GPIO_BTN_QSS,
+ .active_low = 1,
+ }
+};
+
+static struct rtl8366_platform_data tl_wr1043nd_rtl8366rb_data = {
+ .gpio_sda = TL_WR1043ND_GPIO_RTL8366_SDA,
+ .gpio_sck = TL_WR1043ND_GPIO_RTL8366_SCK,
+};
+
+static struct platform_device tl_wr1043nd_rtl8366rb_device = {
+ .name = RTL8366RB_DRIVER_NAME,
+ .id = -1,
+ .dev = {
+ .platform_data = &tl_wr1043nd_rtl8366rb_data,
+ }
+};
+
+static void __init tl_wr1043nd_setup(void)
+{
+ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
+ ath79_eth0_data.mii_bus_dev = &tl_wr1043nd_rtl8366rb_device.dev;
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+ ath79_eth0_data.speed = SPEED_1000;
+ ath79_eth0_data.duplex = DUPLEX_FULL;
+ ath79_eth0_pll_data.pll_1000 = 0x1a000000;
+
+ ath79_register_eth(0);
+
+ ath79_register_usb();
+
+ ath79_register_m25p80(&tl_wr1043nd_flash_data);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr1043nd_leds_gpio),
+ tl_wr1043nd_leds_gpio);
+
+ platform_device_register(&tl_wr1043nd_rtl8366rb_device);
+
+ ath79_register_gpio_keys_polled(-1, TL_WR1043ND_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(tl_wr1043nd_gpio_keys),
+ tl_wr1043nd_gpio_keys);
+
+ ath79_register_wmac(eeprom, mac);
+}
+
+MIPS_MACHINE(ATH79_MACH_TL_WR1043ND, "TL-WR1043ND", "TP-LINK TL-WR1043ND",
+ tl_wr1043nd_setup);
--- /dev/null
+/*
+ * TP-LINK TL-WR2543N/ND board support
+ *
+ * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/rtl8367.h>
+
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-eth.h"
+#include "dev-ap9x-pci.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "dev-usb.h"
+#include "machtypes.h"
+
+#define TL_WR2543N_GPIO_LED_WPS 0
+#define TL_WR2543N_GPIO_LED_USB 8
+
+#define TL_WR2543N_GPIO_BTN_RESET 11
+#define TL_WR2543N_GPIO_BTN_WPS 12
+
+#define TL_WR2543N_GPIO_RTL8367_SDA 1
+#define TL_WR2543N_GPIO_RTL8367_SCK 6
+
+#define TL_WR2543N_KEYS_POLL_INTERVAL 20 /* msecs */
+#define TL_WR2543N_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR2543N_KEYS_POLL_INTERVAL)
+
+static const char *tl_wr2543n_part_probes[] = {
+ "tp-link",
+ NULL,
+};
+
+static struct flash_platform_data tl_wr2543n_flash_data = {
+ .part_probes = tl_wr2543n_part_probes,
+ .max_read_len = 64,
+};
+
+static struct gpio_led tl_wr2543n_leds_gpio[] __initdata = {
+ {
+ .name = "tp-link:green:usb",
+ .gpio = TL_WR2543N_GPIO_LED_USB,
+ .active_low = 1,
+ }, {
+ .name = "tp-link:green:wps",
+ .gpio = TL_WR2543N_GPIO_LED_WPS,
+ .active_low = 1,
+ }
+};
+
+static struct gpio_keys_button tl_wr2543n_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = TL_WR2543N_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = TL_WR2543N_GPIO_BTN_RESET,
+ .active_low = 1,
+ }, {
+ .desc = "wps",
+ .type = EV_KEY,
+ .code = KEY_WPS_BUTTON,
+ .debounce_interval = TL_WR2543N_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = TL_WR2543N_GPIO_BTN_WPS,
+ }
+};
+
+static struct rtl8367_extif_config tl_wr2543n_rtl8367_extif0_cfg = {
+ .mode = RTL8367_EXTIF_MODE_RGMII,
+ .txdelay = 1,
+ .rxdelay = 0,
+ .ability = {
+ .force_mode = 1,
+ .txpause = 1,
+ .rxpause = 1,
+ .link = 1,
+ .duplex = 1,
+ .speed = RTL8367_PORT_SPEED_1000,
+ },
+};
+
+static struct rtl8367_platform_data tl_wr2543n_rtl8367_data = {
+ .gpio_sda = TL_WR2543N_GPIO_RTL8367_SDA,
+ .gpio_sck = TL_WR2543N_GPIO_RTL8367_SCK,
+ .extif0_cfg = &tl_wr2543n_rtl8367_extif0_cfg,
+};
+
+static struct platform_device tl_wr2543n_rtl8367_device = {
+ .name = RTL8367_DRIVER_NAME,
+ .id = -1,
+ .dev = {
+ .platform_data = &tl_wr2543n_rtl8367_data,
+ }
+};
+
+static void __init tl_wr2543n_setup(void)
+{
+ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);
+
+ ath79_register_m25p80(&tl_wr2543n_flash_data);
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr2543n_leds_gpio),
+ tl_wr2543n_leds_gpio);
+ ath79_register_gpio_keys_polled(-1, TL_WR2543N_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(tl_wr2543n_gpio_keys),
+ tl_wr2543n_gpio_keys);
+ ath79_register_usb();
+ ap91_pci_init(eeprom, mac);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, mac, -1);
+ ath79_eth0_data.mii_bus_dev = &tl_wr2543n_rtl8367_device.dev;
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+ ath79_eth0_data.speed = SPEED_1000;
+ ath79_eth0_data.duplex = DUPLEX_FULL;
+ ath79_eth0_pll_data.pll_1000 = 0x1a000000;
+
+ ath79_register_eth(0);
+
+ platform_device_register(&tl_wr2543n_rtl8367_device);
+}
+
+MIPS_MACHINE(ATH79_MACH_TL_WR2543N, "TL-WR2543N", "TP-LINK TL-WR2543N/ND",
+ tl_wr2543n_setup);
--- /dev/null
+/*
+ * TP-LINK TL-WR703N board support
+ *
+ * Copyright (C) 2011 dongyuqi <729650915@qq.com>
+ * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "dev-usb.h"
+#include "dev-wmac.h"
+#include "machtypes.h"
+
+#define TL_WR703N_GPIO_LED_SYSTEM 27
+#define TL_WR703N_GPIO_BTN_RESET 11
+
+#define TL_WR703N_GPIO_USB_POWER 8
+
+#define TL_WR703N_KEYS_POLL_INTERVAL 20 /* msecs */
+#define TL_WR703N_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR703N_KEYS_POLL_INTERVAL)
+
+static const char *tl_wr703n_part_probes[] = {
+ "tp-link",
+ NULL,
+};
+
+static struct flash_platform_data tl_wr703n_flash_data = {
+ .part_probes = tl_wr703n_part_probes,
+};
+
+static struct gpio_led tl_wr703n_leds_gpio[] __initdata = {
+ {
+ .name = "tp-link:blue:system",
+ .gpio = TL_WR703N_GPIO_LED_SYSTEM,
+ .active_low = 1,
+ },
+};
+
+static struct gpio_keys_button tl_wr703n_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = TL_WR703N_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = TL_WR703N_GPIO_BTN_RESET,
+ .active_low = 1,
+ }
+};
+
+static void __init tl_wr703n_setup(void)
+{
+ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
+ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
+
+ ath79_register_m25p80(&tl_wr703n_flash_data);
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr703n_leds_gpio),
+ tl_wr703n_leds_gpio);
+ ath79_register_gpio_keys_polled(-1, TL_WR703N_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(tl_wr703n_gpio_keys),
+ tl_wr703n_gpio_keys);
+
+ gpio_request(TL_WR703N_GPIO_USB_POWER, "USB power");
+ gpio_direction_output(TL_WR703N_GPIO_USB_POWER, 1);
+ ath79_register_usb();
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
+
+ ath79_register_mdio(0, 0x0);
+ ath79_register_eth(0);
+
+ ath79_register_wmac(ee, mac);
+}
+
+MIPS_MACHINE(ATH79_MACH_TL_WR703N, "TL-WR703N", "TP-LINK TL-WR703N v1",
+ tl_wr703n_setup);
--- /dev/null
+/*
+ * TP-LINK TL-WR741ND v4 board support
+ *
+ * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+
+#include <asm/mach-ath79/ath79.h>
+#include <asm/mach-ath79/ar71xx_regs.h>
+
+#include "common.h"
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "dev-wmac.h"
+#include "machtypes.h"
+
+#define TL_WR741NDV4_GPIO_BTN_RESET 11
+#define TL_WR741NDV4_GPIO_BTN_WPS 26
+
+#define TL_WR741NDV4_GPIO_LED_WLAN 0
+#define TL_WR741NDV4_GPIO_LED_QSS 1
+#define TL_WR741NDV4_GPIO_LED_WAN 13
+#define TL_WR741NDV4_GPIO_LED_LAN1 14
+#define TL_WR741NDV4_GPIO_LED_LAN2 15
+#define TL_WR741NDV4_GPIO_LED_LAN3 16
+#define TL_WR741NDV4_GPIO_LED_LAN4 17
+
+#define TL_WR741NDV4_GPIO_LED_SYSTEM 27
+
+#define TL_WR741NDV4_KEYS_POLL_INTERVAL 20 /* msecs */
+#define TL_WR741NDV4_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR741NDV4_KEYS_POLL_INTERVAL)
+
+static const char *tl_wr741ndv4_part_probes[] = {
+ "tp-link",
+ NULL,
+};
+
+static struct flash_platform_data tl_wr741ndv4_flash_data = {
+ .part_probes = tl_wr741ndv4_part_probes,
+};
+
+static struct gpio_led tl_wr741ndv4_leds_gpio[] __initdata = {
+ {
+ .name = "tp-link:green:lan1",
+ .gpio = TL_WR741NDV4_GPIO_LED_LAN1,
+ .active_low = 0,
+ }, {
+ .name = "tp-link:green:lan2",
+ .gpio = TL_WR741NDV4_GPIO_LED_LAN2,
+ .active_low = 0,
+ }, {
+ .name = "tp-link:green:lan3",
+ .gpio = TL_WR741NDV4_GPIO_LED_LAN3,
+ .active_low = 0,
+ }, {
+ .name = "tp-link:green:lan4",
+ .gpio = TL_WR741NDV4_GPIO_LED_LAN4,
+ .active_low = 1,
+ }, {
+ .name = "tp-link:green:qss",
+ .gpio = TL_WR741NDV4_GPIO_LED_QSS,
+ .active_low = 0,
+ }, {
+ .name = "tp-link:green:system",
+ .gpio = TL_WR741NDV4_GPIO_LED_SYSTEM,
+ .active_low = 1,
+ }, {
+ .name = "tp-link:green:wan",
+ .gpio = TL_WR741NDV4_GPIO_LED_WAN,
+ .active_low = 0,
+ }, {
+ .name = "tp-link:green:wlan",
+ .gpio = TL_WR741NDV4_GPIO_LED_WLAN,
+ .active_low = 0,
+ },
+};
+
+static struct gpio_keys_button tl_wr741ndv4_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = TL_WR741NDV4_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = TL_WR741NDV4_GPIO_BTN_RESET,
+ .active_low = 1,
+ }, {
+ .desc = "WPS",
+ .type = EV_KEY,
+ .code = KEY_WPS_BUTTON,
+ .debounce_interval = TL_WR741NDV4_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = TL_WR741NDV4_GPIO_BTN_WPS,
+ .active_low = 1,
+ }
+};
+
+static void __init tl_wr741ndv4_gmac_setup(void)
+{
+ void __iomem *base;
+ u32 t;
+
+ base = ioremap(AR933X_GMAC_BASE, AR933X_GMAC_SIZE);
+
+ t = __raw_readl(base + AR933X_GMAC_REG_ETH_CFG);
+ t |= (AR933X_ETH_CFG_SW_PHY_SWAP | AR933X_ETH_CFG_SW_PHY_ADDR_SWAP);
+ __raw_writel(t, base + AR933X_GMAC_REG_ETH_CFG);
+
+ iounmap(base);
+}
+
+static void __init tl_wr741ndv4_setup(void)
+{
+ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
+ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
+
+ tl_wr741ndv4_gmac_setup();
+
+ ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
+ AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
+ AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
+ AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
+ AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr741ndv4_leds_gpio),
+ tl_wr741ndv4_leds_gpio);
+
+ ath79_register_gpio_keys_polled(1, TL_WR741NDV4_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(tl_wr741ndv4_gpio_keys),
+ tl_wr741ndv4_gpio_keys);
+
+ ath79_register_m25p80(&tl_wr741ndv4_flash_data);
+ ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
+ ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1);
+
+ ath79_register_mdio(0, 0x0);
+ ath79_register_eth(1);
+ ath79_register_eth(0);
+
+ ath79_register_wmac(ee, mac);
+}
+
+MIPS_MACHINE(ATH79_MACH_TL_WR741ND_V4, "TL-WR741ND-v4",
+ "TP-LINK TL-WR741ND v4", tl_wr741ndv4_setup);
--- /dev/null
+/*
+ * TP-LINK TL-WR741ND board support
+ *
+ * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <asm/mach-ath79/ath79.h>
+#include <asm/mach-ath79/ar71xx_regs.h>
+
+#include "common.h"
+#include "dev-ap9x-pci.h"
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "machtypes.h"
+
+#define TL_WR741ND_GPIO_LED_QSS 0
+#define TL_WR741ND_GPIO_LED_SYSTEM 1
+#define TL_WR741ND_GPIO_LED_LAN1 13
+#define TL_WR741ND_GPIO_LED_LAN2 14
+#define TL_WR741ND_GPIO_LED_LAN3 15
+#define TL_WR741ND_GPIO_LED_LAN4 16
+#define TL_WR741ND_GPIO_LED_WAN 17
+
+#define TL_WR741ND_GPIO_BTN_RESET 11
+#define TL_WR741ND_GPIO_BTN_QSS 12
+
+#define TL_WR741ND_KEYS_POLL_INTERVAL 20 /* msecs */
+#define TL_WR741ND_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR741ND_KEYS_POLL_INTERVAL)
+
+static const char *tl_wr741nd_part_probes[] = {
+ "tp-link",
+ NULL,
+};
+
+static struct flash_platform_data tl_wr741nd_flash_data = {
+ .part_probes = tl_wr741nd_part_probes,
+};
+
+static struct gpio_led tl_wr741nd_leds_gpio[] __initdata = {
+ {
+ .name = "tp-link:green:lan1",
+ .gpio = TL_WR741ND_GPIO_LED_LAN1,
+ .active_low = 1,
+ }, {
+ .name = "tp-link:green:lan2",
+ .gpio = TL_WR741ND_GPIO_LED_LAN2,
+ .active_low = 1,
+ }, {
+ .name = "tp-link:green:lan3",
+ .gpio = TL_WR741ND_GPIO_LED_LAN3,
+ .active_low = 1,
+ }, {
+ .name = "tp-link:green:lan4",
+ .gpio = TL_WR741ND_GPIO_LED_LAN4,
+ .active_low = 1,
+ }, {
+ .name = "tp-link:green:qss",
+ .gpio = TL_WR741ND_GPIO_LED_QSS,
+ .active_low = 1,
+ }, {
+ .name = "tp-link:green:system",
+ .gpio = TL_WR741ND_GPIO_LED_SYSTEM,
+ .active_low = 1,
+ }, {
+ .name = "tp-link:green:wan",
+ .gpio = TL_WR741ND_GPIO_LED_WAN,
+ .active_low = 1,
+ },
+};
+
+static struct gpio_keys_button tl_wr741nd_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = TL_WR741ND_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = TL_WR741ND_GPIO_BTN_RESET,
+ .active_low = 1,
+ }, {
+ .desc = "qss",
+ .type = EV_KEY,
+ .code = KEY_WPS_BUTTON,
+ .debounce_interval = TL_WR741ND_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = TL_WR741ND_GPIO_BTN_QSS,
+ .active_low = 1,
+ }
+};
+
+static void __init tl_wr741nd_setup(void)
+{
+ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
+ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
+
+ ath79_register_m25p80(&tl_wr741nd_flash_data);
+
+ ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
+ AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
+ AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
+ AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
+ AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr741nd_leds_gpio),
+ tl_wr741nd_leds_gpio);
+
+ ath79_register_gpio_keys_polled(-1, TL_WR741ND_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(tl_wr741nd_gpio_keys),
+ tl_wr741nd_gpio_keys);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
+ ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1);
+
+ ath79_register_mdio(0, 0x0);
+
+ /* LAN ports */
+ ath79_register_eth(1);
+
+ /* WAN port */
+ ath79_register_eth(0);
+
+ ap9x_pci_setup_wmac_led_pin(0, 1);
+ ap91_pci_init(ee, mac);
+}
+MIPS_MACHINE(ATH79_MACH_TL_WR741ND, "TL-WR741ND", "TP-LINK TL-WR741ND",
+ tl_wr741nd_setup);
--- /dev/null
+/*
+ * TP-LINK TL-WR841N/ND v1 board support
+ *
+ * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-dsa.h"
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "machtypes.h"
+#include "pci.h"
+
+#define TL_WR841ND_V1_GPIO_LED_SYSTEM 2
+#define TL_WR841ND_V1_GPIO_LED_QSS_GREEN 4
+#define TL_WR841ND_V1_GPIO_LED_QSS_RED 5
+
+#define TL_WR841ND_V1_GPIO_BTN_RESET 3
+#define TL_WR841ND_V1_GPIO_BTN_QSS 7
+
+#define TL_WR841ND_V1_KEYS_POLL_INTERVAL 20 /* msecs */
+#define TL_WR841ND_V1_KEYS_DEBOUNCE_INTERVAL \
+ (3 * TL_WR841ND_V1_KEYS_POLL_INTERVAL)
+
+static struct mtd_partition tl_wr841n_v1_partitions[] = {
+ {
+ .name = "redboot",
+ .offset = 0,
+ .size = 0x020000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "kernel",
+ .offset = 0x020000,
+ .size = 0x140000,
+ }, {
+ .name = "rootfs",
+ .offset = 0x160000,
+ .size = 0x280000,
+ }, {
+ .name = "config",
+ .offset = 0x3e0000,
+ .size = 0x020000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "firmware",
+ .offset = 0x020000,
+ .size = 0x3c0000,
+ }
+};
+
+static struct flash_platform_data tl_wr841n_v1_flash_data = {
+ .parts = tl_wr841n_v1_partitions,
+ .nr_parts = ARRAY_SIZE(tl_wr841n_v1_partitions),
+};
+
+static struct gpio_led tl_wr841n_v1_leds_gpio[] __initdata = {
+ {
+ .name = "tp-link:green:system",
+ .gpio = TL_WR841ND_V1_GPIO_LED_SYSTEM,
+ .active_low = 1,
+ }, {
+ .name = "tp-link:red:qss",
+ .gpio = TL_WR841ND_V1_GPIO_LED_QSS_RED,
+ }, {
+ .name = "tp-link:green:qss",
+ .gpio = TL_WR841ND_V1_GPIO_LED_QSS_GREEN,
+ }
+};
+
+static struct gpio_keys_button tl_wr841n_v1_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = TL_WR841ND_V1_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = TL_WR841ND_V1_GPIO_BTN_RESET,
+ .active_low = 1,
+ }, {
+ .desc = "qss",
+ .type = EV_KEY,
+ .code = KEY_WPS_BUTTON,
+ .debounce_interval = TL_WR841ND_V1_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = TL_WR841ND_V1_GPIO_BTN_QSS,
+ .active_low = 1,
+ }
+};
+
+static struct dsa_chip_data tl_wr841n_v1_dsa_chip = {
+ .port_names[0] = "wan",
+ .port_names[1] = "lan1",
+ .port_names[2] = "lan2",
+ .port_names[3] = "lan3",
+ .port_names[4] = "lan4",
+ .port_names[5] = "cpu",
+};
+
+static struct dsa_platform_data tl_wr841n_v1_dsa_data = {
+ .nr_chips = 1,
+ .chip = &tl_wr841n_v1_dsa_chip,
+};
+
+static void __init tl_wr841n_v1_setup(void)
+{
+ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
+
+ ath79_register_mdio(0, 0x0);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
+ ath79_eth0_data.speed = SPEED_100;
+ ath79_eth0_data.duplex = DUPLEX_FULL;
+
+ ath79_register_eth(0);
+ ath79_register_dsa(&ath79_eth0_device.dev, &ath79_mdio0_device.dev,
+ &tl_wr841n_v1_dsa_data);
+
+ ath79_register_m25p80(&tl_wr841n_v1_flash_data);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr841n_v1_leds_gpio),
+ tl_wr841n_v1_leds_gpio);
+
+ ath79_register_gpio_keys_polled(-1, TL_WR841ND_V1_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(tl_wr841n_v1_gpio_keys),
+ tl_wr841n_v1_gpio_keys);
+ ath79_register_pci();
+}
+
+MIPS_MACHINE(ATH79_MACH_TL_WR841N_V1, "TL-WR841N-v1.5", "TP-LINK TL-WR841N v1",
+ tl_wr841n_v1_setup);
--- /dev/null
+/*
+ * TP-LINK TL-WR941ND board support
+ *
+ * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-dsa.h"
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "dev-wmac.h"
+#include "machtypes.h"
+
+#define TL_WR941ND_GPIO_LED_SYSTEM 2
+#define TL_WR941ND_GPIO_LED_QSS_RED 4
+#define TL_WR941ND_GPIO_LED_QSS_GREEN 5
+#define TL_WR941ND_GPIO_LED_WLAN 9
+
+#define TL_WR941ND_GPIO_BTN_RESET 3
+#define TL_WR941ND_GPIO_BTN_QSS 7
+
+#define TL_WR941ND_KEYS_POLL_INTERVAL 20 /* msecs */
+#define TL_WR941ND_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR941ND_KEYS_POLL_INTERVAL)
+
+static const char *tl_wr941nd_part_probes[] = {
+ "tp-link",
+ NULL,
+};
+
+static struct flash_platform_data tl_wr941nd_flash_data = {
+ .part_probes = tl_wr941nd_part_probes,
+};
+
+static struct gpio_led tl_wr941nd_leds_gpio[] __initdata = {
+ {
+ .name = "tp-link:green:system",
+ .gpio = TL_WR941ND_GPIO_LED_SYSTEM,
+ .active_low = 1,
+ }, {
+ .name = "tp-link:red:qss",
+ .gpio = TL_WR941ND_GPIO_LED_QSS_RED,
+ }, {
+ .name = "tp-link:green:qss",
+ .gpio = TL_WR941ND_GPIO_LED_QSS_GREEN,
+ }, {
+ .name = "tp-link:green:wlan",
+ .gpio = TL_WR941ND_GPIO_LED_WLAN,
+ .active_low = 1,
+ }
+};
+
+static struct gpio_keys_button tl_wr941nd_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = TL_WR941ND_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = TL_WR941ND_GPIO_BTN_RESET,
+ .active_low = 1,
+ }, {
+ .desc = "qss",
+ .type = EV_KEY,
+ .code = KEY_WPS_BUTTON,
+ .debounce_interval = TL_WR941ND_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = TL_WR941ND_GPIO_BTN_QSS,
+ .active_low = 1,
+ }
+};
+
+static struct dsa_chip_data tl_wr941nd_dsa_chip = {
+ .port_names[0] = "wan",
+ .port_names[1] = "lan1",
+ .port_names[2] = "lan2",
+ .port_names[3] = "lan3",
+ .port_names[4] = "lan4",
+ .port_names[5] = "cpu",
+};
+
+static struct dsa_platform_data tl_wr941nd_dsa_data = {
+ .nr_chips = 1,
+ .chip = &tl_wr941nd_dsa_chip,
+};
+
+static void __init tl_wr941nd_setup(void)
+{
+ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);
+
+ ath79_register_mdio(0, 0x0);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
+ ath79_eth0_data.speed = SPEED_100;
+ ath79_eth0_data.duplex = DUPLEX_FULL;
+
+ ath79_register_eth(0);
+ ath79_register_dsa(&ath79_eth0_device.dev, &ath79_mdio0_device.dev,
+ &tl_wr941nd_dsa_data);
+
+ ath79_register_m25p80(&tl_wr941nd_flash_data);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr941nd_leds_gpio),
+ tl_wr941nd_leds_gpio);
+
+ ath79_register_gpio_keys_polled(-1, TL_WR941ND_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(tl_wr941nd_gpio_keys),
+ tl_wr941nd_gpio_keys);
+ ath79_register_wmac(eeprom, mac);
+}
+
+MIPS_MACHINE(ATH79_MACH_TL_WR941ND, "TL-WR941ND", "TP-LINK TL-WR941ND",
+ tl_wr941nd_setup);
--- /dev/null
+/*
+ * Ubiquiti RouterStation support
+ *
+ * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ * Copyright (C) 2008 Ubiquiti <support@ubnt.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "dev-usb.h"
+#include "machtypes.h"
+#include "pci.h"
+
+#define UBNT_RS_GPIO_LED_RF 2
+#define UBNT_RS_GPIO_SW4 8
+
+#define UBNT_LS_SR71_GPIO_LED_D25 0
+#define UBNT_LS_SR71_GPIO_LED_D26 1
+#define UBNT_LS_SR71_GPIO_LED_D24 2
+#define UBNT_LS_SR71_GPIO_LED_D23 4
+#define UBNT_LS_SR71_GPIO_LED_D22 5
+#define UBNT_LS_SR71_GPIO_LED_D27 6
+#define UBNT_LS_SR71_GPIO_LED_D28 7
+
+#define UBNT_KEYS_POLL_INTERVAL 20 /* msecs */
+#define UBNT_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_KEYS_POLL_INTERVAL)
+
+static struct gpio_led ubnt_rs_leds_gpio[] __initdata = {
+ {
+ .name = "ubnt:green:rf",
+ .gpio = UBNT_RS_GPIO_LED_RF,
+ .active_low = 0,
+ }
+};
+
+static struct gpio_led ubnt_ls_sr71_leds_gpio[] __initdata = {
+ {
+ .name = "ubnt:green:d22",
+ .gpio = UBNT_LS_SR71_GPIO_LED_D22,
+ .active_low = 0,
+ }, {
+ .name = "ubnt:green:d23",
+ .gpio = UBNT_LS_SR71_GPIO_LED_D23,
+ .active_low = 0,
+ }, {
+ .name = "ubnt:green:d24",
+ .gpio = UBNT_LS_SR71_GPIO_LED_D24,
+ .active_low = 0,
+ }, {
+ .name = "ubnt:red:d25",
+ .gpio = UBNT_LS_SR71_GPIO_LED_D25,
+ .active_low = 0,
+ }, {
+ .name = "ubnt:red:d26",
+ .gpio = UBNT_LS_SR71_GPIO_LED_D26,
+ .active_low = 0,
+ }, {
+ .name = "ubnt:green:d27",
+ .gpio = UBNT_LS_SR71_GPIO_LED_D27,
+ .active_low = 0,
+ }, {
+ .name = "ubnt:green:d28",
+ .gpio = UBNT_LS_SR71_GPIO_LED_D28,
+ .active_low = 0,
+ }
+};
+
+static struct gpio_keys_button ubnt_gpio_keys[] __initdata = {
+ {
+ .desc = "sw4",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = UBNT_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = UBNT_RS_GPIO_SW4,
+ .active_low = 1,
+ }
+};
+
+static const char *ubnt_part_probes[] = {
+ "RedBoot",
+ NULL,
+};
+
+static struct flash_platform_data ubnt_flash_data = {
+ .part_probes = ubnt_part_probes,
+};
+
+static void __init ubnt_generic_setup(void)
+{
+ ath79_register_m25p80(&ubnt_flash_data);
+
+ ath79_register_gpio_keys_polled(-1, UBNT_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(ubnt_gpio_keys),
+ ubnt_gpio_keys);
+ ath79_register_pci();
+}
+
+#define UBNT_RS_WAN_PHYMASK BIT(20)
+#define UBNT_RS_LAN_PHYMASK (BIT(16) | BIT(17) | BIT(18) | BIT(19))
+
+static void __init ubnt_rs_setup(void)
+{
+ ubnt_generic_setup();
+
+ ath79_register_mdio(0, ~(UBNT_RS_WAN_PHYMASK | UBNT_RS_LAN_PHYMASK));
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
+ ath79_eth0_data.phy_mask = UBNT_RS_WAN_PHYMASK;
+
+ /*
+ * There is Secondary MAC address duplicate problem with some
+ * UBNT HW batches. Do not increase Secondary MAC address by 1
+ * but do workaround with 'Locally Administrated' bit.
+ */
+ ath79_init_local_mac(ath79_eth1_data.mac_addr, ath79_mac_base);
+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
+ ath79_eth1_data.speed = SPEED_100;
+ ath79_eth1_data.duplex = DUPLEX_FULL;
+
+ ath79_register_eth(0);
+ ath79_register_eth(1);
+
+ ath79_register_usb();
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_rs_leds_gpio),
+ ubnt_rs_leds_gpio);
+}
+
+MIPS_MACHINE(ATH79_MACH_UBNT_RS, "UBNT-RS", "Ubiquiti RouterStation",
+ ubnt_rs_setup);
+
+#define UBNT_RSPRO_WAN_PHYMASK BIT(4)
+#define UBNT_RSPRO_LAN_PHYMASK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
+
+static void __init ubnt_rspro_setup(void)
+{
+ ubnt_generic_setup();
+
+ ath79_register_mdio(0, ~(UBNT_RSPRO_WAN_PHYMASK |
+ UBNT_RSPRO_LAN_PHYMASK));
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+ ath79_eth0_data.phy_mask = UBNT_RSPRO_WAN_PHYMASK;
+
+ /*
+ * There is Secondary MAC address duplicate problem with some
+ * UBNT HW batches. Do not increase Secondary MAC address by 1
+ * but do workaround with 'Locally Administrated' bit.
+ */
+ ath79_init_local_mac(ath79_eth1_data.mac_addr, ath79_mac_base);
+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+ ath79_eth1_data.phy_mask = UBNT_RSPRO_LAN_PHYMASK;
+ ath79_eth1_data.speed = SPEED_1000;
+ ath79_eth1_data.duplex = DUPLEX_FULL;
+
+ ath79_register_eth(0);
+ ath79_register_eth(1);
+
+ ath79_register_usb();
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_rs_leds_gpio),
+ ubnt_rs_leds_gpio);
+}
+
+MIPS_MACHINE(ATH79_MACH_UBNT_RSPRO, "UBNT-RSPRO", "Ubiquiti RouterStation Pro",
+ ubnt_rspro_setup);
+
+static void __init ubnt_lsx_setup(void)
+{
+ ubnt_generic_setup();
+}
+
+MIPS_MACHINE(ATH79_MACH_UBNT_LSX, "UBNT-LSX", "Ubiquiti LSX", ubnt_lsx_setup);
+
+#define UBNT_LSSR71_PHY_MASK BIT(1)
+
+static void __init ubnt_lssr71_setup(void)
+{
+ ubnt_generic_setup();
+
+ ath79_register_mdio(0, ~UBNT_LSSR71_PHY_MASK);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
+ ath79_eth0_data.phy_mask = UBNT_LSSR71_PHY_MASK;
+
+ ath79_register_eth(0);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_ls_sr71_leds_gpio),
+ ubnt_ls_sr71_leds_gpio);
+}
+
+MIPS_MACHINE(ATH79_MACH_UBNT_LSSR71, "UBNT-LS-SR71", "Ubiquiti LS-SR71",
+ ubnt_lssr71_setup);
--- /dev/null
+/*
+ * Buffalo WHR-HP-G300N board support
+ *
+ * based on ...
+ *
+ * TP-LINK TL-WR741ND board support
+ *
+ * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-ap9x-pci.h"
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "machtypes.h"
+
+#define WHRHPG300N_GPIO_LED_SECURITY 0
+#define WHRHPG300N_GPIO_LED_DIAG 1
+#define WHRHPG300N_GPIO_LED_ROUTER 6
+
+#define WHRHPG300N_GPIO_BTN_ROUTER_ON 7
+#define WHRHPG300N_GPIO_BTN_ROUTER_AUTO 8
+#define WHRHPG300N_GPIO_BTN_RESET 11
+#define WHRHPG300N_GPIO_BTN_AOSS 12
+
+#define WHRHPG300N_KEYS_POLL_INTERVAL 20 /* msecs */
+#define WHRHPG300N_KEYS_DEBOUNCE_INTERVAL (3 * WHRHPG300N_KEYS_POLL_INTERVAL)
+
+#define WHRHPG300N_MAC_OFFSET 0x20c
+
+static struct mtd_partition whrhpg300n_partitions[] = {
+ {
+ .name = "u-boot",
+ .offset = 0,
+ .size = 0x03e000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "u-boot-env",
+ .offset = 0x03e000,
+ .size = 0x002000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "kernel",
+ .offset = 0x040000,
+ .size = 0x0e0000,
+ }, {
+ .name = "rootfs",
+ .offset = 0x120000,
+ .size = 0x2c0000,
+ }, {
+ .name = "user_property",
+ .offset = 0x3e0000,
+ .size = 0x010000,
+ }, {
+ .name = "ART",
+ .offset = 0x3f0000,
+ .size = 0x010000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "firmware",
+ .offset = 0x040000,
+ .size = 0x3a0000,
+ }
+};
+
+static struct flash_platform_data whrhpg300n_flash_data = {
+ .parts = whrhpg300n_partitions,
+ .nr_parts = ARRAY_SIZE(whrhpg300n_partitions),
+};
+
+static struct gpio_led whrhpg300n_leds_gpio[] __initdata = {
+ {
+ .name = "buffalo:orange:security",
+ .gpio = WHRHPG300N_GPIO_LED_SECURITY,
+ .active_low = 1,
+ }, {
+ .name = "buffalo:red:diag",
+ .gpio = WHRHPG300N_GPIO_LED_DIAG,
+ .active_low = 1,
+ }, {
+ .name = "buffalo:green:router",
+ .gpio = WHRHPG300N_GPIO_LED_ROUTER,
+ .active_low = 1,
+ }
+};
+
+static struct gpio_keys_button whrhpg300n_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = WHRHPG300N_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = WHRHPG300N_GPIO_BTN_RESET,
+ .active_low = 1,
+ }, {
+ .desc = "aoss/wps",
+ .type = EV_KEY,
+ .code = KEY_WPS_BUTTON,
+ .gpio = WHRHPG300N_GPIO_BTN_AOSS,
+ .debounce_interval = WHRHPG300N_KEYS_DEBOUNCE_INTERVAL,
+ .active_low = 1,
+ }, {
+ .desc = "router_on",
+ .type = EV_KEY,
+ .code = BTN_2,
+ .gpio = WHRHPG300N_GPIO_BTN_ROUTER_ON,
+ .debounce_interval = WHRHPG300N_KEYS_DEBOUNCE_INTERVAL,
+ .active_low = 1,
+ }, {
+ .desc = "router_auto",
+ .type = EV_KEY,
+ .code = BTN_3,
+ .gpio = WHRHPG300N_GPIO_BTN_ROUTER_AUTO,
+ .debounce_interval = WHRHPG300N_KEYS_DEBOUNCE_INTERVAL,
+ .active_low = 1,
+ }
+};
+
+static void __init whrhpg300n_setup(void)
+{
+ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
+ u8 *mac = (u8 *) KSEG1ADDR(ee + WHRHPG300N_MAC_OFFSET);
+
+ ath79_register_m25p80(&whrhpg300n_flash_data);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(whrhpg300n_leds_gpio),
+ whrhpg300n_leds_gpio);
+
+ ath79_register_gpio_keys_polled(-1, WHRHPG300N_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(whrhpg300n_gpio_keys),
+ whrhpg300n_gpio_keys);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
+ ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
+
+ ath79_register_mdio(0, 0x0);
+
+ /* LAN ports */
+ ath79_register_eth(1);
+ /* WAN port */
+ ath79_register_eth(0);
+
+ ap9x_pci_setup_wmac_led_pin(0, 1);
+
+ ap91_pci_init(ee, mac);
+}
+
+MIPS_MACHINE(ATH79_MACH_WHR_HP_G300N, "WHR-HP-G300N", "Buffalo WHR-HP-G300N",
+ whrhpg300n_setup);
+
+MIPS_MACHINE(ATH79_MACH_WHR_G301N, "WHR-G301N", "Buffalo WHR-G301N",
+ whrhpg300n_setup);
+
+MIPS_MACHINE(ATH79_MACH_WHR_HP_GN, "WHR-HP-GN", "Buffalo WHR-HP-GN",
+ whrhpg300n_setup);
--- /dev/null
+/*
+ * Netgear WNDR3700 board support
+ *
+ * Copyright (C) 2009 Marco Porsch
+ * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/delay.h>
+#include <linux/rtl8366.h>
+
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-ap9x-pci.h"
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "dev-usb.h"
+#include "machtypes.h"
+
+#define WNDR3700_GPIO_LED_WPS_ORANGE 0
+#define WNDR3700_GPIO_LED_POWER_ORANGE 1
+#define WNDR3700_GPIO_LED_POWER_GREEN 2
+#define WNDR3700_GPIO_LED_WPS_GREEN 4
+#define WNDR3700_GPIO_LED_WAN_GREEN 6
+
+#define WNDR3700_GPIO_BTN_WPS 3
+#define WNDR3700_GPIO_BTN_RESET 8
+#define WNDR3700_GPIO_BTN_WIFI 11
+
+#define WNDR3700_GPIO_RTL8366_SDA 5
+#define WNDR3700_GPIO_RTL8366_SCK 7
+
+#define WNDR3700_KEYS_POLL_INTERVAL 20 /* msecs */
+#define WNDR3700_KEYS_DEBOUNCE_INTERVAL (3 * WNDR3700_KEYS_POLL_INTERVAL)
+
+#define WNDR3700_ETH0_MAC_OFFSET 0
+#define WNDR3700_ETH1_MAC_OFFSET 0x6
+
+#define WNDR3700_WMAC0_MAC_OFFSET 0
+#define WNDR3700_WMAC1_MAC_OFFSET 0xc
+#define WNDR3700_CALDATA0_OFFSET 0x1000
+#define WNDR3700_CALDATA1_OFFSET 0x5000
+
+static struct gpio_led wndr3700_leds_gpio[] __initdata = {
+ {
+ .name = "wndr3700:green:power",
+ .gpio = WNDR3700_GPIO_LED_POWER_GREEN,
+ .active_low = 1,
+ }, {
+ .name = "wndr3700:orange:power",
+ .gpio = WNDR3700_GPIO_LED_POWER_ORANGE,
+ .active_low = 1,
+ }, {
+ .name = "wndr3700:green:wps",
+ .gpio = WNDR3700_GPIO_LED_WPS_GREEN,
+ .active_low = 1,
+ }, {
+ .name = "wndr3700:orange:wps",
+ .gpio = WNDR3700_GPIO_LED_WPS_ORANGE,
+ .active_low = 1,
+ }, {
+ .name = "wndr3700:green:wan",
+ .gpio = WNDR3700_GPIO_LED_WAN_GREEN,
+ .active_low = 1,
+ }
+};
+
+static struct gpio_keys_button wndr3700_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = WNDR3700_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = WNDR3700_GPIO_BTN_RESET,
+ .active_low = 1,
+ }, {
+ .desc = "wps",
+ .type = EV_KEY,
+ .code = KEY_WPS_BUTTON,
+ .debounce_interval = WNDR3700_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = WNDR3700_GPIO_BTN_WPS,
+ .active_low = 1,
+ }, {
+ .desc = "wifi",
+ .type = EV_KEY,
+ .code = BTN_2,
+ .debounce_interval = WNDR3700_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = WNDR3700_GPIO_BTN_WIFI,
+ .active_low = 1,
+ }
+};
+
+static struct rtl8366_platform_data wndr3700_rtl8366s_data = {
+ .gpio_sda = WNDR3700_GPIO_RTL8366_SDA,
+ .gpio_sck = WNDR3700_GPIO_RTL8366_SCK,
+};
+
+static struct platform_device wndr3700_rtl8366s_device = {
+ .name = RTL8366S_DRIVER_NAME,
+ .id = -1,
+ .dev = {
+ .platform_data = &wndr3700_rtl8366s_data,
+ }
+};
+
+static void __init wndr3700_setup(void)
+{
+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
+
+ /*
+ * The eth0 and wmac0 interfaces share the same MAC address which
+ * can lead to problems if operated unbridged. Set the locally
+ * administered bit on the eth0 MAC to make it unique.
+ */
+ ath79_init_local_mac(ath79_eth0_data.mac_addr,
+ art + WNDR3700_ETH0_MAC_OFFSET);
+ ath79_eth0_pll_data.pll_1000 = 0x11110000;
+ ath79_eth0_data.mii_bus_dev = &wndr3700_rtl8366s_device.dev;
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+ ath79_eth0_data.speed = SPEED_1000;
+ ath79_eth0_data.duplex = DUPLEX_FULL;
+
+ ath79_init_mac(ath79_eth1_data.mac_addr,
+ art + WNDR3700_ETH1_MAC_OFFSET, 0);
+ ath79_eth1_pll_data.pll_1000 = 0x11110000;
+ ath79_eth1_data.mii_bus_dev = &wndr3700_rtl8366s_device.dev;
+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+ ath79_eth1_data.phy_mask = 0x10;
+
+ ath79_register_eth(0);
+ ath79_register_eth(1);
+
+ ath79_register_usb();
+
+ ath79_register_m25p80(NULL);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(wndr3700_leds_gpio),
+ wndr3700_leds_gpio);
+
+ ath79_register_gpio_keys_polled(-1, WNDR3700_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(wndr3700_gpio_keys),
+ wndr3700_gpio_keys);
+
+ platform_device_register(&wndr3700_rtl8366s_device);
+ platform_device_register_simple("wndr3700-led-usb", -1, NULL, 0);
+
+ ap9x_pci_setup_wmac_led_pin(0, 5);
+ ap9x_pci_setup_wmac_led_pin(1, 5);
+
+ /* 2.4 GHz uses the first fixed antenna group (1, 0, 1, 0) */
+ ap9x_pci_setup_wmac_gpio(0, (0xf << 6), (0xa << 6));
+
+ /* 5 GHz uses the second fixed antenna group (0, 1, 1, 0) */
+ ap9x_pci_setup_wmac_gpio(1, (0xf << 6), (0x6 << 6));
+
+ ap94_pci_init(art + WNDR3700_CALDATA0_OFFSET,
+ art + WNDR3700_WMAC0_MAC_OFFSET,
+ art + WNDR3700_CALDATA1_OFFSET,
+ art + WNDR3700_WMAC1_MAC_OFFSET);
+}
+
+MIPS_MACHINE(ATH79_MACH_WNDR3700, "WNDR3700",
+ "NETGEAR WNDR3700/WNDR3800/WNDRMAC",
+ wndr3700_setup);
--- /dev/null
+/*
+ * NETGEAR WNR2000 board support
+ *
+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ * Copyright (C) 2008-2009 Andy Boyett <agb@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "dev-wmac.h"
+#include "machtypes.h"
+
+#define WNR2000_GPIO_LED_PWR_GREEN 14
+#define WNR2000_GPIO_LED_PWR_AMBER 7
+#define WNR2000_GPIO_LED_WPS 4
+#define WNR2000_GPIO_LED_WLAN 6
+#define WNR2000_GPIO_BTN_RESET 21
+#define WNR2000_GPIO_BTN_WPS 8
+
+#define WNR2000_KEYS_POLL_INTERVAL 20 /* msecs */
+#define WNR2000_KEYS_DEBOUNCE_INTERVAL (3 * WNR2000_KEYS_POLL_INTERVAL)
+
+static struct mtd_partition wnr2000_partitions[] = {
+ {
+ .name = "u-boot",
+ .offset = 0,
+ .size = 0x040000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "u-boot-env",
+ .offset = 0x040000,
+ .size = 0x010000,
+ }, {
+ .name = "rootfs",
+ .offset = 0x050000,
+ .size = 0x240000,
+ }, {
+ .name = "user-config",
+ .offset = 0x290000,
+ .size = 0x010000,
+ }, {
+ .name = "uImage",
+ .offset = 0x2a0000,
+ .size = 0x120000,
+ }, {
+ .name = "language_table",
+ .offset = 0x3c0000,
+ .size = 0x020000,
+ }, {
+ .name = "rootfs_checksum",
+ .offset = 0x3e0000,
+ .size = 0x010000,
+ }, {
+ .name = "art",
+ .offset = 0x3f0000,
+ .size = 0x010000,
+ .mask_flags = MTD_WRITEABLE,
+ }
+};
+
+static struct flash_platform_data wnr2000_flash_data = {
+ .parts = wnr2000_partitions,
+ .nr_parts = ARRAY_SIZE(wnr2000_partitions),
+};
+
+static struct gpio_led wnr2000_leds_gpio[] __initdata = {
+ {
+ .name = "wnr2000:green:power",
+ .gpio = WNR2000_GPIO_LED_PWR_GREEN,
+ .active_low = 1,
+ }, {
+ .name = "wnr2000:amber:power",
+ .gpio = WNR2000_GPIO_LED_PWR_AMBER,
+ .active_low = 1,
+ }, {
+ .name = "wnr2000:green:wps",
+ .gpio = WNR2000_GPIO_LED_WPS,
+ .active_low = 1,
+ }, {
+ .name = "wnr2000:blue:wlan",
+ .gpio = WNR2000_GPIO_LED_WLAN,
+ .active_low = 1,
+ }
+};
+
+static struct gpio_keys_button wnr2000_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = WNR2000_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = WNR2000_GPIO_BTN_RESET,
+ }, {
+ .desc = "wps",
+ .type = EV_KEY,
+ .code = KEY_WPS_BUTTON,
+ .debounce_interval = WNR2000_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = WNR2000_GPIO_BTN_WPS,
+ }
+};
+
+static void __init wnr2000_setup(void)
+{
+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);
+
+ ath79_register_mdio(0, 0x0);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, eeprom, 0);
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
+ ath79_eth0_data.speed = SPEED_100;
+ ath79_eth0_data.duplex = DUPLEX_FULL;
+ ath79_eth0_data.has_ar8216 = 1;
+
+ ath79_init_mac(ath79_eth1_data.mac_addr, eeprom, 1);
+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
+ ath79_eth1_data.phy_mask = 0x10;
+
+ ath79_register_eth(0);
+ ath79_register_eth(1);
+
+ ath79_register_m25p80(&wnr2000_flash_data);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(wnr2000_leds_gpio),
+ wnr2000_leds_gpio);
+
+ ath79_register_gpio_keys_polled(-1, WNR2000_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(wnr2000_gpio_keys),
+ wnr2000_gpio_keys);
+
+ ath79_register_wmac(eeprom, NULL);
+}
+
+MIPS_MACHINE(ATH79_MACH_WNR2000, "WNR2000", "NETGEAR WNR2000", wnr2000_setup);
--- /dev/null
+/*
+ * Compex WP543/WPJ543 board support
+ *
+ * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <asm/mach-ath79/ar71xx_regs.h>
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "dev-usb.h"
+#include "machtypes.h"
+#include "pci.h"
+
+#define WP543_GPIO_SW6 2
+#define WP543_GPIO_LED_1 3
+#define WP543_GPIO_LED_2 4
+#define WP543_GPIO_LED_WLAN 5
+#define WP543_GPIO_LED_CONN 6
+#define WP543_GPIO_LED_DIAG 7
+#define WP543_GPIO_SW4 8
+
+#define WP543_KEYS_POLL_INTERVAL 20 /* msecs */
+#define WP543_KEYS_DEBOUNCE_INTERVAL (3 * WP543_KEYS_POLL_INTERVAL)
+
+static struct gpio_led wp543_leds_gpio[] __initdata = {
+ {
+ .name = "wp543:green:led1",
+ .gpio = WP543_GPIO_LED_1,
+ .active_low = 1,
+ }, {
+ .name = "wp543:green:led2",
+ .gpio = WP543_GPIO_LED_2,
+ .active_low = 1,
+ }, {
+ .name = "wp543:green:wlan",
+ .gpio = WP543_GPIO_LED_WLAN,
+ .active_low = 1,
+ }, {
+ .name = "wp543:green:conn",
+ .gpio = WP543_GPIO_LED_CONN,
+ .active_low = 1,
+ }, {
+ .name = "wp543:green:diag",
+ .gpio = WP543_GPIO_LED_DIAG,
+ .active_low = 1,
+ }
+};
+
+static struct gpio_keys_button wp543_gpio_keys[] __initdata = {
+ {
+ .desc = "sw6",
+ .type = EV_KEY,
+ .code = BTN_0,
+ .debounce_interval = WP543_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = WP543_GPIO_SW6,
+ }, {
+ .desc = "sw4",
+ .type = EV_KEY,
+ .code = BTN_1,
+ .debounce_interval = WP543_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = WP543_GPIO_SW4,
+ }
+};
+
+static const char *wp543_part_probes[] = {
+ "MyLoader",
+ NULL,
+};
+
+static struct flash_platform_data wp543_flash_data = {
+ .part_probes = wp543_part_probes,
+};
+
+static void __init wp543_setup(void)
+{
+ ath79_register_m25p80(&wp543_flash_data);
+
+ ath79_register_mdio(0, 0xfffffff0);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
+ ath79_eth0_data.phy_mask = 0x0f;
+ ath79_eth0_data.reset_bit = AR71XX_RESET_GE0_MAC |
+ AR71XX_RESET_GE0_PHY;
+ ath79_register_eth(0);
+
+ ath79_register_usb();
+ ath79_register_pci();
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(wp543_leds_gpio),
+ wp543_leds_gpio);
+
+ ath79_register_gpio_keys_polled(-1, WP543_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(wp543_gpio_keys),
+ wp543_gpio_keys);
+}
+
+MIPS_MACHINE(ATH79_MACH_WP543, "WP543", "Compex WP543", wp543_setup);
--- /dev/null
+/*
+ * Linksys WRT160NL board support
+ *
+ * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "dev-usb.h"
+#include "dev-wmac.h"
+#include "nvram.h"
+#include "machtypes.h"
+
+#define WRT160NL_GPIO_LED_POWER 14
+#define WRT160NL_GPIO_LED_WPS_AMBER 9
+#define WRT160NL_GPIO_LED_WPS_BLUE 8
+#define WRT160NL_GPIO_LED_WLAN 6
+
+#define WRT160NL_GPIO_BTN_WPS 7
+#define WRT160NL_GPIO_BTN_RESET 21
+
+#define WRT160NL_KEYS_POLL_INTERVAL 20 /* msecs */
+#define WRT160NL_KEYS_DEBOUNCE_INTERVAL (3 * WRT160NL_KEYS_POLL_INTERVAL)
+
+#define WRT160NL_NVRAM_ADDR 0x1f7e0000
+#define WRT160NL_NVRAM_SIZE 0x10000
+
+static const char *wrt160nl_part_probes[] = {
+ "wrt160nl",
+ NULL,
+};
+
+static struct flash_platform_data wrt160nl_flash_data = {
+ .part_probes = wrt160nl_part_probes,
+};
+
+static struct gpio_led wrt160nl_leds_gpio[] __initdata = {
+ {
+ .name = "wrt160nl:blue:power",
+ .gpio = WRT160NL_GPIO_LED_POWER,
+ .active_low = 1,
+ .default_trigger = "default-on",
+ }, {
+ .name = "wrt160nl:amber:wps",
+ .gpio = WRT160NL_GPIO_LED_WPS_AMBER,
+ .active_low = 1,
+ }, {
+ .name = "wrt160nl:blue:wps",
+ .gpio = WRT160NL_GPIO_LED_WPS_BLUE,
+ .active_low = 1,
+ }, {
+ .name = "wrt160nl:blue:wlan",
+ .gpio = WRT160NL_GPIO_LED_WLAN,
+ .active_low = 1,
+ }
+};
+
+static struct gpio_keys_button wrt160nl_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = WRT160NL_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = WRT160NL_GPIO_BTN_RESET,
+ .active_low = 1,
+ }, {
+ .desc = "wps",
+ .type = EV_KEY,
+ .code = KEY_WPS_BUTTON,
+ .debounce_interval = WRT160NL_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = WRT160NL_GPIO_BTN_WPS,
+ .active_low = 1,
+ }
+};
+
+static void __init wrt160nl_setup(void)
+{
+ const char *nvram = (char *) KSEG1ADDR(WRT160NL_NVRAM_ADDR);
+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);
+ u8 mac[6];
+
+ if (ath79_nvram_parse_mac_addr(nvram, WRT160NL_NVRAM_SIZE,
+ "lan_hwaddr=", mac) == 0) {
+ ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
+ ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
+ }
+
+ ath79_register_mdio(0, 0x0);
+
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
+ ath79_eth0_data.phy_mask = 0x01;
+
+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
+ ath79_eth1_data.phy_mask = 0x10;
+
+ ath79_register_eth(0);
+ ath79_register_eth(1);
+
+ ath79_register_m25p80(&wrt160nl_flash_data);
+
+ ath79_register_usb();
+
+ if (ath79_nvram_parse_mac_addr(nvram, WRT160NL_NVRAM_SIZE,
+ "wl0_hwaddr=", mac) == 0)
+ ath79_register_wmac(eeprom, mac);
+ else
+ ath79_register_wmac(eeprom, NULL);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(wrt160nl_leds_gpio),
+ wrt160nl_leds_gpio);
+
+ ath79_register_gpio_keys_polled(-1, WRT160NL_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(wrt160nl_gpio_keys),
+ wrt160nl_gpio_keys);
+}
+
+MIPS_MACHINE(ATH79_MACH_WRT160NL, "WRT160NL", "Linksys WRT160NL",
+ wrt160nl_setup);
--- /dev/null
+/*
+ * Linksys WRT400N board support
+ *
+ * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2009 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-ap9x-pci.h"
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "machtypes.h"
+
+#define WRT400N_GPIO_LED_POWER 1
+#define WRT400N_GPIO_LED_WPS_BLUE 4
+#define WRT400N_GPIO_LED_WPS_AMBER 5
+#define WRT400N_GPIO_LED_WLAN 6
+
+#define WRT400N_GPIO_BTN_RESET 8
+#define WRT400N_GPIO_BTN_WLSEC 3
+
+#define WRT400N_KEYS_POLL_INTERVAL 20 /* msecs */
+#define WRT400N_KEYS_DEBOUNE_INTERVAL (3 * WRT400N_KEYS_POLL_INTERVAL)
+
+#define WRT400N_MAC_ADDR_OFFSET 0x120c
+#define WRT400N_CALDATA0_OFFSET 0x1000
+#define WRT400N_CALDATA1_OFFSET 0x5000
+
+static struct mtd_partition wrt400n_partitions[] = {
+ {
+ .name = "uboot",
+ .offset = 0,
+ .size = 0x030000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "env",
+ .offset = 0x030000,
+ .size = 0x010000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "linux",
+ .offset = 0x040000,
+ .size = 0x140000,
+ }, {
+ .name = "rootfs",
+ .offset = 0x180000,
+ .size = 0x630000,
+ }, {
+ .name = "nvram",
+ .offset = 0x7b0000,
+ .size = 0x010000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "factory",
+ .offset = 0x7c0000,
+ .size = 0x010000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "language",
+ .offset = 0x7d0000,
+ .size = 0x020000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "caldata",
+ .offset = 0x7f0000,
+ .size = 0x010000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "firmware",
+ .offset = 0x040000,
+ .size = 0x770000,
+ }
+};
+
+static struct flash_platform_data wrt400n_flash_data = {
+ .parts = wrt400n_partitions,
+ .nr_parts = ARRAY_SIZE(wrt400n_partitions),
+};
+
+static struct gpio_led wrt400n_leds_gpio[] __initdata = {
+ {
+ .name = "wrt400n:blue:wps",
+ .gpio = WRT400N_GPIO_LED_WPS_BLUE,
+ .active_low = 1,
+ }, {
+ .name = "wrt400n:amber:wps",
+ .gpio = WRT400N_GPIO_LED_WPS_AMBER,
+ .active_low = 1,
+ }, {
+ .name = "wrt400n:blue:wlan",
+ .gpio = WRT400N_GPIO_LED_WLAN,
+ .active_low = 1,
+ }, {
+ .name = "wrt400n:blue:power",
+ .gpio = WRT400N_GPIO_LED_POWER,
+ .active_low = 0,
+ .default_trigger = "default-on",
+ }
+};
+
+static struct gpio_keys_button wrt400n_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = WRT400N_KEYS_DEBOUNE_INTERVAL,
+ .gpio = WRT400N_GPIO_BTN_RESET,
+ .active_low = 1,
+ }, {
+ .desc = "wlsec",
+ .type = EV_KEY,
+ .code = KEY_WPS_BUTTON,
+ .debounce_interval = WRT400N_KEYS_DEBOUNE_INTERVAL,
+ .gpio = WRT400N_GPIO_BTN_WLSEC,
+ .active_low = 1,
+ }
+};
+
+static void __init wrt400n_setup(void)
+{
+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
+ u8 *mac = art + WRT400N_MAC_ADDR_OFFSET;
+
+ ath79_register_mdio(0, 0x0);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
+ ath79_eth0_data.speed = SPEED_100;
+ ath79_eth0_data.duplex = DUPLEX_FULL;
+
+ ath79_init_mac(ath79_eth1_data.mac_addr, mac, 2);
+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
+ ath79_eth1_data.phy_mask = 0x10;
+
+ ath79_register_eth(0);
+ ath79_register_eth(1);
+
+ ath79_register_m25p80(&wrt400n_flash_data);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(wrt400n_leds_gpio),
+ wrt400n_leds_gpio);
+
+ ath79_register_gpio_keys_polled(-1, WRT400N_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(wrt400n_gpio_keys),
+ wrt400n_gpio_keys);
+
+ ap94_pci_init(art + WRT400N_CALDATA0_OFFSET, NULL,
+ art + WRT400N_CALDATA1_OFFSET, NULL);
+}
+
+MIPS_MACHINE(ATH79_MACH_WRT400N, "WRT400N", "Linksys WRT400N", wrt400n_setup);
--- /dev/null
+/*
+ * Buffalo WZR-HP-AG300H board support
+ *
+ * Copyright (C) 2011 Felix Fietkau <nbd@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-eth.h"
+#include "dev-ap9x-pci.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "dev-usb.h"
+#include "machtypes.h"
+
+#define WZRHPAG300H_MAC_OFFSET 0x20c
+#define WZRHPAG300H_KEYS_POLL_INTERVAL 20 /* msecs */
+#define WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL (3 * WZRHPAG300H_KEYS_POLL_INTERVAL)
+
+static struct mtd_partition wzrhpag300h_flash_partitions[] = {
+ {
+ .name = "u-boot",
+ .offset = 0,
+ .size = 0x0040000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "u-boot-env",
+ .offset = 0x0040000,
+ .size = 0x0010000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "art",
+ .offset = 0x0050000,
+ .size = 0x0010000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "kernel",
+ .offset = 0x0060000,
+ .size = 0x0100000,
+ }, {
+ .name = "rootfs",
+ .offset = 0x0160000,
+ .size = 0x1e90000,
+ }, {
+ .name = "user_property",
+ .offset = 0x1ff0000,
+ .size = 0x0010000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "firmware",
+ .offset = 0x0060000,
+ .size = 0x1f90000,
+ }
+};
+
+static struct flash_platform_data wzrhpag300h_flash_data = {
+ .parts = wzrhpag300h_flash_partitions,
+ .nr_parts = ARRAY_SIZE(wzrhpag300h_flash_partitions),
+};
+
+static struct gpio_led wzrhpag300h_leds_gpio[] __initdata = {
+ {
+ .name = "buffalo:red:diag",
+ .gpio = 1,
+ .active_low = 1,
+ },
+};
+
+static struct gpio_keys_button wzrhpag300h_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = 11,
+ .active_low = 1,
+ }, {
+ .desc = "usb",
+ .type = EV_KEY,
+ .code = BTN_2,
+ .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = 3,
+ .active_low = 1,
+ }, {
+ .desc = "aoss",
+ .type = EV_KEY,
+ .code = KEY_WPS_BUTTON,
+ .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = 5,
+ .active_low = 1,
+ }, {
+ .desc = "router_auto",
+ .type = EV_KEY,
+ .code = BTN_6,
+ .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = 6,
+ .active_low = 1,
+ }, {
+ .desc = "router_off",
+ .type = EV_KEY,
+ .code = BTN_5,
+ .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = 7,
+ .active_low = 1,
+ }
+};
+
+static void __init wzrhpag300h_setup(void)
+{
+ u8 *eeprom1 = (u8 *) KSEG1ADDR(0x1f051000);
+ u8 *eeprom2 = (u8 *) KSEG1ADDR(0x1f055000);
+ u8 *mac1 = eeprom1 + WZRHPAG300H_MAC_OFFSET;
+ u8 *mac2 = eeprom2 + WZRHPAG300H_MAC_OFFSET;
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
+ ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 1);
+
+ ath79_register_mdio(0, ~(BIT(0) | BIT(4)));
+
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+ ath79_eth0_data.speed = SPEED_1000;
+ ath79_eth0_data.duplex = DUPLEX_FULL;
+ ath79_eth0_data.phy_mask = BIT(0);
+
+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+ ath79_eth1_data.phy_mask = BIT(4);
+
+ ath79_register_eth(0);
+ ath79_register_eth(1);
+
+ ath79_register_usb();
+ gpio_request(2, "usb");
+ gpio_direction_output(2, 1);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(wzrhpag300h_leds_gpio),
+ wzrhpag300h_leds_gpio);
+
+ ath79_register_gpio_keys_polled(-1, WZRHPAG300H_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(wzrhpag300h_gpio_keys),
+ wzrhpag300h_gpio_keys);
+
+ ath79_register_m25p80_multi(&wzrhpag300h_flash_data);
+
+ ap94_pci_init(eeprom1, mac1, eeprom2, mac2);
+}
+
+MIPS_MACHINE(ATH79_MACH_WZR_HP_AG300H, "WZR-HP-AG300H",
+ "Buffalo WZR-HP-AG300H", wzrhpag300h_setup);
+
--- /dev/null
+/*
+ * Buffalo WZR-HP-G300NH board support
+ *
+ * Copyright (C) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/nxp_74hc153.h>
+#include <linux/rtl8366.h>
+
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-usb.h"
+#include "dev-wmac.h"
+#include "machtypes.h"
+
+#define WZRHPG300NH_GPIO_LED_USB 0
+#define WZRHPG300NH_GPIO_LED_DIAG 1
+#define WZRHPG300NH_GPIO_LED_WIRELESS 6
+#define WZRHPG300NH_GPIO_LED_SECURITY 17
+#define WZRHPG300NH_GPIO_LED_ROUTER 18
+
+#define WZRHPG300NH_GPIO_RTL8366_SDA 19
+#define WZRHPG300NH_GPIO_RTL8366_SCK 20
+
+#define WZRHPG300NH_GPIO_74HC153_S0 9
+#define WZRHPG300NH_GPIO_74HC153_S1 11
+#define WZRHPG300NH_GPIO_74HC153_1Y 12
+#define WZRHPG300NH_GPIO_74HC153_2Y 14
+
+#define WZRHPG300NH_GPIO_EXP_BASE 32
+#define WZRHPG300NH_GPIO_BTN_AOSS (WZRHPG300NH_GPIO_EXP_BASE + 0)
+#define WZRHPG300NH_GPIO_BTN_RESET (WZRHPG300NH_GPIO_EXP_BASE + 1)
+#define WZRHPG300NH_GPIO_BTN_ROUTER_ON (WZRHPG300NH_GPIO_EXP_BASE + 2)
+#define WZRHPG300NH_GPIO_BTN_QOS_ON (WZRHPG300NH_GPIO_EXP_BASE + 3)
+#define WZRHPG300NH_GPIO_BTN_USB (WZRHPG300NH_GPIO_EXP_BASE + 5)
+#define WZRHPG300NH_GPIO_BTN_ROUTER_AUTO (WZRHPG300NH_GPIO_EXP_BASE + 6)
+#define WZRHPG300NH_GPIO_BTN_QOS_OFF (WZRHPG300NH_GPIO_EXP_BASE + 7)
+
+#define WZRHPG300NH_KEYS_POLL_INTERVAL 20 /* msecs */
+#define WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL (3 * WZRHPG300NH_KEYS_POLL_INTERVAL)
+
+#define WZRHPG300NH_MAC_OFFSET 0x20c
+
+static struct mtd_partition wzrhpg300nh_flash_partitions[] = {
+ {
+ .name = "u-boot",
+ .offset = 0,
+ .size = 0x0040000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "u-boot-env",
+ .offset = 0x0040000,
+ .size = 0x0020000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "kernel",
+ .offset = 0x0060000,
+ .size = 0x0100000,
+ }, {
+ .name = "rootfs",
+ .offset = 0x0160000,
+ .size = 0x1e60000,
+ }, {
+ .name = "user_property",
+ .offset = 0x1fc0000,
+ .size = 0x0020000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "art",
+ .offset = 0x1fe0000,
+ .size = 0x0020000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "firmware",
+ .offset = 0x0060000,
+ .size = 0x1f60000,
+ }
+};
+
+static struct physmap_flash_data wzrhpg300nh_flash_data = {
+ .width = 2,
+ .parts = wzrhpg300nh_flash_partitions,
+ .nr_parts = ARRAY_SIZE(wzrhpg300nh_flash_partitions),
+};
+
+#define WZRHPG300NH_FLASH_BASE 0x1e000000
+#define WZRHPG300NH_FLASH_SIZE (32 * 1024 * 1024)
+
+static struct resource wzrhpg300nh_flash_resources[] = {
+ [0] = {
+ .start = WZRHPG300NH_FLASH_BASE,
+ .end = WZRHPG300NH_FLASH_BASE + WZRHPG300NH_FLASH_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device wzrhpg300nh_flash_device = {
+ .name = "physmap-flash",
+ .id = -1,
+ .resource = wzrhpg300nh_flash_resources,
+ .num_resources = ARRAY_SIZE(wzrhpg300nh_flash_resources),
+ .dev = {
+ .platform_data = &wzrhpg300nh_flash_data,
+ }
+};
+
+static struct gpio_led wzrhpg300nh_leds_gpio[] __initdata = {
+ {
+ .name = "buffalo:orange:security",
+ .gpio = WZRHPG300NH_GPIO_LED_SECURITY,
+ .active_low = 1,
+ }, {
+ .name = "buffalo:green:wireless",
+ .gpio = WZRHPG300NH_GPIO_LED_WIRELESS,
+ .active_low = 1,
+ }, {
+ .name = "buffalo:green:router",
+ .gpio = WZRHPG300NH_GPIO_LED_ROUTER,
+ .active_low = 1,
+ }, {
+ .name = "buffalo:red:diag",
+ .gpio = WZRHPG300NH_GPIO_LED_DIAG,
+ .active_low = 1,
+ }, {
+ .name = "buffalo:blue:usb",
+ .gpio = WZRHPG300NH_GPIO_LED_USB,
+ .active_low = 1,
+ }
+};
+
+static struct gpio_keys_button wzrhpg300nh_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = WZRHPG300NH_GPIO_BTN_RESET,
+ .active_low = 1,
+ }, {
+ .desc = "aoss",
+ .type = EV_KEY,
+ .code = KEY_WPS_BUTTON,
+ .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = WZRHPG300NH_GPIO_BTN_AOSS,
+ .active_low = 1,
+ }, {
+ .desc = "usb",
+ .type = EV_KEY,
+ .code = BTN_2,
+ .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = WZRHPG300NH_GPIO_BTN_USB,
+ .active_low = 1,
+ }, {
+ .desc = "qos_on",
+ .type = EV_KEY,
+ .code = BTN_3,
+ .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = WZRHPG300NH_GPIO_BTN_QOS_ON,
+ .active_low = 0,
+ }, {
+ .desc = "qos_off",
+ .type = EV_KEY,
+ .code = BTN_4,
+ .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = WZRHPG300NH_GPIO_BTN_QOS_OFF,
+ .active_low = 0,
+ }, {
+ .desc = "router_on",
+ .type = EV_KEY,
+ .code = BTN_5,
+ .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = WZRHPG300NH_GPIO_BTN_ROUTER_ON,
+ .active_low = 0,
+ }, {
+ .desc = "router_auto",
+ .type = EV_KEY,
+ .code = BTN_6,
+ .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = WZRHPG300NH_GPIO_BTN_ROUTER_AUTO,
+ .active_low = 0,
+ }
+};
+
+static struct nxp_74hc153_platform_data wzrhpg300nh_74hc153_data = {
+ .gpio_base = WZRHPG300NH_GPIO_EXP_BASE,
+ .gpio_pin_s0 = WZRHPG300NH_GPIO_74HC153_S0,
+ .gpio_pin_s1 = WZRHPG300NH_GPIO_74HC153_S1,
+ .gpio_pin_1y = WZRHPG300NH_GPIO_74HC153_1Y,
+ .gpio_pin_2y = WZRHPG300NH_GPIO_74HC153_2Y,
+};
+
+static struct platform_device wzrhpg300nh_74hc153_device = {
+ .name = NXP_74HC153_DRIVER_NAME,
+ .id = -1,
+ .dev = {
+ .platform_data = &wzrhpg300nh_74hc153_data,
+ }
+};
+
+static struct rtl8366_platform_data wzrhpg300nh_rtl8366_data = {
+ .gpio_sda = WZRHPG300NH_GPIO_RTL8366_SDA,
+ .gpio_sck = WZRHPG300NH_GPIO_RTL8366_SCK,
+};
+
+static struct platform_device wzrhpg300nh_rtl8366s_device = {
+ .name = RTL8366S_DRIVER_NAME,
+ .id = -1,
+ .dev = {
+ .platform_data = &wzrhpg300nh_rtl8366_data,
+ }
+};
+
+static struct platform_device wzrhpg300nh_rtl8366rb_device = {
+ .name = RTL8366RB_DRIVER_NAME,
+ .id = -1,
+ .dev = {
+ .platform_data = &wzrhpg300nh_rtl8366_data,
+ }
+};
+
+static void __init wzrhpg300nh_setup(void)
+{
+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000);
+ u8 *mac = eeprom + WZRHPG300NH_MAC_OFFSET;
+ bool hasrtl8366rb = false;
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
+ ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
+
+ if (rtl8366_smi_detect(&wzrhpg300nh_rtl8366_data) == RTL8366_TYPE_RB)
+ hasrtl8366rb = true;
+
+ if (hasrtl8366rb) {
+ ath79_eth0_pll_data.pll_1000 = 0x1f000000;
+ ath79_eth0_data.mii_bus_dev = &wzrhpg300nh_rtl8366rb_device.dev;
+ ath79_eth1_pll_data.pll_1000 = 0x100;
+ ath79_eth1_data.mii_bus_dev = &wzrhpg300nh_rtl8366rb_device.dev;
+ } else {
+ ath79_eth0_pll_data.pll_1000 = 0x1e000100;
+ ath79_eth0_data.mii_bus_dev = &wzrhpg300nh_rtl8366s_device.dev;
+ ath79_eth1_pll_data.pll_1000 = 0x1e000100;
+ ath79_eth1_data.mii_bus_dev = &wzrhpg300nh_rtl8366s_device.dev;
+ }
+
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+ ath79_eth0_data.speed = SPEED_1000;
+ ath79_eth0_data.duplex = DUPLEX_FULL;
+
+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+ ath79_eth1_data.phy_mask = 0x10;
+
+ ath79_register_eth(0);
+ ath79_register_eth(1);
+
+ ath79_register_usb();
+ ath79_register_wmac(eeprom, NULL);
+
+ platform_device_register(&wzrhpg300nh_74hc153_device);
+ platform_device_register(&wzrhpg300nh_flash_device);
+
+ if (hasrtl8366rb)
+ platform_device_register(&wzrhpg300nh_rtl8366rb_device);
+ else
+ platform_device_register(&wzrhpg300nh_rtl8366s_device);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(wzrhpg300nh_leds_gpio),
+ wzrhpg300nh_leds_gpio);
+
+ ath79_register_gpio_keys_polled(-1, WZRHPG300NH_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(wzrhpg300nh_gpio_keys),
+ wzrhpg300nh_gpio_keys);
+
+}
+
+MIPS_MACHINE(ATH79_MACH_WZR_HP_G300NH, "WZR-HP-G300NH",
+ "Buffalo WZR-HP-G300NH", wzrhpg300nh_setup);
--- /dev/null
+/*
+ * Buffalo WZR-HP-G300NH2 board support
+ *
+ * Copyright (C) 2011 Felix Fietkau <nbd@openwrt.org>
+ * Copyright (C) 2011 Mark Deneen <mdeneen@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-ap9x-pci.h"
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "dev-usb.h"
+#include "machtypes.h"
+
+#define WZRHPG300NH2_MAC_OFFSET 0x20c
+#define WZRHPG300NH2_KEYS_POLL_INTERVAL 20 /* msecs */
+#define WZRHPG300NH2_KEYS_DEBOUNCE_INTERVAL (3 * WZRHPG300NH2_KEYS_POLL_INTERVAL)
+
+static struct mtd_partition wzrhpg300nh2_flash_partitions[] = {
+ {
+ .name = "u-boot",
+ .offset = 0,
+ .size = 0x0040000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "u-boot-env",
+ .offset = 0x0040000,
+ .size = 0x0010000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "art",
+ .offset = 0x0050000,
+ .size = 0x0010000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "kernel",
+ .offset = 0x0060000,
+ .size = 0x0100000,
+ }, {
+ .name = "rootfs",
+ .offset = 0x0160000,
+ .size = 0x1e90000,
+ }, {
+ .name = "user_property",
+ .offset = 0x1ff0000,
+ .size = 0x0010000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "firmware",
+ .offset = 0x0060000,
+ .size = 0x1f90000,
+ }
+};
+
+static struct flash_platform_data wzrhpg300nh2_flash_data = {
+ .parts = wzrhpg300nh2_flash_partitions,
+ .nr_parts = ARRAY_SIZE(wzrhpg300nh2_flash_partitions),
+};
+
+static struct gpio_led wzrhpg300nh2_leds_gpio[] __initdata = {
+ {
+ .name = "buffalo:red:diag",
+ .gpio = 16,
+ .active_low = 1,
+ },
+};
+
+static struct gpio_led wzrhpg300nh2_wmac_leds_gpio[] = {
+ {
+ .name = "buffalo:blue:usb",
+ .gpio = 4,
+ .active_low = 1,
+ },
+ {
+ .name = "buffalo:orange:security",
+ .gpio = 6,
+ .active_low = 1,
+ },
+ {
+ .name = "buffalo:green:router",
+ .gpio = 7,
+ .active_low = 1,
+ },
+ {
+ .name = "buffalo:blue:movie_engine_on",
+ .gpio = 8,
+ .active_low = 1,
+ },
+ {
+ .name = "buffalo:blue:movie_engine_off",
+ .gpio = 9,
+ .active_low = 1,
+ },
+};
+
+/* The AOSS button is wmac gpio 12 */
+static struct gpio_keys_button wzrhpg300nh2_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = WZRHPG300NH2_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = 1,
+ .active_low = 1,
+ }, {
+ .desc = "usb",
+ .type = EV_KEY,
+ .code = BTN_2,
+ .debounce_interval = WZRHPG300NH2_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = 7,
+ .active_low = 1,
+ }, {
+ .desc = "qos",
+ .type = EV_KEY,
+ .code = BTN_3,
+ .debounce_interval = WZRHPG300NH2_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = 11,
+ .active_low = 0,
+ }, {
+ .desc = "router_on",
+ .type = EV_KEY,
+ .code = BTN_5,
+ .debounce_interval = WZRHPG300NH2_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = 8,
+ .active_low = 0,
+ },
+};
+
+static void __init wzrhpg300nh2_setup(void)
+{
+
+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1f051000);
+ u8 *mac0 = eeprom + WZRHPG300NH2_MAC_OFFSET;
+ /* There is an eth1 but it is not connected to the switch */
+
+ ath79_register_m25p80_multi(&wzrhpg300nh2_flash_data);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, mac0, 0);
+ ath79_register_mdio(0, ~(BIT(0)));
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, mac0, 0);
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+ ath79_eth0_data.speed = SPEED_1000;
+ ath79_eth0_data.duplex = DUPLEX_FULL;
+ ath79_eth0_data.phy_mask = BIT(0);
+
+ ath79_register_eth(0);
+ ath79_register_usb();
+ /* gpio13 is usb power. Turn it on. */
+ gpio_request(13, "usb");
+ gpio_direction_output(13, 1);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(wzrhpg300nh2_leds_gpio),
+ wzrhpg300nh2_leds_gpio);
+ ath79_register_gpio_keys_polled(-1, WZRHPG300NH2_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(wzrhpg300nh2_gpio_keys),
+ wzrhpg300nh2_gpio_keys);
+ ap9x_pci_setup_wmac_led_pin(0, 5);
+ ap9x_pci_setup_wmac_leds(0, wzrhpg300nh2_wmac_leds_gpio,
+ ARRAY_SIZE(wzrhpg300nh2_wmac_leds_gpio));
+
+ ap91_pci_init(eeprom, mac0);
+}
+
+MIPS_MACHINE(ATH79_MACH_WZR_HP_G300NH2, "WZR-HP-G300NH2",
+ "Buffalo WZR-HP-G300NH2", wzrhpg300nh2_setup);
--- /dev/null
+/*
+ * Buffalo WZR-HP-G450G board support
+ *
+ * Copyright (C) 2011 Felix Fietkau <nbd@openwrt.org>
+ * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <asm/mach-ath79/gpio.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach-ath79/ath79.h>
+
+#include "dev-eth.h"
+#include "dev-m25p80.h"
+#include "dev-ap9x-pci.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-usb.h"
+#include "machtypes.h"
+
+#define WZRHPG450H_KEYS_POLL_INTERVAL 20 /* msecs */
+#define WZRHPG450H_KEYS_DEBOUNCE_INTERVAL (3 * WZRHPG450H_KEYS_POLL_INTERVAL)
+
+static struct mtd_partition wzrhpg450h_partitions[] = {
+ {
+ .name = "u-boot",
+ .offset = 0,
+ .size = 0x0040000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "u-boot-env",
+ .offset = 0x0040000,
+ .size = 0x0010000,
+ }, {
+ .name = "ART",
+ .offset = 0x0050000,
+ .size = 0x0010000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "uImage",
+ .offset = 0x0060000,
+ .size = 0x0100000,
+ }, {
+ .name = "rootfs",
+ .offset = 0x0160000,
+ .size = 0x1e80000,
+ }, {
+ .name = "user_property",
+ .offset = 0x1fe0000,
+ .size = 0x0020000,
+ }, {
+ .name = "firmware",
+ .offset = 0x0060000,
+ .size = 0x1f80000,
+ }
+};
+
+static struct flash_platform_data wzrhpg450h_flash_data = {
+ .parts = wzrhpg450h_partitions,
+ .nr_parts = ARRAY_SIZE(wzrhpg450h_partitions),
+};
+
+static struct gpio_led wzrhpg450h_leds_gpio[] __initdata = {
+ {
+ .name = "buffalo:red:diag",
+ .gpio = 14,
+ .active_low = 1,
+ },
+ {
+ .name = "buffalo:orange:security",
+ .gpio = 13,
+ .active_low = 1,
+ },
+};
+
+
+static struct gpio_led wzrhpg450h_wmac_leds_gpio[] = {
+ {
+ .name = "buffalo:blue:movie_engine",
+ .gpio = 13,
+ .active_low = 1,
+ },
+ {
+ .name = "buffalo:green:router",
+ .gpio = 14,
+ .active_low = 1,
+ },
+};
+
+static struct gpio_keys_button wzrhpg450h_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = WZRHPG450H_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = 6,
+ .active_low = 1,
+ }, {
+ .desc = "usb",
+ .type = EV_KEY,
+ .code = BTN_2,
+ .debounce_interval = WZRHPG450H_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = 1,
+ .active_low = 1,
+ }, {
+ .desc = "aoss",
+ .type = EV_KEY,
+ .code = KEY_WPS_BUTTON,
+ .debounce_interval = WZRHPG450H_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = 8,
+ .active_low = 1,
+ }, {
+ .desc = "movie_engine",
+ .type = EV_KEY,
+ .code = BTN_6,
+ .debounce_interval = WZRHPG450H_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = 7,
+ .active_low = 0,
+ }, {
+ .desc = "router_off",
+ .type = EV_KEY,
+ .code = BTN_5,
+ .debounce_interval = WZRHPG450H_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = 12,
+ .active_low = 0,
+ }
+};
+
+
+static void __init wzrhpg450h_init(void)
+{
+ u8 *ee = (u8 *) KSEG1ADDR(0x1f051000);
+ u8 *mac = (u8 *) ee + 2;
+
+ ath79_register_m25p80_multi(&wzrhpg450h_flash_data);
+
+ ath79_register_mdio(0, ~BIT(0));
+ ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+ ath79_eth0_data.speed = SPEED_1000;
+ ath79_eth0_data.duplex = DUPLEX_FULL;
+ ath79_eth0_data.phy_mask = BIT(0);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(wzrhpg450h_leds_gpio),
+ wzrhpg450h_leds_gpio);
+
+ ath79_register_gpio_keys_polled(-1, WZRHPG450H_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(wzrhpg450h_gpio_keys),
+ wzrhpg450h_gpio_keys);
+
+ ath79_register_eth(0);
+
+ ath79_register_usb();
+ gpio_request(16, "usb");
+ gpio_direction_output(16, 1);
+
+ ap91_pci_init(ee, NULL);
+ ap9x_pci_setup_wmac_led_pin(0, 15);
+ ap9x_pci_setup_wmac_leds(0, wzrhpg450h_wmac_leds_gpio,
+ ARRAY_SIZE(wzrhpg450h_wmac_leds_gpio));
+}
+
+MIPS_MACHINE(ATH79_MACH_WZR_HP_G450H, "WZR-HP-G450H", "Buffalo WZR-HP-G450H",
+ wzrhpg450h_init);
--- /dev/null
+/*
+ * Zcomax ZCN-1523H-2-8/5-16 board support
+ *
+ * Copyright (C) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/mach-ath79/ath79.h>
+#include <asm/mach-ath79/ar71xx_regs.h>
+
+#include "common.h"
+#include "dev-eth.h"
+#include "dev-m25p80.h"
+#include "dev-ap9x-pci.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "machtypes.h"
+
+#define ZCN_1523H_GPIO_BTN_RESET 0
+#define ZCN_1523H_GPIO_LED_INIT 11
+#define ZCN_1523H_GPIO_LED_LAN1 17
+
+#define ZCN_1523H_2_GPIO_LED_WEAK 13
+#define ZCN_1523H_2_GPIO_LED_MEDIUM 14
+#define ZCN_1523H_2_GPIO_LED_STRONG 15
+
+#define ZCN_1523H_5_GPIO_LED_UNKNOWN 1
+#define ZCN_1523H_5_GPIO_LED_LAN2 13
+#define ZCN_1523H_5_GPIO_LED_WEAK 14
+#define ZCN_1523H_5_GPIO_LED_MEDIUM 15
+#define ZCN_1523H_5_GPIO_LED_STRONG 16
+
+#define ZCN_1523H_KEYS_POLL_INTERVAL 20 /* msecs */
+#define ZCN_1523H_KEYS_DEBOUNCE_INTERVAL (3 * ZCN_1523H_KEYS_POLL_INTERVAL)
+
+static struct mtd_partition zcn_1523h_partitions[] = {
+ {
+ .name = "u-boot",
+ .offset = 0,
+ .size = 0x040000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "u-boot-env",
+ .offset = 0x040000,
+ .size = 0x010000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "rootfs",
+ .offset = 0x050000,
+ .size = 0x610000,
+ }, {
+ .name = "kernel",
+ .offset = 0x660000,
+ .size = 0x170000,
+ }, {
+ .name = "configure",
+ .offset = 0x7d0000,
+ .size = 0x010000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "mfg",
+ .offset = 0x7e0000,
+ .size = 0x010000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "eeprom",
+ .offset = 0x7f0000,
+ .size = 0x010000,
+ .mask_flags = MTD_WRITEABLE,
+ }, {
+ .name = "firmware",
+ .offset = 0x050000,
+ .size = 0x780000,
+ }
+};
+
+static struct flash_platform_data zcn_1523h_flash_data = {
+ .parts = zcn_1523h_partitions,
+ .nr_parts = ARRAY_SIZE(zcn_1523h_partitions),
+};
+
+static struct gpio_keys_button zcn_1523h_gpio_keys[] __initdata = {
+ {
+ .desc = "reset",
+ .type = EV_KEY,
+ .code = KEY_RESTART,
+ .debounce_interval = ZCN_1523H_KEYS_DEBOUNCE_INTERVAL,
+ .gpio = ZCN_1523H_GPIO_BTN_RESET,
+ .active_low = 1,
+ }
+};
+
+static struct gpio_led zcn_1523h_leds_gpio[] __initdata = {
+ {
+ .name = "zcn-1523h:amber:init",
+ .gpio = ZCN_1523H_GPIO_LED_INIT,
+ .active_low = 1,
+ }, {
+ .name = "zcn-1523h:green:lan1",
+ .gpio = ZCN_1523H_GPIO_LED_LAN1,
+ .active_low = 1,
+ }
+};
+
+static struct gpio_led zcn_1523h_2_leds_gpio[] __initdata = {
+ {
+ .name = "zcn-1523h:red:weak",
+ .gpio = ZCN_1523H_2_GPIO_LED_WEAK,
+ .active_low = 1,
+ }, {
+ .name = "zcn-1523h:amber:medium",
+ .gpio = ZCN_1523H_2_GPIO_LED_MEDIUM,
+ .active_low = 1,
+ }, {
+ .name = "zcn-1523h:green:strong",
+ .gpio = ZCN_1523H_2_GPIO_LED_STRONG,
+ .active_low = 1,
+ }
+};
+
+static struct gpio_led zcn_1523h_5_leds_gpio[] __initdata = {
+ {
+ .name = "zcn-1523h:red:weak",
+ .gpio = ZCN_1523H_5_GPIO_LED_WEAK,
+ .active_low = 1,
+ }, {
+ .name = "zcn-1523h:amber:medium",
+ .gpio = ZCN_1523H_5_GPIO_LED_MEDIUM,
+ .active_low = 1,
+ }, {
+ .name = "zcn-1523h:green:strong",
+ .gpio = ZCN_1523H_5_GPIO_LED_STRONG,
+ .active_low = 1,
+ }, {
+ .name = "zcn-1523h:green:lan2",
+ .gpio = ZCN_1523H_5_GPIO_LED_LAN2,
+ .active_low = 1,
+ }, {
+ .name = "zcn-1523h:amber:unknown",
+ .gpio = ZCN_1523H_5_GPIO_LED_UNKNOWN,
+ }
+};
+
+static void __init zcn_1523h_generic_setup(void)
+{
+ u8 *mac = (u8 *) KSEG1ADDR(0x1f7e0004);
+ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
+
+ ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
+ AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
+ AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
+ AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
+ AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
+
+ ath79_register_m25p80(&zcn_1523h_flash_data);
+
+ ath79_register_leds_gpio(0, ARRAY_SIZE(zcn_1523h_leds_gpio),
+ zcn_1523h_leds_gpio);
+
+ ath79_register_gpio_keys_polled(-1, ZCN_1523H_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(zcn_1523h_gpio_keys),
+ zcn_1523h_gpio_keys);
+
+ ap91_pci_init(ee, mac);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
+ ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
+
+ ath79_register_mdio(0, 0x0);
+
+ /* LAN1 port */
+ ath79_register_eth(0);
+}
+
+static void __init zcn_1523h_2_setup(void)
+{
+ zcn_1523h_generic_setup();
+ ap9x_pci_setup_wmac_gpio(0, BIT(9), 0);
+
+ ath79_register_leds_gpio(1, ARRAY_SIZE(zcn_1523h_2_leds_gpio),
+ zcn_1523h_2_leds_gpio);
+}
+
+MIPS_MACHINE(ATH79_MACH_ZCN_1523H_2, "ZCN-1523H-2", "Zcomax ZCN-1523H-2",
+ zcn_1523h_2_setup);
+
+static void __init zcn_1523h_5_setup(void)
+{
+ zcn_1523h_generic_setup();
+ ap9x_pci_setup_wmac_gpio(0, BIT(8), 0);
+
+ ath79_register_leds_gpio(1, ARRAY_SIZE(zcn_1523h_5_leds_gpio),
+ zcn_1523h_5_leds_gpio);
+
+ /* LAN2 port */
+ ath79_register_eth(1);
+}
+
+MIPS_MACHINE(ATH79_MACH_ZCN_1523H_5, "ZCN-1523H-5", "Zcomax ZCN-1523H-5",
+ zcn_1523h_5_setup);
--- /dev/null
+/*
+ * Atheros AR71xx minimal nvram support
+ *
+ * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/vmalloc.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/string.h>
+
+#include "nvram.h"
+
+char *ath79_nvram_find_var(const char *name, const char *buf, unsigned buf_len)
+{
+ unsigned len = strlen(name);
+ char *cur, *last;
+
+ if (buf_len == 0 || len == 0)
+ return NULL;
+
+ if (buf_len < len)
+ return NULL;
+
+ if (len == 1)
+ return memchr(buf, (int) *name, buf_len);
+
+ last = (char *) buf + buf_len - len;
+ for (cur = (char *) buf; cur <= last; cur++)
+ if (cur[0] == name[0] && memcmp(cur, name, len) == 0)
+ return cur + len;
+
+ return NULL;
+}
+
+int ath79_nvram_parse_mac_addr(const char *nvram, unsigned nvram_len,
+ const char *name, char *mac)
+{
+ char *buf;
+ char *mac_str;
+ int ret;
+ int t;
+
+ buf = vmalloc(nvram_len);
+ if (!buf)
+ return -ENOMEM;
+
+ memcpy(buf, nvram, nvram_len);
+ buf[nvram_len - 1] = '\0';
+
+ mac_str = ath79_nvram_find_var(name, buf, nvram_len);
+ if (!mac_str) {
+ ret = -EINVAL;
+ goto free;
+ }
+
+ t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
+ &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]);
+
+ if (t != 6) {
+ ret = -EINVAL;
+ goto free;
+ }
+
+ ret = 0;
+
+free:
+ vfree(buf);
+ return ret;
+}
--- /dev/null
+/*
+ * Atheros AR71xx minimal nvram support
+ *
+ * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef _ATH79_NVRAM_H
+#define _ATH79_NVRAM_H
+
+char *ath79_nvram_find_var(const char *name, const char *buf,
+ unsigned buf_len);
+int ath79_nvram_parse_mac_addr(const char *nvram, unsigned nvram_len,
+ const char *name, char *mac);
+
+#endif /* _ATH79_NVRAM_H */
--- /dev/null
+/*
+ * Atheros AP94 reference board PCI initialization
+ *
+ * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/pci.h>
+#include <linux/delay.h>
+
+#include <asm/mach-ath79/ar71xx_regs.h>
+#include <asm/mach-ath79/ath79.h>
+#include <asm/mach-ath79/pci.h>
+
+struct ath9k_fixup {
+ u16 *cal_data;
+ unsigned slot;
+};
+
+static int ath9k_num_fixups;
+static struct ath9k_fixup ath9k_fixups[2];
+
+static void ath9k_pci_fixup(struct pci_dev *dev)
+{
+ void __iomem *mem;
+ u16 *cal_data = NULL;
+ u16 cmd;
+ u32 bar0;
+ u32 val;
+ unsigned i;
+
+ for (i = 0; i < ath9k_num_fixups; i++) {
+ if (ath9k_fixups[i].cal_data == NULL)
+ continue;
+
+ if (ath9k_fixups[i].slot != PCI_SLOT(dev->devfn))
+ continue;
+
+ cal_data = ath9k_fixups[i].cal_data;
+ break;
+ }
+
+ if (cal_data == NULL)
+ return;
+
+ if (*cal_data != 0xa55a) {
+ pr_err("pci %s: invalid calibration data\n", pci_name(dev));
+ return;
+ }
+
+ pr_info("pci %s: fixup device configuration\n", pci_name(dev));
+
+ mem = ioremap(AR71XX_PCI_MEM_BASE, 0x10000);
+ if (!mem) {
+ pr_err("pci %s: ioremap error\n", pci_name(dev));
+ return;
+ }
+
+ pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0);
+
+ switch (ath79_soc) {
+ case ATH79_SOC_AR7161:
+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
+ AR71XX_PCI_MEM_BASE);
+ break;
+ case ATH79_SOC_AR7240:
+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0xffff);
+ break;
+
+ case ATH79_SOC_AR7241:
+ case ATH79_SOC_AR7242:
+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0x1000ffff);
+ break;
+
+ default:
+ BUG();
+ }
+
+ pci_read_config_word(dev, PCI_COMMAND, &cmd);
+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config_word(dev, PCI_COMMAND, cmd);
+
+ /* set pointer to first reg address */
+ cal_data += 3;
+ while (*cal_data != 0xffff) {
+ u32 reg;
+ reg = *cal_data++;
+ val = *cal_data++;
+ val |= (*cal_data++) << 16;
+
+ __raw_writel(val, mem + reg);
+ udelay(100);
+ }
+
+ pci_read_config_dword(dev, PCI_VENDOR_ID, &val);
+ dev->vendor = val & 0xffff;
+ dev->device = (val >> 16) & 0xffff;
+
+ pci_read_config_dword(dev, PCI_CLASS_REVISION, &val);
+ dev->revision = val & 0xff;
+ dev->class = val >> 8; /* upper 3 bytes */
+
+ pci_read_config_word(dev, PCI_COMMAND, &cmd);
+ cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+ pci_write_config_word(dev, PCI_COMMAND, cmd);
+
+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0);
+
+ iounmap(mem);
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath9k_pci_fixup);
+
+void __init pci_enable_ath9k_fixup(unsigned slot, u16 *cal_data)
+{
+ if (ath9k_num_fixups >= ARRAY_SIZE(ath9k_fixups))
+ return;
+
+ ath9k_fixups[ath9k_num_fixups].slot = slot;
+ ath9k_fixups[ath9k_num_fixups].cal_data = cal_data;
+ ath9k_num_fixups++;
+}
--- /dev/null
+#ifndef _PCI_ATH9K_FIXUP
+#define _PCI_ATH9K_FIXUP
+
+void pci_enable_ath9k_fixup(unsigned slot, u16 *cal_data) __init;
+
+#endif /* _PCI_ATH9K_FIXUP */
--- /dev/null
+/*
+ * Atheros AR71xx SoC specific platform data definitions
+ *
+ * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_ATH79_PLATFORM_H
+#define __ASM_MACH_ATH79_PLATFORM_H
+
+#include <linux/if_ether.h>
+#include <linux/skbuff.h>
+#include <linux/phy.h>
+#include <linux/spi/spi.h>
+
+struct ag71xx_switch_platform_data {
+ u8 phy4_mii_en:1;
+};
+
+struct ag71xx_platform_data {
+ phy_interface_t phy_if_mode;
+ u32 phy_mask;
+ int speed;
+ int duplex;
+ u32 reset_bit;
+ u8 mac_addr[ETH_ALEN];
+ struct device *mii_bus_dev;
+
+ u8 has_gbit:1;
+ u8 is_ar91xx:1;
+ u8 is_ar7240:1;
+ u8 is_ar724x:1;
+ u8 has_ar8216:1;
+
+ struct ag71xx_switch_platform_data *switch_data;
+
+ void (*ddr_flush)(void);
+ void (*set_speed)(int speed);
+
+ u32 fifo_cfg1;
+ u32 fifo_cfg2;
+ u32 fifo_cfg3;
+};
+
+struct ag71xx_mdio_platform_data {
+ u32 phy_mask;
+ int is_ar7240;
+};
+
+#endif /* __ASM_MACH_ATH79_PLATFORM_H */
--- /dev/null
+/*
+ * AR913x parallel flash driver platform data definitions
+ *
+ * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef __AR913X_FLASH_H
+#define __AR913X_FLASH_H
+
+struct mtd_partition;
+
+struct ar913x_flash_platform_data {
+ unsigned int width;
+ u8 is_shared:1;
+ unsigned int nr_parts;
+ struct mtd_partition *parts;
+};
+
+#endif /* __AR913X_FLASH_H */
--- /dev/null
+/*
+ * MikroTik RouterBOARD 750 definitions
+ *
+ * Copyright (C) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+#ifndef _MACH_RB750_H
+#define _MACH_RB750_H
+
+#include <linux/bitops.h>
+
+#define RB750_GPIO_LVC573_LE 0 /* Latch enable on LVC573 */
+#define RB750_GPIO_NAND_IO0 1 /* NAND I/O 0 */
+#define RB750_GPIO_NAND_IO1 2 /* NAND I/O 1 */
+#define RB750_GPIO_NAND_IO2 3 /* NAND I/O 2 */
+#define RB750_GPIO_NAND_IO3 4 /* NAND I/O 3 */
+#define RB750_GPIO_NAND_IO4 5 /* NAND I/O 4 */
+#define RB750_GPIO_NAND_IO5 6 /* NAND I/O 5 */
+#define RB750_GPIO_NAND_IO6 7 /* NAND I/O 6 */
+#define RB750_GPIO_NAND_IO7 8 /* NAND I/O 7 */
+#define RB750_GPIO_NAND_NCE 11 /* NAND Chip Enable (active low) */
+#define RB750_GPIO_NAND_RDY 12 /* NAND Ready */
+#define RB750_GPIO_NAND_CLE 14 /* NAND Command Latch Enable */
+#define RB750_GPIO_NAND_ALE 15 /* NAND Address Latch Enable */
+#define RB750_GPIO_NAND_NRE 16 /* NAND Read Enable (active low) */
+#define RB750_GPIO_NAND_NWE 17 /* NAND Write Enable (active low) */
+
+#define RB750_GPIO_BTN_RESET 1
+#define RB750_GPIO_SPI_CS0 2
+#define RB750_GPIO_LED_ACT 12
+#define RB750_GPIO_LED_PORT1 13
+#define RB750_GPIO_LED_PORT2 14
+#define RB750_GPIO_LED_PORT3 15
+#define RB750_GPIO_LED_PORT4 16
+#define RB750_GPIO_LED_PORT5 17
+
+#define RB750_LED_ACT BIT(RB750_GPIO_LED_ACT)
+#define RB750_LED_PORT1 BIT(RB750_GPIO_LED_PORT1)
+#define RB750_LED_PORT2 BIT(RB750_GPIO_LED_PORT2)
+#define RB750_LED_PORT3 BIT(RB750_GPIO_LED_PORT3)
+#define RB750_LED_PORT4 BIT(RB750_GPIO_LED_PORT4)
+#define RB750_LED_PORT5 BIT(RB750_GPIO_LED_PORT5)
+
+#define RB750_LVC573_LE BIT(RB750_GPIO_LVC573_LE)
+
+#define RB750_LED_BITS (RB750_LED_PORT1 | RB750_LED_PORT2 | RB750_LED_PORT3 | \
+ RB750_LED_PORT4 | RB750_LED_PORT5 | RB750_LED_ACT)
+
+struct rb750_led_data {
+ char *name;
+ char *default_trigger;
+ u32 mask;
+ int active_low;
+};
+
+struct rb750_led_platform_data {
+ int num_leds;
+ struct rb750_led_data *leds;
+};
+
+int rb750_latch_change(u32 mask_clr, u32 mask_set);
+void rb750_nand_pins_enable(void);
+void rb750_nand_pins_disable(void);
+
+#endif /* _MACH_RB750_H */
\ No newline at end of file
--- /dev/null
+/*
+ * SPI driver definitions for the CPLD chip on the Mikrotik RB4xx boards
+ *
+ * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This file was based on the patches for Linux 2.6.27.39 published by
+ * MikroTik for their RouterBoard 4xx series devices.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#define CPLD_GPIO_nLED1 0
+#define CPLD_GPIO_nLED2 1
+#define CPLD_GPIO_nLED3 2
+#define CPLD_GPIO_nLED4 3
+#define CPLD_GPIO_FAN 4
+#define CPLD_GPIO_ALE 5
+#define CPLD_GPIO_CLE 6
+#define CPLD_GPIO_nCE 7
+#define CPLD_GPIO_nLED5 8
+
+#define CPLD_NUM_GPIOS 9
+
+#define CPLD_CFG_nLED1 BIT(CPLD_GPIO_nLED1)
+#define CPLD_CFG_nLED2 BIT(CPLD_GPIO_nLED2)
+#define CPLD_CFG_nLED3 BIT(CPLD_GPIO_nLED3)
+#define CPLD_CFG_nLED4 BIT(CPLD_GPIO_nLED4)
+#define CPLD_CFG_FAN BIT(CPLD_GPIO_FAN)
+#define CPLD_CFG_ALE BIT(CPLD_GPIO_ALE)
+#define CPLD_CFG_CLE BIT(CPLD_GPIO_CLE)
+#define CPLD_CFG_nCE BIT(CPLD_GPIO_nCE)
+#define CPLD_CFG_nLED5 BIT(CPLD_GPIO_nLED5)
+
+struct rb4xx_cpld_platform_data {
+ unsigned gpio_base;
+};
+
+extern int rb4xx_cpld_change_cfg(unsigned mask, unsigned value);
+extern int rb4xx_cpld_read(unsigned char *rx_buf,
+ const unsigned char *verify_buf,
+ unsigned cnt);
+extern int rb4xx_cpld_read_from(unsigned addr,
+ unsigned char *rx_buf,
+ const unsigned char *verify_buf,
+ unsigned cnt);
+extern int rb4xx_cpld_write(const unsigned char *buf, unsigned count);
--- /dev/null
+config AG71XX
+ tristate "Atheros AR7XXX/AR9XXX built-in ethernet mac support"
+ depends on ATH79
+ select PHYLIB
+ help
+ If you wish to compile a kernel for AR7XXX/91XXX and enable
+ ethernet support, then you should always answer Y to this.
+
+if AG71XX
+
+config AG71XX_DEBUG
+ bool "Atheros AR71xx built-in ethernet driver debugging"
+ default n
+ help
+ Atheros AR71xx built-in ethernet driver debugging messages.
+
+config AG71XX_DEBUG_FS
+ bool "Atheros AR71xx built-in ethernet driver debugfs support"
+ depends on DEBUG_FS
+ default n
+ help
+ Say Y, if you need access to various statistics provided by
+ the ag71xx driver.
+
+config AG71XX_AR8216_SUPPORT
+ bool "special support for the Atheros AR8216 switch"
+ default n
+ default y if ATH79_MACH_WNR2000 || ATH79_MACH_MZK_W04NU
+ help
+ Say 'y' here if you want to enable special support for the
+ Atheros AR8216 switch found on some boards.
+
+endif
--- /dev/null
+#
+# Makefile for the Atheros AR71xx built-in ethernet macs
+#
+
+ag71xx-y += ag71xx_main.o
+ag71xx-y += ag71xx_ethtool.o
+ag71xx-y += ag71xx_phy.o
+ag71xx-y += ag71xx_mdio.o
+ag71xx-y += ag71xx_ar7240.o
+
+ag71xx-$(CONFIG_AG71XX_DEBUG_FS) += ag71xx_debugfs.o
+ag71xx-$(CONFIG_AG71XX_AR8216_SUPPORT) += ag71xx_ar8216.o
+
+obj-$(CONFIG_AG71XX) += ag71xx.o
+
--- /dev/null
+/*
+ * Atheros AR71xx built-in ethernet mac driver
+ *
+ * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * Based on Atheros' AG7100 driver
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef __AG71XX_H
+#define __AG71XX_H
+
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/random.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/ethtool.h>
+#include <linux/etherdevice.h>
+#include <linux/if_vlan.h>
+#include <linux/phy.h>
+#include <linux/skbuff.h>
+#include <linux/dma-mapping.h>
+#include <linux/workqueue.h>
+
+#include <linux/bitops.h>
+
+#include <asm/mach-ath79/ar71xx_regs.h>
+#include <asm/mach-ath79/ath79.h>
+#include <asm/mach-ath79/ag71xx_platform.h>
+
+#define AG71XX_DRV_NAME "ag71xx"
+#define AG71XX_DRV_VERSION "0.5.35"
+
+#define AG71XX_NAPI_WEIGHT 64
+#define AG71XX_OOM_REFILL (1 + HZ/10)
+
+#define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
+#define AG71XX_INT_TX (AG71XX_INT_TX_PS)
+#define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
+
+#define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
+#define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
+
+#define AG71XX_TX_MTU_LEN 1540
+#define AG71XX_RX_PKT_RESERVE 64
+#define AG71XX_RX_PKT_SIZE \
+ (AG71XX_RX_PKT_RESERVE + ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
+
+#define AG71XX_TX_RING_SIZE_DEFAULT 64
+#define AG71XX_RX_RING_SIZE_DEFAULT 128
+
+#define AG71XX_TX_RING_SIZE_MAX 256
+#define AG71XX_RX_RING_SIZE_MAX 256
+
+#ifdef CONFIG_AG71XX_DEBUG
+#define DBG(fmt, args...) pr_debug(fmt, ## args)
+#else
+#define DBG(fmt, args...) do {} while (0)
+#endif
+
+#define ag71xx_assert(_cond) \
+do { \
+ if (_cond) \
+ break; \
+ printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \
+ BUG(); \
+} while (0)
+
+struct ag71xx_desc {
+ u32 data;
+ u32 ctrl;
+#define DESC_EMPTY BIT(31)
+#define DESC_MORE BIT(24)
+#define DESC_PKTLEN_M 0xfff
+ u32 next;
+ u32 pad;
+} __attribute__((aligned(4)));
+
+struct ag71xx_buf {
+ struct sk_buff *skb;
+ struct ag71xx_desc *desc;
+ dma_addr_t dma_addr;
+ unsigned long timestamp;
+};
+
+struct ag71xx_ring {
+ struct ag71xx_buf *buf;
+ u8 *descs_cpu;
+ dma_addr_t descs_dma;
+ unsigned int desc_size;
+ unsigned int curr;
+ unsigned int dirty;
+ unsigned int size;
+};
+
+struct ag71xx_mdio {
+ struct mii_bus *mii_bus;
+ int mii_irq[PHY_MAX_ADDR];
+ void __iomem *mdio_base;
+ struct ag71xx_mdio_platform_data *pdata;
+};
+
+struct ag71xx_int_stats {
+ unsigned long rx_pr;
+ unsigned long rx_be;
+ unsigned long rx_of;
+ unsigned long tx_ps;
+ unsigned long tx_be;
+ unsigned long tx_ur;
+ unsigned long total;
+};
+
+struct ag71xx_napi_stats {
+ unsigned long napi_calls;
+ unsigned long rx_count;
+ unsigned long rx_packets;
+ unsigned long rx_packets_max;
+ unsigned long tx_count;
+ unsigned long tx_packets;
+ unsigned long tx_packets_max;
+
+ unsigned long rx[AG71XX_NAPI_WEIGHT + 1];
+ unsigned long tx[AG71XX_NAPI_WEIGHT + 1];
+};
+
+struct ag71xx_debug {
+ struct dentry *debugfs_dir;
+
+ struct ag71xx_int_stats int_stats;
+ struct ag71xx_napi_stats napi_stats;
+};
+
+struct ag71xx {
+ void __iomem *mac_base;
+
+ spinlock_t lock;
+ struct platform_device *pdev;
+ struct net_device *dev;
+ struct napi_struct napi;
+ u32 msg_enable;
+
+ struct ag71xx_desc *stop_desc;
+ dma_addr_t stop_desc_dma;
+
+ struct ag71xx_ring rx_ring;
+ struct ag71xx_ring tx_ring;
+
+ struct mii_bus *mii_bus;
+ struct phy_device *phy_dev;
+ void *phy_priv;
+
+ unsigned int link;
+ unsigned int speed;
+ int duplex;
+
+ struct work_struct restart_work;
+ struct delayed_work link_work;
+ struct timer_list oom_timer;
+
+#ifdef CONFIG_AG71XX_DEBUG_FS
+ struct ag71xx_debug debug;
+#endif
+};
+
+extern struct ethtool_ops ag71xx_ethtool_ops;
+void ag71xx_link_adjust(struct ag71xx *ag);
+
+int ag71xx_mdio_driver_init(void) __init;
+void ag71xx_mdio_driver_exit(void);
+
+int ag71xx_phy_connect(struct ag71xx *ag);
+void ag71xx_phy_disconnect(struct ag71xx *ag);
+void ag71xx_phy_start(struct ag71xx *ag);
+void ag71xx_phy_stop(struct ag71xx *ag);
+
+static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag)
+{
+ return ag->pdev->dev.platform_data;
+}
+
+static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
+{
+ return (desc->ctrl & DESC_EMPTY) != 0;
+}
+
+static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
+{
+ return desc->ctrl & DESC_PKTLEN_M;
+}
+
+/* Register offsets */
+#define AG71XX_REG_MAC_CFG1 0x0000
+#define AG71XX_REG_MAC_CFG2 0x0004
+#define AG71XX_REG_MAC_IPG 0x0008
+#define AG71XX_REG_MAC_HDX 0x000c
+#define AG71XX_REG_MAC_MFL 0x0010
+#define AG71XX_REG_MII_CFG 0x0020
+#define AG71XX_REG_MII_CMD 0x0024
+#define AG71XX_REG_MII_ADDR 0x0028
+#define AG71XX_REG_MII_CTRL 0x002c
+#define AG71XX_REG_MII_STATUS 0x0030
+#define AG71XX_REG_MII_IND 0x0034
+#define AG71XX_REG_MAC_IFCTL 0x0038
+#define AG71XX_REG_MAC_ADDR1 0x0040
+#define AG71XX_REG_MAC_ADDR2 0x0044
+#define AG71XX_REG_FIFO_CFG0 0x0048
+#define AG71XX_REG_FIFO_CFG1 0x004c
+#define AG71XX_REG_FIFO_CFG2 0x0050
+#define AG71XX_REG_FIFO_CFG3 0x0054
+#define AG71XX_REG_FIFO_CFG4 0x0058
+#define AG71XX_REG_FIFO_CFG5 0x005c
+#define AG71XX_REG_FIFO_RAM0 0x0060
+#define AG71XX_REG_FIFO_RAM1 0x0064
+#define AG71XX_REG_FIFO_RAM2 0x0068
+#define AG71XX_REG_FIFO_RAM3 0x006c
+#define AG71XX_REG_FIFO_RAM4 0x0070
+#define AG71XX_REG_FIFO_RAM5 0x0074
+#define AG71XX_REG_FIFO_RAM6 0x0078
+#define AG71XX_REG_FIFO_RAM7 0x007c
+
+#define AG71XX_REG_TX_CTRL 0x0180
+#define AG71XX_REG_TX_DESC 0x0184
+#define AG71XX_REG_TX_STATUS 0x0188
+#define AG71XX_REG_RX_CTRL 0x018c
+#define AG71XX_REG_RX_DESC 0x0190
+#define AG71XX_REG_RX_STATUS 0x0194
+#define AG71XX_REG_INT_ENABLE 0x0198
+#define AG71XX_REG_INT_STATUS 0x019c
+
+#define AG71XX_REG_FIFO_DEPTH 0x01a8
+#define AG71XX_REG_RX_SM 0x01b0
+#define AG71XX_REG_TX_SM 0x01b4
+
+#define MAC_CFG1_TXE BIT(0) /* Tx Enable */
+#define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
+#define MAC_CFG1_RXE BIT(2) /* Rx Enable */
+#define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */
+#define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */
+#define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */
+#define MAC_CFG1_LB BIT(8) /* Loopback mode */
+#define MAC_CFG1_SR BIT(31) /* Soft Reset */
+
+#define MAC_CFG2_FDX BIT(0)
+#define MAC_CFG2_CRC_EN BIT(1)
+#define MAC_CFG2_PAD_CRC_EN BIT(2)
+#define MAC_CFG2_LEN_CHECK BIT(4)
+#define MAC_CFG2_HUGE_FRAME_EN BIT(5)
+#define MAC_CFG2_IF_1000 BIT(9)
+#define MAC_CFG2_IF_10_100 BIT(8)
+
+#define FIFO_CFG0_WTM BIT(0) /* Watermark Module */
+#define FIFO_CFG0_RXS BIT(1) /* Rx System Module */
+#define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */
+#define FIFO_CFG0_TXS BIT(3) /* Tx System Module */
+#define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */
+#define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
+ | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
+
+#define FIFO_CFG0_ENABLE_SHIFT 8
+
+#define FIFO_CFG4_DE BIT(0) /* Drop Event */
+#define FIFO_CFG4_DV BIT(1) /* RX_DV Event */
+#define FIFO_CFG4_FC BIT(2) /* False Carrier */
+#define FIFO_CFG4_CE BIT(3) /* Code Error */
+#define FIFO_CFG4_CR BIT(4) /* CRC error */
+#define FIFO_CFG4_LM BIT(5) /* Length Mismatch */
+#define FIFO_CFG4_LO BIT(6) /* Length out of range */
+#define FIFO_CFG4_OK BIT(7) /* Packet is OK */
+#define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
+#define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
+#define FIFO_CFG4_DR BIT(10) /* Dribble */
+#define FIFO_CFG4_LE BIT(11) /* Long Event */
+#define FIFO_CFG4_CF BIT(12) /* Control Frame */
+#define FIFO_CFG4_PF BIT(13) /* Pause Frame */
+#define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
+#define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
+#define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
+#define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
+
+#define FIFO_CFG5_DE BIT(0) /* Drop Event */
+#define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
+#define FIFO_CFG5_FC BIT(2) /* False Carrier */
+#define FIFO_CFG5_CE BIT(3) /* Code Error */
+#define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
+#define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
+#define FIFO_CFG5_OK BIT(6) /* Packet is OK */
+#define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
+#define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
+#define FIFO_CFG5_DR BIT(9) /* Dribble */
+#define FIFO_CFG5_CF BIT(10) /* Control Frame */
+#define FIFO_CFG5_PF BIT(11) /* Pause Frame */
+#define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
+#define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
+#define FIFO_CFG5_LE BIT(14) /* Long Event */
+#define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
+#define FIFO_CFG5_16 BIT(16) /* unknown */
+#define FIFO_CFG5_17 BIT(17) /* unknown */
+#define FIFO_CFG5_SF BIT(18) /* Short Frame */
+#define FIFO_CFG5_BM BIT(19) /* Byte Mode */
+
+#define AG71XX_INT_TX_PS BIT(0)
+#define AG71XX_INT_TX_UR BIT(1)
+#define AG71XX_INT_TX_BE BIT(3)
+#define AG71XX_INT_RX_PR BIT(4)
+#define AG71XX_INT_RX_OF BIT(6)
+#define AG71XX_INT_RX_BE BIT(7)
+
+#define MAC_IFCTL_SPEED BIT(16)
+
+#define MII_CFG_CLK_DIV_4 0
+#define MII_CFG_CLK_DIV_6 2
+#define MII_CFG_CLK_DIV_8 3
+#define MII_CFG_CLK_DIV_10 4
+#define MII_CFG_CLK_DIV_14 5
+#define MII_CFG_CLK_DIV_20 6
+#define MII_CFG_CLK_DIV_28 7
+#define MII_CFG_RESET BIT(31)
+
+#define MII_CMD_WRITE 0x0
+#define MII_CMD_READ 0x1
+#define MII_ADDR_SHIFT 8
+#define MII_IND_BUSY BIT(0)
+#define MII_IND_INVALID BIT(2)
+
+#define TX_CTRL_TXE BIT(0) /* Tx Enable */
+
+#define TX_STATUS_PS BIT(0) /* Packet Sent */
+#define TX_STATUS_UR BIT(1) /* Tx Underrun */
+#define TX_STATUS_BE BIT(3) /* Bus Error */
+
+#define RX_CTRL_RXE BIT(0) /* Rx Enable */
+
+#define RX_STATUS_PR BIT(0) /* Packet Received */
+#define RX_STATUS_OF BIT(2) /* Rx Overflow */
+#define RX_STATUS_BE BIT(3) /* Bus Error */
+
+static inline void ag71xx_check_reg_offset(struct ag71xx *ag, unsigned reg)
+{
+ switch (reg) {
+ case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
+ case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_TX_SM:
+ case AG71XX_REG_MII_CFG:
+ break;
+
+ default:
+ BUG();
+ }
+}
+
+static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
+{
+ ag71xx_check_reg_offset(ag, reg);
+
+ __raw_writel(value, ag->mac_base + reg);
+ /* flush write */
+ (void) __raw_readl(ag->mac_base + reg);
+}
+
+static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
+{
+ ag71xx_check_reg_offset(ag, reg);
+
+ return __raw_readl(ag->mac_base + reg);
+}
+
+static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
+{
+ void __iomem *r;
+
+ ag71xx_check_reg_offset(ag, reg);
+
+ r = ag->mac_base + reg;
+ __raw_writel(__raw_readl(r) | mask, r);
+ /* flush write */
+ (void)__raw_readl(r);
+}
+
+static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
+{
+ void __iomem *r;
+
+ ag71xx_check_reg_offset(ag, reg);
+
+ r = ag->mac_base + reg;
+ __raw_writel(__raw_readl(r) & ~mask, r);
+ /* flush write */
+ (void) __raw_readl(r);
+}
+
+static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
+{
+ ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
+}
+
+static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
+{
+ ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
+}
+
+#ifdef CONFIG_AG71XX_AR8216_SUPPORT
+void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb);
+int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb,
+ int pktlen);
+static inline int ag71xx_has_ar8216(struct ag71xx *ag)
+{
+ return ag71xx_get_pdata(ag)->has_ar8216;
+}
+#else
+static inline void ag71xx_add_ar8216_header(struct ag71xx *ag,
+ struct sk_buff *skb)
+{
+}
+
+static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag,
+ struct sk_buff *skb,
+ int pktlen)
+{
+ return 0;
+}
+static inline int ag71xx_has_ar8216(struct ag71xx *ag)
+{
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_AG71XX_DEBUG_FS
+int ag71xx_debugfs_root_init(void);
+void ag71xx_debugfs_root_exit(void);
+int ag71xx_debugfs_init(struct ag71xx *ag);
+void ag71xx_debugfs_exit(struct ag71xx *ag);
+void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status);
+void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx);
+#else
+static inline int ag71xx_debugfs_root_init(void) { return 0; }
+static inline void ag71xx_debugfs_root_exit(void) {}
+static inline int ag71xx_debugfs_init(struct ag71xx *ag) { return 0; }
+static inline void ag71xx_debugfs_exit(struct ag71xx *ag) {}
+static inline void ag71xx_debugfs_update_int_stats(struct ag71xx *ag,
+ u32 status) {}
+static inline void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag,
+ int rx, int tx) {}
+#endif /* CONFIG_AG71XX_DEBUG_FS */
+
+void ag71xx_ar7240_start(struct ag71xx *ag);
+void ag71xx_ar7240_stop(struct ag71xx *ag);
+int ag71xx_ar7240_init(struct ag71xx *ag);
+void ag71xx_ar7240_cleanup(struct ag71xx *ag);
+
+int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg);
+void ag71xx_mdio_mii_write(struct ag71xx_mdio *am, int addr, int reg, u16 val);
+
+u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
+ unsigned reg_addr);
+int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
+ unsigned reg_addr, u16 reg_val);
+
+#endif /* _AG71XX_H */
--- /dev/null
+/*
+ * Driver for the built-in ethernet switch of the Atheros AR7240 SoC
+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (c) 2010 Felix Fietkau <nbd@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ */
+
+#include <linux/etherdevice.h>
+#include <linux/list.h>
+#include <linux/netdevice.h>
+#include <linux/phy.h>
+#include <linux/mii.h>
+#include <linux/bitops.h>
+#include <linux/switch.h>
+#include "ag71xx.h"
+
+#define BITM(_count) (BIT(_count) - 1)
+#define BITS(_shift, _count) (BITM(_count) << _shift)
+
+#define AR7240_REG_MASK_CTRL 0x00
+#define AR7240_MASK_CTRL_REVISION_M BITM(8)
+#define AR7240_MASK_CTRL_VERSION_M BITM(8)
+#define AR7240_MASK_CTRL_VERSION_S 8
+#define AR7240_MASK_CTRL_VERSION_AR7240 0x01
+#define AR7240_MASK_CTRL_VERSION_AR934X 0x02
+#define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
+
+#define AR7240_REG_MAC_ADDR0 0x20
+#define AR7240_REG_MAC_ADDR1 0x24
+
+#define AR7240_REG_FLOOD_MASK 0x2c
+#define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26)
+
+#define AR7240_REG_GLOBAL_CTRL 0x30
+#define AR7240_GLOBAL_CTRL_MTU_M BITM(12)
+
+#define AR7240_REG_VTU 0x0040
+#define AR7240_VTU_OP BITM(3)
+#define AR7240_VTU_OP_NOOP 0x0
+#define AR7240_VTU_OP_FLUSH 0x1
+#define AR7240_VTU_OP_LOAD 0x2
+#define AR7240_VTU_OP_PURGE 0x3
+#define AR7240_VTU_OP_REMOVE_PORT 0x4
+#define AR7240_VTU_ACTIVE BIT(3)
+#define AR7240_VTU_FULL BIT(4)
+#define AR7240_VTU_PORT BITS(8, 4)
+#define AR7240_VTU_PORT_S 8
+#define AR7240_VTU_VID BITS(16, 12)
+#define AR7240_VTU_VID_S 16
+#define AR7240_VTU_PRIO BITS(28, 3)
+#define AR7240_VTU_PRIO_S 28
+#define AR7240_VTU_PRIO_EN BIT(31)
+
+#define AR7240_REG_VTU_DATA 0x0044
+#define AR7240_VTUDATA_MEMBER BITS(0, 10)
+#define AR7240_VTUDATA_VALID BIT(11)
+
+#define AR7240_REG_ATU 0x50
+#define AR7240_ATU_FLUSH_ALL 0x1
+
+#define AR7240_REG_AT_CTRL 0x5c
+#define AR7240_AT_CTRL_AGE_TIME BITS(0, 15)
+#define AR7240_AT_CTRL_AGE_EN BIT(17)
+#define AR7240_AT_CTRL_LEARN_CHANGE BIT(18)
+#define AR7240_AT_CTRL_RESERVED BIT(19)
+#define AR7240_AT_CTRL_ARP_EN BIT(20)
+
+#define AR7240_REG_TAG_PRIORITY 0x70
+
+#define AR7240_REG_SERVICE_TAG 0x74
+#define AR7240_SERVICE_TAG_M BITM(16)
+
+#define AR7240_REG_CPU_PORT 0x78
+#define AR7240_MIRROR_PORT_S 4
+#define AR7240_CPU_PORT_EN BIT(8)
+
+#define AR7240_REG_MIB_FUNCTION0 0x80
+#define AR7240_MIB_TIMER_M BITM(16)
+#define AR7240_MIB_AT_HALF_EN BIT(16)
+#define AR7240_MIB_BUSY BIT(17)
+#define AR7240_MIB_FUNC_S 24
+#define AR7240_MIB_FUNC_NO_OP 0x0
+#define AR7240_MIB_FUNC_FLUSH 0x1
+#define AR7240_MIB_FUNC_CAPTURE 0x3
+
+#define AR7240_REG_MDIO_CTRL 0x98
+#define AR7240_MDIO_CTRL_DATA_M BITM(16)
+#define AR7240_MDIO_CTRL_REG_ADDR_S 16
+#define AR7240_MDIO_CTRL_PHY_ADDR_S 21
+#define AR7240_MDIO_CTRL_CMD_WRITE 0
+#define AR7240_MDIO_CTRL_CMD_READ BIT(27)
+#define AR7240_MDIO_CTRL_MASTER_EN BIT(30)
+#define AR7240_MDIO_CTRL_BUSY BIT(31)
+
+#define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
+
+#define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
+#define AR7240_PORT_STATUS_SPEED_S 0
+#define AR7240_PORT_STATUS_SPEED_M BITM(2)
+#define AR7240_PORT_STATUS_SPEED_10 0
+#define AR7240_PORT_STATUS_SPEED_100 1
+#define AR7240_PORT_STATUS_SPEED_1000 2
+#define AR7240_PORT_STATUS_TXMAC BIT(2)
+#define AR7240_PORT_STATUS_RXMAC BIT(3)
+#define AR7240_PORT_STATUS_TXFLOW BIT(4)
+#define AR7240_PORT_STATUS_RXFLOW BIT(5)
+#define AR7240_PORT_STATUS_DUPLEX BIT(6)
+#define AR7240_PORT_STATUS_LINK_UP BIT(8)
+#define AR7240_PORT_STATUS_LINK_AUTO BIT(9)
+#define AR7240_PORT_STATUS_LINK_PAUSE BIT(10)
+
+#define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04)
+#define AR7240_PORT_CTRL_STATE_M BITM(3)
+#define AR7240_PORT_CTRL_STATE_DISABLED 0
+#define AR7240_PORT_CTRL_STATE_BLOCK 1
+#define AR7240_PORT_CTRL_STATE_LISTEN 2
+#define AR7240_PORT_CTRL_STATE_LEARN 3
+#define AR7240_PORT_CTRL_STATE_FORWARD 4
+#define AR7240_PORT_CTRL_LEARN_LOCK BIT(7)
+#define AR7240_PORT_CTRL_VLAN_MODE_S 8
+#define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
+#define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
+#define AR7240_PORT_CTRL_VLAN_MODE_ADD 2
+#define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
+#define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10)
+#define AR7240_PORT_CTRL_HEADER BIT(11)
+#define AR7240_PORT_CTRL_MAC_LOOP BIT(12)
+#define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13)
+#define AR7240_PORT_CTRL_LEARN BIT(14)
+#define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15)
+#define AR7240_PORT_CTRL_MIRROR_TX BIT(16)
+#define AR7240_PORT_CTRL_MIRROR_RX BIT(17)
+
+#define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08)
+
+#define AR7240_PORT_VLAN_DEFAULT_ID_S 0
+#define AR7240_PORT_VLAN_DEST_PORTS_S 16
+#define AR7240_PORT_VLAN_MODE_S 30
+#define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
+#define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1
+#define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
+#define AR7240_PORT_VLAN_MODE_SECURE 3
+
+
+#define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100)
+
+#define AR7240_STATS_RXBROAD 0x00
+#define AR7240_STATS_RXPAUSE 0x04
+#define AR7240_STATS_RXMULTI 0x08
+#define AR7240_STATS_RXFCSERR 0x0c
+#define AR7240_STATS_RXALIGNERR 0x10
+#define AR7240_STATS_RXRUNT 0x14
+#define AR7240_STATS_RXFRAGMENT 0x18
+#define AR7240_STATS_RX64BYTE 0x1c
+#define AR7240_STATS_RX128BYTE 0x20
+#define AR7240_STATS_RX256BYTE 0x24
+#define AR7240_STATS_RX512BYTE 0x28
+#define AR7240_STATS_RX1024BYTE 0x2c
+#define AR7240_STATS_RX1518BYTE 0x30
+#define AR7240_STATS_RXMAXBYTE 0x34
+#define AR7240_STATS_RXTOOLONG 0x38
+#define AR7240_STATS_RXGOODBYTE 0x3c
+#define AR7240_STATS_RXBADBYTE 0x44
+#define AR7240_STATS_RXOVERFLOW 0x4c
+#define AR7240_STATS_FILTERED 0x50
+#define AR7240_STATS_TXBROAD 0x54
+#define AR7240_STATS_TXPAUSE 0x58
+#define AR7240_STATS_TXMULTI 0x5c
+#define AR7240_STATS_TXUNDERRUN 0x60
+#define AR7240_STATS_TX64BYTE 0x64
+#define AR7240_STATS_TX128BYTE 0x68
+#define AR7240_STATS_TX256BYTE 0x6c
+#define AR7240_STATS_TX512BYTE 0x70
+#define AR7240_STATS_TX1024BYTE 0x74
+#define AR7240_STATS_TX1518BYTE 0x78
+#define AR7240_STATS_TXMAXBYTE 0x7c
+#define AR7240_STATS_TXOVERSIZE 0x80
+#define AR7240_STATS_TXBYTE 0x84
+#define AR7240_STATS_TXCOLLISION 0x8c
+#define AR7240_STATS_TXABORTCOL 0x90
+#define AR7240_STATS_TXMULTICOL 0x94
+#define AR7240_STATS_TXSINGLECOL 0x98
+#define AR7240_STATS_TXEXCDEFER 0x9c
+#define AR7240_STATS_TXDEFER 0xa0
+#define AR7240_STATS_TXLATECOL 0xa4
+
+#define AR7240_PORT_CPU 0
+#define AR7240_NUM_PORTS 6
+#define AR7240_NUM_PHYS 5
+
+#define AR7240_PHY_ID1 0x004d
+#define AR7240_PHY_ID2 0xd041
+
+#define AR934X_PHY_ID1 0x004d
+#define AR934X_PHY_ID2 0xd042
+
+#define AR7240_MAX_VLANS 16
+
+#define AR934X_REG_OPER_MODE0 0x04
+#define AR934X_OPER_MODE0_MAC_GMII_EN BIT(6)
+#define AR934X_OPER_MODE0_PHY_MII_EN BIT(10)
+
+#define AR934X_REG_OPER_MODE1 0x08
+#define AR934X_REG_OPER_MODE1_PHY4_MII_EN BIT(28)
+
+#define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
+
+#define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08)
+#define AR934X_PORT_VLAN1_DEFAULT_SVID_S 0
+#define AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN BIT(12)
+#define AR934X_PORT_VLAN1_PORT_TLS_MODE BIT(13)
+#define AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN BIT(14)
+#define AR934X_PORT_VLAN1_PORT_CLONE_EN BIT(15)
+#define AR934X_PORT_VLAN1_DEFAULT_CVID_S 16
+#define AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN BIT(28)
+#define AR934X_PORT_VLAN1_ING_PORT_PRI_S 29
+
+#define AR934X_REG_PORT_VLAN2(_port) (AR934X_REG_PORT_BASE((_port)) + 0x0c)
+#define AR934X_PORT_VLAN2_PORT_VID_MEM_S 16
+#define AR934X_PORT_VLAN2_8021Q_MODE_S 30
+#define AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY 0
+#define AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK 1
+#define AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY 2
+#define AR934X_PORT_VLAN2_8021Q_MODE_SECURE 3
+
+#define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
+
+struct ar7240sw_port_stat {
+ unsigned long rx_broadcast;
+ unsigned long rx_pause;
+ unsigned long rx_multicast;
+ unsigned long rx_fcs_error;
+ unsigned long rx_align_error;
+ unsigned long rx_runt;
+ unsigned long rx_fragments;
+ unsigned long rx_64byte;
+ unsigned long rx_128byte;
+ unsigned long rx_256byte;
+ unsigned long rx_512byte;
+ unsigned long rx_1024byte;
+ unsigned long rx_1518byte;
+ unsigned long rx_maxbyte;
+ unsigned long rx_toolong;
+ unsigned long rx_good_byte;
+ unsigned long rx_bad_byte;
+ unsigned long rx_overflow;
+ unsigned long filtered;
+
+ unsigned long tx_broadcast;
+ unsigned long tx_pause;
+ unsigned long tx_multicast;
+ unsigned long tx_underrun;
+ unsigned long tx_64byte;
+ unsigned long tx_128byte;
+ unsigned long tx_256byte;
+ unsigned long tx_512byte;
+ unsigned long tx_1024byte;
+ unsigned long tx_1518byte;
+ unsigned long tx_maxbyte;
+ unsigned long tx_oversize;
+ unsigned long tx_byte;
+ unsigned long tx_collision;
+ unsigned long tx_abortcol;
+ unsigned long tx_multicol;
+ unsigned long tx_singlecol;
+ unsigned long tx_excdefer;
+ unsigned long tx_defer;
+ unsigned long tx_xlatecol;
+};
+
+struct ar7240sw {
+ struct mii_bus *mii_bus;
+ struct ag71xx_switch_platform_data *swdata;
+ struct switch_dev swdev;
+ int num_ports;
+ u8 ver;
+ bool vlan;
+ u16 vlan_id[AR7240_MAX_VLANS];
+ u8 vlan_table[AR7240_MAX_VLANS];
+ u8 vlan_tagged;
+ u16 pvid[AR7240_NUM_PORTS];
+ char buf[80];
+
+ rwlock_t stats_lock;
+ struct ar7240sw_port_stat port_stats[AR7240_NUM_PORTS];
+};
+
+struct ar7240sw_hw_stat {
+ char string[ETH_GSTRING_LEN];
+ int sizeof_stat;
+ int reg;
+};
+
+static DEFINE_MUTEX(reg_mutex);
+
+static inline int sw_is_ar7240(struct ar7240sw *as)
+{
+ return as->ver == AR7240_MASK_CTRL_VERSION_AR7240;
+}
+
+static inline int sw_is_ar934x(struct ar7240sw *as)
+{
+ return as->ver == AR7240_MASK_CTRL_VERSION_AR934X;
+}
+
+static inline u32 ar7240sw_port_mask(struct ar7240sw *as, int port)
+{
+ return BIT(port);
+}
+
+static inline u32 ar7240sw_port_mask_all(struct ar7240sw *as)
+{
+ return BIT(as->swdev.ports) - 1;
+}
+
+static inline u32 ar7240sw_port_mask_but(struct ar7240sw *as, int port)
+{
+ return ar7240sw_port_mask_all(as) & ~BIT(port);
+}
+
+static inline u16 mk_phy_addr(u32 reg)
+{
+ return 0x17 & ((reg >> 4) | 0x10);
+}
+
+static inline u16 mk_phy_reg(u32 reg)
+{
+ return (reg << 1) & 0x1e;
+}
+
+static inline u16 mk_high_addr(u32 reg)
+{
+ return (reg >> 7) & 0x1ff;
+}
+
+static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg)
+{
+ unsigned long flags;
+ u16 phy_addr;
+ u16 phy_reg;
+ u32 hi, lo;
+
+ reg = (reg & 0xfffffffc) >> 2;
+ phy_addr = mk_phy_addr(reg);
+ phy_reg = mk_phy_reg(reg);
+
+ local_irq_save(flags);
+ ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
+ lo = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg);
+ hi = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg + 1);
+ local_irq_restore(flags);
+
+ return (hi << 16) | lo;
+}
+
+static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val)
+{
+ unsigned long flags;
+ u16 phy_addr;
+ u16 phy_reg;
+
+ reg = (reg & 0xfffffffc) >> 2;
+ phy_addr = mk_phy_addr(reg);
+ phy_reg = mk_phy_reg(reg);
+
+ local_irq_save(flags);
+ ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
+ ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg + 1, (val >> 16));
+ ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg, (val & 0xffff));
+ local_irq_restore(flags);
+}
+
+static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr)
+{
+ u32 ret;
+
+ mutex_lock(®_mutex);
+ ret = __ar7240sw_reg_read(mii, reg_addr);
+ mutex_unlock(®_mutex);
+
+ return ret;
+}
+
+static void ar7240sw_reg_write(struct mii_bus *mii, u32 reg_addr, u32 reg_val)
+{
+ mutex_lock(®_mutex);
+ __ar7240sw_reg_write(mii, reg_addr, reg_val);
+ mutex_unlock(®_mutex);
+}
+
+static u32 ar7240sw_reg_rmw(struct mii_bus *mii, u32 reg, u32 mask, u32 val)
+{
+ u32 t;
+
+ mutex_lock(®_mutex);
+ t = __ar7240sw_reg_read(mii, reg);
+ t &= ~mask;
+ t |= val;
+ __ar7240sw_reg_write(mii, reg, t);
+ mutex_unlock(®_mutex);
+
+ return t;
+}
+
+static void ar7240sw_reg_set(struct mii_bus *mii, u32 reg, u32 val)
+{
+ u32 t;
+
+ mutex_lock(®_mutex);
+ t = __ar7240sw_reg_read(mii, reg);
+ t |= val;
+ __ar7240sw_reg_write(mii, reg, t);
+ mutex_unlock(®_mutex);
+}
+
+static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
+ unsigned timeout)
+{
+ int i;
+
+ for (i = 0; i < timeout; i++) {
+ u32 t;
+
+ t = __ar7240sw_reg_read(mii, reg);
+ if ((t & mask) == val)
+ return 0;
+
+ msleep(1);
+ }
+
+ return -ETIMEDOUT;
+}
+
+static int ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
+ unsigned timeout)
+{
+ int ret;
+
+ mutex_lock(®_mutex);
+ ret = __ar7240sw_reg_wait(mii, reg, mask, val, timeout);
+ mutex_unlock(®_mutex);
+ return ret;
+}
+
+u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
+ unsigned reg_addr)
+{
+ u32 t, val = 0xffff;
+ int err;
+
+ if (phy_addr >= AR7240_NUM_PHYS)
+ return 0xffff;
+
+ mutex_lock(®_mutex);
+ t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
+ (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
+ AR7240_MDIO_CTRL_MASTER_EN |
+ AR7240_MDIO_CTRL_BUSY |
+ AR7240_MDIO_CTRL_CMD_READ;
+
+ __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
+ err = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
+ AR7240_MDIO_CTRL_BUSY, 0, 5);
+ if (!err)
+ val = __ar7240sw_reg_read(mii, AR7240_REG_MDIO_CTRL);
+ mutex_unlock(®_mutex);
+
+ return val & AR7240_MDIO_CTRL_DATA_M;
+}
+
+int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
+ unsigned reg_addr, u16 reg_val)
+{
+ u32 t;
+ int ret;
+
+ if (phy_addr >= AR7240_NUM_PHYS)
+ return -EINVAL;
+
+ mutex_lock(®_mutex);
+ t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
+ (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
+ AR7240_MDIO_CTRL_MASTER_EN |
+ AR7240_MDIO_CTRL_BUSY |
+ AR7240_MDIO_CTRL_CMD_WRITE |
+ reg_val;
+
+ __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
+ ret = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
+ AR7240_MDIO_CTRL_BUSY, 0, 5);
+ mutex_unlock(®_mutex);
+
+ return ret;
+}
+
+static int ar7240sw_capture_stats(struct ar7240sw *as)
+{
+ struct mii_bus *mii = as->mii_bus;
+ int port;
+ int ret;
+
+ write_lock(&as->stats_lock);
+
+ /* Capture the hardware statistics for all ports */
+ ar7240sw_reg_write(mii, AR7240_REG_MIB_FUNCTION0,
+ (AR7240_MIB_FUNC_CAPTURE << AR7240_MIB_FUNC_S));
+
+ /* Wait for the capturing to complete. */
+ ret = ar7240sw_reg_wait(mii, AR7240_REG_MIB_FUNCTION0,
+ AR7240_MIB_BUSY, 0, 10);
+
+ if (ret)
+ goto unlock;
+
+ for (port = 0; port < AR7240_NUM_PORTS; port++) {
+ unsigned int base;
+ struct ar7240sw_port_stat *stats;
+
+ base = AR7240_REG_STATS_BASE(port);
+ stats = &as->port_stats[port];
+
+#define READ_STAT(_r) ar7240sw_reg_read(mii, base + AR7240_STATS_ ## _r)
+
+ stats->rx_good_byte += READ_STAT(RXGOODBYTE);
+ stats->tx_byte += READ_STAT(TXBYTE);
+
+#undef READ_STAT
+ }
+
+ ret = 0;
+
+unlock:
+ write_unlock(&as->stats_lock);
+ return ret;
+}
+
+static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port)
+{
+ ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port),
+ AR7240_PORT_CTRL_STATE_DISABLED);
+}
+
+static void ar7240sw_setup(struct ar7240sw *as)
+{
+ struct mii_bus *mii = as->mii_bus;
+
+ /* Enable CPU port, and disable mirror port */
+ ar7240sw_reg_write(mii, AR7240_REG_CPU_PORT,
+ AR7240_CPU_PORT_EN |
+ (15 << AR7240_MIRROR_PORT_S));
+
+ /* Setup TAG priority mapping */
+ ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50);
+
+ /* Enable ARP frame acknowledge, aging, MAC replacing */
+ ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL,
+ AR7240_AT_CTRL_RESERVED |
+ 0x2b /* 5 min age time */ |
+ AR7240_AT_CTRL_AGE_EN |
+ AR7240_AT_CTRL_ARP_EN |
+ AR7240_AT_CTRL_LEARN_CHANGE);
+
+ /* Enable Broadcast frames transmitted to the CPU */
+ ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK,
+ AR7240_FLOOD_MASK_BROAD_TO_CPU);
+
+ /* setup MTU */
+ ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL, AR7240_GLOBAL_CTRL_MTU_M,
+ 1536);
+
+ /* setup Service TAG */
+ ar7240sw_reg_rmw(mii, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0);
+}
+
+static int ar7240sw_reset(struct ar7240sw *as)
+{
+ struct mii_bus *mii = as->mii_bus;
+ int ret;
+ int i;
+
+ /* Set all ports to disabled state. */
+ for (i = 0; i < AR7240_NUM_PORTS; i++)
+ ar7240sw_disable_port(as, i);
+
+ /* Wait for transmit queues to drain. */
+ msleep(2);
+
+ /* Reset the switch. */
+ ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL,
+ AR7240_MASK_CTRL_SOFT_RESET);
+
+ ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL,
+ AR7240_MASK_CTRL_SOFT_RESET, 0, 1000);
+
+ ar7240sw_setup(as);
+ return ret;
+}
+
+static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask)
+{
+ struct mii_bus *mii = as->mii_bus;
+ u32 ctrl;
+ u32 vid, mode;
+
+ ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN |
+ AR7240_PORT_CTRL_SINGLE_VLAN;
+
+ if (port == AR7240_PORT_CPU) {
+ ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
+ AR7240_PORT_STATUS_SPEED_1000 |
+ AR7240_PORT_STATUS_TXFLOW |
+ AR7240_PORT_STATUS_RXFLOW |
+ AR7240_PORT_STATUS_TXMAC |
+ AR7240_PORT_STATUS_RXMAC |
+ AR7240_PORT_STATUS_DUPLEX);
+ } else {
+ ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
+ AR7240_PORT_STATUS_LINK_AUTO);
+ }
+
+ /* Set the default VID for this port */
+ if (as->vlan) {
+ vid = as->vlan_id[as->pvid[port]];
+ mode = AR7240_PORT_VLAN_MODE_SECURE;
+ } else {
+ vid = port;
+ mode = AR7240_PORT_VLAN_MODE_PORT_ONLY;
+ }
+
+ if (as->vlan && (as->vlan_tagged & BIT(port))) {
+ ctrl |= AR7240_PORT_CTRL_VLAN_MODE_ADD <<
+ AR7240_PORT_CTRL_VLAN_MODE_S;
+ } else {
+ ctrl |= AR7240_PORT_CTRL_VLAN_MODE_STRIP <<
+ AR7240_PORT_CTRL_VLAN_MODE_S;
+ }
+
+ if (!portmask) {
+ if (port == AR7240_PORT_CPU)
+ portmask = ar7240sw_port_mask_but(as, AR7240_PORT_CPU);
+ else
+ portmask = ar7240sw_port_mask(as, AR7240_PORT_CPU);
+ }
+
+ /* allow the port to talk to all other ports, but exclude its
+ * own ID to prevent frames from being reflected back to the
+ * port that they came from */
+ portmask &= ar7240sw_port_mask_but(as, port);
+
+ ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl);
+ if (sw_is_ar934x(as)) {
+ u32 vlan1, vlan2;
+
+ vlan1 = (vid << AR934X_PORT_VLAN1_DEFAULT_CVID_S);
+ vlan2 = (portmask << AR934X_PORT_VLAN2_PORT_VID_MEM_S) |
+ (mode << AR934X_PORT_VLAN2_8021Q_MODE_S);
+ ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN1(port), vlan1);
+ ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN2(port), vlan2);
+ } else {
+ u32 vlan;
+
+ vlan = vid | (mode << AR7240_PORT_VLAN_MODE_S) |
+ (portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
+
+ ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan);
+ }
+}
+
+static int ar7240_set_addr(struct ar7240sw *as, u8 *addr)
+{
+ struct mii_bus *mii = as->mii_bus;
+ u32 t;
+
+ t = (addr[4] << 8) | addr[5];
+ ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR0, t);
+
+ t = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
+ ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR1, t);
+
+ return 0;
+}
+
+static int
+ar7240_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar7240sw *as = sw_to_ar7240(dev);
+ as->vlan_id[val->port_vlan] = val->value.i;
+ return 0;
+}
+
+static int
+ar7240_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar7240sw *as = sw_to_ar7240(dev);
+ val->value.i = as->vlan_id[val->port_vlan];
+ return 0;
+}
+
+static int
+ar7240_set_pvid(struct switch_dev *dev, int port, int vlan)
+{
+ struct ar7240sw *as = sw_to_ar7240(dev);
+
+ /* make sure no invalid PVIDs get set */
+
+ if (vlan >= dev->vlans)
+ return -EINVAL;
+
+ as->pvid[port] = vlan;
+ return 0;
+}
+
+static int
+ar7240_get_pvid(struct switch_dev *dev, int port, int *vlan)
+{
+ struct ar7240sw *as = sw_to_ar7240(dev);
+ *vlan = as->pvid[port];
+ return 0;
+}
+
+static int
+ar7240_get_ports(struct switch_dev *dev, struct switch_val *val)
+{
+ struct ar7240sw *as = sw_to_ar7240(dev);
+ u8 ports = as->vlan_table[val->port_vlan];
+ int i;
+
+ val->len = 0;
+ for (i = 0; i < as->swdev.ports; i++) {
+ struct switch_port *p;
+
+ if (!(ports & (1 << i)))
+ continue;
+
+ p = &val->value.ports[val->len++];
+ p->id = i;
+ if (as->vlan_tagged & (1 << i))
+ p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
+ else
+ p->flags = 0;
+ }
+ return 0;
+}
+
+static int
+ar7240_set_ports(struct switch_dev *dev, struct switch_val *val)
+{
+ struct ar7240sw *as = sw_to_ar7240(dev);
+ u8 *vt = &as->vlan_table[val->port_vlan];
+ int i, j;
+
+ *vt = 0;
+ for (i = 0; i < val->len; i++) {
+ struct switch_port *p = &val->value.ports[i];
+
+ if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED))
+ as->vlan_tagged |= (1 << p->id);
+ else {
+ as->vlan_tagged &= ~(1 << p->id);
+ as->pvid[p->id] = val->port_vlan;
+
+ /* make sure that an untagged port does not
+ * appear in other vlans */
+ for (j = 0; j < AR7240_MAX_VLANS; j++) {
+ if (j == val->port_vlan)
+ continue;
+ as->vlan_table[j] &= ~(1 << p->id);
+ }
+ }
+
+ *vt |= 1 << p->id;
+ }
+ return 0;
+}
+
+static int
+ar7240_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar7240sw *as = sw_to_ar7240(dev);
+ as->vlan = !!val->value.i;
+ return 0;
+}
+
+static int
+ar7240_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar7240sw *as = sw_to_ar7240(dev);
+ val->value.i = as->vlan;
+ return 0;
+}
+
+static const char *
+ar7240_speed_str(u32 status)
+{
+ u32 speed;
+
+ speed = (status >> AR7240_PORT_STATUS_SPEED_S) &
+ AR7240_PORT_STATUS_SPEED_M;
+ switch (speed) {
+ case AR7240_PORT_STATUS_SPEED_10:
+ return "10baseT";
+ case AR7240_PORT_STATUS_SPEED_100:
+ return "100baseT";
+ case AR7240_PORT_STATUS_SPEED_1000:
+ return "1000baseT";
+ }
+
+ return "unknown";
+}
+
+static int
+ar7240_port_get_link(struct switch_dev *dev, const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar7240sw *as = sw_to_ar7240(dev);
+ struct mii_bus *mii = as->mii_bus;
+ u32 len;
+ u32 status;
+ int port;
+
+ port = val->port_vlan;
+
+ memset(as->buf, '\0', sizeof(as->buf));
+ status = ar7240sw_reg_read(mii, AR7240_REG_PORT_STATUS(port));
+
+ if (status & AR7240_PORT_STATUS_LINK_UP) {
+ len = snprintf(as->buf, sizeof(as->buf),
+ "port:%d link:up speed:%s %s-duplex %s%s%s",
+ port,
+ ar7240_speed_str(status),
+ (status & AR7240_PORT_STATUS_DUPLEX) ?
+ "full" : "half",
+ (status & AR7240_PORT_STATUS_TXFLOW) ?
+ "txflow ": "",
+ (status & AR7240_PORT_STATUS_RXFLOW) ?
+ "rxflow " : "",
+ (status & AR7240_PORT_STATUS_LINK_AUTO) ?
+ "auto ": "");
+ } else {
+ len = snprintf(as->buf, sizeof(as->buf),
+ "port:%d link:down", port);
+ }
+
+ val->value.s = as->buf;
+ val->len = len;
+
+ return 0;
+}
+
+static void
+ar7240_vtu_op(struct ar7240sw *as, u32 op, u32 val)
+{
+ struct mii_bus *mii = as->mii_bus;
+
+ if (ar7240sw_reg_wait(mii, AR7240_REG_VTU, AR7240_VTU_ACTIVE, 0, 5))
+ return;
+
+ if ((op & AR7240_VTU_OP) == AR7240_VTU_OP_LOAD) {
+ val &= AR7240_VTUDATA_MEMBER;
+ val |= AR7240_VTUDATA_VALID;
+ ar7240sw_reg_write(mii, AR7240_REG_VTU_DATA, val);
+ }
+ op |= AR7240_VTU_ACTIVE;
+ ar7240sw_reg_write(mii, AR7240_REG_VTU, op);
+}
+
+static int
+ar7240_hw_apply(struct switch_dev *dev)
+{
+ struct ar7240sw *as = sw_to_ar7240(dev);
+ u8 portmask[AR7240_NUM_PORTS];
+ int i, j;
+
+ /* flush all vlan translation unit entries */
+ ar7240_vtu_op(as, AR7240_VTU_OP_FLUSH, 0);
+
+ memset(portmask, 0, sizeof(portmask));
+ if (as->vlan) {
+ /* calculate the port destination masks and load vlans
+ * into the vlan translation unit */
+ for (j = 0; j < AR7240_MAX_VLANS; j++) {
+ u8 vp = as->vlan_table[j];
+
+ if (!vp)
+ continue;
+
+ for (i = 0; i < as->swdev.ports; i++) {
+ u8 mask = (1 << i);
+ if (vp & mask)
+ portmask[i] |= vp & ~mask;
+ }
+
+ ar7240_vtu_op(as,
+ AR7240_VTU_OP_LOAD |
+ (as->vlan_id[j] << AR7240_VTU_VID_S),
+ as->vlan_table[j]);
+ }
+ } else {
+ /* vlan disabled:
+ * isolate all ports, but connect them to the cpu port */
+ for (i = 0; i < as->swdev.ports; i++) {
+ if (i == AR7240_PORT_CPU)
+ continue;
+
+ portmask[i] = 1 << AR7240_PORT_CPU;
+ portmask[AR7240_PORT_CPU] |= (1 << i);
+ }
+ }
+
+ /* update the port destination mask registers and tag settings */
+ for (i = 0; i < as->swdev.ports; i++)
+ ar7240sw_setup_port(as, i, portmask[i]);
+
+ return 0;
+}
+
+static int
+ar7240_reset_switch(struct switch_dev *dev)
+{
+ struct ar7240sw *as = sw_to_ar7240(dev);
+ ar7240sw_reset(as);
+ return 0;
+}
+
+static int
+ar7240_get_port_link(struct switch_dev *dev, int port,
+ struct switch_port_link *link)
+{
+ struct ar7240sw *as = sw_to_ar7240(dev);
+ struct mii_bus *mii = as->mii_bus;
+ u32 status;
+
+ if (port > AR7240_NUM_PORTS)
+ return -EINVAL;
+
+ status = ar7240sw_reg_read(mii, AR7240_REG_PORT_STATUS(port));
+
+ link->link = !!(status & AR7240_PORT_STATUS_LINK_UP);
+ link->aneg = !!(status & AR7240_PORT_STATUS_LINK_AUTO);
+ link->duplex = !!(status & AR7240_PORT_STATUS_DUPLEX);
+ link->tx_flow = !!(status & AR7240_PORT_STATUS_TXFLOW);
+ link->rx_flow = !!(status & AR7240_PORT_STATUS_RXFLOW);
+ switch (status & AR7240_PORT_STATUS_SPEED_M) {
+ case AR7240_PORT_STATUS_SPEED_10:
+ link->speed = SWITCH_PORT_SPEED_10;
+ break;
+ case AR7240_PORT_STATUS_SPEED_100:
+ link->speed = SWITCH_PORT_SPEED_100;
+ break;
+ case AR7240_PORT_STATUS_SPEED_1000:
+ link->speed = SWITCH_PORT_SPEED_1000;
+ break;
+ }
+
+ return 0;
+}
+
+static int
+ar7240_get_port_stats(struct switch_dev *dev, int port,
+ struct switch_port_stats *stats)
+{
+ struct ar7240sw *as = sw_to_ar7240(dev);
+
+ if (port > AR7240_NUM_PORTS)
+ return -EINVAL;
+
+ ar7240sw_capture_stats(as);
+
+ read_lock(&as->stats_lock);
+ stats->rx_bytes = as->port_stats[port].rx_good_byte;
+ stats->tx_bytes = as->port_stats[port].tx_byte;
+ read_unlock(&as->stats_lock);
+
+ return 0;
+}
+
+static struct switch_attr ar7240_globals[] = {
+ {
+ .type = SWITCH_TYPE_INT,
+ .name = "enable_vlan",
+ .description = "Enable VLAN mode",
+ .set = ar7240_set_vlan,
+ .get = ar7240_get_vlan,
+ .max = 1
+ },
+};
+
+static struct switch_attr ar7240_port[] = {
+ {
+ .type = SWITCH_TYPE_STRING,
+ .name = "link",
+ .description = "Get port link information",
+ .max = 1,
+ .set = NULL,
+ .get = ar7240_port_get_link,
+ },
+};
+
+static struct switch_attr ar7240_vlan[] = {
+ {
+ .type = SWITCH_TYPE_INT,
+ .name = "vid",
+ .description = "VLAN ID",
+ .set = ar7240_set_vid,
+ .get = ar7240_get_vid,
+ .max = 4094,
+ },
+};
+
+static const struct switch_dev_ops ar7240_ops = {
+ .attr_global = {
+ .attr = ar7240_globals,
+ .n_attr = ARRAY_SIZE(ar7240_globals),
+ },
+ .attr_port = {
+ .attr = ar7240_port,
+ .n_attr = ARRAY_SIZE(ar7240_port),
+ },
+ .attr_vlan = {
+ .attr = ar7240_vlan,
+ .n_attr = ARRAY_SIZE(ar7240_vlan),
+ },
+ .get_port_pvid = ar7240_get_pvid,
+ .set_port_pvid = ar7240_set_pvid,
+ .get_vlan_ports = ar7240_get_ports,
+ .set_vlan_ports = ar7240_set_ports,
+ .apply_config = ar7240_hw_apply,
+ .reset_switch = ar7240_reset_switch,
+ .get_port_link = ar7240_get_port_link,
+ .get_port_stats = ar7240_get_port_stats,
+};
+
+static struct ar7240sw *ar7240_probe(struct ag71xx *ag)
+{
+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
+ struct mii_bus *mii = ag->mii_bus;
+ struct ar7240sw *as;
+ struct switch_dev *swdev;
+ u32 ctrl;
+ u16 phy_id1;
+ u16 phy_id2;
+ int i;
+
+ phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1);
+ phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2);
+ if ((phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) &&
+ (phy_id1 != AR934X_PHY_ID1 || phy_id2 != AR934X_PHY_ID2)) {
+ pr_err("%s: unknown phy id '%04x:%04x'\n",
+ ag->dev->name, phy_id1, phy_id2);
+ return NULL;
+ }
+
+ as = kzalloc(sizeof(*as), GFP_KERNEL);
+ if (!as)
+ return NULL;
+
+ as->mii_bus = mii;
+ as->swdata = pdata->switch_data;
+
+ swdev = &as->swdev;
+
+ ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL);
+ as->ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) &
+ AR7240_MASK_CTRL_VERSION_M;
+
+ if (sw_is_ar7240(as)) {
+ swdev->name = "AR7240/AR9330 built-in switch";
+ } else if (sw_is_ar934x(as)) {
+ swdev->name = "AR934X built-in switch";
+
+ if (pdata->phy_if_mode == PHY_INTERFACE_MODE_GMII) {
+ ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
+ AR934X_OPER_MODE0_MAC_GMII_EN);
+ } else if (pdata->phy_if_mode == PHY_INTERFACE_MODE_MII) {
+ ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
+ AR934X_OPER_MODE0_PHY_MII_EN);
+ } else {
+ pr_err("%s: invalid PHY interface mode\n",
+ ag->dev->name);
+ goto err_free;
+ }
+
+ if (as->swdata->phy4_mii_en)
+ ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE1,
+ AR934X_REG_OPER_MODE1_PHY4_MII_EN);
+ } else {
+ pr_err("%s: unsupported chip, ctrl=%08x\n",
+ ag->dev->name, ctrl);
+ goto err_free;
+ }
+
+ swdev->ports = AR7240_NUM_PORTS - 1;
+ swdev->cpu_port = AR7240_PORT_CPU;
+ swdev->vlans = AR7240_MAX_VLANS;
+ swdev->ops = &ar7240_ops;
+
+ if (register_switch(&as->swdev, ag->dev) < 0)
+ goto err_free;
+
+ pr_info("%s: Found an %s\n", ag->dev->name, swdev->name);
+
+ /* initialize defaults */
+ for (i = 0; i < AR7240_MAX_VLANS; i++)
+ as->vlan_id[i] = i;
+
+ as->vlan_table[0] = ar7240sw_port_mask_all(as);
+
+ return as;
+
+err_free:
+ kfree(as);
+ return NULL;
+}
+
+static void link_function(struct work_struct *work) {
+ struct ag71xx *ag = container_of(work, struct ag71xx, link_work.work);
+ unsigned long flags;
+ int i;
+ int status = 0;
+
+ for (i = 0; i < 4; i++) {
+ int link = ar7240sw_phy_read(ag->mii_bus, i, MII_BMSR);
+ if(link & BMSR_LSTATUS) {
+ status = 1;
+ break;
+ }
+ }
+
+ spin_lock_irqsave(&ag->lock, flags);
+ if(status != ag->link) {
+ ag->link = status;
+ ag71xx_link_adjust(ag);
+ }
+ spin_unlock_irqrestore(&ag->lock, flags);
+
+ schedule_delayed_work(&ag->link_work, HZ / 2);
+}
+
+void ag71xx_ar7240_start(struct ag71xx *ag)
+{
+ struct ar7240sw *as = ag->phy_priv;
+
+ ar7240sw_reset(as);
+
+ ag->speed = SPEED_1000;
+ ag->duplex = 1;
+
+ ar7240_set_addr(as, ag->dev->dev_addr);
+ ar7240_hw_apply(&as->swdev);
+
+ schedule_delayed_work(&ag->link_work, HZ / 10);
+}
+
+void ag71xx_ar7240_stop(struct ag71xx *ag)
+{
+ cancel_delayed_work_sync(&ag->link_work);
+}
+
+int __devinit ag71xx_ar7240_init(struct ag71xx *ag)
+{
+ struct ar7240sw *as;
+
+ as = ar7240_probe(ag);
+ if (!as)
+ return -ENODEV;
+
+ ag->phy_priv = as;
+ ar7240sw_reset(as);
+
+ rwlock_init(&as->stats_lock);
+ INIT_DELAYED_WORK(&ag->link_work, link_function);
+
+ return 0;
+}
+
+void ag71xx_ar7240_cleanup(struct ag71xx *ag)
+{
+ struct ar7240sw *as = ag->phy_priv;
+
+ if (!as)
+ return;
+
+ unregister_switch(&as->swdev);
+ kfree(as);
+ ag->phy_priv = NULL;
+}
--- /dev/null
+/*
+ * Atheros AR71xx built-in ethernet mac driver
+ * Special support for the Atheros ar8216 switch chip
+ *
+ * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * Based on Atheros' AG7100 driver
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include "ag71xx.h"
+
+#define AR8216_PACKET_TYPE_MASK 0xf
+#define AR8216_PACKET_TYPE_NORMAL 0
+
+#define AR8216_HEADER_LEN 2
+
+void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb)
+{
+ skb_push(skb, AR8216_HEADER_LEN);
+ skb->data[0] = 0x10;
+ skb->data[1] = 0x80;
+}
+
+int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb,
+ int pktlen)
+{
+ u8 type;
+
+ type = skb->data[1] & AR8216_PACKET_TYPE_MASK;
+ switch (type) {
+ case AR8216_PACKET_TYPE_NORMAL:
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ skb_pull(skb, AR8216_HEADER_LEN);
+ return 0;
+}
--- /dev/null
+/*
+ * Atheros AR71xx built-in ethernet mac driver
+ *
+ * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * Based on Atheros' AG7100 driver
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/debugfs.h>
+
+#include "ag71xx.h"
+
+static struct dentry *ag71xx_debugfs_root;
+
+static int ag71xx_debugfs_generic_open(struct inode *inode, struct file *file)
+{
+ file->private_data = inode->i_private;
+ return 0;
+}
+
+void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status)
+{
+ if (status)
+ ag->debug.int_stats.total++;
+ if (status & AG71XX_INT_TX_PS)
+ ag->debug.int_stats.tx_ps++;
+ if (status & AG71XX_INT_TX_UR)
+ ag->debug.int_stats.tx_ur++;
+ if (status & AG71XX_INT_TX_BE)
+ ag->debug.int_stats.tx_be++;
+ if (status & AG71XX_INT_RX_PR)
+ ag->debug.int_stats.rx_pr++;
+ if (status & AG71XX_INT_RX_OF)
+ ag->debug.int_stats.rx_of++;
+ if (status & AG71XX_INT_RX_BE)
+ ag->debug.int_stats.rx_be++;
+}
+
+static ssize_t read_file_int_stats(struct file *file, char __user *user_buf,
+ size_t count, loff_t *ppos)
+{
+#define PR_INT_STAT(_label, _field) \
+ len += snprintf(buf + len, sizeof(buf) - len, \
+ "%20s: %10lu\n", _label, ag->debug.int_stats._field);
+
+ struct ag71xx *ag = file->private_data;
+ char buf[256];
+ unsigned int len = 0;
+
+ PR_INT_STAT("TX Packet Sent", tx_ps);
+ PR_INT_STAT("TX Underrun", tx_ur);
+ PR_INT_STAT("TX Bus Error", tx_be);
+ PR_INT_STAT("RX Packet Received", rx_pr);
+ PR_INT_STAT("RX Overflow", rx_of);
+ PR_INT_STAT("RX Bus Error", rx_be);
+ len += snprintf(buf + len, sizeof(buf) - len, "\n");
+ PR_INT_STAT("Total", total);
+
+ return simple_read_from_buffer(user_buf, count, ppos, buf, len);
+#undef PR_INT_STAT
+}
+
+static const struct file_operations ag71xx_fops_int_stats = {
+ .open = ag71xx_debugfs_generic_open,
+ .read = read_file_int_stats,
+ .owner = THIS_MODULE
+};
+
+void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx)
+{
+ struct ag71xx_napi_stats *stats = &ag->debug.napi_stats;
+
+ if (rx) {
+ stats->rx_count++;
+ stats->rx_packets += rx;
+ if (rx <= AG71XX_NAPI_WEIGHT)
+ stats->rx[rx]++;
+ if (rx > stats->rx_packets_max)
+ stats->rx_packets_max = rx;
+ }
+
+ if (tx) {
+ stats->tx_count++;
+ stats->tx_packets += tx;
+ if (tx <= AG71XX_NAPI_WEIGHT)
+ stats->tx[tx]++;
+ if (tx > stats->tx_packets_max)
+ stats->tx_packets_max = tx;
+ }
+}
+
+static ssize_t read_file_napi_stats(struct file *file, char __user *user_buf,
+ size_t count, loff_t *ppos)
+{
+ struct ag71xx *ag = file->private_data;
+ struct ag71xx_napi_stats *stats = &ag->debug.napi_stats;
+ char *buf;
+ unsigned int buflen;
+ unsigned int len = 0;
+ unsigned long rx_avg = 0;
+ unsigned long tx_avg = 0;
+ int ret;
+ int i;
+
+ buflen = 2048;
+ buf = kmalloc(buflen, GFP_KERNEL);
+ if (!buf)
+ return -ENOMEM;
+
+ if (stats->rx_count)
+ rx_avg = stats->rx_packets / stats->rx_count;
+
+ if (stats->tx_count)
+ tx_avg = stats->tx_packets / stats->tx_count;
+
+ len += snprintf(buf + len, buflen - len, "%3s %10s %10s\n",
+ "len", "rx", "tx");
+
+ for (i = 1; i <= AG71XX_NAPI_WEIGHT; i++)
+ len += snprintf(buf + len, buflen - len,
+ "%3d: %10lu %10lu\n",
+ i, stats->rx[i], stats->tx[i]);
+
+ len += snprintf(buf + len, buflen - len, "\n");
+
+ len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n",
+ "sum", stats->rx_count, stats->tx_count);
+ len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n",
+ "avg", rx_avg, tx_avg);
+ len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n",
+ "max", stats->rx_packets_max, stats->tx_packets_max);
+ len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n",
+ "pkt", stats->rx_packets, stats->tx_packets);
+
+ ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
+ kfree(buf);
+
+ return ret;
+}
+
+static const struct file_operations ag71xx_fops_napi_stats = {
+ .open = ag71xx_debugfs_generic_open,
+ .read = read_file_napi_stats,
+ .owner = THIS_MODULE
+};
+
+#define DESC_PRINT_LEN 64
+
+static ssize_t read_file_ring(struct file *file, char __user *user_buf,
+ size_t count, loff_t *ppos,
+ struct ag71xx *ag,
+ struct ag71xx_ring *ring,
+ unsigned desc_reg)
+{
+ char *buf;
+ unsigned int buflen;
+ unsigned int len = 0;
+ unsigned long flags;
+ ssize_t ret;
+ int curr;
+ int dirty;
+ u32 desc_hw;
+ int i;
+
+ buflen = (ring->size * DESC_PRINT_LEN);
+ buf = kmalloc(buflen, GFP_KERNEL);
+ if (!buf)
+ return -ENOMEM;
+
+ len += snprintf(buf + len, buflen - len,
+ "Idx ... %-8s %-8s %-8s %-8s . %-10s\n",
+ "desc", "next", "data", "ctrl", "timestamp");
+
+ spin_lock_irqsave(&ag->lock, flags);
+
+ curr = (ring->curr % ring->size);
+ dirty = (ring->dirty % ring->size);
+ desc_hw = ag71xx_rr(ag, desc_reg);
+ for (i = 0; i < ring->size; i++) {
+ struct ag71xx_buf *ab = &ring->buf[i];
+ u32 desc_dma = ((u32) ring->descs_dma) + i * ring->desc_size;
+
+ len += snprintf(buf + len, buflen - len,
+ "%3d %c%c%c %08x %08x %08x %08x %c %10lu\n",
+ i,
+ (i == curr) ? 'C' : ' ',
+ (i == dirty) ? 'D' : ' ',
+ (desc_hw == desc_dma) ? 'H' : ' ',
+ desc_dma,
+ ab->desc->next,
+ ab->desc->data,
+ ab->desc->ctrl,
+ (ab->desc->ctrl & DESC_EMPTY) ? 'E' : '*',
+ ab->timestamp);
+ }
+
+ spin_unlock_irqrestore(&ag->lock, flags);
+
+ ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
+ kfree(buf);
+
+ return ret;
+}
+
+static ssize_t read_file_tx_ring(struct file *file, char __user *user_buf,
+ size_t count, loff_t *ppos)
+{
+ struct ag71xx *ag = file->private_data;
+
+ return read_file_ring(file, user_buf, count, ppos, ag, &ag->tx_ring,
+ AG71XX_REG_TX_DESC);
+}
+
+static const struct file_operations ag71xx_fops_tx_ring = {
+ .open = ag71xx_debugfs_generic_open,
+ .read = read_file_tx_ring,
+ .owner = THIS_MODULE
+};
+
+static ssize_t read_file_rx_ring(struct file *file, char __user *user_buf,
+ size_t count, loff_t *ppos)
+{
+ struct ag71xx *ag = file->private_data;
+
+ return read_file_ring(file, user_buf, count, ppos, ag, &ag->rx_ring,
+ AG71XX_REG_RX_DESC);
+}
+
+static const struct file_operations ag71xx_fops_rx_ring = {
+ .open = ag71xx_debugfs_generic_open,
+ .read = read_file_rx_ring,
+ .owner = THIS_MODULE
+};
+
+void ag71xx_debugfs_exit(struct ag71xx *ag)
+{
+ debugfs_remove_recursive(ag->debug.debugfs_dir);
+}
+
+int ag71xx_debugfs_init(struct ag71xx *ag)
+{
+ ag->debug.debugfs_dir = debugfs_create_dir(ag->dev->name,
+ ag71xx_debugfs_root);
+ if (!ag->debug.debugfs_dir)
+ return -ENOMEM;
+
+ debugfs_create_file("int_stats", S_IRUGO, ag->debug.debugfs_dir,
+ ag, &ag71xx_fops_int_stats);
+ debugfs_create_file("napi_stats", S_IRUGO, ag->debug.debugfs_dir,
+ ag, &ag71xx_fops_napi_stats);
+ debugfs_create_file("tx_ring", S_IRUGO, ag->debug.debugfs_dir,
+ ag, &ag71xx_fops_tx_ring);
+ debugfs_create_file("rx_ring", S_IRUGO, ag->debug.debugfs_dir,
+ ag, &ag71xx_fops_rx_ring);
+
+ return 0;
+}
+
+int ag71xx_debugfs_root_init(void)
+{
+ if (ag71xx_debugfs_root)
+ return -EBUSY;
+
+ ag71xx_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
+ if (!ag71xx_debugfs_root)
+ return -ENOENT;
+
+ return 0;
+}
+
+void ag71xx_debugfs_root_exit(void)
+{
+ debugfs_remove(ag71xx_debugfs_root);
+ ag71xx_debugfs_root = NULL;
+}
--- /dev/null
+/*
+ * Atheros AR71xx built-in ethernet mac driver
+ *
+ * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * Based on Atheros' AG7100 driver
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include "ag71xx.h"
+
+static int ag71xx_ethtool_get_settings(struct net_device *dev,
+ struct ethtool_cmd *cmd)
+{
+ struct ag71xx *ag = netdev_priv(dev);
+ struct phy_device *phydev = ag->phy_dev;
+
+ if (!phydev)
+ return -ENODEV;
+
+ return phy_ethtool_gset(phydev, cmd);
+}
+
+static int ag71xx_ethtool_set_settings(struct net_device *dev,
+ struct ethtool_cmd *cmd)
+{
+ struct ag71xx *ag = netdev_priv(dev);
+ struct phy_device *phydev = ag->phy_dev;
+
+ if (!phydev)
+ return -ENODEV;
+
+ return phy_ethtool_sset(phydev, cmd);
+}
+
+static void ag71xx_ethtool_get_drvinfo(struct net_device *dev,
+ struct ethtool_drvinfo *info)
+{
+ struct ag71xx *ag = netdev_priv(dev);
+
+ strcpy(info->driver, ag->pdev->dev.driver->name);
+ strcpy(info->version, AG71XX_DRV_VERSION);
+ strcpy(info->bus_info, dev_name(&ag->pdev->dev));
+}
+
+static u32 ag71xx_ethtool_get_msglevel(struct net_device *dev)
+{
+ struct ag71xx *ag = netdev_priv(dev);
+
+ return ag->msg_enable;
+}
+
+static void ag71xx_ethtool_set_msglevel(struct net_device *dev, u32 msg_level)
+{
+ struct ag71xx *ag = netdev_priv(dev);
+
+ ag->msg_enable = msg_level;
+}
+
+static void ag71xx_ethtool_get_ringparam(struct net_device *dev,
+ struct ethtool_ringparam *er)
+{
+ struct ag71xx *ag = netdev_priv(dev);
+
+ er->tx_max_pending = AG71XX_TX_RING_SIZE_MAX;
+ er->rx_max_pending = AG71XX_RX_RING_SIZE_MAX;
+ er->rx_mini_max_pending = 0;
+ er->rx_jumbo_max_pending = 0;
+
+ er->tx_pending = ag->tx_ring.size;
+ er->rx_pending = ag->rx_ring.size;
+ er->rx_mini_pending = 0;
+ er->rx_jumbo_pending = 0;
+}
+
+static int ag71xx_ethtool_set_ringparam(struct net_device *dev,
+ struct ethtool_ringparam *er)
+{
+ struct ag71xx *ag = netdev_priv(dev);
+ unsigned tx_size;
+ unsigned rx_size;
+ int err;
+
+ if (er->rx_mini_pending != 0||
+ er->rx_jumbo_pending != 0 ||
+ er->rx_pending == 0 ||
+ er->tx_pending == 0)
+ return -EINVAL;
+
+ tx_size = er->tx_pending < AG71XX_TX_RING_SIZE_MAX ?
+ er->tx_pending : AG71XX_TX_RING_SIZE_MAX;
+
+ rx_size = er->rx_pending < AG71XX_RX_RING_SIZE_MAX ?
+ er->rx_pending : AG71XX_RX_RING_SIZE_MAX;
+
+ if (netif_running(dev)) {
+ err = dev->netdev_ops->ndo_stop(dev);
+ if (err)
+ return err;
+ }
+
+ ag->tx_ring.size = tx_size;
+ ag->rx_ring.size = rx_size;
+
+ if (netif_running(dev))
+ err = dev->netdev_ops->ndo_open(dev);
+
+ return err;
+}
+
+struct ethtool_ops ag71xx_ethtool_ops = {
+ .set_settings = ag71xx_ethtool_set_settings,
+ .get_settings = ag71xx_ethtool_get_settings,
+ .get_drvinfo = ag71xx_ethtool_get_drvinfo,
+ .get_msglevel = ag71xx_ethtool_get_msglevel,
+ .set_msglevel = ag71xx_ethtool_set_msglevel,
+ .get_ringparam = ag71xx_ethtool_get_ringparam,
+ .set_ringparam = ag71xx_ethtool_set_ringparam,
+ .get_link = ethtool_op_get_link,
+};
--- /dev/null
+/*
+ * Atheros AR71xx built-in ethernet mac driver
+ *
+ * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * Based on Atheros' AG7100 driver
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include "ag71xx.h"
+
+#define AG71XX_DEFAULT_MSG_ENABLE \
+ (NETIF_MSG_DRV \
+ | NETIF_MSG_PROBE \
+ | NETIF_MSG_LINK \
+ | NETIF_MSG_TIMER \
+ | NETIF_MSG_IFDOWN \
+ | NETIF_MSG_IFUP \
+ | NETIF_MSG_RX_ERR \
+ | NETIF_MSG_TX_ERR)
+
+static int ag71xx_msg_level = -1;
+
+module_param_named(msg_level, ag71xx_msg_level, int, 0);
+MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
+
+static void ag71xx_dump_dma_regs(struct ag71xx *ag)
+{
+ DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
+ ag->dev->name,
+ ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
+ ag71xx_rr(ag, AG71XX_REG_TX_DESC),
+ ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
+
+ DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
+ ag->dev->name,
+ ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
+ ag71xx_rr(ag, AG71XX_REG_RX_DESC),
+ ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
+}
+
+static void ag71xx_dump_regs(struct ag71xx *ag)
+{
+ DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
+ ag->dev->name,
+ ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
+ ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
+ ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
+ ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
+ ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
+ DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
+ ag->dev->name,
+ ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
+ ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
+ ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
+ DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
+ ag->dev->name,
+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
+ DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
+ ag->dev->name,
+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
+}
+
+static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
+{
+ DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
+ ag->dev->name, label, intr,
+ (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
+ (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
+ (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
+ (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
+ (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
+ (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
+}
+
+static void ag71xx_ring_free(struct ag71xx_ring *ring)
+{
+ kfree(ring->buf);
+
+ if (ring->descs_cpu)
+ dma_free_coherent(NULL, ring->size * ring->desc_size,
+ ring->descs_cpu, ring->descs_dma);
+}
+
+static int ag71xx_ring_alloc(struct ag71xx_ring *ring)
+{
+ int err;
+ int i;
+
+ ring->desc_size = sizeof(struct ag71xx_desc);
+ if (ring->desc_size % cache_line_size()) {
+ DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
+ ring, ring->desc_size,
+ roundup(ring->desc_size, cache_line_size()));
+ ring->desc_size = roundup(ring->desc_size, cache_line_size());
+ }
+
+ ring->descs_cpu = dma_alloc_coherent(NULL, ring->size * ring->desc_size,
+ &ring->descs_dma, GFP_ATOMIC);
+ if (!ring->descs_cpu) {
+ err = -ENOMEM;
+ goto err;
+ }
+
+
+ ring->buf = kzalloc(ring->size * sizeof(*ring->buf), GFP_KERNEL);
+ if (!ring->buf) {
+ err = -ENOMEM;
+ goto err;
+ }
+
+ for (i = 0; i < ring->size; i++) {
+ int idx = i * ring->desc_size;
+ ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[idx];
+ DBG("ag71xx: ring %p, desc %d at %p\n",
+ ring, i, ring->buf[i].desc);
+ }
+
+ return 0;
+
+err:
+ return err;
+}
+
+static void ag71xx_ring_tx_clean(struct ag71xx *ag)
+{
+ struct ag71xx_ring *ring = &ag->tx_ring;
+ struct net_device *dev = ag->dev;
+
+ while (ring->curr != ring->dirty) {
+ u32 i = ring->dirty % ring->size;
+
+ if (!ag71xx_desc_empty(ring->buf[i].desc)) {
+ ring->buf[i].desc->ctrl = 0;
+ dev->stats.tx_errors++;
+ }
+
+ if (ring->buf[i].skb)
+ dev_kfree_skb_any(ring->buf[i].skb);
+
+ ring->buf[i].skb = NULL;
+
+ ring->dirty++;
+ }
+
+ /* flush descriptors */
+ wmb();
+
+}
+
+static void ag71xx_ring_tx_init(struct ag71xx *ag)
+{
+ struct ag71xx_ring *ring = &ag->tx_ring;
+ int i;
+
+ for (i = 0; i < ring->size; i++) {
+ ring->buf[i].desc->next = (u32) (ring->descs_dma +
+ ring->desc_size * ((i + 1) % ring->size));
+
+ ring->buf[i].desc->ctrl = DESC_EMPTY;
+ ring->buf[i].skb = NULL;
+ }
+
+ /* flush descriptors */
+ wmb();
+
+ ring->curr = 0;
+ ring->dirty = 0;
+}
+
+static void ag71xx_ring_rx_clean(struct ag71xx *ag)
+{
+ struct ag71xx_ring *ring = &ag->rx_ring;
+ int i;
+
+ if (!ring->buf)
+ return;
+
+ for (i = 0; i < ring->size; i++)
+ if (ring->buf[i].skb) {
+ dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
+ AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
+ kfree_skb(ring->buf[i].skb);
+ }
+}
+
+static int ag71xx_rx_reserve(struct ag71xx *ag)
+{
+ int reserve = 0;
+
+ if (ag71xx_get_pdata(ag)->is_ar724x) {
+ if (!ag71xx_has_ar8216(ag))
+ reserve = 2;
+
+ if (ag->phy_dev)
+ reserve += 4 - (ag->phy_dev->pkt_align % 4);
+
+ reserve %= 4;
+ }
+
+ return reserve + AG71XX_RX_PKT_RESERVE;
+}
+
+
+static int ag71xx_ring_rx_init(struct ag71xx *ag)
+{
+ struct ag71xx_ring *ring = &ag->rx_ring;
+ unsigned int reserve = ag71xx_rx_reserve(ag);
+ unsigned int i;
+ int ret;
+
+ ret = 0;
+ for (i = 0; i < ring->size; i++) {
+ ring->buf[i].desc->next = (u32) (ring->descs_dma +
+ ring->desc_size * ((i + 1) % ring->size));
+
+ DBG("ag71xx: RX desc at %p, next is %08x\n",
+ ring->buf[i].desc,
+ ring->buf[i].desc->next);
+ }
+
+ for (i = 0; i < ring->size; i++) {
+ struct sk_buff *skb;
+ dma_addr_t dma_addr;
+
+ skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve);
+ if (!skb) {
+ ret = -ENOMEM;
+ break;
+ }
+
+ skb->dev = ag->dev;
+ skb_reserve(skb, reserve);
+
+ dma_addr = dma_map_single(&ag->dev->dev, skb->data,
+ AG71XX_RX_PKT_SIZE,
+ DMA_FROM_DEVICE);
+ ring->buf[i].skb = skb;
+ ring->buf[i].dma_addr = dma_addr;
+ ring->buf[i].desc->data = (u32) dma_addr;
+ ring->buf[i].desc->ctrl = DESC_EMPTY;
+ }
+
+ /* flush descriptors */
+ wmb();
+
+ ring->curr = 0;
+ ring->dirty = 0;
+
+ return ret;
+}
+
+static int ag71xx_ring_rx_refill(struct ag71xx *ag)
+{
+ struct ag71xx_ring *ring = &ag->rx_ring;
+ unsigned int reserve = ag71xx_rx_reserve(ag);
+ unsigned int count;
+
+ count = 0;
+ for (; ring->curr - ring->dirty > 0; ring->dirty++) {
+ unsigned int i;
+
+ i = ring->dirty % ring->size;
+
+ if (ring->buf[i].skb == NULL) {
+ dma_addr_t dma_addr;
+ struct sk_buff *skb;
+
+ skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve);
+ if (skb == NULL)
+ break;
+
+ skb_reserve(skb, reserve);
+ skb->dev = ag->dev;
+
+ dma_addr = dma_map_single(&ag->dev->dev, skb->data,
+ AG71XX_RX_PKT_SIZE,
+ DMA_FROM_DEVICE);
+
+ ring->buf[i].skb = skb;
+ ring->buf[i].dma_addr = dma_addr;
+ ring->buf[i].desc->data = (u32) dma_addr;
+ }
+
+ ring->buf[i].desc->ctrl = DESC_EMPTY;
+ count++;
+ }
+
+ /* flush descriptors */
+ wmb();
+
+ DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
+
+ return count;
+}
+
+static int ag71xx_rings_init(struct ag71xx *ag)
+{
+ int ret;
+
+ ret = ag71xx_ring_alloc(&ag->tx_ring);
+ if (ret)
+ return ret;
+
+ ag71xx_ring_tx_init(ag);
+
+ ret = ag71xx_ring_alloc(&ag->rx_ring);
+ if (ret)
+ return ret;
+
+ ret = ag71xx_ring_rx_init(ag);
+ return ret;
+}
+
+static void ag71xx_rings_cleanup(struct ag71xx *ag)
+{
+ ag71xx_ring_rx_clean(ag);
+ ag71xx_ring_free(&ag->rx_ring);
+
+ ag71xx_ring_tx_clean(ag);
+ ag71xx_ring_free(&ag->tx_ring);
+}
+
+static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
+{
+ switch (ag->speed) {
+ case SPEED_1000:
+ return "1000";
+ case SPEED_100:
+ return "100";
+ case SPEED_10:
+ return "10";
+ }
+
+ return "?";
+}
+
+static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
+{
+ u32 t;
+
+ t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
+ | (((u32) mac[3]) << 8) | ((u32) mac[2]);
+
+ ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
+
+ t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
+ ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
+}
+
+static void ag71xx_dma_reset(struct ag71xx *ag)
+{
+ u32 val;
+ int i;
+
+ ag71xx_dump_dma_regs(ag);
+
+ /* stop RX and TX */
+ ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
+ ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
+
+ /*
+ * give the hardware some time to really stop all rx/tx activity
+ * clearing the descriptors too early causes random memory corruption
+ */
+ mdelay(1);
+
+ /* clear descriptor addresses */
+ ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
+ ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
+
+ /* clear pending RX/TX interrupts */
+ for (i = 0; i < 256; i++) {
+ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
+ ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
+ }
+
+ /* clear pending errors */
+ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
+ ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
+
+ val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
+ if (val)
+ pr_alert("%s: unable to clear DMA Rx status: %08x\n",
+ ag->dev->name, val);
+
+ val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
+
+ /* mask out reserved bits */
+ val &= ~0xff000000;
+
+ if (val)
+ pr_alert("%s: unable to clear DMA Tx status: %08x\n",
+ ag->dev->name, val);
+
+ ag71xx_dump_dma_regs(ag);
+}
+
+#define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
+ MAC_CFG1_SRX | MAC_CFG1_STX)
+
+#define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
+
+#define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
+ FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
+ FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
+ FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
+ FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
+ FIFO_CFG4_VT)
+
+#define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
+ FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
+ FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
+ FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
+ FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
+ FIFO_CFG5_17 | FIFO_CFG5_SF)
+
+static void ag71xx_hw_stop(struct ag71xx *ag)
+{
+ /* disable all interrupts and stop the rx/tx engine */
+ ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
+ ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
+ ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
+}
+
+static void ag71xx_hw_setup(struct ag71xx *ag)
+{
+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
+
+ /* setup MAC configuration registers */
+ ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
+
+ ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
+ MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
+
+ /* setup max frame length */
+ ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
+
+ /* setup FIFO configuration registers */
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
+ if (pdata->is_ar724x) {
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
+ } else {
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
+ }
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
+}
+
+static void ag71xx_hw_init(struct ag71xx *ag)
+{
+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
+ u32 reset_mask = pdata->reset_bit;
+
+ ag71xx_hw_stop(ag);
+
+ if (pdata->is_ar724x) {
+ u32 reset_phy = reset_mask;
+
+ reset_phy &= AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY;
+ reset_mask &= ~(AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY);
+
+ ath79_device_reset_set(reset_phy);
+ mdelay(50);
+ ath79_device_reset_clear(reset_phy);
+ mdelay(200);
+ }
+
+ ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
+ udelay(20);
+
+ ath79_device_reset_set(reset_mask);
+ mdelay(100);
+ ath79_device_reset_clear(reset_mask);
+ mdelay(200);
+
+ ag71xx_hw_setup(ag);
+
+ ag71xx_dma_reset(ag);
+}
+
+static void ag71xx_fast_reset(struct ag71xx *ag)
+{
+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
+ struct net_device *dev = ag->dev;
+ u32 reset_mask = pdata->reset_bit;
+ u32 rx_ds, tx_ds;
+ u32 mii_reg;
+
+ reset_mask &= AR71XX_RESET_GE0_MAC | AR71XX_RESET_GE1_MAC;
+
+ mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
+ rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
+ tx_ds = ag71xx_rr(ag, AG71XX_REG_TX_DESC);
+
+ ath79_device_reset_set(reset_mask);
+ udelay(10);
+ ath79_device_reset_clear(reset_mask);
+ udelay(10);
+
+ ag71xx_dma_reset(ag);
+ ag71xx_hw_setup(ag);
+
+ ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
+ ag71xx_wr(ag, AG71XX_REG_TX_DESC, tx_ds);
+ ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
+
+ ag71xx_hw_set_macaddr(ag, dev->dev_addr);
+}
+
+static void ag71xx_hw_start(struct ag71xx *ag)
+{
+ /* start RX engine */
+ ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
+
+ /* enable interrupts */
+ ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
+}
+
+void ag71xx_link_adjust(struct ag71xx *ag)
+{
+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
+ u32 cfg2;
+ u32 ifctl;
+ u32 fifo5;
+
+ if (!ag->link) {
+ ag71xx_hw_stop(ag);
+ netif_carrier_off(ag->dev);
+ if (netif_msg_link(ag))
+ pr_info("%s: link down\n", ag->dev->name);
+ return;
+ }
+
+ if (pdata->is_ar724x)
+ ag71xx_fast_reset(ag);
+
+ cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
+ cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
+ cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
+
+ ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
+ ifctl &= ~(MAC_IFCTL_SPEED);
+
+ fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
+ fifo5 &= ~FIFO_CFG5_BM;
+
+ switch (ag->speed) {
+ case SPEED_1000:
+ cfg2 |= MAC_CFG2_IF_1000;
+ fifo5 |= FIFO_CFG5_BM;
+ break;
+ case SPEED_100:
+ cfg2 |= MAC_CFG2_IF_10_100;
+ ifctl |= MAC_IFCTL_SPEED;
+ break;
+ case SPEED_10:
+ cfg2 |= MAC_CFG2_IF_10_100;
+ break;
+ default:
+ BUG();
+ return;
+ }
+
+ if (pdata->is_ar91xx)
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff);
+ else if (pdata->is_ar724x)
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3);
+ else
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
+
+ if (pdata->set_speed)
+ pdata->set_speed(ag->speed);
+
+ ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
+ ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
+ ag71xx_hw_start(ag);
+
+ netif_carrier_on(ag->dev);
+ if (netif_msg_link(ag))
+ pr_info("%s: link up (%sMbps/%s duplex)\n",
+ ag->dev->name,
+ ag71xx_speed_str(ag),
+ (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
+
+ DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
+ ag->dev->name,
+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
+
+ DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
+ ag->dev->name,
+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
+
+ DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x\n",
+ ag->dev->name,
+ ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
+ ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL));
+}
+
+static int ag71xx_open(struct net_device *dev)
+{
+ struct ag71xx *ag = netdev_priv(dev);
+ int ret;
+
+ ret = ag71xx_rings_init(ag);
+ if (ret)
+ goto err;
+
+ napi_enable(&ag->napi);
+
+ netif_carrier_off(dev);
+ ag71xx_phy_start(ag);
+
+ ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
+ ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
+
+ ag71xx_hw_set_macaddr(ag, dev->dev_addr);
+
+ netif_start_queue(dev);
+
+ return 0;
+
+err:
+ ag71xx_rings_cleanup(ag);
+ return ret;
+}
+
+static int ag71xx_stop(struct net_device *dev)
+{
+ struct ag71xx *ag = netdev_priv(dev);
+ unsigned long flags;
+
+ netif_carrier_off(dev);
+ ag71xx_phy_stop(ag);
+
+ spin_lock_irqsave(&ag->lock, flags);
+
+ netif_stop_queue(dev);
+
+ ag71xx_hw_stop(ag);
+ ag71xx_dma_reset(ag);
+
+ napi_disable(&ag->napi);
+ del_timer_sync(&ag->oom_timer);
+
+ spin_unlock_irqrestore(&ag->lock, flags);
+
+ ag71xx_rings_cleanup(ag);
+
+ return 0;
+}
+
+static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
+ struct net_device *dev)
+{
+ struct ag71xx *ag = netdev_priv(dev);
+ struct ag71xx_ring *ring = &ag->tx_ring;
+ struct ag71xx_desc *desc;
+ dma_addr_t dma_addr;
+ int i;
+
+ i = ring->curr % ring->size;
+ desc = ring->buf[i].desc;
+
+ if (!ag71xx_desc_empty(desc))
+ goto err_drop;
+
+ if (ag71xx_has_ar8216(ag))
+ ag71xx_add_ar8216_header(ag, skb);
+
+ if (skb->len <= 0) {
+ DBG("%s: packet len is too small\n", ag->dev->name);
+ goto err_drop;
+ }
+
+ dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
+ DMA_TO_DEVICE);
+
+ ring->buf[i].skb = skb;
+ ring->buf[i].timestamp = jiffies;
+
+ /* setup descriptor fields */
+ desc->data = (u32) dma_addr;
+ desc->ctrl = (skb->len & DESC_PKTLEN_M);
+
+ /* flush descriptor */
+ wmb();
+
+ ring->curr++;
+ if (ring->curr == (ring->dirty + ring->size)) {
+ DBG("%s: tx queue full\n", ag->dev->name);
+ netif_stop_queue(dev);
+ }
+
+ DBG("%s: packet injected into TX queue\n", ag->dev->name);
+
+ /* enable TX engine */
+ ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
+
+ return NETDEV_TX_OK;
+
+err_drop:
+ dev->stats.tx_dropped++;
+
+ dev_kfree_skb(skb);
+ return NETDEV_TX_OK;
+}
+
+static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
+{
+ struct ag71xx *ag = netdev_priv(dev);
+ int ret;
+
+ switch (cmd) {
+ case SIOCETHTOOL:
+ if (ag->phy_dev == NULL)
+ break;
+
+ spin_lock_irq(&ag->lock);
+ ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
+ spin_unlock_irq(&ag->lock);
+ return ret;
+
+ case SIOCSIFHWADDR:
+ if (copy_from_user
+ (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
+ return -EFAULT;
+ return 0;
+
+ case SIOCGIFHWADDR:
+ if (copy_to_user
+ (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
+ return -EFAULT;
+ return 0;
+
+ case SIOCGMIIPHY:
+ case SIOCGMIIREG:
+ case SIOCSMIIREG:
+ if (ag->phy_dev == NULL)
+ break;
+
+ return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
+
+ default:
+ break;
+ }
+
+ return -EOPNOTSUPP;
+}
+
+static void ag71xx_oom_timer_handler(unsigned long data)
+{
+ struct net_device *dev = (struct net_device *) data;
+ struct ag71xx *ag = netdev_priv(dev);
+
+ napi_schedule(&ag->napi);
+}
+
+static void ag71xx_tx_timeout(struct net_device *dev)
+{
+ struct ag71xx *ag = netdev_priv(dev);
+
+ if (netif_msg_tx_err(ag))
+ pr_info("%s: tx timeout\n", ag->dev->name);
+
+ schedule_work(&ag->restart_work);
+}
+
+static void ag71xx_restart_work_func(struct work_struct *work)
+{
+ struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
+
+ if (ag71xx_get_pdata(ag)->is_ar724x) {
+ ag->link = 0;
+ ag71xx_link_adjust(ag);
+ return;
+ }
+
+ ag71xx_stop(ag->dev);
+ ag71xx_open(ag->dev);
+}
+
+static bool ag71xx_check_dma_stuck(struct ag71xx *ag, unsigned long timestamp)
+{
+ u32 rx_sm, tx_sm, rx_fd;
+
+ if (likely(time_before(jiffies, timestamp + HZ/10)))
+ return false;
+
+ if (!netif_carrier_ok(ag->dev))
+ return false;
+
+ rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
+ if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
+ return true;
+
+ tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
+ rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
+ if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
+ ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
+ return true;
+
+ return false;
+}
+
+static int ag71xx_tx_packets(struct ag71xx *ag)
+{
+ struct ag71xx_ring *ring = &ag->tx_ring;
+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
+ int sent;
+
+ DBG("%s: processing TX ring\n", ag->dev->name);
+
+ sent = 0;
+ while (ring->dirty != ring->curr) {
+ unsigned int i = ring->dirty % ring->size;
+ struct ag71xx_desc *desc = ring->buf[i].desc;
+ struct sk_buff *skb = ring->buf[i].skb;
+
+ if (!ag71xx_desc_empty(desc)) {
+ if (pdata->is_ar7240 &&
+ ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp))
+ schedule_work(&ag->restart_work);
+ break;
+ }
+
+ ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
+
+ ag->dev->stats.tx_bytes += skb->len;
+ ag->dev->stats.tx_packets++;
+
+ dev_kfree_skb_any(skb);
+ ring->buf[i].skb = NULL;
+
+ ring->dirty++;
+ sent++;
+ }
+
+ DBG("%s: %d packets sent out\n", ag->dev->name, sent);
+
+ if ((ring->curr - ring->dirty) < (ring->size * 3) / 4)
+ netif_wake_queue(ag->dev);
+
+ return sent;
+}
+
+static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
+{
+ struct net_device *dev = ag->dev;
+ struct ag71xx_ring *ring = &ag->rx_ring;
+ int done = 0;
+
+ DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
+ dev->name, limit, ring->curr, ring->dirty);
+
+ while (done < limit) {
+ unsigned int i = ring->curr % ring->size;
+ struct ag71xx_desc *desc = ring->buf[i].desc;
+ struct sk_buff *skb;
+ int pktlen;
+ int err = 0;
+
+ if (ag71xx_desc_empty(desc))
+ break;
+
+ if ((ring->dirty + ring->size) == ring->curr) {
+ ag71xx_assert(0);
+ break;
+ }
+
+ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
+
+ skb = ring->buf[i].skb;
+ pktlen = ag71xx_desc_pktlen(desc);
+ pktlen -= ETH_FCS_LEN;
+
+ dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
+ AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
+
+ dev->last_rx = jiffies;
+ dev->stats.rx_packets++;
+ dev->stats.rx_bytes += pktlen;
+
+ skb_put(skb, pktlen);
+ if (ag71xx_has_ar8216(ag))
+ err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
+
+ if (err) {
+ dev->stats.rx_dropped++;
+ kfree_skb(skb);
+ } else {
+ skb->dev = dev;
+ skb->ip_summed = CHECKSUM_NONE;
+ if (ag->phy_dev) {
+ ag->phy_dev->netif_receive_skb(skb);
+ } else {
+ skb->protocol = eth_type_trans(skb, dev);
+ netif_receive_skb(skb);
+ }
+ }
+
+ ring->buf[i].skb = NULL;
+ done++;
+
+ ring->curr++;
+ }
+
+ ag71xx_ring_rx_refill(ag);
+
+ DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
+ dev->name, ring->curr, ring->dirty, done);
+
+ return done;
+}
+
+static int ag71xx_poll(struct napi_struct *napi, int limit)
+{
+ struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
+ struct net_device *dev = ag->dev;
+ struct ag71xx_ring *rx_ring;
+ unsigned long flags;
+ u32 status;
+ int tx_done;
+ int rx_done;
+
+ pdata->ddr_flush();
+ tx_done = ag71xx_tx_packets(ag);
+
+ DBG("%s: processing RX ring\n", dev->name);
+ rx_done = ag71xx_rx_packets(ag, limit);
+
+ ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
+
+ rx_ring = &ag->rx_ring;
+ if (rx_ring->buf[rx_ring->dirty % rx_ring->size].skb == NULL)
+ goto oom;
+
+ status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
+ if (unlikely(status & RX_STATUS_OF)) {
+ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
+ dev->stats.rx_fifo_errors++;
+
+ /* restart RX */
+ ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
+ }
+
+ if (rx_done < limit) {
+ if (status & RX_STATUS_PR)
+ goto more;
+
+ status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
+ if (status & TX_STATUS_PS)
+ goto more;
+
+ DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
+ dev->name, rx_done, tx_done, limit);
+
+ napi_complete(napi);
+
+ /* enable interrupts */
+ spin_lock_irqsave(&ag->lock, flags);
+ ag71xx_int_enable(ag, AG71XX_INT_POLL);
+ spin_unlock_irqrestore(&ag->lock, flags);
+ return rx_done;
+ }
+
+more:
+ DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
+ dev->name, rx_done, tx_done, limit);
+ return rx_done;
+
+oom:
+ if (netif_msg_rx_err(ag))
+ pr_info("%s: out of memory\n", dev->name);
+
+ mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
+ napi_complete(napi);
+ return 0;
+}
+
+static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
+{
+ struct net_device *dev = dev_id;
+ struct ag71xx *ag = netdev_priv(dev);
+ u32 status;
+
+ status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
+ ag71xx_dump_intr(ag, "raw", status);
+
+ if (unlikely(!status))
+ return IRQ_NONE;
+
+ if (unlikely(status & AG71XX_INT_ERR)) {
+ if (status & AG71XX_INT_TX_BE) {
+ ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
+ dev_err(&dev->dev, "TX BUS error\n");
+ }
+ if (status & AG71XX_INT_RX_BE) {
+ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
+ dev_err(&dev->dev, "RX BUS error\n");
+ }
+ }
+
+ if (likely(status & AG71XX_INT_POLL)) {
+ ag71xx_int_disable(ag, AG71XX_INT_POLL);
+ DBG("%s: enable polling mode\n", dev->name);
+ napi_schedule(&ag->napi);
+ }
+
+ ag71xx_debugfs_update_int_stats(ag, status);
+
+ return IRQ_HANDLED;
+}
+
+#ifdef CONFIG_NET_POLL_CONTROLLER
+/*
+ * Polling 'interrupt' - used by things like netconsole to send skbs
+ * without having to re-enable interrupts. It's not called while
+ * the interrupt routine is executing.
+ */
+static void ag71xx_netpoll(struct net_device *dev)
+{
+ disable_irq(dev->irq);
+ ag71xx_interrupt(dev->irq, dev);
+ enable_irq(dev->irq);
+}
+#endif
+
+static const struct net_device_ops ag71xx_netdev_ops = {
+ .ndo_open = ag71xx_open,
+ .ndo_stop = ag71xx_stop,
+ .ndo_start_xmit = ag71xx_hard_start_xmit,
+ .ndo_do_ioctl = ag71xx_do_ioctl,
+ .ndo_tx_timeout = ag71xx_tx_timeout,
+ .ndo_change_mtu = eth_change_mtu,
+ .ndo_set_mac_address = eth_mac_addr,
+ .ndo_validate_addr = eth_validate_addr,
+#ifdef CONFIG_NET_POLL_CONTROLLER
+ .ndo_poll_controller = ag71xx_netpoll,
+#endif
+};
+
+static int __devinit ag71xx_probe(struct platform_device *pdev)
+{
+ struct net_device *dev;
+ struct resource *res;
+ struct ag71xx *ag;
+ struct ag71xx_platform_data *pdata;
+ int err;
+
+ pdata = pdev->dev.platform_data;
+ if (!pdata) {
+ dev_err(&pdev->dev, "no platform data specified\n");
+ err = -ENXIO;
+ goto err_out;
+ }
+
+ if (pdata->mii_bus_dev == NULL) {
+ dev_err(&pdev->dev, "no MII bus device specified\n");
+ err = -EINVAL;
+ goto err_out;
+ }
+
+ dev = alloc_etherdev(sizeof(*ag));
+ if (!dev) {
+ dev_err(&pdev->dev, "alloc_etherdev failed\n");
+ err = -ENOMEM;
+ goto err_out;
+ }
+
+ SET_NETDEV_DEV(dev, &pdev->dev);
+
+ ag = netdev_priv(dev);
+ ag->pdev = pdev;
+ ag->dev = dev;
+ ag->msg_enable = netif_msg_init(ag71xx_msg_level,
+ AG71XX_DEFAULT_MSG_ENABLE);
+ spin_lock_init(&ag->lock);
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
+ if (!res) {
+ dev_err(&pdev->dev, "no mac_base resource found\n");
+ err = -ENXIO;
+ goto err_out;
+ }
+
+ ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
+ if (!ag->mac_base) {
+ dev_err(&pdev->dev, "unable to ioremap mac_base\n");
+ err = -ENOMEM;
+ goto err_free_dev;
+ }
+
+ dev->irq = platform_get_irq(pdev, 0);
+ err = request_irq(dev->irq, ag71xx_interrupt,
+ IRQF_DISABLED,
+ dev->name, dev);
+ if (err) {
+ dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
+ goto err_unmap_base;
+ }
+
+ dev->base_addr = (unsigned long)ag->mac_base;
+ dev->netdev_ops = &ag71xx_netdev_ops;
+ dev->ethtool_ops = &ag71xx_ethtool_ops;
+
+ INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
+
+ init_timer(&ag->oom_timer);
+ ag->oom_timer.data = (unsigned long) dev;
+ ag->oom_timer.function = ag71xx_oom_timer_handler;
+
+ ag->tx_ring.size = AG71XX_TX_RING_SIZE_DEFAULT;
+ ag->rx_ring.size = AG71XX_RX_RING_SIZE_DEFAULT;
+
+ ag->stop_desc = dma_alloc_coherent(NULL,
+ sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL);
+
+ if (!ag->stop_desc)
+ goto err_free_irq;
+
+ ag->stop_desc->data = 0;
+ ag->stop_desc->ctrl = 0;
+ ag->stop_desc->next = (u32) ag->stop_desc_dma;
+
+ memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
+
+ netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
+
+ err = register_netdev(dev);
+ if (err) {
+ dev_err(&pdev->dev, "unable to register net device\n");
+ goto err_free_desc;
+ }
+
+ pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d\n",
+ dev->name, dev->base_addr, dev->irq);
+
+ ag71xx_dump_regs(ag);
+
+ ag71xx_hw_init(ag);
+
+ ag71xx_dump_regs(ag);
+
+ err = ag71xx_phy_connect(ag);
+ if (err)
+ goto err_unregister_netdev;
+
+ err = ag71xx_debugfs_init(ag);
+ if (err)
+ goto err_phy_disconnect;
+
+ platform_set_drvdata(pdev, dev);
+
+ return 0;
+
+err_phy_disconnect:
+ ag71xx_phy_disconnect(ag);
+err_unregister_netdev:
+ unregister_netdev(dev);
+err_free_desc:
+ dma_free_coherent(NULL, sizeof(struct ag71xx_desc), ag->stop_desc,
+ ag->stop_desc_dma);
+err_free_irq:
+ free_irq(dev->irq, dev);
+err_unmap_base:
+ iounmap(ag->mac_base);
+err_free_dev:
+ kfree(dev);
+err_out:
+ platform_set_drvdata(pdev, NULL);
+ return err;
+}
+
+static int __devexit ag71xx_remove(struct platform_device *pdev)
+{
+ struct net_device *dev = platform_get_drvdata(pdev);
+
+ if (dev) {
+ struct ag71xx *ag = netdev_priv(dev);
+
+ ag71xx_debugfs_exit(ag);
+ ag71xx_phy_disconnect(ag);
+ unregister_netdev(dev);
+ free_irq(dev->irq, dev);
+ iounmap(ag->mac_base);
+ kfree(dev);
+ platform_set_drvdata(pdev, NULL);
+ }
+
+ return 0;
+}
+
+static struct platform_driver ag71xx_driver = {
+ .probe = ag71xx_probe,
+ .remove = __exit_p(ag71xx_remove),
+ .driver = {
+ .name = AG71XX_DRV_NAME,
+ }
+};
+
+static int __init ag71xx_module_init(void)
+{
+ int ret;
+
+ ret = ag71xx_debugfs_root_init();
+ if (ret)
+ goto err_out;
+
+ ret = ag71xx_mdio_driver_init();
+ if (ret)
+ goto err_debugfs_exit;
+
+ ret = platform_driver_register(&ag71xx_driver);
+ if (ret)
+ goto err_mdio_exit;
+
+ return 0;
+
+err_mdio_exit:
+ ag71xx_mdio_driver_exit();
+err_debugfs_exit:
+ ag71xx_debugfs_root_exit();
+err_out:
+ return ret;
+}
+
+static void __exit ag71xx_module_exit(void)
+{
+ platform_driver_unregister(&ag71xx_driver);
+ ag71xx_mdio_driver_exit();
+ ag71xx_debugfs_root_exit();
+}
+
+module_init(ag71xx_module_init);
+module_exit(ag71xx_module_exit);
+
+MODULE_VERSION(AG71XX_DRV_VERSION);
+MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
+MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
--- /dev/null
+/*
+ * Atheros AR71xx built-in ethernet mac driver
+ *
+ * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * Based on Atheros' AG7100 driver
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include "ag71xx.h"
+
+#define AG71XX_MDIO_RETRY 1000
+#define AG71XX_MDIO_DELAY 5
+
+static inline void ag71xx_mdio_wr(struct ag71xx_mdio *am, unsigned reg,
+ u32 value)
+{
+ void __iomem *r;
+
+ r = am->mdio_base + reg;
+ __raw_writel(value, r);
+
+ /* flush write */
+ (void) __raw_readl(r);
+}
+
+static inline u32 ag71xx_mdio_rr(struct ag71xx_mdio *am, unsigned reg)
+{
+ return __raw_readl(am->mdio_base + reg);
+}
+
+static void ag71xx_mdio_dump_regs(struct ag71xx_mdio *am)
+{
+ DBG("%s: mii_cfg=%08x, mii_cmd=%08x, mii_addr=%08x\n",
+ am->mii_bus->name,
+ ag71xx_mdio_rr(am, AG71XX_REG_MII_CFG),
+ ag71xx_mdio_rr(am, AG71XX_REG_MII_CMD),
+ ag71xx_mdio_rr(am, AG71XX_REG_MII_ADDR));
+ DBG("%s: mii_ctrl=%08x, mii_status=%08x, mii_ind=%08x\n",
+ am->mii_bus->name,
+ ag71xx_mdio_rr(am, AG71XX_REG_MII_CTRL),
+ ag71xx_mdio_rr(am, AG71XX_REG_MII_STATUS),
+ ag71xx_mdio_rr(am, AG71XX_REG_MII_IND));
+}
+
+int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg)
+{
+ int ret;
+ int i;
+
+ ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_WRITE);
+ ag71xx_mdio_wr(am, AG71XX_REG_MII_ADDR,
+ ((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff));
+ ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_READ);
+
+ i = AG71XX_MDIO_RETRY;
+ while (ag71xx_mdio_rr(am, AG71XX_REG_MII_IND) & MII_IND_BUSY) {
+ if (i-- == 0) {
+ pr_err("%s: mii_read timed out\n", am->mii_bus->name);
+ ret = 0xffff;
+ goto out;
+ }
+ udelay(AG71XX_MDIO_DELAY);
+ }
+
+ ret = ag71xx_mdio_rr(am, AG71XX_REG_MII_STATUS) & 0xffff;
+ ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_WRITE);
+
+ DBG("mii_read: addr=%04x, reg=%04x, value=%04x\n", addr, reg, ret);
+
+out:
+ return ret;
+}
+
+void ag71xx_mdio_mii_write(struct ag71xx_mdio *am, int addr, int reg, u16 val)
+{
+ int i;
+
+ DBG("mii_write: addr=%04x, reg=%04x, value=%04x\n", addr, reg, val);
+
+ ag71xx_mdio_wr(am, AG71XX_REG_MII_ADDR,
+ ((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff));
+ ag71xx_mdio_wr(am, AG71XX_REG_MII_CTRL, val);
+
+ i = AG71XX_MDIO_RETRY;
+ while (ag71xx_mdio_rr(am, AG71XX_REG_MII_IND) & MII_IND_BUSY) {
+ if (i-- == 0) {
+ pr_err("%s: mii_write timed out\n", am->mii_bus->name);
+ break;
+ }
+ udelay(AG71XX_MDIO_DELAY);
+ }
+}
+
+static int ag71xx_mdio_reset(struct mii_bus *bus)
+{
+ struct ag71xx_mdio *am = bus->priv;
+ u32 t;
+
+ if (am->pdata->is_ar7240)
+ t = MII_CFG_CLK_DIV_6;
+ else
+ t = MII_CFG_CLK_DIV_28;
+
+ ag71xx_mdio_wr(am, AG71XX_REG_MII_CFG, t | MII_CFG_RESET);
+ udelay(100);
+
+ ag71xx_mdio_wr(am, AG71XX_REG_MII_CFG, t);
+ udelay(100);
+
+ return 0;
+}
+
+static int ag71xx_mdio_read(struct mii_bus *bus, int addr, int reg)
+{
+ struct ag71xx_mdio *am = bus->priv;
+
+ if (am->pdata->is_ar7240)
+ return ar7240sw_phy_read(bus, addr, reg);
+ else
+ return ag71xx_mdio_mii_read(am, addr, reg);
+}
+
+static int ag71xx_mdio_write(struct mii_bus *bus, int addr, int reg, u16 val)
+{
+ struct ag71xx_mdio *am = bus->priv;
+
+ if (am->pdata->is_ar7240)
+ ar7240sw_phy_write(bus, addr, reg, val);
+ else
+ ag71xx_mdio_mii_write(am, addr, reg, val);
+ return 0;
+}
+
+static int __devinit ag71xx_mdio_probe(struct platform_device *pdev)
+{
+ struct ag71xx_mdio_platform_data *pdata;
+ struct ag71xx_mdio *am;
+ struct resource *res;
+ int i;
+ int err;
+
+ pdata = pdev->dev.platform_data;
+ if (!pdata) {
+ dev_err(&pdev->dev, "no platform data specified\n");
+ return -EINVAL;
+ }
+
+ am = kzalloc(sizeof(*am), GFP_KERNEL);
+ if (!am) {
+ err = -ENOMEM;
+ goto err_out;
+ }
+
+ am->pdata = pdata;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(&pdev->dev, "no iomem resource found\n");
+ err = -ENXIO;
+ goto err_out;
+ }
+
+ am->mdio_base = ioremap_nocache(res->start, res->end - res->start + 1);
+ if (!am->mdio_base) {
+ dev_err(&pdev->dev, "unable to ioremap registers\n");
+ err = -ENOMEM;
+ goto err_free_mdio;
+ }
+
+ am->mii_bus = mdiobus_alloc();
+ if (am->mii_bus == NULL) {
+ err = -ENOMEM;
+ goto err_iounmap;
+ }
+
+ am->mii_bus->name = "ag71xx_mdio";
+ am->mii_bus->read = ag71xx_mdio_read;
+ am->mii_bus->write = ag71xx_mdio_write;
+ am->mii_bus->reset = ag71xx_mdio_reset;
+ am->mii_bus->irq = am->mii_irq;
+ am->mii_bus->priv = am;
+ am->mii_bus->parent = &pdev->dev;
+ snprintf(am->mii_bus->id, MII_BUS_ID_SIZE, "%s", dev_name(&pdev->dev));
+ am->mii_bus->phy_mask = pdata->phy_mask;
+
+ for (i = 0; i < PHY_MAX_ADDR; i++)
+ am->mii_irq[i] = PHY_POLL;
+
+ ag71xx_mdio_wr(am, AG71XX_REG_MAC_CFG1, 0);
+
+ err = mdiobus_register(am->mii_bus);
+ if (err)
+ goto err_free_bus;
+
+ ag71xx_mdio_dump_regs(am);
+
+ platform_set_drvdata(pdev, am);
+ return 0;
+
+err_free_bus:
+ mdiobus_free(am->mii_bus);
+err_iounmap:
+ iounmap(am->mdio_base);
+err_free_mdio:
+ kfree(am);
+err_out:
+ return err;
+}
+
+static int __devexit ag71xx_mdio_remove(struct platform_device *pdev)
+{
+ struct ag71xx_mdio *am = platform_get_drvdata(pdev);
+
+ if (am) {
+ mdiobus_unregister(am->mii_bus);
+ mdiobus_free(am->mii_bus);
+ iounmap(am->mdio_base);
+ kfree(am);
+ platform_set_drvdata(pdev, NULL);
+ }
+
+ return 0;
+}
+
+static struct platform_driver ag71xx_mdio_driver = {
+ .probe = ag71xx_mdio_probe,
+ .remove = __exit_p(ag71xx_mdio_remove),
+ .driver = {
+ .name = "ag71xx-mdio",
+ }
+};
+
+int __init ag71xx_mdio_driver_init(void)
+{
+ return platform_driver_register(&ag71xx_mdio_driver);
+}
+
+void ag71xx_mdio_driver_exit(void)
+{
+ platform_driver_unregister(&ag71xx_mdio_driver);
+}
--- /dev/null
+/*
+ * Atheros AR71xx built-in ethernet mac driver
+ *
+ * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * Based on Atheros' AG7100 driver
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include "ag71xx.h"
+
+static void ag71xx_phy_link_adjust(struct net_device *dev)
+{
+ struct ag71xx *ag = netdev_priv(dev);
+ struct phy_device *phydev = ag->phy_dev;
+ unsigned long flags;
+ int status_change = 0;
+
+ spin_lock_irqsave(&ag->lock, flags);
+
+ if (phydev->link) {
+ if (ag->duplex != phydev->duplex
+ || ag->speed != phydev->speed) {
+ status_change = 1;
+ }
+ }
+
+ if (phydev->link != ag->link)
+ status_change = 1;
+
+ ag->link = phydev->link;
+ ag->duplex = phydev->duplex;
+ ag->speed = phydev->speed;
+
+ if (status_change)
+ ag71xx_link_adjust(ag);
+
+ spin_unlock_irqrestore(&ag->lock, flags);
+}
+
+void ag71xx_phy_start(struct ag71xx *ag)
+{
+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
+
+ if (ag->phy_dev) {
+ phy_start(ag->phy_dev);
+ } else if (pdata->switch_data) {
+ ag71xx_ar7240_start(ag);
+ } else {
+ ag->link = 1;
+ ag71xx_link_adjust(ag);
+ }
+}
+
+void ag71xx_phy_stop(struct ag71xx *ag)
+{
+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
+ unsigned long flags;
+
+ if (ag->phy_dev)
+ phy_stop(ag->phy_dev);
+ else if (pdata->switch_data)
+ ag71xx_ar7240_stop(ag);
+
+ spin_lock_irqsave(&ag->lock, flags);
+ if (ag->link) {
+ ag->link = 0;
+ ag71xx_link_adjust(ag);
+ }
+ spin_unlock_irqrestore(&ag->lock, flags);
+}
+
+static int ag71xx_phy_connect_fixed(struct ag71xx *ag)
+{
+ struct net_device *dev = ag->dev;
+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
+ int ret = 0;
+
+ /* use fixed settings */
+ switch (pdata->speed) {
+ case SPEED_10:
+ case SPEED_100:
+ case SPEED_1000:
+ break;
+ default:
+ netdev_err(dev, "invalid speed specified\n");
+ ret = -EINVAL;
+ break;
+ }
+
+ netdev_dbg(dev, "using fixed link parameters\n");
+
+ ag->duplex = pdata->duplex;
+ ag->speed = pdata->speed;
+
+ return ret;
+}
+
+static int ag71xx_phy_connect_multi(struct ag71xx *ag)
+{
+ struct net_device *dev = ag->dev;
+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
+ struct phy_device *phydev = NULL;
+ int phy_addr;
+ int ret = 0;
+
+ for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
+ if (!(pdata->phy_mask & (1 << phy_addr)))
+ continue;
+
+ if (ag->mii_bus->phy_map[phy_addr] == NULL)
+ continue;
+
+ DBG("%s: PHY found at %s, uid=%08x\n",
+ dev->name,
+ dev_name(&ag->mii_bus->phy_map[phy_addr]->dev),
+ ag->mii_bus->phy_map[phy_addr]->phy_id);
+
+ if (phydev == NULL)
+ phydev = ag->mii_bus->phy_map[phy_addr];
+ }
+
+ if (!phydev) {
+ netdev_err(dev, "no PHY found with phy_mask=%08x\n",
+ pdata->phy_mask);
+ return -ENODEV;
+ }
+
+ ag->phy_dev = phy_connect(dev, dev_name(&phydev->dev),
+ &ag71xx_phy_link_adjust, 0,
+ pdata->phy_if_mode);
+
+ if (IS_ERR(ag->phy_dev)) {
+ netdev_err(dev, "could not connect to PHY at %s\n",
+ dev_name(&phydev->dev));
+ return PTR_ERR(ag->phy_dev);
+ }
+
+ /* mask with MAC supported features */
+ if (pdata->has_gbit)
+ phydev->supported &= PHY_GBIT_FEATURES;
+ else
+ phydev->supported &= PHY_BASIC_FEATURES;
+
+ phydev->advertising = phydev->supported;
+
+ netdev_info(dev, "connected to PHY at %s [uid=%08x, driver=%s]\n",
+ dev_name(&phydev->dev), phydev->phy_id, phydev->drv->name);
+
+ ag->link = 0;
+ ag->speed = 0;
+ ag->duplex = -1;
+
+ return ret;
+}
+
+static int dev_is_class(struct device *dev, void *class)
+{
+ if (dev->class != NULL && !strcmp(dev->class->name, class))
+ return 1;
+
+ return 0;
+}
+
+static struct device *dev_find_class(struct device *parent, char *class)
+{
+ if (dev_is_class(parent, class)) {
+ get_device(parent);
+ return parent;
+ }
+
+ return device_find_child(parent, class, dev_is_class);
+}
+
+static struct mii_bus *dev_to_mii_bus(struct device *dev)
+{
+ struct device *d;
+
+ d = dev_find_class(dev, "mdio_bus");
+ if (d != NULL) {
+ struct mii_bus *bus;
+
+ bus = to_mii_bus(d);
+ put_device(d);
+
+ return bus;
+ }
+
+ return NULL;
+}
+
+int __devinit ag71xx_phy_connect(struct ag71xx *ag)
+{
+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
+
+ if (pdata->mii_bus_dev == NULL ||
+ pdata->mii_bus_dev->bus == NULL )
+ return ag71xx_phy_connect_fixed(ag);
+
+ ag->mii_bus = dev_to_mii_bus(pdata->mii_bus_dev);
+ if (ag->mii_bus == NULL) {
+ netdev_err(ag->dev, "unable to find MII bus on device '%s'\n",
+ dev_name(pdata->mii_bus_dev));
+ return -ENODEV;
+ }
+
+ /* Reset the mdio bus explicitly */
+ if (ag->mii_bus->reset) {
+ mutex_lock(&ag->mii_bus->mdio_lock);
+ ag->mii_bus->reset(ag->mii_bus);
+ mutex_unlock(&ag->mii_bus->mdio_lock);
+ }
+
+ if (pdata->switch_data)
+ return ag71xx_ar7240_init(ag);
+
+ if (pdata->phy_mask)
+ return ag71xx_phy_connect_multi(ag);
+
+ return ag71xx_phy_connect_fixed(ag);
+}
+
+void ag71xx_phy_disconnect(struct ag71xx *ag)
+{
+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
+
+ if (pdata->switch_data)
+ ag71xx_ar7240_cleanup(ag);
+ else if (ag->phy_dev)
+ phy_disconnect(ag->phy_dev);
+}
--- /dev/null
+From 781c5ae32a2e8aede2e1756dfbea1abb3cf09ffc Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 5 Jun 2011 23:38:44 +0200
+Subject: [PATCH 01/27] MIPS: ath79: Change number of available IRQs
+
+The status register of the miscellaneous interrupt controller is 32 bits
+wide, but the actual value of NR_IRQS covers only 8 of them. Change
+NR_IRQS in order to make all of those interrupt lines usable.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Patchwork: https://patchwork.linux-mips.org/patch/2441/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/include/asm/mach-ath79/irq.h | 4 ++--
+ 1 files changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/include/asm/mach-ath79/irq.h
++++ b/arch/mips/include/asm/mach-ath79/irq.h
+@@ -10,10 +10,10 @@
+ #define __ASM_MACH_ATH79_IRQ_H
+
+ #define MIPS_CPU_IRQ_BASE 0
+-#define NR_IRQS 16
++#define NR_IRQS 40
+
+ #define ATH79_MISC_IRQ_BASE 8
+-#define ATH79_MISC_IRQ_COUNT 8
++#define ATH79_MISC_IRQ_COUNT 32
+
+ #define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2)
+ #define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3)
--- /dev/null
+From 9951cfc88b5d818391bebc7a56b678942b89721e Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 5 Jun 2011 23:38:45 +0200
+Subject: [PATCH 02/27] MIPS: ath79: Handle more MISC IRQs
+
+The AR724X SoCs have more IRQ sources hooked into the MISC IRQ controller.
+The patch adds support for them.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Patchwork: https://patchwork.linux-mips.org/patch/2440/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/ath79/irq.c | 12 ++++++++++++
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 4 ++++
+ arch/mips/include/asm/mach-ath79/irq.h | 4 ++++
+ 3 files changed, 20 insertions(+), 0 deletions(-)
+
+--- a/arch/mips/ath79/irq.c
++++ b/arch/mips/ath79/irq.c
+@@ -46,6 +46,15 @@ static void ath79_misc_irq_handler(unsig
+ else if (pending & MISC_INT_TIMER)
+ generic_handle_irq(ATH79_MISC_IRQ_TIMER);
+
++ else if (pending & MISC_INT_TIMER2)
++ generic_handle_irq(ATH79_MISC_IRQ_TIMER2);
++
++ else if (pending & MISC_INT_TIMER3)
++ generic_handle_irq(ATH79_MISC_IRQ_TIMER3);
++
++ else if (pending & MISC_INT_TIMER4)
++ generic_handle_irq(ATH79_MISC_IRQ_TIMER4);
++
+ else if (pending & MISC_INT_OHCI)
+ generic_handle_irq(ATH79_MISC_IRQ_OHCI);
+
+@@ -58,6 +67,9 @@ static void ath79_misc_irq_handler(unsig
+ else if (pending & MISC_INT_WDOG)
+ generic_handle_irq(ATH79_MISC_IRQ_WDOG);
+
++ else if (pending & MISC_INT_ETHSW)
++ generic_handle_irq(ATH79_MISC_IRQ_ETHSW);
++
+ else
+ spurious_interrupt();
+ }
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -130,6 +130,10 @@
+
+ #define AR724X_RESET_REG_RESET_MODULE 0x1c
+
++#define MISC_INT_ETHSW BIT(12)
++#define MISC_INT_TIMER4 BIT(10)
++#define MISC_INT_TIMER3 BIT(9)
++#define MISC_INT_TIMER2 BIT(8)
+ #define MISC_INT_DMA BIT(7)
+ #define MISC_INT_OHCI BIT(6)
+ #define MISC_INT_PERFC BIT(5)
+--- a/arch/mips/include/asm/mach-ath79/irq.h
++++ b/arch/mips/include/asm/mach-ath79/irq.h
+@@ -30,6 +30,10 @@
+ #define ATH79_MISC_IRQ_PERFC (ATH79_MISC_IRQ_BASE + 5)
+ #define ATH79_MISC_IRQ_OHCI (ATH79_MISC_IRQ_BASE + 6)
+ #define ATH79_MISC_IRQ_DMA (ATH79_MISC_IRQ_BASE + 7)
++#define ATH79_MISC_IRQ_TIMER2 (ATH79_MISC_IRQ_BASE + 8)
++#define ATH79_MISC_IRQ_TIMER3 (ATH79_MISC_IRQ_BASE + 9)
++#define ATH79_MISC_IRQ_TIMER4 (ATH79_MISC_IRQ_BASE + 10)
++#define ATH79_MISC_IRQ_ETHSW (ATH79_MISC_IRQ_BASE + 12)
+
+ #include_next <irq.h>
+
--- /dev/null
+From cb888b2552199ace429731b772d5257c598d53df Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 5 Jun 2011 23:38:46 +0200
+Subject: [PATCH 03/27] MIPS: ath79: add common USB Host Controller device
+
+Add common platform_device and helper code to make the registration of
+the built-in USB controllers easier on the board which are using them.
+Also register the USB controller on the AP81 and PB44 boards.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Patchwork: https://patchwork.linux-mips.org/patch/2442/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/ath79/Kconfig | 5 +
+ arch/mips/ath79/Makefile | 1 +
+ arch/mips/ath79/dev-usb.c | 178 ++++++++++++++++++++++++
+ arch/mips/ath79/dev-usb.h | 17 +++
+ arch/mips/ath79/mach-ap81.c | 2 +
+ arch/mips/ath79/mach-pb44.c | 2 +
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 32 ++++-
+ 7 files changed, 236 insertions(+), 1 deletions(-)
+ create mode 100644 arch/mips/ath79/dev-usb.c
+ create mode 100644 arch/mips/ath79/dev-usb.h
+
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -9,6 +9,7 @@ config ATH79_MACH_AP81
+ select ATH79_DEV_GPIO_BUTTONS
+ select ATH79_DEV_LEDS_GPIO
+ select ATH79_DEV_SPI
++ select ATH79_DEV_USB
+ help
+ Say 'Y' here if you want your kernel to support the
+ Atheros AP81 reference board.
+@@ -19,6 +20,7 @@ config ATH79_MACH_PB44
+ select ATH79_DEV_GPIO_BUTTONS
+ select ATH79_DEV_LEDS_GPIO
+ select ATH79_DEV_SPI
++ select ATH79_DEV_USB
+ help
+ Say 'Y' here if you want your kernel to support the
+ Atheros PB44 reference board.
+@@ -52,4 +54,7 @@ config ATH79_DEV_LEDS_GPIO
+ config ATH79_DEV_SPI
+ def_bool n
+
++config ATH79_DEV_USB
++ def_bool n
++
+ endif
+--- a/arch/mips/ath79/Makefile
++++ b/arch/mips/ath79/Makefile
+@@ -20,6 +20,7 @@ obj-$(CONFIG_ATH79_DEV_AR913X_WMAC) += d
+ obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o
+ obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o
+ obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o
++obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o
+
+ #
+ # Machines
+--- /dev/null
++++ b/arch/mips/ath79/dev-usb.c
+@@ -0,0 +1,178 @@
++/*
++ * Atheros AR7XXX/AR9XXX USB Host Controller device
++ *
++ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ *
++ * Parts of this file are based on Atheros' 2.6.15 BSP
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/irq.h>
++#include <linux/dma-mapping.h>
++#include <linux/platform_device.h>
++
++#include <asm/mach-ath79/ath79.h>
++#include <asm/mach-ath79/ar71xx_regs.h>
++#include "common.h"
++#include "dev-usb.h"
++
++static struct resource ath79_ohci_resources[] = {
++ [0] = {
++ /* .start and .end fields are filled dynamically */
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = ATH79_MISC_IRQ_OHCI,
++ .end = ATH79_MISC_IRQ_OHCI,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static u64 ath79_ohci_dmamask = DMA_BIT_MASK(32);
++static struct platform_device ath79_ohci_device = {
++ .name = "ath79-ohci",
++ .id = -1,
++ .resource = ath79_ohci_resources,
++ .num_resources = ARRAY_SIZE(ath79_ohci_resources),
++ .dev = {
++ .dma_mask = &ath79_ohci_dmamask,
++ .coherent_dma_mask = DMA_BIT_MASK(32),
++ },
++};
++
++static struct resource ath79_ehci_resources[] = {
++ [0] = {
++ /* .start and .end fields are filled dynamically */
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = ATH79_CPU_IRQ_USB,
++ .end = ATH79_CPU_IRQ_USB,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static u64 ath79_ehci_dmamask = DMA_BIT_MASK(32);
++static struct platform_device ath79_ehci_device = {
++ .name = "ath79-ehci",
++ .id = -1,
++ .resource = ath79_ehci_resources,
++ .num_resources = ARRAY_SIZE(ath79_ehci_resources),
++ .dev = {
++ .dma_mask = &ath79_ehci_dmamask,
++ .coherent_dma_mask = DMA_BIT_MASK(32),
++ },
++};
++
++#define AR71XX_USB_RESET_MASK (AR71XX_RESET_USB_HOST | \
++ AR71XX_RESET_USB_PHY | \
++ AR71XX_RESET_USB_OHCI_DLL)
++
++static void __init ath79_usb_setup(void)
++{
++ void __iomem *usb_ctrl_base;
++
++ ath79_device_reset_set(AR71XX_USB_RESET_MASK);
++ mdelay(1000);
++ ath79_device_reset_clear(AR71XX_USB_RESET_MASK);
++
++ usb_ctrl_base = ioremap(AR71XX_USB_CTRL_BASE, AR71XX_USB_CTRL_SIZE);
++
++ /* Turning on the Buff and Desc swap bits */
++ __raw_writel(0xf0000, usb_ctrl_base + AR71XX_USB_CTRL_REG_CONFIG);
++
++ /* WAR for HW bug. Here it adjusts the duration between two SOFS */
++ __raw_writel(0x20c00, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ);
++
++ iounmap(usb_ctrl_base);
++
++ mdelay(900);
++
++ ath79_ohci_resources[0].start = AR71XX_OHCI_BASE;
++ ath79_ohci_resources[0].end = AR71XX_OHCI_BASE + AR71XX_OHCI_SIZE - 1;
++ platform_device_register(&ath79_ohci_device);
++
++ ath79_ehci_resources[0].start = AR71XX_EHCI_BASE;
++ ath79_ehci_resources[0].end = AR71XX_EHCI_BASE + AR71XX_EHCI_SIZE - 1;
++ ath79_ehci_device.name = "ar71xx-ehci";
++ platform_device_register(&ath79_ehci_device);
++}
++
++static void __init ar7240_usb_setup(void)
++{
++ void __iomem *usb_ctrl_base;
++
++ ath79_device_reset_clear(AR7240_RESET_OHCI_DLL);
++ ath79_device_reset_set(AR7240_RESET_USB_HOST);
++
++ mdelay(1000);
++
++ ath79_device_reset_set(AR7240_RESET_OHCI_DLL);
++ ath79_device_reset_clear(AR7240_RESET_USB_HOST);
++
++ usb_ctrl_base = ioremap(AR7240_USB_CTRL_BASE, AR7240_USB_CTRL_SIZE);
++
++ /* WAR for HW bug. Here it adjusts the duration between two SOFS */
++ __raw_writel(0x3, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ);
++
++ iounmap(usb_ctrl_base);
++
++ ath79_ohci_resources[0].start = AR7240_OHCI_BASE;
++ ath79_ohci_resources[0].end = AR7240_OHCI_BASE + AR7240_OHCI_SIZE - 1;
++ platform_device_register(&ath79_ohci_device);
++}
++
++static void __init ar724x_usb_setup(void)
++{
++ ath79_device_reset_set(AR724X_RESET_USBSUS_OVERRIDE);
++ mdelay(10);
++
++ ath79_device_reset_clear(AR724X_RESET_USB_HOST);
++ mdelay(10);
++
++ ath79_device_reset_clear(AR724X_RESET_USB_PHY);
++ mdelay(10);
++
++ ath79_ehci_resources[0].start = AR724X_EHCI_BASE;
++ ath79_ehci_resources[0].end = AR724X_EHCI_BASE + AR724X_EHCI_SIZE - 1;
++ ath79_ehci_device.name = "ar724x-ehci";
++ platform_device_register(&ath79_ehci_device);
++}
++
++static void __init ar913x_usb_setup(void)
++{
++ ath79_device_reset_set(AR913X_RESET_USBSUS_OVERRIDE);
++ mdelay(10);
++
++ ath79_device_reset_clear(AR913X_RESET_USB_HOST);
++ mdelay(10);
++
++ ath79_device_reset_clear(AR913X_RESET_USB_PHY);
++ mdelay(10);
++
++ ath79_ehci_resources[0].start = AR913X_EHCI_BASE;
++ ath79_ehci_resources[0].end = AR913X_EHCI_BASE + AR913X_EHCI_SIZE - 1;
++ ath79_ehci_device.name = "ar913x-ehci";
++ platform_device_register(&ath79_ehci_device);
++}
++
++void __init ath79_register_usb(void)
++{
++ if (soc_is_ar71xx())
++ ath79_usb_setup();
++ else if (soc_is_ar7240())
++ ar7240_usb_setup();
++ else if (soc_is_ar7241() || soc_is_ar7242())
++ ar724x_usb_setup();
++ else if (soc_is_ar913x())
++ ar913x_usb_setup();
++ else
++ BUG();
++}
+--- /dev/null
++++ b/arch/mips/ath79/dev-usb.h
+@@ -0,0 +1,17 @@
++/*
++ * Atheros AR71XX/AR724X/AR913X USB Host Controller support
++ *
++ * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
++
++#ifndef _ATH79_DEV_USB_H
++#define _ATH79_DEV_USB_H
++
++void ath79_register_usb(void);
++
++#endif /* _ATH79_DEV_USB_H */
+--- a/arch/mips/ath79/mach-ap81.c
++++ b/arch/mips/ath79/mach-ap81.c
+@@ -14,6 +14,7 @@
+ #include "dev-gpio-buttons.h"
+ #include "dev-leds-gpio.h"
+ #include "dev-spi.h"
++#include "dev-usb.h"
+
+ #define AP81_GPIO_LED_STATUS 1
+ #define AP81_GPIO_LED_AOSS 3
+@@ -92,6 +93,7 @@ static void __init ap81_setup(void)
+ ath79_register_spi(&ap81_spi_data, ap81_spi_info,
+ ARRAY_SIZE(ap81_spi_info));
+ ath79_register_ar913x_wmac(cal_data);
++ ath79_register_usb();
+ }
+
+ MIPS_MACHINE(ATH79_MACH_AP81, "AP81", "Atheros AP81 reference board",
+--- a/arch/mips/ath79/mach-pb44.c
++++ b/arch/mips/ath79/mach-pb44.c
+@@ -18,6 +18,7 @@
+ #include "dev-gpio-buttons.h"
+ #include "dev-leds-gpio.h"
+ #include "dev-spi.h"
++#include "dev-usb.h"
+
+ #define PB44_GPIO_I2C_SCL 0
+ #define PB44_GPIO_I2C_SDA 1
+@@ -112,6 +113,7 @@ static void __init pb44_init(void)
+ pb44_gpio_keys);
+ ath79_register_spi(&pb44_spi_data, pb44_spi_info,
+ ARRAY_SIZE(pb44_spi_info));
++ ath79_register_usb();
+ }
+
+ MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board",
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -20,6 +20,10 @@
+ #include <linux/bitops.h>
+
+ #define AR71XX_APB_BASE 0x18000000
++#define AR71XX_EHCI_BASE 0x1b000000
++#define AR71XX_EHCI_SIZE 0x1000
++#define AR71XX_OHCI_BASE 0x1c000000
++#define AR71XX_OHCI_SIZE 0x1000
+ #define AR71XX_SPI_BASE 0x1f000000
+ #define AR71XX_SPI_SIZE 0x01000000
+
+@@ -27,6 +31,8 @@
+ #define AR71XX_DDR_CTRL_SIZE 0x100
+ #define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
+ #define AR71XX_UART_SIZE 0x100
++#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
++#define AR71XX_USB_CTRL_SIZE 0x100
+ #define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
+ #define AR71XX_GPIO_SIZE 0x100
+ #define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
+@@ -34,6 +40,16 @@
+ #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
+ #define AR71XX_RESET_SIZE 0x100
+
++#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
++#define AR7240_USB_CTRL_SIZE 0x100
++#define AR7240_OHCI_BASE 0x1b000000
++#define AR7240_OHCI_SIZE 0x1000
++
++#define AR724X_EHCI_BASE 0x1b000000
++#define AR724X_EHCI_SIZE 0x1000
++
++#define AR913X_EHCI_BASE 0x1b000000
++#define AR913X_EHCI_SIZE 0x1000
+ #define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
+ #define AR913X_WMAC_SIZE 0x30000
+
+@@ -105,6 +121,12 @@
+ #define AR913X_AHB_DIV_MASK 0x1
+
+ /*
++ * USB_CONFIG block
++ */
++#define AR71XX_USB_CTRL_REG_FLADJ 0x00
++#define AR71XX_USB_CTRL_REG_CONFIG 0x04
++
++/*
+ * RESET block
+ */
+ #define AR71XX_RESET_REG_TIMER 0x00
+@@ -162,14 +184,22 @@
+ #define AR71XX_RESET_PCI_BUS BIT(1)
+ #define AR71XX_RESET_PCI_CORE BIT(0)
+
++#define AR7240_RESET_USB_HOST BIT(5)
++#define AR7240_RESET_OHCI_DLL BIT(3)
++
+ #define AR724X_RESET_GE1_MDIO BIT(23)
+ #define AR724X_RESET_GE0_MDIO BIT(22)
+ #define AR724X_RESET_PCIE_PHY_SERIAL BIT(10)
+ #define AR724X_RESET_PCIE_PHY BIT(7)
+ #define AR724X_RESET_PCIE BIT(6)
+-#define AR724X_RESET_OHCI_DLL BIT(3)
++#define AR724X_RESET_USB_HOST BIT(5)
++#define AR724X_RESET_USB_PHY BIT(4)
++#define AR724X_RESET_USBSUS_OVERRIDE BIT(3)
+
+ #define AR913X_RESET_AMBA2WMAC BIT(22)
++#define AR913X_RESET_USBSUS_OVERRIDE BIT(10)
++#define AR913X_RESET_USB_HOST BIT(5)
++#define AR913X_RESET_USB_PHY BIT(4)
+
+ #define REV_ID_MAJOR_MASK 0xfff0
+ #define REV_ID_MAJOR_AR71XX 0x00a0
--- /dev/null
+From 44f70a7cd3c0a8481877174a0f12b013c5667933 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 20 Jun 2011 21:26:01 +0200
+Subject: [PATCH 04/27] MIPS: ath79: Remove superfluous parentheses
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: Kathy Giori <kgiori@qca.qualcomm.com>
+Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com>
+Patchwork: https://patchwork.linux-mips.org/patch/2519/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/ath79/setup.c | 6 +++---
+ 1 files changed, 3 insertions(+), 3 deletions(-)
+
+--- a/arch/mips/ath79/setup.c
++++ b/arch/mips/ath79/setup.c
+@@ -101,19 +101,19 @@ static void __init ath79_detect_sys_type
+ case REV_ID_MAJOR_AR7240:
+ ath79_soc = ATH79_SOC_AR7240;
+ chip = "7240";
+- rev = (id & AR724X_REV_ID_REVISION_MASK);
++ rev = id & AR724X_REV_ID_REVISION_MASK;
+ break;
+
+ case REV_ID_MAJOR_AR7241:
+ ath79_soc = ATH79_SOC_AR7241;
+ chip = "7241";
+- rev = (id & AR724X_REV_ID_REVISION_MASK);
++ rev = id & AR724X_REV_ID_REVISION_MASK;
+ break;
+
+ case REV_ID_MAJOR_AR7242:
+ ath79_soc = ATH79_SOC_AR7242;
+ chip = "7242";
+- rev = (id & AR724X_REV_ID_REVISION_MASK);
++ rev = id & AR724X_REV_ID_REVISION_MASK;
+ break;
+
+ case REV_ID_MAJOR_AR913X:
--- /dev/null
+From a6b04a056cd63e9241b94bc5dcc8847fa4cb1d34 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Thu, 23 Jun 2011 18:13:14 +0200
+Subject: [PATCH 05/27] MIPS: ath79: add revision id for the AR933X SoCs
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: Kathy Giori <kgiori@qca.qualcomm.com>
+Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com>
+Patchwork: https://patchwork.linux-mips.org/patch/2538/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/ath79/setup.c | 12 ++++++++++++
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 4 ++++
+ arch/mips/include/asm/mach-ath79/ath79.h | 4 +++-
+ 3 files changed, 19 insertions(+), 1 deletions(-)
+
+--- a/arch/mips/ath79/setup.c
++++ b/arch/mips/ath79/setup.c
+@@ -116,6 +116,18 @@ static void __init ath79_detect_sys_type
+ rev = id & AR724X_REV_ID_REVISION_MASK;
+ break;
+
++ case REV_ID_MAJOR_AR9330:
++ ath79_soc = ATH79_SOC_AR9330;
++ chip = "9330";
++ rev = id & AR933X_REV_ID_REVISION_MASK;
++ break;
++
++ case REV_ID_MAJOR_AR9331:
++ ath79_soc = ATH79_SOC_AR9331;
++ chip = "9331";
++ rev = id & AR933X_REV_ID_REVISION_MASK;
++ break;
++
+ case REV_ID_MAJOR_AR913X:
+ minor = id & AR913X_REV_ID_MINOR_MASK;
+ rev = id >> AR913X_REV_ID_REVISION_SHIFT;
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -207,6 +207,8 @@
+ #define REV_ID_MAJOR_AR7240 0x00c0
+ #define REV_ID_MAJOR_AR7241 0x0100
+ #define REV_ID_MAJOR_AR7242 0x1100
++#define REV_ID_MAJOR_AR9330 0x0110
++#define REV_ID_MAJOR_AR9331 0x1110
+
+ #define AR71XX_REV_ID_MINOR_MASK 0x3
+ #define AR71XX_REV_ID_MINOR_AR7130 0x0
+@@ -221,6 +223,8 @@
+ #define AR913X_REV_ID_REVISION_MASK 0x3
+ #define AR913X_REV_ID_REVISION_SHIFT 2
+
++#define AR933X_REV_ID_REVISION_MASK 0x3
++
+ #define AR724X_REV_ID_REVISION_MASK 0x3
+
+ /*
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
++++ b/arch/mips/include/asm/mach-ath79/ath79.h
+@@ -26,7 +26,9 @@ enum ath79_soc_type {
+ ATH79_SOC_AR7241,
+ ATH79_SOC_AR7242,
+ ATH79_SOC_AR9130,
+- ATH79_SOC_AR9132
++ ATH79_SOC_AR9132,
++ ATH79_SOC_AR9330,
++ ATH79_SOC_AR9331,
+ };
+
+ extern enum ath79_soc_type ath79_soc;
--- /dev/null
+From 84ead7964e423c37a73da30a1a2c4c486f74242d Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 20 Jun 2011 21:26:03 +0200
+Subject: [PATCH 06/27] MIPS: ath79: Add early printk support for the AR933X SoCs
+
+The AR933X SoCs are using a different UART, thus require
+different code for early printk support.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: Kathy Giori <kgiori@qca.qualcomm.com>
+Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com>
+Patchwork: https://patchwork.linux-mips.org/patch/2521/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/ath79/early_printk.c | 76 +++++++++++++++++++++---
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 3 +
+ arch/mips/include/asm/mach-ath79/ar933x_uart.h | 67 +++++++++++++++++++++
+ 3 files changed, 137 insertions(+), 9 deletions(-)
+ create mode 100644 arch/mips/include/asm/mach-ath79/ar933x_uart.h
+
+--- a/arch/mips/ath79/early_printk.c
++++ b/arch/mips/ath79/early_printk.c
+@@ -1,7 +1,7 @@
+ /*
+- * Atheros AR71XX/AR724X/AR913X SoC early printk support
++ * Atheros AR7XXX/AR9XXX SoC early printk support
+ *
+- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+@@ -10,27 +10,85 @@
+ */
+
+ #include <linux/io.h>
++#include <linux/errno.h>
+ #include <linux/serial_reg.h>
+ #include <asm/addrspace.h>
+
++#include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/ar71xx_regs.h>
++#include <asm/mach-ath79/ar933x_uart.h>
+
+-static inline void prom_wait_thre(void __iomem *base)
++static void (*_prom_putchar) (unsigned char);
++
++static inline void prom_putchar_wait(void __iomem *reg, u32 mask, u32 val)
+ {
+- u32 lsr;
++ u32 t;
+
+ do {
+- lsr = __raw_readl(base + UART_LSR * 4);
+- if (lsr & UART_LSR_THRE)
++ t = __raw_readl(reg);
++ if ((t & mask) == val)
+ break;
+ } while (1);
+ }
+
+-void prom_putchar(unsigned char ch)
++static void prom_putchar_ar71xx(unsigned char ch)
+ {
+ void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE));
+
+- prom_wait_thre(base);
++ prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE);
+ __raw_writel(ch, base + UART_TX * 4);
+- prom_wait_thre(base);
++ prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE);
++}
++
++static void prom_putchar_ar933x(unsigned char ch)
++{
++ void __iomem *base = (void __iomem *)(KSEG1ADDR(AR933X_UART_BASE));
++
++ prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR,
++ AR933X_UART_DATA_TX_CSR);
++ __raw_writel(AR933X_UART_DATA_TX_CSR | ch, base + AR933X_UART_DATA_REG);
++ prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR,
++ AR933X_UART_DATA_TX_CSR);
++}
++
++static void prom_putchar_dummy(unsigned char ch)
++{
++ /* nothing to do */
++}
++
++static void prom_putchar_init(void)
++{
++ void __iomem *base;
++ u32 id;
++
++ base = (void __iomem *)(KSEG1ADDR(AR71XX_RESET_BASE));
++ id = __raw_readl(base + AR71XX_RESET_REG_REV_ID);
++ id &= REV_ID_MAJOR_MASK;
++
++ switch (id) {
++ case REV_ID_MAJOR_AR71XX:
++ case REV_ID_MAJOR_AR7240:
++ case REV_ID_MAJOR_AR7241:
++ case REV_ID_MAJOR_AR7242:
++ case REV_ID_MAJOR_AR913X:
++ _prom_putchar = prom_putchar_ar71xx;
++ break;
++
++ case REV_ID_MAJOR_AR9330:
++ case REV_ID_MAJOR_AR9331:
++ _prom_putchar = prom_putchar_ar933x;
++ break;
++
++ default:
++ _prom_putchar = prom_putchar_dummy;
++ break;
++ }
++}
++
++void prom_putchar(unsigned char ch)
++{
++ if (!_prom_putchar)
++ prom_putchar_init();
++
++ _prom_putchar(ch);
+ }
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -53,6 +53,9 @@
+ #define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
+ #define AR913X_WMAC_SIZE 0x30000
+
++#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
++#define AR933X_UART_SIZE 0x14
++
+ /*
+ * DDR_CTRL block
+ */
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ath79/ar933x_uart.h
+@@ -0,0 +1,67 @@
++/*
++ * Atheros AR933X UART defines
++ *
++ * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
++
++#ifndef __AR933X_UART_H
++#define __AR933X_UART_H
++
++#define AR933X_UART_REGS_SIZE 20
++#define AR933X_UART_FIFO_SIZE 16
++
++#define AR933X_UART_DATA_REG 0x00
++#define AR933X_UART_CS_REG 0x04
++#define AR933X_UART_CLOCK_REG 0x08
++#define AR933X_UART_INT_REG 0x0c
++#define AR933X_UART_INT_EN_REG 0x10
++
++#define AR933X_UART_DATA_TX_RX_MASK 0xff
++#define AR933X_UART_DATA_RX_CSR BIT(8)
++#define AR933X_UART_DATA_TX_CSR BIT(9)
++
++#define AR933X_UART_CS_PARITY_S 0
++#define AR933X_UART_CS_PARITY_M 0x3
++#define AR933X_UART_CS_PARITY_NONE 0
++#define AR933X_UART_CS_PARITY_ODD 1
++#define AR933X_UART_CS_PARITY_EVEN 2
++#define AR933X_UART_CS_IF_MODE_S 2
++#define AR933X_UART_CS_IF_MODE_M 0x3
++#define AR933X_UART_CS_IF_MODE_NONE 0
++#define AR933X_UART_CS_IF_MODE_DTE 1
++#define AR933X_UART_CS_IF_MODE_DCE 2
++#define AR933X_UART_CS_FLOW_CTRL_S 4
++#define AR933X_UART_CS_FLOW_CTRL_M 0x3
++#define AR933X_UART_CS_DMA_EN BIT(6)
++#define AR933X_UART_CS_TX_READY_ORIDE BIT(7)
++#define AR933X_UART_CS_RX_READY_ORIDE BIT(8)
++#define AR933X_UART_CS_TX_READY BIT(9)
++#define AR933X_UART_CS_RX_BREAK BIT(10)
++#define AR933X_UART_CS_TX_BREAK BIT(11)
++#define AR933X_UART_CS_HOST_INT BIT(12)
++#define AR933X_UART_CS_HOST_INT_EN BIT(13)
++#define AR933X_UART_CS_TX_BUSY BIT(14)
++#define AR933X_UART_CS_RX_BUSY BIT(15)
++
++#define AR933X_UART_CLOCK_STEP_M 0xffff
++#define AR933X_UART_CLOCK_SCALE_M 0xfff
++#define AR933X_UART_CLOCK_SCALE_S 16
++#define AR933X_UART_CLOCK_STEP_M 0xffff
++
++#define AR933X_UART_INT_RX_VALID BIT(0)
++#define AR933X_UART_INT_TX_READY BIT(1)
++#define AR933X_UART_INT_RX_FRAMING_ERR BIT(2)
++#define AR933X_UART_INT_RX_OFLOW_ERR BIT(3)
++#define AR933X_UART_INT_TX_OFLOW_ERR BIT(4)
++#define AR933X_UART_INT_RX_PARITY_ERR BIT(5)
++#define AR933X_UART_INT_RX_BREAK_ON BIT(6)
++#define AR933X_UART_INT_RX_BREAK_OFF BIT(7)
++#define AR933X_UART_INT_RX_FULL BIT(8)
++#define AR933X_UART_INT_TX_EMPTY BIT(9)
++#define AR933X_UART_INT_ALLINTS 0x3ff
++
++#endif /* __AR933X_UART_H */
--- /dev/null
+From 29c8b2eef2011bf9392479487a51f6927892bfd6 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 20 Jun 2011 21:26:04 +0200
+Subject: [PATCH 07/27] MIPS: ath79: add AR933X specific clock init
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: Kathy Giori <kgiori@qca.qualcomm.com>
+Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com>
+Patchwork: https://patchwork.linux-mips.org/patch/2522/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/ath79/clock.c | 55 ++++++++++++++++++++++++
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 22 +++++++++
+ arch/mips/include/asm/mach-ath79/ath79.h | 6 +++
+ 3 files changed, 83 insertions(+), 0 deletions(-)
+
+--- a/arch/mips/ath79/clock.c
++++ b/arch/mips/ath79/clock.c
+@@ -110,6 +110,59 @@ static void __init ar913x_clocks_init(vo
+ ath79_uart_clk.rate = ath79_ahb_clk.rate;
+ }
+
++static void __init ar933x_clocks_init(void)
++{
++ u32 clock_ctrl;
++ u32 cpu_config;
++ u32 freq;
++ u32 t;
++
++ t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
++ if (t & AR933X_BOOTSTRAP_REF_CLK_40)
++ ath79_ref_clk.rate = (40 * 1000 * 1000);
++ else
++ ath79_ref_clk.rate = (25 * 1000 * 1000);
++
++ clock_ctrl = ath79_pll_rr(AR933X_PLL_CLOCK_CTRL_REG);
++ if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
++ ath79_cpu_clk.rate = ath79_ref_clk.rate;
++ ath79_ahb_clk.rate = ath79_ref_clk.rate;
++ ath79_ddr_clk.rate = ath79_ref_clk.rate;
++ } else {
++ cpu_config = ath79_pll_rr(AR933X_PLL_CPU_CONFIG_REG);
++
++ t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
++ AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
++ freq = ath79_ref_clk.rate / t;
++
++ t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
++ AR933X_PLL_CPU_CONFIG_NINT_MASK;
++ freq *= t;
++
++ t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
++ AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
++ if (t == 0)
++ t = 1;
++
++ freq >>= t;
++
++ t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
++ AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
++ ath79_cpu_clk.rate = freq / t;
++
++ t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
++ AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
++ ath79_ddr_clk.rate = freq / t;
++
++ t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
++ AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
++ ath79_ahb_clk.rate = freq / t;
++ }
++
++ ath79_wdt_clk.rate = ath79_ref_clk.rate;
++ ath79_uart_clk.rate = ath79_ref_clk.rate;
++}
++
+ void __init ath79_clocks_init(void)
+ {
+ if (soc_is_ar71xx())
+@@ -118,6 +171,8 @@ void __init ath79_clocks_init(void)
+ ar724x_clocks_init();
+ else if (soc_is_ar913x())
+ ar913x_clocks_init();
++ else if (soc_is_ar933x())
++ ar933x_clocks_init();
+ else
+ BUG();
+
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -123,6 +123,24 @@
+ #define AR913X_AHB_DIV_SHIFT 19
+ #define AR913X_AHB_DIV_MASK 0x1
+
++#define AR933X_PLL_CPU_CONFIG_REG 0x00
++#define AR933X_PLL_CLOCK_CTRL_REG 0x08
++
++#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
++#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
++#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16
++#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
++#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23
++#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
++
++#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2)
++#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5
++#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3
++#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10
++#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3
++#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15
++#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
++
+ /*
+ * USB_CONFIG block
+ */
+@@ -155,6 +173,8 @@
+
+ #define AR724X_RESET_REG_RESET_MODULE 0x1c
+
++#define AR933X_RESET_REG_BOOTSTRAP 0xac
++
+ #define MISC_INT_ETHSW BIT(12)
+ #define MISC_INT_TIMER4 BIT(10)
+ #define MISC_INT_TIMER3 BIT(9)
+@@ -204,6 +224,8 @@
+ #define AR913X_RESET_USB_HOST BIT(5)
+ #define AR913X_RESET_USB_PHY BIT(4)
+
++#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
++
+ #define REV_ID_MAJOR_MASK 0xfff0
+ #define REV_ID_MAJOR_AR71XX 0x00a0
+ #define REV_ID_MAJOR_AR913X 0x00b0
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
++++ b/arch/mips/include/asm/mach-ath79/ath79.h
+@@ -68,6 +68,12 @@ static inline int soc_is_ar913x(void)
+ ath79_soc == ATH79_SOC_AR9132);
+ }
+
++static inline int soc_is_ar933x(void)
++{
++ return (ath79_soc == ATH79_SOC_AR9330 ||
++ ath79_soc == ATH79_SOC_AR9331);
++}
++
+ extern void __iomem *ath79_ddr_base;
+ extern void __iomem *ath79_pll_base;
+ extern void __iomem *ath79_reset_base;
--- /dev/null
+From 00624e5d91c0e76f38730633eff51fc7630dd27b Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 20 Jun 2011 21:26:05 +0200
+Subject: [PATCH 08/27] MIPS: ath79: Add AR933X specific glue for ath79_device_reset_{set,clear}
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: Kathy Giori <kgiori@qca.qualcomm.com>
+Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com>
+Patchwork: https://patchwork.linux-mips.org/patch/2523/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/ath79/common.c | 4 ++++
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 +
+ 2 files changed, 5 insertions(+), 0 deletions(-)
+
+--- a/arch/mips/ath79/common.c
++++ b/arch/mips/ath79/common.c
+@@ -64,6 +64,8 @@ void ath79_device_reset_set(u32 mask)
+ reg = AR724X_RESET_REG_RESET_MODULE;
+ else if (soc_is_ar913x())
+ reg = AR913X_RESET_REG_RESET_MODULE;
++ else if (soc_is_ar933x())
++ reg = AR933X_RESET_REG_RESET_MODULE;
+ else
+ BUG();
+
+@@ -86,6 +88,8 @@ void ath79_device_reset_clear(u32 mask)
+ reg = AR724X_RESET_REG_RESET_MODULE;
+ else if (soc_is_ar913x())
+ reg = AR913X_RESET_REG_RESET_MODULE;
++ else if (soc_is_ar933x())
++ reg = AR933X_RESET_REG_RESET_MODULE;
+ else
+ BUG();
+
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -173,6 +173,7 @@
+
+ #define AR724X_RESET_REG_RESET_MODULE 0x1c
+
++#define AR933X_RESET_REG_RESET_MODULE 0x1c
+ #define AR933X_RESET_REG_BOOTSTRAP 0xac
+
+ #define MISC_INT_ETHSW BIT(12)
--- /dev/null
+From f2963f6a811da75e2531fd1312aa124cd73f15d5 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 20 Jun 2011 21:26:06 +0200
+Subject: [PATCH 09/27] MIPS: ath79: Add AR933X specific IRQ initialization
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: Kathy Giori <kgiori@qca.qualcomm.com>
+Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com>
+Patchwork: https://patchwork.linux-mips.org/patch/2530/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/ath79/irq.c | 5 ++++-
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 5 +++++
+ 2 files changed, 9 insertions(+), 1 deletions(-)
+
+--- a/arch/mips/ath79/irq.c
++++ b/arch/mips/ath79/irq.c
+@@ -129,7 +129,7 @@ static void __init ath79_misc_irq_init(v
+
+ if (soc_is_ar71xx() || soc_is_ar913x())
+ ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
+- else if (soc_is_ar724x())
++ else if (soc_is_ar724x() || soc_is_ar933x())
+ ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
+ else
+ BUG();
+@@ -186,6 +186,9 @@ void __init arch_init_irq(void)
+ } else if (soc_is_ar913x()) {
+ ath79_ip2_flush_reg = AR913X_DDR_REG_FLUSH_WMAC;
+ ath79_ip3_flush_reg = AR913X_DDR_REG_FLUSH_USB;
++ } else if (soc_is_ar933x()) {
++ ath79_ip2_flush_reg = AR933X_DDR_REG_FLUSH_WMAC;
++ ath79_ip3_flush_reg = AR933X_DDR_REG_FLUSH_USB;
+ } else
+ BUG();
+
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -82,6 +82,11 @@
+ #define AR913X_DDR_REG_FLUSH_USB 0x84
+ #define AR913X_DDR_REG_FLUSH_WMAC 0x88
+
++#define AR933X_DDR_REG_FLUSH_GE0 0x7c
++#define AR933X_DDR_REG_FLUSH_GE1 0x80
++#define AR933X_DDR_REG_FLUSH_USB 0x84
++#define AR933X_DDR_REG_FLUSH_WMAC 0x88
++
+ /*
+ * PLL block
+ */
--- /dev/null
+From e39670cd076caecfa75f5d97803a275dbd1ec4ab Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 20 Jun 2011 21:26:07 +0200
+Subject: [PATCH 10/27] MIPS: ath79: add AR933X specific GPIO initialization
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: Kathy Giori <kgiori@qca.qualcomm.com>
+Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com>
+Patchwork: https://patchwork.linux-mips.org/patch/2524/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/ath79/gpio.c | 2 ++
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 +
+ 2 files changed, 3 insertions(+), 0 deletions(-)
+
+--- a/arch/mips/ath79/gpio.c
++++ b/arch/mips/ath79/gpio.c
+@@ -153,6 +153,8 @@ void __init ath79_gpio_init(void)
+ ath79_gpio_count = AR724X_GPIO_COUNT;
+ else if (soc_is_ar913x())
+ ath79_gpio_count = AR913X_GPIO_COUNT;
++ else if (soc_is_ar933x())
++ ath79_gpio_count = AR933X_GPIO_COUNT;
+ else
+ BUG();
+
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -298,5 +298,6 @@
+ #define AR71XX_GPIO_COUNT 16
+ #define AR724X_GPIO_COUNT 18
+ #define AR913X_GPIO_COUNT 22
++#define AR933X_GPIO_COUNT 30
+
+ #endif /* __ASM_MACH_AR71XX_REGS_H */
--- /dev/null
+From 7ab361d321763ef6296f35eb18ae05be8e28e64a Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 20 Jun 2011 21:26:08 +0200
+Subject: [PATCH 11/27] MIPS: ath79: Add config symbol for the AR933X SoCs
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: Kathy Giori <kgiori@qca.qualcomm.com>
+Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com>
+Patchwork: https://patchwork.linux-mips.org/patch/2525/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/ath79/Kconfig | 3 +++
+ 1 files changed, 3 insertions(+), 0 deletions(-)
+
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -41,6 +41,9 @@ config SOC_AR913X
+ select USB_ARCH_HAS_EHCI
+ def_bool n
+
++config SOC_AR933X
++ def_bool n
++
+ config ATH79_DEV_AR913X_WMAC
+ depends on SOC_AR913X
+ def_bool n
--- /dev/null
+From 7191a2673adbddbbb5aea3489892119e698e77b6 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 20 Jun 2011 21:26:09 +0200
+Subject: [PATCH 12/27] USB: ehci-ath79: Add device_id entry for the AR933X SoCs
+
+Also make the USB_EHCI_ATH79 selectable for the AR933X SoCs.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: Kathy Giori <kgiori@qca.qualcomm.com>
+Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com>
+Cc: Greg Kroah-Hartman <gregkh@suse.de>
+Cc: Alan Stern <stern@rowland.harvard.edu>
+Cc: linux-usb@vger.kernel.org
+Patchwork: https://patchwork.linux-mips.org/patch/2529/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ drivers/usb/host/Kconfig | 2 +-
+ drivers/usb/host/ehci-ath79.c | 4 ++++
+ 2 files changed, 5 insertions(+), 1 deletions(-)
+
+--- a/drivers/usb/host/Kconfig
++++ b/drivers/usb/host/Kconfig
+@@ -210,7 +210,7 @@ config USB_CNS3XXX_EHCI
+
+ config USB_EHCI_ATH79
+ bool "EHCI support for AR7XXX/AR9XXX SoCs"
+- depends on USB_EHCI_HCD && (SOC_AR71XX || SOC_AR724X || SOC_AR913X)
++ depends on USB_EHCI_HCD && (SOC_AR71XX || SOC_AR724X || SOC_AR913X || SOC_AR933X)
+ select USB_EHCI_ROOT_HUB_TT
+ default y
+ ---help---
+--- a/drivers/usb/host/ehci-ath79.c
++++ b/drivers/usb/host/ehci-ath79.c
+@@ -33,6 +33,10 @@ static const struct platform_device_id e
+ .driver_data = EHCI_ATH79_IP_V2,
+ },
+ {
++ .name = "ar933x-ehci",
++ .driver_data = EHCI_ATH79_IP_V2,
++ },
++ {
+ /* terminating entry */
+ },
+ };
--- /dev/null
+From 1355a27c85ae89225e738b9016656a406542ed1b Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 20 Jun 2011 21:26:10 +0200
+Subject: [PATCH 13/27] MIPS: ath79: add AR933X specific USB platform device registration
+
+Also select the USB_ARCH_HAS_EHCI symbol in order to make the
+EHCI driver available.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: Kathy Giori <kgiori@qca.qualcomm.com>
+Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com>
+Patchwork: https://patchwork.linux-mips.org/patch/2527/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/ath79/Kconfig | 1 +
+ arch/mips/ath79/dev-usb.c | 19 +++++++++++++++++++
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 7 +++++++
+ 3 files changed, 27 insertions(+), 0 deletions(-)
+
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -42,6 +42,7 @@ config SOC_AR913X
+ def_bool n
+
+ config SOC_AR933X
++ select USB_ARCH_HAS_EHCI
+ def_bool n
+
+ config ATH79_DEV_AR913X_WMAC
+--- a/arch/mips/ath79/dev-usb.c
++++ b/arch/mips/ath79/dev-usb.c
+@@ -163,6 +163,23 @@ static void __init ar913x_usb_setup(void
+ platform_device_register(&ath79_ehci_device);
+ }
+
++static void __init ar933x_usb_setup(void)
++{
++ ath79_device_reset_set(AR933X_RESET_USBSUS_OVERRIDE);
++ mdelay(10);
++
++ ath79_device_reset_clear(AR933X_RESET_USB_HOST);
++ mdelay(10);
++
++ ath79_device_reset_clear(AR933X_RESET_USB_PHY);
++ mdelay(10);
++
++ ath79_ehci_resources[0].start = AR933X_EHCI_BASE;
++ ath79_ehci_resources[0].end = AR933X_EHCI_BASE + AR933X_EHCI_SIZE - 1;
++ ath79_ehci_device.name = "ar933x-ehci";
++ platform_device_register(&ath79_ehci_device);
++}
++
+ void __init ath79_register_usb(void)
+ {
+ if (soc_is_ar71xx())
+@@ -173,6 +190,8 @@ void __init ath79_register_usb(void)
+ ar724x_usb_setup();
+ else if (soc_is_ar913x())
+ ar913x_usb_setup();
++ else if (soc_is_ar933x())
++ ar933x_usb_setup();
+ else
+ BUG();
+ }
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -56,6 +56,9 @@
+ #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
+ #define AR933X_UART_SIZE 0x14
+
++#define AR933X_EHCI_BASE 0x1b000000
++#define AR933X_EHCI_SIZE 0x1000
++
+ /*
+ * DDR_CTRL block
+ */
+@@ -230,6 +233,10 @@
+ #define AR913X_RESET_USB_HOST BIT(5)
+ #define AR913X_RESET_USB_PHY BIT(4)
+
++#define AR933X_RESET_USB_HOST BIT(5)
++#define AR933X_RESET_USB_PHY BIT(4)
++#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
++
+ #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
+
+ #define REV_ID_MAJOR_MASK 0xfff0
--- /dev/null
+From 1de387abd06fb67aaa8e27a48e378ffd9aaddd74 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 20 Jun 2011 19:26:11 +0200
+Subject: [PATCH 14/27] SERIAL: AR933X: Add driver for the built-in UART of the SoC
+
+This patch adds the driver for the built-in UART of the
+Atheros AR933X SoCs.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: Kathy Giori <kgiori@qca.qualcomm.com>
+Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com>
+Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
+Cc: linux-serial@vger.kernel.org
+Patchwork: https://patchwork.linux-mips.org/patch/2526/
+Signed-off-by: Alan Cox <alan@linux.intel.com>
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ .../include/asm/mach-ath79/ar933x_uart_platform.h | 18 +
+ drivers/tty/serial/Kconfig | 23 +
+ drivers/tty/serial/Makefile | 1 +
+ drivers/tty/serial/ar933x_uart.c | 688 ++++++++++++++++++++
+ include/linux/serial_core.h | 4 +
+ 5 files changed, 734 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h
+ create mode 100644 drivers/tty/serial/ar933x_uart.c
+
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h
+@@ -0,0 +1,18 @@
++/*
++ * Platform data definition for Atheros AR933X UART
++ *
++ * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
++
++#ifndef _AR933X_UART_PLATFORM_H
++#define _AR933X_UART_PLATFORM_H
++
++struct ar933x_uart_platform_data {
++ unsigned uartclk;
++};
++
++#endif /* _AR933X_UART_PLATFORM_H */
+--- a/drivers/tty/serial/Kconfig
++++ b/drivers/tty/serial/Kconfig
+@@ -1610,4 +1610,27 @@ config SERIAL_XILINX_PS_UART_CONSOLE
+ help
+ Enable a Xilinx PS UART port to be the system console.
+
++config SERIAL_AR933X
++ bool "AR933X serial port support"
++ depends on SOC_AR933X
++ select SERIAL_CORE
++ help
++ If you have an Atheros AR933X SOC based board and want to use the
++ built-in UART of the SoC, say Y to this option.
++
++config SERIAL_AR933X_CONSOLE
++ bool "Console on AR933X serial port"
++ depends on SERIAL_AR933X=y
++ select SERIAL_CORE_CONSOLE
++ help
++ Enable a built-in UART port of the AR933X to be the system console.
++
++config SERIAL_AR933X_NR_UARTS
++ int "Maximum number of AR933X serial ports"
++ depends on SERIAL_AR933X
++ default "2"
++ help
++ Set this to the number of serial ports you want the driver
++ to support.
++
+ endmenu
+--- a/drivers/tty/serial/Makefile
++++ b/drivers/tty/serial/Makefile
+@@ -94,3 +94,4 @@ obj-$(CONFIG_SERIAL_MSM_SMD) += msm_smd_
+ obj-$(CONFIG_SERIAL_MXS_AUART) += mxs-auart.o
+ obj-$(CONFIG_SERIAL_LANTIQ) += lantiq.o
+ obj-$(CONFIG_SERIAL_XILINX_PS_UART) += xilinx_uartps.o
++obj-$(CONFIG_SERIAL_AR933X) += ar933x_uart.o
+--- /dev/null
++++ b/drivers/tty/serial/ar933x_uart.c
+@@ -0,0 +1,688 @@
++/*
++ * Atheros AR933X SoC built-in UART driver
++ *
++ * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
++ *
++ * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
++
++#include <linux/module.h>
++#include <linux/ioport.h>
++#include <linux/init.h>
++#include <linux/console.h>
++#include <linux/sysrq.h>
++#include <linux/delay.h>
++#include <linux/platform_device.h>
++#include <linux/tty.h>
++#include <linux/tty_flip.h>
++#include <linux/serial_core.h>
++#include <linux/serial.h>
++#include <linux/slab.h>
++#include <linux/io.h>
++#include <linux/irq.h>
++
++#include <asm/mach-ath79/ar933x_uart.h>
++#include <asm/mach-ath79/ar933x_uart_platform.h>
++
++#define DRIVER_NAME "ar933x-uart"
++
++#define AR933X_DUMMY_STATUS_RD 0x01
++
++static struct uart_driver ar933x_uart_driver;
++
++struct ar933x_uart_port {
++ struct uart_port port;
++ unsigned int ier; /* shadow Interrupt Enable Register */
++};
++
++static inline unsigned int ar933x_uart_read(struct ar933x_uart_port *up,
++ int offset)
++{
++ return readl(up->port.membase + offset);
++}
++
++static inline void ar933x_uart_write(struct ar933x_uart_port *up,
++ int offset, unsigned int value)
++{
++ writel(value, up->port.membase + offset);
++}
++
++static inline void ar933x_uart_rmw(struct ar933x_uart_port *up,
++ unsigned int offset,
++ unsigned int mask,
++ unsigned int val)
++{
++ unsigned int t;
++
++ t = ar933x_uart_read(up, offset);
++ t &= ~mask;
++ t |= val;
++ ar933x_uart_write(up, offset, t);
++}
++
++static inline void ar933x_uart_rmw_set(struct ar933x_uart_port *up,
++ unsigned int offset,
++ unsigned int val)
++{
++ ar933x_uart_rmw(up, offset, 0, val);
++}
++
++static inline void ar933x_uart_rmw_clear(struct ar933x_uart_port *up,
++ unsigned int offset,
++ unsigned int val)
++{
++ ar933x_uart_rmw(up, offset, val, 0);
++}
++
++static inline void ar933x_uart_start_tx_interrupt(struct ar933x_uart_port *up)
++{
++ up->ier |= AR933X_UART_INT_TX_EMPTY;
++ ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
++}
++
++static inline void ar933x_uart_stop_tx_interrupt(struct ar933x_uart_port *up)
++{
++ up->ier &= ~AR933X_UART_INT_TX_EMPTY;
++ ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
++}
++
++static inline void ar933x_uart_putc(struct ar933x_uart_port *up, int ch)
++{
++ unsigned int rdata;
++
++ rdata = ch & AR933X_UART_DATA_TX_RX_MASK;
++ rdata |= AR933X_UART_DATA_TX_CSR;
++ ar933x_uart_write(up, AR933X_UART_DATA_REG, rdata);
++}
++
++static unsigned int ar933x_uart_tx_empty(struct uart_port *port)
++{
++ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
++ unsigned long flags;
++ unsigned int rdata;
++
++ spin_lock_irqsave(&up->port.lock, flags);
++ rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG);
++ spin_unlock_irqrestore(&up->port.lock, flags);
++
++ return (rdata & AR933X_UART_DATA_TX_CSR) ? 0 : TIOCSER_TEMT;
++}
++
++static unsigned int ar933x_uart_get_mctrl(struct uart_port *port)
++{
++ return TIOCM_CAR;
++}
++
++static void ar933x_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
++{
++}
++
++static void ar933x_uart_start_tx(struct uart_port *port)
++{
++ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
++
++ ar933x_uart_start_tx_interrupt(up);
++}
++
++static void ar933x_uart_stop_tx(struct uart_port *port)
++{
++ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
++
++ ar933x_uart_stop_tx_interrupt(up);
++}
++
++static void ar933x_uart_stop_rx(struct uart_port *port)
++{
++ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
++
++ up->ier &= ~AR933X_UART_INT_RX_VALID;
++ ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
++}
++
++static void ar933x_uart_break_ctl(struct uart_port *port, int break_state)
++{
++ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
++ unsigned long flags;
++
++ spin_lock_irqsave(&up->port.lock, flags);
++ if (break_state == -1)
++ ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
++ AR933X_UART_CS_TX_BREAK);
++ else
++ ar933x_uart_rmw_clear(up, AR933X_UART_CS_REG,
++ AR933X_UART_CS_TX_BREAK);
++ spin_unlock_irqrestore(&up->port.lock, flags);
++}
++
++static void ar933x_uart_enable_ms(struct uart_port *port)
++{
++}
++
++static void ar933x_uart_set_termios(struct uart_port *port,
++ struct ktermios *new,
++ struct ktermios *old)
++{
++ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
++ unsigned int cs;
++ unsigned long flags;
++ unsigned int baud, scale;
++
++ /* Only CS8 is supported */
++ new->c_cflag &= ~CSIZE;
++ new->c_cflag |= CS8;
++
++ /* Only one stop bit is supported */
++ new->c_cflag &= ~CSTOPB;
++
++ cs = 0;
++ if (new->c_cflag & PARENB) {
++ if (!(new->c_cflag & PARODD))
++ cs |= AR933X_UART_CS_PARITY_EVEN;
++ else
++ cs |= AR933X_UART_CS_PARITY_ODD;
++ } else {
++ cs |= AR933X_UART_CS_PARITY_NONE;
++ }
++
++ /* Mark/space parity is not supported */
++ new->c_cflag &= ~CMSPAR;
++
++ baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
++ scale = (port->uartclk / (16 * baud)) - 1;
++
++ /*
++ * Ok, we're now changing the port state. Do it with
++ * interrupts disabled.
++ */
++ spin_lock_irqsave(&up->port.lock, flags);
++
++ /* Update the per-port timeout. */
++ uart_update_timeout(port, new->c_cflag, baud);
++
++ up->port.ignore_status_mask = 0;
++
++ /* ignore all characters if CREAD is not set */
++ if ((new->c_cflag & CREAD) == 0)
++ up->port.ignore_status_mask |= AR933X_DUMMY_STATUS_RD;
++
++ ar933x_uart_write(up, AR933X_UART_CLOCK_REG,
++ scale << AR933X_UART_CLOCK_SCALE_S | 8192);
++
++ /* setup configuration register */
++ ar933x_uart_rmw(up, AR933X_UART_CS_REG, AR933X_UART_CS_PARITY_M, cs);
++
++ /* enable host interrupt */
++ ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
++ AR933X_UART_CS_HOST_INT_EN);
++
++ spin_unlock_irqrestore(&up->port.lock, flags);
++
++ if (tty_termios_baud_rate(new))
++ tty_termios_encode_baud_rate(new, baud, baud);
++}
++
++static void ar933x_uart_rx_chars(struct ar933x_uart_port *up)
++{
++ struct tty_struct *tty;
++ int max_count = 256;
++
++ tty = tty_port_tty_get(&up->port.state->port);
++ do {
++ unsigned int rdata;
++ unsigned char ch;
++
++ rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG);
++ if ((rdata & AR933X_UART_DATA_RX_CSR) == 0)
++ break;
++
++ /* remove the character from the FIFO */
++ ar933x_uart_write(up, AR933X_UART_DATA_REG,
++ AR933X_UART_DATA_RX_CSR);
++
++ if (!tty) {
++ /* discard the data if no tty available */
++ continue;
++ }
++
++ up->port.icount.rx++;
++ ch = rdata & AR933X_UART_DATA_TX_RX_MASK;
++
++ if (uart_handle_sysrq_char(&up->port, ch))
++ continue;
++
++ if ((up->port.ignore_status_mask & AR933X_DUMMY_STATUS_RD) == 0)
++ tty_insert_flip_char(tty, ch, TTY_NORMAL);
++ } while (max_count-- > 0);
++
++ if (tty) {
++ tty_flip_buffer_push(tty);
++ tty_kref_put(tty);
++ }
++}
++
++static void ar933x_uart_tx_chars(struct ar933x_uart_port *up)
++{
++ struct circ_buf *xmit = &up->port.state->xmit;
++ int count;
++
++ if (uart_tx_stopped(&up->port))
++ return;
++
++ count = up->port.fifosize;
++ do {
++ unsigned int rdata;
++
++ rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG);
++ if ((rdata & AR933X_UART_DATA_TX_CSR) == 0)
++ break;
++
++ if (up->port.x_char) {
++ ar933x_uart_putc(up, up->port.x_char);
++ up->port.icount.tx++;
++ up->port.x_char = 0;
++ continue;
++ }
++
++ if (uart_circ_empty(xmit))
++ break;
++
++ ar933x_uart_putc(up, xmit->buf[xmit->tail]);
++
++ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
++ up->port.icount.tx++;
++ } while (--count > 0);
++
++ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
++ uart_write_wakeup(&up->port);
++
++ if (!uart_circ_empty(xmit))
++ ar933x_uart_start_tx_interrupt(up);
++}
++
++static irqreturn_t ar933x_uart_interrupt(int irq, void *dev_id)
++{
++ struct ar933x_uart_port *up = dev_id;
++ unsigned int status;
++
++ status = ar933x_uart_read(up, AR933X_UART_CS_REG);
++ if ((status & AR933X_UART_CS_HOST_INT) == 0)
++ return IRQ_NONE;
++
++ spin_lock(&up->port.lock);
++
++ status = ar933x_uart_read(up, AR933X_UART_INT_REG);
++ status &= ar933x_uart_read(up, AR933X_UART_INT_EN_REG);
++
++ if (status & AR933X_UART_INT_RX_VALID) {
++ ar933x_uart_write(up, AR933X_UART_INT_REG,
++ AR933X_UART_INT_RX_VALID);
++ ar933x_uart_rx_chars(up);
++ }
++
++ if (status & AR933X_UART_INT_TX_EMPTY) {
++ ar933x_uart_write(up, AR933X_UART_INT_REG,
++ AR933X_UART_INT_TX_EMPTY);
++ ar933x_uart_stop_tx_interrupt(up);
++ ar933x_uart_tx_chars(up);
++ }
++
++ spin_unlock(&up->port.lock);
++
++ return IRQ_HANDLED;
++}
++
++static int ar933x_uart_startup(struct uart_port *port)
++{
++ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
++ unsigned long flags;
++ int ret;
++
++ ret = request_irq(up->port.irq, ar933x_uart_interrupt,
++ up->port.irqflags, dev_name(up->port.dev), up);
++ if (ret)
++ return ret;
++
++ spin_lock_irqsave(&up->port.lock, flags);
++
++ /* Enable HOST interrupts */
++ ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
++ AR933X_UART_CS_HOST_INT_EN);
++
++ /* Enable RX interrupts */
++ up->ier = AR933X_UART_INT_RX_VALID;
++ ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
++
++ spin_unlock_irqrestore(&up->port.lock, flags);
++
++ return 0;
++}
++
++static void ar933x_uart_shutdown(struct uart_port *port)
++{
++ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
++
++ /* Disable all interrupts */
++ up->ier = 0;
++ ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
++
++ /* Disable break condition */
++ ar933x_uart_rmw_clear(up, AR933X_UART_CS_REG,
++ AR933X_UART_CS_TX_BREAK);
++
++ free_irq(up->port.irq, up);
++}
++
++static const char *ar933x_uart_type(struct uart_port *port)
++{
++ return (port->type == PORT_AR933X) ? "AR933X UART" : NULL;
++}
++
++static void ar933x_uart_release_port(struct uart_port *port)
++{
++ /* Nothing to release ... */
++}
++
++static int ar933x_uart_request_port(struct uart_port *port)
++{
++ /* UARTs always present */
++ return 0;
++}
++
++static void ar933x_uart_config_port(struct uart_port *port, int flags)
++{
++ if (flags & UART_CONFIG_TYPE)
++ port->type = PORT_AR933X;
++}
++
++static int ar933x_uart_verify_port(struct uart_port *port,
++ struct serial_struct *ser)
++{
++ if (ser->type != PORT_UNKNOWN &&
++ ser->type != PORT_AR933X)
++ return -EINVAL;
++
++ if (ser->irq < 0 || ser->irq >= NR_IRQS)
++ return -EINVAL;
++
++ if (ser->baud_base < 28800)
++ return -EINVAL;
++
++ return 0;
++}
++
++static struct uart_ops ar933x_uart_ops = {
++ .tx_empty = ar933x_uart_tx_empty,
++ .set_mctrl = ar933x_uart_set_mctrl,
++ .get_mctrl = ar933x_uart_get_mctrl,
++ .stop_tx = ar933x_uart_stop_tx,
++ .start_tx = ar933x_uart_start_tx,
++ .stop_rx = ar933x_uart_stop_rx,
++ .enable_ms = ar933x_uart_enable_ms,
++ .break_ctl = ar933x_uart_break_ctl,
++ .startup = ar933x_uart_startup,
++ .shutdown = ar933x_uart_shutdown,
++ .set_termios = ar933x_uart_set_termios,
++ .type = ar933x_uart_type,
++ .release_port = ar933x_uart_release_port,
++ .request_port = ar933x_uart_request_port,
++ .config_port = ar933x_uart_config_port,
++ .verify_port = ar933x_uart_verify_port,
++};
++
++#ifdef CONFIG_SERIAL_AR933X_CONSOLE
++
++static struct ar933x_uart_port *
++ar933x_console_ports[CONFIG_SERIAL_AR933X_NR_UARTS];
++
++static void ar933x_uart_wait_xmitr(struct ar933x_uart_port *up)
++{
++ unsigned int status;
++ unsigned int timeout = 60000;
++
++ /* Wait up to 60ms for the character(s) to be sent. */
++ do {
++ status = ar933x_uart_read(up, AR933X_UART_DATA_REG);
++ if (--timeout == 0)
++ break;
++ udelay(1);
++ } while ((status & AR933X_UART_DATA_TX_CSR) == 0);
++}
++
++static void ar933x_uart_console_putchar(struct uart_port *port, int ch)
++{
++ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
++
++ ar933x_uart_wait_xmitr(up);
++ ar933x_uart_putc(up, ch);
++}
++
++static void ar933x_uart_console_write(struct console *co, const char *s,
++ unsigned int count)
++{
++ struct ar933x_uart_port *up = ar933x_console_ports[co->index];
++ unsigned long flags;
++ unsigned int int_en;
++ int locked = 1;
++
++ local_irq_save(flags);
++
++ if (up->port.sysrq)
++ locked = 0;
++ else if (oops_in_progress)
++ locked = spin_trylock(&up->port.lock);
++ else
++ spin_lock(&up->port.lock);
++
++ /*
++ * First save the IER then disable the interrupts
++ */
++ int_en = ar933x_uart_read(up, AR933X_UART_INT_EN_REG);
++ ar933x_uart_write(up, AR933X_UART_INT_EN_REG, 0);
++
++ uart_console_write(&up->port, s, count, ar933x_uart_console_putchar);
++
++ /*
++ * Finally, wait for transmitter to become empty
++ * and restore the IER
++ */
++ ar933x_uart_wait_xmitr(up);
++ ar933x_uart_write(up, AR933X_UART_INT_EN_REG, int_en);
++
++ ar933x_uart_write(up, AR933X_UART_INT_REG, AR933X_UART_INT_ALLINTS);
++
++ if (locked)
++ spin_unlock(&up->port.lock);
++
++ local_irq_restore(flags);
++}
++
++static int ar933x_uart_console_setup(struct console *co, char *options)
++{
++ struct ar933x_uart_port *up;
++ int baud = 115200;
++ int bits = 8;
++ int parity = 'n';
++ int flow = 'n';
++
++ if (co->index < 0 || co->index >= CONFIG_SERIAL_AR933X_NR_UARTS)
++ return -EINVAL;
++
++ up = ar933x_console_ports[co->index];
++ if (!up)
++ return -ENODEV;
++
++ if (options)
++ uart_parse_options(options, &baud, &parity, &bits, &flow);
++
++ return uart_set_options(&up->port, co, baud, parity, bits, flow);
++}
++
++static struct console ar933x_uart_console = {
++ .name = "ttyATH",
++ .write = ar933x_uart_console_write,
++ .device = uart_console_device,
++ .setup = ar933x_uart_console_setup,
++ .flags = CON_PRINTBUFFER,
++ .index = -1,
++ .data = &ar933x_uart_driver,
++};
++
++static void ar933x_uart_add_console_port(struct ar933x_uart_port *up)
++{
++ ar933x_console_ports[up->port.line] = up;
++}
++
++#define AR933X_SERIAL_CONSOLE (&ar933x_uart_console)
++
++#else
++
++static inline void ar933x_uart_add_console_port(struct ar933x_uart_port *up) {}
++
++#define AR933X_SERIAL_CONSOLE NULL
++
++#endif /* CONFIG_SERIAL_AR933X_CONSOLE */
++
++static struct uart_driver ar933x_uart_driver = {
++ .owner = THIS_MODULE,
++ .driver_name = DRIVER_NAME,
++ .dev_name = "ttyATH",
++ .nr = CONFIG_SERIAL_AR933X_NR_UARTS,
++ .cons = AR933X_SERIAL_CONSOLE,
++};
++
++static int __devinit ar933x_uart_probe(struct platform_device *pdev)
++{
++ struct ar933x_uart_platform_data *pdata;
++ struct ar933x_uart_port *up;
++ struct uart_port *port;
++ struct resource *mem_res;
++ struct resource *irq_res;
++ int id;
++ int ret;
++
++ pdata = pdev->dev.platform_data;
++ if (!pdata)
++ return -EINVAL;
++
++ id = pdev->id;
++ if (id == -1)
++ id = 0;
++
++ if (id > CONFIG_SERIAL_AR933X_NR_UARTS)
++ return -EINVAL;
++
++ mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!mem_res) {
++ dev_err(&pdev->dev, "no MEM resource\n");
++ return -EINVAL;
++ }
++
++ irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
++ if (!irq_res) {
++ dev_err(&pdev->dev, "no IRQ resource\n");
++ return -EINVAL;
++ }
++
++ up = kzalloc(sizeof(struct ar933x_uart_port), GFP_KERNEL);
++ if (!up)
++ return -ENOMEM;
++
++ port = &up->port;
++ port->mapbase = mem_res->start;
++
++ port->membase = ioremap(mem_res->start, AR933X_UART_REGS_SIZE);
++ if (!port->membase) {
++ ret = -ENOMEM;
++ goto err_free_up;
++ }
++
++ port->line = id;
++ port->irq = irq_res->start;
++ port->dev = &pdev->dev;
++ port->type = PORT_AR933X;
++ port->iotype = UPIO_MEM32;
++ port->uartclk = pdata->uartclk;
++
++ port->regshift = 2;
++ port->fifosize = AR933X_UART_FIFO_SIZE;
++ port->ops = &ar933x_uart_ops;
++
++ ar933x_uart_add_console_port(up);
++
++ ret = uart_add_one_port(&ar933x_uart_driver, &up->port);
++ if (ret)
++ goto err_unmap;
++
++ platform_set_drvdata(pdev, up);
++ return 0;
++
++err_unmap:
++ iounmap(up->port.membase);
++err_free_up:
++ kfree(up);
++ return ret;
++}
++
++static int __devexit ar933x_uart_remove(struct platform_device *pdev)
++{
++ struct ar933x_uart_port *up;
++
++ up = platform_get_drvdata(pdev);
++ platform_set_drvdata(pdev, NULL);
++
++ if (up) {
++ uart_remove_one_port(&ar933x_uart_driver, &up->port);
++ iounmap(up->port.membase);
++ kfree(up);
++ }
++
++ return 0;
++}
++
++static struct platform_driver ar933x_uart_platform_driver = {
++ .probe = ar933x_uart_probe,
++ .remove = __devexit_p(ar933x_uart_remove),
++ .driver = {
++ .name = DRIVER_NAME,
++ .owner = THIS_MODULE,
++ },
++};
++
++static int __init ar933x_uart_init(void)
++{
++ int ret;
++
++ ar933x_uart_driver.nr = CONFIG_SERIAL_AR933X_NR_UARTS;
++ ret = uart_register_driver(&ar933x_uart_driver);
++ if (ret)
++ goto err_out;
++
++ ret = platform_driver_register(&ar933x_uart_platform_driver);
++ if (ret)
++ goto err_unregister_uart_driver;
++
++ return 0;
++
++err_unregister_uart_driver:
++ uart_unregister_driver(&ar933x_uart_driver);
++err_out:
++ return ret;
++}
++
++static void __exit ar933x_uart_exit(void)
++{
++ platform_driver_unregister(&ar933x_uart_platform_driver);
++ uart_unregister_driver(&ar933x_uart_driver);
++}
++
++module_init(ar933x_uart_init);
++module_exit(ar933x_uart_exit);
++
++MODULE_DESCRIPTION("Atheros AR933X UART driver");
++MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
++MODULE_LICENSE("GPL v2");
++MODULE_ALIAS("platform:" DRIVER_NAME);
+--- a/include/linux/serial_core.h
++++ b/include/linux/serial_core.h
+@@ -207,6 +207,10 @@
+ /* Xilinx PSS UART */
+ #define PORT_XUARTPS 98
+
++/* Atheros AR933X SoC */
++#define PORT_AR933X 99
++
++
+ #ifdef __KERNEL__
+
+ #include <linux/compiler.h>
--- /dev/null
+From d9215f4c69b414f589eeeff002af7ef58b96b172 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 20 Jun 2011 19:26:12 +0200
+Subject: [PATCH 15/27] MIPS: ath79: register UART device for the AR933X SoCs
+
+The AR933X SoCs does not have a 8250 compatible UART, they
+are using a different UART core. Register a different platform
+device for the different UART.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: Kathy Giori <kgiori@qca.qualcomm.com>
+Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com>
+Patchwork: https://patchwork.linux-mips.org/patch/2528/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/ath79/dev-common.c | 38 ++++++++++++++++++++++++++++++++++++--
+ 1 files changed, 36 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/ath79/dev-common.c
++++ b/arch/mips/ath79/dev-common.c
+@@ -20,6 +20,7 @@
+
+ #include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/ar71xx_regs.h>
++#include <asm/mach-ath79/ar933x_uart_platform.h>
+ #include "common.h"
+ #include "dev-common.h"
+
+@@ -54,6 +55,30 @@ static struct platform_device ath79_uart
+ },
+ };
+
++static struct resource ar933x_uart_resources[] = {
++ {
++ .start = AR933X_UART_BASE,
++ .end = AR933X_UART_BASE + AR71XX_UART_SIZE - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .start = ATH79_MISC_IRQ_UART,
++ .end = ATH79_MISC_IRQ_UART,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct ar933x_uart_platform_data ar933x_uart_data;
++static struct platform_device ar933x_uart_device = {
++ .name = "ar933x-uart",
++ .id = -1,
++ .resource = ar933x_uart_resources,
++ .num_resources = ARRAY_SIZE(ar933x_uart_resources),
++ .dev = {
++ .platform_data = &ar933x_uart_data,
++ },
++};
++
+ void __init ath79_register_uart(void)
+ {
+ struct clk *clk;
+@@ -62,8 +87,17 @@ void __init ath79_register_uart(void)
+ if (IS_ERR(clk))
+ panic("unable to get UART clock, err=%ld", PTR_ERR(clk));
+
+- ath79_uart_data[0].uartclk = clk_get_rate(clk);
+- platform_device_register(&ath79_uart_device);
++ if (soc_is_ar71xx() ||
++ soc_is_ar724x() ||
++ soc_is_ar913x()) {
++ ath79_uart_data[0].uartclk = clk_get_rate(clk);
++ platform_device_register(&ath79_uart_device);
++ } else if (soc_is_ar933x()) {
++ ar933x_uart_data.uartclk = clk_get_rate(clk);
++ platform_device_register(&ar933x_uart_device);
++ } else {
++ BUG();
++ }
+ }
+
+ static struct platform_device ath79_wdt_device = {
--- /dev/null
+From d7b27740e8376c1c147297b526f9a8e330c1fe17 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 20 Jun 2011 19:26:13 +0200
+Subject: [PATCH 16/27] MIPS: ath79: Add initial support for the Atheros AP121 reference board
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: Kathy Giori <kgiori@qca.qualcomm.com>
+Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com>
+Patchwork: https://patchwork.linux-mips.org/patch/2531/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/ath79/Kconfig | 11 +++++
+ arch/mips/ath79/Makefile | 1 +
+ arch/mips/ath79/mach-ap121.c | 88 ++++++++++++++++++++++++++++++++++++++++++
+ arch/mips/ath79/machtypes.h | 1 +
+ 4 files changed, 101 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/ath79/mach-ap121.c
+
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -2,6 +2,17 @@ if ATH79
+
+ menu "Atheros AR71XX/AR724X/AR913X machine selection"
+
++config ATH79_MACH_AP121
++ bool "Atheros AP121 reference board"
++ select SOC_AR933X
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_SPI
++ select ATH79_DEV_USB
++ help
++ Say 'Y' here if you want your kernel to support the
++ Atheros AP121 reference board.
++
+ config ATH79_MACH_AP81
+ bool "Atheros AP81 reference board"
+ select SOC_AR913X
+--- a/arch/mips/ath79/Makefile
++++ b/arch/mips/ath79/Makefile
+@@ -25,5 +25,6 @@ obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.
+ #
+ # Machines
+ #
++obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o
+ obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o
+ obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o
+--- /dev/null
++++ b/arch/mips/ath79/mach-ap121.c
+@@ -0,0 +1,88 @@
++/*
++ * Atheros AP121 board support
++ *
++ * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
++
++#include "machtypes.h"
++#include "dev-gpio-buttons.h"
++#include "dev-leds-gpio.h"
++#include "dev-spi.h"
++#include "dev-usb.h"
++
++#define AP121_GPIO_LED_WLAN 0
++#define AP121_GPIO_LED_USB 1
++
++#define AP121_GPIO_BTN_JUMPSTART 11
++#define AP121_GPIO_BTN_RESET 12
++
++#define AP121_KEYS_POLL_INTERVAL 20 /* msecs */
++#define AP121_KEYS_DEBOUNCE_INTERVAL (3 * AP121_KEYS_POLL_INTERVAL)
++
++#define AP121_CAL_DATA_ADDR 0x1fff1000
++
++static struct gpio_led ap121_leds_gpio[] __initdata = {
++ {
++ .name = "ap121:green:usb",
++ .gpio = AP121_GPIO_LED_USB,
++ .active_low = 0,
++ },
++ {
++ .name = "ap121:green:wlan",
++ .gpio = AP121_GPIO_LED_WLAN,
++ .active_low = 0,
++ },
++};
++
++static struct gpio_keys_button ap121_gpio_keys[] __initdata = {
++ {
++ .desc = "jumpstart button",
++ .type = EV_KEY,
++ .code = KEY_WPS_BUTTON,
++ .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
++ .gpio = AP121_GPIO_BTN_JUMPSTART,
++ .active_low = 1,
++ },
++ {
++ .desc = "reset button",
++ .type = EV_KEY,
++ .code = KEY_RESTART,
++ .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
++ .gpio = AP121_GPIO_BTN_RESET,
++ .active_low = 1,
++ }
++};
++
++static struct spi_board_info ap121_spi_info[] = {
++ {
++ .bus_num = 0,
++ .chip_select = 0,
++ .max_speed_hz = 25000000,
++ .modalias = "mx25l1606e",
++ }
++};
++
++static struct ath79_spi_platform_data ap121_spi_data = {
++ .bus_num = 0,
++ .num_chipselect = 1,
++};
++
++static void __init ap121_setup(void)
++{
++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_leds_gpio),
++ ap121_leds_gpio);
++ ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL,
++ ARRAY_SIZE(ap121_gpio_keys),
++ ap121_gpio_keys);
++
++ ath79_register_spi(&ap121_spi_data, ap121_spi_info,
++ ARRAY_SIZE(ap121_spi_info));
++ ath79_register_usb();
++}
++
++MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board",
++ ap121_setup);
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -16,6 +16,7 @@
+
+ enum ath79_mach_type {
+ ATH79_MACH_GENERIC = 0,
++ ATH79_MACH_AP121, /* Atheros AP121 reference board */
+ ATH79_MACH_AP81, /* Atheros AP81 reference board */
+ ATH79_MACH_PB44, /* Atheros PB44 reference board */
+ };
--- /dev/null
+From 958e444a5a7750c407ed0c90af28f74295478e99 Mon Sep 17 00:00:00 2001
+From: Rene Bolldorf <xsecute@googlemail.com>
+Date: Thu, 17 Nov 2011 14:25:09 +0000
+Subject: [PATCH 17/27] MIPS: Initial PCI support for Atheros 724x SoCs.
+
+[ralf@linux-mips.org: Fixed the odd formatting of all break statements.]
+
+Signed-off-by: Rene Bolldorf <xsecute@googlemail.com>
+Cc: linux-mips@linux-mips.org
+Cc: linux-kernel@vger.kernel.org
+Patchwork: https://patchwork.linux-mips.org/patch/3019/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/include/asm/mach-ath79/pci-ath724x.h | 21 +++
+ arch/mips/pci/Makefile | 1 +
+ arch/mips/pci/pci-ath724x.c | 174 ++++++++++++++++++++++++
+ 3 files changed, 196 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/include/asm/mach-ath79/pci-ath724x.h
+ create mode 100644 arch/mips/pci/pci-ath724x.c
+
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ath79/pci-ath724x.h
+@@ -0,0 +1,21 @@
++/*
++ * Atheros 724x PCI support
++ *
++ * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
++
++#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H
++#define __ASM_MACH_ATH79_PCI_ATH724X_H
++
++struct ath724x_pci_data {
++ int irq;
++ void *pdata;
++};
++
++void ath724x_pci_add_data(struct ath724x_pci_data *data, int size);
++
++#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */
+--- a/arch/mips/pci/Makefile
++++ b/arch/mips/pci/Makefile
+@@ -19,6 +19,7 @@ obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
+ obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
+ ops-bcm63xx.o
+ obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
++obj-$(CONFIG_SOC_AR724X) += pci-ath724x.o
+
+ #
+ # These are still pretty much in the old state, watch, go blind.
+--- /dev/null
++++ b/arch/mips/pci/pci-ath724x.c
+@@ -0,0 +1,174 @@
++/*
++ * Atheros 724x PCI support
++ *
++ * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
++
++#include <linux/pci.h>
++#include <asm/mach-ath79/pci-ath724x.h>
++
++#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys))
++#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
++
++#define ATH724X_PCI_DEV_BASE 0x14000000
++#define ATH724X_PCI_MEM_BASE 0x10000000
++#define ATH724X_PCI_MEM_SIZE 0x08000000
++
++static DEFINE_SPINLOCK(ath724x_pci_lock);
++static struct ath724x_pci_data *pci_data;
++static int pci_data_size;
++
++static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
++ int size, uint32_t *value)
++{
++ unsigned long flags, addr, tval, mask;
++
++ if (devfn)
++ return PCIBIOS_DEVICE_NOT_FOUND;
++
++ if (where & (size - 1))
++ return PCIBIOS_BAD_REGISTER_NUMBER;
++
++ spin_lock_irqsave(&ath724x_pci_lock, flags);
++
++ switch (size) {
++ case 1:
++ addr = where & ~3;
++ mask = 0xff000000 >> ((where % 4) * 8);
++ tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
++ tval = tval & ~mask;
++ *value = (tval >> ((4 - (where % 4))*8));
++ break;
++ case 2:
++ addr = where & ~3;
++ mask = 0xffff0000 >> ((where % 4)*8);
++ tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
++ tval = tval & ~mask;
++ *value = (tval >> ((4 - (where % 4))*8));
++ break;
++ case 4:
++ *value = reg_read(ATH724X_PCI_DEV_BASE + where);
++ break;
++ default:
++ spin_unlock_irqrestore(&ath724x_pci_lock, flags);
++
++ return PCIBIOS_BAD_REGISTER_NUMBER;
++ }
++
++ spin_unlock_irqrestore(&ath724x_pci_lock, flags);
++
++ return PCIBIOS_SUCCESSFUL;
++}
++
++static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
++ int size, uint32_t value)
++{
++ unsigned long flags, tval, addr, mask;
++
++ if (devfn)
++ return PCIBIOS_DEVICE_NOT_FOUND;
++
++ if (where & (size - 1))
++ return PCIBIOS_BAD_REGISTER_NUMBER;
++
++ spin_lock_irqsave(&ath724x_pci_lock, flags);
++
++ switch (size) {
++ case 1:
++ addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
++ mask = 0xff000000 >> ((where % 4)*8);
++ tval = reg_read(addr);
++ tval = tval & ~mask;
++ tval |= (value << ((4 - (where % 4))*8)) & mask;
++ reg_write(addr, tval);
++ break;
++ case 2:
++ addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
++ mask = 0xffff0000 >> ((where % 4)*8);
++ tval = reg_read(addr);
++ tval = tval & ~mask;
++ tval |= (value << ((4 - (where % 4))*8)) & mask;
++ reg_write(addr, tval);
++ break;
++ case 4:
++ reg_write((ATH724X_PCI_DEV_BASE + where), value);
++ break;
++ default:
++ spin_unlock_irqrestore(&ath724x_pci_lock, flags);
++
++ return PCIBIOS_BAD_REGISTER_NUMBER;
++ }
++
++ spin_unlock_irqrestore(&ath724x_pci_lock, flags);
++
++ return PCIBIOS_SUCCESSFUL;
++}
++
++static struct pci_ops ath724x_pci_ops = {
++ .read = ath724x_pci_read,
++ .write = ath724x_pci_write,
++};
++
++static struct resource ath724x_io_resource = {
++ .name = "PCI IO space",
++ .start = 0,
++ .end = 0,
++ .flags = IORESOURCE_IO,
++};
++
++static struct resource ath724x_mem_resource = {
++ .name = "PCI memory space",
++ .start = ATH724X_PCI_MEM_BASE,
++ .end = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1,
++ .flags = IORESOURCE_MEM,
++};
++
++static struct pci_controller ath724x_pci_controller = {
++ .pci_ops = &ath724x_pci_ops,
++ .io_resource = &ath724x_io_resource,
++ .mem_resource = &ath724x_mem_resource,
++};
++
++void ath724x_pci_add_data(struct ath724x_pci_data *data, int size)
++{
++ pci_data = data;
++ pci_data_size = size;
++}
++
++int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
++{
++ unsigned int devfn = dev->devfn;
++ int irq = -1;
++
++ if (devfn > pci_data_size - 1)
++ return irq;
++
++ irq = pci_data[devfn].irq;
++
++ return irq;
++}
++
++int pcibios_plat_dev_init(struct pci_dev *dev)
++{
++ unsigned int devfn = dev->devfn;
++
++ if (devfn > pci_data_size - 1)
++ return PCIBIOS_DEVICE_NOT_FOUND;
++
++ dev->dev.platform_data = pci_data[devfn].pdata;
++
++ return PCIBIOS_SUCCESSFUL;
++}
++
++static int __init ath724x_pcibios_init(void)
++{
++ register_pci_controller(&ath724x_pci_controller);
++
++ return PCIBIOS_SUCCESSFUL;
++}
++
++arch_initcall(ath724x_pcibios_init);
--- /dev/null
+From e6a1210bef8b48a946f1afb6d951f4b2448219ac Mon Sep 17 00:00:00 2001
+From: Rene Bolldorf <xsecute@googlemail.com>
+Date: Fri, 18 Nov 2011 00:17:42 +0000
+Subject: [PATCH 18/27] Initial support for the Ubiquiti Networks XM board (rev 1.0).
+
+Signed-off-by: Rene Bolldorf <xsecute@googlemail.com>
+Cc: linux-mips@linux-mips.org
+Cc: linux-kernel@vger.kernel.org
+Patchwork: https://patchwork.linux-mips.org/patch/3020/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/ath79/Kconfig | 11 ++++
+ arch/mips/ath79/Makefile | 1 +
+ arch/mips/ath79/mach-ubnt-xm.c | 119 ++++++++++++++++++++++++++++++++++++++++
+ arch/mips/ath79/machtypes.h | 1 +
+ 4 files changed, 132 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/ath79/mach-ubnt-xm.c
+
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -36,6 +36,16 @@ config ATH79_MACH_PB44
+ Say 'Y' here if you want your kernel to support the
+ Atheros PB44 reference board.
+
++config ATH79_MACH_UBNT_XM
++ bool "Ubiquiti Networks XM (rev 1.0) board"
++ select SOC_AR724X
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_SPI
++ help
++ Say 'Y' here if you want your kernel to support the
++ Ubiquiti Networks XM (rev 1.0) board.
++
+ endmenu
+
+ config SOC_AR71XX
+@@ -46,6 +56,7 @@ config SOC_AR71XX
+ config SOC_AR724X
+ select USB_ARCH_HAS_EHCI
+ select USB_ARCH_HAS_OHCI
++ select HW_HAS_PCI
+ def_bool n
+
+ config SOC_AR913X
+--- a/arch/mips/ath79/Makefile
++++ b/arch/mips/ath79/Makefile
+@@ -28,3 +28,4 @@ obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.
+ obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o
+ obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o
+ obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o
++obj-$(CONFIG_ATH79_MACH_UBNT_XM) += mach-ubnt-xm.o
+--- /dev/null
++++ b/arch/mips/ath79/mach-ubnt-xm.c
+@@ -0,0 +1,119 @@
++/*
++ * Ubiquiti Networks XM (rev 1.0) board support
++ *
++ * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
++ *
++ * Derived from: mach-pb44.c
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/pci.h>
++
++#ifdef CONFIG_PCI
++#include <linux/ath9k_platform.h>
++#include <asm/mach-ath79/pci-ath724x.h>
++#endif /* CONFIG_PCI */
++
++#include "machtypes.h"
++#include "dev-gpio-buttons.h"
++#include "dev-leds-gpio.h"
++#include "dev-spi.h"
++
++#define UBNT_XM_GPIO_LED_L1 0
++#define UBNT_XM_GPIO_LED_L2 1
++#define UBNT_XM_GPIO_LED_L3 11
++#define UBNT_XM_GPIO_LED_L4 7
++
++#define UBNT_XM_GPIO_BTN_RESET 12
++
++#define UBNT_XM_KEYS_POLL_INTERVAL 20
++#define UBNT_XM_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_XM_KEYS_POLL_INTERVAL)
++
++#define UBNT_XM_PCI_IRQ 48
++#define UBNT_XM_EEPROM_ADDR (u8 *) KSEG1ADDR(0x1fff1000)
++
++static struct gpio_led ubnt_xm_leds_gpio[] __initdata = {
++ {
++ .name = "ubnt-xm:red:link1",
++ .gpio = UBNT_XM_GPIO_LED_L1,
++ .active_low = 0,
++ }, {
++ .name = "ubnt-xm:orange:link2",
++ .gpio = UBNT_XM_GPIO_LED_L2,
++ .active_low = 0,
++ }, {
++ .name = "ubnt-xm:green:link3",
++ .gpio = UBNT_XM_GPIO_LED_L3,
++ .active_low = 0,
++ }, {
++ .name = "ubnt-xm:green:link4",
++ .gpio = UBNT_XM_GPIO_LED_L4,
++ .active_low = 0,
++ },
++};
++
++static struct gpio_keys_button ubnt_xm_gpio_keys[] __initdata = {
++ {
++ .desc = "reset",
++ .type = EV_KEY,
++ .code = KEY_RESTART,
++ .debounce_interval = UBNT_XM_KEYS_DEBOUNCE_INTERVAL,
++ .gpio = UBNT_XM_GPIO_BTN_RESET,
++ .active_low = 1,
++ }
++};
++
++static struct spi_board_info ubnt_xm_spi_info[] = {
++ {
++ .bus_num = 0,
++ .chip_select = 0,
++ .max_speed_hz = 25000000,
++ .modalias = "mx25l6405d",
++ }
++};
++
++static struct ath79_spi_platform_data ubnt_xm_spi_data = {
++ .bus_num = 0,
++ .num_chipselect = 1,
++};
++
++#ifdef CONFIG_PCI
++static struct ath9k_platform_data ubnt_xm_eeprom_data;
++
++static struct ath724x_pci_data ubnt_xm_pci_data[] = {
++ {
++ .irq = UBNT_XM_PCI_IRQ,
++ .pdata = &ubnt_xm_eeprom_data,
++ },
++};
++#endif /* CONFIG_PCI */
++
++static void __init ubnt_xm_init(void)
++{
++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio),
++ ubnt_xm_leds_gpio);
++
++ ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
++ ARRAY_SIZE(ubnt_xm_gpio_keys),
++ ubnt_xm_gpio_keys);
++
++ ath79_register_spi(&ubnt_xm_spi_data, ubnt_xm_spi_info,
++ ARRAY_SIZE(ubnt_xm_spi_info));
++
++#ifdef CONFIG_PCI
++ memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
++ sizeof(ubnt_xm_eeprom_data.eeprom_data));
++
++ ath724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data));
++#endif /* CONFIG_PCI */
++
++}
++
++MIPS_MACHINE(ATH79_MACH_UBNT_XM,
++ "UBNT-XM",
++ "Ubiquiti Networks XM (rev 1.0) board",
++ ubnt_xm_init);
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -19,6 +19,7 @@ enum ath79_mach_type {
+ ATH79_MACH_AP121, /* Atheros AP121 reference board */
+ ATH79_MACH_AP81, /* Atheros AP81 reference board */
+ ATH79_MACH_PB44, /* Atheros PB44 reference board */
++ ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */
+ };
+
+ #endif /* _ATH79_MACHTYPE_H */
--- /dev/null
+From d3cdd75072bc5df5b18dcafb45cbe9a3a62b840b Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 18 Nov 2011 00:17:46 +0000
+Subject: [PATCH 19/27] MIPS: ath79: Store the SoC revision in a global variable
+
+Knowing the exact revision of the SoC is required to make runtime decisions
+in various code paths. We have determined the SoC revision already, so we
+only need to store that in a global variable.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Cc: Imre Kaloz <kaloz@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Patchwork: https://patchwork.linux-mips.org/patch/3027/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/ath79/common.c | 1 +
+ arch/mips/ath79/setup.c | 2 ++
+ arch/mips/include/asm/mach-ath79/ath79.h | 1 +
+ 3 files changed, 4 insertions(+), 0 deletions(-)
+
+--- a/arch/mips/ath79/common.c
++++ b/arch/mips/ath79/common.c
+@@ -30,6 +30,7 @@ u32 ath79_ddr_freq;
+ EXPORT_SYMBOL_GPL(ath79_ddr_freq);
+
+ enum ath79_soc_type ath79_soc;
++unsigned int ath79_soc_rev;
+
+ void __iomem *ath79_pll_base;
+ void __iomem *ath79_reset_base;
+--- a/arch/mips/ath79/setup.c
++++ b/arch/mips/ath79/setup.c
+@@ -149,6 +149,8 @@ static void __init ath79_detect_sys_type
+ panic("ath79: unknown SoC, id:0x%08x\n", id);
+ }
+
++ ath79_soc_rev = rev;
++
+ sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
+ pr_info("SoC: %s\n", ath79_sys_type);
+ }
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
++++ b/arch/mips/include/asm/mach-ath79/ath79.h
+@@ -32,6 +32,7 @@ enum ath79_soc_type {
+ };
+
+ extern enum ath79_soc_type ath79_soc;
++extern unsigned int ath79_soc_rev;
+
+ static inline int soc_is_ar71xx(void)
+ {
--- /dev/null
+From cc2140939233382c1e58abc1d0a1b88fdd6215e6 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 18 Nov 2011 00:17:53 +0000
+Subject: [PATCH 20/27] MIPS: ath79: Remove 'ar913x' from common variable and function names
+
+The wireless MAC specific variables and the registration code can be shared
+between multiple SoCs. Remove the 'ar913x' part from the function and
+variable names to avoid confusions.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Cc: Imre Kaloz <kaloz@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Patchwork: https://patchwork.linux-mips.org/patch/3028/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/ath79/dev-ar913x-wmac.c | 20 ++++++++++----------
+ arch/mips/ath79/dev-ar913x-wmac.h | 8 ++++----
+ arch/mips/ath79/mach-ap81.c | 2 +-
+ 3 files changed, 15 insertions(+), 15 deletions(-)
+
+--- a/arch/mips/ath79/dev-ar913x-wmac.c
++++ b/arch/mips/ath79/dev-ar913x-wmac.c
+@@ -19,9 +19,9 @@
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include "dev-ar913x-wmac.h"
+
+-static struct ath9k_platform_data ar913x_wmac_data;
++static struct ath9k_platform_data ath79_wmac_data;
+
+-static struct resource ar913x_wmac_resources[] = {
++static struct resource ath79_wmac_resources[] = {
+ {
+ .start = AR913X_WMAC_BASE,
+ .end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1,
+@@ -33,21 +33,21 @@ static struct resource ar913x_wmac_resou
+ },
+ };
+
+-static struct platform_device ar913x_wmac_device = {
++static struct platform_device ath79_wmac_device = {
+ .name = "ath9k",
+ .id = -1,
+- .resource = ar913x_wmac_resources,
+- .num_resources = ARRAY_SIZE(ar913x_wmac_resources),
++ .resource = ath79_wmac_resources,
++ .num_resources = ARRAY_SIZE(ath79_wmac_resources),
+ .dev = {
+- .platform_data = &ar913x_wmac_data,
++ .platform_data = &ath79_wmac_data,
+ },
+ };
+
+-void __init ath79_register_ar913x_wmac(u8 *cal_data)
++void __init ath79_register_wmac(u8 *cal_data)
+ {
+ if (cal_data)
+- memcpy(ar913x_wmac_data.eeprom_data, cal_data,
+- sizeof(ar913x_wmac_data.eeprom_data));
++ memcpy(ath79_wmac_data.eeprom_data, cal_data,
++ sizeof(ath79_wmac_data.eeprom_data));
+
+ /* reset the WMAC */
+ ath79_device_reset_set(AR913X_RESET_AMBA2WMAC);
+@@ -56,5 +56,5 @@ void __init ath79_register_ar913x_wmac(u
+ ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC);
+ mdelay(10);
+
+- platform_device_register(&ar913x_wmac_device);
++ platform_device_register(&ath79_wmac_device);
+ }
+--- a/arch/mips/ath79/dev-ar913x-wmac.h
++++ b/arch/mips/ath79/dev-ar913x-wmac.h
+@@ -9,9 +9,9 @@
+ * by the Free Software Foundation.
+ */
+
+-#ifndef _ATH79_DEV_AR913X_WMAC_H
+-#define _ATH79_DEV_AR913X_WMAC_H
++#ifndef _ATH79_DEV_WMAC_H
++#define _ATH79_DEV_WMAC_H
+
+-void ath79_register_ar913x_wmac(u8 *cal_data);
++void ath79_register_wmac(u8 *cal_data);
+
+-#endif /* _ATH79_DEV_AR913X_WMAC_H */
++#endif /* _ATH79_DEV_WMAC_H */
+--- a/arch/mips/ath79/mach-ap81.c
++++ b/arch/mips/ath79/mach-ap81.c
+@@ -92,7 +92,7 @@ static void __init ap81_setup(void)
+ ap81_gpio_keys);
+ ath79_register_spi(&ap81_spi_data, ap81_spi_info,
+ ARRAY_SIZE(ap81_spi_info));
+- ath79_register_ar913x_wmac(cal_data);
++ ath79_register_wmac(cal_data);
+ ath79_register_usb();
+ }
+
--- /dev/null
+From 6e3f244874b8ae660136531b696ad05abe549607 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 18 Nov 2011 00:17:53 +0000
+Subject: [PATCH 21/27] MIPS: ath79: Separate AR913x SoC specific WMAC setup code
+
+The device registration code can be shared between the different SoCs, but
+the required setup code varies Move AR913x specific setup code into a
+separate function in order to make adding support for another SoCs easier.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Cc: Imre Kaloz <kaloz@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Patchwork: https://patchwork.linux-mips.org/patch/3029/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/ath79/dev-ar913x-wmac.c | 24 +++++++++++++++++-------
+ 1 files changed, 17 insertions(+), 7 deletions(-)
+
+--- a/arch/mips/ath79/dev-ar913x-wmac.c
++++ b/arch/mips/ath79/dev-ar913x-wmac.c
+@@ -23,8 +23,7 @@ static struct ath9k_platform_data ath79_
+
+ static struct resource ath79_wmac_resources[] = {
+ {
+- .start = AR913X_WMAC_BASE,
+- .end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1,
++ /* .start and .end fields are filled dynamically */
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = ATH79_CPU_IRQ_IP2,
+@@ -43,12 +42,8 @@ static struct platform_device ath79_wmac
+ },
+ };
+
+-void __init ath79_register_wmac(u8 *cal_data)
++static void __init ar913x_wmac_setup(void)
+ {
+- if (cal_data)
+- memcpy(ath79_wmac_data.eeprom_data, cal_data,
+- sizeof(ath79_wmac_data.eeprom_data));
+-
+ /* reset the WMAC */
+ ath79_device_reset_set(AR913X_RESET_AMBA2WMAC);
+ mdelay(10);
+@@ -56,5 +51,20 @@ void __init ath79_register_wmac(u8 *cal_
+ ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC);
+ mdelay(10);
+
++ ath79_wmac_resources[0].start = AR913X_WMAC_BASE;
++ ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
++}
++
++void __init ath79_register_wmac(u8 *cal_data)
++{
++ if (soc_is_ar913x())
++ ar913x_wmac_setup();
++ else
++ BUG();
++
++ if (cal_data)
++ memcpy(ath79_wmac_data.eeprom_data, cal_data,
++ sizeof(ath79_wmac_data.eeprom_data));
++
+ platform_device_register(&ath79_wmac_device);
+ }
--- /dev/null
+From e2201a02b529acc65a5a1b19a52b93f9c2d98088 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 18 Nov 2011 00:17:53 +0000
+Subject: [PATCH 22/27] MIPS: ath79: Add AR933x specific WMAC setup code
+
+The wireless MAC of the AR933x SoCs uses different base address, and
+requires different setup code.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Cc: Imre Kaloz <kaloz@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Patchwork: https://patchwork.linux-mips.org/patch/3030/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/ath79/dev-ar913x-wmac.c | 43 ++++++++++++++++++++++-
+ arch/mips/ath79/dev-ar913x-wmac.h | 4 +-
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 4 ++-
+ 3 files changed, 46 insertions(+), 5 deletions(-)
+
+--- a/arch/mips/ath79/dev-ar913x-wmac.c
++++ b/arch/mips/ath79/dev-ar913x-wmac.c
+@@ -1,7 +1,7 @@
+ /*
+- * Atheros AR913X SoC built-in WMAC device support
++ * Atheros AR913X/AR933X SoC built-in WMAC device support
+ *
+- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+@@ -55,10 +55,49 @@ static void __init ar913x_wmac_setup(voi
+ ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
+ }
+
++
++static int ar933x_wmac_reset(void)
++{
++ ath79_device_reset_clear(AR933X_RESET_WMAC);
++ ath79_device_reset_set(AR933X_RESET_WMAC);
++
++ return 0;
++}
++
++static int ar933x_r1_get_wmac_revision(void)
++{
++ return ath79_soc_rev;
++}
++
++static void __init ar933x_wmac_setup(void)
++{
++ u32 t;
++
++ ar933x_wmac_reset();
++
++ ath79_wmac_device.name = "ar933x_wmac";
++
++ ath79_wmac_resources[0].start = AR933X_WMAC_BASE;
++ ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1;
++
++ t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
++ if (t & AR933X_BOOTSTRAP_REF_CLK_40)
++ ath79_wmac_data.is_clk_25mhz = false;
++ else
++ ath79_wmac_data.is_clk_25mhz = true;
++
++ if (ath79_soc_rev == 1)
++ ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision;
++
++ ath79_wmac_data.external_reset = ar933x_wmac_reset;
++}
++
+ void __init ath79_register_wmac(u8 *cal_data)
+ {
+ if (soc_is_ar913x())
+ ar913x_wmac_setup();
++ if (soc_is_ar933x())
++ ar933x_wmac_setup();
+ else
+ BUG();
+
+--- a/arch/mips/ath79/dev-ar913x-wmac.h
++++ b/arch/mips/ath79/dev-ar913x-wmac.h
+@@ -1,7 +1,7 @@
+ /*
+- * Atheros AR913X SoC built-in WMAC device support
++ * Atheros AR913X/AR933X SoC built-in WMAC device support
+ *
+- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -55,7 +55,8 @@
+
+ #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
+ #define AR933X_UART_SIZE 0x14
+-
++#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
++#define AR933X_WMAC_SIZE 0x20000
+ #define AR933X_EHCI_BASE 0x1b000000
+ #define AR933X_EHCI_SIZE 0x1000
+
+@@ -233,6 +234,7 @@
+ #define AR913X_RESET_USB_HOST BIT(5)
+ #define AR913X_RESET_USB_PHY BIT(4)
+
++#define AR933X_RESET_WMAC BIT(11)
+ #define AR933X_RESET_USB_HOST BIT(5)
+ #define AR933X_RESET_USB_PHY BIT(4)
+ #define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
--- /dev/null
+From b784c5ab6423d0327d34d08e3532a16a4563e845 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 18 Nov 2011 00:17:54 +0000
+Subject: [PATCH 23/27] MIPS: ath79: Rename ATH79_DEV_AR913X_WMAC option to ATH79_DEV_WMAC
+
+The ATH79_DEV_AR913X_WMAC option was used to select the AR913x specific
+wireless MAC registration code. The registration code now supports the
+AR933X SoCs as well. Rename the option to reflect the changes.
+
+Also make the new option depends on SOC_AR933X.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Cc: Imre Kaloz <kaloz@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Patchwork: https://patchwork.linux-mips.org/patch/3031/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/ath79/Kconfig | 11 ++++++-----
+ arch/mips/ath79/Makefile | 2 +-
+ 2 files changed, 7 insertions(+), 6 deletions(-)
+
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -9,6 +9,7 @@ config ATH79_MACH_AP121
+ select ATH79_DEV_LEDS_GPIO
+ select ATH79_DEV_SPI
+ select ATH79_DEV_USB
++ select ATH79_DEV_WMAC
+ help
+ Say 'Y' here if you want your kernel to support the
+ Atheros AP121 reference board.
+@@ -16,11 +17,11 @@ config ATH79_MACH_AP121
+ config ATH79_MACH_AP81
+ bool "Atheros AP81 reference board"
+ select SOC_AR913X
+- select ATH79_DEV_AR913X_WMAC
+ select ATH79_DEV_GPIO_BUTTONS
+ select ATH79_DEV_LEDS_GPIO
+ select ATH79_DEV_SPI
+ select ATH79_DEV_USB
++ select ATH79_DEV_WMAC
+ help
+ Say 'Y' here if you want your kernel to support the
+ Atheros AP81 reference board.
+@@ -67,10 +68,6 @@ config SOC_AR933X
+ select USB_ARCH_HAS_EHCI
+ def_bool n
+
+-config ATH79_DEV_AR913X_WMAC
+- depends on SOC_AR913X
+- def_bool n
+-
+ config ATH79_DEV_GPIO_BUTTONS
+ def_bool n
+
+@@ -83,4 +80,8 @@ config ATH79_DEV_SPI
+ config ATH79_DEV_USB
+ def_bool n
+
++config ATH79_DEV_WMAC
++ depends on (SOC_AR913X || SOC_AR933X)
++ def_bool n
++
+ endif
+--- a/arch/mips/ath79/Makefile
++++ b/arch/mips/ath79/Makefile
+@@ -16,11 +16,11 @@ obj-$(CONFIG_EARLY_PRINTK) += early_pri
+ # Devices
+ #
+ obj-y += dev-common.o
+-obj-$(CONFIG_ATH79_DEV_AR913X_WMAC) += dev-ar913x-wmac.o
+ obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o
+ obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o
+ obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o
+ obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o
++obj-$(CONFIG_ATH79_DEV_WMAC) += dev-ar913x-wmac.o
+
+ #
+ # Machines
--- /dev/null
+From 7091af5ca0aad47826a4e3f699a7985e2d8aa886 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 18 Nov 2011 00:17:54 +0000
+Subject: [PATCH 24/27] MIPS: ath79: Register the wireless MAC device on the AP121 board
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Cc: Imre Kaloz <kaloz@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Patchwork: https://patchwork.linux-mips.org/patch/3032/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/ath79/mach-ap121.c | 4 ++++
+ 1 files changed, 4 insertions(+), 0 deletions(-)
+
+--- a/arch/mips/ath79/mach-ap121.c
++++ b/arch/mips/ath79/mach-ap121.c
+@@ -13,6 +13,7 @@
+ #include "dev-leds-gpio.h"
+ #include "dev-spi.h"
+ #include "dev-usb.h"
++#include "dev-ar913x-wmac.h"
+
+ #define AP121_GPIO_LED_WLAN 0
+ #define AP121_GPIO_LED_USB 1
+@@ -73,6 +74,8 @@ static struct ath79_spi_platform_data ap
+
+ static void __init ap121_setup(void)
+ {
++ u8 *cal_data = (u8 *) KSEG1ADDR(AP121_CAL_DATA_ADDR);
++
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_leds_gpio),
+ ap121_leds_gpio);
+ ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL,
+@@ -82,6 +85,7 @@ static void __init ap121_setup(void)
+ ath79_register_spi(&ap121_spi_data, ap121_spi_info,
+ ARRAY_SIZE(ap121_spi_info));
+ ath79_register_usb();
++ ath79_register_wmac(cal_data);
+ }
+
+ MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board",
--- /dev/null
+From ece52fe72b70e35f72edf940233d125257a5f4bc Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 18 Nov 2011 00:17:54 +0000
+Subject: [PATCH 25/27] MIPS: ath79: Rename dev-ar913x-wmac.h to dev-wmac.h
+
+The 'ar913x' part was removed from the common variable and function names,
+so remove that from the relevant header file name as well.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Cc: Imre Kaloz <kaloz@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Patchwork: https://patchwork.linux-mips.org/patch/3033/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/ath79/dev-ar913x-wmac.c | 2 +-
+ arch/mips/ath79/dev-ar913x-wmac.h | 17 -----------------
+ arch/mips/ath79/dev-wmac.h | 17 +++++++++++++++++
+ arch/mips/ath79/mach-ap121.c | 2 +-
+ arch/mips/ath79/mach-ap81.c | 2 +-
+ 5 files changed, 20 insertions(+), 20 deletions(-)
+ delete mode 100644 arch/mips/ath79/dev-ar913x-wmac.h
+ create mode 100644 arch/mips/ath79/dev-wmac.h
+
+--- a/arch/mips/ath79/dev-ar913x-wmac.c
++++ b/arch/mips/ath79/dev-ar913x-wmac.c
+@@ -17,7 +17,7 @@
+
+ #include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/ar71xx_regs.h>
+-#include "dev-ar913x-wmac.h"
++#include "dev-wmac.h"
+
+ static struct ath9k_platform_data ath79_wmac_data;
+
+--- a/arch/mips/ath79/dev-ar913x-wmac.h
++++ /dev/null
+@@ -1,17 +0,0 @@
+-/*
+- * Atheros AR913X/AR933X SoC built-in WMAC device support
+- *
+- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published
+- * by the Free Software Foundation.
+- */
+-
+-#ifndef _ATH79_DEV_WMAC_H
+-#define _ATH79_DEV_WMAC_H
+-
+-void ath79_register_wmac(u8 *cal_data);
+-
+-#endif /* _ATH79_DEV_WMAC_H */
+--- /dev/null
++++ b/arch/mips/ath79/dev-wmac.h
+@@ -0,0 +1,17 @@
++/*
++ * Atheros AR913X/AR933X SoC built-in WMAC device support
++ *
++ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
++
++#ifndef _ATH79_DEV_WMAC_H
++#define _ATH79_DEV_WMAC_H
++
++void ath79_register_wmac(u8 *cal_data);
++
++#endif /* _ATH79_DEV_WMAC_H */
+--- a/arch/mips/ath79/mach-ap121.c
++++ b/arch/mips/ath79/mach-ap121.c
+@@ -13,7 +13,7 @@
+ #include "dev-leds-gpio.h"
+ #include "dev-spi.h"
+ #include "dev-usb.h"
+-#include "dev-ar913x-wmac.h"
++#include "dev-wmac.h"
+
+ #define AP121_GPIO_LED_WLAN 0
+ #define AP121_GPIO_LED_USB 1
+--- a/arch/mips/ath79/mach-ap81.c
++++ b/arch/mips/ath79/mach-ap81.c
+@@ -10,7 +10,7 @@
+ */
+
+ #include "machtypes.h"
+-#include "dev-ar913x-wmac.h"
++#include "dev-wmac.h"
+ #include "dev-gpio-buttons.h"
+ #include "dev-leds-gpio.h"
+ #include "dev-spi.h"
--- /dev/null
+From c1999a36c113e583f785728b3d8f7a26412c61cd Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 18 Nov 2011 00:17:54 +0000
+Subject: [PATCH 26/27] MIPS: ath79: Rename dev-ar913x-wmac.c to dev-wmac.c
+
+Rename the file as a last step of the 'ar913x' removal changes.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Cc: Imre Kaloz <kaloz@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Patchwork: https://patchwork.linux-mips.org/patch/3034/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/ath79/Makefile | 2 +-
+ arch/mips/ath79/dev-ar913x-wmac.c | 109 -------------------------------------
+ arch/mips/ath79/dev-wmac.c | 109 +++++++++++++++++++++++++++++++++++++
+ 3 files changed, 110 insertions(+), 110 deletions(-)
+ delete mode 100644 arch/mips/ath79/dev-ar913x-wmac.c
+ create mode 100644 arch/mips/ath79/dev-wmac.c
+
+--- a/arch/mips/ath79/Makefile
++++ b/arch/mips/ath79/Makefile
+@@ -20,7 +20,7 @@ obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) +=
+ obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o
+ obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o
+ obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o
+-obj-$(CONFIG_ATH79_DEV_WMAC) += dev-ar913x-wmac.o
++obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wmac.o
+
+ #
+ # Machines
+--- a/arch/mips/ath79/dev-ar913x-wmac.c
++++ /dev/null
+@@ -1,109 +0,0 @@
+-/*
+- * Atheros AR913X/AR933X SoC built-in WMAC device support
+- *
+- * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published
+- * by the Free Software Foundation.
+- */
+-
+-#include <linux/init.h>
+-#include <linux/delay.h>
+-#include <linux/irq.h>
+-#include <linux/platform_device.h>
+-#include <linux/ath9k_platform.h>
+-
+-#include <asm/mach-ath79/ath79.h>
+-#include <asm/mach-ath79/ar71xx_regs.h>
+-#include "dev-wmac.h"
+-
+-static struct ath9k_platform_data ath79_wmac_data;
+-
+-static struct resource ath79_wmac_resources[] = {
+- {
+- /* .start and .end fields are filled dynamically */
+- .flags = IORESOURCE_MEM,
+- }, {
+- .start = ATH79_CPU_IRQ_IP2,
+- .end = ATH79_CPU_IRQ_IP2,
+- .flags = IORESOURCE_IRQ,
+- },
+-};
+-
+-static struct platform_device ath79_wmac_device = {
+- .name = "ath9k",
+- .id = -1,
+- .resource = ath79_wmac_resources,
+- .num_resources = ARRAY_SIZE(ath79_wmac_resources),
+- .dev = {
+- .platform_data = &ath79_wmac_data,
+- },
+-};
+-
+-static void __init ar913x_wmac_setup(void)
+-{
+- /* reset the WMAC */
+- ath79_device_reset_set(AR913X_RESET_AMBA2WMAC);
+- mdelay(10);
+-
+- ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC);
+- mdelay(10);
+-
+- ath79_wmac_resources[0].start = AR913X_WMAC_BASE;
+- ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
+-}
+-
+-
+-static int ar933x_wmac_reset(void)
+-{
+- ath79_device_reset_clear(AR933X_RESET_WMAC);
+- ath79_device_reset_set(AR933X_RESET_WMAC);
+-
+- return 0;
+-}
+-
+-static int ar933x_r1_get_wmac_revision(void)
+-{
+- return ath79_soc_rev;
+-}
+-
+-static void __init ar933x_wmac_setup(void)
+-{
+- u32 t;
+-
+- ar933x_wmac_reset();
+-
+- ath79_wmac_device.name = "ar933x_wmac";
+-
+- ath79_wmac_resources[0].start = AR933X_WMAC_BASE;
+- ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1;
+-
+- t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
+- if (t & AR933X_BOOTSTRAP_REF_CLK_40)
+- ath79_wmac_data.is_clk_25mhz = false;
+- else
+- ath79_wmac_data.is_clk_25mhz = true;
+-
+- if (ath79_soc_rev == 1)
+- ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision;
+-
+- ath79_wmac_data.external_reset = ar933x_wmac_reset;
+-}
+-
+-void __init ath79_register_wmac(u8 *cal_data)
+-{
+- if (soc_is_ar913x())
+- ar913x_wmac_setup();
+- if (soc_is_ar933x())
+- ar933x_wmac_setup();
+- else
+- BUG();
+-
+- if (cal_data)
+- memcpy(ath79_wmac_data.eeprom_data, cal_data,
+- sizeof(ath79_wmac_data.eeprom_data));
+-
+- platform_device_register(&ath79_wmac_device);
+-}
+--- /dev/null
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -0,0 +1,109 @@
++/*
++ * Atheros AR913X/AR933X SoC built-in WMAC device support
++ *
++ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/irq.h>
++#include <linux/platform_device.h>
++#include <linux/ath9k_platform.h>
++
++#include <asm/mach-ath79/ath79.h>
++#include <asm/mach-ath79/ar71xx_regs.h>
++#include "dev-wmac.h"
++
++static struct ath9k_platform_data ath79_wmac_data;
++
++static struct resource ath79_wmac_resources[] = {
++ {
++ /* .start and .end fields are filled dynamically */
++ .flags = IORESOURCE_MEM,
++ }, {
++ .start = ATH79_CPU_IRQ_IP2,
++ .end = ATH79_CPU_IRQ_IP2,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct platform_device ath79_wmac_device = {
++ .name = "ath9k",
++ .id = -1,
++ .resource = ath79_wmac_resources,
++ .num_resources = ARRAY_SIZE(ath79_wmac_resources),
++ .dev = {
++ .platform_data = &ath79_wmac_data,
++ },
++};
++
++static void __init ar913x_wmac_setup(void)
++{
++ /* reset the WMAC */
++ ath79_device_reset_set(AR913X_RESET_AMBA2WMAC);
++ mdelay(10);
++
++ ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC);
++ mdelay(10);
++
++ ath79_wmac_resources[0].start = AR913X_WMAC_BASE;
++ ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
++}
++
++
++static int ar933x_wmac_reset(void)
++{
++ ath79_device_reset_clear(AR933X_RESET_WMAC);
++ ath79_device_reset_set(AR933X_RESET_WMAC);
++
++ return 0;
++}
++
++static int ar933x_r1_get_wmac_revision(void)
++{
++ return ath79_soc_rev;
++}
++
++static void __init ar933x_wmac_setup(void)
++{
++ u32 t;
++
++ ar933x_wmac_reset();
++
++ ath79_wmac_device.name = "ar933x_wmac";
++
++ ath79_wmac_resources[0].start = AR933X_WMAC_BASE;
++ ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1;
++
++ t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
++ if (t & AR933X_BOOTSTRAP_REF_CLK_40)
++ ath79_wmac_data.is_clk_25mhz = false;
++ else
++ ath79_wmac_data.is_clk_25mhz = true;
++
++ if (ath79_soc_rev == 1)
++ ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision;
++
++ ath79_wmac_data.external_reset = ar933x_wmac_reset;
++}
++
++void __init ath79_register_wmac(u8 *cal_data)
++{
++ if (soc_is_ar913x())
++ ar913x_wmac_setup();
++ if (soc_is_ar933x())
++ ar933x_wmac_setup();
++ else
++ BUG();
++
++ if (cal_data)
++ memcpy(ath79_wmac_data.eeprom_data, cal_data,
++ sizeof(ath79_wmac_data.eeprom_data));
++
++ platform_device_register(&ath79_wmac_device);
++}
--- /dev/null
+From 156560a512a39284148d556ab96e2e833e816666 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 23 Dec 2011 19:25:42 +0100
+Subject: [PATCH 27/27] watchdog: ath79_wdt: flush register writes
+
+The watchdog register writes required to have a flush
+in order to commit the values to the register. Without
+the flush, the driver not function correctly on AR934X
+SoCs.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
+---
+ drivers/watchdog/ath79_wdt.c | 6 ++++++
+ 1 files changed, 6 insertions(+), 0 deletions(-)
+
+--- a/drivers/watchdog/ath79_wdt.c
++++ b/drivers/watchdog/ath79_wdt.c
+@@ -68,17 +68,23 @@ static int max_timeout;
+ static inline void ath79_wdt_keepalive(void)
+ {
+ ath79_reset_wr(AR71XX_RESET_REG_WDOG, wdt_freq * timeout);
++ /* flush write */
++ ath79_reset_rr(AR71XX_RESET_REG_WDOG);
+ }
+
+ static inline void ath79_wdt_enable(void)
+ {
+ ath79_wdt_keepalive();
+ ath79_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_FCR);
++ /* flush write */
++ ath79_reset_rr(AR71XX_RESET_REG_WDOG_CTRL);
+ }
+
+ static inline void ath79_wdt_disable(void)
+ {
+ ath79_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_NONE);
++ /* flush write */
++ ath79_reset_rr(AR71XX_RESET_REG_WDOG_CTRL);
+ }
+
+ static int ath79_wdt_set_timeout(int val)
--- /dev/null
+From cf6855546330c3d349d41496975f32255bb6fd07 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 9 Dec 2011 22:02:57 +0100
+Subject: [PATCH 01/35] MIPS: ath79: avoid a kernel bug on AR913X
+
+Wireless mac registration causes a BUG on AR913X SoCs due to
+a missing 'else'.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ arch/mips/ath79/dev-wmac.c | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -96,7 +96,7 @@ void __init ath79_register_wmac(u8 *cal_
+ {
+ if (soc_is_ar913x())
+ ar913x_wmac_setup();
+- if (soc_is_ar933x())
++ else if (soc_is_ar933x())
+ ar933x_wmac_setup();
+ else
+ BUG();
--- /dev/null
+From c98b48027516a2e71688a5957e4e0120f4aa8c61 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 18 Nov 2011 09:47:44 +0100
+Subject: [PATCH 02/35] MIPS: ath79: separate common PCI code
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The 'pcibios_map_irq' and 'pcibios_plat_dev_init'
+are common functions and only instance one of them
+can be present in a single kernel.
+
+Currently these functions can be built only if the
+CONFIG_SOC_AR724X option is selected. However the
+ath79 platform contain support for the AR71XX SoCs,.
+The AR71XX SoCs have a differnet PCI controller,
+and those will require a different code.
+
+Move the common PCI code into a separeate file in
+order to be able to use that with other SoCs as
+well.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: René Bolldorf <xsecute@googlemail.com>
+
+v4: - add an Acked-by tag from René
+v3: - no changes
+v2: - no changes
+---
+ arch/mips/ath79/Makefile | 1 +
+ arch/mips/ath79/pci.c | 46 +++++++++++++++++++++++++++++++++++++++++++
+ arch/mips/pci/pci-ath724x.c | 34 -------------------------------
+ 3 files changed, 47 insertions(+), 34 deletions(-)
+ create mode 100644 arch/mips/ath79/pci.c
+
+--- a/arch/mips/ath79/Makefile
++++ b/arch/mips/ath79/Makefile
+@@ -11,6 +11,7 @@
+ obj-y := prom.o setup.o irq.o common.o clock.o gpio.o
+
+ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
++obj-$(CONFIG_PCI) += pci.o
+
+ #
+ # Devices
+--- /dev/null
++++ b/arch/mips/ath79/pci.c
+@@ -0,0 +1,46 @@
++/*
++ * Atheros AR71XX/AR724X specific PCI setup code
++ *
++ * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
++
++#include <linux/pci.h>
++#include <asm/mach-ath79/pci-ath724x.h>
++
++static struct ath724x_pci_data *pci_data;
++static int pci_data_size;
++
++void ath724x_pci_add_data(struct ath724x_pci_data *data, int size)
++{
++ pci_data = data;
++ pci_data_size = size;
++}
++
++int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
++{
++ unsigned int devfn = dev->devfn;
++ int irq = -1;
++
++ if (devfn > pci_data_size - 1)
++ return irq;
++
++ irq = pci_data[devfn].irq;
++
++ return irq;
++}
++
++int pcibios_plat_dev_init(struct pci_dev *dev)
++{
++ unsigned int devfn = dev->devfn;
++
++ if (devfn > pci_data_size - 1)
++ return PCIBIOS_DEVICE_NOT_FOUND;
++
++ dev->dev.platform_data = pci_data[devfn].pdata;
++
++ return PCIBIOS_SUCCESSFUL;
++}
+--- a/arch/mips/pci/pci-ath724x.c
++++ b/arch/mips/pci/pci-ath724x.c
+@@ -9,7 +9,6 @@
+ */
+
+ #include <linux/pci.h>
+-#include <asm/mach-ath79/pci-ath724x.h>
+
+ #define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys))
+ #define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
+@@ -19,8 +18,6 @@
+ #define ATH724X_PCI_MEM_SIZE 0x08000000
+
+ static DEFINE_SPINLOCK(ath724x_pci_lock);
+-static struct ath724x_pci_data *pci_data;
+-static int pci_data_size;
+
+ static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
+ int size, uint32_t *value)
+@@ -133,37 +130,6 @@ static struct pci_controller ath724x_pci
+ .mem_resource = &ath724x_mem_resource,
+ };
+
+-void ath724x_pci_add_data(struct ath724x_pci_data *data, int size)
+-{
+- pci_data = data;
+- pci_data_size = size;
+-}
+-
+-int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
+-{
+- unsigned int devfn = dev->devfn;
+- int irq = -1;
+-
+- if (devfn > pci_data_size - 1)
+- return irq;
+-
+- irq = pci_data[devfn].irq;
+-
+- return irq;
+-}
+-
+-int pcibios_plat_dev_init(struct pci_dev *dev)
+-{
+- unsigned int devfn = dev->devfn;
+-
+- if (devfn > pci_data_size - 1)
+- return PCIBIOS_DEVICE_NOT_FOUND;
+-
+- dev->dev.platform_data = pci_data[devfn].pdata;
+-
+- return PCIBIOS_SUCCESSFUL;
+-}
+-
+ static int __init ath724x_pcibios_init(void)
+ {
+ register_pci_controller(&ath724x_pci_controller);
--- /dev/null
+From 204fd70abd99099f6c2e2213a2baa1d51c03a039 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 18 Nov 2011 09:50:50 +0100
+Subject: [PATCH 03/35] MIPS: ath79: rename pci-ath724x.h
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The declared function in this header file is used by the
+ath79 platform code only. Move the header to the platform
+directory.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: René Bolldorf <xsecute@googlemail.com>
+
+v4: - add an Acked-by tag from René
+v3: - move include "pci.h" out of the #ifdef CONFIG_PCI section
+v2: - no changes
+---
+ arch/mips/ath79/mach-ubnt-xm.c | 2 +-
+ arch/mips/ath79/pci.c | 2 +-
+ arch/mips/ath79/pci.h | 21 +++++++++++++++++++++
+ arch/mips/include/asm/mach-ath79/pci-ath724x.h | 21 ---------------------
+ 4 files changed, 23 insertions(+), 23 deletions(-)
+ create mode 100644 arch/mips/ath79/pci.h
+ delete mode 100644 arch/mips/include/asm/mach-ath79/pci-ath724x.h
+
+--- a/arch/mips/ath79/mach-ubnt-xm.c
++++ b/arch/mips/ath79/mach-ubnt-xm.c
+@@ -15,13 +15,13 @@
+
+ #ifdef CONFIG_PCI
+ #include <linux/ath9k_platform.h>
+-#include <asm/mach-ath79/pci-ath724x.h>
+ #endif /* CONFIG_PCI */
+
+ #include "machtypes.h"
+ #include "dev-gpio-buttons.h"
+ #include "dev-leds-gpio.h"
+ #include "dev-spi.h"
++#include "pci.h"
+
+ #define UBNT_XM_GPIO_LED_L1 0
+ #define UBNT_XM_GPIO_LED_L2 1
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -9,7 +9,7 @@
+ */
+
+ #include <linux/pci.h>
+-#include <asm/mach-ath79/pci-ath724x.h>
++#include "pci.h"
+
+ static struct ath724x_pci_data *pci_data;
+ static int pci_data_size;
+--- /dev/null
++++ b/arch/mips/ath79/pci.h
+@@ -0,0 +1,21 @@
++/*
++ * Atheros 724x PCI support
++ *
++ * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
++
++#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H
++#define __ASM_MACH_ATH79_PCI_ATH724X_H
++
++struct ath724x_pci_data {
++ int irq;
++ void *pdata;
++};
++
++void ath724x_pci_add_data(struct ath724x_pci_data *data, int size);
++
++#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */
+--- a/arch/mips/include/asm/mach-ath79/pci-ath724x.h
++++ /dev/null
+@@ -1,21 +0,0 @@
+-/*
+- * Atheros 724x PCI support
+- *
+- * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published
+- * by the Free Software Foundation.
+- */
+-
+-#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H
+-#define __ASM_MACH_ATH79_PCI_ATH724X_H
+-
+-struct ath724x_pci_data {
+- int irq;
+- void *pdata;
+-};
+-
+-void ath724x_pci_add_data(struct ath724x_pci_data *data, int size);
+-
+-#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */
--- /dev/null
+From 7e59b95e3424c078de0d75d699433da0dd289fc1 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 18 Nov 2011 10:13:37 +0100
+Subject: [PATCH 04/35] MIPS: ath79: make ath724x_pcibios_init visible for external code
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: René Bolldorf <xsecute@googlemail.com>
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+
+v4: - add a sob tag
+v3: - no changes
+v2: - fix a typo in my e-mail address
+---
+ arch/mips/include/asm/mach-ath79/pci.h | 20 ++++++++++++++++++++
+ arch/mips/pci/pci-ath724x.c | 3 ++-
+ 2 files changed, 22 insertions(+), 1 deletions(-)
+ create mode 100644 arch/mips/include/asm/mach-ath79/pci.h
+
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ath79/pci.h
+@@ -0,0 +1,20 @@
++/*
++ * Atheros 724x PCI support
++ *
++ * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
++
++#ifndef __ASM_MACH_ATH79_PCI_H
++#define __ASM_MACH_ATH79_PCI_H
++
++#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X)
++int ath724x_pcibios_init(void);
++#else
++static inline int ath724x_pcibios_init(void) { return 0 };
++#endif
++
++#endif /* __ASM_MACH_ATH79_PCI_H */
+--- a/arch/mips/pci/pci-ath724x.c
++++ b/arch/mips/pci/pci-ath724x.c
+@@ -9,6 +9,7 @@
+ */
+
+ #include <linux/pci.h>
++#include <asm/mach-ath79/pci.h>
+
+ #define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys))
+ #define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
+@@ -130,7 +131,7 @@ static struct pci_controller ath724x_pci
+ .mem_resource = &ath724x_mem_resource,
+ };
+
+-static int __init ath724x_pcibios_init(void)
++int __init ath724x_pcibios_init(void)
+ {
+ register_pci_controller(&ath724x_pci_controller);
+
--- /dev/null
+From fbf38a9b03d0c47ed602f090ebb2d8ecc0d51d04 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 18 Nov 2011 10:25:26 +0100
+Subject: [PATCH 05/35] MIPS: ath79: add a common PCI registration function
+
+The current code unconditionally registers the AR724X
+specific PCI controller, even if the kernel is running
+on a different SoC.
+
+Add a common function for PCI controller registration,
+and only register the AR724X PCI controller if the kernel
+is running on an AR724X SoC.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+
+v4: - simplify ath79_register_pci function
+v3: - fix compile error if CONFIG_PCI is not defined
+ - add __init annotation to ath79_register_pci
+v2: - no changes
+---
+ arch/mips/ath79/mach-ubnt-xm.c | 1 +
+ arch/mips/ath79/pci.c | 10 ++++++++++
+ arch/mips/ath79/pci.h | 6 ++++++
+ arch/mips/pci/pci-ath724x.c | 2 --
+ 4 files changed, 17 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/ath79/mach-ubnt-xm.c
++++ b/arch/mips/ath79/mach-ubnt-xm.c
+@@ -111,6 +111,7 @@ static void __init ubnt_xm_init(void)
+ ath724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data));
+ #endif /* CONFIG_PCI */
+
++ ath79_register_pci();
+ }
+
+ MIPS_MACHINE(ATH79_MACH_UBNT_XM,
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -9,6 +9,8 @@
+ */
+
+ #include <linux/pci.h>
++#include <asm/mach-ath79/ath79.h>
++#include <asm/mach-ath79/pci.h>
+ #include "pci.h"
+
+ static struct ath724x_pci_data *pci_data;
+@@ -44,3 +46,11 @@ int pcibios_plat_dev_init(struct pci_dev
+
+ return PCIBIOS_SUCCESSFUL;
+ }
++
++int __init ath79_register_pci(void)
++{
++ if (soc_is_ar724x())
++ return ath724x_pcibios_init();
++
++ return -ENODEV;
++}
+--- a/arch/mips/ath79/pci.h
++++ b/arch/mips/ath79/pci.h
+@@ -18,4 +18,10 @@ struct ath724x_pci_data {
+
+ void ath724x_pci_add_data(struct ath724x_pci_data *data, int size);
+
++#ifdef CONFIG_PCI
++int ath79_register_pci(void);
++#else
++static inline int ath79_register_pci(void) { return 0; }
++#endif
++
+ #endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */
+--- a/arch/mips/pci/pci-ath724x.c
++++ b/arch/mips/pci/pci-ath724x.c
+@@ -137,5 +137,3 @@ int __init ath724x_pcibios_init(void)
+
+ return PCIBIOS_SUCCESSFUL;
+ }
+-
+-arch_initcall(ath724x_pcibios_init);
--- /dev/null
+From 9510a9988638ae2386277a832fab2df8ca37d75a Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 18 Nov 2011 11:07:26 +0100
+Subject: [PATCH 06/35] MIPS: ath79: rename pci-ath724x.c to make it reflect the real SoC name
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: René Bolldorf <xsecute@googlemail.com>
+
+v4: - add an Acked-by tag from René
+v4: - no changes
+v3: - no changes
+v2: - no changes
+---
+ arch/mips/pci/Makefile | 2 +-
+ arch/mips/pci/pci-ar724x.c | 139 +++++++++++++++++++++++++++++++++++++++++++
+ arch/mips/pci/pci-ath724x.c | 139 -------------------------------------------
+ 3 files changed, 140 insertions(+), 140 deletions(-)
+ create mode 100644 arch/mips/pci/pci-ar724x.c
+ delete mode 100644 arch/mips/pci/pci-ath724x.c
+
+--- a/arch/mips/pci/Makefile
++++ b/arch/mips/pci/Makefile
+@@ -19,7 +19,7 @@ obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
+ obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
+ ops-bcm63xx.o
+ obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
+-obj-$(CONFIG_SOC_AR724X) += pci-ath724x.o
++obj-$(CONFIG_SOC_AR724X) += pci-ar724x.o
+
+ #
+ # These are still pretty much in the old state, watch, go blind.
+--- /dev/null
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -0,0 +1,139 @@
++/*
++ * Atheros 724x PCI support
++ *
++ * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
++
++#include <linux/pci.h>
++#include <asm/mach-ath79/pci.h>
++
++#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys))
++#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
++
++#define ATH724X_PCI_DEV_BASE 0x14000000
++#define ATH724X_PCI_MEM_BASE 0x10000000
++#define ATH724X_PCI_MEM_SIZE 0x08000000
++
++static DEFINE_SPINLOCK(ath724x_pci_lock);
++
++static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
++ int size, uint32_t *value)
++{
++ unsigned long flags, addr, tval, mask;
++
++ if (devfn)
++ return PCIBIOS_DEVICE_NOT_FOUND;
++
++ if (where & (size - 1))
++ return PCIBIOS_BAD_REGISTER_NUMBER;
++
++ spin_lock_irqsave(&ath724x_pci_lock, flags);
++
++ switch (size) {
++ case 1:
++ addr = where & ~3;
++ mask = 0xff000000 >> ((where % 4) * 8);
++ tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
++ tval = tval & ~mask;
++ *value = (tval >> ((4 - (where % 4))*8));
++ break;
++ case 2:
++ addr = where & ~3;
++ mask = 0xffff0000 >> ((where % 4)*8);
++ tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
++ tval = tval & ~mask;
++ *value = (tval >> ((4 - (where % 4))*8));
++ break;
++ case 4:
++ *value = reg_read(ATH724X_PCI_DEV_BASE + where);
++ break;
++ default:
++ spin_unlock_irqrestore(&ath724x_pci_lock, flags);
++
++ return PCIBIOS_BAD_REGISTER_NUMBER;
++ }
++
++ spin_unlock_irqrestore(&ath724x_pci_lock, flags);
++
++ return PCIBIOS_SUCCESSFUL;
++}
++
++static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
++ int size, uint32_t value)
++{
++ unsigned long flags, tval, addr, mask;
++
++ if (devfn)
++ return PCIBIOS_DEVICE_NOT_FOUND;
++
++ if (where & (size - 1))
++ return PCIBIOS_BAD_REGISTER_NUMBER;
++
++ spin_lock_irqsave(&ath724x_pci_lock, flags);
++
++ switch (size) {
++ case 1:
++ addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
++ mask = 0xff000000 >> ((where % 4)*8);
++ tval = reg_read(addr);
++ tval = tval & ~mask;
++ tval |= (value << ((4 - (where % 4))*8)) & mask;
++ reg_write(addr, tval);
++ break;
++ case 2:
++ addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
++ mask = 0xffff0000 >> ((where % 4)*8);
++ tval = reg_read(addr);
++ tval = tval & ~mask;
++ tval |= (value << ((4 - (where % 4))*8)) & mask;
++ reg_write(addr, tval);
++ break;
++ case 4:
++ reg_write((ATH724X_PCI_DEV_BASE + where), value);
++ break;
++ default:
++ spin_unlock_irqrestore(&ath724x_pci_lock, flags);
++
++ return PCIBIOS_BAD_REGISTER_NUMBER;
++ }
++
++ spin_unlock_irqrestore(&ath724x_pci_lock, flags);
++
++ return PCIBIOS_SUCCESSFUL;
++}
++
++static struct pci_ops ath724x_pci_ops = {
++ .read = ath724x_pci_read,
++ .write = ath724x_pci_write,
++};
++
++static struct resource ath724x_io_resource = {
++ .name = "PCI IO space",
++ .start = 0,
++ .end = 0,
++ .flags = IORESOURCE_IO,
++};
++
++static struct resource ath724x_mem_resource = {
++ .name = "PCI memory space",
++ .start = ATH724X_PCI_MEM_BASE,
++ .end = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1,
++ .flags = IORESOURCE_MEM,
++};
++
++static struct pci_controller ath724x_pci_controller = {
++ .pci_ops = &ath724x_pci_ops,
++ .io_resource = &ath724x_io_resource,
++ .mem_resource = &ath724x_mem_resource,
++};
++
++int __init ath724x_pcibios_init(void)
++{
++ register_pci_controller(&ath724x_pci_controller);
++
++ return PCIBIOS_SUCCESSFUL;
++}
+--- a/arch/mips/pci/pci-ath724x.c
++++ /dev/null
+@@ -1,139 +0,0 @@
+-/*
+- * Atheros 724x PCI support
+- *
+- * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published
+- * by the Free Software Foundation.
+- */
+-
+-#include <linux/pci.h>
+-#include <asm/mach-ath79/pci.h>
+-
+-#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys))
+-#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
+-
+-#define ATH724X_PCI_DEV_BASE 0x14000000
+-#define ATH724X_PCI_MEM_BASE 0x10000000
+-#define ATH724X_PCI_MEM_SIZE 0x08000000
+-
+-static DEFINE_SPINLOCK(ath724x_pci_lock);
+-
+-static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
+- int size, uint32_t *value)
+-{
+- unsigned long flags, addr, tval, mask;
+-
+- if (devfn)
+- return PCIBIOS_DEVICE_NOT_FOUND;
+-
+- if (where & (size - 1))
+- return PCIBIOS_BAD_REGISTER_NUMBER;
+-
+- spin_lock_irqsave(&ath724x_pci_lock, flags);
+-
+- switch (size) {
+- case 1:
+- addr = where & ~3;
+- mask = 0xff000000 >> ((where % 4) * 8);
+- tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
+- tval = tval & ~mask;
+- *value = (tval >> ((4 - (where % 4))*8));
+- break;
+- case 2:
+- addr = where & ~3;
+- mask = 0xffff0000 >> ((where % 4)*8);
+- tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
+- tval = tval & ~mask;
+- *value = (tval >> ((4 - (where % 4))*8));
+- break;
+- case 4:
+- *value = reg_read(ATH724X_PCI_DEV_BASE + where);
+- break;
+- default:
+- spin_unlock_irqrestore(&ath724x_pci_lock, flags);
+-
+- return PCIBIOS_BAD_REGISTER_NUMBER;
+- }
+-
+- spin_unlock_irqrestore(&ath724x_pci_lock, flags);
+-
+- return PCIBIOS_SUCCESSFUL;
+-}
+-
+-static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
+- int size, uint32_t value)
+-{
+- unsigned long flags, tval, addr, mask;
+-
+- if (devfn)
+- return PCIBIOS_DEVICE_NOT_FOUND;
+-
+- if (where & (size - 1))
+- return PCIBIOS_BAD_REGISTER_NUMBER;
+-
+- spin_lock_irqsave(&ath724x_pci_lock, flags);
+-
+- switch (size) {
+- case 1:
+- addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
+- mask = 0xff000000 >> ((where % 4)*8);
+- tval = reg_read(addr);
+- tval = tval & ~mask;
+- tval |= (value << ((4 - (where % 4))*8)) & mask;
+- reg_write(addr, tval);
+- break;
+- case 2:
+- addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
+- mask = 0xffff0000 >> ((where % 4)*8);
+- tval = reg_read(addr);
+- tval = tval & ~mask;
+- tval |= (value << ((4 - (where % 4))*8)) & mask;
+- reg_write(addr, tval);
+- break;
+- case 4:
+- reg_write((ATH724X_PCI_DEV_BASE + where), value);
+- break;
+- default:
+- spin_unlock_irqrestore(&ath724x_pci_lock, flags);
+-
+- return PCIBIOS_BAD_REGISTER_NUMBER;
+- }
+-
+- spin_unlock_irqrestore(&ath724x_pci_lock, flags);
+-
+- return PCIBIOS_SUCCESSFUL;
+-}
+-
+-static struct pci_ops ath724x_pci_ops = {
+- .read = ath724x_pci_read,
+- .write = ath724x_pci_write,
+-};
+-
+-static struct resource ath724x_io_resource = {
+- .name = "PCI IO space",
+- .start = 0,
+- .end = 0,
+- .flags = IORESOURCE_IO,
+-};
+-
+-static struct resource ath724x_mem_resource = {
+- .name = "PCI memory space",
+- .start = ATH724X_PCI_MEM_BASE,
+- .end = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1,
+- .flags = IORESOURCE_MEM,
+-};
+-
+-static struct pci_controller ath724x_pci_controller = {
+- .pci_ops = &ath724x_pci_ops,
+- .io_resource = &ath724x_io_resource,
+- .mem_resource = &ath724x_mem_resource,
+-};
+-
+-int __init ath724x_pcibios_init(void)
+-{
+- register_pci_controller(&ath724x_pci_controller);
+-
+- return PCIBIOS_SUCCESSFUL;
+-}
--- /dev/null
+From 0cbee5634678ffbd10bee9e302d013392dd8289e Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 18 Nov 2011 11:16:33 +0100
+Subject: [PATCH 07/35] MIPS: ath79: replace ath724x to ar724x
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Replace the 'ath724x' to 'ar724x' in function, variable and
+structure names to reflect the name of the real SoC.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: René Bolldorf <xsecute@googlemail.com>
+
+v4: - add an Acked-by tag from René
+ - refreshed due to the changes in a previous patch
+v3: - no changes
+v2: - no changes
+---
+ arch/mips/ath79/mach-ubnt-xm.c | 4 +-
+ arch/mips/ath79/pci.c | 6 ++--
+ arch/mips/ath79/pci.h | 10 +++---
+ arch/mips/include/asm/mach-ath79/pci.h | 4 +-
+ arch/mips/pci/pci-ar724x.c | 62 ++++++++++++++++----------------
+ 5 files changed, 43 insertions(+), 43 deletions(-)
+
+--- a/arch/mips/ath79/mach-ubnt-xm.c
++++ b/arch/mips/ath79/mach-ubnt-xm.c
+@@ -84,7 +84,7 @@ static struct ath79_spi_platform_data ub
+ #ifdef CONFIG_PCI
+ static struct ath9k_platform_data ubnt_xm_eeprom_data;
+
+-static struct ath724x_pci_data ubnt_xm_pci_data[] = {
++static struct ar724x_pci_data ubnt_xm_pci_data[] = {
+ {
+ .irq = UBNT_XM_PCI_IRQ,
+ .pdata = &ubnt_xm_eeprom_data,
+@@ -108,7 +108,7 @@ static void __init ubnt_xm_init(void)
+ memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
+ sizeof(ubnt_xm_eeprom_data.eeprom_data));
+
+- ath724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data));
++ ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data));
+ #endif /* CONFIG_PCI */
+
+ ath79_register_pci();
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -13,10 +13,10 @@
+ #include <asm/mach-ath79/pci.h>
+ #include "pci.h"
+
+-static struct ath724x_pci_data *pci_data;
++static struct ar724x_pci_data *pci_data;
+ static int pci_data_size;
+
+-void ath724x_pci_add_data(struct ath724x_pci_data *data, int size)
++void ar724x_pci_add_data(struct ar724x_pci_data *data, int size)
+ {
+ pci_data = data;
+ pci_data_size = size;
+@@ -50,7 +50,7 @@ int pcibios_plat_dev_init(struct pci_dev
+ int __init ath79_register_pci(void)
+ {
+ if (soc_is_ar724x())
+- return ath724x_pcibios_init();
++ return ar724x_pcibios_init();
+
+ return -ENODEV;
+ }
+--- a/arch/mips/ath79/pci.h
++++ b/arch/mips/ath79/pci.h
+@@ -8,15 +8,15 @@
+ * by the Free Software Foundation.
+ */
+
+-#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H
+-#define __ASM_MACH_ATH79_PCI_ATH724X_H
++#ifndef _ATH79_PCI_H
++#define _ATH79_PCI_H
+
+-struct ath724x_pci_data {
++struct ar724x_pci_data {
+ int irq;
+ void *pdata;
+ };
+
+-void ath724x_pci_add_data(struct ath724x_pci_data *data, int size);
++void ar724x_pci_add_data(struct ar724x_pci_data *data, int size);
+
+ #ifdef CONFIG_PCI
+ int ath79_register_pci(void);
+@@ -24,4 +24,4 @@ int ath79_register_pci(void);
+ static inline int ath79_register_pci(void) { return 0; }
+ #endif
+
+-#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */
++#endif /* _ATH79_PCI_H */
+--- a/arch/mips/include/asm/mach-ath79/pci.h
++++ b/arch/mips/include/asm/mach-ath79/pci.h
+@@ -12,9 +12,9 @@
+ #define __ASM_MACH_ATH79_PCI_H
+
+ #if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X)
+-int ath724x_pcibios_init(void);
++int ar724x_pcibios_init(void);
+ #else
+-static inline int ath724x_pcibios_init(void) { return 0 };
++static inline int ar724x_pcibios_init(void) { return 0 };
+ #endif
+
+ #endif /* __ASM_MACH_ATH79_PCI_H */
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -14,13 +14,13 @@
+ #define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys))
+ #define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
+
+-#define ATH724X_PCI_DEV_BASE 0x14000000
+-#define ATH724X_PCI_MEM_BASE 0x10000000
+-#define ATH724X_PCI_MEM_SIZE 0x08000000
++#define AR724X_PCI_DEV_BASE 0x14000000
++#define AR724X_PCI_MEM_BASE 0x10000000
++#define AR724X_PCI_MEM_SIZE 0x08000000
+
+-static DEFINE_SPINLOCK(ath724x_pci_lock);
++static DEFINE_SPINLOCK(ar724x_pci_lock);
+
+-static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
++static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
+ int size, uint32_t *value)
+ {
+ unsigned long flags, addr, tval, mask;
+@@ -31,38 +31,38 @@ static int ath724x_pci_read(struct pci_b
+ if (where & (size - 1))
+ return PCIBIOS_BAD_REGISTER_NUMBER;
+
+- spin_lock_irqsave(&ath724x_pci_lock, flags);
++ spin_lock_irqsave(&ar724x_pci_lock, flags);
+
+ switch (size) {
+ case 1:
+ addr = where & ~3;
+ mask = 0xff000000 >> ((where % 4) * 8);
+- tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
++ tval = reg_read(AR724X_PCI_DEV_BASE + addr);
+ tval = tval & ~mask;
+ *value = (tval >> ((4 - (where % 4))*8));
+ break;
+ case 2:
+ addr = where & ~3;
+ mask = 0xffff0000 >> ((where % 4)*8);
+- tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
++ tval = reg_read(AR724X_PCI_DEV_BASE + addr);
+ tval = tval & ~mask;
+ *value = (tval >> ((4 - (where % 4))*8));
+ break;
+ case 4:
+- *value = reg_read(ATH724X_PCI_DEV_BASE + where);
++ *value = reg_read(AR724X_PCI_DEV_BASE + where);
+ break;
+ default:
+- spin_unlock_irqrestore(&ath724x_pci_lock, flags);
++ spin_unlock_irqrestore(&ar724x_pci_lock, flags);
+
+ return PCIBIOS_BAD_REGISTER_NUMBER;
+ }
+
+- spin_unlock_irqrestore(&ath724x_pci_lock, flags);
++ spin_unlock_irqrestore(&ar724x_pci_lock, flags);
+
+ return PCIBIOS_SUCCESSFUL;
+ }
+
+-static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
++static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
+ int size, uint32_t value)
+ {
+ unsigned long flags, tval, addr, mask;
+@@ -73,11 +73,11 @@ static int ath724x_pci_write(struct pci_
+ if (where & (size - 1))
+ return PCIBIOS_BAD_REGISTER_NUMBER;
+
+- spin_lock_irqsave(&ath724x_pci_lock, flags);
++ spin_lock_irqsave(&ar724x_pci_lock, flags);
+
+ switch (size) {
+ case 1:
+- addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
++ addr = (AR724X_PCI_DEV_BASE + where) & ~3;
+ mask = 0xff000000 >> ((where % 4)*8);
+ tval = reg_read(addr);
+ tval = tval & ~mask;
+@@ -85,7 +85,7 @@ static int ath724x_pci_write(struct pci_
+ reg_write(addr, tval);
+ break;
+ case 2:
+- addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
++ addr = (AR724X_PCI_DEV_BASE + where) & ~3;
+ mask = 0xffff0000 >> ((where % 4)*8);
+ tval = reg_read(addr);
+ tval = tval & ~mask;
+@@ -93,47 +93,47 @@ static int ath724x_pci_write(struct pci_
+ reg_write(addr, tval);
+ break;
+ case 4:
+- reg_write((ATH724X_PCI_DEV_BASE + where), value);
++ reg_write((AR724X_PCI_DEV_BASE + where), value);
+ break;
+ default:
+- spin_unlock_irqrestore(&ath724x_pci_lock, flags);
++ spin_unlock_irqrestore(&ar724x_pci_lock, flags);
+
+ return PCIBIOS_BAD_REGISTER_NUMBER;
+ }
+
+- spin_unlock_irqrestore(&ath724x_pci_lock, flags);
++ spin_unlock_irqrestore(&ar724x_pci_lock, flags);
+
+ return PCIBIOS_SUCCESSFUL;
+ }
+
+-static struct pci_ops ath724x_pci_ops = {
+- .read = ath724x_pci_read,
+- .write = ath724x_pci_write,
++static struct pci_ops ar724x_pci_ops = {
++ .read = ar724x_pci_read,
++ .write = ar724x_pci_write,
+ };
+
+-static struct resource ath724x_io_resource = {
++static struct resource ar724x_io_resource = {
+ .name = "PCI IO space",
+ .start = 0,
+ .end = 0,
+ .flags = IORESOURCE_IO,
+ };
+
+-static struct resource ath724x_mem_resource = {
++static struct resource ar724x_mem_resource = {
+ .name = "PCI memory space",
+- .start = ATH724X_PCI_MEM_BASE,
+- .end = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1,
++ .start = AR724X_PCI_MEM_BASE,
++ .end = AR724X_PCI_MEM_BASE + AR724X_PCI_MEM_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ };
+
+-static struct pci_controller ath724x_pci_controller = {
+- .pci_ops = &ath724x_pci_ops,
+- .io_resource = &ath724x_io_resource,
+- .mem_resource = &ath724x_mem_resource,
++static struct pci_controller ar724x_pci_controller = {
++ .pci_ops = &ar724x_pci_ops,
++ .io_resource = &ar724x_io_resource,
++ .mem_resource = &ar724x_mem_resource,
+ };
+
+-int __init ath724x_pcibios_init(void)
++int __init ar724x_pcibios_init(void)
+ {
+- register_pci_controller(&ath724x_pci_controller);
++ register_pci_controller(&ar724x_pci_controller);
+
+ return PCIBIOS_SUCCESSFUL;
+ }
--- /dev/null
+From db464f2ad82c03f847d8eabbb8251b5c567e6720 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 18 Nov 2011 11:52:41 +0100
+Subject: [PATCH 08/35] MIPS: ath79: use io-accessor macros in pci-ar724x.c
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: René Bolldorf <xsecute@googlemail.com>
+
+v4: - add an Acked-by tag from René
+v3: - no changes
+v2: - no changes
+---
+ arch/mips/pci/pci-ar724x.c | 38 ++++++++++++++++++++++++--------------
+ 1 files changed, 24 insertions(+), 14 deletions(-)
+
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -11,19 +11,19 @@
+ #include <linux/pci.h>
+ #include <asm/mach-ath79/pci.h>
+
+-#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys))
+-#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
+-
+-#define AR724X_PCI_DEV_BASE 0x14000000
++#define AR724X_PCI_CFG_BASE 0x14000000
++#define AR724X_PCI_CFG_SIZE 0x1000
+ #define AR724X_PCI_MEM_BASE 0x10000000
+ #define AR724X_PCI_MEM_SIZE 0x08000000
+
+ static DEFINE_SPINLOCK(ar724x_pci_lock);
++static void __iomem *ar724x_pci_devcfg_base;
+
+ static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
+ int size, uint32_t *value)
+ {
+ unsigned long flags, addr, tval, mask;
++ void __iomem *base;
+
+ if (devfn)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+@@ -31,25 +31,27 @@ static int ar724x_pci_read(struct pci_bu
+ if (where & (size - 1))
+ return PCIBIOS_BAD_REGISTER_NUMBER;
+
++ base = ar724x_pci_devcfg_base;
++
+ spin_lock_irqsave(&ar724x_pci_lock, flags);
+
+ switch (size) {
+ case 1:
+ addr = where & ~3;
+ mask = 0xff000000 >> ((where % 4) * 8);
+- tval = reg_read(AR724X_PCI_DEV_BASE + addr);
++ tval = __raw_readl(base + addr);
+ tval = tval & ~mask;
+ *value = (tval >> ((4 - (where % 4))*8));
+ break;
+ case 2:
+ addr = where & ~3;
+ mask = 0xffff0000 >> ((where % 4)*8);
+- tval = reg_read(AR724X_PCI_DEV_BASE + addr);
++ tval = __raw_readl(base + addr);
+ tval = tval & ~mask;
+ *value = (tval >> ((4 - (where % 4))*8));
+ break;
+ case 4:
+- *value = reg_read(AR724X_PCI_DEV_BASE + where);
++ *value = __raw_readl(base + where);
+ break;
+ default:
+ spin_unlock_irqrestore(&ar724x_pci_lock, flags);
+@@ -66,6 +68,7 @@ static int ar724x_pci_write(struct pci_b
+ int size, uint32_t value)
+ {
+ unsigned long flags, tval, addr, mask;
++ void __iomem *base;
+
+ if (devfn)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+@@ -73,27 +76,29 @@ static int ar724x_pci_write(struct pci_b
+ if (where & (size - 1))
+ return PCIBIOS_BAD_REGISTER_NUMBER;
+
++ base = ar724x_pci_devcfg_base;
++
+ spin_lock_irqsave(&ar724x_pci_lock, flags);
+
+ switch (size) {
+ case 1:
+- addr = (AR724X_PCI_DEV_BASE + where) & ~3;
++ addr = where & ~3;
+ mask = 0xff000000 >> ((where % 4)*8);
+- tval = reg_read(addr);
++ tval = __raw_readl(base + addr);
+ tval = tval & ~mask;
+ tval |= (value << ((4 - (where % 4))*8)) & mask;
+- reg_write(addr, tval);
++ __raw_writel(tval, base + addr);
+ break;
+ case 2:
+- addr = (AR724X_PCI_DEV_BASE + where) & ~3;
++ addr = where & ~3;
+ mask = 0xffff0000 >> ((where % 4)*8);
+- tval = reg_read(addr);
++ tval = __raw_readl(base + addr);
+ tval = tval & ~mask;
+ tval |= (value << ((4 - (where % 4))*8)) & mask;
+- reg_write(addr, tval);
++ __raw_writel(tval, base + addr);
+ break;
+ case 4:
+- reg_write((AR724X_PCI_DEV_BASE + where), value);
++ __raw_writel(value, (base + where));
+ break;
+ default:
+ spin_unlock_irqrestore(&ar724x_pci_lock, flags);
+@@ -133,6 +138,11 @@ static struct pci_controller ar724x_pci_
+
+ int __init ar724x_pcibios_init(void)
+ {
++ ar724x_pci_devcfg_base = ioremap(AR724X_PCI_CFG_BASE,
++ AR724X_PCI_CFG_SIZE);
++ if (ar724x_pci_devcfg_base == NULL)
++ return -ENOMEM;
++
+ register_pci_controller(&ar724x_pci_controller);
+
+ return PCIBIOS_SUCCESSFUL;
--- /dev/null
+From 744ffdd4e90cd6671f46eadf9d7cf55b07618d73 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 18 Nov 2011 21:37:17 +0100
+Subject: [PATCH 09/35] MIPS: ath79: remove superfluous alignment checks from pci-ar724x.c
+
+The alignment of the 'where' parameters are checked
+in the core PCI code already.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+
+v2: - no changes
+---
+ arch/mips/pci/pci-ar724x.c | 6 ------
+ 1 files changed, 0 insertions(+), 6 deletions(-)
+
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -28,9 +28,6 @@ static int ar724x_pci_read(struct pci_bu
+ if (devfn)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+- if (where & (size - 1))
+- return PCIBIOS_BAD_REGISTER_NUMBER;
+-
+ base = ar724x_pci_devcfg_base;
+
+ spin_lock_irqsave(&ar724x_pci_lock, flags);
+@@ -73,9 +70,6 @@ static int ar724x_pci_write(struct pci_b
+ if (devfn)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+- if (where & (size - 1))
+- return PCIBIOS_BAD_REGISTER_NUMBER;
+-
+ base = ar724x_pci_devcfg_base;
+
+ spin_lock_irqsave(&ar724x_pci_lock, flags);
--- /dev/null
+From 2e535c334018d58b0bf6df583486abda5bfb2003 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 18 Nov 2011 22:25:30 +0100
+Subject: [PATCH 10/35] MIPS: ath79: fix broken ar724x_pci_{read,write} functions
+
+The current ar724x_pci_{read,write} functions are
+broken. Due to that, pci_read_config_byte returns
+with bogus values, and pci_write_config_{byte,word}
+unconditionally clears the accessed PCI configuration
+registers instead of changing the value of them.
+
+The patch fixes the broken functions, thus the PCI
+configuration space can be accessed correctly.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+
+v2: - no changes
+
+Output of 'lspci -vv' without the patch:
+
+00:00.0 Network controller: Atheros Communications Inc. AR9285 Wireless
+Network Adapter (PCI-Express) (rev 01)
+ Subsystem: Atheros Communications Inc. Device a091
+ Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0
+ Interrupt: pin A routed to IRQ 0
+ Region 0: Memory at 10000000 (64-bit, non-prefetchable) [size=64K]
+ Capabilities: [40] Power Management version 3
+ Flags: PMEClk- DSI- D1+ D2- AuxCurrent=375mA PME(D0+,D1+,D2-,D3hot+,D3cold-)
+ Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
+ Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit-
+ Address: 00000000 Data: 0000
+ Capabilities: [60] Express (v2) Legacy Endpoint, MSI 00
+ DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us
+ ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
+ DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
+ RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop-
+ MaxPayload 128 bytes, MaxReadReq 512 bytes
+ DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
+ LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM unknown, Latency L0 <512ns, L1 <64us
+ ClockPM- Surprise- LLActRep- BwNot-
+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk-
+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
+ DevCap2: Completion Timeout: Not Supported, TimeoutDis+
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-
+ LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB
+ Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+ Compliance De-emphasis: -6dB
+ LnkSta2: Current De-emphasis Level: -6dB
+
+Output of 'lspci -vv' with the patch:
+
+00:00.0 Network controller: Atheros Communications Inc. AR9285 Wireless
+Network Adapter (PCI-Express) (rev 01)
+ Subsystem: Atheros Communications Inc. Device a091
+ Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0
+ Interrupt: pin A routed to IRQ 48
+ Region 0: Memory at 10000000 (64-bit, non-prefetchable) [size=64K]
+ Capabilities: [40] Power Management version 3
+ Flags: PMEClk- DSI- D1+ D2- AuxCurrent=375mA PME(D0+,D1+,D2-,D3hot+,D3cold-)
+ Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
+ Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit-
+ Address: 00000000 Data: 0000
+ Capabilities: [60] Express (v2) Legacy Endpoint, MSI 00
+ DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us
+ ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
+ DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
+ RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop-
+ MaxPayload 128 bytes, MaxReadReq 512 bytes
+ DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
+ LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM unknown, Latency L0 <512ns, L1 <64us
+ ClockPM- Surprise- LLActRep- BwNot-
+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk-
+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
+ DevCap2: Completion Timeout: Not Supported, TimeoutDis+
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-
+ LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB
+ Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+ Compliance De-emphasis: -6dB
+ LnkSta2: Current De-emphasis Level: -6dB
+ Capabilities: [100 v1] Advanced Error Reporting
+ UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+ CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
+ AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-
+ Capabilities: [140 v1] Virtual Channel
+ Caps: LPEVC=0 RefClk=100ns PATEntryBits=1
+ Arb: Fixed- WRR32- WRR64- WRR128-
+ Ctrl: ArbSelect=Fixed
+ Status: InProgress-
+ VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
+ Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
+ Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff
+ Status: NegoPending- InProgress-
+ Capabilities: [160 v1] Device Serial Number 00-15-17-ff-ff-24-14-12
+ Capabilities: [170 v1] Power Budgeting <?>
+---
+ arch/mips/pci/pci-ar724x.c | 52 ++++++++++++++++++++++----------------------
+ 1 files changed, 26 insertions(+), 26 deletions(-)
+
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -22,8 +22,9 @@ static void __iomem *ar724x_pci_devcfg_b
+ static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
+ int size, uint32_t *value)
+ {
+- unsigned long flags, addr, tval, mask;
++ unsigned long flags;
+ void __iomem *base;
++ u32 data;
+
+ if (devfn)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+@@ -31,24 +32,22 @@ static int ar724x_pci_read(struct pci_bu
+ base = ar724x_pci_devcfg_base;
+
+ spin_lock_irqsave(&ar724x_pci_lock, flags);
++ data = __raw_readl(base + (where & ~3));
+
+ switch (size) {
+ case 1:
+- addr = where & ~3;
+- mask = 0xff000000 >> ((where % 4) * 8);
+- tval = __raw_readl(base + addr);
+- tval = tval & ~mask;
+- *value = (tval >> ((4 - (where % 4))*8));
++ if (where & 1)
++ data >>= 8;
++ if (where & 2)
++ data >>= 16;
++ data &= 0xff;
+ break;
+ case 2:
+- addr = where & ~3;
+- mask = 0xffff0000 >> ((where % 4)*8);
+- tval = __raw_readl(base + addr);
+- tval = tval & ~mask;
+- *value = (tval >> ((4 - (where % 4))*8));
++ if (where & 2)
++ data >>= 16;
++ data &= 0xffff;
+ break;
+ case 4:
+- *value = __raw_readl(base + where);
+ break;
+ default:
+ spin_unlock_irqrestore(&ar724x_pci_lock, flags);
+@@ -57,6 +56,7 @@ static int ar724x_pci_read(struct pci_bu
+ }
+
+ spin_unlock_irqrestore(&ar724x_pci_lock, flags);
++ *value = data;
+
+ return PCIBIOS_SUCCESSFUL;
+ }
+@@ -64,8 +64,10 @@ static int ar724x_pci_read(struct pci_bu
+ static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
+ int size, uint32_t value)
+ {
+- unsigned long flags, tval, addr, mask;
++ unsigned long flags;
+ void __iomem *base;
++ u32 data;
++ int s;
+
+ if (devfn)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+@@ -73,26 +75,21 @@ static int ar724x_pci_write(struct pci_b
+ base = ar724x_pci_devcfg_base;
+
+ spin_lock_irqsave(&ar724x_pci_lock, flags);
++ data = __raw_readl(base + (where & ~3));
+
+ switch (size) {
+ case 1:
+- addr = where & ~3;
+- mask = 0xff000000 >> ((where % 4)*8);
+- tval = __raw_readl(base + addr);
+- tval = tval & ~mask;
+- tval |= (value << ((4 - (where % 4))*8)) & mask;
+- __raw_writel(tval, base + addr);
++ s = ((where & 3) * 8);
++ data &= ~(0xff << s);
++ data |= ((value & 0xff) << s);
+ break;
+ case 2:
+- addr = where & ~3;
+- mask = 0xffff0000 >> ((where % 4)*8);
+- tval = __raw_readl(base + addr);
+- tval = tval & ~mask;
+- tval |= (value << ((4 - (where % 4))*8)) & mask;
+- __raw_writel(tval, base + addr);
++ s = ((where & 2) * 8);
++ data &= ~(0xffff << s);
++ data |= ((value & 0xffff) << s);
+ break;
+ case 4:
+- __raw_writel(value, (base + where));
++ data = value;
+ break;
+ default:
+ spin_unlock_irqrestore(&ar724x_pci_lock, flags);
+@@ -100,6 +97,9 @@ static int ar724x_pci_write(struct pci_b
+ return PCIBIOS_BAD_REGISTER_NUMBER;
+ }
+
++ __raw_writel(data, base + (where & ~3));
++ /* flush write */
++ __raw_readl(base + (where & ~3));
+ spin_unlock_irqrestore(&ar724x_pci_lock, flags);
+
+ return PCIBIOS_SUCCESSFUL;
--- /dev/null
+From b2ee3bd8706521c9bbf43405c767010927c101e5 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 21 Nov 2011 17:57:51 +0100
+Subject: [PATCH 11/35] MIPS: ath79: add a workaround for a PCI controller bug in AR7240 SoCs
+
+The PCI controller of the AR724X SoCs has a hardware
+bag. If the BAR0 register of the PCI device is set to
+the proper base address, the memory address space of
+the device is not accessible.
+
+When the device driver tries to access the memory
+address space of the PCI device, it leads to data
+bus error, similiar to this:
+
+Data bus error, epc == 801f69a0, ra == 801f698c
+Oops[#1]:
+Cpu 0
+$ 0 : 00000000 00000061 deadbeef 000000ff
+$ 4 : 00000000 000000ff 00000014 00000000
+$ 8 : ff000000 fffffffc 00000000 00000000
+$12 : 000001f5 00000006 00000000 6e637920
+$16 : 81ca4000 81ca0260 81ca4000 804d70f0
+$20 : fffffff4 0000002b 803ad4c4 00000000
+$24 : 00000003 00000000
+$28 : 81c20000 81c21c60 00000000 801f698c
+Hi : 00000000
+Lo : 00000000
+epc : 801f69a0 ath9k_hw_init+0xd0/0xa70
+ Not tainted
+ra : 801f698c ath9k_hw_init+0xbc/0xa70
+Status: 1000c103 KERNEL EXL IE
+Cause : 1080001c
+PrId : 00019374 (MIPS 24Kc)
+Modules linked in:
+Process swapper (pid: 1, threadinfo=81c20000, task=81c18000, tls=00000000)
+Stack : 00000000 00000000 00000000 00000000 81c21c78 81ca0260 00000000 804d70f0
+ 81ca0260 81c21cc0 81ca0e80 81ca0260 81ca4000 804d70f0 fffffff4 0000002b
+ 803ad4c4 00000000 00000000 801e3ae8 81c9d080 81ca0e80 b0000000 800b9b9c
+ 00000008 81c9d000 8031aeb0 802d38a0 00000000 81c14c00 81c14c60 00000000
+ 81ca0e80 81ca0260 b0000000 801f08a4 81c9c820 81c21d48 81c9c820 80144320
+ ...
+Call Trace:
+[<801f69a0>] ath9k_hw_init+0xd0/0xa70
+[<801e3ae8>] ath9k_init_device+0x174/0x680
+[<801f08a4>] ath_pci_probe+0x27c/0x380
+[<8019e490>] pci_device_probe+0x74/0x9c
+[<801bfadc>] driver_probe_device+0x9c/0x1b4
+[<801bfcb0>] __driver_attach+0xbc/0xc4
+[<801bea0c>] bus_for_each_dev+0x5c/0x98
+[<801bf394>] bus_add_driver+0x1d0/0x2a4
+[<801c0364>] driver_register+0x8c/0x16c
+[<8019e72c>] __pci_register_driver+0x4c/0xe4
+[<803d3d40>] ath9k_init+0x3c/0x88
+[<80060930>] do_one_initcall+0x3c/0x1cc
+[<803c297c>] kernel_init+0xa4/0x138
+[<80063c04>] kernel_thread_helper+0x10/0x18
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+
+v2: - apply the workaround on AR7240 only
+ - remove unrelated defines
+---
+ arch/mips/pci/pci-ar724x.c | 36 +++++++++++++++++++++++++++++++++++-
+ 1 files changed, 35 insertions(+), 1 deletions(-)
+
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -9,6 +9,7 @@
+ */
+
+ #include <linux/pci.h>
++#include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/pci.h>
+
+ #define AR724X_PCI_CFG_BASE 0x14000000
+@@ -16,9 +17,14 @@
+ #define AR724X_PCI_MEM_BASE 0x10000000
+ #define AR724X_PCI_MEM_SIZE 0x08000000
+
++#define AR7240_BAR0_WAR_VALUE 0xffff
++
+ static DEFINE_SPINLOCK(ar724x_pci_lock);
+ static void __iomem *ar724x_pci_devcfg_base;
+
++static u32 ar724x_pci_bar0_value;
++static bool ar724x_pci_bar0_is_cached;
++
+ static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
+ int size, uint32_t *value)
+ {
+@@ -56,7 +62,14 @@ static int ar724x_pci_read(struct pci_bu
+ }
+
+ spin_unlock_irqrestore(&ar724x_pci_lock, flags);
+- *value = data;
++
++ if (where == PCI_BASE_ADDRESS_0 && size == 4 &&
++ ar724x_pci_bar0_is_cached) {
++ /* use the cached value */
++ *value = ar724x_pci_bar0_value;
++ } else {
++ *value = data;
++ }
+
+ return PCIBIOS_SUCCESSFUL;
+ }
+@@ -72,6 +85,27 @@ static int ar724x_pci_write(struct pci_b
+ if (devfn)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
++ if (soc_is_ar7240() && where == PCI_BASE_ADDRESS_0 && size == 4) {
++ if (value != 0xffffffff) {
++ /*
++ * WAR for a hw issue. If the BAR0 register of the
++ * device is set to the proper base address, the
++ * memory space of the device is not accessible.
++ *
++ * Cache the intended value so it can be read back,
++ * and write a SoC specific constant value to the
++ * BAR0 register in order to make the device memory
++ * accessible.
++ */
++ ar724x_pci_bar0_is_cached = true;
++ ar724x_pci_bar0_value = value;
++
++ value = AR7240_BAR0_WAR_VALUE;
++ } else {
++ ar724x_pci_bar0_is_cached = false;
++ }
++ }
++
+ base = ar724x_pci_devcfg_base;
+
+ spin_lock_irqsave(&ar724x_pci_lock, flags);
--- /dev/null
+From cfb725275ea25857e8f0e3bf358fff7c84cc787c Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Tue, 22 Nov 2011 13:59:39 +0100
+Subject: [PATCH 12/35] MIPS: ath79: fix a wrong IRQ number
+
+The Ubiquiti XM board setup code uses an invalid
+IRQ number, because it if above of NR_IRQS. This
+leads to failed 'request_irq' calls:
+
+ ath9k 0000:00:00.0: request_irq failed
+ ath9k: probe of 0000:00:00.0 failed with error -22
+
+Preserve some IRQ numbers for the built-in IRQ
+controller of PCI host controllers in the
+AR71XX/AR724X SoCs, and use the correct IRQ
+number in the board setup code.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+
+v2: - no changes
+
+The IRQ controller code is also missing, that will be
+added in a separate patch.
+---
+ arch/mips/ath79/mach-ubnt-xm.c | 5 +++--
+ arch/mips/include/asm/mach-ath79/irq.h | 6 +++++-
+ 2 files changed, 8 insertions(+), 3 deletions(-)
+
+--- a/arch/mips/ath79/mach-ubnt-xm.c
++++ b/arch/mips/ath79/mach-ubnt-xm.c
+@@ -17,6 +17,8 @@
+ #include <linux/ath9k_platform.h>
+ #endif /* CONFIG_PCI */
+
++#include <asm/mach-ath79/irq.h>
++
+ #include "machtypes.h"
+ #include "dev-gpio-buttons.h"
+ #include "dev-leds-gpio.h"
+@@ -33,7 +35,6 @@
+ #define UBNT_XM_KEYS_POLL_INTERVAL 20
+ #define UBNT_XM_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_XM_KEYS_POLL_INTERVAL)
+
+-#define UBNT_XM_PCI_IRQ 48
+ #define UBNT_XM_EEPROM_ADDR (u8 *) KSEG1ADDR(0x1fff1000)
+
+ static struct gpio_led ubnt_xm_leds_gpio[] __initdata = {
+@@ -86,7 +87,7 @@ static struct ath9k_platform_data ubnt_x
+
+ static struct ar724x_pci_data ubnt_xm_pci_data[] = {
+ {
+- .irq = UBNT_XM_PCI_IRQ,
++ .irq = ATH79_PCI_IRQ(0),
+ .pdata = &ubnt_xm_eeprom_data,
+ },
+ };
+--- a/arch/mips/include/asm/mach-ath79/irq.h
++++ b/arch/mips/include/asm/mach-ath79/irq.h
+@@ -10,11 +10,15 @@
+ #define __ASM_MACH_ATH79_IRQ_H
+
+ #define MIPS_CPU_IRQ_BASE 0
+-#define NR_IRQS 40
++#define NR_IRQS 46
+
+ #define ATH79_MISC_IRQ_BASE 8
+ #define ATH79_MISC_IRQ_COUNT 32
+
++#define ATH79_PCI_IRQ_BASE (ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT)
++#define ATH79_PCI_IRQ_COUNT 6
++#define ATH79_PCI_IRQ(_x) (ATH79_PCI_IRQ_BASE + (_x))
++
+ #define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2)
+ #define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3)
+ #define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4)
--- /dev/null
+From a4fbc2dec67a5d760e25e3c3a6c392191a5405c6 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Tue, 22 Nov 2011 14:11:19 +0100
+Subject: [PATCH 13/35] MIPS: ath79: add PCI IRQ handling code for AR724X SoCs
+
+The PCI Host Controller of the AR724x SoC has a
+built-in IRQ controller. The current code does
+not supports that, so the IRQ lines wired to this
+controller are not usable. This leads to failed
+'request_irq' calls:
+
+ ath9k 0000:00:00.0: request_irq failed
+ ath9k: probe of 0000:00:00.0 failed with error -89
+
+This patch adds support for the IRQ controller
+in order to make PCI IRQs work.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+
+v2: - move the interrupt controller related defines from
+ the workaround patch
+---
+ arch/mips/ath79/pci.c | 3 +-
+ arch/mips/include/asm/mach-ath79/pci.h | 4 +-
+ arch/mips/pci/pci-ar724x.c | 118 +++++++++++++++++++++++++++++++-
+ 3 files changed, 120 insertions(+), 5 deletions(-)
+
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -10,6 +10,7 @@
+
+ #include <linux/pci.h>
+ #include <asm/mach-ath79/ath79.h>
++#include <asm/mach-ath79/irq.h>
+ #include <asm/mach-ath79/pci.h>
+ #include "pci.h"
+
+@@ -50,7 +51,7 @@ int pcibios_plat_dev_init(struct pci_dev
+ int __init ath79_register_pci(void)
+ {
+ if (soc_is_ar724x())
+- return ar724x_pcibios_init();
++ return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2);
+
+ return -ENODEV;
+ }
+--- a/arch/mips/include/asm/mach-ath79/pci.h
++++ b/arch/mips/include/asm/mach-ath79/pci.h
+@@ -12,9 +12,9 @@
+ #define __ASM_MACH_ATH79_PCI_H
+
+ #if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X)
+-int ar724x_pcibios_init(void);
++int ar724x_pcibios_init(int irq);
+ #else
+-static inline int ar724x_pcibios_init(void) { return 0 };
++static inline int ar724x_pcibios_init(int irq) { return 0 };
+ #endif
+
+ #endif /* __ASM_MACH_ATH79_PCI_H */
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -8,19 +8,32 @@
+ * by the Free Software Foundation.
+ */
+
++#include <linux/irq.h>
+ #include <linux/pci.h>
+ #include <asm/mach-ath79/ath79.h>
++#include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/pci.h>
+
+ #define AR724X_PCI_CFG_BASE 0x14000000
+ #define AR724X_PCI_CFG_SIZE 0x1000
++#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000)
++#define AR724X_PCI_CTRL_SIZE 0x100
++
+ #define AR724X_PCI_MEM_BASE 0x10000000
+ #define AR724X_PCI_MEM_SIZE 0x08000000
+
++#define AR724X_PCI_REG_INT_STATUS 0x4c
++#define AR724X_PCI_REG_INT_MASK 0x50
++
++#define AR724X_PCI_INT_DEV0 BIT(14)
++
++#define AR724X_PCI_IRQ_COUNT 1
++
+ #define AR7240_BAR0_WAR_VALUE 0xffff
+
+ static DEFINE_SPINLOCK(ar724x_pci_lock);
+ static void __iomem *ar724x_pci_devcfg_base;
++static void __iomem *ar724x_pci_ctrl_base;
+
+ static u32 ar724x_pci_bar0_value;
+ static bool ar724x_pci_bar0_is_cached;
+@@ -164,14 +177,115 @@ static struct pci_controller ar724x_pci_
+ .mem_resource = &ar724x_mem_resource,
+ };
+
+-int __init ar724x_pcibios_init(void)
++static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
++{
++ void __iomem *base;
++ u32 pending;
++
++ base = ar724x_pci_ctrl_base;
++
++ pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
++ __raw_readl(base + AR724X_PCI_REG_INT_MASK);
++
++ if (pending & AR724X_PCI_INT_DEV0)
++ generic_handle_irq(ATH79_PCI_IRQ(0));
++
++ else
++ spurious_interrupt();
++}
++
++static void ar724x_pci_irq_unmask(struct irq_data *d)
++{
++ void __iomem *base;
++ u32 t;
++
++ base = ar724x_pci_ctrl_base;
++
++ switch (d->irq) {
++ case ATH79_PCI_IRQ(0):
++ t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
++ __raw_writel(t | AR724X_PCI_INT_DEV0,
++ base + AR724X_PCI_REG_INT_MASK);
++ /* flush write */
++ __raw_readl(base + AR724X_PCI_REG_INT_MASK);
++ }
++}
++
++static void ar724x_pci_irq_mask(struct irq_data *d)
++{
++ void __iomem *base;
++ u32 t;
++
++ base = ar724x_pci_ctrl_base;
++
++ switch (d->irq) {
++ case ATH79_PCI_IRQ(0):
++ t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
++ __raw_writel(t & ~AR724X_PCI_INT_DEV0,
++ base + AR724X_PCI_REG_INT_MASK);
++
++ /* flush write */
++ __raw_readl(base + AR724X_PCI_REG_INT_MASK);
++
++ t = __raw_readl(base + AR724X_PCI_REG_INT_STATUS);
++ __raw_writel(t | AR724X_PCI_INT_DEV0,
++ base + AR724X_PCI_REG_INT_STATUS);
++
++ /* flush write */
++ __raw_readl(base + AR724X_PCI_REG_INT_STATUS);
++ }
++}
++
++static struct irq_chip ar724x_pci_irq_chip = {
++ .name = "AR724X PCI ",
++ .irq_mask = ar724x_pci_irq_mask,
++ .irq_unmask = ar724x_pci_irq_unmask,
++ .irq_mask_ack = ar724x_pci_irq_mask,
++};
++
++static void __init ar724x_pci_irq_init(int irq)
++{
++ void __iomem *base;
++ int i;
++
++ base = ar724x_pci_ctrl_base;
++
++ __raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
++ __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
++
++ BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR724X_PCI_IRQ_COUNT);
++
++ for (i = ATH79_PCI_IRQ_BASE;
++ i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++)
++ irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
++ handle_level_irq);
++
++ irq_set_chained_handler(irq, ar724x_pci_irq_handler);
++}
++
++int __init ar724x_pcibios_init(int irq)
+ {
++ int ret;
++
++ ret = -ENOMEM;
++
+ ar724x_pci_devcfg_base = ioremap(AR724X_PCI_CFG_BASE,
+ AR724X_PCI_CFG_SIZE);
+ if (ar724x_pci_devcfg_base == NULL)
+- return -ENOMEM;
++ goto err;
+
++ ar724x_pci_ctrl_base = ioremap(AR724X_PCI_CTRL_BASE,
++ AR724X_PCI_CTRL_SIZE);
++ if (ar724x_pci_ctrl_base == NULL)
++ goto err_unmap_devcfg;
++
++ ar724x_pci_irq_init(irq);
+ register_pci_controller(&ar724x_pci_controller);
+
+ return PCIBIOS_SUCCESSFUL;
++
++err_unmap_devcfg:
++ iounmap(ar724x_pci_devcfg_base);
++err:
++ return ret;
+ }
--- /dev/null
+From adeefb0860e92f44c7d66d5fccdb217fccfb8a81 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 20 Nov 2011 10:19:08 +0100
+Subject: [PATCH 14/35] MIPS: ath79: get rid of some ifdefs in mach-ubnt-xm.c
+
+Remove a superfluous ifdef around an include. Also
+reorganize the board setup code a bit, so another
+ifdef can be removed.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+
+v2: - no changes
+---
+ arch/mips/ath79/mach-ubnt-xm.c | 23 ++++++++++++-----------
+ 1 files changed, 12 insertions(+), 11 deletions(-)
+
+--- a/arch/mips/ath79/mach-ubnt-xm.c
++++ b/arch/mips/ath79/mach-ubnt-xm.c
+@@ -12,10 +12,7 @@
+
+ #include <linux/init.h>
+ #include <linux/pci.h>
+-
+-#ifdef CONFIG_PCI
+ #include <linux/ath9k_platform.h>
+-#endif /* CONFIG_PCI */
+
+ #include <asm/mach-ath79/irq.h>
+
+@@ -91,6 +88,17 @@ static struct ar724x_pci_data ubnt_xm_pc
+ .pdata = &ubnt_xm_eeprom_data,
+ },
+ };
++
++static void __init ubnt_xm_pci_init(void)
++{
++ memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
++ sizeof(ubnt_xm_eeprom_data.eeprom_data));
++
++ ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data));
++ ath79_register_pci();
++}
++#else
++static inline void ubnt_xm_pci_init(void) {}
+ #endif /* CONFIG_PCI */
+
+ static void __init ubnt_xm_init(void)
+@@ -105,14 +113,7 @@ static void __init ubnt_xm_init(void)
+ ath79_register_spi(&ubnt_xm_spi_data, ubnt_xm_spi_info,
+ ARRAY_SIZE(ubnt_xm_spi_info));
+
+-#ifdef CONFIG_PCI
+- memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
+- sizeof(ubnt_xm_eeprom_data.eeprom_data));
+-
+- ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data));
+-#endif /* CONFIG_PCI */
+-
+- ath79_register_pci();
++ ubnt_xm_pci_init();
+ }
+
+ MIPS_MACHINE(ATH79_MACH_UBNT_XM,
--- /dev/null
+From 83d74abc7d549f5d6292b0474be080983239c0bd Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 20 Nov 2011 10:29:36 +0100
+Subject: [PATCH 15/35] MIPS: ath79: allow to use board specific pci_plat_dev_init functions
+
+Th current implementation causes NULL pointer dereference
+if 'pci_data' is not set:
+
+pci 0000:00:00.0: BAR 0: assigned [mem 0x10000000-0x1000ffff 64bit]
+pci 0000:00:00.0: BAR 0: set to [mem 0x10000000-0x1000ffff 64bit] (PCI
+address [0x10000000-0x1000ffff])
+CPU 0 Unable to handle kernel paging request at virtual address 00000000, epc == 802daca0, ra == 802e78a4
+Oops[#1]:
+Cpu 0
+$ 0 : 00000000 80420000 00000000 00000000
+$ 4 : 00000000 00000000 00000001 00000001
+$ 8 : 00000001 0000032c 81c54700 00000001
+$12 : 0000032d 0000000f 00000000 ffffffff
+$16 : 81c14c00 00000001 802dac74 80195f98
+$20 : 802ea050 00000000 00000000 00000000
+$24 : 00000003 800617f0
+$28 : 81c20000 81c21e70 00000000 802e78a4
+Hi : 00000000
+Lo : 4190ab00
+epc : 802daca0 0x802daca0
+ Not tainted
+ra : 802e78a4 0x802e78a4
+Status: 1000c003 KERNEL EXL IE
+Cause : 00800008
+BadVA : 00000000
+PrId : 00019374 (MIPS 24Kc)
+Modules linked in:
+Process swapper (pid: 1, threadinfo=81c20000, task=81c18000, tls=00000000)
+Stack : 00000000 8027d5d8 802e8ae0 00000000 01000000 802e8b5c 81c50600 00000000
+ 802ff290 00000000 80420000 802ea0bc 00000000 00000000 80420000 802ff290
+ 80420000 80060930 33390000 00000000 00002308 80140a80 00000028 802d0000
+ 00000000 800ba024 802ff004 802ff0c8 802ff290 00000000 00000000 00000000
+ 00000000 802d897c 01234567 7f827068 00000000 0045f798 00460000 00000000
+
+This can be avoided by calling the 'ar724x_pci_add_data'
+function from the board specific setup code. However it
+makes no sense to use that function for every board,
+especially when the board does not needs to set the
+platform_data field of any PCI device.
+
+The patch allows the board setup code to specify a board
+specific function if that is required.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+
+v2: - no changes
+
+The pci_irq_map function can throw another NULL pointer
+dereference, that will be fixed in a subsequent patch.
+---
+ arch/mips/ath79/mach-ubnt-xm.c | 13 ++++++++++++-
+ arch/mips/ath79/pci.c | 14 ++++++++------
+ arch/mips/ath79/pci.h | 4 +++-
+ 3 files changed, 23 insertions(+), 8 deletions(-)
+
+--- a/arch/mips/ath79/mach-ubnt-xm.c
++++ b/arch/mips/ath79/mach-ubnt-xm.c
+@@ -85,16 +85,27 @@ static struct ath9k_platform_data ubnt_x
+ static struct ar724x_pci_data ubnt_xm_pci_data[] = {
+ {
+ .irq = ATH79_PCI_IRQ(0),
+- .pdata = &ubnt_xm_eeprom_data,
+ },
+ };
+
++static int ubnt_xm_pci_plat_dev_init(struct pci_dev *dev)
++{
++ switch (PCI_SLOT(dev->devfn)) {
++ case 0:
++ dev->dev.platform_data = &ubnt_xm_eeprom_data;
++ break;
++ }
++
++ return 0;
++}
++
+ static void __init ubnt_xm_pci_init(void)
+ {
+ memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
+ sizeof(ubnt_xm_eeprom_data.eeprom_data));
+
+ ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data));
++ ath79_pci_set_plat_dev_init(ubnt_xm_pci_plat_dev_init);
+ ath79_register_pci();
+ }
+ #else
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -14,6 +14,7 @@
+ #include <asm/mach-ath79/pci.h>
+ #include "pci.h"
+
++static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev);
+ static struct ar724x_pci_data *pci_data;
+ static int pci_data_size;
+
+@@ -38,14 +39,15 @@ int __init pcibios_map_irq(const struct
+
+ int pcibios_plat_dev_init(struct pci_dev *dev)
+ {
+- unsigned int devfn = dev->devfn;
+-
+- if (devfn > pci_data_size - 1)
+- return PCIBIOS_DEVICE_NOT_FOUND;
++ if (ath79_pci_plat_dev_init)
++ return ath79_pci_plat_dev_init(dev);
+
+- dev->dev.platform_data = pci_data[devfn].pdata;
++ return 0;
++}
+
+- return PCIBIOS_SUCCESSFUL;
++void __init ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev))
++{
++ ath79_pci_plat_dev_init = func;
+ }
+
+ int __init ath79_register_pci(void)
+--- a/arch/mips/ath79/pci.h
++++ b/arch/mips/ath79/pci.h
+@@ -13,14 +13,16 @@
+
+ struct ar724x_pci_data {
+ int irq;
+- void *pdata;
+ };
+
+ void ar724x_pci_add_data(struct ar724x_pci_data *data, int size);
+
+ #ifdef CONFIG_PCI
++void ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev));
+ int ath79_register_pci(void);
+ #else
++static inline void
++ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *)) {}
+ static inline int ath79_register_pci(void) { return 0; }
+ #endif
+
--- /dev/null
+From 9f6d46372cf2a493eaeeffbefe0a796379f838fa Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Tue, 22 Nov 2011 22:54:32 +0100
+Subject: [PATCH 16/35] MIPS: ath79: add support for the PCI host controller of the AR71XX SoCs
+
+The Atheros AR71XX SoCs have a built-in PCI Host Controller.
+This patch adds a driver for that, and modifies the relevant
+files in order to allow to register the PCI controller from
+board specific setup.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
+
+v2: - add missing pci-ar71xx.c
+---
+ arch/mips/ath79/Kconfig | 1 +
+ arch/mips/include/asm/mach-ath79/pci.h | 6 +
+ arch/mips/pci/Makefile | 1 +
+ arch/mips/pci/pci-ar71xx.c | 375 ++++++++++++++++++++++++++++++++
+ 4 files changed, 383 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/pci/pci-ar71xx.c
+
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -52,6 +52,7 @@ endmenu
+ config SOC_AR71XX
+ select USB_ARCH_HAS_EHCI
+ select USB_ARCH_HAS_OHCI
++ select HW_HAS_PCI
+ def_bool n
+
+ config SOC_AR724X
+--- a/arch/mips/include/asm/mach-ath79/pci.h
++++ b/arch/mips/include/asm/mach-ath79/pci.h
+@@ -11,6 +11,12 @@
+ #ifndef __ASM_MACH_ATH79_PCI_H
+ #define __ASM_MACH_ATH79_PCI_H
+
++#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR71XX)
++int ar71xx_pcibios_init(void);
++#else
++static inline int ar71xx_pcibios_init(void) { return 0 };
++#endif
++
+ #if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X)
+ int ar724x_pcibios_init(int irq);
+ #else
+--- a/arch/mips/pci/Makefile
++++ b/arch/mips/pci/Makefile
+@@ -19,6 +19,7 @@ obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
+ obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
+ ops-bcm63xx.o
+ obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
++obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o
+ obj-$(CONFIG_SOC_AR724X) += pci-ar724x.o
+
+ #
+--- /dev/null
++++ b/arch/mips/pci/pci-ar71xx.c
+@@ -0,0 +1,375 @@
++/*
++ * Atheros AR71xx PCI host controller driver
++ *
++ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ *
++ * Parts of this file are based on Atheros' 2.6.15 BSP
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
++
++#include <linux/resource.h>
++#include <linux/types.h>
++#include <linux/delay.h>
++#include <linux/bitops.h>
++#include <linux/pci.h>
++#include <linux/pci_regs.h>
++#include <linux/interrupt.h>
++
++#include <asm/mach-ath79/ar71xx_regs.h>
++#include <asm/mach-ath79/ath79.h>
++#include <asm/mach-ath79/pci.h>
++
++#define AR71XX_PCI_MEM_BASE 0x10000000
++#define AR71XX_PCI_MEM_SIZE 0x08000000
++
++#define AR71XX_PCI_WIN0_OFFS 0x10000000
++#define AR71XX_PCI_WIN1_OFFS 0x11000000
++#define AR71XX_PCI_WIN2_OFFS 0x12000000
++#define AR71XX_PCI_WIN3_OFFS 0x13000000
++#define AR71XX_PCI_WIN4_OFFS 0x14000000
++#define AR71XX_PCI_WIN5_OFFS 0x15000000
++#define AR71XX_PCI_WIN6_OFFS 0x16000000
++#define AR71XX_PCI_WIN7_OFFS 0x07000000
++
++#define AR71XX_PCI_CFG_BASE \
++ (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
++#define AR71XX_PCI_CFG_SIZE 0x100
++
++#define AR71XX_PCI_REG_CRP_AD_CBE 0x00
++#define AR71XX_PCI_REG_CRP_WRDATA 0x04
++#define AR71XX_PCI_REG_CRP_RDDATA 0x08
++#define AR71XX_PCI_REG_CFG_AD 0x0c
++#define AR71XX_PCI_REG_CFG_CBE 0x10
++#define AR71XX_PCI_REG_CFG_WRDATA 0x14
++#define AR71XX_PCI_REG_CFG_RDDATA 0x18
++#define AR71XX_PCI_REG_PCI_ERR 0x1c
++#define AR71XX_PCI_REG_PCI_ERR_ADDR 0x20
++#define AR71XX_PCI_REG_AHB_ERR 0x24
++#define AR71XX_PCI_REG_AHB_ERR_ADDR 0x28
++
++#define AR71XX_PCI_CRP_CMD_WRITE 0x00010000
++#define AR71XX_PCI_CRP_CMD_READ 0x00000000
++#define AR71XX_PCI_CFG_CMD_READ 0x0000000a
++#define AR71XX_PCI_CFG_CMD_WRITE 0x0000000b
++
++#define AR71XX_PCI_INT_CORE BIT(4)
++#define AR71XX_PCI_INT_DEV2 BIT(2)
++#define AR71XX_PCI_INT_DEV1 BIT(1)
++#define AR71XX_PCI_INT_DEV0 BIT(0)
++
++#define AR71XX_PCI_IRQ_COUNT 5
++
++static DEFINE_SPINLOCK(ar71xx_pci_lock);
++static void __iomem *ar71xx_pcicfg_base;
++
++/* Byte lane enable bits */
++static const u8 ar71xx_pci_ble_table[4][4] = {
++ {0x0, 0xf, 0xf, 0xf},
++ {0xe, 0xd, 0xb, 0x7},
++ {0xc, 0xf, 0x3, 0xf},
++ {0xf, 0xf, 0xf, 0xf},
++};
++
++static const u32 ar71xx_pci_read_mask[8] = {
++ 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0
++};
++
++static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
++{
++ u32 t;
++
++ t = ar71xx_pci_ble_table[size & 3][where & 3];
++ BUG_ON(t == 0xf);
++ t <<= (local) ? 20 : 4;
++
++ return t;
++}
++
++static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn,
++ int where)
++{
++ u32 ret;
++
++ if (!bus->number) {
++ /* type 0 */
++ ret = (1 << PCI_SLOT(devfn)) | (PCI_FUNC(devfn) << 8) |
++ (where & ~3);
++ } else {
++ /* type 1 */
++ ret = (bus->number << 16) | (PCI_SLOT(devfn) << 11) |
++ (PCI_FUNC(devfn) << 8) | (where & ~3) | 1;
++ }
++
++ return ret;
++}
++
++static int ar71xx_pci_check_error(int quiet)
++{
++ void __iomem *base = ar71xx_pcicfg_base;
++ u32 pci_err;
++ u32 ahb_err;
++
++ pci_err = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR) & 3;
++ if (pci_err) {
++ if (!quiet) {
++ u32 addr;
++
++ addr = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR_ADDR);
++ pr_crit("ar71xx: %s bus error %d at addr 0x%x\n",
++ "PCI", pci_err, addr);
++ }
++
++ /* clear PCI error status */
++ __raw_writel(pci_err, base + AR71XX_PCI_REG_PCI_ERR);
++ }
++
++ ahb_err = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR) & 1;
++ if (ahb_err) {
++ if (!quiet) {
++ u32 addr;
++
++ addr = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR_ADDR);
++ pr_crit("ar71xx: %s bus error %d at addr 0x%x\n",
++ "AHB", ahb_err, addr);
++ }
++
++ /* clear AHB error status */
++ __raw_writel(ahb_err, base + AR71XX_PCI_REG_AHB_ERR);
++ }
++
++ return !!(ahb_err | pci_err);
++}
++
++static inline void ar71xx_pci_local_write(int where, int size, u32 value)
++{
++ void __iomem *base = ar71xx_pcicfg_base;
++ u32 ad_cbe;
++
++ value = value << (8 * (where & 3));
++
++ ad_cbe = AR71XX_PCI_CRP_CMD_WRITE | (where & ~3);
++ ad_cbe |= ar71xx_pci_get_ble(where, size, 1);
++
++ __raw_writel(ad_cbe, base + AR71XX_PCI_REG_CRP_AD_CBE);
++ __raw_writel(value, base + AR71XX_PCI_REG_CRP_WRDATA);
++}
++
++static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
++ unsigned int devfn,
++ int where, int size, u32 cmd)
++{
++ void __iomem *base = ar71xx_pcicfg_base;
++ u32 addr;
++
++ addr = ar71xx_pci_bus_addr(bus, devfn, where);
++
++ __raw_writel(addr, base + AR71XX_PCI_REG_CFG_AD);
++ __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0),
++ base + AR71XX_PCI_REG_CFG_CBE);
++
++ return ar71xx_pci_check_error(1);
++}
++
++static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
++ int where, int size, u32 *value)
++{
++ void __iomem *base = ar71xx_pcicfg_base;
++ unsigned long flags;
++ u32 data;
++ int err;
++ int ret;
++
++ ret = PCIBIOS_SUCCESSFUL;
++ data = ~0;
++
++ spin_lock_irqsave(&ar71xx_pci_lock, flags);
++
++ err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
++ AR71XX_PCI_CFG_CMD_READ);
++ if (err)
++ ret = PCIBIOS_DEVICE_NOT_FOUND;
++ else
++ data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA);
++
++ spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
++
++ *value = (data >> (8 * (where & 3))) & ar71xx_pci_read_mask[size & 7];
++
++ return ret;
++}
++
++static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
++ int where, int size, u32 value)
++{
++ void __iomem *base = ar71xx_pcicfg_base;
++ unsigned long flags;
++ int err;
++ int ret;
++
++ value = value << (8 * (where & 3));
++ ret = PCIBIOS_SUCCESSFUL;
++
++ spin_lock_irqsave(&ar71xx_pci_lock, flags);
++
++ err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
++ AR71XX_PCI_CFG_CMD_WRITE);
++ if (err)
++ ret = PCIBIOS_DEVICE_NOT_FOUND;
++ else
++ __raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA);
++
++ spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
++
++ return ret;
++}
++
++static struct pci_ops ar71xx_pci_ops = {
++ .read = ar71xx_pci_read_config,
++ .write = ar71xx_pci_write_config,
++};
++
++static struct resource ar71xx_pci_io_resource = {
++ .name = "PCI IO space",
++ .start = 0,
++ .end = 0,
++ .flags = IORESOURCE_IO,
++};
++
++static struct resource ar71xx_pci_mem_resource = {
++ .name = "PCI memory space",
++ .start = AR71XX_PCI_MEM_BASE,
++ .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1,
++ .flags = IORESOURCE_MEM
++};
++
++static struct pci_controller ar71xx_pci_controller = {
++ .pci_ops = &ar71xx_pci_ops,
++ .mem_resource = &ar71xx_pci_mem_resource,
++ .io_resource = &ar71xx_pci_io_resource,
++};
++
++static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
++{
++ void __iomem *base = ath79_reset_base;
++ u32 pending;
++
++ pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
++ __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
++
++ if (pending & AR71XX_PCI_INT_DEV0)
++ generic_handle_irq(ATH79_PCI_IRQ(0));
++
++ else if (pending & AR71XX_PCI_INT_DEV1)
++ generic_handle_irq(ATH79_PCI_IRQ(1));
++
++ else if (pending & AR71XX_PCI_INT_DEV2)
++ generic_handle_irq(ATH79_PCI_IRQ(2));
++
++ else if (pending & AR71XX_PCI_INT_CORE)
++ generic_handle_irq(ATH79_PCI_IRQ(4));
++
++ else
++ spurious_interrupt();
++}
++
++static void ar71xx_pci_irq_unmask(struct irq_data *d)
++{
++ unsigned int irq = d->irq - ATH79_PCI_IRQ_BASE;
++ void __iomem *base = ath79_reset_base;
++ u32 t;
++
++ t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
++ __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
++
++ /* flush write */
++ __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
++}
++
++static void ar71xx_pci_irq_mask(struct irq_data *d)
++{
++ unsigned int irq = d->irq - ATH79_PCI_IRQ_BASE;
++ void __iomem *base = ath79_reset_base;
++ u32 t;
++
++ t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
++ __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
++
++ /* flush write */
++ __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
++}
++
++static struct irq_chip ar71xx_pci_irq_chip = {
++ .name = "AR71XX PCI",
++ .irq_mask = ar71xx_pci_irq_mask,
++ .irq_unmask = ar71xx_pci_irq_unmask,
++ .irq_mask_ack = ar71xx_pci_irq_mask,
++};
++
++static __init void ar71xx_pci_irq_init(void)
++{
++ void __iomem *base = ath79_reset_base;
++ int i;
++
++ __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
++ __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
++
++ BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT);
++
++ for (i = ATH79_PCI_IRQ_BASE;
++ i < ATH79_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++)
++ irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
++ handle_level_irq);
++
++ irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar71xx_pci_irq_handler);
++}
++
++static __init void ar71xx_pci_reset(void)
++{
++ void __iomem *ddr_base = ath79_ddr_base;
++
++ ath79_device_reset_set(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE);
++ mdelay(100);
++
++ ath79_device_reset_clear(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE);
++ mdelay(100);
++
++ __raw_writel(AR71XX_PCI_WIN0_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN0);
++ __raw_writel(AR71XX_PCI_WIN1_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN1);
++ __raw_writel(AR71XX_PCI_WIN2_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN2);
++ __raw_writel(AR71XX_PCI_WIN3_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN3);
++ __raw_writel(AR71XX_PCI_WIN4_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN4);
++ __raw_writel(AR71XX_PCI_WIN5_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN5);
++ __raw_writel(AR71XX_PCI_WIN6_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN6);
++ __raw_writel(AR71XX_PCI_WIN7_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN7);
++
++ mdelay(100);
++}
++
++__init int ar71xx_pcibios_init(void)
++{
++ u32 t;
++
++ ar71xx_pcicfg_base = ioremap(AR71XX_PCI_CFG_BASE, AR71XX_PCI_CFG_SIZE);
++ if (ar71xx_pcicfg_base == NULL)
++ return -ENOMEM;
++
++ ar71xx_pci_reset();
++
++ /* setup COMMAND register */
++ t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
++ | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
++ ar71xx_pci_local_write(PCI_COMMAND, 4, t);
++
++ /* clear bus errors */
++ ar71xx_pci_check_error(1);
++
++ ar71xx_pci_irq_init();
++
++ register_pci_controller(&ar71xx_pci_controller);
++
++ return 0;
++}
--- /dev/null
+From 8a1a5852aa7f8cfc027b2b0bb51cbbac4309e144 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 20 Nov 2011 14:32:09 +0100
+Subject: [PATCH 17/35] MIPS: ath79: allow to use SoC specific PCI IRQ maps
+
+The PCI controllers in the AR71XX and in the
+AR724X SoCs are different, and both of them
+uses different IRQ wiring.
+
+The patch modifies the 'pcibios_map_irq' function
+in order to allow to use different IRQ maps for
+the different SoCs. The patch also adds a function,
+which lets the board setup code to override the
+default IRQ map.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+
+v2: - no changes
+---
+ arch/mips/ath79/pci.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++---
+ arch/mips/ath79/pci.h | 9 ++++++
+ 2 files changed, 77 insertions(+), 4 deletions(-)
+
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -8,6 +8,7 @@
+ * by the Free Software Foundation.
+ */
+
++#include <linux/init.h>
+ #include <linux/pci.h>
+ #include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/irq.h>
+@@ -15,9 +16,35 @@
+ #include "pci.h"
+
+ static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev);
++static const struct ath79_pci_irq *ath79_pci_irq_map __initdata;
++static unsigned ath79_pci_nr_irqs __initdata;
+ static struct ar724x_pci_data *pci_data;
+ static int pci_data_size;
+
++static const struct ath79_pci_irq ar71xx_pci_irq_map[] __initconst = {
++ {
++ .slot = 17,
++ .pin = 1,
++ .irq = ATH79_PCI_IRQ(0),
++ }, {
++ .slot = 18,
++ .pin = 1,
++ .irq = ATH79_PCI_IRQ(1),
++ }, {
++ .slot = 19,
++ .pin = 1,
++ .irq = ATH79_PCI_IRQ(2),
++ }
++};
++
++static const struct ath79_pci_irq ar724x_pci_irq_map[] __initconst = {
++ {
++ .slot = 0,
++ .pin = 1,
++ .irq = ATH79_PCI_IRQ(0),
++ }
++};
++
+ void ar724x_pci_add_data(struct ar724x_pci_data *data, int size)
+ {
+ pci_data = data;
+@@ -26,13 +53,40 @@ void ar724x_pci_add_data(struct ar724x_p
+
+ int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
+ {
+- unsigned int devfn = dev->devfn;
+ int irq = -1;
++ int i;
+
+- if (devfn > pci_data_size - 1)
+- return irq;
+-
+- irq = pci_data[devfn].irq;
++ if (ath79_pci_nr_irqs == 0 ||
++ ath79_pci_irq_map == NULL) {
++ if (soc_is_ar71xx()) {
++ ath79_pci_irq_map = ar71xx_pci_irq_map;
++ ath79_pci_nr_irqs = ARRAY_SIZE(ar71xx_pci_irq_map);
++ } else if (soc_is_ar724x()) {
++ ath79_pci_irq_map = ar724x_pci_irq_map;
++ ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
++ } else {
++ pr_crit("pci %s: invalid irq map\n",
++ pci_name((struct pci_dev *) dev));
++ return irq;
++ }
++ }
++
++ for (i = 0; i < ath79_pci_nr_irqs; i++) {
++ const struct ath79_pci_irq *entry;
++
++ entry = &ath79_pci_irq_map[i];
++ if (entry->slot == slot && entry->pin == pin) {
++ irq = entry->irq;
++ break;
++ }
++ }
++
++ if (irq < 0)
++ pr_crit("pci %s: no irq found for pin %u\n",
++ pci_name((struct pci_dev *) dev), pin);
++ else
++ pr_info("pci %s: using irq %d for pin %u\n",
++ pci_name((struct pci_dev *) dev), irq, pin);
+
+ return irq;
+ }
+@@ -45,6 +99,13 @@ int pcibios_plat_dev_init(struct pci_dev
+ return 0;
+ }
+
++void __init ath79_pci_set_irq_map(unsigned nr_irqs,
++ const struct ath79_pci_irq *map)
++{
++ ath79_pci_nr_irqs = nr_irqs;
++ ath79_pci_irq_map = map;
++}
++
+ void __init ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev))
+ {
+ ath79_pci_plat_dev_init = func;
+@@ -52,6 +113,9 @@ void __init ath79_pci_set_plat_dev_init(
+
+ int __init ath79_register_pci(void)
+ {
++ if (soc_is_ar71xx())
++ return ar71xx_pcibios_init();
++
+ if (soc_is_ar724x())
+ return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2);
+
+--- a/arch/mips/ath79/pci.h
++++ b/arch/mips/ath79/pci.h
+@@ -15,13 +15,22 @@ struct ar724x_pci_data {
+ int irq;
+ };
+
++struct ath79_pci_irq {
++ u8 slot;
++ u8 pin;
++ int irq;
++};
++
+ void ar724x_pci_add_data(struct ar724x_pci_data *data, int size);
+
+ #ifdef CONFIG_PCI
++void ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map);
+ void ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev));
+ int ath79_register_pci(void);
+ #else
+ static inline void
++ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map) {}
++static inline void
+ ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *)) {}
+ static inline int ath79_register_pci(void) { return 0; }
+ #endif
--- /dev/null
+From 0b026adc7a471edd018a060427e62d06e54be2bc Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 20 Nov 2011 15:50:32 +0100
+Subject: [PATCH 18/35] MIPS: ath79: remove ar724x_pci_add_data function
+
+The variables set by this function are not used anymore.
+Remove the function and the relevant variables as well.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+
+v2: - no changes
+---
+ arch/mips/ath79/mach-ubnt-xm.c | 7 -------
+ arch/mips/ath79/pci.c | 8 --------
+ arch/mips/ath79/pci.h | 6 ------
+ 3 files changed, 0 insertions(+), 21 deletions(-)
+
+--- a/arch/mips/ath79/mach-ubnt-xm.c
++++ b/arch/mips/ath79/mach-ubnt-xm.c
+@@ -82,12 +82,6 @@ static struct ath79_spi_platform_data ub
+ #ifdef CONFIG_PCI
+ static struct ath9k_platform_data ubnt_xm_eeprom_data;
+
+-static struct ar724x_pci_data ubnt_xm_pci_data[] = {
+- {
+- .irq = ATH79_PCI_IRQ(0),
+- },
+-};
+-
+ static int ubnt_xm_pci_plat_dev_init(struct pci_dev *dev)
+ {
+ switch (PCI_SLOT(dev->devfn)) {
+@@ -104,7 +98,6 @@ static void __init ubnt_xm_pci_init(void
+ memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
+ sizeof(ubnt_xm_eeprom_data.eeprom_data));
+
+- ar724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data));
+ ath79_pci_set_plat_dev_init(ubnt_xm_pci_plat_dev_init);
+ ath79_register_pci();
+ }
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -18,8 +18,6 @@
+ static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev);
+ static const struct ath79_pci_irq *ath79_pci_irq_map __initdata;
+ static unsigned ath79_pci_nr_irqs __initdata;
+-static struct ar724x_pci_data *pci_data;
+-static int pci_data_size;
+
+ static const struct ath79_pci_irq ar71xx_pci_irq_map[] __initconst = {
+ {
+@@ -45,12 +43,6 @@ static const struct ath79_pci_irq ar724x
+ }
+ };
+
+-void ar724x_pci_add_data(struct ar724x_pci_data *data, int size)
+-{
+- pci_data = data;
+- pci_data_size = size;
+-}
+-
+ int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
+ {
+ int irq = -1;
+--- a/arch/mips/ath79/pci.h
++++ b/arch/mips/ath79/pci.h
+@@ -11,18 +11,12 @@
+ #ifndef _ATH79_PCI_H
+ #define _ATH79_PCI_H
+
+-struct ar724x_pci_data {
+- int irq;
+-};
+-
+ struct ath79_pci_irq {
+ u8 slot;
+ u8 pin;
+ int irq;
+ };
+
+-void ar724x_pci_add_data(struct ar724x_pci_data *data, int size);
+-
+ #ifdef CONFIG_PCI
+ void ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map);
+ void ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev));
--- /dev/null
+From 1759a5bc87d0eb8dbb0d8a9794b336813057eb88 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Thu, 25 Nov 2010 17:59:28 +0100
+Subject: [PATCH 19/35] MIPS: ath79: register PCI controller on the PB44 board
+
+The PB44 reference board has two miniPCI slots. Register
+the PCI controller to make those usable.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+
+v2: - no changes
+---
+ arch/mips/ath79/mach-pb44.c | 2 ++
+ 1 files changed, 2 insertions(+), 0 deletions(-)
+
+--- a/arch/mips/ath79/mach-pb44.c
++++ b/arch/mips/ath79/mach-pb44.c
+@@ -19,6 +19,7 @@
+ #include "dev-leds-gpio.h"
+ #include "dev-spi.h"
+ #include "dev-usb.h"
++#include "pci.h"
+
+ #define PB44_GPIO_I2C_SCL 0
+ #define PB44_GPIO_I2C_SDA 1
+@@ -114,6 +115,7 @@ static void __init pb44_init(void)
+ ath79_register_spi(&pb44_spi_data, pb44_spi_info,
+ ARRAY_SIZE(pb44_spi_info));
+ ath79_register_usb();
++ ath79_register_pci();
+ }
+
+ MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board",
--- /dev/null
+From e83c294ff219ff709b8179cbff64f293199a6dad Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Tue, 22 Nov 2011 21:13:58 +0100
+Subject: [PATCH 20/35] MIPS: ath79: update copyright headers of PCI related files
+
+Add copyright records according to the recent changes in
+the PCI code. Also fix up the descriptions.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
+
+Just in case if someone is curious about why 2008 and 2009 years are
+present in this change:
+
+The recent PCI specific changes were based on an existing
+code which can be found in the OpenWrt repository, and we
+are working on that since 2008.
+
+v2: - no changes
+---
+ arch/mips/ath79/pci.c | 4 ++++
+ arch/mips/ath79/pci.h | 4 +++-
+ arch/mips/include/asm/mach-ath79/pci.h | 4 +++-
+ arch/mips/pci/pci-ar724x.c | 3 ++-
+ 4 files changed, 12 insertions(+), 3 deletions(-)
+
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -2,6 +2,10 @@
+ * Atheros AR71XX/AR724X specific PCI setup code
+ *
+ * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
++ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ *
++ * Parts of this file are based on Atheros' 2.6.15 BSP
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+--- a/arch/mips/ath79/pci.h
++++ b/arch/mips/ath79/pci.h
+@@ -1,7 +1,9 @@
+ /*
+- * Atheros 724x PCI support
++ * Atheros AR71XX/AR724X PCI support
+ *
+ * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
++ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+--- a/arch/mips/include/asm/mach-ath79/pci.h
++++ b/arch/mips/include/asm/mach-ath79/pci.h
+@@ -1,7 +1,9 @@
+ /*
+- * Atheros 724x PCI support
++ * Atheros AR71XX/AR724X PCI support
+ *
+ * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
++ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -1,7 +1,8 @@
+ /*
+- * Atheros 724x PCI support
++ * Atheros AR724X PCI host controller driver
+ *
+ * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
++ * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
--- /dev/null
+From f60aed87f838ecfa4033ff1f63f97d05359b3b51 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 11 Dec 2011 17:36:08 +0100
+Subject: [PATCH 21/35] MIPS: ath79: add early_printk support for AR934X
+
+The patch allows to see kernel messages on AR934X SoCs in
+early boot stage.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+ arch/mips/ath79/early_printk.c | 3 +++
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 6 +++++-
+ 2 files changed, 8 insertions(+), 1 deletions(-)
+
+--- a/arch/mips/ath79/early_printk.c
++++ b/arch/mips/ath79/early_printk.c
+@@ -71,6 +71,9 @@ static void prom_putchar_init(void)
+ case REV_ID_MAJOR_AR7241:
+ case REV_ID_MAJOR_AR7242:
+ case REV_ID_MAJOR_AR913X:
++ case REV_ID_MAJOR_AR9341:
++ case REV_ID_MAJOR_AR9342:
++ case REV_ID_MAJOR_AR9344:
+ _prom_putchar = prom_putchar_ar71xx;
+ break;
+
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -1,10 +1,11 @@
+ /*
+ * Atheros AR71XX/AR724X/AR913X SoC register definitions
+ *
++ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
+ * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+- * Parts of this file are based on Atheros' 2.6.15 BSP
++ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+@@ -249,6 +250,9 @@
+ #define REV_ID_MAJOR_AR7242 0x1100
+ #define REV_ID_MAJOR_AR9330 0x0110
+ #define REV_ID_MAJOR_AR9331 0x1110
++#define REV_ID_MAJOR_AR9341 0x0120
++#define REV_ID_MAJOR_AR9342 0x1120
++#define REV_ID_MAJOR_AR9344 0x2120
+
+ #define AR71XX_REV_ID_MINOR_MASK 0x3
+ #define AR71XX_REV_ID_MINOR_AR7130 0x0
--- /dev/null
+From 655a57ed2df5e34c32645e08c3244facba70ae5f Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 9 Dec 2011 14:39:04 +0100
+Subject: [PATCH 22/35] MIPS: ath79: sort case statements in ath79_detect_sys_type
+
+Sort the case statements alphabetically in order to improve
+readability.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+ arch/mips/ath79/setup.c | 24 ++++++++++++------------
+ 1 files changed, 12 insertions(+), 12 deletions(-)
+
+--- a/arch/mips/ath79/setup.c
++++ b/arch/mips/ath79/setup.c
+@@ -116,18 +116,6 @@ static void __init ath79_detect_sys_type
+ rev = id & AR724X_REV_ID_REVISION_MASK;
+ break;
+
+- case REV_ID_MAJOR_AR9330:
+- ath79_soc = ATH79_SOC_AR9330;
+- chip = "9330";
+- rev = id & AR933X_REV_ID_REVISION_MASK;
+- break;
+-
+- case REV_ID_MAJOR_AR9331:
+- ath79_soc = ATH79_SOC_AR9331;
+- chip = "9331";
+- rev = id & AR933X_REV_ID_REVISION_MASK;
+- break;
+-
+ case REV_ID_MAJOR_AR913X:
+ minor = id & AR913X_REV_ID_MINOR_MASK;
+ rev = id >> AR913X_REV_ID_REVISION_SHIFT;
+@@ -145,6 +133,18 @@ static void __init ath79_detect_sys_type
+ }
+ break;
+
++ case REV_ID_MAJOR_AR9330:
++ ath79_soc = ATH79_SOC_AR9330;
++ chip = "9330";
++ rev = id & AR933X_REV_ID_REVISION_MASK;
++ break;
++
++ case REV_ID_MAJOR_AR9331:
++ ath79_soc = ATH79_SOC_AR9331;
++ chip = "9331";
++ rev = id & AR933X_REV_ID_REVISION_MASK;
++ break;
++
+ default:
+ panic("ath79: unknown SoC, id:0x%08x\n", id);
+ }
--- /dev/null
+From 9c19e86a7eccf8efd159ba213290830164f33a71 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 11 Dec 2011 17:36:42 +0100
+Subject: [PATCH 23/35] MIPS: ath79: add SoC detection code for AR934X
+
+Also add 'soc_is_ar934[124x]' helper functions and a Kconfig
+symbol for the AR934X SoCs.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+ arch/mips/ath79/Kconfig | 4 ++++
+ arch/mips/ath79/setup.c | 21 ++++++++++++++++++++-
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 ++
+ arch/mips/include/asm/mach-ath79/ath79.h | 23 +++++++++++++++++++++++
+ 4 files changed, 49 insertions(+), 1 deletions(-)
+
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -69,6 +69,10 @@ config SOC_AR933X
+ select USB_ARCH_HAS_EHCI
+ def_bool n
+
++config SOC_AR934X
++ select USB_ARCH_HAS_EHCI
++ def_bool n
++
+ config ATH79_DEV_GPIO_BUTTONS
+ def_bool n
+
+--- a/arch/mips/ath79/setup.c
++++ b/arch/mips/ath79/setup.c
+@@ -1,10 +1,11 @@
+ /*
+ * Atheros AR71XX/AR724X/AR913X specific setup
+ *
++ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+- * Parts of this file are based on Atheros' 2.6.15 BSP
++ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+@@ -145,6 +146,24 @@ static void __init ath79_detect_sys_type
+ rev = id & AR933X_REV_ID_REVISION_MASK;
+ break;
+
++ case REV_ID_MAJOR_AR9341:
++ ath79_soc = ATH79_SOC_AR9341;
++ chip = "9341";
++ rev = id & AR934X_REV_ID_REVISION_MASK;
++ break;
++
++ case REV_ID_MAJOR_AR9342:
++ ath79_soc = ATH79_SOC_AR9342;
++ chip = "9342";
++ rev = id & AR934X_REV_ID_REVISION_MASK;
++ break;
++
++ case REV_ID_MAJOR_AR9344:
++ ath79_soc = ATH79_SOC_AR9344;
++ chip = "9344";
++ rev = id & AR934X_REV_ID_REVISION_MASK;
++ break;
++
+ default:
+ panic("ath79: unknown SoC, id:0x%08x\n", id);
+ }
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -271,6 +271,8 @@
+
+ #define AR724X_REV_ID_REVISION_MASK 0x3
+
++#define AR934X_REV_ID_REVISION_MASK 0xf
++
+ /*
+ * SPI block
+ */
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
++++ b/arch/mips/include/asm/mach-ath79/ath79.h
+@@ -29,6 +29,9 @@ enum ath79_soc_type {
+ ATH79_SOC_AR9132,
+ ATH79_SOC_AR9330,
+ ATH79_SOC_AR9331,
++ ATH79_SOC_AR9341,
++ ATH79_SOC_AR9342,
++ ATH79_SOC_AR9344,
+ };
+
+ extern enum ath79_soc_type ath79_soc;
+@@ -75,6 +78,26 @@ static inline int soc_is_ar933x(void)
+ ath79_soc == ATH79_SOC_AR9331);
+ }
+
++static inline int soc_is_ar9341(void)
++{
++ return (ath79_soc == ATH79_SOC_AR9341);
++}
++
++static inline int soc_is_ar9342(void)
++{
++ return (ath79_soc == ATH79_SOC_AR9342);
++}
++
++static inline int soc_is_ar9344(void)
++{
++ return (ath79_soc == ATH79_SOC_AR9344);
++}
++
++static inline int soc_is_ar934x(void)
++{
++ return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
++}
++
+ extern void __iomem *ath79_ddr_base;
+ extern void __iomem *ath79_pll_base;
+ extern void __iomem *ath79_reset_base;
--- /dev/null
+From 783addfa256e79892f889e95ec5cda34f4e91eb7 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 9 Dec 2011 20:36:32 +0100
+Subject: [PATCH 24/35] MIPS: ath79: add clock initialization code for AR934X
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+ arch/mips/ath79/clock.c | 81 ++++++++++++++++++++++++
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 53 +++++++++++++++
+ 2 files changed, 134 insertions(+), 0 deletions(-)
+
+--- a/arch/mips/ath79/clock.c
++++ b/arch/mips/ath79/clock.c
+@@ -1,8 +1,11 @@
+ /*
+ * Atheros AR71XX/AR724X/AR913X common routines
+ *
++ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
+ * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
+ *
++ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
++ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+@@ -163,6 +166,82 @@ static void __init ar933x_clocks_init(vo
+ ath79_uart_clk.rate = ath79_ref_clk.rate;
+ }
+
++static void __init ar934x_clocks_init(void)
++{
++ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
++ u32 cpu_pll, ddr_pll;
++ u32 bootstrap;
++
++ bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
++ if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
++ ath79_ref_clk.rate = 40 * 1000 * 1000;
++ else
++ ath79_ref_clk.rate = 25 * 1000 * 1000;
++
++ pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
++ out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
++ AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
++ ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
++ AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
++ nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
++ AR934X_PLL_CPU_CONFIG_NINT_MASK;
++ frac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
++ AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
++
++ cpu_pll = nint * ath79_ref_clk.rate / ref_div;
++ cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 6));
++ cpu_pll /= (1 << out_div);
++
++ pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
++ out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
++ AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
++ ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
++ AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
++ nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
++ AR934X_PLL_DDR_CONFIG_NINT_MASK;
++ frac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
++ AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
++
++ ddr_pll = nint * ath79_ref_clk.rate / ref_div;
++ ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 10));
++ ddr_pll /= (1 << out_div);
++
++ clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
++
++ postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
++ AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
++
++ if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
++ ath79_cpu_clk.rate = ath79_ref_clk.rate;
++ else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
++ ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);
++ else
++ ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);
++
++ postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
++ AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;
++
++ if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
++ ath79_ddr_clk.rate = ath79_ref_clk.rate;
++ else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
++ ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);
++ else
++ ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);
++
++ postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
++ AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;
++
++ if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
++ ath79_ahb_clk.rate = ath79_ref_clk.rate;
++ else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
++ ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
++ else
++ ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
++
++ ath79_wdt_clk.rate = ath79_ref_clk.rate;
++ ath79_uart_clk.rate = ath79_ref_clk.rate;
++}
++
+ void __init ath79_clocks_init(void)
+ {
+ if (soc_is_ar71xx())
+@@ -173,6 +252,8 @@ void __init ath79_clocks_init(void)
+ ar913x_clocks_init();
+ else if (soc_is_ar933x())
+ ar933x_clocks_init();
++ else if (soc_is_ar934x())
++ ar934x_clocks_init();
+ else
+ BUG();
+
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -151,6 +151,41 @@
+ #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15
+ #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
+
++#define AR934X_PLL_CPU_CONFIG_REG 0x00
++#define AR934X_PLL_DDR_CONFIG_REG 0x04
++#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
++
++#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
++#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
++#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6
++#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f
++#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
++#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
++#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
++#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
++
++#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
++#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
++#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10
++#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f
++#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
++#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
++#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
++#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
++
++#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
++#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
++#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
++#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5
++#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
++#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10
++#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
++#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15
++#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
++#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
++#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
++#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
++
+ /*
+ * USB_CONFIG block
+ */
+@@ -186,6 +221,8 @@
+ #define AR933X_RESET_REG_RESET_MODULE 0x1c
+ #define AR933X_RESET_REG_BOOTSTRAP 0xac
+
++#define AR934X_RESET_REG_BOOTSTRAP 0xb0
++
+ #define MISC_INT_ETHSW BIT(12)
+ #define MISC_INT_TIMER4 BIT(10)
+ #define MISC_INT_TIMER3 BIT(9)
+@@ -242,6 +279,22 @@
+
+ #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
+
++#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
++#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22)
++#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21)
++#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20)
++#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19)
++#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18)
++#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17)
++#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16)
++#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7)
++#define AR934X_BOOTSTRAP_PCIE_RC BIT(6)
++#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5)
++#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4)
++#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2)
++#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
++#define AR934X_BOOTSTRAP_DDR1 BIT(0)
++
+ #define REV_ID_MAJOR_MASK 0xfff0
+ #define REV_ID_MAJOR_AR71XX 0x00a0
+ #define REV_ID_MAJOR_AR913X 0x00b0
--- /dev/null
+From c01b6005cfa2d762c2de33d5be2e82f91afaa66f Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 9 Dec 2011 20:53:47 +0100
+Subject: [PATCH 25/35] MIPS: ath79: add GPIO support code for AR934X
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+ arch/mips/ath79/gpio.c | 47 +++++++++++++++++++++++-
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 +
+ 2 files changed, 47 insertions(+), 1 deletions(-)
+
+--- a/arch/mips/ath79/gpio.c
++++ b/arch/mips/ath79/gpio.c
+@@ -1,9 +1,12 @@
+ /*
+ * Atheros AR71XX/AR724X/AR913X GPIO API support
+ *
+- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
++ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
++ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
++ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+@@ -89,6 +92,42 @@ static int ath79_gpio_direction_output(s
+ return 0;
+ }
+
++static int ar934x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
++{
++ void __iomem *base = ath79_gpio_base;
++ unsigned long flags;
++
++ spin_lock_irqsave(&ath79_gpio_lock, flags);
++
++ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset),
++ base + AR71XX_GPIO_REG_OE);
++
++ spin_unlock_irqrestore(&ath79_gpio_lock, flags);
++
++ return 0;
++}
++
++static int ar934x_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
++ int value)
++{
++ void __iomem *base = ath79_gpio_base;
++ unsigned long flags;
++
++ spin_lock_irqsave(&ath79_gpio_lock, flags);
++
++ if (value)
++ __raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET);
++ else
++ __raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR);
++
++ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset),
++ base + AR71XX_GPIO_REG_OE);
++
++ spin_unlock_irqrestore(&ath79_gpio_lock, flags);
++
++ return 0;
++}
++
+ static struct gpio_chip ath79_gpio_chip = {
+ .label = "ath79",
+ .get = ath79_gpio_get_value,
+@@ -155,11 +194,17 @@ void __init ath79_gpio_init(void)
+ ath79_gpio_count = AR913X_GPIO_COUNT;
+ else if (soc_is_ar933x())
+ ath79_gpio_count = AR933X_GPIO_COUNT;
++ else if (soc_is_ar934x())
++ ath79_gpio_count = AR934X_GPIO_COUNT;
+ else
+ BUG();
+
+ ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
+ ath79_gpio_chip.ngpio = ath79_gpio_count;
++ if (soc_is_ar934x()) {
++ ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
++ ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
++ }
+
+ err = gpiochip_add(&ath79_gpio_chip);
+ if (err)
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -367,5 +367,6 @@
+ #define AR724X_GPIO_COUNT 18
+ #define AR913X_GPIO_COUNT 22
+ #define AR933X_GPIO_COUNT 30
++#define AR934X_GPIO_COUNT 23
+
+ #endif /* __ASM_MACH_AR71XX_REGS_H */
--- /dev/null
+From e69d89040d4884ea4069352338f555694e65fe70 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 9 Dec 2011 21:30:03 +0100
+Subject: [PATCH 26/35] MIPS: ath79: rework IP2/IP3 interrupt handling
+
+The current implementation assumes that flushing the
+DDR writeback buffer is required for IP2/IP3 interrupts,
+however this is not true for all SoCs.
+
+Use SoC specific IP2/IP3 handlers instead of flushing
+the buffers in the dispatcher code.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+ arch/mips/ath79/irq.c | 92 ++++++++++++++++++++++++++++++++++++++-----------
+ 1 files changed, 72 insertions(+), 20 deletions(-)
+
+--- a/arch/mips/ath79/irq.c
++++ b/arch/mips/ath79/irq.c
+@@ -1,7 +1,7 @@
+ /*
+ * Atheros AR71xx/AR724x/AR913x specific interrupt handling
+ *
+- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * Parts of this file are based on Atheros' 2.6.15 BSP
+@@ -23,8 +23,8 @@
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include "common.h"
+
+-static unsigned int ath79_ip2_flush_reg;
+-static unsigned int ath79_ip3_flush_reg;
++static void (*ath79_ip2_handler)(void);
++static void (*ath79_ip3_handler)(void);
+
+ static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
+ {
+@@ -152,10 +152,8 @@ asmlinkage void plat_irq_dispatch(void)
+ if (pending & STATUSF_IP7)
+ do_IRQ(ATH79_CPU_IRQ_TIMER);
+
+- else if (pending & STATUSF_IP2) {
+- ath79_ddr_wb_flush(ath79_ip2_flush_reg);
+- do_IRQ(ATH79_CPU_IRQ_IP2);
+- }
++ else if (pending & STATUSF_IP2)
++ ath79_ip2_handler();
+
+ else if (pending & STATUSF_IP4)
+ do_IRQ(ATH79_CPU_IRQ_GE0);
+@@ -163,10 +161,8 @@ asmlinkage void plat_irq_dispatch(void)
+ else if (pending & STATUSF_IP5)
+ do_IRQ(ATH79_CPU_IRQ_GE1);
+
+- else if (pending & STATUSF_IP3) {
+- ath79_ddr_wb_flush(ath79_ip3_flush_reg);
+- do_IRQ(ATH79_CPU_IRQ_USB);
+- }
++ else if (pending & STATUSF_IP3)
++ ath79_ip3_handler();
+
+ else if (pending & STATUSF_IP6)
+ do_IRQ(ATH79_CPU_IRQ_MISC);
+@@ -175,22 +171,78 @@ asmlinkage void plat_irq_dispatch(void)
+ spurious_interrupt();
+ }
+
++/*
++ * The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for
++ * these devices typically allocate coherent DMA memory, however the
++ * DMA controller may still have some unsynchronized data in the FIFO.
++ * Issue a flush in the handlers to ensure that the driver sees
++ * the update.
++ */
++static void ar71xx_ip2_handler(void)
++{
++ ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI);
++ do_IRQ(ATH79_CPU_IRQ_IP2);
++}
++
++static void ar724x_ip2_handler(void)
++{
++ ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_PCIE);
++ do_IRQ(ATH79_CPU_IRQ_IP2);
++}
++
++static void ar913x_ip2_handler(void)
++{
++ ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_WMAC);
++ do_IRQ(ATH79_CPU_IRQ_IP2);
++}
++
++static void ar933x_ip2_handler(void)
++{
++ ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_WMAC);
++ do_IRQ(ATH79_CPU_IRQ_IP2);
++}
++
++static void ar71xx_ip3_handler(void)
++{
++ ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB);
++ do_IRQ(ATH79_CPU_IRQ_USB);
++}
++
++static void ar724x_ip3_handler(void)
++{
++ ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_USB);
++ do_IRQ(ATH79_CPU_IRQ_USB);
++}
++
++static void ar913x_ip3_handler(void)
++{
++ ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_USB);
++ do_IRQ(ATH79_CPU_IRQ_USB);
++}
++
++static void ar933x_ip3_handler(void)
++{
++ ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_USB);
++ do_IRQ(ATH79_CPU_IRQ_USB);
++}
++
+ void __init arch_init_irq(void)
+ {
+ if (soc_is_ar71xx()) {
+- ath79_ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI;
+- ath79_ip3_flush_reg = AR71XX_DDR_REG_FLUSH_USB;
++ ath79_ip2_handler = ar71xx_ip2_handler;
++ ath79_ip3_handler = ar71xx_ip3_handler;
+ } else if (soc_is_ar724x()) {
+- ath79_ip2_flush_reg = AR724X_DDR_REG_FLUSH_PCIE;
+- ath79_ip3_flush_reg = AR724X_DDR_REG_FLUSH_USB;
++ ath79_ip2_handler = ar724x_ip2_handler;
++ ath79_ip3_handler = ar724x_ip3_handler;
+ } else if (soc_is_ar913x()) {
+- ath79_ip2_flush_reg = AR913X_DDR_REG_FLUSH_WMAC;
+- ath79_ip3_flush_reg = AR913X_DDR_REG_FLUSH_USB;
++ ath79_ip2_handler = ar913x_ip2_handler;
++ ath79_ip3_handler = ar913x_ip3_handler;
+ } else if (soc_is_ar933x()) {
+- ath79_ip2_flush_reg = AR933X_DDR_REG_FLUSH_WMAC;
+- ath79_ip3_flush_reg = AR933X_DDR_REG_FLUSH_USB;
+- } else
++ ath79_ip2_handler = ar933x_ip2_handler;
++ ath79_ip3_handler = ar933x_ip3_handler;
++ } else {
+ BUG();
++ }
+
+ cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC;
+ mips_cpu_irq_init();
--- /dev/null
+From 9db6021011556948d2d28d6957cee451bc2985aa Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 9 Dec 2011 21:59:50 +0100
+Subject: [PATCH 27/35] MIPS: ath79: add IRQ handling code for AR934X
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+ arch/mips/ath79/irq.c | 55 +++++++++++++++++++++++-
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 25 +++++++++++
+ arch/mips/include/asm/mach-ath79/irq.h | 6 ++-
+ 3 files changed, 83 insertions(+), 3 deletions(-)
+
+--- a/arch/mips/ath79/irq.c
++++ b/arch/mips/ath79/irq.c
+@@ -1,10 +1,11 @@
+ /*
+ * Atheros AR71xx/AR724x/AR913x specific interrupt handling
+ *
++ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+- * Parts of this file are based on Atheros' 2.6.15 BSP
++ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+@@ -129,7 +130,7 @@ static void __init ath79_misc_irq_init(v
+
+ if (soc_is_ar71xx() || soc_is_ar913x())
+ ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
+- else if (soc_is_ar724x() || soc_is_ar933x())
++ else if (soc_is_ar724x() || soc_is_ar933x() || soc_is_ar934x())
+ ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
+ else
+ BUG();
+@@ -143,6 +144,39 @@ static void __init ath79_misc_irq_init(v
+ irq_set_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler);
+ }
+
++static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
++{
++ u32 status;
++
++ disable_irq_nosync(irq);
++
++ status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
++
++ if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) {
++ ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_PCIE);
++ generic_handle_irq(ATH79_IP2_IRQ(0));
++ } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) {
++ ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_WMAC);
++ generic_handle_irq(ATH79_IP2_IRQ(1));
++ } else {
++ spurious_interrupt();
++ }
++
++ enable_irq(irq);
++}
++
++static void ar934x_ip2_irq_init(void)
++{
++ int i;
++
++ for (i = ATH79_IP2_IRQ_BASE;
++ i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
++ irq_set_chip_and_handler(i, &dummy_irq_chip,
++ handle_level_irq);
++
++ irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar934x_ip2_irq_dispatch);
++}
++
+ asmlinkage void plat_irq_dispatch(void)
+ {
+ unsigned long pending;
+@@ -202,6 +236,11 @@ static void ar933x_ip2_handler(void)
+ do_IRQ(ATH79_CPU_IRQ_IP2);
+ }
+
++static void ar934x_ip2_handler(void)
++{
++ do_IRQ(ATH79_CPU_IRQ_IP2);
++}
++
+ static void ar71xx_ip3_handler(void)
+ {
+ ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB);
+@@ -226,6 +265,12 @@ static void ar933x_ip3_handler(void)
+ do_IRQ(ATH79_CPU_IRQ_USB);
+ }
+
++static void ar934x_ip3_handler(void)
++{
++ ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_USB);
++ do_IRQ(ATH79_CPU_IRQ_USB);
++}
++
+ void __init arch_init_irq(void)
+ {
+ if (soc_is_ar71xx()) {
+@@ -240,6 +285,9 @@ void __init arch_init_irq(void)
+ } else if (soc_is_ar933x()) {
+ ath79_ip2_handler = ar933x_ip2_handler;
+ ath79_ip3_handler = ar933x_ip3_handler;
++ } else if (soc_is_ar934x()) {
++ ath79_ip2_handler = ar934x_ip2_handler;
++ ath79_ip3_handler = ar934x_ip3_handler;
+ } else {
+ BUG();
+ }
+@@ -247,4 +295,7 @@ void __init arch_init_irq(void)
+ cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC;
+ mips_cpu_irq_init();
+ ath79_misc_irq_init();
++
++ if (soc_is_ar934x())
++ ar934x_ip2_irq_init();
+ }
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -92,6 +92,12 @@
+ #define AR933X_DDR_REG_FLUSH_USB 0x84
+ #define AR933X_DDR_REG_FLUSH_WMAC 0x88
+
++#define AR934X_DDR_REG_FLUSH_GE0 0x9c
++#define AR934X_DDR_REG_FLUSH_GE1 0xa0
++#define AR934X_DDR_REG_FLUSH_USB 0xa4
++#define AR934X_DDR_REG_FLUSH_PCIE 0xa8
++#define AR934X_DDR_REG_FLUSH_WMAC 0xac
++
+ /*
+ * PLL block
+ */
+@@ -222,6 +228,7 @@
+ #define AR933X_RESET_REG_BOOTSTRAP 0xac
+
+ #define AR934X_RESET_REG_BOOTSTRAP 0xb0
++#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
+
+ #define MISC_INT_ETHSW BIT(12)
+ #define MISC_INT_TIMER4 BIT(10)
+@@ -295,6 +302,24 @@
+ #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
+ #define AR934X_BOOTSTRAP_DDR1 BIT(0)
+
++#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
++#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
++#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
++#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
++#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4)
++#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
++#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
++#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
++#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
++#define AR934X_PCIE_WMAC_INT_WMAC_ALL \
++ (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
++ AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)
++
++#define AR934X_PCIE_WMAC_INT_PCIE_ALL \
++ (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
++ AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
++ AR934X_PCIE_WMAC_INT_PCIE_RC3)
++
+ #define REV_ID_MAJOR_MASK 0xfff0
+ #define REV_ID_MAJOR_AR71XX 0x00a0
+ #define REV_ID_MAJOR_AR913X 0x00b0
+--- a/arch/mips/include/asm/mach-ath79/irq.h
++++ b/arch/mips/include/asm/mach-ath79/irq.h
+@@ -10,7 +10,7 @@
+ #define __ASM_MACH_ATH79_IRQ_H
+
+ #define MIPS_CPU_IRQ_BASE 0
+-#define NR_IRQS 46
++#define NR_IRQS 48
+
+ #define ATH79_MISC_IRQ_BASE 8
+ #define ATH79_MISC_IRQ_COUNT 32
+@@ -19,6 +19,10 @@
+ #define ATH79_PCI_IRQ_COUNT 6
+ #define ATH79_PCI_IRQ(_x) (ATH79_PCI_IRQ_BASE + (_x))
+
++#define ATH79_IP2_IRQ_BASE (ATH79_PCI_IRQ_BASE + ATH79_PCI_IRQ_COUNT)
++#define ATH79_IP2_IRQ_COUNT 2
++#define ATH79_IP2_IRQ(_x) (ATH79_IP2_IRQ_BASE + (_x))
++
+ #define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2)
+ #define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3)
+ #define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4)
--- /dev/null
+From da0f20f8a99de9193fc484a25d1f9edc913c98fd Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sat, 10 Dec 2011 20:09:39 +0100
+Subject: [PATCH 28/35] MIPS: ath79: add AR934X specific glue to ath79_device_reset_{clear,set}
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+ arch/mips/ath79/common.c | 9 ++++++++-
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 +
+ 2 files changed, 9 insertions(+), 1 deletions(-)
+
+--- a/arch/mips/ath79/common.c
++++ b/arch/mips/ath79/common.c
+@@ -1,9 +1,12 @@
+ /*
+ * Atheros AR71XX/AR724X/AR913X common routines
+ *
+- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
++ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
++ * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
++ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+@@ -67,6 +70,8 @@ void ath79_device_reset_set(u32 mask)
+ reg = AR913X_RESET_REG_RESET_MODULE;
+ else if (soc_is_ar933x())
+ reg = AR933X_RESET_REG_RESET_MODULE;
++ else if (soc_is_ar934x())
++ reg = AR934X_RESET_REG_RESET_MODULE;
+ else
+ BUG();
+
+@@ -91,6 +96,8 @@ void ath79_device_reset_clear(u32 mask)
+ reg = AR913X_RESET_REG_RESET_MODULE;
+ else if (soc_is_ar933x())
+ reg = AR933X_RESET_REG_RESET_MODULE;
++ else if (soc_is_ar934x())
++ reg = AR934X_RESET_REG_RESET_MODULE;
+ else
+ BUG();
+
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -227,6 +227,7 @@
+ #define AR933X_RESET_REG_RESET_MODULE 0x1c
+ #define AR933X_RESET_REG_BOOTSTRAP 0xac
+
++#define AR934X_RESET_REG_RESET_MODULE 0x1c
+ #define AR934X_RESET_REG_BOOTSTRAP 0xb0
+ #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
+
--- /dev/null
+From 6b6803a249a27aa708bc5f24aa15270e30f3de61 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sat, 10 Dec 2011 19:55:05 +0100
+Subject: [PATCH 29/35] MIPS: ath79: register UART device for AR934X SoCs
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+ arch/mips/ath79/dev-common.c | 3 ++-
+ 1 files changed, 2 insertions(+), 1 deletions(-)
+
+--- a/arch/mips/ath79/dev-common.c
++++ b/arch/mips/ath79/dev-common.c
+@@ -89,7 +89,8 @@ void __init ath79_register_uart(void)
+
+ if (soc_is_ar71xx() ||
+ soc_is_ar724x() ||
+- soc_is_ar913x()) {
++ soc_is_ar913x() ||
++ soc_is_ar934x()) {
+ ath79_uart_data[0].uartclk = clk_get_rate(clk);
+ platform_device_register(&ath79_uart_device);
+ } else if (soc_is_ar933x()) {
--- /dev/null
+From 58b69cf52387a7351ec13b52d3d6a495fe611c29 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 9 Dec 2011 22:07:23 +0100
+Subject: [PATCH 30/35] MIPS: ath79: add WMAC registration code for AR934X
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+ arch/mips/ath79/Kconfig | 2 +-
+ arch/mips/ath79/dev-wmac.c | 30 ++++++++++++++++++++++-
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 3 ++
+ 3 files changed, 32 insertions(+), 3 deletions(-)
+
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -86,7 +86,7 @@ config ATH79_DEV_USB
+ def_bool n
+
+ config ATH79_DEV_WMAC
+- depends on (SOC_AR913X || SOC_AR933X)
++ depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X)
+ def_bool n
+
+ endif
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -1,9 +1,12 @@
+ /*
+ * Atheros AR913X/AR933X SoC built-in WMAC device support
+ *
++ * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
++ * Parts of this file are based on Atheros 2.6.15/2.6.31 BSP
++ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+@@ -26,8 +29,7 @@ static struct resource ath79_wmac_resour
+ /* .start and .end fields are filled dynamically */
+ .flags = IORESOURCE_MEM,
+ }, {
+- .start = ATH79_CPU_IRQ_IP2,
+- .end = ATH79_CPU_IRQ_IP2,
++ /* .start and .end fields are filled dynamically */
+ .flags = IORESOURCE_IRQ,
+ },
+ };
+@@ -53,6 +55,8 @@ static void __init ar913x_wmac_setup(voi
+
+ ath79_wmac_resources[0].start = AR913X_WMAC_BASE;
+ ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
++ ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2;
++ ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2;
+ }
+
+
+@@ -79,6 +83,8 @@ static void __init ar933x_wmac_setup(voi
+
+ ath79_wmac_resources[0].start = AR933X_WMAC_BASE;
+ ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1;
++ ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2;
++ ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2;
+
+ t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
+ if (t & AR933X_BOOTSTRAP_REF_CLK_40)
+@@ -92,12 +98,32 @@ static void __init ar933x_wmac_setup(voi
+ ath79_wmac_data.external_reset = ar933x_wmac_reset;
+ }
+
++static void ar934x_wmac_setup(void)
++{
++ u32 t;
++
++ ath79_wmac_device.name = "ar934x_wmac";
++
++ ath79_wmac_resources[0].start = AR934X_WMAC_BASE;
++ ath79_wmac_resources[0].end = AR934X_WMAC_BASE + AR934X_WMAC_SIZE - 1;
++ ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
++ ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
++
++ t = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
++ if (t & AR934X_BOOTSTRAP_REF_CLK_40)
++ ath79_wmac_data.is_clk_25mhz = false;
++ else
++ ath79_wmac_data.is_clk_25mhz = true;
++}
++
+ void __init ath79_register_wmac(u8 *cal_data)
+ {
+ if (soc_is_ar913x())
+ ar913x_wmac_setup();
+ else if (soc_is_ar933x())
+ ar933x_wmac_setup();
++ else if (soc_is_ar934x())
++ ar934x_wmac_setup();
+ else
+ BUG();
+
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -61,6 +61,9 @@
+ #define AR933X_EHCI_BASE 0x1b000000
+ #define AR933X_EHCI_SIZE 0x1000
+
++#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
++#define AR934X_WMAC_SIZE 0x20000
++
+ /*
+ * DDR_CTRL block
+ */
--- /dev/null
+From 2d832612094b5592641364773c5ab2a3658f7120 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 11 Dec 2011 18:34:13 +0100
+Subject: [PATCH 31/35] MIPS: ath79: add USB platform setup code for AR934X
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+ arch/mips/ath79/dev-usb.c | 28 +++++++++++++++++++
+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 35 ++++++++++++++++++++++++
+ 2 files changed, 63 insertions(+), 0 deletions(-)
+
+--- a/arch/mips/ath79/dev-usb.c
++++ b/arch/mips/ath79/dev-usb.c
+@@ -180,6 +180,32 @@ static void __init ar933x_usb_setup(void
+ platform_device_register(&ath79_ehci_device);
+ }
+
++static void __init ar934x_usb_setup(void)
++{
++ u32 bootstrap;
++
++ bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
++ if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE)
++ return;
++
++ ath79_device_reset_clear(AR934X_RESET_USBSUS_OVERRIDE);
++ udelay(1000);
++
++ ath79_device_reset_set(AR934X_RESET_USB_PHY);
++ udelay(1000);
++
++ ath79_device_reset_set(AR934X_RESET_USB_PHY_ANALOG);
++ udelay(1000);
++
++ ath79_device_reset_set(AR934X_RESET_USB_HOST);
++ udelay(1000);
++
++ ath79_ehci_resources[0].start = AR934X_EHCI_BASE;
++ ath79_ehci_resources[0].end = AR934X_EHCI_BASE + AR934X_EHCI_SIZE - 1;
++ ath79_ehci_device.name = "ar934x-ehci";
++ platform_device_register(&ath79_ehci_device);
++}
++
+ void __init ath79_register_usb(void)
+ {
+ if (soc_is_ar71xx())
+@@ -192,6 +218,8 @@ void __init ath79_register_usb(void)
+ ar913x_usb_setup();
+ else if (soc_is_ar933x())
+ ar933x_usb_setup();
++ else if (soc_is_ar934x())
++ ar934x_usb_setup();
+ else
+ BUG();
+ }
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -63,6 +63,8 @@
+
+ #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
+ #define AR934X_WMAC_SIZE 0x20000
++#define AR934X_EHCI_BASE 0x1b000000
++#define AR934X_EHCI_SIZE 0x1000
+
+ /*
+ * DDR_CTRL block
+@@ -288,6 +290,39 @@
+ #define AR933X_RESET_USB_PHY BIT(4)
+ #define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
+
++#define AR934X_RESET_HOST BIT(31)
++#define AR934X_RESET_SLIC BIT(30)
++#define AR934X_RESET_HDMA BIT(29)
++#define AR934X_RESET_EXTERNAL BIT(28)
++#define AR934X_RESET_RTC BIT(27)
++#define AR934X_RESET_PCIE_EP_INT BIT(26)
++#define AR934X_RESET_CHKSUM_ACC BIT(25)
++#define AR934X_RESET_FULL_CHIP BIT(24)
++#define AR934X_RESET_GE1_MDIO BIT(23)
++#define AR934X_RESET_GE0_MDIO BIT(22)
++#define AR934X_RESET_CPU_NMI BIT(21)
++#define AR934X_RESET_CPU_COLD BIT(20)
++#define AR934X_RESET_HOST_RESET_INT BIT(19)
++#define AR934X_RESET_PCIE_EP BIT(18)
++#define AR934X_RESET_UART1 BIT(17)
++#define AR934X_RESET_DDR BIT(16)
++#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
++#define AR934X_RESET_NANDF BIT(14)
++#define AR934X_RESET_GE1_MAC BIT(13)
++#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12)
++#define AR934X_RESET_USB_PHY_ANALOG BIT(11)
++#define AR934X_RESET_HOST_DMA_INT BIT(10)
++#define AR934X_RESET_GE0_MAC BIT(9)
++#define AR934X_RESET_ETH_SIWTCH BIT(8)
++#define AR934X_RESET_PCIE_PHY BIT(7)
++#define AR934X_RESET_PCIE BIT(6)
++#define AR934X_RESET_USB_HOST BIT(5)
++#define AR934X_RESET_USB_PHY BIT(4)
++#define AR934X_RESET_USBSUS_OVERRIDE BIT(3)
++#define AR934X_RESET_LUT BIT(2)
++#define AR934X_RESET_MBOX BIT(1)
++#define AR934X_RESET_I2S BIT(0)
++
+ #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
+
+ #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
--- /dev/null
+From f299f36542f81f05cff7cdebb50abde202faf6df Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sat, 17 Dec 2011 10:04:18 +0100
+Subject: [PATCH 32/35] MIPS: ath79: add PCI_AR724X Kconfig symbol
+
+The AR724X specific PCI code can be used for the
+AR934X SoCs, however it can be selected only if
+SOC_AR724X is set.
+
+Introduce a new Kconfig symbol in order to be able
+to use the code for AR934X as well.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+ arch/mips/ath79/Kconfig | 4 ++++
+ arch/mips/include/asm/mach-ath79/pci.h | 2 +-
+ arch/mips/pci/Makefile | 2 +-
+ 3 files changed, 6 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -59,6 +59,7 @@ config SOC_AR724X
+ select USB_ARCH_HAS_EHCI
+ select USB_ARCH_HAS_OHCI
+ select HW_HAS_PCI
++ select PCI_AR724X if PCI
+ def_bool n
+
+ config SOC_AR913X
+@@ -73,6 +74,9 @@ config SOC_AR934X
+ select USB_ARCH_HAS_EHCI
+ def_bool n
+
++config PCI_AR724X
++ def_bool n
++
+ config ATH79_DEV_GPIO_BUTTONS
+ def_bool n
+
+--- a/arch/mips/include/asm/mach-ath79/pci.h
++++ b/arch/mips/include/asm/mach-ath79/pci.h
+@@ -19,7 +19,7 @@ int ar71xx_pcibios_init(void);
+ static inline int ar71xx_pcibios_init(void) { return 0 };
+ #endif
+
+-#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X)
++#if defined(CONFIG_PCI_AR724X)
+ int ar724x_pcibios_init(int irq);
+ #else
+ static inline int ar724x_pcibios_init(int irq) { return 0 };
+--- a/arch/mips/pci/Makefile
++++ b/arch/mips/pci/Makefile
+@@ -20,7 +20,7 @@ obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o
+ ops-bcm63xx.o
+ obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
+ obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o
+-obj-$(CONFIG_SOC_AR724X) += pci-ar724x.o
++obj-$(CONFIG_PCI_AR724X) += pci-ar724x.o
+
+ #
+ # These are still pretty much in the old state, watch, go blind.
--- /dev/null
+From e30d942814a606c5258c7adafc6bbb49836573e9 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sat, 17 Dec 2011 10:13:08 +0100
+Subject: [PATCH 33/35] MIPS: ath79: add PCI registration code for AR934X
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+ arch/mips/ath79/Kconfig | 2 ++
+ arch/mips/ath79/pci.c | 13 ++++++++++++-
+ 2 files changed, 14 insertions(+), 1 deletions(-)
+
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -72,6 +72,8 @@ config SOC_AR933X
+
+ config SOC_AR934X
+ select USB_ARCH_HAS_EHCI
++ select HW_HAS_PCI
++ select PCI_AR724X if PCI
+ def_bool n
+
+ config PCI_AR724X
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -14,6 +14,7 @@
+
+ #include <linux/init.h>
+ #include <linux/pci.h>
++#include <asm/mach-ath79/ar71xx_regs.h>
+ #include <asm/mach-ath79/ath79.h>
+ #include <asm/mach-ath79/irq.h>
+ #include <asm/mach-ath79/pci.h>
+@@ -57,7 +58,9 @@ int __init pcibios_map_irq(const struct
+ if (soc_is_ar71xx()) {
+ ath79_pci_irq_map = ar71xx_pci_irq_map;
+ ath79_pci_nr_irqs = ARRAY_SIZE(ar71xx_pci_irq_map);
+- } else if (soc_is_ar724x()) {
++ } else if (soc_is_ar724x() ||
++ soc_is_ar9342() ||
++ soc_is_ar9344()) {
+ ath79_pci_irq_map = ar724x_pci_irq_map;
+ ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
+ } else {
+@@ -115,5 +118,13 @@ int __init ath79_register_pci(void)
+ if (soc_is_ar724x())
+ return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2);
+
++ if (soc_is_ar9342() || soc_is_ar9344()) {
++ u32 bootstrap;
++
++ bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
++ if (bootstrap & AR934X_BOOTSTRAP_PCIE_RC)
++ return ar724x_pcibios_init(ATH79_IP2_IRQ(0));
++ }
++
+ return -ENODEV;
+ }
--- /dev/null
+From a01e8727327cf0fb6382ca8700a3a3f73d93202a Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Fri, 9 Dec 2011 22:23:02 +0100
+Subject: [PATCH 34/35] MIPS: ath79: add initial support for the Atheros DB120 board
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+---
+ arch/mips/ath79/Kconfig | 12 +++
+ arch/mips/ath79/Makefile | 1 +
+ arch/mips/ath79/mach-db120.c | 155 ++++++++++++++++++++++++++++++++++++++++++
+ arch/mips/ath79/machtypes.h | 1 +
+ 4 files changed, 169 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/ath79/mach-db120.c
+
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -26,6 +26,18 @@ config ATH79_MACH_AP81
+ Say 'Y' here if you want your kernel to support the
+ Atheros AP81 reference board.
+
++config ATH79_MACH_DB120
++ bool "Atheros DB120 reference board"
++ select SOC_AR934X
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_SPI
++ select ATH79_DEV_USB
++ select ATH79_DEV_WMAC
++ help
++ Say 'Y' here if you want your kernel to support the
++ Atheros DB120 reference board.
++
+ config ATH79_MACH_PB44
+ bool "Atheros PB44 reference board"
+ select SOC_AR71XX
+--- a/arch/mips/ath79/Makefile
++++ b/arch/mips/ath79/Makefile
+@@ -28,5 +28,6 @@ obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wma
+ #
+ obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o
+ obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o
++obj-$(CONFIG_ATH79_MACH_DB120) += mach-db120.o
+ obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o
+ obj-$(CONFIG_ATH79_MACH_UBNT_XM) += mach-ubnt-xm.o
+--- /dev/null
++++ b/arch/mips/ath79/mach-db120.c
+@@ -0,0 +1,155 @@
++/*
++ * Atheros DB120 reference board support
++ *
++ * Copyright (c) 2011 Qualcomm Atheros
++ * Copyright (c) 2011 Gabor Juhos <juhosg@openwrt.org>
++ *
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted (subject to the limitations in the
++ * disclaimer below) provided that the following conditions are met:
++ *
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ *
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the
++ * distribution.
++ *
++ * * Neither the name of Qualcomm Atheros nor the names of its
++ * contributors may be used to endorse or promote products derived
++ * from this software without specific prior written permission.
++ *
++ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
++ * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
++ * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
++ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
++ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
++ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
++ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
++ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <linux/pci.h>
++#include <linux/ath9k_platform.h>
++
++#include "machtypes.h"
++#include "dev-gpio-buttons.h"
++#include "dev-leds-gpio.h"
++#include "dev-spi.h"
++#include "dev-usb.h"
++#include "dev-wmac.h"
++#include "pci.h"
++
++#define DB120_GPIO_LED_WLAN_5G 12
++#define DB120_GPIO_LED_WLAN_2G 13
++#define DB120_GPIO_LED_STATUS 14
++#define DB120_GPIO_LED_WPS 15
++
++#define DB120_GPIO_BTN_WPS 16
++
++#define DB120_KEYS_POLL_INTERVAL 20 /* msecs */
++#define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL)
++
++#define DB120_WMAC_CALDATA_OFFSET 0x1000
++#define DB120_PCIE_CALDATA_OFFSET 0x5000
++
++static struct gpio_led db120_leds_gpio[] __initdata = {
++ {
++ .name = "db120:green:status",
++ .gpio = DB120_GPIO_LED_STATUS,
++ .active_low = 1,
++ },
++ {
++ .name = "db120:green:wps",
++ .gpio = DB120_GPIO_LED_WPS,
++ .active_low = 1,
++ },
++ {
++ .name = "db120:green:wlan-5g",
++ .gpio = DB120_GPIO_LED_WLAN_5G,
++ .active_low = 1,
++ },
++ {
++ .name = "db120:green:wlan-2g",
++ .gpio = DB120_GPIO_LED_WLAN_2G,
++ .active_low = 1,
++ },
++};
++
++static struct gpio_keys_button db120_gpio_keys[] __initdata = {
++ {
++ .desc = "WPS button",
++ .type = EV_KEY,
++ .code = KEY_WPS_BUTTON,
++ .debounce_interval = DB120_KEYS_DEBOUNCE_INTERVAL,
++ .gpio = DB120_GPIO_BTN_WPS,
++ .active_low = 1,
++ },
++};
++
++static struct spi_board_info db120_spi_info[] = {
++ {
++ .bus_num = 0,
++ .chip_select = 0,
++ .max_speed_hz = 25000000,
++ .modalias = "s25sl064a",
++ }
++};
++
++static struct ath79_spi_platform_data db120_spi_data = {
++ .bus_num = 0,
++ .num_chipselect = 1,
++};
++
++#ifdef CONFIG_PCI
++static struct ath9k_platform_data db120_ath9k_data;
++
++static int db120_pci_plat_dev_init(struct pci_dev *dev)
++{
++ switch (PCI_SLOT(dev->devfn)) {
++ case 0:
++ dev->dev.platform_data = &db120_ath9k_data;
++ break;
++ }
++
++ return 0;
++}
++
++static void __init db120_pci_init(u8 *eeprom)
++{
++ memcpy(db120_ath9k_data.eeprom_data, eeprom,
++ sizeof(db120_ath9k_data.eeprom_data));
++
++ ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init);
++ ath79_register_pci();
++}
++#else
++static inline void db120_pci_init(void) {}
++#endif /* CONFIG_PCI */
++
++static void __init db120_setup(void)
++{
++ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
++
++ ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio),
++ db120_leds_gpio);
++ ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL,
++ ARRAY_SIZE(db120_gpio_keys),
++ db120_gpio_keys);
++ ath79_register_spi(&db120_spi_data, db120_spi_info,
++ ARRAY_SIZE(db120_spi_info));
++ ath79_register_usb();
++ ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET);
++ db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
++}
++
++MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board",
++ db120_setup);
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -18,6 +18,7 @@ enum ath79_mach_type {
+ ATH79_MACH_GENERIC = 0,
+ ATH79_MACH_AP121, /* Atheros AP121 reference board */
+ ATH79_MACH_AP81, /* Atheros AP81 reference board */
++ ATH79_MACH_DB120, /* Atheros DB120 reference board */
+ ATH79_MACH_PB44, /* Atheros PB44 reference board */
+ ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */
+ };
--- /dev/null
+From cbf8930fe259777fb746f0387bf821729061c122 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Sun, 11 Dec 2011 22:09:20 +0100
+Subject: [PATCH 35/35] USB: ehci-ath79: add device_id entry for the AR934X SoCs
+
+Also make the USB_EHCI_ATH79 selectable for the AR934X SoCs.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
+Cc: Alan Stern <stern@rowland.harvard.edu>
+Cc: Greg Kroah-Hartman <gregkh@suse.de>
+Cc: linux-usb@vger.kernel.org
+---
+ drivers/usb/host/Kconfig | 2 +-
+ drivers/usb/host/ehci-ath79.c | 4 ++++
+ 2 files changed, 5 insertions(+), 1 deletions(-)
+
+--- a/drivers/usb/host/Kconfig
++++ b/drivers/usb/host/Kconfig
+@@ -210,7 +210,7 @@ config USB_CNS3XXX_EHCI
+
+ config USB_EHCI_ATH79
+ bool "EHCI support for AR7XXX/AR9XXX SoCs"
+- depends on USB_EHCI_HCD && (SOC_AR71XX || SOC_AR724X || SOC_AR913X || SOC_AR933X)
++ depends on USB_EHCI_HCD && (SOC_AR71XX || SOC_AR724X || SOC_AR913X || SOC_AR933X || SOC_AR934X)
+ select USB_EHCI_ROOT_HUB_TT
+ default y
+ ---help---
+--- a/drivers/usb/host/ehci-ath79.c
++++ b/drivers/usb/host/ehci-ath79.c
+@@ -37,6 +37,10 @@ static const struct platform_device_id e
+ .driver_data = EHCI_ATH79_IP_V2,
+ },
+ {
++ .name = "ar934x-ehci",
++ .driver_data = EHCI_ATH79_IP_V2,
++ },
++ {
+ /* terminating entry */
+ },
+ };
--- /dev/null
+From 48b7e765e6e097d20d809fadd17a4355d26ad6d5 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Wed, 11 Jan 2012 20:06:35 +0100
+Subject: [PATCH 1/7] spi/ath79: add delay between SCK changes
+
+The driver uses the "as fast as it can" approach
+to drive the SCK signal. However this does not
+work with certain low speed SPI chips (e.g. the
+PCF2123 RTC chip). Add per-bit slowdowns in order
+to be able to use the driver with such chips as
+well.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ drivers/spi/spi-ath79.c | 8 ++++++++
+ 1 files changed, 8 insertions(+), 0 deletions(-)
+
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -52,6 +52,12 @@ static inline struct ath79_spi *ath79_sp
+ return spi_master_get_devdata(spi->master);
+ }
+
++static inline void ath79_spi_delay(unsigned nsecs)
++{
++ if (nsecs)
++ ndelay(nsecs);
++}
++
+ static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
+ {
+ struct ath79_spi *sp = ath79_spidev_to_sp(spi);
+@@ -184,7 +190,9 @@ static u32 ath79_spi_txrx_mode0(struct s
+
+ /* setup MSB (to slave) on trailing edge */
+ ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
++ ath79_spi_delay(nsecs);
+ ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
++ ath79_spi_delay(nsecs);
+
+ word <<= 1;
+ }
--- /dev/null
+From 0ad8cbbb978bc01de08eadd3357ea188302b83ce Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Wed, 11 Jan 2012 20:33:41 +0100
+Subject: [PATCH 2/7] spi/ath79: add missing HIGH->LOW SCK transition
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ drivers/spi/spi-ath79.c | 1 +
+ 1 files changed, 1 insertions(+), 0 deletions(-)
+
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -193,6 +193,7 @@ static u32 ath79_spi_txrx_mode0(struct s
+ ath79_spi_delay(nsecs);
+ ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
+ ath79_spi_delay(nsecs);
++ ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
+
+ word <<= 1;
+ }
--- /dev/null
+From 7385ff2cb72d6a0107890760466b9564aa5204c1 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 9 Jan 2012 15:03:28 +0100
+Subject: [PATCH 3/7] spi/ath79: remove superfluous chip select code
+
+The spi_bitbang driver calls the chipselect function
+of the driver from spi_bitbang_setup in order to
+deselect the given SPI chip, so we don't have to
+initialize the CS line here.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ drivers/spi/spi-ath79.c | 6 ------
+ 1 files changed, 0 insertions(+), 6 deletions(-)
+
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -121,12 +121,6 @@ static int ath79_spi_setup_cs(struct spi
+ gpio_free(cdata->gpio);
+ return status;
+ }
+- } else {
+- if (spi->mode & SPI_CS_HIGH)
+- sp->ioc_base |= AR71XX_SPI_IOC_CS0;
+- else
+- sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
+- ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
+ }
+
+ return 0;
--- /dev/null
+From c5bfb0c760a5d8de7ffc3a6acfb8c782be6af1a5 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 9 Jan 2012 15:04:21 +0100
+Subject: [PATCH 4/7] spi/ath79: use gpio_request_one
+
+Use gpio_request_one() instead of multiple gpiolib calls.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ drivers/spi/spi-ath79.c | 26 +++++++++++++-------------
+ 1 files changed, 13 insertions(+), 13 deletions(-)
+
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -93,6 +93,7 @@ static int ath79_spi_setup_cs(struct spi
+ {
+ struct ath79_spi *sp = ath79_spidev_to_sp(spi);
+ struct ath79_spi_controller_data *cdata;
++ int status;
+
+ cdata = spi->controller_data;
+ if (spi->chip_select && !cdata)
+@@ -108,22 +109,21 @@ static int ath79_spi_setup_cs(struct spi
+ /* TODO: setup speed? */
+ ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
+
++ status = 0;
+ if (spi->chip_select) {
+- int status = 0;
++ unsigned long flags;
+
+- status = gpio_request(cdata->gpio, dev_name(&spi->dev));
+- if (status)
+- return status;
++ flags = GPIOF_DIR_OUT;
++ if (spi->mode & SPI_CS_HIGH)
++ flags |= GPIOF_INIT_HIGH;
++ else
++ flags |= GPIOF_INIT_LOW;
+
+- status = gpio_direction_output(cdata->gpio,
+- spi->mode & SPI_CS_HIGH);
+- if (status) {
+- gpio_free(cdata->gpio);
+- return status;
+- }
++ status = gpio_request_one(cdata->gpio, flags,
++ dev_name(&spi->dev));
+ }
+
+- return 0;
++ return status;
+ }
+
+ static void ath79_spi_cleanup_cs(struct spi_device *spi)
--- /dev/null
+From 4518ae06e5fc953abfd9c2b66c6155fc2b2696ce Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Mon, 9 Jan 2012 15:00:46 +0100
+Subject: [PATCH 5/7] spi/ath79: introduce ath79_spi_{en,dis}able helpers
+
+---
+ drivers/spi/spi-ath79.c | 41 +++++++++++++++++++++++++----------------
+ 1 files changed, 25 insertions(+), 16 deletions(-)
+
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -89,16 +89,8 @@ static void ath79_spi_chipselect(struct
+
+ }
+
+-static int ath79_spi_setup_cs(struct spi_device *spi)
++static void ath79_spi_enable(struct ath79_spi *sp)
+ {
+- struct ath79_spi *sp = ath79_spidev_to_sp(spi);
+- struct ath79_spi_controller_data *cdata;
+- int status;
+-
+- cdata = spi->controller_data;
+- if (spi->chip_select && !cdata)
+- return -EINVAL;
+-
+ /* enable GPIO mode */
+ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
+
+@@ -108,6 +100,25 @@ static int ath79_spi_setup_cs(struct spi
+
+ /* TODO: setup speed? */
+ ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
++}
++
++static void ath79_spi_disable(struct ath79_spi *sp)
++{
++ /* restore CTRL register */
++ ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
++ /* disable GPIO mode */
++ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
++}
++
++static int ath79_spi_setup_cs(struct spi_device *spi)
++{
++ struct ath79_spi *sp = ath79_spidev_to_sp(spi);
++ struct ath79_spi_controller_data *cdata;
++ int status;
++
++ cdata = spi->controller_data;
++ if (spi->chip_select && !cdata)
++ return -EINVAL;
+
+ status = 0;
+ if (spi->chip_select) {
+@@ -134,11 +145,6 @@ static void ath79_spi_cleanup_cs(struct
+ struct ath79_spi_controller_data *cdata = spi->controller_data;
+ gpio_free(cdata->gpio);
+ }
+-
+- /* restore CTRL register */
+- ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
+- /* disable GPIO mode */
+- ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
+ }
+
+ static int ath79_spi_setup(struct spi_device *spi)
+@@ -242,13 +248,15 @@ static __devinit int ath79_spi_probe(str
+ goto err_put_master;
+ }
+
++ ath79_spi_enable(sp);
+ ret = spi_bitbang_start(&sp->bitbang);
+ if (ret)
+- goto err_unmap;
++ goto err_disable;
+
+ return 0;
+
+-err_unmap:
++err_disable:
++ ath79_spi_disable(sp);
+ iounmap(sp->base);
+ err_put_master:
+ platform_set_drvdata(pdev, NULL);
+@@ -262,6 +270,7 @@ static __devexit int ath79_spi_remove(st
+ struct ath79_spi *sp = platform_get_drvdata(pdev);
+
+ spi_bitbang_stop(&sp->bitbang);
++ ath79_spi_disable(sp);
+ iounmap(sp->base);
+ platform_set_drvdata(pdev, NULL);
+ spi_master_put(sp->bitbang.master);
--- /dev/null
+From 1025bfbe327b3f9f7227e781c71751d5251803cb Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Wed, 11 Jan 2012 22:19:32 +0100
+Subject: [PATCH 6/7] spi/ath79: add shutdown handler
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ drivers/spi/spi-ath79.c | 12 +++++++++++-
+ 1 files changed, 11 insertions(+), 1 deletions(-)
+
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -265,7 +265,7 @@ err_put_master:
+ return ret;
+ }
+
+-static __devexit int ath79_spi_remove(struct platform_device *pdev)
++static void __ath79_spi_remove(struct platform_device *pdev)
+ {
+ struct ath79_spi *sp = platform_get_drvdata(pdev);
+
+@@ -274,13 +274,23 @@ static __devexit int ath79_spi_remove(st
+ iounmap(sp->base);
+ platform_set_drvdata(pdev, NULL);
+ spi_master_put(sp->bitbang.master);
++}
+
++static __devexit int ath79_spi_remove(struct platform_device *pdev)
++{
++ __ath79_spi_remove(pdev);
+ return 0;
+ }
+
++static void ath79_spi_shutdown(struct platform_device *pdev)
++{
++ __ath79_spi_remove(pdev);
++}
++
+ static struct platform_driver ath79_spi_driver = {
+ .probe = ath79_spi_probe,
+ .remove = __devexit_p(ath79_spi_remove),
++ .shutdown = ath79_spi_shutdown,
+ .driver = {
+ .name = DRV_NAME,
+ .owner = THIS_MODULE,
--- /dev/null
+From b875f877d06acb852342636db4c3d1e6c9fe01ba Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
+Date: Wed, 11 Jan 2012 22:25:11 +0100
+Subject: [PATCH 7/7] spi/ath79: make chipselect logic more flexible
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+---
+ .../include/asm/mach-ath79/ath79_spi_platform.h | 8 ++-
+ drivers/spi/spi-ath79.c | 65 +++++++++++--------
+ 2 files changed, 45 insertions(+), 28 deletions(-)
+
+--- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
++++ b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
+@@ -16,8 +16,14 @@ struct ath79_spi_platform_data {
+ unsigned num_chipselect;
+ };
+
++enum ath79_spi_cs_type {
++ ATH79_SPI_CS_TYPE_INTERNAL,
++ ATH79_SPI_CS_TYPE_GPIO,
++};
++
+ struct ath79_spi_controller_data {
+- unsigned gpio;
++ enum ath79_spi_cs_type cs_type;
++ unsigned cs_line;
+ };
+
+ #endif /* _ATH79_SPI_PLATFORM_H */
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -30,6 +30,8 @@
+
+ #define DRV_NAME "ath79-spi"
+
++#define ATH79_SPI_CS_LINE_MAX 2
++
+ struct ath79_spi {
+ struct spi_bitbang bitbang;
+ u32 ioc_base;
+@@ -62,6 +64,7 @@ static void ath79_spi_chipselect(struct
+ {
+ struct ath79_spi *sp = ath79_spidev_to_sp(spi);
+ int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
++ struct ath79_spi_controller_data *cdata = spi->controller_data;
+
+ if (is_active) {
+ /* set initial clock polarity */
+@@ -73,20 +76,21 @@ static void ath79_spi_chipselect(struct
+ ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
+ }
+
+- if (spi->chip_select) {
+- struct ath79_spi_controller_data *cdata = spi->controller_data;
+-
+- /* SPI is normally active-low */
+- gpio_set_value(cdata->gpio, cs_high);
+- } else {
++ switch (cdata->cs_type) {
++ case ATH79_SPI_CS_TYPE_INTERNAL:
+ if (cs_high)
+- sp->ioc_base |= AR71XX_SPI_IOC_CS0;
++ sp->ioc_base |= AR71XX_SPI_IOC_CS(cdata->cs_line);
+ else
+- sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
++ sp->ioc_base &= ~AR71XX_SPI_IOC_CS(cdata->cs_line);
+
+ ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
+- }
++ break;
+
++ case ATH79_SPI_CS_TYPE_GPIO:
++ /* SPI is normally active-low */
++ gpio_set_value(cdata->cs_line, cs_high);
++ break;
++ }
+ }
+
+ static void ath79_spi_enable(struct ath79_spi *sp)
+@@ -114,24 +118,30 @@ static int ath79_spi_setup_cs(struct spi
+ {
+ struct ath79_spi *sp = ath79_spidev_to_sp(spi);
+ struct ath79_spi_controller_data *cdata;
++ unsigned long flags;
+ int status;
+
+ cdata = spi->controller_data;
+- if (spi->chip_select && !cdata)
++ if (!cdata)
+ return -EINVAL;
+
+ status = 0;
+- if (spi->chip_select) {
+- unsigned long flags;
++ switch (cdata->cs_type) {
++ case ATH79_SPI_CS_TYPE_INTERNAL:
++ if (cdata->cs_line > ATH79_SPI_CS_LINE_MAX)
++ status = -EINVAL;
++ break;
+
++ case ATH79_SPI_CS_TYPE_GPIO:
+ flags = GPIOF_DIR_OUT;
+ if (spi->mode & SPI_CS_HIGH)
+ flags |= GPIOF_INIT_HIGH;
+ else
+ flags |= GPIOF_INIT_LOW;
+
+- status = gpio_request_one(cdata->gpio, flags,
++ status = gpio_request_one(cdata->cs_line, flags,
+ dev_name(&spi->dev));
++ break;
+ }
+
+ return status;
+@@ -139,11 +149,15 @@ static int ath79_spi_setup_cs(struct spi
+
+ static void ath79_spi_cleanup_cs(struct spi_device *spi)
+ {
+- struct ath79_spi *sp = ath79_spidev_to_sp(spi);
++ struct ath79_spi_controller_data *cdata = spi->controller_data;
+
+- if (spi->chip_select) {
+- struct ath79_spi_controller_data *cdata = spi->controller_data;
+- gpio_free(cdata->gpio);
++ switch (cdata->cs_type) {
++ case ATH79_SPI_CS_TYPE_INTERNAL:
++ /* nothing to do */
++ break;
++ case ATH79_SPI_CS_TYPE_GPIO:
++ gpio_free(cdata->cs_line);
++ break;
+ }
+ }
+
+@@ -209,6 +223,10 @@ static __devinit int ath79_spi_probe(str
+ struct resource *r;
+ int ret;
+
++ pdata = pdev->dev.platform_data;
++ if (!pdata)
++ return -EINVAL;
++
+ master = spi_alloc_master(&pdev->dev, sizeof(*sp));
+ if (master == NULL) {
+ dev_err(&pdev->dev, "failed to allocate spi master\n");
+@@ -218,17 +236,10 @@ static __devinit int ath79_spi_probe(str
+ sp = spi_master_get_devdata(master);
+ platform_set_drvdata(pdev, sp);
+
+- pdata = pdev->dev.platform_data;
+-
+ master->setup = ath79_spi_setup;
+ master->cleanup = ath79_spi_cleanup;
+- if (pdata) {
+- master->bus_num = pdata->bus_num;
+- master->num_chipselect = pdata->num_chipselect;
+- } else {
+- master->bus_num = -1;
+- master->num_chipselect = 1;
+- }
++ master->bus_num = pdata->bus_num;
++ master->num_chipselect = pdata->num_chipselect;
+
+ sp->bitbang.master = spi_master_get(master);
+ sp->bitbang.chipselect = ath79_spi_chipselect;
--- /dev/null
+--- a/arch/mips/ath79/mach-ap121.c
++++ b/arch/mips/ath79/mach-ap121.c
+@@ -58,12 +58,18 @@ static struct gpio_keys_button ap121_gpi
+ }
+ };
+
++static struct ath79_spi_controller_data ap121_spi0_data = {
++ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
++ .cs_line = 0,
++};
++
+ static struct spi_board_info ap121_spi_info[] = {
+ {
+ .bus_num = 0,
+ .chip_select = 0,
+ .max_speed_hz = 25000000,
+ .modalias = "mx25l1606e",
++ .controller_data = &ap121_spi0_data,
+ }
+ };
+
+--- a/arch/mips/ath79/mach-ap81.c
++++ b/arch/mips/ath79/mach-ap81.c
+@@ -67,12 +67,18 @@ static struct gpio_keys_button ap81_gpio
+ }
+ };
+
++static struct ath79_spi_controller_data ap81_spi0_data = {
++ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
++ .cs_line = 0,
++};
++
+ static struct spi_board_info ap81_spi_info[] = {
+ {
+ .bus_num = 0,
+ .chip_select = 0,
+ .max_speed_hz = 25000000,
+ .modalias = "m25p64",
++ .controller_data = &ap81_spi0_data,
+ }
+ };
+
+--- a/arch/mips/ath79/mach-db120.c
++++ b/arch/mips/ath79/mach-db120.c
+@@ -95,12 +95,18 @@ static struct gpio_keys_button db120_gpi
+ },
+ };
+
++static struct ath79_spi_controller_data db120_spi0_data = {
++ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
++ .cs_line = 0,
++};
++
+ static struct spi_board_info db120_spi_info[] = {
+ {
+ .bus_num = 0,
+ .chip_select = 0,
+ .max_speed_hz = 25000000,
+ .modalias = "s25sl064a",
++ .controller_data = &db120_spi0_data,
+ }
+ };
+
+--- a/arch/mips/ath79/mach-pb44.c
++++ b/arch/mips/ath79/mach-pb44.c
+@@ -87,12 +87,18 @@ static struct gpio_keys_button pb44_gpio
+ }
+ };
+
++static struct ath79_spi_controller_data pb44_spi0_data = {
++ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
++ .cs_line = 0,
++};
++
+ static struct spi_board_info pb44_spi_info[] = {
+ {
+ .bus_num = 0,
+ .chip_select = 0,
+ .max_speed_hz = 25000000,
+ .modalias = "m25p64",
++ .controller_data = &pb44_spi0_data,
+ },
+ };
+
+--- a/arch/mips/ath79/mach-ubnt-xm.c
++++ b/arch/mips/ath79/mach-ubnt-xm.c
+@@ -65,12 +65,18 @@ static struct gpio_keys_button ubnt_xm_g
+ }
+ };
+
++static struct ath79_spi_controller_data ubnt_xm_spi0_data = {
++ .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
++ .cs_line = 0,
++};
++
+ static struct spi_board_info ubnt_xm_spi_info[] = {
+ {
+ .bus_num = 0,
+ .chip_select = 0,
+ .max_speed_hz = 25000000,
+ .modalias = "mx25l6405d",
++ .controller_data = &ubnt_xm_spi0_data,
+ }
+ };
+
--- /dev/null
+--- a/arch/mips/ath79/gpio.c
++++ b/arch/mips/ath79/gpio.c
+@@ -188,8 +188,10 @@ void __init ath79_gpio_init(void)
+
+ if (soc_is_ar71xx())
+ ath79_gpio_count = AR71XX_GPIO_COUNT;
+- else if (soc_is_ar724x())
+- ath79_gpio_count = AR724X_GPIO_COUNT;
++ else if (soc_is_ar7240())
++ ath79_gpio_count = AR7240_GPIO_COUNT;
++ else if (soc_is_ar7241() || soc_is_ar7242())
++ ath79_gpio_count = AR7241_GPIO_COUNT;
+ else if (soc_is_ar913x())
+ ath79_gpio_count = AR913X_GPIO_COUNT;
+ else if (soc_is_ar933x())
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -428,7 +428,8 @@
+ #define AR71XX_GPIO_REG_FUNC 0x28
+
+ #define AR71XX_GPIO_COUNT 16
+-#define AR724X_GPIO_COUNT 18
++#define AR7240_GPIO_COUNT 18
++#define AR7241_GPIO_COUNT 20
+ #define AR913X_GPIO_COUNT 22
+ #define AR933X_GPIO_COUNT 30
+ #define AR934X_GPIO_COUNT 23
--- /dev/null
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -62,8 +62,8 @@ static void __init ar913x_wmac_setup(voi
+
+ static int ar933x_wmac_reset(void)
+ {
+- ath79_device_reset_clear(AR933X_RESET_WMAC);
+ ath79_device_reset_set(AR933X_RESET_WMAC);
++ ath79_device_reset_clear(AR933X_RESET_WMAC);
+
+ return 0;
+ }
--- /dev/null
+--- a/drivers/leds/leds-rb750.c
++++ b/drivers/leds/leds-rb750.c
+@@ -9,12 +9,13 @@
+ *
+ */
+ #include <linux/kernel.h>
++#include <linux/module.h>
+ #include <linux/init.h>
+ #include <linux/platform_device.h>
+ #include <linux/leds.h>
+ #include <linux/slab.h>
+
+-#include <asm/mach-ar71xx/mach-rb750.h>
++#include <asm/mach-ath79/mach-rb750.h>
+
+ #define DRV_NAME "leds-rb750"
+
--- /dev/null
+--- a/drivers/leds/leds-wndr3700-usb.c
++++ b/drivers/leds/leds-wndr3700-usb.c
+@@ -12,7 +12,8 @@
+ #include <linux/module.h>
+ #include <linux/platform_device.h>
+
+-#include <asm/mach-ar71xx/ar71xx.h>
++#include <asm/mach-ath79/ar71xx_regs.h>
++#include <asm/mach-ath79/ath79.h>
+
+ #define DRIVER_NAME "wndr3700-led-usb"
+
+@@ -20,14 +21,14 @@ static void wndr3700_usb_led_set(struct
+ enum led_brightness brightness)
+ {
+ if (brightness)
+- ar71xx_device_start(RESET_MODULE_GE1_PHY);
++ ath79_device_reset_clear(AR71XX_RESET_GE1_PHY);
+ else
+- ar71xx_device_stop(RESET_MODULE_GE1_PHY);
++ ath79_device_reset_set(AR71XX_RESET_GE1_PHY);
+ }
+
+ static enum led_brightness wndr3700_usb_led_get(struct led_classdev *cdev)
+ {
+- return ar71xx_device_stopped(RESET_MODULE_GE1_PHY) ? LED_OFF : LED_FULL;
++ return ath79_device_reset_get(AR71XX_RESET_GE1_PHY) ? LED_OFF : LED_FULL;
+ }
+
+ static struct led_classdev wndr3700_usb_led = {
--- /dev/null
+--- a/drivers/mtd/nand/rb4xx_nand.c
++++ b/drivers/mtd/nand/rb4xx_nand.c
+@@ -12,6 +12,8 @@
+ * by the Free Software Foundation.
+ */
+
++#include <linux/kernel.h>
++#include <linux/module.h>
+ #include <linux/init.h>
+ #include <linux/mtd/nand.h>
+ #include <linux/mtd/mtd.h>
+@@ -22,8 +24,8 @@
+ #include <linux/gpio.h>
+ #include <linux/slab.h>
+
+-#include <asm/mach-ar71xx/ar71xx.h>
+-#include <asm/mach-ar71xx/rb4xx_cpld.h>
++#include <asm/mach-ath79/ath79.h>
++#include <asm/mach-ath79/rb4xx_cpld.h>
+
+ #define DRV_NAME "rb4xx-nand"
+ #define DRV_VERSION "0.2.0"
+@@ -238,12 +240,8 @@ static int __devinit rb4xx_nand_probe(st
+ goto err_set_drvdata;
+ }
+
+-#ifdef CONFIG_MTD_PARTITIONS
+- ret = add_mtd_partitions(&info->mtd, rb4xx_nand_partitions,
++ mtd_device_register(&info->mtd, rb4xx_nand_partitions,
+ ARRAY_SIZE(rb4xx_nand_partitions));
+-#else
+- ret = add_mtd_device(&info->mtd);
+-#endif
+ if (ret)
+ goto err_release_nand;
+
--- /dev/null
+--- a/drivers/mtd/nand/rb750_nand.c
++++ b/drivers/mtd/nand/rb750_nand.c
+@@ -1,14 +1,15 @@
+ /*
+ * NAND flash driver for the MikroTik RouterBOARD 750
+ *
+- * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+-#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
+ #include <linux/mtd/nand.h>
+ #include <linux/mtd/mtd.h>
+ #include <linux/mtd/partitions.h>
+@@ -16,8 +17,9 @@
+ #include <linux/io.h>
+ #include <linux/slab.h>
+
+-#include <asm/mach-ar71xx/ar71xx.h>
+-#include <asm/mach-ar71xx/mach-rb750.h>
++#include <asm/mach-ath79/ar71xx_regs.h>
++#include <asm/mach-ath79/ath79.h>
++#include <asm/mach-ath79/mach-rb750.h>
+
+ #define DRV_NAME "rb750-nand"
+ #define DRV_VERSION "0.1.0"
+@@ -73,7 +75,7 @@ static struct mtd_partition rb750_nand_p
+
+ static void rb750_nand_write(const u8 *buf, unsigned len)
+ {
+- void __iomem *base = ar71xx_gpio_base;
++ void __iomem *base = ath79_gpio_base;
+ u32 out;
+ u32 t;
+ unsigned i;
+@@ -107,7 +109,7 @@ static void rb750_nand_write(const u8 *b
+ static int rb750_nand_read_verify(u8 *read_buf, unsigned len,
+ const u8 *verify_buf)
+ {
+- void __iomem *base = ar71xx_gpio_base;
++ void __iomem *base = ath79_gpio_base;
+ unsigned i;
+
+ for (i = 0; i < len; i++) {
+@@ -136,7 +138,7 @@ static int rb750_nand_read_verify(u8 *re
+
+ static void rb750_nand_select_chip(struct mtd_info *mtd, int chip)
+ {
+- void __iomem *base = ar71xx_gpio_base;
++ void __iomem *base = ath79_gpio_base;
+ u32 func;
+ u32 t;
+
+@@ -145,9 +147,7 @@ static void rb750_nand_select_chip(struc
+ /* disable latch */
+ rb750_latch_change(RB750_LVC573_LE, 0);
+
+- /* disable alternate functions */
+- ar71xx_gpio_function_setup(AR724X_GPIO_FUNC_JTAG_DISABLE,
+- AR724X_GPIO_FUNC_SPI_EN);
++ rb750_nand_pins_enable();
+
+ /* set input mode for data lines */
+ t = __raw_readl(base + AR71XX_GPIO_REG_OE);
+@@ -172,9 +172,7 @@ static void rb750_nand_select_chip(struc
+ __raw_writel(t | RB750_NAND_IO0 | RB750_NAND_RDY,
+ base + AR71XX_GPIO_REG_OE);
+
+- /* restore alternate functions */
+- ar71xx_gpio_function_setup(AR724X_GPIO_FUNC_SPI_EN,
+- AR724X_GPIO_FUNC_JTAG_DISABLE);
++ rb750_nand_pins_disable();
+
+ /* enable latch */
+ rb750_latch_change(0, RB750_LVC573_LE);
+@@ -183,7 +181,7 @@ static void rb750_nand_select_chip(struc
+
+ static int rb750_nand_dev_ready(struct mtd_info *mtd)
+ {
+- void __iomem *base = ar71xx_gpio_base;
++ void __iomem *base = ath79_gpio_base;
+
+ return !!(__raw_readl(base + AR71XX_GPIO_REG_IN) & RB750_NAND_RDY);
+ }
+@@ -192,7 +190,7 @@ static void rb750_nand_cmd_ctrl(struct m
+ unsigned int ctrl)
+ {
+ if (ctrl & NAND_CTRL_CHANGE) {
+- void __iomem *base = ar71xx_gpio_base;
++ void __iomem *base = ath79_gpio_base;
+ u32 t;
+
+ t = __raw_readl(base + AR71XX_GPIO_REG_OUT);
+@@ -236,7 +234,7 @@ static int rb750_nand_verify_buf(struct
+
+ static void __init rb750_nand_gpio_init(void)
+ {
+- void __iomem *base = ar71xx_gpio_base;
++ void __iomem *base = ath79_gpio_base;
+ u32 out;
+ u32 t;
+
+@@ -306,12 +304,8 @@ static int __devinit rb750_nand_probe(st
+ goto err_set_drvdata;
+ }
+
+-#ifdef CONFIG_MTD_PARTITIONS
+- ret = add_mtd_partitions(&info->mtd, rb750_nand_partitions,
++ ret = mtd_device_register(&info->mtd, rb750_nand_partitions,
+ ARRAY_SIZE(rb750_nand_partitions));
+-#else
+- ret = add_mtd_device(&info->mtd);
+-#endif
+ if (ret)
+ goto err_release_nand;
+
--- /dev/null
+--- a/drivers/spi/spi-ap83.c
++++ b/drivers/spi/spi-ap83.c
+@@ -10,6 +10,7 @@
+ */
+
+ #include <linux/kernel.h>
++#include <linux/module.h>
+ #include <linux/init.h>
+ #include <linux/delay.h>
+ #include <linux/spinlock.h>
+@@ -21,8 +22,7 @@
+ #include <linux/bitops.h>
+ #include <linux/gpio.h>
+
+-#include <asm/mach-ar71xx/ar71xx.h>
+-#include <asm/mach-ar71xx/platform.h>
++#include <asm/mach-ath79/ath79.h>
+
+ #define DRV_DESC "Atheros AP83 board SPI Controller driver"
+ #define DRV_VERSION "0.1.0"
+@@ -106,7 +106,7 @@ static void ap83_spi_chipselect(struct s
+ dev_dbg(&spi->dev, "set CS to %d\n", (on) ? 0 : 1);
+
+ if (on) {
+- ar71xx_flash_acquire();
++ ath79_flash_acquire();
+
+ sp->addr = 0;
+ ap83_spi_rr(sp, sp->addr);
+@@ -114,7 +114,7 @@ static void ap83_spi_chipselect(struct s
+ gpio_set_value(AP83_SPI_GPIO_CS, 0);
+ } else {
+ gpio_set_value(AP83_SPI_GPIO_CS, 1);
+- ar71xx_flash_release();
++ ath79_flash_release();
+ }
+ }
+
+@@ -127,7 +127,7 @@ static void ap83_spi_chipselect(struct s
+
+ #define EXPAND_BITBANG_TXRX
+ #include <linux/spi/spi_bitbang.h>
+-#include "spi_bitbang_txrx.h"
++#include "spi-bitbang-txrx.h"
+
+ static u32 ap83_spi_txrx_mode0(struct spi_device *spi,
+ unsigned nsecs, u32 word, u8 bits)
--- /dev/null
+--- a/drivers/spi/spi-rb4xx-cpld.c
++++ b/drivers/spi/spi-rb4xx-cpld.c
+@@ -13,6 +13,7 @@
+
+ #include <linux/types.h>
+ #include <linux/kernel.h>
++#include <linux/module.h>
+ #include <linux/init.h>
+ #include <linux/module.h>
+ #include <linux/device.h>
+@@ -21,7 +22,7 @@
+ #include <linux/gpio.h>
+ #include <linux/slab.h>
+
+-#include <asm/mach-ar71xx/rb4xx_cpld.h>
++#include <asm/mach-ath79/rb4xx_cpld.h>
+
+ #define DRV_NAME "spi-rb4xx-cpld"
+ #define DRV_DESC "RB4xx CPLD driver"
--- /dev/null
+--- a/drivers/spi/spi-rb4xx.c
++++ b/drivers/spi/spi-rb4xx.c
+@@ -12,7 +12,10 @@
+ *
+ */
+
++#include <linux/clk.h>
++#include <linux/err.h>
+ #include <linux/kernel.h>
++#include <linux/module.h>
+ #include <linux/init.h>
+ #include <linux/delay.h>
+ #include <linux/spinlock.h>
+@@ -20,7 +23,8 @@
+ #include <linux/platform_device.h>
+ #include <linux/spi/spi.h>
+
+-#include <asm/mach-ar71xx/ar71xx.h>
++#include <asm/mach-ath79/ar71xx_regs.h>
++#include <asm/mach-ath79/ath79.h>
+
+ #define DRV_NAME "rb4xx-spi"
+ #define DRV_DESC "Mikrotik RB4xx SPI controller driver"
+@@ -41,13 +45,16 @@ struct rb4xx_spi {
+ unsigned spi_ctrl_flash;
+ unsigned spi_ctrl_fread;
+
++ struct clk *ahb_clk;
++ unsigned long ahb_freq;
++
+ spinlock_t lock;
+ struct list_head queue;
+ int busy:1;
+ int cs_wait;
+ };
+
+-static unsigned spi_clk_low = SPI_IOC_CS1;
++static unsigned spi_clk_low = AR71XX_SPI_IOC_CS1;
+
+ #ifdef RB4XX_SPI_DEBUG
+ static inline void do_spi_delay(void)
+@@ -60,10 +67,11 @@ static inline void do_spi_delay(void) {
+
+ static inline void do_spi_init(struct spi_device *spi)
+ {
+- unsigned cs = SPI_IOC_CS0 | SPI_IOC_CS1;
++ unsigned cs = AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1;
+
+ if (!(spi->mode & SPI_CS_HIGH))
+- cs ^= (spi->chip_select == 2) ? SPI_IOC_CS1 : SPI_IOC_CS0;
++ cs ^= (spi->chip_select == 2) ? AR71XX_SPI_IOC_CS1 :
++ AR71XX_SPI_IOC_CS0;
+
+ spi_clk_low = cs;
+ }
+@@ -71,17 +79,18 @@ static inline void do_spi_init(struct sp
+ static inline void do_spi_finish(void __iomem *base)
+ {
+ do_spi_delay();
+- __raw_writel(SPI_IOC_CS0 | SPI_IOC_CS1, base + SPI_REG_IOC);
++ __raw_writel(AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1,
++ base + AR71XX_SPI_REG_IOC);
+ }
+
+ static inline void do_spi_clk(void __iomem *base, int bit)
+ {
+- unsigned bval = spi_clk_low | ((bit & 1) ? SPI_IOC_DO : 0);
++ unsigned bval = spi_clk_low | ((bit & 1) ? AR71XX_SPI_IOC_DO : 0);
+
+ do_spi_delay();
+- __raw_writel(bval, base + SPI_REG_IOC);
++ __raw_writel(bval, base + AR71XX_SPI_REG_IOC);
+ do_spi_delay();
+- __raw_writel(bval | SPI_IOC_CLK, base + SPI_REG_IOC);
++ __raw_writel(bval | AR71XX_SPI_IOC_CLK, base + AR71XX_SPI_REG_IOC);
+ }
+
+ static void do_spi_byte(void __iomem *base, unsigned char byte)
+@@ -97,19 +106,19 @@ static void do_spi_byte(void __iomem *ba
+
+ pr_debug("spi_byte sent 0x%02x got 0x%02x\n",
+ (unsigned)byte,
+- (unsigned char)__raw_readl(base + SPI_REG_RDS));
++ (unsigned char)__raw_readl(base + AR71XX_SPI_REG_RDS));
+ }
+
+ static inline void do_spi_clk_fast(void __iomem *base, unsigned bit1,
+ unsigned bit2)
+ {
+ unsigned bval = (spi_clk_low |
+- ((bit1 & 1) ? SPI_IOC_DO : 0) |
+- ((bit2 & 1) ? SPI_IOC_CS2 : 0));
++ ((bit1 & 1) ? AR71XX_SPI_IOC_DO : 0) |
++ ((bit2 & 1) ? AR71XX_SPI_IOC_CS2 : 0));
+ do_spi_delay();
+- __raw_writel(bval, base + SPI_REG_IOC);
++ __raw_writel(bval, base + AR71XX_SPI_REG_IOC);
+ do_spi_delay();
+- __raw_writel(bval | SPI_IOC_CLK, base + SPI_REG_IOC);
++ __raw_writel(bval | AR71XX_SPI_IOC_CLK, base + AR71XX_SPI_REG_IOC);
+ }
+
+ static void do_spi_byte_fast(void __iomem *base, unsigned char byte)
+@@ -121,7 +130,7 @@ static void do_spi_byte_fast(void __iome
+
+ pr_debug("spi_byte_fast sent 0x%02x got 0x%02x\n",
+ (unsigned)byte,
+- (unsigned char) __raw_readl(base + SPI_REG_RDS));
++ (unsigned char) __raw_readl(base + AR71XX_SPI_REG_RDS));
+ }
+
+ static int rb4xx_spi_txrx(void __iomem *base, struct spi_transfer *t)
+@@ -150,9 +159,9 @@ static int rb4xx_spi_txrx(void __iomem *
+ do_spi_byte(base, sdata);
+
+ if (rx_ptr) {
+- rx_ptr[i] = __raw_readl(base + SPI_REG_RDS) & 0xff;
++ rx_ptr[i] = __raw_readl(base + AR71XX_SPI_REG_RDS) & 0xff;
+ } else if (rxv_ptr) {
+- unsigned char c = __raw_readl(base + SPI_REG_RDS);
++ unsigned char c = __raw_readl(base + AR71XX_SPI_REG_RDS);
+ if (rxv_ptr[i] != c)
+ return i;
+ }
+@@ -201,9 +210,9 @@ static int rb4xx_spi_read_fast(struct rb
+ if (t->tx_buf && !t->verify)
+ return -1;
+
+- __raw_writel(SPI_FS_GPIO, base + SPI_REG_FS);
+- __raw_writel(rbspi->spi_ctrl_fread, base + SPI_REG_CTRL);
+- __raw_writel(0, base + SPI_REG_FS);
++ __raw_writel(AR71XX_SPI_FS_GPIO, base + AR71XX_SPI_REG_FS);
++ __raw_writel(rbspi->spi_ctrl_fread, base + AR71XX_SPI_REG_CTRL);
++ __raw_writel(0, base + AR71XX_SPI_REG_FS);
+
+ if (t->rx_buf) {
+ memcpy(t->rx_buf, (const void *)addr, t->len);
+@@ -216,9 +225,9 @@ static int rb4xx_spi_read_fast(struct rb
+ m->actual_length += t->len;
+
+ if (rbspi->spi_ctrl_flash != rbspi->spi_ctrl_fread) {
+- __raw_writel(SPI_FS_GPIO, base + SPI_REG_FS);
+- __raw_writel(rbspi->spi_ctrl_flash, base + SPI_REG_CTRL);
+- __raw_writel(0, base + SPI_REG_FS);
++ __raw_writel(AR71XX_SPI_FS_GPIO, base + AR71XX_SPI_REG_FS);
++ __raw_writel(rbspi->spi_ctrl_flash, base + AR71XX_SPI_REG_CTRL);
++ __raw_writel(0, base + AR71XX_SPI_REG_FS);
+ }
+
+ return 0;
+@@ -237,8 +246,8 @@ static int rb4xx_spi_msg(struct rb4xx_sp
+ if (rb4xx_spi_read_fast(rbspi, m) == 0)
+ return -1;
+
+- __raw_writel(SPI_FS_GPIO, base + SPI_REG_FS);
+- __raw_writel(SPI_CTRL_FASTEST, base + SPI_REG_CTRL);
++ __raw_writel(AR71XX_SPI_FS_GPIO, base + AR71XX_SPI_REG_FS);
++ __raw_writel(SPI_CTRL_FASTEST, base + AR71XX_SPI_REG_CTRL);
+ do_spi_init(m->spi);
+
+ list_for_each_entry(t, &m->transfers, transfer_list) {
+@@ -262,8 +271,8 @@ static int rb4xx_spi_msg(struct rb4xx_sp
+ }
+
+ do_spi_finish(base);
+- __raw_writel(rbspi->spi_ctrl_flash, base + SPI_REG_CTRL);
+- __raw_writel(0, base + SPI_REG_FS);
++ __raw_writel(rbspi->spi_ctrl_flash, base + AR71XX_SPI_REG_CTRL);
++ __raw_writel(0, base + AR71XX_SPI_REG_FS);
+ return -1;
+ }
+
+@@ -352,11 +361,12 @@ static int rb4xx_spi_setup(struct spi_de
+ return 0;
+ }
+
+-static unsigned get_spi_ctrl(unsigned hz_max, const char *name)
++static unsigned get_spi_ctrl(struct rb4xx_spi *rbspi, unsigned hz_max,
++ const char *name)
+ {
+ unsigned div;
+
+- div = (ar71xx_ahb_freq - 1) / (2 * hz_max);
++ div = (rbspi->ahb_freq - 1) / (2 * hz_max);
+
+ /*
+ * CPU has a bug at (div == 0) - first bit read is random
+@@ -365,7 +375,7 @@ static unsigned get_spi_ctrl(unsigned hz
+ ++div;
+
+ if (name) {
+- unsigned ahb_khz = (ar71xx_ahb_freq + 500) / 1000;
++ unsigned ahb_khz = (rbspi->ahb_freq + 500) / 1000;
+ unsigned div_real = 2 * (div + 1);
+ pr_debug("rb4xx: %s SPI clock %u kHz (AHB %u kHz / %u)\n",
+ name,
+@@ -396,23 +406,40 @@ static int rb4xx_spi_probe(struct platfo
+ master->transfer = rb4xx_spi_transfer;
+
+ rbspi = spi_master_get_devdata(master);
++
++ rbspi->ahb_clk = clk_get(&pdev->dev, "AHB");
++ if (IS_ERR(rbspi->ahb_clk)) {
++ err = PTR_ERR(rbspi->ahb_clk);
++ goto err_put_master;
++ }
++
++ err = clk_enable(rbspi->ahb_clk);
++ if (err)
++ goto err_clk_put;
++
++ rbspi->ahb_freq = clk_get_rate(rbspi->ahb_clk);
++ if (!rbspi->ahb_freq) {
++ err = -EINVAL;
++ goto err_clk_disable;
++ }
++
+ platform_set_drvdata(pdev, rbspi);
+
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (r == NULL) {
+ err = -ENOENT;
+- goto err_put_master;
++ goto err_clk_disable;
+ }
+
+ rbspi->base = ioremap(r->start, r->end - r->start + 1);
+ if (!rbspi->base) {
+ err = -ENXIO;
+- goto err_put_master;
++ goto err_clk_disable;
+ }
+
+ rbspi->master = master;
+- rbspi->spi_ctrl_flash = get_spi_ctrl(SPI_FLASH_HZ, "FLASH");
+- rbspi->spi_ctrl_fread = get_spi_ctrl(SPI_CPLD_HZ, "CPLD");
++ rbspi->spi_ctrl_flash = get_spi_ctrl(rbspi, SPI_FLASH_HZ, "FLASH");
++ rbspi->spi_ctrl_fread = get_spi_ctrl(rbspi, SPI_CPLD_HZ, "CPLD");
+ rbspi->cs_wait = -1;
+
+ spin_lock_init(&rbspi->lock);
+@@ -428,6 +455,10 @@ static int rb4xx_spi_probe(struct platfo
+
+ err_iounmap:
+ iounmap(rbspi->base);
++err_clk_disable:
++ clk_disable(rbspi->ahb_clk);
++err_clk_put:
++ clk_put(rbspi->ahb_clk);
+ err_put_master:
+ platform_set_drvdata(pdev, NULL);
+ spi_master_put(master);
+@@ -440,6 +471,8 @@ static int rb4xx_spi_remove(struct platf
+ struct rb4xx_spi *rbspi = platform_get_drvdata(pdev);
+
+ iounmap(rbspi->base);
++ clk_disable(rbspi->ahb_clk);
++ clk_put(rbspi->ahb_clk);
+ platform_set_drvdata(pdev, NULL);
+ spi_master_put(rbspi->master);
+
--- /dev/null
+--- a/drivers/mtd/tplinkpart.c
++++ b/drivers/mtd/tplinkpart.c
+@@ -108,7 +108,7 @@ static int tplink_check_rootfs_magic(str
+
+ static int tplink_parse_partitions(struct mtd_info *master,
+ struct mtd_partition **pparts,
+- unsigned long origin)
++ struct mtd_part_parser_data *data)
+ {
+ struct mtd_partition *parts;
+ struct tplink_fw_header *header;
--- /dev/null
+--- a/drivers/mtd/wrt160nl_part.c
++++ b/drivers/mtd/wrt160nl_part.c
+@@ -85,7 +85,7 @@ static struct mtd_partition trx_parts[TR
+
+ static int wrt160nl_parse_partitions(struct mtd_info *master,
+ struct mtd_partition **pparts,
+- unsigned long origin)
++ struct mtd_part_parser_data *data)
+ {
+ struct wrt160nl_header *header;
+ struct trx_header *theader;
--- /dev/null
+--- a/drivers/mtd/maps/physmap.c
++++ b/drivers/mtd/maps/physmap.c
+@@ -29,6 +29,66 @@ struct physmap_flash_info {
+ struct map_info map[MAX_RESOURCES];
+ };
+
++static struct platform_device *physmap_map2pdev(struct map_info *map)
++{
++ return (struct platform_device *) map->map_priv_1;
++}
++
++static void physmap_lock(struct map_info *map)
++{
++ struct platform_device *pdev;
++ struct physmap_flash_data *physmap_data;
++
++ pdev = physmap_map2pdev(map);
++ physmap_data = pdev->dev.platform_data;
++ physmap_data->lock(pdev);
++}
++
++static void physmap_unlock(struct map_info *map)
++{
++ struct platform_device *pdev;
++ struct physmap_flash_data *physmap_data;
++
++ pdev = physmap_map2pdev(map);
++ physmap_data = pdev->dev.platform_data;
++ physmap_data->unlock(pdev);
++}
++
++static map_word physmap_flash_read_lock(struct map_info *map, unsigned long ofs)
++{
++ map_word ret;
++
++ physmap_lock(map);
++ ret = inline_map_read(map, ofs);
++ physmap_unlock(map);
++
++ return ret;
++}
++
++static void physmap_flash_write_lock(struct map_info *map, map_word d,
++ unsigned long ofs)
++{
++ physmap_lock(map);
++ inline_map_write(map, d, ofs);
++ physmap_unlock(map);
++}
++
++static void physmap_flash_copy_from_lock(struct map_info *map, void *to,
++ unsigned long from, ssize_t len)
++{
++ physmap_lock(map);
++ inline_map_copy_from(map, to, from, len);
++ physmap_unlock(map);
++}
++
++static void physmap_flash_copy_to_lock(struct map_info *map, unsigned long to,
++ const void *from, ssize_t len)
++{
++ physmap_lock(map);
++ inline_map_copy_to(map, to, from, len);
++ physmap_unlock(map);
++}
++
+ static int physmap_flash_remove(struct platform_device *dev)
+ {
+ struct physmap_flash_info *info;
+@@ -140,6 +200,13 @@ static int physmap_flash_probe(struct pl
+
+ simple_map_init(&info->map[i]);
+
++ if (physmap_data->lock && physmap_data->unlock) {
++ info->map[i].read = physmap_flash_read_lock;
++ info->map[i].write = physmap_flash_write_lock;
++ info->map[i].copy_from = physmap_flash_copy_from_lock;
++ info->map[i].copy_to = physmap_flash_copy_to_lock;
++ }
++
+ probe_type = rom_probe_types;
+ if (physmap_data->probe_type == NULL) {
+ for (; info->mtd[i] == NULL && *probe_type != NULL; probe_type++)
+--- a/include/linux/mtd/physmap.h
++++ b/include/linux/mtd/physmap.h
+@@ -26,6 +26,8 @@ struct physmap_flash_data {
+ unsigned int width;
+ int (*init)(struct platform_device *);
+ void (*exit)(struct platform_device *);
++ void (*lock)(struct platform_device *);
++ void (*unlock)(struct platform_device *);
+ void (*set_vpp)(struct platform_device *, int);
+ unsigned int nr_parts;
+ unsigned int pfow_base;
--- /dev/null
+--- a/drivers/mtd/chips/jedec_probe.c
++++ b/drivers/mtd/chips/jedec_probe.c
+@@ -148,6 +148,7 @@
+ #define SST39LF160 0x2782
+ #define SST39VF1601 0x234b
+ #define SST39VF3201 0x235b
++#define SST39VF6401B 0x236d
+ #define SST39WF1601 0x274b
+ #define SST39WF1602 0x274a
+ #define SST39LF512 0x00D4
+@@ -1568,6 +1569,18 @@ static const struct amd_flash_info jedec
+ ERASEINFO(0x10000,64),
+ }
+ }, {
++ .mfr_id = CFI_MFR_SST,
++ .dev_id = SST39VF6401B,
++ .name = "SST 39VF6401B",
++ .devtypes = CFI_DEVICETYPE_X16,
++ .uaddr = MTD_UADDR_0xAAAA_0x5555,
++ .dev_size = SIZE_8MiB,
++ .cmd_set = P_ID_AMD_STD,
++ .nr_regions = 1,
++ .regions = {
++ ERASEINFO(0x10000,128)
++ }
++ }, {
+ .mfr_id = CFI_MFR_ST,
+ .dev_id = M29F800AB,
+ .name = "ST M29F800AB",
--- /dev/null
+--- a/drivers/mtd/chips/cfi_cmdset_0002.c
++++ b/drivers/mtd/chips/cfi_cmdset_0002.c
+@@ -1214,8 +1214,8 @@ static int __xipram do_write_oneword(str
+ break;
+ }
+
+- if (chip_ready(map, adr))
+- break;
++ if (chip_good(map, adr, datum))
++ goto enable_xip;
+
+ /* Latency issues. Drop the lock, wait a while and retry */
+ UDELAY(map, chip, adr, 1);
+@@ -1231,6 +1231,8 @@ static int __xipram do_write_oneword(str
+
+ ret = -EIO;
+ }
++
++ enable_xip:
+ xip_enable(map, chip, adr);
+ op_done:
+ chip->state = FL_READY;
+@@ -1563,7 +1565,6 @@ static int cfi_amdstd_write_buffers(stru
+ return 0;
+ }
+
+-
+ /*
+ * Handle devices with one erase region, that only implement
+ * the chip erase command.
+@@ -1627,8 +1628,8 @@ static int __xipram do_erase_chip(struct
+ chip->erase_suspended = 0;
+ }
+
+- if (chip_ready(map, adr))
+- break;
++ if (chip_good(map, adr, map_word_ff(map)))
++ goto op_done;
+
+ if (time_after(jiffies, timeo)) {
+ printk(KERN_WARNING "MTD %s(): software timeout\n",
+@@ -1648,6 +1649,7 @@ static int __xipram do_erase_chip(struct
+ ret = -EIO;
+ }
+
++ op_done:
+ chip->state = FL_READY;
+ xip_enable(map, chip, adr);
+ put_chip(map, chip, adr);
+@@ -1715,9 +1717,9 @@ static int __xipram do_erase_oneblock(st
+ chip->erase_suspended = 0;
+ }
+
+- if (chip_ready(map, adr)) {
++ if (chip_good(map, adr, map_word_ff(map))) {
+ xip_enable(map, chip, adr);
+- break;
++ goto op_done;
+ }
+
+ if (time_after(jiffies, timeo)) {
+@@ -1739,6 +1741,7 @@ static int __xipram do_erase_oneblock(st
+ ret = -EIO;
+ }
+
++ op_done:
+ chip->state = FL_READY;
+ put_chip(map, chip, adr);
+ mutex_unlock(&chip->mutex);
--- /dev/null
+--- a/drivers/mtd/Kconfig
++++ b/drivers/mtd/Kconfig
+@@ -148,6 +148,12 @@ config MTD_AR7_PARTS
+ ---help---
+ TI AR7 partitioning support
+
++config MTD_WRT160NL_PARTS
++ tristate "Linksys WRT160NL partitioning support"
++ depends on MTD_PARTITIONS && ATH79_MACH_WRT160NL
++ ---help---
++ Linksys WRT160NL partitioning support
++
+ config MTD_MYLOADER_PARTS
+ tristate "MyLoader partition parsing"
+ depends on ADM5120 || ATHEROS_AR231X || ATHEROS_AR71XX || ATH79
+--- a/drivers/mtd/Makefile
++++ b/drivers/mtd/Makefile
+@@ -11,6 +11,7 @@ obj-$(CONFIG_MTD_REDBOOT_PARTS) += redbo
+ obj-$(CONFIG_MTD_CMDLINE_PARTS) += cmdlinepart.o
+ obj-$(CONFIG_MTD_AFS_PARTS) += afs.o
+ obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o
++obj-$(CONFIG_MTD_WRT160NL_PARTS) += wrt160nl_part.o
+ obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o
+
+ # 'Users' - code which presents functionality to userspace.
--- /dev/null
+--- a/drivers/mtd/Kconfig
++++ b/drivers/mtd/Kconfig
+@@ -150,7 +150,7 @@ config MTD_AR7_PARTS
+
+ config MTD_WRT160NL_PARTS
+ tristate "Linksys WRT160NL partitioning support"
+- depends on MTD_PARTITIONS && ATH79_MACH_WRT160NL
++ depends on ATH79_MACH_WRT160NL
+ ---help---
+ Linksys WRT160NL partitioning support
+
+@@ -170,6 +170,12 @@ config MTD_MYLOADER_PARTS
+ You will still need the parsing functions to be called by the driver
+ for your particular device. It won't happen automatically.
+
++config MTD_TPLINK_PARTS
++ tristate "TP-Link AR7XXX/AR9XXX partitioning support"
++ depends on ATH79
++ ---help---
++ TBD.
++
+ comment "User Modules And Translation Layers"
+
+ config MTD_CHAR
+--- a/drivers/mtd/Makefile
++++ b/drivers/mtd/Makefile
+@@ -13,6 +13,7 @@ obj-$(CONFIG_MTD_AFS_PARTS) += afs.o
+ obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o
+ obj-$(CONFIG_MTD_WRT160NL_PARTS) += wrt160nl_part.o
+ obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o
++obj-$(CONFIG_MTD_TPLINK_PARTS) += tplinkpart.o
+
+ # 'Users' - code which presents functionality to userspace.
+ obj-$(CONFIG_MTD_CHAR) += mtdchar.o
--- /dev/null
+--- a/drivers/mtd/devices/m25p80.c
++++ b/drivers/mtd/devices/m25p80.c
+@@ -100,6 +100,7 @@ struct m25p {
+ u16 addr_width;
+ u8 erase_opcode;
+ u8 *command;
++ size_t max_read_len;
+ };
+
+ static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
+@@ -352,6 +353,7 @@ static int m25p80_read(struct mtd_info *
+ struct m25p *flash = mtd_to_m25p(mtd);
+ struct spi_transfer t[2];
+ struct spi_message m;
++ loff_t ofs;
+
+ pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
+ __func__, (u32)from, len);
+@@ -374,8 +376,6 @@ static int m25p80_read(struct mtd_info *
+ t[0].len = m25p_cmdsz(flash) + FAST_READ_DUMMY_BYTE;
+ spi_message_add_tail(&t[0], &m);
+
+- t[1].rx_buf = buf;
+- t[1].len = len;
+ spi_message_add_tail(&t[1], &m);
+
+ /* Byte count starts at zero. */
+@@ -383,13 +383,6 @@ static int m25p80_read(struct mtd_info *
+
+ mutex_lock(&flash->lock);
+
+- /* Wait till previous write/erase is done. */
+- if (wait_till_ready(flash)) {
+- /* REVISIT status return?? */
+- mutex_unlock(&flash->lock);
+- return 1;
+- }
+-
+ /* FIXME switch to OPCODE_FAST_READ. It's required for higher
+ * clocks; and at this writing, every chip this driver handles
+ * supports that opcode.
+@@ -397,11 +390,44 @@ static int m25p80_read(struct mtd_info *
+
+ /* Set up the write data buffer. */
+ flash->command[0] = OPCODE_READ;
+- m25p_addr2cmd(flash, from, flash->command);
+
+- spi_sync(flash->spi, &m);
++ ofs = 0;
++ while (len) {
++ size_t readlen;
++ size_t done;
++ int ret;
++
++ ret = wait_till_ready(flash);
++ if (ret) {
++ mutex_unlock(&flash->lock);
++ return 1;
++ }
++
++ if (flash->max_read_len > 0 &&
++ flash->max_read_len < len)
++ readlen = flash->max_read_len;
++ else
++ readlen = len;
++
++ t[1].rx_buf = buf + ofs;
++ t[1].len = readlen;
++
++ m25p_addr2cmd(flash, from + ofs, flash->command);
++
++ spi_sync(flash->spi, &m);
+
+- *retlen = m.actual_length - m25p_cmdsz(flash) - FAST_READ_DUMMY_BYTE;
++ done = m.actual_length - m25p_cmdsz(flash) -
++ FAST_READ_DUMMY_BYTE;
++ if (done != readlen) {
++ mutex_unlock(&flash->lock);
++ return 1;
++ }
++
++ ofs += done;
++ len -= done;
++ }
++
++ *retlen = ofs;
+
+ mutex_unlock(&flash->lock);
+
+@@ -924,6 +950,12 @@ static int __devinit m25p_probe(struct s
+ flash->mtd.erase = m25p80_erase;
+ flash->mtd.read = m25p80_read;
+
++ if (data && data->max_read_len) {
++ flash->max_read_len = data->max_read_len;
++ dev_warn(&spi->dev, "max_read_len set to %d bytes\n",
++ flash->max_read_len);
++ }
++
+ /* sst flash chips use AAI word program */
+ if (JEDEC_MFR(info->jedec_id) == CFI_MFR_SST)
+ flash->mtd.write = sst_write;
+--- a/include/linux/spi/flash.h
++++ b/include/linux/spi/flash.h
+@@ -25,6 +25,7 @@ struct flash_platform_data {
+
+ char *type;
+
++ size_t max_read_len;
+ /* we'll likely add more ... use JEDEC IDs, etc */
+ };
+
--- /dev/null
+--- a/drivers/mtd/devices/m25p80.c
++++ b/drivers/mtd/devices/m25p80.c
+@@ -1016,7 +1016,9 @@ static int __devinit m25p_probe(struct s
+ /* partitions should match sector boundaries; and it may be good to
+ * use readonly partitions for writeprotected sectors (BP2..BP0).
+ */
+- return mtd_device_parse_register(&flash->mtd, NULL, &ppdata,
++ return mtd_device_parse_register(&flash->mtd,
++ data ? data->part_probes : NULL,
++ &ppdata,
+ data ? data->parts : NULL,
+ data ? data->nr_parts : 0);
+ }
+--- a/include/linux/spi/flash.h
++++ b/include/linux/spi/flash.h
+@@ -24,6 +24,7 @@ struct flash_platform_data {
+ unsigned int nr_parts;
+
+ char *type;
++ const char **part_probes;
+
+ size_t max_read_len;
+ /* we'll likely add more ... use JEDEC IDs, etc */
--- /dev/null
+--- a/drivers/mtd/redboot.c
++++ b/drivers/mtd/redboot.c
+@@ -79,31 +79,32 @@ static int parse_redboot_partitions(stru
+ static char nullstring[] = "unallocated";
+ #endif
+
++ buf = vmalloc(master->erasesize);
++ if (!buf)
++ return -ENOMEM;
++
++ restart:
+ if ( directory < 0 ) {
+ offset = master->size + directory * master->erasesize;
+- while (master->block_isbad &&
++ while (master->block_isbad &&
+ master->block_isbad(master, offset)) {
+ if (!offset) {
+ nogood:
+ printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n");
++ vfree(buf);
+ return -EIO;
+ }
+ offset -= master->erasesize;
+ }
+ } else {
+ offset = directory * master->erasesize;
+- while (master->block_isbad &&
++ while (master->block_isbad &&
+ master->block_isbad(master, offset)) {
+ offset += master->erasesize;
+ if (offset == master->size)
+ goto nogood;
+ }
+ }
+- buf = vmalloc(master->erasesize);
+-
+- if (!buf)
+- return -ENOMEM;
+-
+ printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n",
+ master->name, offset);
+
+@@ -175,6 +176,11 @@ static int parse_redboot_partitions(stru
+ }
+ if (i == numslots) {
+ /* Didn't find it */
++ if (offset + master->erasesize < master->size) {
++ /* not at the end of the flash yet, maybe next block :) */
++ directory++;
++ goto restart;
++ }
+ printk(KERN_NOTICE "No RedBoot partition table detected in %s\n",
+ master->name);
+ ret = 0;
--- /dev/null
+--- a/drivers/mtd/nand/Kconfig
++++ b/drivers/mtd/nand/Kconfig
+@@ -537,4 +537,8 @@ config MTD_NAND_FSMC
+ Enables support for NAND Flash chips on the ST Microelectronics
+ Flexible Static Memory Controller (FSMC)
+
++config MTD_NAND_RB4XX
++ tristate "NAND flash driver for RouterBoard 4xx series"
++ depends on MTD_NAND && ATH79_MACH_RB4XX
++
+ endif # MTD_NAND
+--- a/drivers/mtd/nand/Makefile
++++ b/drivers/mtd/nand/Makefile
+@@ -33,6 +33,7 @@ obj-$(CONFIG_MTD_NAND_CM_X270) += cmx27
+ obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o
+ obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o
+ obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
++obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o
+ obj-$(CONFIG_MTD_ALAUDA) += alauda.o
+ obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o
+ obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o
--- /dev/null
+--- a/drivers/mtd/nand/Kconfig
++++ b/drivers/mtd/nand/Kconfig
+@@ -541,4 +541,8 @@ config MTD_NAND_RB4XX
+ tristate "NAND flash driver for RouterBoard 4xx series"
+ depends on MTD_NAND && ATH79_MACH_RB4XX
+
++config MTD_NAND_RB750
++ tristate "NAND flash driver for the RouterBoard 750"
++ depends on MTD_NAND && ATH79_MACH_RB750
++
+ endif # MTD_NAND
+--- a/drivers/mtd/nand/Makefile
++++ b/drivers/mtd/nand/Makefile
+@@ -34,6 +34,7 @@ obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx
+ obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o
+ obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
+ obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o
++obj-$(CONFIG_MTD_NAND_RB750) += rb750_nand.o
+ obj-$(CONFIG_MTD_ALAUDA) += alauda.o
+ obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o
+ obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o
--- /dev/null
+--- a/drivers/mtd/chips/cfi_cmdset_0002.c
++++ b/drivers/mtd/chips/cfi_cmdset_0002.c
+@@ -39,7 +39,7 @@
+ #include <linux/mtd/xip.h>
+
+ #define AMD_BOOTLOC_BUG
+-#define FORCE_WORD_WRITE 0
++#define FORCE_WORD_WRITE 1
+
+ #define MAX_WORD_RETRIES 3
+
+@@ -50,7 +50,9 @@
+
+ static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
+ static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
++#if !FORCE_WORD_WRITE
+ static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
++#endif
+ static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
+ static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
+ static void cfi_amdstd_sync (struct mtd_info *);
+@@ -183,6 +185,7 @@ static void fixup_amd_bootblock(struct m
+ }
+ #endif
+
++#if !FORCE_WORD_WRITE
+ static void fixup_use_write_buffers(struct mtd_info *mtd)
+ {
+ struct map_info *map = mtd->priv;
+@@ -192,6 +195,7 @@ static void fixup_use_write_buffers(stru
+ mtd->write = cfi_amdstd_write_buffers;
+ }
+ }
++#endif /* !FORCE_WORD_WRITE */
+
+ /* Atmel chips don't use the same PRI format as AMD chips */
+ static void fixup_convert_atmel_pri(struct mtd_info *mtd)
+@@ -1374,6 +1378,7 @@ static int cfi_amdstd_write_words(struct
+ /*
+ * FIXME: interleaved mode not tested, and probably not supported!
+ */
++#if !FORCE_WORD_WRITE
+ static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
+ unsigned long adr, const u_char *buf,
+ int len)
+@@ -1485,7 +1490,6 @@ static int __xipram do_write_buffer(stru
+ return ret;
+ }
+
+-
+ static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
+ size_t *retlen, const u_char *buf)
+ {
+@@ -1564,6 +1568,7 @@ static int cfi_amdstd_write_buffers(stru
+
+ return 0;
+ }
++#endif /* !FORCE_WORD_WRITE */
+
+ /*
+ * Handle devices with one erase region, that only implement
--- /dev/null
+--- a/drivers/net/ethernet/atheros/Kconfig
++++ b/drivers/net/ethernet/atheros/Kconfig
+@@ -67,4 +67,6 @@ config ATL1C
+ To compile this driver as a module, choose M here. The module
+ will be called atl1c.
+
++source drivers/net/ethernet/atheros/ag71xx/Kconfig
++
+ endif # NET_VENDOR_ATHEROS
+--- a/drivers/net/ethernet/atheros/Makefile
++++ b/drivers/net/ethernet/atheros/Makefile
+@@ -2,6 +2,7 @@
+ # Makefile for the Atheros network device drivers.
+ #
+
++obj-$(CONFIG_AG71XX) += ag71xx/
+ obj-$(CONFIG_ATL1) += atlx/
+ obj-$(CONFIG_ATL2) += atlx/
+ obj-$(CONFIG_ATL1E) += atl1e/
--- /dev/null
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -124,6 +124,11 @@ config RTL8306_PHY
+ tristate "Driver for Realtek RTL8306S switches"
+ select SWCONFIG
+
++config MICREL_PHY
++ tristate "Drivers for Micrel/Kendin PHYs"
++ ---help---
++ Currently has a driver for the KSZ8041
++
+ config FIXED_PHY
+ bool "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs"
+ depends on PHYLIB=y
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -25,6 +25,7 @@ obj-$(CONFIG_RTL8366S_PHY) += rtl8366s.o
+ obj-$(CONFIG_RTL8366RB_PHY) += rtl8366rb.o
+ obj-$(CONFIG_RTL8367_PHY) += rtl8367.o
+ obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o
++obj-$(CONFIG_MICREL_PHY) += micrel.o
+ obj-$(CONFIG_FIXED_PHY) += fixed.o
+ obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o
+ obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o
--- /dev/null
+--- a/net/dsa/tag_trailer.c
++++ b/net/dsa/tag_trailer.c
+@@ -87,7 +87,7 @@ static int trailer_rcv(struct sk_buff *s
+
+ trailer = skb_tail_pointer(skb) - 4;
+ if (trailer[0] != 0x80 || (trailer[1] & 0xf8) != 0x00 ||
+- (trailer[3] & 0xef) != 0x00 || trailer[3] != 0x00)
++ (trailer[2] & 0xef) != 0x00 || (trailer[3] & 0xfe) != 0x00)
+ goto out_drop;
+
+ source_port = trailer[1] & 7;
--- /dev/null
+--- a/net/dsa/Kconfig
++++ b/net/dsa/Kconfig
+@@ -36,6 +36,13 @@ config NET_DSA_MV88E6060
+ This enables support for the Marvell 88E6060 ethernet switch
+ chip.
+
++config NET_DSA_MV88E6063
++ bool "Marvell 88E6063 ethernet switch chip support"
++ select NET_DSA_TAG_TRAILER
++ ---help---
++ This enables support for the Marvell 88E6063 ethernet switch
++ chip
++
+ config NET_DSA_MV88E6XXX_NEED_PPU
+ bool
+ default n
+--- a/net/dsa/Makefile
++++ b/net/dsa/Makefile
+@@ -6,6 +6,7 @@ obj-$(CONFIG_NET_DSA_TAG_TRAILER) += tag
+ # switch drivers
+ obj-$(CONFIG_NET_DSA_MV88E6XXX) += mv88e6xxx.o
+ obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o
++obj-$(CONFIG_NET_DSA_MV88E6063) += mv88e6063.o
+ obj-$(CONFIG_NET_DSA_MV88E6123_61_65) += mv88e6123_61_65.o
+ obj-$(CONFIG_NET_DSA_MV88E6131) += mv88e6131.o
+
--- /dev/null
+--- a/drivers/Makefile
++++ b/drivers/Makefile
+@@ -51,8 +51,8 @@ obj-$(CONFIG_IDE) += ide/
+ obj-$(CONFIG_SCSI) += scsi/
+ obj-$(CONFIG_ATA) += ata/
+ obj-$(CONFIG_TARGET_CORE) += target/
+-obj-$(CONFIG_MTD) += mtd/
+ obj-$(CONFIG_SPI) += spi/
++obj-$(CONFIG_MTD) += mtd/
+ obj-y += net/
+ obj-$(CONFIG_ATM) += atm/
+ obj-$(CONFIG_FUSION) += message/
--- /dev/null
+--- a/include/linux/spi/spi.h
++++ b/include/linux/spi/spi.h
+@@ -441,6 +441,8 @@ struct spi_transfer {
+ dma_addr_t rx_dma;
+
+ unsigned cs_change:1;
++ unsigned verify:1;
++ unsigned fast_write:1;
+ u8 bits_per_word;
+ u16 delay_usecs;
+ u32 speed_hz;
+@@ -482,6 +484,7 @@ struct spi_message {
+ struct spi_device *spi;
+
+ unsigned is_dma_mapped:1;
++ unsigned fast_read:1;
+
+ /* REVISIT: we might want a flag affecting the behavior of the
+ * last transfer ... allowing things like "read 16 bit length L"
--- /dev/null
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -289,6 +289,12 @@ config SPI_PXA2XX
+ config SPI_PXA2XX_PCI
+ def_bool SPI_PXA2XX && X86_32 && PCI
+
++config SPI_RB4XX
++ tristate "Mikrotik RB4XX SPI master"
++ depends on SPI_MASTER && ATH79_MACH_RB4XX
++ help
++ SPI controller driver for the Mikrotik RB4xx series boards.
++
+ config SPI_S3C24XX
+ tristate "Samsung S3C24XX series SPI"
+ depends on ARCH_S3C2410 && EXPERIMENTAL
+--- a/drivers/spi/Makefile
++++ b/drivers/spi/Makefile
+@@ -45,6 +45,7 @@ obj-$(CONFIG_SPI_PL022) += spi-pl022.o
+ obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o
+ obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx.o
+ obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o
++obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o
+ obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
+ spi-s3c24xx-hw-y := spi-s3c24xx.o
+ spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o
--- /dev/null
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -441,6 +441,13 @@ config SPI_TLE62X0
+ sysfs interface, with each line presented as a kind of GPIO
+ exposing both switch control and diagnostic feedback.
+
++config SPI_RB4XX_CPLD
++ tristate "MikroTik RB4XX CPLD driver"
++ depends on ATH79_MACH_RB4XX
++ help
++ SPI driver for the Xilinx CPLD chip present on the
++ MikroTik RB4xx boards.
++
+ #
+ # Add new SPI protocol masters in alphabetical order above this line
+ #
+--- a/drivers/spi/Makefile
++++ b/drivers/spi/Makefile
+@@ -46,6 +46,7 @@ obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.
+ obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx.o
+ obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o
+ obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o
++obj-$(CONFIG_SPI_RB4XX_CPLD) += spi-rb4xx-cpld.o
+ obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
+ spi-s3c24xx-hw-y := spi-s3c24xx.o
+ spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o
--- /dev/null
+--- a/drivers/spi/Makefile
++++ b/drivers/spi/Makefile
+@@ -12,6 +12,7 @@ obj-$(CONFIG_SPI_SPIDEV) += spidev.o
+ # SPI master controller drivers (bus)
+ obj-$(CONFIG_SPI_ALTERA) += spi-altera.o
+ obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o
++obj-$(CONFIG_SPI_AP83) += spi-ap83.o
+ obj-$(CONFIG_SPI_ATH79) += spi-ath79.o
+ obj-$(CONFIG_SPI_AU1550) += spi-au1550.o
+ obj-$(CONFIG_SPI_BFIN) += spi-bfin5xx.o
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -59,6 +59,14 @@ config SPI_ALTERA
+ help
+ This is the driver for the Altera SPI Controller.
+
++config SPI_AP83
++ tristate "Atheros AP83 specific SPI Controller"
++ depends on SPI_MASTER && ATH79_MACH_AP83
++ select SPI_BITBANG
++ help
++ This is a specific SPI controller driver for the Atheros AP83
++ reference board.
++
+ config SPI_ATH79
+ tristate "Atheros AR71XX/AR724X/AR913X SPI controller driver"
+ depends on ATH79 && GENERIC_GPIO
--- /dev/null
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -456,6 +456,11 @@ config SPI_RB4XX_CPLD
+ SPI driver for the Xilinx CPLD chip present on the
+ MikroTik RB4xx boards.
+
++config SPI_VSC7385
++ tristate "Vitesse VSC7385 ethernet switch driver"
++ help
++ SPI driver for the Vitesse VSC7385 ethernet switch.
++
+ #
+ # Add new SPI protocol masters in alphabetical order above this line
+ #
+--- a/drivers/spi/Makefile
++++ b/drivers/spi/Makefile
+@@ -61,5 +61,5 @@ obj-$(CONFIG_SPI_TI_SSP) += spi-ti-ssp.
+ obj-$(CONFIG_SPI_TLE62X0) += spi-tle62x0.o
+ obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o
+ obj-$(CONFIG_SPI_TXX9) += spi-txx9.o
++obj-$(CONFIG_SPI_VSC7385) += spi-vsc7385.o
+ obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o
+-
--- /dev/null
+--- a/drivers/leds/Kconfig
++++ b/drivers/leds/Kconfig
+@@ -395,6 +395,13 @@ config LEDS_TRIGGERS
+ These triggers allow kernel events to drive the LEDs and can
+ be configured via sysfs. If unsure, say Y.
+
++config LEDS_WNDR3700_USB
++ tristate "NETGEAR WNDR3700 USB LED driver"
++ depends on LEDS_CLASS && ATH79_MACH_WNDR3700
++ help
++ This option enables support for the USB LED found on the
++ NETGEAR WNDR3700 board.
++
+ comment "LED Triggers"
+
+ config LEDS_TRIGGER_TIMER
+--- a/drivers/leds/Makefile
++++ b/drivers/leds/Makefile
+@@ -33,6 +33,7 @@ obj-$(CONFIG_LEDS_DA903X) += leds-da903
+ obj-$(CONFIG_LEDS_WM831X_STATUS) += leds-wm831x-status.o
+ obj-$(CONFIG_LEDS_WM8350) += leds-wm8350.o
+ obj-$(CONFIG_LEDS_PWM) += leds-pwm.o
++obj-${CONFIG_LEDS_WNDR3700_USB} += leds-wndr3700-usb.o
+ obj-$(CONFIG_LEDS_REGULATOR) += leds-regulator.o
+ obj-$(CONFIG_LEDS_INTEL_SS4200) += leds-ss4200.o
+ obj-$(CONFIG_LEDS_LT3593) += leds-lt3593.o
--- /dev/null
+--- a/drivers/leds/Kconfig
++++ b/drivers/leds/Kconfig
+@@ -402,6 +402,10 @@ config LEDS_WNDR3700_USB
+ This option enables support for the USB LED found on the
+ NETGEAR WNDR3700 board.
+
++config LEDS_RB750
++ tristate "LED driver for the Mikrotik RouterBOARD 750"
++ depends on LEDS_CLASS && ATH79_MACH_RB750
++
+ comment "LED Triggers"
+
+ config LEDS_TRIGGER_TIMER
+--- a/drivers/leds/Makefile
++++ b/drivers/leds/Makefile
+@@ -40,6 +40,7 @@ obj-$(CONFIG_LEDS_LT3593) += leds-lt359
+ obj-$(CONFIG_LEDS_ADP5520) += leds-adp5520.o
+ obj-$(CONFIG_LEDS_DELL_NETBOOKS) += dell-led.o
+ obj-$(CONFIG_LEDS_MC13783) += leds-mc13783.o
++obj-$(CONFIG_LEDS_RB750) += leds-rb750.o
+ obj-$(CONFIG_LEDS_NS2) += leds-ns2.o
+ obj-$(CONFIG_LEDS_NETXBIG) += leds-netxbig.o
+ obj-$(CONFIG_LEDS_ASIC3) += leds-asic3.o
--- /dev/null
+--- a/drivers/gpio/Kconfig
++++ b/drivers/gpio/Kconfig
+@@ -489,4 +489,13 @@ config GPIO_TPS65910
+ help
+ Select this option to enable GPIO driver for the TPS65910
+ chip family.
++
++comment "Other GPIO expanders"
++
++config GPIO_NXP_74HC153
++ tristate "NXP 74HC153 Dual 4-input multiplexer"
++ help
++ Platform driver for NXP 74HC153 Dual 4-input Multiplexer. This
++ provides a GPIO interface supporting input mode only.
++
+ endif
+--- a/drivers/gpio/Makefile
++++ b/drivers/gpio/Makefile
+@@ -35,6 +35,7 @@ obj-$(CONFIG_GPIO_MSM_V2) += gpio-msm-v2
+ obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o
+ obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o
+ obj-$(CONFIG_PLAT_NOMADIK) += gpio-nomadik.o
++obj-$(CONFIG_GPIO_NXP_74HC153) += gpio-nxp-74hc153.o
+ obj-$(CONFIG_ARCH_OMAP) += gpio-omap.o
+ obj-$(CONFIG_GPIO_PCA953X) += gpio-pca953x.o
+ obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o
--- /dev/null
+--- a/arch/mips/Makefile
++++ b/arch/mips/Makefile
+@@ -174,6 +174,7 @@ endif
+ #
+ libs-$(CONFIG_ARC) += arch/mips/fw/arc/
+ libs-$(CONFIG_CFE) += arch/mips/fw/cfe/
++libs-$(CONFIG_MYLOADER) += arch/mips/fw/myloader/
+ libs-$(CONFIG_SNIPROM) += arch/mips/fw/sni/
+ libs-y += arch/mips/fw/lib/
+
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -953,6 +953,9 @@ config MIPS_NILE4
+ config MIPS_DISABLE_OBSOLETE_IDE
+ bool
+
++config MYLOADER
++ bool
++
+ config SYNC_R4K
+ bool
+
--- /dev/null
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -15,6 +15,7 @@
+ #include <linux/init.h>
+ #include <linux/delay.h>
+ #include <linux/irq.h>
++#include <linux/etherdevice.h>
+ #include <linux/platform_device.h>
+ #include <linux/ath9k_platform.h>
+
+@@ -22,6 +23,7 @@
+ #include <asm/mach-ath79/ar71xx_regs.h>
+ #include "dev-wmac.h"
+
++static u8 ath79_wmac_mac[ETH_ALEN];
+ static struct ath9k_platform_data ath79_wmac_data;
+
+ static struct resource ath79_wmac_resources[] = {
+@@ -116,7 +118,7 @@ static void ar934x_wmac_setup(void)
+ ath79_wmac_data.is_clk_25mhz = true;
+ }
+
+-void __init ath79_register_wmac(u8 *cal_data)
++void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
+ {
+ if (soc_is_ar913x())
+ ar913x_wmac_setup();
+@@ -131,5 +133,10 @@ void __init ath79_register_wmac(u8 *cal_
+ memcpy(ath79_wmac_data.eeprom_data, cal_data,
+ sizeof(ath79_wmac_data.eeprom_data));
+
++ if (mac_addr) {
++ memcpy(ath79_wmac_mac, mac_addr, sizeof(ath79_wmac_mac));
++ ath79_wmac_data.macaddr = ath79_wmac_mac;
++ }
++
+ platform_device_register(&ath79_wmac_device);
+ }
+--- a/arch/mips/ath79/dev-wmac.h
++++ b/arch/mips/ath79/dev-wmac.h
+@@ -12,6 +12,6 @@
+ #ifndef _ATH79_DEV_WMAC_H
+ #define _ATH79_DEV_WMAC_H
+
+-void ath79_register_wmac(u8 *cal_data);
++void ath79_register_wmac(u8 *cal_data, u8 *mac_addr);
+
+ #endif /* _ATH79_DEV_WMAC_H */
+--- a/arch/mips/ath79/mach-ap81.c
++++ b/arch/mips/ath79/mach-ap81.c
+@@ -98,7 +98,7 @@ static void __init ap81_setup(void)
+ ap81_gpio_keys);
+ ath79_register_spi(&ap81_spi_data, ap81_spi_info,
+ ARRAY_SIZE(ap81_spi_info));
+- ath79_register_wmac(cal_data);
++ ath79_register_wmac(cal_data, NULL);
+ ath79_register_usb();
+ }
+
+--- a/arch/mips/ath79/mach-db120.c
++++ b/arch/mips/ath79/mach-db120.c
+@@ -153,7 +153,7 @@ static void __init db120_setup(void)
+ ath79_register_spi(&db120_spi_data, db120_spi_info,
+ ARRAY_SIZE(db120_spi_info));
+ ath79_register_usb();
+- ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET);
++ ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL);
+ db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
+ }
+
+--- a/arch/mips/ath79/mach-ap121.c
++++ b/arch/mips/ath79/mach-ap121.c
+@@ -91,7 +91,7 @@ static void __init ap121_setup(void)
+ ath79_register_spi(&ap121_spi_data, ap121_spi_info,
+ ARRAY_SIZE(ap121_spi_info));
+ ath79_register_usb();
+- ath79_register_wmac(cal_data);
++ ath79_register_wmac(cal_data, NULL);
+ }
+
+ MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board",
--- /dev/null
+--- a/arch/mips/ath79/gpio.c
++++ b/arch/mips/ath79/gpio.c
+@@ -25,7 +25,9 @@
+ #include <asm/mach-ath79/ath79.h>
+ #include "common.h"
+
+-static void __iomem *ath79_gpio_base;
++void __iomem *ath79_gpio_base;
++EXPORT_SYMBOL_GPL(ath79_gpio_base);
++
+ static unsigned long ath79_gpio_count;
+ static DEFINE_SPINLOCK(ath79_gpio_lock);
+
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
++++ b/arch/mips/include/asm/mach-ath79/ath79.h
+@@ -99,6 +99,7 @@ static inline int soc_is_ar934x(void)
+ }
+
+ extern void __iomem *ath79_ddr_base;
++extern void __iomem *ath79_gpio_base;
+ extern void __iomem *ath79_pll_base;
+ extern void __iomem *ath79_reset_base;
+
--- /dev/null
+--- a/arch/mips/ath79/common.c
++++ b/arch/mips/ath79/common.c
+@@ -22,6 +22,7 @@
+ #include "common.h"
+
+ static DEFINE_SPINLOCK(ath79_device_reset_lock);
++static DEFINE_MUTEX(ath79_flash_mutex);
+
+ u32 ath79_cpu_freq;
+ EXPORT_SYMBOL_GPL(ath79_cpu_freq);
+@@ -107,3 +108,16 @@ void ath79_device_reset_clear(u32 mask)
+ spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
+ }
+ EXPORT_SYMBOL_GPL(ath79_device_reset_clear);
++
++void ath79_flash_acquire(void)
++{
++ mutex_lock(&ath79_flash_mutex);
++}
++EXPORT_SYMBOL_GPL(ath79_flash_acquire);
++
++void ath79_flash_release(void)
++{
++ mutex_unlock(&ath79_flash_mutex);
++}
++EXPORT_SYMBOL_GPL(ath79_flash_release);
++
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
++++ b/arch/mips/include/asm/mach-ath79/ath79.h
+@@ -126,4 +126,7 @@ static inline u32 ath79_reset_rr(unsigne
+ void ath79_device_reset_set(u32 mask);
+ void ath79_device_reset_clear(u32 mask);
+
++void ath79_flash_acquire(void);
++void ath79_flash_release(void);
++
+ #endif /* __ASM_MACH_ATH79_H */
--- /dev/null
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
++++ b/arch/mips/include/asm/mach-ath79/ath79.h
+@@ -125,6 +125,7 @@ static inline u32 ath79_reset_rr(unsigne
+
+ void ath79_device_reset_set(u32 mask);
+ void ath79_device_reset_clear(u32 mask);
++u32 ath79_device_reset_get(u32 mask);
+
+ void ath79_flash_acquire(void);
+ void ath79_flash_release(void);
+--- a/arch/mips/ath79/common.c
++++ b/arch/mips/ath79/common.c
+@@ -109,6 +109,32 @@ void ath79_device_reset_clear(u32 mask)
+ }
+ EXPORT_SYMBOL_GPL(ath79_device_reset_clear);
+
++u32 ath79_device_reset_get(u32 mask)
++{
++ unsigned long flags;
++ u32 reg;
++ u32 ret;
++
++ if (soc_is_ar71xx())
++ reg = AR71XX_RESET_REG_RESET_MODULE;
++ else if (soc_is_ar724x())
++ reg = AR724X_RESET_REG_RESET_MODULE;
++ else if (soc_is_ar913x())
++ reg = AR913X_RESET_REG_RESET_MODULE;
++ else if (soc_is_ar933x())
++ reg = AR933X_RESET_REG_RESET_MODULE;
++ else if (soc_is_ar934x())
++ reg = AR934X_RESET_REG_RESET_MODULE;
++ else
++ BUG();
++
++ spin_lock_irqsave(&ath79_device_reset_lock, flags);
++ ret = ath79_reset_rr(reg);
++ spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
++ return ret;
++}
++EXPORT_SYMBOL_GPL(ath79_device_reset_get);
++
+ void ath79_flash_acquire(void)
+ {
+ mutex_lock(&ath79_flash_mutex);
--- /dev/null
+--- a/arch/mips/ath79/common.h
++++ b/arch/mips/ath79/common.h
+@@ -26,6 +26,7 @@ void ath79_ddr_wb_flush(unsigned int reg
+ void ath79_gpio_function_enable(u32 mask);
+ void ath79_gpio_function_disable(u32 mask);
+ void ath79_gpio_function_setup(u32 set, u32 clear);
++void ath79_gpio_output_select(unsigned gpio, u8 val);
+ void ath79_gpio_init(void);
+
+ #endif /* __ATH79_COMMON_H */
+--- a/arch/mips/ath79/gpio.c
++++ b/arch/mips/ath79/gpio.c
+@@ -184,6 +184,34 @@ void ath79_gpio_function_setup(u32 set,
+ spin_unlock_irqrestore(&ath79_gpio_lock, flags);
+ }
+
++void __init ath79_gpio_output_select(unsigned gpio, u8 val)
++{
++ void __iomem *base = ath79_gpio_base;
++ unsigned long flags;
++ unsigned int reg;
++ u32 t, s;
++
++ BUG_ON(!soc_is_ar934x());
++
++ if (gpio >= AR934X_GPIO_COUNT)
++ return;
++
++ reg = AR934X_GPIO_REG_OUT_FUNC0 + 4 * (gpio / 4);
++ s = 8 * (gpio % 4);
++
++ spin_lock_irqsave(&ath79_gpio_lock, flags);
++
++ t = __raw_readl(base + reg);
++ t &= ~(0xff << s);
++ t |= val << s;
++ __raw_writel(t, base + reg);
++
++ /* flush write */
++ (void) __raw_readl(base + reg);
++
++ spin_unlock_irqrestore(&ath79_gpio_lock, flags);
++}
++
+ void __init ath79_gpio_init(void)
+ {
+ int err;
--- /dev/null
+--- a/arch/mips/ath79/prom.c
++++ b/arch/mips/ath79/prom.c
+@@ -19,6 +19,8 @@
+
+ #include "common.h"
+
++static char ath79_cmdline_buf[COMMAND_LINE_SIZE] __initdata;
++
+ static inline int is_valid_ram_addr(void *addr)
+ {
+ if (((u32) addr > KSEG0) &&
+@@ -32,6 +34,41 @@ static inline int is_valid_ram_addr(void
+ return 0;
+ }
+
++static void __init ath79_prom_append_cmdline(const char *name,
++ const char *value)
++{
++ snprintf(ath79_cmdline_buf, sizeof(ath79_cmdline_buf),
++ " %s=%s", name, value);
++ strlcat(arcs_cmdline, ath79_cmdline_buf, sizeof(arcs_cmdline));
++}
++
++static const char * __init ath79_prom_find_env(char **envp, const char *name)
++{
++ const char *ret = NULL;
++ int len;
++ char **p;
++
++ if (!is_valid_ram_addr(envp))
++ return NULL;
++
++ len = strlen(name);
++ for (p = envp; is_valid_ram_addr(*p); p++) {
++ if (strncmp(name, *p, len) == 0 && (*p)[len] == '=') {
++ ret = *p + len + 1;
++ break;
++ }
++
++ /* RedBoot env comes in pointer pairs - key, value */
++ if (strncmp(name, *p, len) == 0 && (*p)[len] == 0)
++ if (is_valid_ram_addr(*(++p))) {
++ ret = *p;
++ break;
++ }
++ }
++
++ return ret;
++}
++
+ static __init void ath79_prom_init_cmdline(int argc, char **argv)
+ {
+ int i;
+@@ -48,7 +85,32 @@ static __init void ath79_prom_init_cmdli
+
+ void __init prom_init(void)
+ {
++ const char *env;
++ char **envp;
++
+ ath79_prom_init_cmdline(fw_arg0, (char **)fw_arg1);
++
++ envp = (char **)fw_arg2;
++ if (!strstr(arcs_cmdline, "ethaddr=")) {
++ env = ath79_prom_find_env(envp, "ethaddr");
++ if (env)
++ ath79_prom_append_cmdline("ethaddr", env);
++ }
++
++ if (!strstr(arcs_cmdline, "board=")) {
++ env = ath79_prom_find_env(envp, "board");
++ if (env) {
++ /* Workaround for buggy bootloaders */
++ if (strcmp(env, "RouterStation") == 0 ||
++ strcmp(env, "Ubiquiti AR71xx-based board") == 0)
++ env = "UBNT-RS";
++
++ if (strcmp(env, "RouterStation PRO") == 0)
++ env = "UBNT-RSPRO";
++
++ ath79_prom_append_cmdline("board", env);
++ }
++ }
+ }
+
+ void __init prom_free_prom_memory(void)
--- /dev/null
+--- a/arch/mips/ath79/prom.c
++++ b/arch/mips/ath79/prom.c
+@@ -16,6 +16,7 @@
+
+ #include <asm/bootinfo.h>
+ #include <asm/addrspace.h>
++#include <asm/fw/myloader/myloader.h>
+
+ #include "common.h"
+
+@@ -69,6 +70,34 @@ static const char * __init ath79_prom_fi
+ return ret;
+ }
+
++static int __init ath79_prom_init_myloader(void)
++{
++ struct myloader_info *mylo;
++ char mac_buf[32];
++ unsigned char *mac;
++
++ mylo = myloader_get_info();
++ if (!mylo)
++ return 0;
++
++ switch (mylo->did) {
++ case DEVID_COMPEX_WP543:
++ ath79_prom_append_cmdline("board", "WP543");
++ break;
++ default:
++ pr_warn("prom: unknown device id: %x\n", mylo->did);
++ return 0;
++ }
++
++ mac = mylo->macs[0];
++ snprintf(mac_buf, sizeof(mac_buf), "%02x:%02x:%02x:%02x:%02x:%02x",
++ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
++
++ ath79_prom_append_cmdline("ethaddr", mac_buf);
++
++ return 1;
++}
++
+ static __init void ath79_prom_init_cmdline(int argc, char **argv)
+ {
+ int i;
+@@ -88,6 +117,9 @@ void __init prom_init(void)
+ const char *env;
+ char **envp;
+
++ if (ath79_prom_init_myloader())
++ return;
++
+ ath79_prom_init_cmdline(fw_arg0, (char **)fw_arg1);
+
+ envp = (char **)fw_arg2;
--- /dev/null
+--- a/arch/mips/ath79/prom.c
++++ b/arch/mips/ath79/prom.c
+@@ -70,6 +70,35 @@ static const char * __init ath79_prom_fi
+ return ret;
+ }
+
++#ifdef CONFIG_IMAGE_CMDLINE_HACK
++extern char __image_cmdline[];
++
++static int __init ath79_use_image_cmdline(void)
++{
++ char *p = __image_cmdline;
++ int replace = 0;
++
++ if (*p == '-') {
++ replace = 1;
++ p++;
++ }
++
++ if (*p == '\0')
++ return 0;
++
++ if (replace) {
++ strlcpy(arcs_cmdline, p, sizeof(arcs_cmdline));
++ } else {
++ strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
++ strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
++ }
++
++ return 1;
++}
++#else
++static inline int ath79_use_image_cmdline(void) { return 0; }
++#endif
++
+ static int __init ath79_prom_init_myloader(void)
+ {
+ struct myloader_info *mylo;
+@@ -95,6 +124,8 @@ static int __init ath79_prom_init_myload
+
+ ath79_prom_append_cmdline("ethaddr", mac_buf);
+
++ ath79_use_image_cmdline();
++
+ return 1;
+ }
+
+@@ -102,6 +133,9 @@ static __init void ath79_prom_init_cmdli
+ {
+ int i;
+
++ if (ath79_use_image_cmdline())
++ return;
++
+ if (!is_valid_ram_addr(argv))
+ return;
+
--- /dev/null
+--- a/arch/mips/ath79/setup.c
++++ b/arch/mips/ath79/setup.c
+@@ -215,6 +215,8 @@ void __init plat_time_init(void)
+ mips_hpt_frequency = clk_get_rate(clk) / 2;
+ }
+
++__setup("board=", mips_machtype_setup);
++
+ static int __init ath79_setup(void)
+ {
+ ath79_gpio_init();
--- /dev/null
+--- a/arch/mips/ath79/dev-wmac.c
++++ b/arch/mips/ath79/dev-wmac.c
+@@ -24,7 +24,10 @@
+ #include "dev-wmac.h"
+
+ static u8 ath79_wmac_mac[ETH_ALEN];
+-static struct ath9k_platform_data ath79_wmac_data;
++
++static struct ath9k_platform_data ath79_wmac_data = {
++ .led_pin = -1,
++};
+
+ static struct resource ath79_wmac_resources[] = {
+ {
--- /dev/null
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -20,7 +20,13 @@
+ #include <linux/io.h>
+ #include <linux/bitops.h>
+
++#define AR71XX_PCI_MEM_BASE 0x10000000
++#define AR71XX_PCI_MEM_SIZE 0x08000000
+ #define AR71XX_APB_BASE 0x18000000
++#define AR71XX_GE0_BASE 0x19000000
++#define AR71XX_GE0_SIZE 0x10000
++#define AR71XX_GE1_BASE 0x1a000000
++#define AR71XX_GE1_SIZE 0x10000
+ #define AR71XX_EHCI_BASE 0x1b000000
+ #define AR71XX_EHCI_SIZE 0x1000
+ #define AR71XX_OHCI_BASE 0x1c000000
+@@ -40,6 +46,8 @@
+ #define AR71XX_PLL_SIZE 0x100
+ #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
+ #define AR71XX_RESET_SIZE 0x100
++#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
++#define AR71XX_MII_SIZE 0x100
+
+ #define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
+ #define AR7240_USB_CTRL_SIZE 0x100
+@@ -56,11 +64,15 @@
+
+ #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
+ #define AR933X_UART_SIZE 0x14
++#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
++#define AR933X_GMAC_SIZE 0x04
+ #define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
+ #define AR933X_WMAC_SIZE 0x20000
+ #define AR933X_EHCI_BASE 0x1b000000
+ #define AR933X_EHCI_SIZE 0x1000
+
++#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
++#define AR934X_GMAC_SIZE 0x14
+ #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
+ #define AR934X_WMAC_SIZE 0x20000
+ #define AR934X_EHCI_BASE 0x1b000000
+@@ -120,6 +132,9 @@
+ #define AR71XX_AHB_DIV_SHIFT 20
+ #define AR71XX_AHB_DIV_MASK 0x7
+
++#define AR71XX_ETH0_PLL_SHIFT 17
++#define AR71XX_ETH1_PLL_SHIFT 19
++
+ #define AR724X_PLL_REG_CPU_CONFIG 0x00
+ #define AR724X_PLL_REG_PCIE_CONFIG 0x18
+
+@@ -132,6 +147,8 @@
+ #define AR724X_DDR_DIV_SHIFT 22
+ #define AR724X_DDR_DIV_MASK 0x3
+
++#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c
++
+ #define AR913X_PLL_REG_CPU_CONFIG 0x00
+ #define AR913X_PLL_REG_ETH_CONFIG 0x04
+ #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
+@@ -144,6 +161,9 @@
+ #define AR913X_AHB_DIV_SHIFT 19
+ #define AR913X_AHB_DIV_MASK 0x1
+
++#define AR913X_ETH0_PLL_SHIFT 20
++#define AR913X_ETH1_PLL_SHIFT 22
++
+ #define AR933X_PLL_CPU_CONFIG_REG 0x00
+ #define AR933X_PLL_CLOCK_CTRL_REG 0x08
+
+@@ -285,7 +305,11 @@
+ #define AR913X_RESET_USB_HOST BIT(5)
+ #define AR913X_RESET_USB_PHY BIT(4)
+
++#define AR933X_RESET_GE1_MDIO BIT(23)
++#define AR933X_RESET_GE0_MDIO BIT(22)
++#define AR933X_RESET_GE1_MAC BIT(13)
+ #define AR933X_RESET_WMAC BIT(11)
++#define AR933X_RESET_GE0_MAC BIT(9)
+ #define AR933X_RESET_USB_HOST BIT(5)
+ #define AR933X_RESET_USB_PHY BIT(4)
+ #define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
+@@ -323,6 +347,8 @@
+ #define AR934X_RESET_MBOX BIT(1)
+ #define AR934X_RESET_I2S BIT(0)
+
++#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
++#define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
+ #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
+
+ #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
+@@ -427,6 +453,14 @@
+ #define AR71XX_GPIO_REG_INT_ENABLE 0x24
+ #define AR71XX_GPIO_REG_FUNC 0x28
+
++#define AR934X_GPIO_REG_OUT_FUNC0 0x2c
++#define AR934X_GPIO_REG_OUT_FUNC1 0x30
++#define AR934X_GPIO_REG_OUT_FUNC2 0x34
++#define AR934X_GPIO_REG_OUT_FUNC3 0x38
++#define AR934X_GPIO_REG_OUT_FUNC4 0x3c
++#define AR934X_GPIO_REG_OUT_FUNC5 0x40
++#define AR934X_GPIO_REG_FUNC 0x6c
++
+ #define AR71XX_GPIO_COUNT 16
+ #define AR7240_GPIO_COUNT 18
+ #define AR7241_GPIO_COUNT 20
+@@ -434,4 +468,124 @@
+ #define AR933X_GPIO_COUNT 30
+ #define AR934X_GPIO_COUNT 23
+
++#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
++#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
++#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
++#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12)
++#define AR71XX_GPIO_FUNC_UART_EN BIT(8)
++#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4)
++#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
++
++#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19)
++#define AR724X_GPIO_FUNC_SPI_EN BIT(18)
++#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
++#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
++#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12)
++#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11)
++#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10)
++#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9)
++#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8)
++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
++#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
++#define AR724X_GPIO_FUNC_UART_EN BIT(1)
++#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
++
++#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22)
++#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
++#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20)
++#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19)
++#define AR913X_GPIO_FUNC_I2S1_EN BIT(18)
++#define AR913X_GPIO_FUNC_I2S0_EN BIT(17)
++#define AR913X_GPIO_FUNC_SLIC_EN BIT(16)
++#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
++#define AR913X_GPIO_FUNC_UART_EN BIT(8)
++#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4)
++
++#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31)
++#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30)
++#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29)
++#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27)
++#define AR933X_GPIO_FUNC_I2SO_EN BIT(26)
++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25)
++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24)
++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23)
++#define AR933X_GPIO_FUNC_SPI_EN BIT(18)
++#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
++#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
++#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
++#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
++#define AR933X_GPIO_FUNC_UART_EN BIT(1)
++#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0)
++
++#define AR934X_GPIO_FUNC_DDR_DQOE_EN BIT(17)
++#define AR934X_GPIO_FUNC_SPI_CS_1_EN BIT(14)
++#define AR934X_GPIO_FUNC_SPI_CS_0_EN BIT(13)
++
++#define AR934X_GPIO_OUT_GPIO 0x00
++
++/*
++ * MII_CTRL block
++ */
++#define AR71XX_MII_REG_MII0_CTRL 0x00
++#define AR71XX_MII_REG_MII1_CTRL 0x04
++
++#define AR71XX_MII_CTRL_IF_MASK 3
++#define AR71XX_MII_CTRL_SPEED_SHIFT 4
++#define AR71XX_MII_CTRL_SPEED_MASK 3
++#define AR71XX_MII_CTRL_SPEED_10 0
++#define AR71XX_MII_CTRL_SPEED_100 1
++#define AR71XX_MII_CTRL_SPEED_1000 2
++
++#define AR71XX_MII0_CTRL_IF_GMII 0
++#define AR71XX_MII0_CTRL_IF_MII 1
++#define AR71XX_MII0_CTRL_IF_RGMII 2
++#define AR71XX_MII0_CTRL_IF_RMII 3
++
++#define AR71XX_MII1_CTRL_IF_RGMII 0
++#define AR71XX_MII1_CTRL_IF_RMII 1
++
++/*
++ * AR933X GMAC interface
++ */
++#define AR933X_GMAC_REG_ETH_CFG 0x00
++
++#define AR933X_ETH_CFG_RGMII_GE0 BIT(0)
++#define AR933X_ETH_CFG_MII_GE0 BIT(1)
++#define AR933X_ETH_CFG_GMII_GE0 BIT(2)
++#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3)
++#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4)
++#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5)
++#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7)
++#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
++#define AR933X_ETH_CFG_RMII_GE0 BIT(9)
++#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0
++#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10)
++
++/*
++ * AR934X GMAC Interface
++ */
++#define AR934X_GMAC_REG_ETH_CFG 0x00
++
++#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0)
++#define AR934X_ETH_CFG_MII_GMAC0 BIT(1)
++#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2)
++#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3)
++#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4)
++#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5)
++#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6)
++#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7)
++#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9)
++#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10)
++#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11)
++#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
++#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
++
+ #endif /* __ASM_MACH_AR71XX_REGS_H */
--- /dev/null
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -88,6 +88,20 @@ config SOC_AR934X
+ select PCI_AR724X if PCI
+ def_bool n
+
++config ATH79_DEV_M25P80
++ select ATH79_DEV_SPI
++ def_bool n
++
++config ATH79_DEV_AP9X_PCI
++ select ATH79_PCI_ATH9K_FIXUP
++ def_bool n
++
++config ATH79_DEV_DSA
++ def_bool n
++
++config ATH79_DEV_ETH
++ def_bool n
++
+ config PCI_AR724X
+ def_bool n
+
+@@ -107,4 +121,10 @@ config ATH79_DEV_WMAC
+ depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X)
+ def_bool n
+
++config ATH79_NVRAM
++ def_bool n
++
++config ATH79_PCI_ATH9K_FIXUP
++ def_bool n
++
+ endif
+--- a/arch/mips/ath79/Makefile
++++ b/arch/mips/ath79/Makefile
+@@ -17,13 +17,23 @@ obj-$(CONFIG_PCI) += pci.o
+ # Devices
+ #
+ obj-y += dev-common.o
++obj-$(CONFIG_ATH79_DEV_AP9X_PCI) += dev-ap9x-pci.o
++obj-$(CONFIG_ATH79_DEV_DSA) += dev-dsa.o
++obj-$(CONFIG_ATH79_DEV_ETH) += dev-eth.o
+ obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o
+ obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o
++obj-$(CONFIG_ATH79_DEV_M25P80) += dev-m25p80.o
+ obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o
+ obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o
+ obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wmac.o
+
+ #
++# Miscellaneous objects
++#
++obj-$(CONFIG_ATH79_NVRAM) += nvram.o
++obj-$(CONFIG_ATH79_PCI_ATH9K_FIXUP) += pci-ath9k-fixup.o
++
++#
+ # Machines
+ #
+ obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o
--- /dev/null
+--- a/arch/mips/ath79/mach-ap121.c
++++ b/arch/mips/ath79/mach-ap121.c
+@@ -1,19 +1,23 @@
+ /*
+ * Atheros AP121 board support
+ *
+- * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/partitions.h>
+
+-#include "machtypes.h"
++#include "dev-eth.h"
+ #include "dev-gpio-buttons.h"
+ #include "dev-leds-gpio.h"
++#include "dev-m25p80.h"
+ #include "dev-spi.h"
+ #include "dev-usb.h"
+ #include "dev-wmac.h"
++#include "machtypes.h"
+
+ #define AP121_GPIO_LED_WLAN 0
+ #define AP121_GPIO_LED_USB 1
+@@ -24,7 +28,82 @@
+ #define AP121_KEYS_POLL_INTERVAL 20 /* msecs */
+ #define AP121_KEYS_DEBOUNCE_INTERVAL (3 * AP121_KEYS_POLL_INTERVAL)
+
+-#define AP121_CAL_DATA_ADDR 0x1fff1000
++#define AP121_MAC0_OFFSET 0x0000
++#define AP121_MAC1_OFFSET 0x0006
++#define AP121_CALDATA_OFFSET 0x1000
++#define AP121_WMAC_MAC_OFFSET 0x1002
++
++#define AP121_MINI_GPIO_LED_WLAN 0
++#define AP121_MINI_GPIO_BTN_JUMPSTART 12
++#define AP121_MINI_GPIO_BTN_RESET 11
++
++static struct mtd_partition ap121_parts[] = {
++ {
++ .name = "u-boot",
++ .offset = 0,
++ .size = 0x010000,
++ .mask_flags = MTD_WRITEABLE,
++ },
++ {
++ .name = "rootfs",
++ .offset = 0x010000,
++ .size = 0x130000,
++ },
++ {
++ .name = "uImage",
++ .offset = 0x140000,
++ .size = 0x0a0000,
++ },
++ {
++ .name = "NVRAM",
++ .offset = 0x1e0000,
++ .size = 0x010000,
++ },
++ {
++ .name = "ART",
++ .offset = 0x1f0000,
++ .size = 0x010000,
++ .mask_flags = MTD_WRITEABLE,
++ },
++};
++
++static struct mtd_partition ap121_mini_parts[] = {
++ {
++ .name = "u-boot",
++ .offset = 0,
++ .size = 0x040000,
++ .mask_flags = MTD_WRITEABLE,
++ },
++ {
++ .name = "u-boot-env",
++ .offset = 0x040000,
++ .size = 0x010000,
++ .mask_flags = MTD_WRITEABLE,
++ },
++ {
++ .name = "rootfs",
++ .offset = 0x050000,
++ .size = 0x2b0000,
++ },
++ {
++ .name = "uImage",
++ .offset = 0x300000,
++ .size = 0x0e0000,
++ },
++ {
++ .name = "NVRAM",
++ .offset = 0x3e0000,
++ .size = 0x010000,
++ },
++ {
++ .name = "ART",
++ .offset = 0x3f0000,
++ .size = 0x010000,
++ .mask_flags = MTD_WRITEABLE,
++ },
++};
++
++static struct flash_platform_data ap121_flash_data;
+
+ static struct gpio_led ap121_leds_gpio[] __initdata = {
+ {
+@@ -58,41 +137,84 @@ static struct gpio_keys_button ap121_gpi
+ }
+ };
+
+-static struct ath79_spi_controller_data ap121_spi0_data = {
+- .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
+- .cs_line = 0,
++static struct gpio_led ap121_mini_leds_gpio[] __initdata = {
++ {
++ .name = "ap121:green:wlan",
++ .gpio = AP121_MINI_GPIO_LED_WLAN,
++ .active_low = 0,
++ },
+ };
+
+-static struct spi_board_info ap121_spi_info[] = {
+- {
+- .bus_num = 0,
+- .chip_select = 0,
+- .max_speed_hz = 25000000,
+- .modalias = "mx25l1606e",
+- .controller_data = &ap121_spi0_data,
++static struct gpio_keys_button ap121_mini_gpio_keys[] __initdata = {
++ {
++ .desc = "jumpstart button",
++ .type = EV_KEY,
++ .code = KEY_WPS_BUTTON,
++ .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
++ .gpio = AP121_MINI_GPIO_BTN_JUMPSTART,
++ .active_low = 1,
++ },
++ {
++ .desc = "reset button",
++ .type = EV_KEY,
++ .code = KEY_RESTART,
++ .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
++ .gpio = AP121_MINI_GPIO_BTN_RESET,
++ .active_low = 1,
+ }
+ };
+
+-static struct ath79_spi_platform_data ap121_spi_data = {
+- .bus_num = 0,
+- .num_chipselect = 1,
+-};
++static void __init ap121_common_setup(void)
++{
++ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
++
++ ath79_register_m25p80(&ap121_flash_data);
++ ath79_register_wmac(art + AP121_CALDATA_OFFSET,
++ art + AP121_WMAC_MAC_OFFSET);
++
++ ath79_init_mac(ath79_eth0_data.mac_addr, art + AP121_MAC0_OFFSET, 0);
++ ath79_init_mac(ath79_eth1_data.mac_addr, art + AP121_MAC1_OFFSET, 0);
++
++ ath79_register_mdio(0, 0x0);
++
++ /* LAN ports */
++ ath79_register_eth(1);
++
++ /* WAN port */
++ ath79_register_eth(0);
++}
+
+ static void __init ap121_setup(void)
+ {
+- u8 *cal_data = (u8 *) KSEG1ADDR(AP121_CAL_DATA_ADDR);
++ ap121_flash_data.parts = ap121_parts;
++ ap121_flash_data.nr_parts = ARRAY_SIZE(ap121_parts);
++
++ ap121_common_setup();
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_leds_gpio),
+ ap121_leds_gpio);
+ ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(ap121_gpio_keys),
+ ap121_gpio_keys);
+-
+- ath79_register_spi(&ap121_spi_data, ap121_spi_info,
+- ARRAY_SIZE(ap121_spi_info));
+ ath79_register_usb();
+- ath79_register_wmac(cal_data, NULL);
+ }
+
+ MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board",
+ ap121_setup);
++
++static void __init ap121_mini_setup(void)
++{
++ ap121_flash_data.parts = ap121_mini_parts;
++ ap121_flash_data.nr_parts = ARRAY_SIZE(ap121_mini_parts);
++
++ ap121_common_setup();
++
++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_mini_leds_gpio),
++ ap121_mini_leds_gpio);
++ ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL,
++ ARRAY_SIZE(ap121_mini_gpio_keys),
++ ap121_mini_gpio_keys);
++}
++
++MIPS_MACHINE(ATH79_MACH_AP121_MINI, "AP121-MINI", "Atheros AP121-MINI",
++ ap121_mini_setup);
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -5,9 +5,10 @@ menu "Atheros AR71XX/AR724X/AR913X machi
+ config ATH79_MACH_AP121
+ bool "Atheros AP121 reference board"
+ select SOC_AR933X
++ select ATH79_DEV_ETH
+ select ATH79_DEV_GPIO_BUTTONS
+ select ATH79_DEV_LEDS_GPIO
+- select ATH79_DEV_SPI
++ select ATH79_DEV_M25P80
+ select ATH79_DEV_USB
+ select ATH79_DEV_WMAC
+ help
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -17,6 +17,7 @@
+ enum ath79_mach_type {
+ ATH79_MACH_GENERIC = 0,
+ ATH79_MACH_AP121, /* Atheros AP121 reference board */
++ ATH79_MACH_AP121_MINI, /* Atheros AP121-MINI reference board */
+ ATH79_MACH_AP81, /* Atheros AP81 reference board */
+ ATH79_MACH_DB120, /* Atheros DB120 reference board */
+ ATH79_MACH_PB44, /* Atheros PB44 reference board */
--- /dev/null
+--- a/arch/mips/ath79/mach-ap81.c
++++ b/arch/mips/ath79/mach-ap81.c
+@@ -9,12 +9,16 @@
+ * by the Free Software Foundation.
+ */
+
+-#include "machtypes.h"
+-#include "dev-wmac.h"
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/partitions.h>
++
++#include "dev-eth.h"
+ #include "dev-gpio-buttons.h"
+ #include "dev-leds-gpio.h"
+-#include "dev-spi.h"
++#include "dev-m25p80.h"
+ #include "dev-usb.h"
++#include "dev-wmac.h"
++#include "machtypes.h"
+
+ #define AP81_GPIO_LED_STATUS 1
+ #define AP81_GPIO_LED_AOSS 3
+@@ -29,6 +33,37 @@
+
+ #define AP81_CAL_DATA_ADDR 0x1fff1000
+
++static struct mtd_partition ap81_partitions[] = {
++ {
++ .name = "u-boot",
++ .offset = 0,
++ .size = 0x040000,
++ .mask_flags = MTD_WRITEABLE,
++ }, {
++ .name = "u-boot-env",
++ .offset = 0x040000,
++ .size = 0x010000,
++ }, {
++ .name = "rootfs",
++ .offset = 0x050000,
++ .size = 0x500000,
++ }, {
++ .name = "uImage",
++ .offset = 0x550000,
++ .size = 0x100000,
++ }, {
++ .name = "ART",
++ .offset = 0x650000,
++ .size = 0x1b0000,
++ .mask_flags = MTD_WRITEABLE,
++ }
++};
++
++static struct flash_platform_data ap81_flash_data = {
++ .parts = ap81_partitions,
++ .nr_parts = ARRAY_SIZE(ap81_partitions),
++};
++
+ static struct gpio_led ap81_leds_gpio[] __initdata = {
+ {
+ .name = "ap81:green:status",
+@@ -67,26 +102,6 @@ static struct gpio_keys_button ap81_gpio
+ }
+ };
+
+-static struct ath79_spi_controller_data ap81_spi0_data = {
+- .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
+- .cs_line = 0,
+-};
+-
+-static struct spi_board_info ap81_spi_info[] = {
+- {
+- .bus_num = 0,
+- .chip_select = 0,
+- .max_speed_hz = 25000000,
+- .modalias = "m25p64",
+- .controller_data = &ap81_spi0_data,
+- }
+-};
+-
+-static struct ath79_spi_platform_data ap81_spi_data = {
+- .bus_num = 0,
+- .num_chipselect = 1,
+-};
+-
+ static void __init ap81_setup(void)
+ {
+ u8 *cal_data = (u8 *) KSEG1ADDR(AP81_CAL_DATA_ADDR);
+@@ -96,10 +111,24 @@ static void __init ap81_setup(void)
+ ath79_register_gpio_keys_polled(-1, AP81_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(ap81_gpio_keys),
+ ap81_gpio_keys);
+- ath79_register_spi(&ap81_spi_data, ap81_spi_info,
+- ARRAY_SIZE(ap81_spi_info));
++ ath79_register_m25p80(&ap81_flash_data);
+ ath79_register_wmac(cal_data, NULL);
+ ath79_register_usb();
++
++ ath79_register_mdio(0, 0x0);
++
++ ath79_init_mac(ath79_eth0_data.mac_addr, cal_data, 0);
++ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
++ ath79_eth0_data.speed = SPEED_100;
++ ath79_eth0_data.duplex = DUPLEX_FULL;
++ ath79_eth0_data.has_ar8216 = 1;
++
++ ath79_init_mac(ath79_eth1_data.mac_addr, cal_data, 1);
++ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
++ ath79_eth1_data.phy_mask = 0x10;
++
++ ath79_register_eth(0);
++ ath79_register_eth(1);
+ }
+
+ MIPS_MACHINE(ATH79_MACH_AP81, "AP81", "Atheros AP81 reference board",
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -18,9 +18,10 @@ config ATH79_MACH_AP121
+ config ATH79_MACH_AP81
+ bool "Atheros AP81 reference board"
+ select SOC_AR913X
++ select ATH79_DEV_ETH
+ select ATH79_DEV_GPIO_BUTTONS
+ select ATH79_DEV_LEDS_GPIO
+- select ATH79_DEV_SPI
++ select ATH79_DEV_M25P80
+ select ATH79_DEV_USB
+ select ATH79_DEV_WMAC
+ help
--- /dev/null
+--- a/arch/mips/ath79/mach-db120.c
++++ b/arch/mips/ath79/mach-db120.c
+@@ -37,17 +37,26 @@
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/partitions.h>
+ #include <linux/pci.h>
++#include <linux/platform_device.h>
+ #include <linux/ath9k_platform.h>
+
+-#include "machtypes.h"
++#include <asm/mach-ath79/ar71xx_regs.h>
++
++#include "common.h"
++#include "dev-ap9x-pci.h"
++#include "dev-eth.h"
+ #include "dev-gpio-buttons.h"
+ #include "dev-leds-gpio.h"
++#include "dev-m25p80.h"
+ #include "dev-spi.h"
+ #include "dev-usb.h"
+ #include "dev-wmac.h"
+-#include "pci.h"
++#include "machtypes.h"
+
++#define DB120_GPIO_LED_USB 11
+ #define DB120_GPIO_LED_WLAN_5G 12
+ #define DB120_GPIO_LED_WLAN_2G 13
+ #define DB120_GPIO_LED_STATUS 14
+@@ -58,8 +67,50 @@
+ #define DB120_KEYS_POLL_INTERVAL 20 /* msecs */
+ #define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL)
+
+-#define DB120_WMAC_CALDATA_OFFSET 0x1000
+-#define DB120_PCIE_CALDATA_OFFSET 0x5000
++#define DB120_MAC0_OFFSET 0
++#define DB120_MAC1_OFFSET 6
++#define DB120_WMAC_CALDATA_OFFSET 0x1000
++#define DB120_PCIE_CALDATA_OFFSET 0x5000
++
++static struct mtd_partition db120_partitions[] = {
++ {
++ .name = "u-boot",
++ .offset = 0,
++ .size = 0x040000,
++ .mask_flags = MTD_WRITEABLE,
++ },
++ {
++ .name = "u-boot-env",
++ .offset = 0x040000,
++ .size = 0x010000,
++ },
++ {
++ .name = "rootfs",
++ .offset = 0x050000,
++ .size = 0x630000,
++ },
++ {
++ .name = "uImage",
++ .offset = 0x680000,
++ .size = 0x160000,
++ },
++ {
++ .name = "NVRAM",
++ .offset = 0x7E0000,
++ .size = 0x010000,
++ },
++ {
++ .name = "ART",
++ .offset = 0x7F0000,
++ .size = 0x010000,
++ .mask_flags = MTD_WRITEABLE,
++ }
++};
++
++static struct flash_platform_data db120_flash_data = {
++ .parts = db120_partitions,
++ .nr_parts = ARRAY_SIZE(db120_partitions),
++};
+
+ static struct gpio_led db120_leds_gpio[] __initdata = {
+ {
+@@ -82,6 +133,11 @@ static struct gpio_led db120_leds_gpio[]
+ .gpio = DB120_GPIO_LED_WLAN_2G,
+ .active_low = 1,
+ },
++ {
++ .name = "db120:green:usb",
++ .gpio = DB120_GPIO_LED_USB,
++ .active_low = 1,
++ }
+ };
+
+ static struct gpio_keys_button db120_gpio_keys[] __initdata = {
+@@ -95,66 +151,65 @@ static struct gpio_keys_button db120_gpi
+ },
+ };
+
+-static struct ath79_spi_controller_data db120_spi0_data = {
+- .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
+- .cs_line = 0,
+-};
+-
+-static struct spi_board_info db120_spi_info[] = {
+- {
+- .bus_num = 0,
+- .chip_select = 0,
+- .max_speed_hz = 25000000,
+- .modalias = "s25sl064a",
+- .controller_data = &db120_spi0_data,
+- }
+-};
+-
+-static struct ath79_spi_platform_data db120_spi_data = {
+- .bus_num = 0,
+- .num_chipselect = 1,
+-};
+-
+-#ifdef CONFIG_PCI
+-static struct ath9k_platform_data db120_ath9k_data;
+-
+-static int db120_pci_plat_dev_init(struct pci_dev *dev)
++static void __init db120_gmac_setup(void)
+ {
+- switch (PCI_SLOT(dev->devfn)) {
+- case 0:
+- dev->dev.platform_data = &db120_ath9k_data;
+- break;
+- }
++ void __iomem *base;
++ u32 t;
+
+- return 0;
+-}
++ base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
+
+-static void __init db120_pci_init(u8 *eeprom)
+-{
+- memcpy(db120_ath9k_data.eeprom_data, eeprom,
+- sizeof(db120_ath9k_data.eeprom_data));
++ t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
++ t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
++ AR934X_ETH_CFG_MII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE);
++ __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
+
+- ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init);
+- ath79_register_pci();
++ iounmap(base);
+ }
+-#else
+-static inline void db120_pci_init(void) {}
+-#endif /* CONFIG_PCI */
+
+ static void __init db120_setup(void)
+ {
+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
+
++ ath79_gpio_output_select(DB120_GPIO_LED_USB, AR934X_GPIO_OUT_GPIO);
++ ath79_register_m25p80(&db120_flash_data);
++
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio),
+ db120_leds_gpio);
+ ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(db120_gpio_keys),
+ db120_gpio_keys);
+- ath79_register_spi(&db120_spi_data, db120_spi_info,
+- ARRAY_SIZE(db120_spi_info));
+ ath79_register_usb();
+ ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL);
+- db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
++ ap91_pci_init(art + DB120_PCIE_CALDATA_OFFSET, NULL);
++
++ db120_gmac_setup();
++
++ ath79_register_mdio(0, 0x0);
++ ath79_register_mdio(1, 0x0);
++
++ ath79_init_mac(ath79_eth0_data.mac_addr, art + DB120_MAC0_OFFSET, 0);
++#if 0
++ /* GMAC0 is connected to an AR8327 switch */
++ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
++ ath79_eth0_data.speed = SPEED_1000;
++ ath79_eth0_data.duplex = DUPLEX_FULL;
++#else
++ /* GMAC0 is connected to PHY4 of the internal switch */
++ ath79_switch_data.phy4_mii_en = 1;
++
++ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
++ ath79_eth0_data.phy_mask = BIT(4);
++ ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
++#endif
++ ath79_register_eth(0);
++
++ /* GMAC1 is connected to the internal switch */
++ ath79_init_mac(ath79_eth1_data.mac_addr, art + DB120_MAC1_OFFSET, 0);
++ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
++ ath79_eth1_data.speed = SPEED_1000;
++ ath79_eth1_data.duplex = DUPLEX_FULL;
++
++ ath79_register_eth(1);
+ }
+
+ MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board",
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -31,9 +31,11 @@ config ATH79_MACH_AP81
+ config ATH79_MACH_DB120
+ bool "Atheros DB120 reference board"
+ select SOC_AR934X
++ select ATH79_DEV_AP9X_PCI if PCI
++ select ATH79_DEV_ETH
+ select ATH79_DEV_GPIO_BUTTONS
+ select ATH79_DEV_LEDS_GPIO
+- select ATH79_DEV_SPI
++ select ATH79_DEV_M25P80
+ select ATH79_DEV_USB
+ select ATH79_DEV_WMAC
+ help
--- /dev/null
+--- a/arch/mips/ath79/mach-pb44.c
++++ b/arch/mips/ath79/mach-pb44.c
+@@ -8,23 +8,48 @@
+ * by the Free Software Foundation.
+ */
+
++#include <linux/delay.h>
+ #include <linux/init.h>
+ #include <linux/platform_device.h>
+ #include <linux/i2c.h>
+ #include <linux/i2c-gpio.h>
+ #include <linux/i2c/pcf857x.h>
++#include <linux/i2c/pcf857x.h>
++#include <linux/spi/flash.h>
++#include <linux/spi/vsc7385.h>
+
+-#include "machtypes.h"
++#include <asm/mach-ath79/ar71xx_regs.h>
++#include <asm/mach-ath79/ath79.h>
++
++#include "dev-eth.h"
+ #include "dev-gpio-buttons.h"
+ #include "dev-leds-gpio.h"
+ #include "dev-spi.h"
+ #include "dev-usb.h"
++#include "machtypes.h"
+ #include "pci.h"
+
+ #define PB44_GPIO_I2C_SCL 0
+ #define PB44_GPIO_I2C_SDA 1
+
++#define PB44_PCF8757_VSC7395_CS 0
++#define PB44_PCF8757_STEREO_CS 1
++#define PB44_PCF8757_SLIC_CS0 2
++#define PB44_PCF8757_SLIC_TEST 3
++#define PB44_PCF8757_SLIC_INT0 4
++#define PB44_PCF8757_SLIC_INT1 5
++#define PB44_PCF8757_SW_RESET 6
++#define PB44_PCF8757_SW_JUMP 8
++#define PB44_PCF8757_LED_JUMP1 9
++#define PB44_PCF8757_LED_JUMP2 10
++#define PB44_PCF8757_TP24 11
++#define PB44_PCF8757_TP25 12
++#define PB44_PCF8757_TP26 13
++#define PB44_PCF8757_TP27 14
++#define PB44_PCF8757_TP28 15
++
+ #define PB44_GPIO_EXP_BASE 16
++#define PB44_GPIO_VSC7395_CS (PB44_GPIO_EXP_BASE + PB44_PCF8757_VSC7395_CS)
+ #define PB44_GPIO_SW_RESET (PB44_GPIO_EXP_BASE + 6)
+ #define PB44_GPIO_SW_JUMP (PB44_GPIO_EXP_BASE + 8)
+ #define PB44_GPIO_LED_JUMP1 (PB44_GPIO_EXP_BASE + 9)
+@@ -92,21 +117,66 @@ static struct ath79_spi_controller_data
+ .cs_line = 0,
+ };
+
++static struct ath79_spi_controller_data pb44_spi1_data = {
++ .cs_type = ATH79_SPI_CS_TYPE_GPIO,
++ .cs_line = PB44_GPIO_VSC7395_CS,
++};
++
++static void pb44_vsc7395_reset(void)
++{
++ ath79_device_reset_set(AR71XX_RESET_GE1_PHY);
++ udelay(10);
++ ath79_device_reset_clear(AR71XX_RESET_GE1_PHY);
++ mdelay(50);
++}
++
++static struct vsc7385_platform_data pb44_vsc7395_data = {
++ .reset = pb44_vsc7395_reset,
++ .ucode_name = "vsc7395_ucode_pb44.bin",
++ .mac_cfg = {
++ .tx_ipg = 6,
++ .bit2 = 1,
++ .clk_sel = 0,
++ },
++};
++
++static const char *pb44_part_probes[] = {
++ "RedBoot",
++ NULL,
++};
++
++static struct flash_platform_data pb44_flash_data = {
++ .part_probes = pb44_part_probes,
++};
++
+ static struct spi_board_info pb44_spi_info[] = {
+ {
+ .bus_num = 0,
+ .chip_select = 0,
+ .max_speed_hz = 25000000,
+ .modalias = "m25p64",
++ .platform_data = &pb44_flash_data,
+ .controller_data = &pb44_spi0_data,
+ },
++ {
++ .bus_num = 0,
++ .chip_select = 1,
++ .max_speed_hz = 25000000,
++ .modalias = "spi-vsc7385",
++ .platform_data = &pb44_vsc7395_data,
++ .controller_data = &pb44_spi1_data,
++ }
+ };
+
+ static struct ath79_spi_platform_data pb44_spi_data = {
+ .bus_num = 0,
+- .num_chipselect = 1,
++ .num_chipselect = 2,
+ };
+
++#define PB44_WAN_PHYMASK BIT(0)
++#define PB44_LAN_PHYMASK 0
++#define PB44_MDIO_PHYMASK (PB44_LAN_PHYMASK | PB44_WAN_PHYMASK)
++
+ static void __init pb44_init(void)
+ {
+ i2c_register_board_info(0, pb44_i2c_board_info,
+@@ -122,6 +192,22 @@ static void __init pb44_init(void)
+ ARRAY_SIZE(pb44_spi_info));
+ ath79_register_usb();
+ ath79_register_pci();
++
++ ath79_register_mdio(0, ~PB44_MDIO_PHYMASK);
++
++ ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
++ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
++ ath79_eth0_data.phy_mask = PB44_WAN_PHYMASK;
++
++ ath79_register_eth(0);
++
++ ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
++ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
++ ath79_eth1_data.speed = SPEED_1000;
++ ath79_eth1_data.duplex = DUPLEX_FULL;
++ ath79_eth1_pll_data.pll_1000 = 0x110000;
++
++ ath79_register_eth(1);
+ }
+
+ MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board",
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -45,6 +45,7 @@ config ATH79_MACH_DB120
+ config ATH79_MACH_PB44
+ bool "Atheros PB44 reference board"
+ select SOC_AR71XX
++ select ATH79_DEV_ETH
+ select ATH79_DEV_GPIO_BUTTONS
+ select ATH79_DEV_LEDS_GPIO
+ select ATH79_DEV_SPI
--- /dev/null
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -57,9 +57,10 @@ config ATH79_MACH_PB44
+ config ATH79_MACH_UBNT_XM
+ bool "Ubiquiti Networks XM (rev 1.0) board"
+ select SOC_AR724X
++ select ATH79_DEV_AP9X_PCI if PCI
+ select ATH79_DEV_GPIO_BUTTONS
+ select ATH79_DEV_LEDS_GPIO
+- select ATH79_DEV_SPI
++ select ATH79_DEV_M25P80
+ help
+ Say 'Y' here if you want your kernel to support the
+ Ubiquiti Networks XM (rev 1.0) board.
+--- a/arch/mips/ath79/mach-ubnt-xm.c
++++ b/arch/mips/ath79/mach-ubnt-xm.c
+@@ -16,10 +16,11 @@
+
+ #include <asm/mach-ath79/irq.h>
+
+-#include "machtypes.h"
++#include "dev-ap9x-pci.h"
+ #include "dev-gpio-buttons.h"
+ #include "dev-leds-gpio.h"
+-#include "dev-spi.h"
++#include "dev-m25p80.h"
++#include "machtypes.h"
+ #include "pci.h"
+
+ #define UBNT_XM_GPIO_LED_L1 0
+@@ -32,7 +33,7 @@
+ #define UBNT_XM_KEYS_POLL_INTERVAL 20
+ #define UBNT_XM_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_XM_KEYS_POLL_INTERVAL)
+
+-#define UBNT_XM_EEPROM_ADDR (u8 *) KSEG1ADDR(0x1fff1000)
++#define UBNT_XM_EEPROM_ADDR 0x1fff1000
+
+ static struct gpio_led ubnt_xm_leds_gpio[] __initdata = {
+ {
+@@ -65,54 +66,10 @@ static struct gpio_keys_button ubnt_xm_g
+ }
+ };
+
+-static struct ath79_spi_controller_data ubnt_xm_spi0_data = {
+- .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
+- .cs_line = 0,
+-};
+-
+-static struct spi_board_info ubnt_xm_spi_info[] = {
+- {
+- .bus_num = 0,
+- .chip_select = 0,
+- .max_speed_hz = 25000000,
+- .modalias = "mx25l6405d",
+- .controller_data = &ubnt_xm_spi0_data,
+- }
+-};
+-
+-static struct ath79_spi_platform_data ubnt_xm_spi_data = {
+- .bus_num = 0,
+- .num_chipselect = 1,
+-};
+-
+-#ifdef CONFIG_PCI
+-static struct ath9k_platform_data ubnt_xm_eeprom_data;
+-
+-static int ubnt_xm_pci_plat_dev_init(struct pci_dev *dev)
+-{
+- switch (PCI_SLOT(dev->devfn)) {
+- case 0:
+- dev->dev.platform_data = &ubnt_xm_eeprom_data;
+- break;
+- }
+-
+- return 0;
+-}
+-
+-static void __init ubnt_xm_pci_init(void)
+-{
+- memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
+- sizeof(ubnt_xm_eeprom_data.eeprom_data));
+-
+- ath79_pci_set_plat_dev_init(ubnt_xm_pci_plat_dev_init);
+- ath79_register_pci();
+-}
+-#else
+-static inline void ubnt_xm_pci_init(void) {}
+-#endif /* CONFIG_PCI */
+-
+ static void __init ubnt_xm_init(void)
+ {
++ u8 *eeprom = (u8 *) KSEG1ADDR(UBNT_XM_EEPROM_ADDR);
++
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio),
+ ubnt_xm_leds_gpio);
+
+@@ -120,10 +77,8 @@ static void __init ubnt_xm_init(void)
+ ARRAY_SIZE(ubnt_xm_gpio_keys),
+ ubnt_xm_gpio_keys);
+
+- ath79_register_spi(&ubnt_xm_spi_data, ubnt_xm_spi_info,
+- ARRAY_SIZE(ubnt_xm_spi_info));
+-
+- ubnt_xm_pci_init();
++ ath79_register_m25p80(NULL);
++ ap91_pci_init(eeprom, NULL);
+ }
+
+ MIPS_MACHINE(ATH79_MACH_UBNT_XM,
--- /dev/null
+--- a/arch/mips/ath79/mach-ubnt-xm.c
++++ b/arch/mips/ath79/mach-ubnt-xm.c
+@@ -13,15 +13,17 @@
+ #include <linux/init.h>
+ #include <linux/pci.h>
+ #include <linux/ath9k_platform.h>
++#include <linux/etherdevice.h>
+
+ #include <asm/mach-ath79/irq.h>
+
+ #include "dev-ap9x-pci.h"
++#include "dev-eth.h"
+ #include "dev-gpio-buttons.h"
+ #include "dev-leds-gpio.h"
+ #include "dev-m25p80.h"
++#include "dev-usb.h"
+ #include "machtypes.h"
+-#include "pci.h"
+
+ #define UBNT_XM_GPIO_LED_L1 0
+ #define UBNT_XM_GPIO_LED_L2 1
+@@ -37,19 +39,19 @@
+
+ static struct gpio_led ubnt_xm_leds_gpio[] __initdata = {
+ {
+- .name = "ubnt-xm:red:link1",
++ .name = "ubnt:red:link1",
+ .gpio = UBNT_XM_GPIO_LED_L1,
+ .active_low = 0,
+ }, {
+- .name = "ubnt-xm:orange:link2",
++ .name = "ubnt:orange:link2",
+ .gpio = UBNT_XM_GPIO_LED_L2,
+ .active_low = 0,
+ }, {
+- .name = "ubnt-xm:green:link3",
++ .name = "ubnt:green:link3",
+ .gpio = UBNT_XM_GPIO_LED_L3,
+ .active_low = 0,
+ }, {
+- .name = "ubnt-xm:green:link4",
++ .name = "ubnt:green:link4",
+ .gpio = UBNT_XM_GPIO_LED_L4,
+ .active_low = 0,
+ },
+@@ -66,9 +68,13 @@ static struct gpio_keys_button ubnt_xm_g
+ }
+ };
+
++#define UBNT_M_WAN_PHYMASK BIT(4)
++
+ static void __init ubnt_xm_init(void)
+ {
+ u8 *eeprom = (u8 *) KSEG1ADDR(UBNT_XM_EEPROM_ADDR);
++ u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000);
++ u8 *mac2 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio),
+ ubnt_xm_leds_gpio);
+@@ -79,9 +85,99 @@ static void __init ubnt_xm_init(void)
+
+ ath79_register_m25p80(NULL);
+ ap91_pci_init(eeprom, NULL);
++
++ ath79_register_mdio(0, ~UBNT_M_WAN_PHYMASK);
++ ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
++ ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
++ ath79_register_eth(0);
+ }
+
+ MIPS_MACHINE(ATH79_MACH_UBNT_XM,
+ "UBNT-XM",
+ "Ubiquiti Networks XM (rev 1.0) board",
+ ubnt_xm_init);
++
++MIPS_MACHINE(ATH79_MACH_UBNT_BULLET_M, "UBNT-BM", "Ubiquiti Bullet M",
++ ubnt_xm_init);
++
++static void __init ubnt_rocket_m_setup(void)
++{
++ ubnt_xm_init();
++ ath79_register_usb();
++}
++
++MIPS_MACHINE(ATH79_MACH_UBNT_ROCKET_M, "UBNT-RM", "Ubiquiti Rocket M",
++ ubnt_rocket_m_setup);
++
++static void __init ubnt_nano_m_setup(void)
++{
++ ubnt_xm_init();
++ ath79_register_eth(1);
++}
++
++MIPS_MACHINE(ATH79_MACH_UBNT_NANO_M, "UBNT-NM", "Ubiquiti Nanostation M",
++ ubnt_nano_m_setup);
++
++static struct gpio_led ubnt_airrouter_leds_gpio[] __initdata = {
++ {
++ .name = "ubnt:green:globe",
++ .gpio = 0,
++ .active_low = 1,
++ }
++};
++
++static void __init ubnt_airrouter_setup(void)
++{
++ u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000);
++ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
++
++ ath79_register_m25p80(NULL);
++ ath79_register_mdio(0, ~UBNT_M_WAN_PHYMASK);
++
++ ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
++ ath79_init_local_mac(ath79_eth1_data.mac_addr, mac1);
++
++ ath79_register_eth(1);
++ ath79_register_eth(0);
++ ath79_register_usb();
++
++ ap91_pci_init(ee, NULL);
++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_airrouter_leds_gpio),
++ ubnt_airrouter_leds_gpio);
++}
++
++MIPS_MACHINE(ATH79_MACH_UBNT_AIRROUTER, "UBNT-AR", "Ubiquiti AirRouter",
++ ubnt_airrouter_setup);
++
++static struct gpio_led ubnt_unifi_leds_gpio[] __initdata = {
++ {
++ .name = "ubnt:orange:dome",
++ .gpio = 1,
++ .active_low = 0,
++ }, {
++ .name = "ubnt:green:dome",
++ .gpio = 0,
++ .active_low = 0,
++ }
++};
++
++static void __init ubnt_unifi_setup(void)
++{
++ u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000);
++ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
++
++ ath79_register_m25p80(NULL);
++
++ ath79_register_mdio(0, ~UBNT_M_WAN_PHYMASK);
++
++ ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
++ ath79_register_eth(0);
++
++ ap91_pci_init(ee, NULL);
++
++ ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_unifi_leds_gpio),
++ ubnt_unifi_leds_gpio);
++}
++
++MIPS_MACHINE(ATH79_MACH_UBNT_UNIFI, "UBNT-UF", "Ubiquiti UniFi",
++ ubnt_unifi_setup);
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -58,9 +58,11 @@ config ATH79_MACH_UBNT_XM
+ bool "Ubiquiti Networks XM (rev 1.0) board"
+ select SOC_AR724X
+ select ATH79_DEV_AP9X_PCI if PCI
++ select ATH79_DEV_ETH
+ select ATH79_DEV_GPIO_BUTTONS
+ select ATH79_DEV_LEDS_GPIO
+ select ATH79_DEV_M25P80
++ select ATH79_DEV_USB
+ help
+ Say 'Y' here if you want your kernel to support the
+ Ubiquiti Networks XM (rev 1.0) board.
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -21,6 +21,11 @@ enum ath79_mach_type {
+ ATH79_MACH_AP81, /* Atheros AP81 reference board */
+ ATH79_MACH_DB120, /* Atheros DB120 reference board */
+ ATH79_MACH_PB44, /* Atheros PB44 reference board */
++ ATH79_MACH_UBNT_AIRROUTER, /* Ubiquiti AirRouter */
++ ATH79_MACH_UBNT_BULLET_M, /* Ubiquiti Bullet M */
++ ATH79_MACH_UBNT_NANO_M, /* Ubiquiti NanoStation M */
++ ATH79_MACH_UBNT_ROCKET_M, /* Ubiquiti Rocket M */
++ ATH79_MACH_UBNT_UNIFI, /* Ubiquiti Unifi */
+ ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */
+ };
+
--- /dev/null
+--- a/arch/mips/ath79/machtypes.h
++++ b/arch/mips/ath79/machtypes.h
+@@ -16,17 +16,77 @@
+
+ enum ath79_mach_type {
+ ATH79_MACH_GENERIC = 0,
++ ATH79_MACH_ALFA_AP96, /* ALFA Network AP96 board */
++ ATH79_MACH_ALFA_NX, /* ALFA Network N2/N5 board */
++ ATH79_MACH_ALL0258N, /* Allnet ALL0258N */
+ ATH79_MACH_AP121, /* Atheros AP121 reference board */
+ ATH79_MACH_AP121_MINI, /* Atheros AP121-MINI reference board */
+ ATH79_MACH_AP81, /* Atheros AP81 reference board */
++ ATH79_MACH_AP83, /* Atheros AP83 */
++ ATH79_MACH_AP96, /* Atheros AP96 */
++ ATH79_MACH_AW_NR580, /* AzureWave AW-NR580 */
+ ATH79_MACH_DB120, /* Atheros DB120 reference board */
+ ATH79_MACH_PB44, /* Atheros PB44 reference board */
++ ATH79_MACH_DIR_600_A1, /* D-Link DIR-600 rev. A1 */
++ ATH79_MACH_DIR_615_C1, /* D-Link DIR-615 rev. C1 */
++ ATH79_MACH_DIR_825_B1, /* D-Link DIR-825 rev. B1 */
++ ATH79_MACH_EAP7660D, /* Senao EAP7660D */
++ ATH79_MACH_JA76PF, /* jjPlus JA76PF */
++ ATH79_MACH_JWAP003, /* jjPlus JWAP003 */
++ ATH79_MACH_HORNET_UB, /* ALFA Networks Hornet-UB */
++ ATH79_MACH_MZK_W04NU, /* Planex MZK-W04NU */
++ ATH79_MACH_MZK_W300NH, /* Planex MZK-W300NH */
++ ATH79_MACH_NBG460N, /* Zyxel NBG460N/550N/550NH */
++ ATH79_MACH_OM2P, /* OpenMesh OM2P */
++ ATH79_MACH_PB42, /* Atheros PB42 */
++ ATH79_MACH_PB92, /* Atheros PB92 */
++ ATH79_MACH_RB_411, /* MikroTik RouterBOARD 411/411A/411AH */
++ ATH79_MACH_RB_411U, /* MikroTik RouterBOARD 411U */
++ ATH79_MACH_RB_433, /* MikroTik RouterBOARD 433/433AH */
++ ATH79_MACH_RB_433U, /* MikroTik RouterBOARD 433UAH */
++ ATH79_MACH_RB_450G, /* MikroTik RouterBOARD 450G */
++ ATH79_MACH_RB_450, /* MikroTik RouterBOARD 450 */
++ ATH79_MACH_RB_493, /* Mikrotik RouterBOARD 493/493AH */
++ ATH79_MACH_RB_493G, /* Mikrotik RouterBOARD 493G */
++ ATH79_MACH_RB_750, /* MikroTik RouterBOARD 750 */
++ ATH79_MACH_RW2458N, /* Redwave RW2458N */
++ ATH79_MACH_TEW_632BRP, /* TRENDnet TEW-632BRP */
++ ATH79_MACH_TL_MR3020, /* TP-LINK TL-MR3020 */
++ ATH79_MACH_TL_MR3220, /* TP-LINK TL-MR3220 */
++ ATH79_MACH_TL_MR3420, /* TP-LINK TL-MR3420 */
++ ATH79_MACH_TL_WA901ND, /* TP-LINK TL-WA901ND */
++ ATH79_MACH_TL_WA901ND_V2, /* TP-LINK TL-WA901ND v2 */
++ ATH79_MACH_TL_WR1043ND, /* TP-LINK TL-WR1041ND */
++ ATH79_MACH_TL_WR2543N, /* TP-LINK TL-WR2543N/ND */
++ ATH79_MACH_TL_WR703N, /* TP-LINK TL-WR703N */
++ ATH79_MACH_TL_WR741ND, /* TP-LINK TL-WR741ND */
++ ATH79_MACH_TL_WR741ND_V4, /* TP-LINK TL-WR741ND v4*/
++ ATH79_MACH_TL_WR841N_V1, /* TP-LINK TL-WR841N v1 */
++ ATH79_MACH_TL_WR841N_V7, /* TP-LINK TL-WR841N/ND v7 */
++ ATH79_MACH_TL_WR941ND, /* TP-LINK TL-WR941ND */
+ ATH79_MACH_UBNT_AIRROUTER, /* Ubiquiti AirRouter */
+ ATH79_MACH_UBNT_BULLET_M, /* Ubiquiti Bullet M */
++ ATH79_MACH_UBNT_LSSR71, /* Ubiquiti LS-SR71 */
++ ATH79_MACH_UBNT_LSX, /* Ubiquiti LSX */
+ ATH79_MACH_UBNT_NANO_M, /* Ubiquiti NanoStation M */
+ ATH79_MACH_UBNT_ROCKET_M, /* Ubiquiti Rocket M */
++ ATH79_MACH_UBNT_RSPRO, /* Ubiquiti RouterStation Pro */
++ ATH79_MACH_UBNT_RS, /* Ubiquiti RouterStation */
+ ATH79_MACH_UBNT_UNIFI, /* Ubiquiti Unifi */
+ ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */
++ ATH79_MACH_WHR_G301N, /* Buffalo WHR-G301N */
++ ATH79_MACH_WHR_HP_G300N, /* Buffalo WHR-HP-G300N */
++ ATH79_MACH_WHR_HP_GN, /* Buffalo WHR-HP-GN */
++ ATH79_MACH_WNDR3700, /* NETGEAR WNDR3700/WNDR3800/WNDRMAC */
++ ATH79_MACH_WNR2000, /* NETGEAR WNR2000 */
++ ATH79_MACH_WP543, /* Compex WP543 */
++ ATH79_MACH_WRT160NL, /* Linksys WRT160NL */
++ ATH79_MACH_WRT400N, /* Linksys WRT400N */
++ ATH79_MACH_WZR_HP_AG300H, /* Buffalo WZR-HP-AG300H */
++ ATH79_MACH_WZR_HP_G300NH, /* Buffalo WZR-HP-G300NH */
++ ATH79_MACH_WZR_HP_G300NH2, /* Buffalo WZR-HP-G300NH2 */
++ ATH79_MACH_WZR_HP_G450H, /* Buffalo WZR-HP-G450H */
++ ATH79_MACH_ZCN_1523H_2, /* Zcomax ZCN-1523H-2-xx */
+ };
+
+ #endif /* _ATH79_MACHTYPE_H */
+--- a/arch/mips/ath79/Kconfig
++++ b/arch/mips/ath79/Kconfig
+@@ -2,6 +2,42 @@ if ATH79
+
+ menu "Atheros AR71XX/AR724X/AR913X machine selection"
+
++config ATH79_MACH_ALFA_AP96
++ bool "ALFA Network AP96 board support"
++ select SOC_AR71XX
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_SPI
++ select ATH79_DEV_USB
++
++config ATH79_MACH_HORNET_UB
++ bool "ALFA Network Hornet-UB board support"
++ select SOC_AR933X
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++ select ATH79_DEV_USB
++ select ATH79_DEV_WMAC
++
++config ATH79_MACH_ALFA_NX
++ bool "ALFA Network N2/N5 board support"
++ select SOC_AR724X
++ select ATH79_DEV_AP9X_PCI if PCI
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++
++config ATH79_MACH_ALL0258N
++ bool "Allnet ALL0258N support"
++ select SOC_AR724X
++ select ATH79_DEV_AP9X_PCI if PCI
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++
+ config ATH79_MACH_AP121
+ bool "Atheros AP121 reference board"
+ select SOC_AR933X
+@@ -28,6 +64,36 @@ config ATH79_MACH_AP81
+ Say 'Y' here if you want your kernel to support the
+ Atheros AP81 reference board.
+
++config ATH79_MACH_AP83
++ bool "Atheros AP83 board support"
++ select SOC_AR913X
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_USB
++ select ATH79_DEV_WMAC
++
++config ATH79_MACH_AP96
++ bool "Atheros AP96 board support"
++ select SOC_AR71XX
++ select ATH79_DEV_ETH
++ select ATH79_DEV_AP9X_PCI if PCI
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++ select ATH79_DEV_USB
++
++config ATH79_MACH_AP121
++ bool "Atheros AP121 reference board"
++ select SOC_AR933X
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_SPI
++ select ATH79_DEV_USB
++ select ATH79_DEV_WMAC
++ help
++ Say 'Y' here if you want your kernel to support the
++ Atheros AP121 reference board.
++
+ config ATH79_MACH_DB120
+ bool "Atheros DB120 reference board"
+ select SOC_AR934X
+@@ -42,6 +108,13 @@ config ATH79_MACH_DB120
+ Say 'Y' here if you want your kernel to support the
+ Atheros DB120 reference board.
+
++config ATH79_MACH_PB42
++ bool "Atheros PB42 board support"
++ select SOC_AR71XX
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_M25P80
++
+ config ATH79_MACH_PB44
+ bool "Atheros PB44 reference board"
+ select SOC_AR71XX
+@@ -54,6 +127,349 @@ config ATH79_MACH_PB44
+ Say 'Y' here if you want your kernel to support the
+ Atheros PB44 reference board.
+
++config ATH79_MACH_PB92
++ bool "Atheros PB92 board support"
++ select SOC_AR724X
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_PB9X_PCI if PCI
++ select ATH79_DEV_USB
++
++config ATH79_MACH_AW_NR580
++ bool "AzureWave AW-NR580 board support"
++ select SOC_AR71XX
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++
++config ATH79_MACH_WHR_HP_G300N
++ bool "Buffalo WHR-HP-G300N board support"
++ select SOC_AR724X
++ select ATH79_DEV_ETH
++ select ATH79_DEV_AP9X_PCI if PCI
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++
++config ATH79_MACH_WZR_HP_AG300H
++ bool "Buffalo WZR-HP-AG300H board support"
++ select SOC_AR71XX
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++ select ATH79_DEV_USB
++
++config ATH79_MACH_WZR_HP_G300NH
++ bool "Buffalo WZR-HP-G300NH board support"
++ select SOC_AR913X
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_USB
++ select ATH79_DEV_WMAC
++ select RTL8366_SMI
++
++config ATH79_MACH_WZR_HP_G300NH2
++ bool "Buffalo WZR-HP-G300NH2 board support"
++ select SOC_AR724X
++ select ATH79_DEV_AP9X_PCI if PCI
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++ select ATH79_DEV_USB
++
++config ATH79_MACH_WZR_HP_G450H
++ bool "Buffalo WZR-HP-G450H board support"
++ select SOC_AR724X
++ select ATH79_DEV_ETH
++ select ATH79_DEV_AP9X_PCI if PCI
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++ select ATH79_DEV_USB
++
++config ATH79_MACH_WP543
++ bool "Compex WP543/WPJ543 board support"
++ select SOC_AR71XX
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++ select ATH79_DEV_USB
++ select MYLOADER
++
++config ATH79_MACH_DIR_600_A1
++ bool "D-Link DIR-600 rev. A1 support"
++ select SOC_AR724X
++ select ATH79_DEV_AP9X_PCI if PCI
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++ select ATH79_NVRAM
++
++config ATH79_MACH_DIR_615_C1
++ bool "D-Link DIR-615 rev. C1 support"
++ select SOC_AR913X
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++ select ATH79_DEV_WMAC
++ select ATH79_NVRAM
++
++config ATH79_MACH_DIR_825_B1
++ bool "D-Link DIR-825 rev. B1 board support"
++ select SOC_AR71XX
++ select ATH79_DEV_ETH
++ select ATH79_DEV_AP9X_PCI if PCI
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++ select ATH79_DEV_USB
++
++config ATH79_MACH_JA76PF
++ bool "jjPlus JA76PF board support"
++ select SOC_AR71XX
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++ select ATH79_DEV_USB
++
++config ATH79_MACH_JWAP003
++ bool "jjPlus JWAP003 board support"
++ select SOC_AR71XX
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_M25P80
++ select ATH79_DEV_USB
++
++config ATH79_MACH_WRT160NL
++ bool "Linksys WRT160NL board support"
++ select SOC_AR913X
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++ select ATH79_DEV_USB
++ select ATH79_DEV_WMAC
++ select ATH79_NVRAM
++
++config ATH79_MACH_WRT400N
++ bool "Linksys WRT400N board support"
++ select SOC_AR71XX
++ select ATH79_DEV_ETH
++ select ATH79_DEV_AP9X_PCI if PCI
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++
++config ATH79_MACH_RB4XX
++ bool "MikroTik RouterBOARD 4xx series support"
++ select SOC_AR71XX
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_USB
++
++config ATH79_MACH_RB750
++ bool "MikroTik RouterBOARD 750 support"
++ select SOC_AR724X
++ select ATH79_DEV_ETH
++
++config ATH79_MACH_WNDR3700
++ bool "NETGEAR WNDR3700 board support"
++ select SOC_AR71XX
++ select ATH79_DEV_AP9X_PCI if PCI
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++ select ATH79_DEV_USB
++
++config ATH79_MACH_WNR2000
++ bool "NETGEAR WNR2000 board support"
++ select SOC_AR913X
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++ select ATH79_DEV_WMAC
++
++config ATH79_MACH_OM2P
++ bool "OpenMesh OM2P board support"
++ select SOC_AR724X
++ select ATH79_DEV_AP9X_PCI if PCI
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++
++config ATH79_MACH_MZK_W04NU
++ bool "Planex MZK-W04NU board support"
++ select SOC_AR913X
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++ select ATH79_DEV_USB
++ select ATH79_DEV_WMAC
++
++config ATH79_MACH_MZK_W300NH
++ bool "Planex MZK-W300NH board support"
++ select SOC_AR913X
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++ select ATH79_DEV_WMAC
++
++config ATH79_MACH_RW2458N
++ bool "Redwave RW2458N board support"
++ select SOC_AR724X
++ select ATH79_DEV_ETH
++ select ATH79_DEV_AP9X_PCI if PCI
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++ select ATH79_DEV_USB
++
++config ATH79_MACH_EAP7660D
++ bool "Senao EAP7660D support"
++ select SOC_AR71XX
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++
++config ATH79_MACH_TL_MR3020
++ bool "TP-LINK TL-MR3020 support"
++ select SOC_AR933X
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++ select ATH79_DEV_USB
++ select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_MR3X20
++ bool "TP-LINK TL-MR3220/3420 support"
++ select SOC_AR724X
++ select ATH79_DEV_AP9X_PCI if PCI
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++ select ATH79_DEV_USB
++
++config ATH79_MACH_TL_WA901ND
++ bool "TP-LINK TL-WA901ND support"
++ select SOC_AR724X
++ select ATH79_DEV_AP9X_PCI if PCI
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++
++config ATH79_MACH_TL_WA901ND_V2
++ bool "TP-LINK TL-WA901ND v2 support"
++ select SOC_AR913X
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++ select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_WR703N
++ bool "TP-LINK TL-WR703N support"
++ select SOC_AR933X
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++ select ATH79_DEV_USB
++ select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_WR741ND
++ bool "TP-LINK TL-WR741ND support"
++ select SOC_AR724X
++ select ATH79_DEV_AP9X_PCI if PCI
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++
++config ATH79_MACH_TL_WR741ND_V4
++ bool "TP-LINK TL-WR741ND v4 support"
++ select SOC_AR933X
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++ select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_WR841N_V1
++ bool "TP-LINK TL-WR841N v1 support"
++ select SOC_AR71XX
++ select ATH79_DEV_DSA
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++
++config ATH79_MACH_TL_WR941ND
++ bool "TP-LINK TL-WR941ND support"
++ select SOC_AR913X
++ select ATH79_DEV_DSA
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++ select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_WR1043ND
++ bool "TP-LINK TL-WR1043ND support"
++ select SOC_AR913X
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++ select ATH79_DEV_USB
++ select ATH79_DEV_WMAC
++
++config ATH79_MACH_TL_WR2543N
++ bool "TP-LINK TL-WR2543N/ND support"
++ select SOC_AR724X
++ select ATH79_DEV_AP9X_PCI if PCI
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++ select ATH79_DEV_USB
++
++config ATH79_MACH_TEW_632BRP
++ bool "TRENDnet TEW-632BRP support"
++ select SOC_AR913X
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++ select ATH79_DEV_WMAC
++ select ATH79_NVRAM
++
++config ATH79_MACH_UBNT
++ bool "Ubiquiti AR71xx based boards support"
++ select SOC_AR71XX
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++ select ATH79_DEV_USB
++
+ config ATH79_MACH_UBNT_XM
+ bool "Ubiquiti Networks XM (rev 1.0) board"
+ select SOC_AR724X
+@@ -67,6 +483,24 @@ config ATH79_MACH_UBNT_XM
+ Say 'Y' here if you want your kernel to support the
+ Ubiquiti Networks XM (rev 1.0) board.
+
++config ATH79_MACH_ZCN_1523H
++ bool "Zcomax ZCN-1523H support"
++ select SOC_AR724X
++ select ATH79_DEV_AP9X_PCI if PCI
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++
++config ATH79_MACH_NBG460N
++ bool "Zyxel NBG460N/550N/550NH board support"
++ select SOC_AR913X
++ select ATH79_DEV_ETH
++ select ATH79_DEV_GPIO_BUTTONS
++ select ATH79_DEV_LEDS_GPIO
++ select ATH79_DEV_M25P80
++ select ATH79_DEV_WMAC
++
+ endmenu
+
+ config SOC_AR71XX
+@@ -96,10 +530,6 @@ config SOC_AR934X
+ select PCI_AR724X if PCI
+ def_bool n
+
+-config ATH79_DEV_M25P80
+- select ATH79_DEV_SPI
+- def_bool n
+-
+ config ATH79_DEV_AP9X_PCI
+ select ATH79_PCI_ATH9K_FIXUP
+ def_bool n
+@@ -110,7 +540,14 @@ config ATH79_DEV_DSA
+ config ATH79_DEV_ETH
+ def_bool n
+
+-config PCI_AR724X
++config ATH79_DEV_M25P80
++ select ATH79_DEV_SPI
++ def_bool n
++
++config ATH79_DEV_DSA
++ def_bool n
++
++config ATH79_DEV_ETH
+ def_bool n
+
+ config ATH79_DEV_GPIO_BUTTONS
+@@ -135,4 +572,7 @@ config ATH79_NVRAM
+ config ATH79_PCI_ATH9K_FIXUP
+ def_bool n
+
++config PCI_AR724X
++ def_bool n
++
+ endif
+--- a/arch/mips/ath79/Makefile
++++ b/arch/mips/ath79/Makefile
+@@ -36,8 +36,53 @@ obj-$(CONFIG_ATH79_PCI_ATH9K_FIXUP) += p
+ #
+ # Machines
+ #
++obj-$(CONFIG_ATH79_MACH_ALFA_AP96) += mach-alfa-ap96.o
++obj-$(CONFIG_ATH79_MACH_ALFA_NX) += mach-alfa-nx.o
++obj-$(CONFIG_ATH79_MACH_ALL0258N) += mach-all0258n.o
+ obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o
+ obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o
++obj-$(CONFIG_ATH79_MACH_AP83) += mach-ap83.o
++obj-$(CONFIG_ATH79_MACH_AP96) += mach-ap96.o
++obj-$(CONFIG_ATH79_MACH_AW_NR580) += mach-aw-nr580.o
+ obj-$(CONFIG_ATH79_MACH_DB120) += mach-db120.o
++obj-$(CONFIG_ATH79_MACH_DIR_600_A1) += mach-dir-600-a1.o
++obj-$(CONFIG_ATH79_MACH_DIR_615_C1) += mach-dir-615-c1.o
++obj-$(CONFIG_ATH79_MACH_DIR_825_B1) += mach-dir-825-b1.o
++obj-$(CONFIG_ATH79_MACH_EAP7660D) += mach-eap7660d.o
++obj-$(CONFIG_ATH79_MACH_JA76PF) += mach-ja76pf.o
++obj-$(CONFIG_ATH79_MACH_JWAP003) += mach-jwap003.o
++obj-$(CONFIG_ATH79_MACH_HORNET_UB) += mach-hornet-ub.o
++obj-$(CONFIG_ATH79_MACH_MZK_W04NU) += mach-mzk-w04nu.o
++obj-$(CONFIG_ATH79_MACH_MZK_W300NH) += mach-mzk-w300nh.o
++obj-$(CONFIG_ATH79_MACH_NBG460N) += mach-nbg460n.o
++obj-$(CONFIG_ATH79_MACH_OM2P) += mach-om2p.o
++obj-$(CONFIG_ATH79_MACH_PB42) += mach-pb42.o
+ obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o
++obj-$(CONFIG_ATH79_MACH_PB92) += mach-pb92.o
++obj-$(CONFIG_ATH79_MACH_RB4XX) += mach-rb4xx.o
++obj-$(CONFIG_ATH79_MACH_RB750) += mach-rb750.o
++obj-$(CONFIG_ATH79_MACH_RW2458N) += mach-rw2458n.o
++obj-$(CONFIG_ATH79_MACH_TEW_632BRP) += mach-tew-632brp.o
++obj-$(CONFIG_ATH79_MACH_TL_MR3020) += mach-tl-mr3020.o
++obj-$(CONFIG_ATH79_MACH_TL_MR3X20) += mach-tl-mr3x20.o
++obj-$(CONFIG_ATH79_MACH_TL_WA901ND) += mach-tl-wa901nd.o
++obj-$(CONFIG_ATH79_MACH_TL_WA901ND_V2) += mach-tl-wa901nd-v2.o
++obj-$(CONFIG_ATH79_MACH_TL_WR741ND) += mach-tl-wr741nd.o
++obj-$(CONFIG_ATH79_MACH_TL_WR741ND_V4) += mach-tl-wr741nd-v4.o
++obj-$(CONFIG_ATH79_MACH_TL_WR841N_V1) += mach-tl-wr841n.o
++obj-$(CONFIG_ATH79_MACH_TL_WR941ND) += mach-tl-wr941nd.o
++obj-$(CONFIG_ATH79_MACH_TL_WR1043ND) += mach-tl-wr1043nd.o
++obj-$(CONFIG_ATH79_MACH_TL_WR2543N) += mach-tl-wr2543n.o
++obj-$(CONFIG_ATH79_MACH_TL_WR703N) += mach-tl-wr703n.o
++obj-$(CONFIG_ATH79_MACH_UBNT) += mach-ubnt.o
+ obj-$(CONFIG_ATH79_MACH_UBNT_XM) += mach-ubnt-xm.o
++obj-$(CONFIG_ATH79_MACH_WHR_HP_G300N) += mach-whr-hp-g300n.o
++obj-$(CONFIG_ATH79_MACH_WNDR3700) += mach-wndr3700.o
++obj-$(CONFIG_ATH79_MACH_WNR2000) += mach-wnr2000.o
++obj-$(CONFIG_ATH79_MACH_WP543) += mach-wp543.o
++obj-$(CONFIG_ATH79_MACH_WRT160NL) += mach-wrt160nl.o
++obj-$(CONFIG_ATH79_MACH_WRT400N) += mach-wrt400n.o
++obj-$(CONFIG_ATH79_MACH_WZR_HP_G300NH) += mach-wzr-hp-g300nh.o
++obj-$(CONFIG_ATH79_MACH_WZR_HP_G300NH2) += mach-wzr-hp-g300nh2.o
++obj-$(CONFIG_ATH79_MACH_WZR_HP_AG300H) += mach-wzr-hp-ag300h.o
++obj-$(CONFIG_ATH79_MACH_WZR_HP_G450H) += mach-wzr-hp-g450h.o
--- /dev/null
+--- a/drivers/net/phy/mdio-bitbang.c
++++ b/drivers/net/phy/mdio-bitbang.c
+@@ -165,16 +165,7 @@ static int mdiobb_read(struct mii_bus *b
+
+ ctrl->ops->set_mdio_dir(ctrl, 0);
+
+- /* check the turnaround bit: the PHY should be driving it to zero */
+- if (mdiobb_get_bit(ctrl) != 0) {
+- /* PHY didn't drive TA low -- flush any bits it
+- * may be trying to send.
+- */
+- for (i = 0; i < 32; i++)
+- mdiobb_get_bit(ctrl);
+-
+- return 0xffff;
+- }
++ mdiobb_get_bit(ctrl);
+
+ ret = mdiobb_get_num(ctrl, 16);
+ mdiobb_get_bit(ctrl);
--- /dev/null
+--- a/arch/mips/include/asm/checksum.h
++++ b/arch/mips/include/asm/checksum.h
+@@ -12,6 +12,7 @@
+ #define _ASM_CHECKSUM_H
+
+ #include <linux/in6.h>
++#include <linux/unaligned/packed_struct.h>
+
+ #include <asm/uaccess.h>
+
+@@ -104,26 +105,30 @@ static inline __sum16 ip_fast_csum(const
+ const unsigned int *stop = word + ihl;
+ unsigned int csum;
+ int carry;
++ unsigned int w;
+
+- csum = word[0];
+- csum += word[1];
+- carry = (csum < word[1]);
++ csum = __get_unaligned_cpu32(word++);
++
++ w = __get_unaligned_cpu32(word++);
++ csum += w;
++ carry = (csum < w);
+ csum += carry;
+
+- csum += word[2];
+- carry = (csum < word[2]);
++ w = __get_unaligned_cpu32(word++);
++ csum += w;
++ carry = (csum < w);
+ csum += carry;
+
+- csum += word[3];
+- carry = (csum < word[3]);
++ w = __get_unaligned_cpu32(word++);
++ csum += w;
++ carry = (csum < w);
+ csum += carry;
+
+- word += 4;
+ do {
+- csum += *word;
+- carry = (csum < *word);
++ w = __get_unaligned_cpu32(word++);
++ csum += w;
++ carry = (csum < w);
+ csum += carry;
+- word++;
+ } while (word != stop);
+
+ return csum_fold(csum);
+--- a/include/linux/ip.h
++++ b/include/linux/ip.h
+@@ -102,7 +102,7 @@ struct iphdr {
+ __be32 saddr;
+ __be32 daddr;
+ /*The options start here. */
+-};
++} __packed;
+
+ #ifdef __KERNEL__
+ #include <linux/skbuff.h>
+--- a/include/linux/ipv6.h
++++ b/include/linux/ipv6.h
+@@ -126,7 +126,7 @@ struct ipv6hdr {
+
+ struct in6_addr saddr;
+ struct in6_addr daddr;
+-};
++} __packed;
+
+ #ifdef __KERNEL__
+ /*
+--- a/include/linux/tcp.h
++++ b/include/linux/tcp.h
+@@ -54,7 +54,7 @@ struct tcphdr {
+ __be16 window;
+ __sum16 check;
+ __be16 urg_ptr;
+-};
++} __packed;
+
+ /*
+ * The union cast uses a gcc extension to avoid aliasing problems
+--- a/include/linux/udp.h
++++ b/include/linux/udp.h
+@@ -24,7 +24,7 @@ struct udphdr {
+ __be16 dest;
+ __be16 len;
+ __sum16 check;
+-};
++} __packed;
+
+ /* UDP socket options */
+ #define UDP_CORK 1 /* Never send partially complete segments */
+--- a/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c
++++ b/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c
+@@ -14,6 +14,7 @@
+ #include <linux/skbuff.h>
+ #include <linux/icmp.h>
+ #include <linux/sysctl.h>
++#include <linux/unaligned/packed_struct.h>
+ #include <net/route.h>
+ #include <net/ip.h>
+
+@@ -44,8 +45,8 @@ static bool ipv4_pkt_to_tuple(const stru
+ if (ap == NULL)
+ return false;
+
+- tuple->src.u3.ip = ap[0];
+- tuple->dst.u3.ip = ap[1];
++ tuple->src.u3.ip = __get_unaligned_cpu32(ap++);
++ tuple->dst.u3.ip = __get_unaligned_cpu32(ap);
+
+ return true;
+ }
projects / openwrt / svn-archive / archive.git / commitdiff