bcm63xx: add 3.9 support
authorJonas Gorski <jogo@openwrt.org>
Sun, 19 May 2013 18:32:13 +0000 (18:32 +0000)
committerJonas Gorski <jogo@openwrt.org>
Sun, 19 May 2013 18:32:13 +0000 (18:32 +0000)
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 36660

133 files changed:
target/linux/brcm63xx/config-3.9 [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/005-spi-bcm63xx-properly-prepare-clocks-before-enabling-.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/006-spi-bcm63xx-remove-duplicated-mode-bits-check.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/007-spi-bcm63xx-remove-unneeded-debug-message.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/008-spi-bcm63xx-remove-unused-variable-bs-from-bcm63xx_s.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/009-spi-bcm63xx-check-spi-bits_per_word-in-spi_setup.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/010-spi-bcm63xx-simplify-bcm63xx_spi_check_transfer.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/011-spi-bcm63xx-remove-spi-chip-select-validity-check.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/012-spi-bcm63xx-inline-bcm63xx_spi_check_transfer.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/013-spi-bcm63xx-inline-hz-usage-in-bcm63xx_spi_setup_tra.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/014-spi-bcm63xx-use-devm_ioremap_resource.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/015-spi-bcm63xx-remove-unused-speed_hz-member-variable.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/018-MIPS-BCM63XX-merge-bcm63xx_clk.h-into-bcm63xx-clk.c.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/019-bcm63xx_enet-use-managed-io-memory-allocations.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/020-bcm63xx_enet-use-managed-memory-allocations.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/021-bcm63xx_enet-properly-prepare-unprepare-clocks-befor.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/022-MIPS-BCM63XX-remove-duplicate-spi-register-definitio.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/023-MIPS-BCM63XX-fix-revision-ID-width.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/024-MIPS-BCM63XX-rework-chip-detection.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/025-MIPS-BCM63XX-add-basic-BCM6362-support.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/026-MIPS-BCM63XX-enable-SPI-controller-for-BCM6362.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/027-MIPS-BCM63XX-enable-pcie-for-BCM6362.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/028-MIPS-BCM63XX-add-flash-detection-for-BCM6362.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/029-MIPS-BCM63XX-add-missing-clocks-for-BCM6328-and-BCM6.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/030-MTD-bcm63xxpart-use-size-macro-for-CFE-block-size.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/031-MIPS-BCM63XX-export-PSI-size-from-nvram.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/032-MTD-bcm63xxpart-use-nvram-for-PSI-size.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/100-MIPS-BCM63XX-add-USB-host-clock-enable-delay.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/101-MIPS-BCM63XX-add-USB-device-clock-enable-delay-to-cl.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/102-MIPS-BCM63XX-move-code-touching-the-USB-private-regi.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/103-MIPS-BCM63XX-add-OHCI-EHCI-configuration-bits-to-com.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/104-MIPS-BCM63XX-introduce-BCM63XX_OHCI-configuration-sy.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/105-MIPS-BCM63XX-add-support-for-the-on-chip-OHCI-contro.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/106-MIPS-BCM63XX-register-OHCI-controller-if-board-enabl.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/107-MIPS-BCM63XX-introduce-BCM63XX_EHCI-configuration-sy.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/108-MIPS-BCM63XX-add-support-for-the-on-chip-EHCI-contro.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/109-MIPS-BCM63XX-register-EHCI-controller-if-board-enabl.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/110-MIPS-BCM63XX-EHCI-controller-does-not-support-overcu.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/201-SPI-Allow-specifying-the-parsers-for-SPI-flash.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/202-MTD-DEVICES-m25p80-use-parsers-if-provided-in-flash-.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/203-MTD-DEVICES-m25p80-add-support-for-limiting-reads.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/300-reset_buttons.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/301-led_count.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/302-extended-platform-devices.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/303-spi-board-info.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/304-boardid_fixup.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/305-MIPS-BCM63XX-allow-second-UART-on-BCM6328.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/306-MIPS-BCM63XX-expose-the-HS-SPI-clock.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/307-MIPS-BCM63XX-add-HSSPI-register-definitions.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/308-board_leds_naming.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/309-cfe_version_mod.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/310-BCM63XX-Add-SMP-support-to-prom.c.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/311-MIPS-BCM63XX-Handle-SW-IRQs-0-1.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/312-MIPS-BCM63XX-select-SYS_HAS_CPU_BMIPS4350-for-suppor.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/313-MIPS-BCM63XX-rename-__dispatch_internal-to-__dispatc.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/314-MIPS-BCM63XX-replace-irq-dispatch-code-with-a-generi.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/315-MIPS-BCM63XX-append-cpu-number-to-irq_-stat-mask.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/316-MIPS-BCM63XX-populate-irq_-stat-mask-_addr-for-secon.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/317-MIPS-BCM63XX-use-a-helper-for-getting-the-right-regi.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/318-MIPS-BCM63XX-add-cpu-argument-to-dispatch-internal.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/319-MIPS-BCM63XX-protect-irq-register-accesses-with-a-sp.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/320-MIPS-BCM63XX-wire-up-the-second-CPU-s-irq-line.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/321-MIPS-BCM63XX-add-cpumask-argument-to-unmask.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/322-MIPS-BCM63XX-allow-setting-affinity-for-IPIC.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/323-cfe_simplify_detection.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/324-bcm63xxpart_use_cfedetection.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/400-bcm963xx_flashmap.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/401-bcm963xx_real_rootfs_length.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/402_bcm63xx_enet_vlan_incoming_fixed.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/403-6358-enet1-external-mii-clk.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/404-NET-bcm63xx_enet-move-phy_-dis-connect-into-probe-re.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/405-bcm63xx_enet-implement-reset_autoneg-ethtool.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/406-bcm63xx_enet-split-dma-registers-access.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/407-bcm63xx_enet-add-support-for-bcm6368-internal-ethern.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/408-bcm63xx_enet-enable-rgmii-clock-on-external-ports.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/409-MIPS-BCM63XX-add-HS-SPI-platform-device-and-register.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/410-SPI-MIPS-BCM63XX-Add-HS-SPI-driver.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/411-MIPS-BCM63XX-Register-SPI-flash-if-present.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/412-MTD-physmap-allow-passing-pp_data.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/413-BCM63XX-allow-providing-fixup-data-in-board-data.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/414-MTD-m25p80-allow-passing-pp_data.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/415-MIPS-BCM63XX-store-the-flash-type-in-global-variable.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/416-BCM63XX-add-a-fixup-for-ath9k-devices.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/417-MTD-bcm63xxpart-allow-passing-a-caldata-offset.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/418-MIPS-BCM63XX-pass-caldata-info-to-flash.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/419-MIPS-BCM63XX-enable-enet-for-BCM6345.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/420-BCM63XX-add-endian-check-for-ath9k.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/421-BCM63XX-add-led-pin-for-ath9k.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/422-BCM63XX-add-a-fixup-for-rt2x00-devices.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/423-bcm63xx_enet_add_b53_support.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/500-board-D4PW.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/501-board-NB4.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/502-board-96338W2_E7T.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/503-board-CPVA642.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/504-board_dsl_274xb_rev_c.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/505-board_spw500v.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/506-board_gw6200_gw6000.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/507-board-MAGIC.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/508-board_hw553.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/509-board_rta1320_16m.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/510-board_spw303v.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/511-board_V2500V.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/512-board_BTV2110.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/513-board_livebox.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/514-board_ct536_ct5621.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/515-board_DWV-S0_fixes.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/516-board_96348A-122.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/517-RTA1205W_16_uart_fixes.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/519_board_CPVA502plus.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/520-bcm63xx-add-support-for-96368MVWG-board.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/521-bcm63xx-add-support-for-96368MVNgr-board.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/522-MIPS-BCM63XX-add-96328avng-reference-board.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/523-MIPS-BCM63XX-add-963281TAN-reference-board.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/524-board_dsl_274xb_rev_f.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/525-board_96348w3.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/526-board_CT6373-1.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/527-board_dva-g3810bn-tl-1.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/528-board_nb6.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/529-board_fast2604.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/530-board_963281T_TEF.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/531-board_96328A-1441N1.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/532-board_96328a-1241N.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/533-board_rta770bw.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/534-board_hw556.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/535-board_rta770w.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/550-alice_gate2_leds.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/551-96348gw_a_leds.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/552-board_96348gw-10_reset_button.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/553-boards_probe_switch.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/554-board_DWVS0_leds_buttons.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/800-wl_exports.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/801-ssb_export_fallback_sprom.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.9/802-rtl8367r_fix_RGMII_support.patch [new file with mode: 0644]

diff --git a/target/linux/brcm63xx/config-3.9 b/target/linux/brcm63xx/config-3.9
new file mode 100644 (file)
index 0000000..5b231c4
--- /dev/null
@@ -0,0 +1,178 @@
+# CONFIG_ALWAYS_USE_PERSISTENT_CLOCK is not set
+CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
+CONFIG_ARCH_DISCARD_MEMBLOCK=y
+CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_AUDIT=y
+CONFIG_AUDIT_GENERIC=y
+CONFIG_B53=y
+CONFIG_B53_MMAP_DRIVER=y
+CONFIG_B53_PHY_DRIVER=y
+CONFIG_B53_PHY_FIXUP=y
+CONFIG_B53_SPI_DRIVER=y
+CONFIG_BCM63XX=y
+CONFIG_BCM63XX_EHCI=y
+CONFIG_BCM63XX_ENET=y
+CONFIG_BCM63XX_OHCI=y
+CONFIG_BCM63XX_PHY=y
+CONFIG_BCM63XX_WDT=y
+CONFIG_BOARD_BCM963XX=y
+# CONFIG_BOARD_LIVEBOX is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_CEVT_R4K=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPSR1=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_R4K_FPU=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CSRC_R4K=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_74X164=y
+CONFIG_GPIO_DEVRES=y
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HAMRADIO is not set
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HW_HAS_PCI=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_BCM63XX=y
+CONFIG_HZ=250
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+CONFIG_IMAGE_CMDLINE_HACK=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+CONFIG_IRQ_CPU=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_LEDS_GPIO=y
+# CONFIG_LZO_COMPRESS is not set
+# CONFIG_LZO_DECOMPRESS is not set
+CONFIG_M25PXX_USE_FAST_READ=y
+CONFIG_MDIO_BOARDINFO=y
+CONFIG_MIPS=y
+# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_MACHINE is not set
+CONFIG_MIPS_MT_DISABLED=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MTD_BCM63XX_PARTS=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_BE_BYTE_SWAP=y
+# CONFIG_MTD_CFI_GEOMETRY is not set
+# CONFIG_MTD_CFI_NOSWAP is not set
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_REDBOOT_PARTS=y
+CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_PCI=y
+# CONFIG_PCIEAER is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PHYLIB=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_RALINK is not set
+# CONFIG_RCU_STALL_COMMON is not set
+CONFIG_RELAY=y
+CONFIG_RTL8366_SMI=y
+CONFIG_RTL8367_PHY=y
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_BCM63XX=y
+CONFIG_SERIAL_BCM63XX_CONSOLE=y
+CONFIG_SPI=y
+CONFIG_SPI_BCM63XX=y
+CONFIG_SPI_BCM63XX_HSSPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_GPIO=y
+CONFIG_SPI_MASTER=y
+CONFIG_SQUASHFS_EMBEDDED=y
+CONFIG_SSB=y
+CONFIG_SSB_B43_PCI_BRIDGE=y
+CONFIG_SSB_BLOCKIO=y
+# CONFIG_SSB_DRIVER_MIPS is not set
+CONFIG_SSB_DRIVER_PCICORE=y
+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
+CONFIG_SSB_PCIHOST=y
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+CONFIG_SSB_SPROM=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_SWCONFIG=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_UIDGID_CONVERTED=y
+CONFIG_USB_ARCH_HAS_XHCI=y
+# CONFIG_USB_HCD_SSB is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+CONFIG_ZONE_DMA_FLAG=0
diff --git a/target/linux/brcm63xx/patches-3.9/005-spi-bcm63xx-properly-prepare-clocks-before-enabling-.patch b/target/linux/brcm63xx/patches-3.9/005-spi-bcm63xx-properly-prepare-clocks-before-enabling-.patch
new file mode 100644 (file)
index 0000000..b75a57c
--- /dev/null
@@ -0,0 +1,61 @@
+From e504d3ed9b35f43e61cf239b103667d87cd7bf3c Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Mon, 10 Sep 2012 01:26:55 +0200
+Subject: [PATCH 03/12] spi/bcm63xx: properly prepare clocks before enabling
+ them
+
+Use proper clk_prepare/unprepare calls in preparation for switching
+to the generic clock framework.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ drivers/spi/spi-bcm63xx.c |   10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+--- a/drivers/spi/spi-bcm63xx.c
++++ b/drivers/spi/spi-bcm63xx.c
+@@ -493,7 +493,7 @@ static int bcm63xx_spi_probe(struct plat
+       }
+       /* Initialize hardware */
+-      clk_enable(bs->clk);
++      clk_prepare_enable(bs->clk);
+       bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
+       /* register and we are done */
+@@ -509,7 +509,7 @@ static int bcm63xx_spi_probe(struct plat
+       return 0;
+ out_clk_disable:
+-      clk_disable(clk);
++      clk_disable_unprepare(clk);
+ out_err:
+       platform_set_drvdata(pdev, NULL);
+       spi_master_put(master);
+@@ -530,7 +530,7 @@ static int bcm63xx_spi_remove(struct pla
+       bcm_spi_writeb(bs, 0, SPI_INT_MASK);
+       /* HW shutdown */
+-      clk_disable(bs->clk);
++      clk_disable_unprepare(bs->clk);
+       clk_put(bs->clk);
+       platform_set_drvdata(pdev, 0);
+@@ -549,7 +549,7 @@ static int bcm63xx_spi_suspend(struct de
+       spi_master_suspend(master);
+-      clk_disable(bs->clk);
++      clk_disable_unprepare(bs->clk);
+       return 0;
+ }
+@@ -560,7 +560,7 @@ static int bcm63xx_spi_resume(struct dev
+                       platform_get_drvdata(to_platform_device(dev));
+       struct bcm63xx_spi *bs = spi_master_get_devdata(master);
+-      clk_enable(bs->clk);
++      clk_prepare_enable(bs->clk);
+       spi_master_resume(master);
diff --git a/target/linux/brcm63xx/patches-3.9/006-spi-bcm63xx-remove-duplicated-mode-bits-check.patch b/target/linux/brcm63xx/patches-3.9/006-spi-bcm63xx-remove-duplicated-mode-bits-check.patch
new file mode 100644 (file)
index 0000000..d387300
--- /dev/null
@@ -0,0 +1,27 @@
+From 3abf34d4e0460bb098fabe3cc8207108bae1905a Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Mon, 11 Mar 2013 13:40:26 +0100
+Subject: [PATCH 04/12] spi/bcm63xx: remove duplicated mode bits check
+
+The spi subsystem already checks the mode bits before calling setup.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ drivers/spi/spi-bcm63xx.c |    6 ------
+ 1 file changed, 6 deletions(-)
+
+--- a/drivers/spi/spi-bcm63xx.c
++++ b/drivers/spi/spi-bcm63xx.c
+@@ -158,12 +158,6 @@ static int bcm63xx_spi_setup(struct spi_
+       if (!spi->bits_per_word)
+               spi->bits_per_word = 8;
+-      if (spi->mode & ~MODEBITS) {
+-              dev_err(&spi->dev, "%s, unsupported mode bits %x\n",
+-                      __func__, spi->mode & ~MODEBITS);
+-              return -EINVAL;
+-      }
+-
+       dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
+               __func__, spi->mode & MODEBITS, spi->bits_per_word, 0);
diff --git a/target/linux/brcm63xx/patches-3.9/007-spi-bcm63xx-remove-unneeded-debug-message.patch b/target/linux/brcm63xx/patches-3.9/007-spi-bcm63xx-remove-unneeded-debug-message.patch
new file mode 100644 (file)
index 0000000..a7fae94
--- /dev/null
@@ -0,0 +1,26 @@
+From ee18b0ac561afb9dd7d87a4217e80151a7e29dfc Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Mon, 11 Mar 2013 13:42:22 +0100
+Subject: [PATCH 05/12] spi/bcm63xx: remove unneeded debug message
+
+The spi subsystem already provides this info in a more extensive
+debug print except for the nsecs/bit - which wasn't calculated anyway
+and fixed to 0.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ drivers/spi/spi-bcm63xx.c |    3 ---
+ 1 file changed, 3 deletions(-)
+
+--- a/drivers/spi/spi-bcm63xx.c
++++ b/drivers/spi/spi-bcm63xx.c
+@@ -158,9 +158,6 @@ static int bcm63xx_spi_setup(struct spi_
+       if (!spi->bits_per_word)
+               spi->bits_per_word = 8;
+-      dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
+-              __func__, spi->mode & MODEBITS, spi->bits_per_word, 0);
+-
+       return 0;
+ }
diff --git a/target/linux/brcm63xx/patches-3.9/008-spi-bcm63xx-remove-unused-variable-bs-from-bcm63xx_s.patch b/target/linux/brcm63xx/patches-3.9/008-spi-bcm63xx-remove-unused-variable-bs-from-bcm63xx_s.patch
new file mode 100644 (file)
index 0000000..81ea919
--- /dev/null
@@ -0,0 +1,26 @@
+From 30151fe21befa84d9cd27d63f1bf3973988c811e Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Mon, 11 Mar 2013 13:47:19 +0100
+Subject: [PATCH 06/12] spi/bcm63xx: remove unused variable bs from
+ bcm63xx_spi_setup
+
+It is only written, but never read.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ drivers/spi/spi-bcm63xx.c |    4 ----
+ 1 file changed, 4 deletions(-)
+
+--- a/drivers/spi/spi-bcm63xx.c
++++ b/drivers/spi/spi-bcm63xx.c
+@@ -151,10 +151,6 @@ static void bcm63xx_spi_setup_transfer(s
+ static int bcm63xx_spi_setup(struct spi_device *spi)
+ {
+-      struct bcm63xx_spi *bs;
+-
+-      bs = spi_master_get_devdata(spi->master);
+-
+       if (!spi->bits_per_word)
+               spi->bits_per_word = 8;
diff --git a/target/linux/brcm63xx/patches-3.9/009-spi-bcm63xx-check-spi-bits_per_word-in-spi_setup.patch b/target/linux/brcm63xx/patches-3.9/009-spi-bcm63xx-check-spi-bits_per_word-in-spi_setup.patch
new file mode 100644 (file)
index 0000000..49a7ac2
--- /dev/null
@@ -0,0 +1,29 @@
+From 13a364be644ed9b4666d452756556bb98afdcc56 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Mon, 11 Mar 2013 13:48:27 +0100
+Subject: [PATCH 07/12] spi/bcm63xx: check spi bits_per_word in spi_setup
+
+Instead of fixing up the bits_per_word (which the spi subsystem already
+does for us), check it for supported values.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ drivers/spi/spi-bcm63xx.c |    7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+--- a/drivers/spi/spi-bcm63xx.c
++++ b/drivers/spi/spi-bcm63xx.c
+@@ -151,8 +151,11 @@ static void bcm63xx_spi_setup_transfer(s
+ static int bcm63xx_spi_setup(struct spi_device *spi)
+ {
+-      if (!spi->bits_per_word)
+-              spi->bits_per_word = 8;
++      if (spi->bits_per_word != 8) {
++              dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
++                      __func__, spi->bits_per_word);
++              return -EINVAL;
++      }
+       return 0;
+ }
diff --git a/target/linux/brcm63xx/patches-3.9/010-spi-bcm63xx-simplify-bcm63xx_spi_check_transfer.patch b/target/linux/brcm63xx/patches-3.9/010-spi-bcm63xx-simplify-bcm63xx_spi_check_transfer.patch
new file mode 100644 (file)
index 0000000..57c1e46
--- /dev/null
@@ -0,0 +1,30 @@
+From d69ac73da38f0d16cc6b4524cd734b907db6eab8 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Mon, 11 Mar 2013 13:51:10 +0100
+Subject: [PATCH 08/12] spi/bcm63xx: simplify bcm63xx_spi_check_transfer
+
+bcm63xx_spi_check_transfer is only called from one place that has
+t always set, so directly check the transfer's bits_per_word.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ drivers/spi/spi-bcm63xx.c |    7 ++-----
+ 1 file changed, 2 insertions(+), 5 deletions(-)
+
+--- a/drivers/spi/spi-bcm63xx.c
++++ b/drivers/spi/spi-bcm63xx.c
+@@ -96,12 +96,9 @@ static const unsigned bcm63xx_spi_freq_t
+ static int bcm63xx_spi_check_transfer(struct spi_device *spi,
+                                       struct spi_transfer *t)
+ {
+-      u8 bits_per_word;
+-
+-      bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
+-      if (bits_per_word != 8) {
++      if (t->bits_per_word != 8) {
+               dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
+-                      __func__, bits_per_word);
++                      __func__, t->bits_per_word);
+               return -EINVAL;
+       }
diff --git a/target/linux/brcm63xx/patches-3.9/011-spi-bcm63xx-remove-spi-chip-select-validity-check.patch b/target/linux/brcm63xx/patches-3.9/011-spi-bcm63xx-remove-spi-chip-select-validity-check.patch
new file mode 100644 (file)
index 0000000..4f1a1cc
--- /dev/null
@@ -0,0 +1,28 @@
+From 9c5a988562468823a5e2973f04134a8bd97e7718 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Mon, 11 Mar 2013 13:53:16 +0100
+Subject: [PATCH 09/12] spi/bcm63xx: remove spi chip select validity check
+
+The check would belong in bcm63xx_spi_setup if the spi subsystem
+weren't already doing the check for us, so just drop it.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ drivers/spi/spi-bcm63xx.c |    6 ------
+ 1 file changed, 6 deletions(-)
+
+--- a/drivers/spi/spi-bcm63xx.c
++++ b/drivers/spi/spi-bcm63xx.c
+@@ -102,12 +102,6 @@ static int bcm63xx_spi_check_transfer(st
+               return -EINVAL;
+       }
+-      if (spi->chip_select > spi->master->num_chipselect) {
+-              dev_err(&spi->dev, "%s, unsupported slave %d\n",
+-                      __func__, spi->chip_select);
+-              return -EINVAL;
+-      }
+-
+       return 0;
+ }
diff --git a/target/linux/brcm63xx/patches-3.9/012-spi-bcm63xx-inline-bcm63xx_spi_check_transfer.patch b/target/linux/brcm63xx/patches-3.9/012-spi-bcm63xx-inline-bcm63xx_spi_check_transfer.patch
new file mode 100644 (file)
index 0000000..f684d83
--- /dev/null
@@ -0,0 +1,48 @@
+From 3fffc5f76c830c375692a67948734168ee4c516a Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Mon, 11 Mar 2013 13:59:30 +0100
+Subject: [PATCH 10/12] spi/bcm63xx: inline bcm63xx_spi_check_transfer
+
+It only does one check, so just do the check directly in the caller.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ drivers/spi/spi-bcm63xx.c |   19 +++++--------------
+ 1 file changed, 5 insertions(+), 14 deletions(-)
+
+--- a/drivers/spi/spi-bcm63xx.c
++++ b/drivers/spi/spi-bcm63xx.c
+@@ -93,18 +93,6 @@ static const unsigned bcm63xx_spi_freq_t
+       {   391000, SPI_CLK_0_391MHZ }
+ };
+-static int bcm63xx_spi_check_transfer(struct spi_device *spi,
+-                                      struct spi_transfer *t)
+-{
+-      if (t->bits_per_word != 8) {
+-              dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
+-                      __func__, t->bits_per_word);
+-              return -EINVAL;
+-      }
+-
+-      return 0;
+-}
+-
+ static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
+                                     struct spi_transfer *t)
+ {
+@@ -293,9 +281,12 @@ static int bcm63xx_spi_transfer_one(stru
+        * full-duplex transfers.
+        */
+       list_for_each_entry(t, &m->transfers, transfer_list) {
+-              status = bcm63xx_spi_check_transfer(spi, t);
+-              if (status < 0)
++              if (t->bits_per_word != 8) {
++                      dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
++                              __func__, t->bits_per_word);
++                      status = -EINVAL;
+                       goto exit;
++              }
+               if (!first)
+                       first = t;
diff --git a/target/linux/brcm63xx/patches-3.9/013-spi-bcm63xx-inline-hz-usage-in-bcm63xx_spi_setup_tra.patch b/target/linux/brcm63xx/patches-3.9/013-spi-bcm63xx-inline-hz-usage-in-bcm63xx_spi_setup_tra.patch
new file mode 100644 (file)
index 0000000..fba37d5
--- /dev/null
@@ -0,0 +1,43 @@
+From 2646be877afc663d1688a2add8386b027c9d7e31 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Mon, 11 Mar 2013 14:08:06 +0100
+Subject: [PATCH 11/12] spi/bcm63xx: inline hz usage in
+ bcm63xx_spi_setup_transfer
+
+bcm63xx_spi_setup_transfer is called from only one place, and that has
+t always set, to hz will always be t->speed_hz - just use it directly in
+the two places instead of moving it in a local variable.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ drivers/spi/spi-bcm63xx.c |    7 ++-----
+ 1 file changed, 2 insertions(+), 5 deletions(-)
+
+--- a/drivers/spi/spi-bcm63xx.c
++++ b/drivers/spi/spi-bcm63xx.c
+@@ -97,15 +97,12 @@ static void bcm63xx_spi_setup_transfer(s
+                                     struct spi_transfer *t)
+ {
+       struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
+-      u32 hz;
+       u8 clk_cfg, reg;
+       int i;
+-      hz = (t) ? t->speed_hz : spi->max_speed_hz;
+-
+       /* Find the closest clock configuration */
+       for (i = 0; i < SPI_CLK_MASK; i++) {
+-              if (hz >= bcm63xx_spi_freq_table[i][0]) {
++              if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) {
+                       clk_cfg = bcm63xx_spi_freq_table[i][1];
+                       break;
+               }
+@@ -122,7 +119,7 @@ static void bcm63xx_spi_setup_transfer(s
+       bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
+       dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
+-              clk_cfg, hz);
++              clk_cfg, t->speed_hz);
+ }
+ /* the spi->mode bits understood by this driver: */
diff --git a/target/linux/brcm63xx/patches-3.9/014-spi-bcm63xx-use-devm_ioremap_resource.patch b/target/linux/brcm63xx/patches-3.9/014-spi-bcm63xx-use-devm_ioremap_resource.patch
new file mode 100644 (file)
index 0000000..82fbe6c
--- /dev/null
@@ -0,0 +1,36 @@
+From 95af2d7751d31ea07b7a0d8ec7030f6c62df0ae2 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Mon, 11 Mar 2013 14:20:33 +0100
+Subject: [PATCH 12/12] spi/bcm63xx: use devm_ioremap_resource()
+
+Use devm_ioremap_resource() which provides its own error messages.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ drivers/spi/spi-bcm63xx.c |   15 +++------------
+ 1 file changed, 3 insertions(+), 12 deletions(-)
+
+--- a/drivers/spi/spi-bcm63xx.c
++++ b/drivers/spi/spi-bcm63xx.c
+@@ -412,18 +412,9 @@ static int bcm63xx_spi_probe(struct plat
+       platform_set_drvdata(pdev, master);
+       bs->pdev = pdev;
+-      if (!devm_request_mem_region(&pdev->dev, r->start,
+-                                      resource_size(r), PFX)) {
+-              dev_err(dev, "iomem request failed\n");
+-              ret = -ENXIO;
+-              goto out_err;
+-      }
+-
+-      bs->regs = devm_ioremap_nocache(&pdev->dev, r->start,
+-                                                      resource_size(r));
+-      if (!bs->regs) {
+-              dev_err(dev, "unable to ioremap regs\n");
+-              ret = -ENOMEM;
++      bs->regs = devm_ioremap_resource(&pdev->dev, r);
++      if (IS_ERR(bs->regs)) {
++              ret = PTR_ERR(bs->regs);
+               goto out_err;
+       }
diff --git a/target/linux/brcm63xx/patches-3.9/015-spi-bcm63xx-remove-unused-speed_hz-member-variable.patch b/target/linux/brcm63xx/patches-3.9/015-spi-bcm63xx-remove-unused-speed_hz-member-variable.patch
new file mode 100644 (file)
index 0000000..d7b9327
--- /dev/null
@@ -0,0 +1,67 @@
+From 5ff6b05a18295fa7e03de0fdf32d681a90b69df5 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Sat, 30 Mar 2013 10:26:55 +0100
+Subject: [PATCH] spi/bcm63xx: remove unused speed_hz member variable
+
+speed_hz is a write only member, so we can safely remove it and its
+generation. Also fixes the missing clk_put after getting the periph
+clock.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/dev-spi.c                          |   11 -----------
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h |    1 -
+ drivers/spi/spi-bcm63xx.c                            |    2 --
+ 3 files changed, 14 deletions(-)
+
+--- a/arch/mips/bcm63xx/dev-spi.c
++++ b/arch/mips/bcm63xx/dev-spi.c
+@@ -85,20 +85,9 @@ static struct platform_device bcm63xx_sp
+ int __init bcm63xx_spi_register(void)
+ {
+-      struct clk *periph_clk;
+-
+       if (BCMCPU_IS_6328() || BCMCPU_IS_6345())
+               return -ENODEV;
+-      periph_clk = clk_get(NULL, "periph");
+-      if (IS_ERR(periph_clk)) {
+-              pr_err("unable to get periph clock\n");
+-              return -ENODEV;
+-      }
+-
+-      /* Set bus frequency */
+-      spi_pdata.speed_hz = clk_get_rate(periph_clk);
+-
+       spi_resources[0].start = bcm63xx_regset_address(RSET_SPI);
+       spi_resources[0].end = spi_resources[0].start;
+       spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI);
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
+@@ -13,7 +13,6 @@ struct bcm63xx_spi_pdata {
+       unsigned int    msg_ctl_width;
+       int             bus_num;
+       int             num_chipselect;
+-      u32             speed_hz;
+ };
+ enum bcm63xx_regs_spi {
+--- a/drivers/spi/spi-bcm63xx.c
++++ b/drivers/spi/spi-bcm63xx.c
+@@ -46,7 +46,6 @@ struct bcm63xx_spi {
+       int                     irq;
+       /* Platform data */
+-      u32                     speed_hz;
+       unsigned                fifo_size;
+       unsigned int            msg_type_shift;
+       unsigned int            msg_ctl_width;
+@@ -436,7 +435,6 @@ static int bcm63xx_spi_probe(struct plat
+       master->unprepare_transfer_hardware = bcm63xx_spi_unprepare_transfer;
+       master->transfer_one_message = bcm63xx_spi_transfer_one;
+       master->mode_bits = MODEBITS;
+-      bs->speed_hz = pdata->speed_hz;
+       bs->msg_type_shift = pdata->msg_type_shift;
+       bs->msg_ctl_width = pdata->msg_ctl_width;
+       bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
diff --git a/target/linux/brcm63xx/patches-3.9/018-MIPS-BCM63XX-merge-bcm63xx_clk.h-into-bcm63xx-clk.c.patch b/target/linux/brcm63xx/patches-3.9/018-MIPS-BCM63XX-merge-bcm63xx_clk.h-into-bcm63xx-clk.c.patch
new file mode 100644 (file)
index 0000000..c3dedb4
--- /dev/null
@@ -0,0 +1,57 @@
+From 715d03e5409fac9cbe76fd802db49ca15158378f Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Sat, 30 Mar 2013 20:31:48 +0100
+Subject: [PATCH] MIPS: BCM63XX: merge bcm63xx_clk.h into bcm63xx/clk.c
+
+All the header file does is provide the internal structure of clk,
+which shouldn't be used by anyone except clk.c itself anyway.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/clk.c                          |    8 +++++++-
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_clk.h |   11 -----------
+ drivers/tty/serial/bcm63xx_uart.c                |    1 -
+ 3 files changed, 7 insertions(+), 13 deletions(-)
+ delete mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_clk.h
+
+--- a/arch/mips/bcm63xx/clk.c
++++ b/arch/mips/bcm63xx/clk.c
+@@ -15,7 +15,13 @@
+ #include <bcm63xx_io.h>
+ #include <bcm63xx_regs.h>
+ #include <bcm63xx_reset.h>
+-#include <bcm63xx_clk.h>
++
++struct clk {
++      void            (*set)(struct clk *, int);
++      unsigned int    rate;
++      unsigned int    usage;
++      int             id;
++};
+ static DEFINE_MUTEX(clocks_mutex);
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_clk.h
++++ /dev/null
+@@ -1,11 +0,0 @@
+-#ifndef BCM63XX_CLK_H_
+-#define BCM63XX_CLK_H_
+-
+-struct clk {
+-      void            (*set)(struct clk *, int);
+-      unsigned int    rate;
+-      unsigned int    usage;
+-      int             id;
+-};
+-
+-#endif /* ! BCM63XX_CLK_H_ */
+--- a/drivers/tty/serial/bcm63xx_uart.c
++++ b/drivers/tty/serial/bcm63xx_uart.c
+@@ -30,7 +30,6 @@
+ #include <linux/serial.h>
+ #include <linux/serial_core.h>
+-#include <bcm63xx_clk.h>
+ #include <bcm63xx_irq.h>
+ #include <bcm63xx_regs.h>
+ #include <bcm63xx_io.h>
diff --git a/target/linux/brcm63xx/patches-3.9/019-bcm63xx_enet-use-managed-io-memory-allocations.patch b/target/linux/brcm63xx/patches-3.9/019-bcm63xx_enet-use-managed-io-memory-allocations.patch
new file mode 100644 (file)
index 0000000..5d0fb8e
--- /dev/null
@@ -0,0 +1,118 @@
+From 80b0356aea30e9fc9e075d31c2bf37e7cbfea8c9 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Sun, 10 Mar 2013 13:59:55 +0100
+Subject: [PATCH 1/3] bcm63xx_enet: use managed io memory allocations
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ drivers/net/ethernet/broadcom/bcm63xx_enet.c |   43 +++++---------------------
+ 1 file changed, 7 insertions(+), 36 deletions(-)
+
+--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+@@ -1619,7 +1619,6 @@ static int bcm_enet_probe(struct platfor
+       struct resource *res_mem, *res_irq, *res_irq_rx, *res_irq_tx;
+       struct mii_bus *bus;
+       const char *clk_name;
+-      unsigned int iomem_size;
+       int i, ret;
+       /* stop if shared driver failed, assume driver->probe will be
+@@ -1644,17 +1643,12 @@ static int bcm_enet_probe(struct platfor
+       if (ret)
+               goto out;
+-      iomem_size = resource_size(res_mem);
+-      if (!request_mem_region(res_mem->start, iomem_size, "bcm63xx_enet")) {
+-              ret = -EBUSY;
+-              goto out;
+-      }
+-
+-      priv->base = ioremap(res_mem->start, iomem_size);
++      priv->base = devm_request_and_ioremap(&pdev->dev, res_mem);
+       if (priv->base == NULL) {
+               ret = -ENOMEM;
+-              goto out_release_mem;
++              goto out;
+       }
++
+       dev->irq = priv->irq = res_irq->start;
+       priv->irq_rx = res_irq_rx->start;
+       priv->irq_tx = res_irq_tx->start;
+@@ -1674,7 +1668,7 @@ static int bcm_enet_probe(struct platfor
+       priv->mac_clk = clk_get(&pdev->dev, clk_name);
+       if (IS_ERR(priv->mac_clk)) {
+               ret = PTR_ERR(priv->mac_clk);
+-              goto out_unmap;
++              goto out;
+       }
+       clk_enable(priv->mac_clk);
+@@ -1814,12 +1808,6 @@ out_uninit_hw:
+ out_put_clk_mac:
+       clk_disable(priv->mac_clk);
+       clk_put(priv->mac_clk);
+-
+-out_unmap:
+-      iounmap(priv->base);
+-
+-out_release_mem:
+-      release_mem_region(res_mem->start, iomem_size);
+ out:
+       free_netdev(dev);
+       return ret;
+@@ -1833,7 +1821,6 @@ static int bcm_enet_remove(struct platfo
+ {
+       struct bcm_enet_priv *priv;
+       struct net_device *dev;
+-      struct resource *res;
+       /* stop netdevice */
+       dev = platform_get_drvdata(pdev);
+@@ -1856,11 +1843,6 @@ static int bcm_enet_remove(struct platfo
+                                      bcm_enet_mdio_write_mii);
+       }
+-      /* release device resources */
+-      iounmap(priv->base);
+-      res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+-      release_mem_region(res->start, resource_size(res));
+-
+       /* disable hw block clocks */
+       if (priv->phy_clk) {
+               clk_disable(priv->phy_clk);
+@@ -1889,31 +1871,20 @@ struct platform_driver bcm63xx_enet_driv
+ static int bcm_enet_shared_probe(struct platform_device *pdev)
+ {
+       struct resource *res;
+-      unsigned int iomem_size;
+       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       if (!res)
+               return -ENODEV;
+-      iomem_size = resource_size(res);
+-      if (!request_mem_region(res->start, iomem_size, "bcm63xx_enet_dma"))
+-              return -EBUSY;
+-
+-      bcm_enet_shared_base = ioremap(res->start, iomem_size);
+-      if (!bcm_enet_shared_base) {
+-              release_mem_region(res->start, iomem_size);
++      bcm_enet_shared_base = devm_request_and_ioremap(&pdev->dev, res);
++      if (!bcm_enet_shared_base)
+               return -ENOMEM;
+-      }
++
+       return 0;
+ }
+ static int bcm_enet_shared_remove(struct platform_device *pdev)
+ {
+-      struct resource *res;
+-
+-      iounmap(bcm_enet_shared_base);
+-      res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+-      release_mem_region(res->start, resource_size(res));
+       return 0;
+ }
diff --git a/target/linux/brcm63xx/patches-3.9/020-bcm63xx_enet-use-managed-memory-allocations.patch b/target/linux/brcm63xx/patches-3.9/020-bcm63xx_enet-use-managed-memory-allocations.patch
new file mode 100644 (file)
index 0000000..d121fce
--- /dev/null
@@ -0,0 +1,42 @@
+From 451a609ca472f80838df056689359c5486d832c1 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Sun, 10 Mar 2013 14:05:01 +0100
+Subject: [PATCH 2/3] bcm63xx_enet: use managed memory allocations
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ drivers/net/ethernet/broadcom/bcm63xx_enet.c |    8 +++-----
+ 1 file changed, 3 insertions(+), 5 deletions(-)
+
+--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+@@ -1727,7 +1727,8 @@ static int bcm_enet_probe(struct platfor
+                * if a slave is not present on hw */
+               bus->phy_mask = ~(1 << priv->phy_id);
+-              bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
++              bus->irq = devm_kzalloc(&pdev->dev, sizeof(int) * PHY_MAX_ADDR,
++                                      GFP_KERNEL);
+               if (!bus->irq) {
+                       ret = -ENOMEM;
+                       goto out_free_mdio;
+@@ -1788,10 +1789,8 @@ static int bcm_enet_probe(struct platfor
+       return 0;
+ out_unregister_mdio:
+-      if (priv->mii_bus) {
++      if (priv->mii_bus)
+               mdiobus_unregister(priv->mii_bus);
+-              kfree(priv->mii_bus->irq);
+-      }
+ out_free_mdio:
+       if (priv->mii_bus)
+@@ -1832,7 +1831,6 @@ static int bcm_enet_remove(struct platfo
+       if (priv->has_phy) {
+               mdiobus_unregister(priv->mii_bus);
+-              kfree(priv->mii_bus->irq);
+               mdiobus_free(priv->mii_bus);
+       } else {
+               struct bcm63xx_enet_platform_data *pd;
diff --git a/target/linux/brcm63xx/patches-3.9/021-bcm63xx_enet-properly-prepare-unprepare-clocks-befor.patch b/target/linux/brcm63xx/patches-3.9/021-bcm63xx_enet-properly-prepare-unprepare-clocks-befor.patch
new file mode 100644 (file)
index 0000000..5f05685
--- /dev/null
@@ -0,0 +1,62 @@
+From 8d6b746129f11efe4ba69aeb2c982359d33c6ec3 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Mon, 10 Sep 2012 01:28:47 +0200
+Subject: [PATCH 3/3] bcm63xx_enet: properly prepare/unprepare clocks
+ before/after usage
+
+Use clk_prepare_enable/disable_unprepare calls in preparation for
+switching to the generic clock framework.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ drivers/net/ethernet/broadcom/bcm63xx_enet.c |   12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+@@ -1670,7 +1670,7 @@ static int bcm_enet_probe(struct platfor
+               ret = PTR_ERR(priv->mac_clk);
+               goto out;
+       }
+-      clk_enable(priv->mac_clk);
++      clk_prepare_enable(priv->mac_clk);
+       /* initialize default and fetch platform data */
+       priv->rx_ring_size = BCMENET_DEF_RX_DESC;
+@@ -1699,7 +1699,7 @@ static int bcm_enet_probe(struct platfor
+                       priv->phy_clk = NULL;
+                       goto out_put_clk_mac;
+               }
+-              clk_enable(priv->phy_clk);
++              clk_prepare_enable(priv->phy_clk);
+       }
+       /* do minimal hardware init to be able to probe mii bus */
+@@ -1800,12 +1800,12 @@ out_uninit_hw:
+       /* turn off mdc clock */
+       enet_writel(priv, 0, ENET_MIISC_REG);
+       if (priv->phy_clk) {
+-              clk_disable(priv->phy_clk);
++              clk_disable_unprepare(priv->phy_clk);
+               clk_put(priv->phy_clk);
+       }
+ out_put_clk_mac:
+-      clk_disable(priv->mac_clk);
++      clk_disable_unprepare(priv->mac_clk);
+       clk_put(priv->mac_clk);
+ out:
+       free_netdev(dev);
+@@ -1843,10 +1843,10 @@ static int bcm_enet_remove(struct platfo
+       /* disable hw block clocks */
+       if (priv->phy_clk) {
+-              clk_disable(priv->phy_clk);
++              clk_disable_unprepare(priv->phy_clk);
+               clk_put(priv->phy_clk);
+       }
+-      clk_disable(priv->mac_clk);
++      clk_disable_unprepare(priv->mac_clk);
+       clk_put(priv->mac_clk);
+       platform_set_drvdata(pdev, NULL);
diff --git a/target/linux/brcm63xx/patches-3.9/022-MIPS-BCM63XX-remove-duplicate-spi-register-definitio.patch b/target/linux/brcm63xx/patches-3.9/022-MIPS-BCM63XX-remove-duplicate-spi-register-definitio.patch
new file mode 100644 (file)
index 0000000..50bbb93
--- /dev/null
@@ -0,0 +1,166 @@
+From e1a3ace7260fad338a76595b116a6bf5b5627aa2 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Thu, 7 Mar 2013 12:20:10 +0100
+Subject: [PATCH 1/7] MIPS: BCM63XX: remove duplicate spi register definitions
+
+BCM6338 and BCM6348, and BCM6358 and everything after that share the
+same register layout. To not have to redefine them for each new chip
+and keep the code size small, only use the definitions for the first
+chip with the certain layout.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/dev-spi.c                        |   24 +++---------
+ .../include/asm/mach-bcm63xx/bcm63xx_dev_spi.h     |   10 +----
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h  |   40 +-------------------
+ 3 files changed, 10 insertions(+), 64 deletions(-)
+
+--- a/arch/mips/bcm63xx/dev-spi.c
++++ b/arch/mips/bcm63xx/dev-spi.c
+@@ -22,10 +22,6 @@
+ /*
+  * register offsets
+  */
+-static const unsigned long bcm6338_regs_spi[] = {
+-      __GEN_SPI_REGS_TABLE(6338)
+-};
+-
+ static const unsigned long bcm6348_regs_spi[] = {
+       __GEN_SPI_REGS_TABLE(6348)
+ };
+@@ -34,23 +30,15 @@ static const unsigned long bcm6358_regs_
+       __GEN_SPI_REGS_TABLE(6358)
+ };
+-static const unsigned long bcm6368_regs_spi[] = {
+-      __GEN_SPI_REGS_TABLE(6368)
+-};
+-
+ const unsigned long *bcm63xx_regs_spi;
+ EXPORT_SYMBOL(bcm63xx_regs_spi);
+ static __init void bcm63xx_spi_regs_init(void)
+ {
+-      if (BCMCPU_IS_6338())
+-              bcm63xx_regs_spi = bcm6338_regs_spi;
+-      if (BCMCPU_IS_6348())
++      if (BCMCPU_IS_6338() || BCMCPU_IS_6348())
+               bcm63xx_regs_spi = bcm6348_regs_spi;
+-      if (BCMCPU_IS_6358())
++      if (BCMCPU_IS_6358() || BCMCPU_IS_6368())
+               bcm63xx_regs_spi = bcm6358_regs_spi;
+-      if (BCMCPU_IS_6368())
+-              bcm63xx_regs_spi = bcm6368_regs_spi;
+ }
+ #else
+ static __init void bcm63xx_spi_regs_init(void) { }
+@@ -93,10 +81,10 @@ int __init bcm63xx_spi_register(void)
+       spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI);
+       if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
+-              spi_resources[0].end += BCM_6338_RSET_SPI_SIZE - 1;
+-              spi_pdata.fifo_size = SPI_6338_MSG_DATA_SIZE;
+-              spi_pdata.msg_type_shift = SPI_6338_MSG_TYPE_SHIFT;
+-              spi_pdata.msg_ctl_width = SPI_6338_MSG_CTL_WIDTH;
++              spi_resources[0].end += BCM_6348_RSET_SPI_SIZE - 1;
++              spi_pdata.fifo_size = SPI_6348_MSG_DATA_SIZE;
++              spi_pdata.msg_type_shift = SPI_6348_MSG_TYPE_SHIFT;
++              spi_pdata.msg_ctl_width = SPI_6348_MSG_CTL_WIDTH;
+       }
+       if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
+@@ -71,18 +71,12 @@ static inline unsigned long bcm63xx_spir
+       return bcm63xx_regs_spi[reg];
+ #else
+-#ifdef CONFIG_BCM63XX_CPU_6338
+-      __GEN_SPI_RSET(6338)
+-#endif
+-#ifdef CONFIG_BCM63XX_CPU_6348
++#if defined(CONFIG_BCM63XX_CPU_6338) || defined(CONFIG_BCM63XX_CPU_6348)
+       __GEN_SPI_RSET(6348)
+ #endif
+-#ifdef CONFIG_BCM63XX_CPU_6358
++#if defined(CONFIG_BCM63XX_CPU_6358) || defined(CONFIG_BCM63XX_CPU_6368)
+       __GEN_SPI_RSET(6358)
+ #endif
+-#ifdef CONFIG_BCM63XX_CPU_6368
+-      __GEN_SPI_RSET(6368)
+-#endif
+ #endif
+       return 0;
+ }
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -1223,24 +1223,7 @@
+  * _REG relative to RSET_SPI
+  *************************************************************************/
+-/* BCM 6338 SPI core */
+-#define SPI_6338_CMD                  0x00    /* 16-bits register */
+-#define SPI_6338_INT_STATUS           0x02
+-#define SPI_6338_INT_MASK_ST          0x03
+-#define SPI_6338_INT_MASK             0x04
+-#define SPI_6338_ST                   0x05
+-#define SPI_6338_CLK_CFG              0x06
+-#define SPI_6338_FILL_BYTE            0x07
+-#define SPI_6338_MSG_TAIL             0x09
+-#define SPI_6338_RX_TAIL              0x0b
+-#define SPI_6338_MSG_CTL              0x40    /* 8-bits register */
+-#define SPI_6338_MSG_CTL_WIDTH                8
+-#define SPI_6338_MSG_DATA             0x41
+-#define SPI_6338_MSG_DATA_SIZE                0x3f
+-#define SPI_6338_RX_DATA              0x80
+-#define SPI_6338_RX_DATA_SIZE         0x3f
+-
+-/* BCM 6348 SPI core */
++/* BCM 6338/6348 SPI core */
+ #define SPI_6348_CMD                  0x00    /* 16-bits register */
+ #define SPI_6348_INT_STATUS           0x02
+ #define SPI_6348_INT_MASK_ST          0x03
+@@ -1257,7 +1240,7 @@
+ #define SPI_6348_RX_DATA              0x80
+ #define SPI_6348_RX_DATA_SIZE         0x3f
+-/* BCM 6358 SPI core */
++/* BCM 6358/6368 SPI core */
+ #define SPI_6358_MSG_CTL              0x00    /* 16-bits register */
+ #define SPI_6358_MSG_CTL_WIDTH                16
+ #define SPI_6358_MSG_DATA             0x02
+@@ -1274,23 +1257,6 @@
+ #define SPI_6358_MSG_TAIL             0x709
+ #define SPI_6358_RX_TAIL              0x70B
+-/* BCM 6358 SPI core */
+-#define SPI_6368_MSG_CTL              0x00    /* 16-bits register */
+-#define SPI_6368_MSG_CTL_WIDTH                16
+-#define SPI_6368_MSG_DATA             0x02
+-#define SPI_6368_MSG_DATA_SIZE                0x21e
+-#define SPI_6368_RX_DATA              0x400
+-#define SPI_6368_RX_DATA_SIZE         0x220
+-#define SPI_6368_CMD                  0x700   /* 16-bits register */
+-#define SPI_6368_INT_STATUS           0x702
+-#define SPI_6368_INT_MASK_ST          0x703
+-#define SPI_6368_INT_MASK             0x704
+-#define SPI_6368_ST                   0x705
+-#define SPI_6368_CLK_CFG              0x706
+-#define SPI_6368_FILL_BYTE            0x707
+-#define SPI_6368_MSG_TAIL             0x709
+-#define SPI_6368_RX_TAIL              0x70B
+-
+ /* Shared SPI definitions */
+ /* Message configuration */
+@@ -1298,10 +1264,8 @@
+ #define SPI_HD_W                      0x01
+ #define SPI_HD_R                      0x02
+ #define SPI_BYTE_CNT_SHIFT            0
+-#define SPI_6338_MSG_TYPE_SHIFT               6
+ #define SPI_6348_MSG_TYPE_SHIFT               6
+ #define SPI_6358_MSG_TYPE_SHIFT               14
+-#define SPI_6368_MSG_TYPE_SHIFT               14
+ /* Command */
+ #define SPI_CMD_NOOP                  0x00
diff --git a/target/linux/brcm63xx/patches-3.9/023-MIPS-BCM63XX-fix-revision-ID-width.patch b/target/linux/brcm63xx/patches-3.9/023-MIPS-BCM63XX-fix-revision-ID-width.patch
new file mode 100644 (file)
index 0000000..0ee88e1
--- /dev/null
@@ -0,0 +1,68 @@
+From 609c69339a24bd034f5359dad14087276ce5a83f Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Sun, 15 Jan 2012 14:41:22 +0100
+Subject: [PATCH 2/7] MIPS: BCM63XX: fix revision ID width
+
+The REVID is only 8 bit wide.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/cpu.c                           |    4 ++--
+ arch/mips/bcm63xx/setup.c                         |    2 +-
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h  |    2 +-
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |    2 +-
+ 4 files changed, 5 insertions(+), 5 deletions(-)
+
+--- a/arch/mips/bcm63xx/cpu.c
++++ b/arch/mips/bcm63xx/cpu.c
+@@ -25,7 +25,7 @@ const int *bcm63xx_irqs;
+ EXPORT_SYMBOL(bcm63xx_irqs);
+ static u16 bcm63xx_cpu_id;
+-static u16 bcm63xx_cpu_rev;
++static u8 bcm63xx_cpu_rev;
+ static unsigned int bcm63xx_cpu_freq;
+ static unsigned int bcm63xx_memory_size;
+@@ -87,7 +87,7 @@ u16 __bcm63xx_get_cpu_id(void)
+ EXPORT_SYMBOL(__bcm63xx_get_cpu_id);
+-u16 bcm63xx_get_cpu_rev(void)
++u8 bcm63xx_get_cpu_rev(void)
+ {
+       return bcm63xx_cpu_rev;
+ }
+--- a/arch/mips/bcm63xx/setup.c
++++ b/arch/mips/bcm63xx/setup.c
+@@ -126,7 +126,7 @@ static void __bcm63xx_machine_reboot(cha
+ const char *get_system_type(void)
+ {
+       static char buf[128];
+-      snprintf(buf, sizeof(buf), "bcm63xx/%s (0x%04x/0x%04X)",
++      snprintf(buf, sizeof(buf), "bcm63xx/%s (0x%04x/0x%02X)",
+                board_get_name(),
+                bcm63xx_get_cpu_id(), bcm63xx_get_cpu_rev());
+       return buf;
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+@@ -18,7 +18,7 @@
+ void __init bcm63xx_cpu_init(void);
+ u16 __bcm63xx_get_cpu_id(void);
+-u16 bcm63xx_get_cpu_rev(void);
++u8 bcm63xx_get_cpu_rev(void);
+ unsigned int bcm63xx_get_cpu_freq(void);
+ #ifdef CONFIG_BCM63XX_CPU_6328
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -10,7 +10,7 @@
+ #define REV_CHIPID_SHIFT              16
+ #define REV_CHIPID_MASK                       (0xffff << REV_CHIPID_SHIFT)
+ #define REV_REVID_SHIFT                       0
+-#define REV_REVID_MASK                        (0xffff << REV_REVID_SHIFT)
++#define REV_REVID_MASK                        (0xff << REV_REVID_SHIFT)
+ /* Clock Control register */
+ #define PERF_CKCTL_REG                        0x4
diff --git a/target/linux/brcm63xx/patches-3.9/024-MIPS-BCM63XX-rework-chip-detection.patch b/target/linux/brcm63xx/patches-3.9/024-MIPS-BCM63XX-rework-chip-detection.patch
new file mode 100644 (file)
index 0000000..0ff9edf
--- /dev/null
@@ -0,0 +1,133 @@
+From 3f4570c9794fcae1cf62fbf3266a2e23edac67a5 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Wed, 27 Jun 2012 15:01:09 +0200
+Subject: [PATCH 3/7] MIPS: BCM63XX: rework chip detection
+
+Instead of trying to use a correlation of cpu prid and chip id and
+hoping they will always be unique, use the cpu prid to determine the
+chip id register location and just read out the chip id.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/cpu.c |   87 +++++++++++++++++++++++------------------------
+ 1 file changed, 42 insertions(+), 45 deletions(-)
+
+--- a/arch/mips/bcm63xx/cpu.c
++++ b/arch/mips/bcm63xx/cpu.c
+@@ -240,53 +240,27 @@ static unsigned int detect_memory_size(v
+ void __init bcm63xx_cpu_init(void)
+ {
+-      unsigned int tmp, expected_cpu_id;
++      unsigned int tmp;
+       struct cpuinfo_mips *c = &current_cpu_data;
+       unsigned int cpu = smp_processor_id();
++      u32 chipid_reg;
+       /* soc registers location depends on cpu type */
+-      expected_cpu_id = 0;
++      chipid_reg = 0;
+       switch (c->cputype) {
+       case CPU_BMIPS3300:
+-              if ((read_c0_prid() & 0xff00) == PRID_IMP_BMIPS3300_ALT) {
+-                      expected_cpu_id = BCM6348_CPU_ID;
+-                      bcm63xx_regs_base = bcm6348_regs_base;
+-                      bcm63xx_irqs = bcm6348_irqs;
+-              } else {
++              if ((read_c0_prid() & 0xff00) != PRID_IMP_BMIPS3300_ALT)
+                       __cpu_name[cpu] = "Broadcom BCM6338";
+-                      expected_cpu_id = BCM6338_CPU_ID;
+-                      bcm63xx_regs_base = bcm6338_regs_base;
+-                      bcm63xx_irqs = bcm6338_irqs;
+-              }
+-              break;
++              /* fall-through */
+       case CPU_BMIPS32:
+-              expected_cpu_id = BCM6345_CPU_ID;
+-              bcm63xx_regs_base = bcm6345_regs_base;
+-              bcm63xx_irqs = bcm6345_irqs;
++              chipid_reg = BCM_6345_PERF_BASE;
+               break;
+       case CPU_BMIPS4350:
+-              if ((read_c0_prid() & 0xf0) == 0x10) {
+-                      expected_cpu_id = BCM6358_CPU_ID;
+-                      bcm63xx_regs_base = bcm6358_regs_base;
+-                      bcm63xx_irqs = bcm6358_irqs;
+-              } else {
+-                      /* all newer chips have the same chip id location */
+-                      u16 chip_id = bcm_readw(BCM_6368_PERF_BASE);
+-
+-                      switch (chip_id) {
+-                      case BCM6328_CPU_ID:
+-                              expected_cpu_id = BCM6328_CPU_ID;
+-                              bcm63xx_regs_base = bcm6328_regs_base;
+-                              bcm63xx_irqs = bcm6328_irqs;
+-                              break;
+-                      case BCM6368_CPU_ID:
+-                              expected_cpu_id = BCM6368_CPU_ID;
+-                              bcm63xx_regs_base = bcm6368_regs_base;
+-                              bcm63xx_irqs = bcm6368_irqs;
+-                              break;
+-                      }
+-              }
++              if ((read_c0_prid() & 0xf0) == 0x10)
++                      chipid_reg = BCM_6345_PERF_BASE;
++              else
++                      chipid_reg = BCM_6368_PERF_BASE;
+               break;
+       }
+@@ -294,20 +268,43 @@ void __init bcm63xx_cpu_init(void)
+        * really early to panic, but delaying panic would not help since we
+        * will never get any working console
+        */
+-      if (!expected_cpu_id)
++      if (!chipid_reg)
+               panic("unsupported Broadcom CPU");
+-      /*
+-       * bcm63xx_regs_base is set, we can access soc registers
+-       */
+-
+-      /* double check CPU type */
+-      tmp = bcm_perf_readl(PERF_REV_REG);
++      /* read out CPU type */
++      tmp = bcm_readl(chipid_reg);
+       bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
+       bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
+-      if (bcm63xx_cpu_id != expected_cpu_id)
+-              panic("bcm63xx CPU id mismatch");
++      switch (bcm63xx_cpu_id) {
++      case BCM6328_CPU_ID:
++              bcm63xx_regs_base = bcm6328_regs_base;
++              bcm63xx_irqs = bcm6328_irqs;
++              break;
++      case BCM6338_CPU_ID:
++              bcm63xx_regs_base = bcm6338_regs_base;
++              bcm63xx_irqs = bcm6338_irqs;
++              break;
++      case BCM6345_CPU_ID:
++              bcm63xx_regs_base = bcm6345_regs_base;
++              bcm63xx_irqs = bcm6345_irqs;
++              break;
++      case BCM6348_CPU_ID:
++              bcm63xx_regs_base = bcm6348_regs_base;
++              bcm63xx_irqs = bcm6348_irqs;
++              break;
++      case BCM6358_CPU_ID:
++              bcm63xx_regs_base = bcm6358_regs_base;
++              bcm63xx_irqs = bcm6358_irqs;
++              break;
++      case BCM6368_CPU_ID:
++              bcm63xx_regs_base = bcm6368_regs_base;
++              bcm63xx_irqs = bcm6368_irqs;
++              break;
++      default:
++              panic("unsupported broadcom CPU %x", bcm63xx_cpu_id);
++              break;
++      }
+       bcm63xx_cpu_freq = detect_cpu_clock();
+       bcm63xx_memory_size = detect_memory_size();
diff --git a/target/linux/brcm63xx/patches-3.9/025-MIPS-BCM63XX-add-basic-BCM6362-support.patch b/target/linux/brcm63xx/patches-3.9/025-MIPS-BCM63XX-add-basic-BCM6362-support.patch
new file mode 100644 (file)
index 0000000..53a6497
--- /dev/null
@@ -0,0 +1,575 @@
+From 1071a9c9527d68eca4605e2eb1686609bfecf287 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Mon, 21 Nov 2011 00:48:52 +0100
+Subject: [PATCH 4/7] MIPS: BCM63XX: add basic BCM6362 support
+
+Add basic support for detecting and booting the BCM6362.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/Kconfig                         |    4 +
+ arch/mips/bcm63xx/boards/board_bcm963xx.c         |    6 +-
+ arch/mips/bcm63xx/cpu.c                           |   51 +++++++-
+ arch/mips/bcm63xx/irq.c                           |   22 ++++
+ arch/mips/bcm63xx/prom.c                          |    2 +
+ arch/mips/bcm63xx/reset.c                         |   28 +++++
+ arch/mips/bcm63xx/setup.c                         |    3 +
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h  |  139 +++++++++++++++++++++
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h |    2 +
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |   61 ++++++++-
+ arch/mips/include/asm/mach-bcm63xx/ioremap.h      |    1 +
+ 11 files changed, 314 insertions(+), 5 deletions(-)
+
+--- a/arch/mips/bcm63xx/Kconfig
++++ b/arch/mips/bcm63xx/Kconfig
+@@ -25,6 +25,10 @@ config BCM63XX_CPU_6358
+       bool "support 6358 CPU"
+       select HW_HAS_PCI
++config BCM63XX_CPU_6362
++      bool "support 6362 CPU"
++      select HW_HAS_PCI
++
+ config BCM63XX_CPU_6368
+       bool "support 6368 CPU"
+       select HW_HAS_PCI
+--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+@@ -726,11 +726,11 @@ void __init board_prom_init(void)
+       u32 val;
+       /* read base address of boot chip select (0)
+-       * 6328 does not have MPI but boots from a fixed address
++       * 6328/6362 do not have MPI but boot from a fixed address
+        */
+-      if (BCMCPU_IS_6328())
++      if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) {
+               val = 0x18000000;
+-      else {
++      } else {
+               val = bcm_mpi_readl(MPI_CSBASE_REG(0));
+               val &= MPI_CSBASE_BASE_MASK;
+       }
+--- a/arch/mips/bcm63xx/cpu.c
++++ b/arch/mips/bcm63xx/cpu.c
+@@ -71,6 +71,15 @@ static const int bcm6358_irqs[] = {
+ };
++static const unsigned long bcm6362_regs_base[] = {
++      __GEN_CPU_REGS_TABLE(6362)
++};
++
++static const int bcm6362_irqs[] = {
++      __GEN_CPU_IRQ_TABLE(6362)
++
++};
++
+ static const unsigned long bcm6368_regs_base[] = {
+       __GEN_CPU_REGS_TABLE(6368)
+ };
+@@ -169,6 +178,42 @@ static unsigned int detect_cpu_clock(voi
+               return (16 * 1000000 * n1 * n2) / m1;
+       }
++      case BCM6362_CPU_ID:
++      {
++              unsigned int tmp, mips_pll_fcvo;
++
++              tmp = bcm_misc_readl(MISC_STRAPBUS_6362_REG);
++              mips_pll_fcvo = (tmp & STRAPBUS_6362_FCVO_MASK)
++                              >> STRAPBUS_6362_FCVO_SHIFT;
++              switch (mips_pll_fcvo) {
++              case 0x03:
++              case 0x0b:
++              case 0x13:
++              case 0x1b:
++                      return 240000000;
++              case 0x04:
++              case 0x0c:
++              case 0x14:
++              case 0x1c:
++                      return 160000000;
++              case 0x05:
++              case 0x0e:
++              case 0x16:
++              case 0x1e:
++              case 0x1f:
++                      return 400000000;
++              case 0x06:
++                      return 440000000;
++              case 0x07:
++              case 0x17:
++                      return 384000000;
++              case 0x15:
++              case 0x1d:
++                      return 200000000;
++              default:
++                      return 320000000;
++              }
++      }
+       case BCM6368_CPU_ID:
+       {
+               unsigned int tmp, p1, p2, ndiv, m1;
+@@ -205,7 +250,7 @@ static unsigned int detect_memory_size(v
+       unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
+       u32 val;
+-      if (BCMCPU_IS_6328())
++      if (BCMCPU_IS_6328() || BCMCPU_IS_6362())
+               return bcm_ddr_readl(DDR_CSEND_REG) << 24;
+       if (BCMCPU_IS_6345()) {
+@@ -297,6 +342,10 @@ void __init bcm63xx_cpu_init(void)
+               bcm63xx_regs_base = bcm6358_regs_base;
+               bcm63xx_irqs = bcm6358_irqs;
+               break;
++      case BCM6362_CPU_ID:
++              bcm63xx_regs_base = bcm6362_regs_base;
++              bcm63xx_irqs = bcm6362_irqs;
++              break;
+       case BCM6368_CPU_ID:
+               bcm63xx_regs_base = bcm6368_regs_base;
+               bcm63xx_irqs = bcm6368_irqs;
+--- a/arch/mips/bcm63xx/irq.c
++++ b/arch/mips/bcm63xx/irq.c
+@@ -82,6 +82,17 @@ static void __internal_irq_unmask_64(uns
+ #define ext_irq_cfg_reg1      PERF_EXTIRQ_CFG_REG_6358
+ #define ext_irq_cfg_reg2      0
+ #endif
++#ifdef CONFIG_BCM63XX_CPU_6362
++#define irq_stat_reg          PERF_IRQSTAT_6362_REG
++#define irq_mask_reg          PERF_IRQMASK_6362_REG
++#define irq_bits              64
++#define is_ext_irq_cascaded   1
++#define ext_irq_start         (BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE)
++#define ext_irq_end           (BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE)
++#define ext_irq_count         4
++#define ext_irq_cfg_reg1      PERF_EXTIRQ_CFG_REG_6362
++#define ext_irq_cfg_reg2      0
++#endif
+ #ifdef CONFIG_BCM63XX_CPU_6368
+ #define irq_stat_reg          PERF_IRQSTAT_6368_REG
+ #define irq_mask_reg          PERF_IRQMASK_6368_REG
+@@ -170,6 +181,16 @@ static void bcm63xx_init_irq(void)
+               ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
+               ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
+               break;
++      case BCM6362_CPU_ID:
++              irq_stat_addr += PERF_IRQSTAT_6362_REG;
++              irq_mask_addr += PERF_IRQMASK_6362_REG;
++              irq_bits = 64;
++              ext_irq_count = 4;
++              is_ext_irq_cascaded = 1;
++              ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE;
++              ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE;
++              ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
++              break;
+       case BCM6368_CPU_ID:
+               irq_stat_addr += PERF_IRQSTAT_6368_REG;
+               irq_mask_addr += PERF_IRQMASK_6368_REG;
+@@ -458,6 +479,7 @@ static int bcm63xx_external_irq_set_type
+       case BCM6338_CPU_ID:
+       case BCM6345_CPU_ID:
+       case BCM6358_CPU_ID:
++      case BCM6362_CPU_ID:
+       case BCM6368_CPU_ID:
+               if (levelsense)
+                       reg |= EXTIRQ_CFG_LEVELSENSE(irq);
+--- a/arch/mips/bcm63xx/prom.c
++++ b/arch/mips/bcm63xx/prom.c
+@@ -36,6 +36,8 @@ void __init prom_init(void)
+               mask = CKCTL_6348_ALL_SAFE_EN;
+       else if (BCMCPU_IS_6358())
+               mask = CKCTL_6358_ALL_SAFE_EN;
++      else if (BCMCPU_IS_6362())
++              mask = CKCTL_6362_ALL_SAFE_EN;
+       else if (BCMCPU_IS_6368())
+               mask = CKCTL_6368_ALL_SAFE_EN;
+       else
+--- a/arch/mips/bcm63xx/reset.c
++++ b/arch/mips/bcm63xx/reset.c
+@@ -85,6 +85,20 @@
+ #define BCM6358_RESET_PCIE    0
+ #define BCM6358_RESET_PCIE_EXT        0
++#define BCM6362_RESET_SPI     SOFTRESET_6362_SPI_MASK
++#define BCM6362_RESET_ENET    0
++#define BCM6362_RESET_USBH    SOFTRESET_6362_USBH_MASK
++#define BCM6362_RESET_USBD    SOFTRESET_6362_USBS_MASK
++#define BCM6362_RESET_DSL     0
++#define BCM6362_RESET_SAR     SOFTRESET_6362_SAR_MASK
++#define BCM6362_RESET_EPHY    SOFTRESET_6362_EPHY_MASK
++#define BCM6362_RESET_ENETSW  SOFTRESET_6362_ENETSW_MASK
++#define BCM6362_RESET_PCM     SOFTRESET_6362_PCM_MASK
++#define BCM6362_RESET_MPI     0
++#define BCM6362_RESET_PCIE      (SOFTRESET_6362_PCIE_MASK | \
++                               SOFTRESET_6362_PCIE_CORE_MASK)
++#define BCM6362_RESET_PCIE_EXT        SOFTRESET_6362_PCIE_EXT_MASK
++
+ #define BCM6368_RESET_SPI     SOFTRESET_6368_SPI_MASK
+ #define BCM6368_RESET_ENET    0
+ #define BCM6368_RESET_USBH    SOFTRESET_6368_USBH_MASK
+@@ -119,6 +133,10 @@ static const u32 bcm6358_reset_bits[] =
+       __GEN_RESET_BITS_TABLE(6358)
+ };
++static const u32 bcm6362_reset_bits[] = {
++      __GEN_RESET_BITS_TABLE(6362)
++};
++
+ static const u32 bcm6368_reset_bits[] = {
+       __GEN_RESET_BITS_TABLE(6368)
+ };
+@@ -140,6 +158,9 @@ static int __init bcm63xx_reset_bits_ini
+       } else if (BCMCPU_IS_6358()) {
+               reset_reg = PERF_SOFTRESET_6358_REG;
+               bcm63xx_reset_bits = bcm6358_reset_bits;
++      } else if (BCMCPU_IS_6362()) {
++              reset_reg = PERF_SOFTRESET_6362_REG;
++              bcm63xx_reset_bits = bcm6362_reset_bits;
+       } else if (BCMCPU_IS_6368()) {
+               reset_reg = PERF_SOFTRESET_6368_REG;
+               bcm63xx_reset_bits = bcm6368_reset_bits;
+@@ -182,6 +203,13 @@ static const u32 bcm63xx_reset_bits[] =
+ #define reset_reg PERF_SOFTRESET_6358_REG
+ #endif
++#ifdef CONFIG_BCM63XX_CPU_6362
++static const u32 bcm63xx_reset_bits[] = {
++      __GEN_RESET_BITS_TABLE(6362)
++};
++#define reset_reg PERF_SOFTRESET_6362_REG
++#endif
++
+ #ifdef CONFIG_BCM63XX_CPU_6368
+ static const u32 bcm63xx_reset_bits[] = {
+       __GEN_RESET_BITS_TABLE(6368)
+--- a/arch/mips/bcm63xx/setup.c
++++ b/arch/mips/bcm63xx/setup.c
+@@ -83,6 +83,9 @@ void bcm63xx_machine_reboot(void)
+       case BCM6358_CPU_ID:
+               perf_regs[0] = PERF_EXTIRQ_CFG_REG_6358;
+               break;
++      case BCM6362_CPU_ID:
++              perf_regs[0] = PERF_EXTIRQ_CFG_REG_6362;
++              break;
+       }
+       for (i = 0; i < 2; i++) {
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+@@ -14,6 +14,7 @@
+ #define BCM6345_CPU_ID                0x6345
+ #define BCM6348_CPU_ID                0x6348
+ #define BCM6358_CPU_ID                0x6358
++#define BCM6362_CPU_ID                0x6362
+ #define BCM6368_CPU_ID                0x6368
+ void __init bcm63xx_cpu_init(void);
+@@ -86,6 +87,20 @@ unsigned int bcm63xx_get_cpu_freq(void);
+ # define BCMCPU_IS_6358()     (0)
+ #endif
++#ifdef CONFIG_BCM63XX_CPU_6362
++# ifdef bcm63xx_get_cpu_id
++#  undef bcm63xx_get_cpu_id
++#  define bcm63xx_get_cpu_id()        __bcm63xx_get_cpu_id()
++#  define BCMCPU_RUNTIME_DETECT
++# else
++#  define bcm63xx_get_cpu_id()        BCM6362_CPU_ID
++# endif
++# define BCMCPU_IS_6362()     (bcm63xx_get_cpu_id() == BCM6362_CPU_ID)
++#else
++# define BCMCPU_IS_6362()     (0)
++#endif
++
++
+ #ifdef CONFIG_BCM63XX_CPU_6368
+ # ifdef bcm63xx_get_cpu_id
+ #  undef bcm63xx_get_cpu_id
+@@ -406,6 +421,62 @@ enum bcm63xx_regs_set {
+ /*
++ * 6362 register sets base address
++ */
++#define BCM_6362_DSL_LMEM_BASE                (0xdeadbeef)
++#define BCM_6362_PERF_BASE            (0xb0000000)
++#define BCM_6362_TIMER_BASE           (0xb0000040)
++#define BCM_6362_WDT_BASE             (0xb000005c)
++#define BCM_6362_UART0_BASE             (0xb0000100)
++#define BCM_6362_UART1_BASE           (0xb0000120)
++#define BCM_6362_GPIO_BASE            (0xb0000080)
++#define BCM_6362_SPI_BASE             (0xb0000800)
++#define BCM_6362_HSSPI_BASE           (0xb0001000)
++#define BCM_6362_UDC0_BASE            (0xdeadbeef)
++#define BCM_6362_USBDMA_BASE          (0xb000c000)
++#define BCM_6362_OHCI0_BASE           (0xb0002600)
++#define BCM_6362_OHCI_PRIV_BASE               (0xdeadbeef)
++#define BCM_6362_USBH_PRIV_BASE               (0xb0002700)
++#define BCM_6362_USBD_BASE            (0xb0002400)
++#define BCM_6362_MPI_BASE             (0xdeadbeef)
++#define BCM_6362_PCMCIA_BASE          (0xdeadbeef)
++#define BCM_6362_PCIE_BASE            (0xb0e40000)
++#define BCM_6362_SDRAM_REGS_BASE      (0xdeadbeef)
++#define BCM_6362_DSL_BASE             (0xdeadbeef)
++#define BCM_6362_UBUS_BASE            (0xdeadbeef)
++#define BCM_6362_ENET0_BASE           (0xdeadbeef)
++#define BCM_6362_ENET1_BASE           (0xdeadbeef)
++#define BCM_6362_ENETDMA_BASE         (0xb000d800)
++#define BCM_6362_ENETDMAC_BASE                (0xb000da00)
++#define BCM_6362_ENETDMAS_BASE                (0xb000dc00)
++#define BCM_6362_ENETSW_BASE          (0xb0e00000)
++#define BCM_6362_EHCI0_BASE           (0xb0002500)
++#define BCM_6362_SDRAM_BASE           (0xdeadbeef)
++#define BCM_6362_MEMC_BASE            (0xdeadbeef)
++#define BCM_6362_DDR_BASE             (0xb0003000)
++#define BCM_6362_M2M_BASE             (0xdeadbeef)
++#define BCM_6362_ATM_BASE             (0xdeadbeef)
++#define BCM_6362_XTM_BASE             (0xb0007800)
++#define BCM_6362_XTMDMA_BASE          (0xb000b800)
++#define BCM_6362_XTMDMAC_BASE         (0xdeadbeef)
++#define BCM_6362_XTMDMAS_BASE         (0xdeadbeef)
++#define BCM_6362_PCM_BASE             (0xb000a800)
++#define BCM_6362_PCMDMA_BASE          (0xdeadbeef)
++#define BCM_6362_PCMDMAC_BASE         (0xdeadbeef)
++#define BCM_6362_PCMDMAS_BASE         (0xdeadbeef)
++#define BCM_6362_RNG_BASE             (0xdeadbeef)
++#define BCM_6362_MISC_BASE            (0xb0001800)
++
++#define BCM_6362_NAND_REG_BASE                (0xb0000200)
++#define BCM_6362_NAND_CACHE_BASE      (0xb0000600)
++#define BCM_6362_LED_BASE             (0xb0001900)
++#define BCM_6362_IPSEC_BASE           (0xb0002800)
++#define BCM_6362_IPSEC_DMA_BASE               (0xb000d000)
++#define BCM_6362_WLAN_CHIPCOMMON_BASE (0xb0004000)
++#define BCM_6362_WLAN_D11_BASE                (0xb0005000)
++#define BCM_6362_WLAN_SHIM_BASE               (0xb0007000)
++
++/*
+  * 6368 register sets base address
+  */
+ #define BCM_6368_DSL_LMEM_BASE                (0xdeadbeef)
+@@ -564,6 +635,9 @@ static inline unsigned long bcm63xx_regs
+ #ifdef CONFIG_BCM63XX_CPU_6358
+       __GEN_RSET(6358)
+ #endif
++#ifdef CONFIG_BCM63XX_CPU_6362
++      __GEN_RSET(6362)
++#endif
+ #ifdef CONFIG_BCM63XX_CPU_6368
+       __GEN_RSET(6368)
+ #endif
+@@ -820,6 +894,71 @@ enum bcm63xx_irq {
+ #define BCM_6358_EXT_IRQ3             (IRQ_INTERNAL_BASE + 28)
+ /*
++ * 6362 irqs
++ */
++#define BCM_6362_HIGH_IRQ_BASE                (IRQ_INTERNAL_BASE + 32)
++
++#define BCM_6362_TIMER_IRQ            (IRQ_INTERNAL_BASE + 0)
++#define BCM_6362_SPI_IRQ              (IRQ_INTERNAL_BASE + 2)
++#define BCM_6362_UART0_IRQ            (IRQ_INTERNAL_BASE + 3)
++#define BCM_6362_UART1_IRQ            (IRQ_INTERNAL_BASE + 4)
++#define BCM_6362_DSL_IRQ              (IRQ_INTERNAL_BASE + 28)
++#define BCM_6362_UDC0_IRQ             0
++#define BCM_6362_ENET0_IRQ            0
++#define BCM_6362_ENET1_IRQ            0
++#define BCM_6362_ENET_PHY_IRQ         (IRQ_INTERNAL_BASE + 14)
++#define BCM_6362_HSSPI_IRQ            (IRQ_INTERNAL_BASE + 5)
++#define BCM_6362_OHCI0_IRQ            (IRQ_INTERNAL_BASE + 9)
++#define BCM_6362_EHCI0_IRQ            (IRQ_INTERNAL_BASE + 10)
++#define BCM_6362_USBD_IRQ             (IRQ_INTERNAL_BASE + 11)
++#define BCM_6362_USBD_RXDMA0_IRQ      (IRQ_INTERNAL_BASE + 20)
++#define BCM_6362_USBD_TXDMA0_IRQ      (IRQ_INTERNAL_BASE + 21)
++#define BCM_6362_USBD_RXDMA1_IRQ      (IRQ_INTERNAL_BASE + 22)
++#define BCM_6362_USBD_TXDMA1_IRQ      (IRQ_INTERNAL_BASE + 23)
++#define BCM_6362_USBD_RXDMA2_IRQ      (IRQ_INTERNAL_BASE + 24)
++#define BCM_6362_USBD_TXDMA2_IRQ      (IRQ_INTERNAL_BASE + 25)
++#define BCM_6362_PCMCIA_IRQ           0
++#define BCM_6362_ENET0_RXDMA_IRQ      0
++#define BCM_6362_ENET0_TXDMA_IRQ      0
++#define BCM_6362_ENET1_RXDMA_IRQ      0
++#define BCM_6362_ENET1_TXDMA_IRQ      0
++#define BCM_6362_PCI_IRQ              (IRQ_INTERNAL_BASE + 30)
++#define BCM_6362_ATM_IRQ              0
++#define BCM_6362_ENETSW_RXDMA0_IRQ    (BCM_6362_HIGH_IRQ_BASE + 0)
++#define BCM_6362_ENETSW_RXDMA1_IRQ    (BCM_6362_HIGH_IRQ_BASE + 1)
++#define BCM_6362_ENETSW_RXDMA2_IRQ    (BCM_6362_HIGH_IRQ_BASE + 2)
++#define BCM_6362_ENETSW_RXDMA3_IRQ    (BCM_6362_HIGH_IRQ_BASE + 3)
++#define BCM_6362_ENETSW_TXDMA0_IRQ    0
++#define BCM_6362_ENETSW_TXDMA1_IRQ    0
++#define BCM_6362_ENETSW_TXDMA2_IRQ    0
++#define BCM_6362_ENETSW_TXDMA3_IRQ    0
++#define BCM_6362_XTM_IRQ              0
++#define BCM_6362_XTM_DMA0_IRQ         (BCM_6362_HIGH_IRQ_BASE + 12)
++
++#define BCM_6362_RING_OSC_IRQ         (IRQ_INTERNAL_BASE + 1)
++#define BCM_6362_WLAN_GPIO_IRQ                (IRQ_INTERNAL_BASE + 6)
++#define BCM_6362_WLAN_IRQ             (IRQ_INTERNAL_BASE + 7)
++#define BCM_6362_IPSEC_IRQ            (IRQ_INTERNAL_BASE + 8)
++#define BCM_6362_NAND_IRQ             (IRQ_INTERNAL_BASE + 12)
++#define BCM_6362_PCM_IRQ              (IRQ_INTERNAL_BASE + 13)
++#define BCM_6362_DG_IRQ                       (IRQ_INTERNAL_BASE + 15)
++#define BCM_6362_EPHY_ENERGY0_IRQ     (IRQ_INTERNAL_BASE + 16)
++#define BCM_6362_EPHY_ENERGY1_IRQ     (IRQ_INTERNAL_BASE + 17)
++#define BCM_6362_EPHY_ENERGY2_IRQ     (IRQ_INTERNAL_BASE + 18)
++#define BCM_6362_EPHY_ENERGY3_IRQ     (IRQ_INTERNAL_BASE + 19)
++#define BCM_6362_IPSEC_DMA0_IRQ               (IRQ_INTERNAL_BASE + 26)
++#define BCM_6362_IPSEC_DMA1_IRQ               (IRQ_INTERNAL_BASE + 27)
++#define BCM_6362_FAP0_IRQ             (IRQ_INTERNAL_BASE + 29)
++#define BCM_6362_PCM_DMA0_IRQ         (BCM_6362_HIGH_IRQ_BASE + 4)
++#define BCM_6362_PCM_DMA1_IRQ         (BCM_6362_HIGH_IRQ_BASE + 5)
++#define BCM_6362_DECT0_IRQ            (BCM_6362_HIGH_IRQ_BASE + 6)
++#define BCM_6362_DECT1_IRQ            (BCM_6362_HIGH_IRQ_BASE + 7)
++#define BCM_6362_EXT_IRQ0             (BCM_6362_HIGH_IRQ_BASE + 8)
++#define BCM_6362_EXT_IRQ1             (BCM_6362_HIGH_IRQ_BASE + 9)
++#define BCM_6362_EXT_IRQ2             (BCM_6362_HIGH_IRQ_BASE + 10)
++#define BCM_6362_EXT_IRQ3             (BCM_6362_HIGH_IRQ_BASE + 11)
++
++/*
+  * 6368 irqs
+  */
+ #define BCM_6368_HIGH_IRQ_BASE                (IRQ_INTERNAL_BASE + 32)
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
+@@ -17,6 +17,8 @@ static inline unsigned long bcm63xx_gpio
+               return 8;
+       case BCM6345_CPU_ID:
+               return 16;
++      case BCM6362_CPU_ID:
++              return 48;
+       case BCM6368_CPU_ID:
+               return 38;
+       case BCM6348_CPU_ID:
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -112,6 +112,39 @@
+                                       CKCTL_6358_USBSU_EN |           \
+                                       CKCTL_6358_EPHY_EN)
++#define CKCTL_6362_ADSL_QPROC_EN      (1 << 1)
++#define CKCTL_6362_ADSL_AFE_EN                (1 << 2)
++#define CKCTL_6362_ADSL_EN            (1 << 3)
++#define CKCTL_6362_MIPS_EN            (1 << 4)
++#define CKCTL_6362_WLAN_OCP_EN                (1 << 5)
++#define CKCTL_6362_SWPKT_USB_EN               (1 << 7)
++#define CKCTL_6362_SWPKT_SAR_EN               (1 << 8)
++#define CKCTL_6362_SAR_EN             (1 << 9)
++#define CKCTL_6362_ROBOSW_EN          (1 << 10)
++#define CKCTL_6362_PCM_EN             (1 << 11)
++#define CKCTL_6362_USBD_EN            (1 << 12)
++#define CKCTL_6362_USBH_EN            (1 << 13)
++#define CKCTL_6362_IPSEC_EN           (1 << 14)
++#define CKCTL_6362_SPI_EN             (1 << 15)
++#define CKCTL_6362_HSSPI_EN           (1 << 16)
++#define CKCTL_6362_PCIE_EN            (1 << 17)
++#define CKCTL_6362_FAP_EN             (1 << 18)
++#define CKCTL_6362_PHYMIPS_EN         (1 << 19)
++#define CKCTL_6362_NAND_EN            (1 << 20)
++
++#define CKCTL_6362_ALL_SAFE_EN                (CKCTL_6362_PHYMIPS_EN |        \
++                                      CKCTL_6362_ADSL_QPROC_EN |      \
++                                      CKCTL_6362_ADSL_AFE_EN |        \
++                                      CKCTL_6362_ADSL_EN |            \
++                                      CKCTL_6362_SAR_EN  |            \
++                                      CKCTL_6362_PCM_EN  |            \
++                                      CKCTL_6362_IPSEC_EN |           \
++                                      CKCTL_6362_USBD_EN |            \
++                                      CKCTL_6362_USBH_EN |            \
++                                      CKCTL_6362_ROBOSW_EN |          \
++                                      CKCTL_6362_PCIE_EN)
++
++
+ #define CKCTL_6368_VDSL_QPROC_EN      (1 << 2)
+ #define CKCTL_6368_VDSL_AFE_EN                (1 << 3)
+ #define CKCTL_6368_VDSL_BONDING_EN    (1 << 4)
+@@ -153,6 +186,7 @@
+ #define PERF_IRQMASK_6345_REG         0xc
+ #define PERF_IRQMASK_6348_REG         0xc
+ #define PERF_IRQMASK_6358_REG         0xc
++#define PERF_IRQMASK_6362_REG         0x20
+ #define PERF_IRQMASK_6368_REG         0x20
+ /* Interrupt Status register */
+@@ -161,6 +195,7 @@
+ #define PERF_IRQSTAT_6345_REG         0x10
+ #define PERF_IRQSTAT_6348_REG         0x10
+ #define PERF_IRQSTAT_6358_REG         0x10
++#define PERF_IRQSTAT_6362_REG         0x28
+ #define PERF_IRQSTAT_6368_REG         0x28
+ /* External Interrupt Configuration register */
+@@ -169,6 +204,7 @@
+ #define PERF_EXTIRQ_CFG_REG_6345      0x14
+ #define PERF_EXTIRQ_CFG_REG_6348      0x14
+ #define PERF_EXTIRQ_CFG_REG_6358      0x14
++#define PERF_EXTIRQ_CFG_REG_6362      0x18
+ #define PERF_EXTIRQ_CFG_REG_6368      0x18
+ #define PERF_EXTIRQ_CFG_REG2_6368     0x1c
+@@ -197,6 +233,7 @@
+ #define PERF_SOFTRESET_REG            0x28
+ #define PERF_SOFTRESET_6328_REG               0x10
+ #define PERF_SOFTRESET_6358_REG               0x34
++#define PERF_SOFTRESET_6362_REG               0x10
+ #define PERF_SOFTRESET_6368_REG               0x10
+ #define SOFTRESET_6328_SPI_MASK               (1 << 0)
+@@ -259,6 +296,22 @@
+ #define SOFTRESET_6358_PCM_MASK               (1 << 13)
+ #define SOFTRESET_6358_ADSL_MASK      (1 << 14)
++#define SOFTRESET_6362_SPI_MASK               (1 << 0)
++#define SOFTRESET_6362_IPSEC_MASK     (1 << 1)
++#define SOFTRESET_6362_EPHY_MASK      (1 << 2)
++#define SOFTRESET_6362_SAR_MASK               (1 << 3)
++#define SOFTRESET_6362_ENETSW_MASK    (1 << 4)
++#define SOFTRESET_6362_USBS_MASK      (1 << 5)
++#define SOFTRESET_6362_USBH_MASK      (1 << 6)
++#define SOFTRESET_6362_PCM_MASK               (1 << 7)
++#define SOFTRESET_6362_PCIE_CORE_MASK (1 << 8)
++#define SOFTRESET_6362_PCIE_MASK      (1 << 9)
++#define SOFTRESET_6362_PCIE_EXT_MASK  (1 << 10)
++#define SOFTRESET_6362_WLAN_SHIM_MASK (1 << 11)
++#define SOFTRESET_6362_DDR_PHY_MASK   (1 << 12)
++#define SOFTRESET_6362_FAP_MASK               (1 << 13)
++#define SOFTRESET_6362_WLAN_UBUS_MASK (1 << 14)
++
+ #define SOFTRESET_6368_SPI_MASK               (1 << 0)
+ #define SOFTRESET_6368_MPI_MASK               (1 << 3)
+ #define SOFTRESET_6368_EPHY_MASK      (1 << 6)
+@@ -1240,7 +1293,7 @@
+ #define SPI_6348_RX_DATA              0x80
+ #define SPI_6348_RX_DATA_SIZE         0x3f
+-/* BCM 6358/6368 SPI core */
++/* BCM 6358/6262/6368 SPI core */
+ #define SPI_6358_MSG_CTL              0x00    /* 16-bits register */
+ #define SPI_6358_MSG_CTL_WIDTH                16
+ #define SPI_6358_MSG_DATA             0x02
+@@ -1316,6 +1369,12 @@
+ #define SERDES_PCIE_EN                        (1 << 0)
+ #define SERDES_PCIE_EXD_EN            (1 << 15)
++#define MISC_STRAPBUS_6362_REG                0x14
++#define STRAPBUS_6362_FCVO_SHIFT      1
++#define STRAPBUS_6362_FCVO_MASK               (0x1f << STRAPBUS_6362_FCVO_SHIFT)
++#define STRAPBUS_6362_BOOT_SEL_SERIAL (1 << 15)
++#define STRAPBUS_6362_BOOT_SEL_NAND   (0 << 15)
++
+ #define MISC_STRAPBUS_6328_REG                0x240
+ #define STRAPBUS_6328_FCVO_SHIFT      7
+ #define STRAPBUS_6328_FCVO_MASK               (0x1f << STRAPBUS_6328_FCVO_SHIFT)
+--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
++++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
+@@ -19,6 +19,7 @@ static inline int is_bcm63xx_internal_re
+                       return 1;
+               break;
+       case BCM6328_CPU_ID:
++      case BCM6362_CPU_ID:
+       case BCM6368_CPU_ID:
+               if (offset >= 0xb0000000 && offset < 0xb1000000)
+                       return 1;
diff --git a/target/linux/brcm63xx/patches-3.9/026-MIPS-BCM63XX-enable-SPI-controller-for-BCM6362.patch b/target/linux/brcm63xx/patches-3.9/026-MIPS-BCM63XX-enable-SPI-controller-for-BCM6362.patch
new file mode 100644 (file)
index 0000000..27a411d
--- /dev/null
@@ -0,0 +1,57 @@
+From 5da349ee614f61a2e6edb403098f40c6d40f2553 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Thu, 5 Jul 2012 21:19:20 +0200
+Subject: [PATCH 5/7] MIPS: BCM63XX: enable SPI controller for BCM6362
+
+The SPI controller shares the same register layout as the 6358 one.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/clk.c                              |    2 ++
+ arch/mips/bcm63xx/dev-spi.c                          |    4 ++--
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h |    3 ++-
+ 3 files changed, 6 insertions(+), 3 deletions(-)
+
+--- a/arch/mips/bcm63xx/clk.c
++++ b/arch/mips/bcm63xx/clk.c
+@@ -202,6 +202,8 @@ static void spi_set(struct clk *clk, int
+               mask = CKCTL_6348_SPI_EN;
+       else if (BCMCPU_IS_6358())
+               mask = CKCTL_6358_SPI_EN;
++      else if (BCMCPU_IS_6362())
++              mask = CKCTL_6362_SPI_EN;
+       else
+               /* BCMCPU_IS_6368 */
+               mask = CKCTL_6368_SPI_EN;
+--- a/arch/mips/bcm63xx/dev-spi.c
++++ b/arch/mips/bcm63xx/dev-spi.c
+@@ -37,7 +37,7 @@ static __init void bcm63xx_spi_regs_init
+ {
+       if (BCMCPU_IS_6338() || BCMCPU_IS_6348())
+               bcm63xx_regs_spi = bcm6348_regs_spi;
+-      if (BCMCPU_IS_6358() || BCMCPU_IS_6368())
++      if (BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368())
+               bcm63xx_regs_spi = bcm6358_regs_spi;
+ }
+ #else
+@@ -87,7 +87,7 @@ int __init bcm63xx_spi_register(void)
+               spi_pdata.msg_ctl_width = SPI_6348_MSG_CTL_WIDTH;
+       }
+-      if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
++      if (BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) {
+               spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1;
+               spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE;
+               spi_pdata.msg_type_shift = SPI_6358_MSG_TYPE_SHIFT;
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
+@@ -74,7 +74,8 @@ static inline unsigned long bcm63xx_spir
+ #if defined(CONFIG_BCM63XX_CPU_6338) || defined(CONFIG_BCM63XX_CPU_6348)
+       __GEN_SPI_RSET(6348)
+ #endif
+-#if defined(CONFIG_BCM63XX_CPU_6358) || defined(CONFIG_BCM63XX_CPU_6368)
++#if defined(CONFIG_BCM63XX_CPU_6358) || defined(CONFIG_BCM63XX_CPU_6362) || \
++      defined(CONFIG_BCM63XX_CPU_6368)
+       __GEN_SPI_RSET(6358)
+ #endif
+ #endif
diff --git a/target/linux/brcm63xx/patches-3.9/027-MIPS-BCM63XX-enable-pcie-for-BCM6362.patch b/target/linux/brcm63xx/patches-3.9/027-MIPS-BCM63XX-enable-pcie-for-BCM6362.patch
new file mode 100644 (file)
index 0000000..3c5b119
--- /dev/null
@@ -0,0 +1,56 @@
+From ec6f1e53b22d01e628b79b99f7a33960034e97e7 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Mon, 21 Nov 2011 00:53:26 +0100
+Subject: [PATCH 6/7] MIPS: BCM63XX: enable pcie for BCM6362
+
+The PCIe controller is almost the same as the BCM6328 one, with only
+the SERDES register being at a different location.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |    3 ++-
+ arch/mips/pci/pci-bcm63xx.c                       |   11 +++++++++--
+ 2 files changed, 11 insertions(+), 3 deletions(-)
+
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -1365,7 +1365,8 @@
+ /*************************************************************************
+  * _REG relative to RSET_MISC
+  *************************************************************************/
+-#define MISC_SERDES_CTRL_REG          0x0
++#define MISC_SERDES_CTRL_6328_REG     0x0
++#define MISC_SERDES_CTRL_6362_REG     0x4
+ #define SERDES_PCIE_EN                        (1 << 0)
+ #define SERDES_PCIE_EXD_EN            (1 << 15)
+--- a/arch/mips/pci/pci-bcm63xx.c
++++ b/arch/mips/pci/pci-bcm63xx.c
+@@ -121,11 +121,17 @@ void __iomem *pci_iospace_start;
+ static void __init bcm63xx_reset_pcie(void)
+ {
+       u32 val;
++      u32 reg;
+       /* enable SERDES */
+-      val = bcm_misc_readl(MISC_SERDES_CTRL_REG);
++      if (BCMCPU_IS_6328())
++              reg = MISC_SERDES_CTRL_6328_REG;
++      else
++              reg = MISC_SERDES_CTRL_6362_REG;
++
++      val = bcm_misc_readl(reg);
+       val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN;
+-      bcm_misc_writel(val, MISC_SERDES_CTRL_REG);
++      bcm_misc_writel(val, reg);
+       /* reset the PCIe core */
+       bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1);
+@@ -330,6 +336,7 @@ static int __init bcm63xx_pci_init(void)
+       switch (bcm63xx_get_cpu_id()) {
+       case BCM6328_CPU_ID:
++      case BCM6362_CPU_ID:
+               return bcm63xx_register_pcie();
+       case BCM6348_CPU_ID:
+       case BCM6358_CPU_ID:
diff --git a/target/linux/brcm63xx/patches-3.9/028-MIPS-BCM63XX-add-flash-detection-for-BCM6362.patch b/target/linux/brcm63xx/patches-3.9/028-MIPS-BCM63XX-add-flash-detection-for-BCM6362.patch
new file mode 100644 (file)
index 0000000..38125a5
--- /dev/null
@@ -0,0 +1,38 @@
+From 01034e48e72783ced82a050e862f82ee3dfdb783 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Mon, 21 Nov 2011 00:48:52 +0100
+Subject: [PATCH 7/7] MIPS: BCM63XX: add flash detection for BCM6362
+
+BCM6362 support booting from SPI flash and NAND.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/dev-flash.c                     |    6 ++++++
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |    1 +
+ 2 files changed, 7 insertions(+)
+
+--- a/arch/mips/bcm63xx/dev-flash.c
++++ b/arch/mips/bcm63xx/dev-flash.c
+@@ -77,6 +77,12 @@ static int __init bcm63xx_detect_flash_t
+                       return BCM63XX_FLASH_TYPE_PARALLEL;
+               else
+                       return BCM63XX_FLASH_TYPE_SERIAL;
++      case BCM6362_CPU_ID:
++              val = bcm_misc_readl(MISC_STRAPBUS_6362_REG);
++              if (val & STRAPBUS_6362_BOOT_SEL_SERIAL)
++                      return BCM63XX_FLASH_TYPE_SERIAL;
++              else
++                      return BCM63XX_FLASH_TYPE_NAND;
+       case BCM6368_CPU_ID:
+               val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
+               switch (val & STRAPBUS_6368_BOOT_SEL_MASK) {
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -1372,6 +1372,7 @@
+ #define MISC_STRAPBUS_6362_REG                0x14
+ #define STRAPBUS_6362_FCVO_SHIFT      1
++#define STRAPBUS_6362_HSSPI_CLK_FAST  (1 << 13)
+ #define STRAPBUS_6362_FCVO_MASK               (0x1f << STRAPBUS_6362_FCVO_SHIFT)
+ #define STRAPBUS_6362_BOOT_SEL_SERIAL (1 << 15)
+ #define STRAPBUS_6362_BOOT_SEL_NAND   (0 << 15)
diff --git a/target/linux/brcm63xx/patches-3.9/029-MIPS-BCM63XX-add-missing-clocks-for-BCM6328-and-BCM6.patch b/target/linux/brcm63xx/patches-3.9/029-MIPS-BCM63XX-add-missing-clocks-for-BCM6328-and-BCM6.patch
new file mode 100644 (file)
index 0000000..bc72a00
--- /dev/null
@@ -0,0 +1,91 @@
+From d31454bc822e1957e758e75d4367bcd12af89743 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Thu, 18 Apr 2013 21:23:11 +0200
+Subject: [PATCH] MIPS: BCM63XX: add missing clocks for BCM6328 and BCM6362
+
+Add currently unused missing clocks for BCM6328 and BCM6362.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/clk.c |   33 +++++++++++++++++++++++++--------
+ 1 file changed, 25 insertions(+), 8 deletions(-)
+
+--- a/arch/mips/bcm63xx/clk.c
++++ b/arch/mips/bcm63xx/clk.c
+@@ -125,11 +125,18 @@ static struct clk clk_ephy = {
+  */
+ static void enetsw_set(struct clk *clk, int enable)
+ {
+-      if (!BCMCPU_IS_6368())
++      if (BCMCPU_IS_6328())
++              bcm_hwclock_set(CKCTL_6328_ROBOSW_EN, enable);
++      else if (BCMCPU_IS_6362())
++              bcm_hwclock_set(CKCTL_6362_ROBOSW_EN, enable);
++      else if (BCMCPU_IS_6368())
++              bcm_hwclock_set(CKCTL_6368_ROBOSW_EN |
++                              CKCTL_6368_SWPKT_USB_EN |
++                              CKCTL_6368_SWPKT_SAR_EN,
++                              enable);
++      else
+               return;
+-      bcm_hwclock_set(CKCTL_6368_ROBOSW_EN |
+-                      CKCTL_6368_SWPKT_USB_EN |
+-                      CKCTL_6368_SWPKT_SAR_EN, enable);
++
+       if (enable) {
+               /* reset switch core afer clock change */
+               bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 1);
+@@ -166,6 +173,8 @@ static void usbh_set(struct clk *clk, in
+               bcm_hwclock_set(CKCTL_6328_USBH_EN, enable);
+       else if (BCMCPU_IS_6348())
+               bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
++      else if (BCMCPU_IS_6362())
++              bcm_hwclock_set(CKCTL_6362_USBH_EN, enable);
+       else if (BCMCPU_IS_6368())
+               bcm_hwclock_set(CKCTL_6368_USBH_EN, enable);
+ }
+@@ -181,6 +190,8 @@ static void usbd_set(struct clk *clk, in
+ {
+       if (BCMCPU_IS_6328())
+               bcm_hwclock_set(CKCTL_6328_USBD_EN, enable);
++      else if (BCMCPU_IS_6362())
++              bcm_hwclock_set(CKCTL_6362_USBD_EN, enable);
+       else if (BCMCPU_IS_6368())
+               bcm_hwclock_set(CKCTL_6368_USBD_EN, enable);
+ }
+@@ -244,7 +255,10 @@ static struct clk clk_xtm = {
+  */
+ static void ipsec_set(struct clk *clk, int enable)
+ {
+-      bcm_hwclock_set(CKCTL_6368_IPSEC_EN, enable);
++      if (BCMCPU_IS_6362())
++              bcm_hwclock_set(CKCTL_6362_IPSEC_EN, enable);
++      else if (BCMCPU_IS_6368())
++              bcm_hwclock_set(CKCTL_6368_IPSEC_EN, enable);
+ }
+ static struct clk clk_ipsec = {
+@@ -257,7 +271,10 @@ static struct clk clk_ipsec = {
+ static void pcie_set(struct clk *clk, int enable)
+ {
+-      bcm_hwclock_set(CKCTL_6328_PCIE_EN, enable);
++      if (BCMCPU_IS_6328())
++              bcm_hwclock_set(CKCTL_6328_PCIE_EN, enable);
++      else if (BCMCPU_IS_6362())
++              bcm_hwclock_set(CKCTL_6362_PCIE_EN, enable);
+ }
+ static struct clk clk_pcie = {
+@@ -323,9 +340,9 @@ struct clk *clk_get(struct device *dev,
+               return &clk_periph;
+       if (BCMCPU_IS_6358() && !strcmp(id, "pcm"))
+               return &clk_pcm;
+-      if (BCMCPU_IS_6368() && !strcmp(id, "ipsec"))
++      if ((BCMCPU_IS_6362() || BCMCPU_IS_6368()) && !strcmp(id, "ipsec"))
+               return &clk_ipsec;
+-      if (BCMCPU_IS_6328() && !strcmp(id, "pcie"))
++      if ((BCMCPU_IS_6328() || BCMCPU_IS_6362()) && !strcmp(id, "pcie"))
+               return &clk_pcie;
+       return ERR_PTR(-ENOENT);
+ }
diff --git a/target/linux/brcm63xx/patches-3.9/030-MTD-bcm63xxpart-use-size-macro-for-CFE-block-size.patch b/target/linux/brcm63xx/patches-3.9/030-MTD-bcm63xxpart-use-size-macro-for-CFE-block-size.patch
new file mode 100644 (file)
index 0000000..a7f7822
--- /dev/null
@@ -0,0 +1,29 @@
+From e2092cf1b164ede62b740c7c95905171fb6232ff Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Sat, 23 Mar 2013 12:32:56 +0100
+Subject: [PATCH v2 1/3] MTD: bcm63xxpart: use size macro for CFE block size
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ drivers/mtd/bcm63xxpart.c |    3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/mtd/bcm63xxpart.c
++++ b/drivers/mtd/bcm63xxpart.c
+@@ -27,6 +27,7 @@
+ #include <linux/crc32.h>
+ #include <linux/module.h>
+ #include <linux/kernel.h>
++#include <linux/sizes.h>
+ #include <linux/slab.h>
+ #include <linux/vmalloc.h>
+ #include <linux/mtd/mtd.h>
+@@ -37,7 +38,7 @@
+ #define BCM63XX_EXTENDED_SIZE 0xBFC00000      /* Extended flash address */
+-#define BCM63XX_CFE_BLOCK_SIZE        0x10000         /* always at least 64KiB */
++#define BCM63XX_CFE_BLOCK_SIZE        SZ_64K          /* always at least 64KiB */
+ #define BCM63XX_CFE_MAGIC_OFFSET 0x4e0
diff --git a/target/linux/brcm63xx/patches-3.9/031-MIPS-BCM63XX-export-PSI-size-from-nvram.patch b/target/linux/brcm63xx/patches-3.9/031-MIPS-BCM63XX-export-PSI-size-from-nvram.patch
new file mode 100644 (file)
index 0000000..8ff9659
--- /dev/null
@@ -0,0 +1,58 @@
+From bda508f975d1372568a4fc9862be501a6176fd46 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Sat, 12 May 2012 23:04:17 +0200
+Subject: [PATCH v2 2/3] MIPS: BCM63XX: export PSI size from nvram
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/nvram.c                          |   13 +++++++++++++
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h |    7 +++++++
+ 2 files changed, 20 insertions(+)
+
+--- a/arch/mips/bcm63xx/nvram.c
++++ b/arch/mips/bcm63xx/nvram.c
+@@ -15,6 +15,7 @@
+ #include <linux/export.h>
+ #include <linux/kernel.h>
+ #include <linux/if_ether.h>
++#include <linux/sizes.h>
+ #include <bcm63xx_nvram.h>
+@@ -35,6 +36,8 @@ struct bcm963xx_nvram {
+       u32     checksum_high;
+ };
++#define BCM63XX_DEFAULT_PSI_SIZE      SZ_64K
++
+ static struct bcm963xx_nvram nvram;
+ static int mac_addr_used;
+@@ -104,3 +107,13 @@ int bcm63xx_nvram_get_mac_address(u8 *ma
+       return 0;
+ }
+ EXPORT_SYMBOL(bcm63xx_nvram_get_mac_address);
++
++unsigned int bcm63xx_nvram_get_psi_size(void)
++{
++      /* max is 64k, but some vendors use higher values */
++      if (nvram.psi_size > 0 && nvram.psi_size <= 512)
++              return nvram.psi_size * SZ_1K;
++
++      return BCM63XX_DEFAULT_PSI_SIZE;
++}
++EXPORT_SYMBOL(bcm63xx_nvram_get_psi_size);
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h
+@@ -30,4 +30,11 @@ u8 *bcm63xx_nvram_get_name(void);
+  */
+ int bcm63xx_nvram_get_mac_address(u8 *mac);
++/**
++ * bcm63xx_nvram_get_psi_size() - returns the size of the PSI area
++ *
++ * Returns the size of the Persitent Storage Information area in bytes.
++ */
++unsigned int bcm63xx_nvram_get_psi_size(void);
++
+ #endif /* BCM63XX_NVRAM_H */
diff --git a/target/linux/brcm63xx/patches-3.9/032-MTD-bcm63xxpart-use-nvram-for-PSI-size.patch b/target/linux/brcm63xx/patches-3.9/032-MTD-bcm63xxpart-use-nvram-for-PSI-size.patch
new file mode 100644 (file)
index 0000000..f1c1a0f
--- /dev/null
@@ -0,0 +1,42 @@
+From f6eefaa4a08ec27c69485c2fc4db23247b84f8c9 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Tue, 1 May 2012 14:10:39 +0200
+Subject: [PATCH v2 3/3] MTD: bcm63xxpart: use nvram for PSI size
+
+Read out the SPI size from nvram instead of defaulting to 64K - some
+vendors actually use values larger than the "max" value of 64.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ drivers/mtd/bcm63xxpart.c |    6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+--- a/drivers/mtd/bcm63xxpart.c
++++ b/drivers/mtd/bcm63xxpart.c
+@@ -4,7 +4,7 @@
+  * Copyright © 2006-2008  Florian Fainelli <florian@openwrt.org>
+  *                      Mike Albon <malbon@openwrt.org>
+  * Copyright © 2009-2010  Daniel Dickinson <openwrt@cshore.neomailbox.net>
+- * Copyright © 2011-2012  Jonas Gorski <jonas.gorski@gmail.com>
++ * Copyright © 2011-2013  Jonas Gorski <jonas.gorski@gmail.com>
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+@@ -34,6 +34,7 @@
+ #include <linux/mtd/partitions.h>
+ #include <linux/bcm963xx_tag.h>
++#include <asm/mach-bcm63xx/bcm63xx_nvram.h>
+ #include <asm/mach-bcm63xx/board_bcm963xx.h>
+ #define BCM63XX_EXTENDED_SIZE 0xBFC00000      /* Extended flash address */
+@@ -91,7 +92,8 @@ static int bcm63xx_parse_cfe_partitions(
+                             BCM63XX_CFE_BLOCK_SIZE);
+       cfelen = cfe_erasesize;
+-      nvramlen = cfe_erasesize;
++      nvramlen = bcm63xx_nvram_get_psi_size();
++      nvramlen = roundup(nvramlen, cfe_erasesize);
+       /* Allocate memory for buffer */
+       buf = vmalloc(sizeof(struct bcm_tag));
diff --git a/target/linux/brcm63xx/patches-3.9/100-MIPS-BCM63XX-add-USB-host-clock-enable-delay.patch b/target/linux/brcm63xx/patches-3.9/100-MIPS-BCM63XX-add-USB-host-clock-enable-delay.patch
new file mode 100644 (file)
index 0000000..63d385b
--- /dev/null
@@ -0,0 +1,28 @@
+From 80a2f983e9f44dbc3e01ae31c62d877846a7f791 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <florian@openwrt.org>
+Date: Mon, 28 Jan 2013 20:06:19 +0100
+Subject: [PATCH 01/11] MIPS: BCM63XX: add USB host clock enable delay
+
+Knowledge of the clock setup delay should remain at the clock level (so
+it can be clock specific and CPU specific). Add the 100 milliseconds
+required clock delay for the USB host clock when it gets enabled.
+
+Signed-off-by: Florian Fainelli <florian@openwrt.org>
+---
+ arch/mips/bcm63xx/clk.c |    5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/arch/mips/bcm63xx/clk.c
++++ b/arch/mips/bcm63xx/clk.c
+@@ -177,6 +177,11 @@ static void usbh_set(struct clk *clk, in
+               bcm_hwclock_set(CKCTL_6362_USBH_EN, enable);
+       else if (BCMCPU_IS_6368())
+               bcm_hwclock_set(CKCTL_6368_USBH_EN, enable);
++      else
++              return;
++
++      if (enable)
++              msleep(100);
+ }
+ static struct clk clk_usbh = {
diff --git a/target/linux/brcm63xx/patches-3.9/101-MIPS-BCM63XX-add-USB-device-clock-enable-delay-to-cl.patch b/target/linux/brcm63xx/patches-3.9/101-MIPS-BCM63XX-add-USB-device-clock-enable-delay-to-cl.patch
new file mode 100644 (file)
index 0000000..eaf7503
--- /dev/null
@@ -0,0 +1,41 @@
+From 8e9bf528a122741f0171b89c297b63041116d704 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <florian@openwrt.org>
+Date: Mon, 28 Jan 2013 20:06:20 +0100
+Subject: [PATCH 02/11] MIPS: BCM63XX: add USB device clock enable delay to
+ clock code
+
+This patch adds the required 10 micro seconds delay to the USB device
+clock enable operation. Put this where the correct clock knowledege is,
+which is in the clock code, and remove this delay from the bcm63xx_udc
+gadget driver where it was before.
+
+Signed-off-by: Florian Fainelli <florian@openwrt.org>
+---
+ arch/mips/bcm63xx/clk.c          |    5 +++++
+ drivers/usb/gadget/bcm63xx_udc.c |    1 -
+ 2 files changed, 5 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/bcm63xx/clk.c
++++ b/arch/mips/bcm63xx/clk.c
+@@ -199,6 +199,11 @@ static void usbd_set(struct clk *clk, in
+               bcm_hwclock_set(CKCTL_6362_USBD_EN, enable);
+       else if (BCMCPU_IS_6368())
+               bcm_hwclock_set(CKCTL_6368_USBD_EN, enable);
++      else
++              return;
++
++      if (enable)
++              udelay(10);
+ }
+ static struct clk clk_usbd = {
+--- a/drivers/usb/gadget/bcm63xx_udc.c
++++ b/drivers/usb/gadget/bcm63xx_udc.c
+@@ -386,7 +386,6 @@ static inline void set_clocks(struct bcm
+       if (is_enabled) {
+               clk_enable(udc->usbh_clk);
+               clk_enable(udc->usbd_clk);
+-              udelay(10);
+       } else {
+               clk_disable(udc->usbd_clk);
+               clk_disable(udc->usbh_clk);
diff --git a/target/linux/brcm63xx/patches-3.9/102-MIPS-BCM63XX-move-code-touching-the-USB-private-regi.patch b/target/linux/brcm63xx/patches-3.9/102-MIPS-BCM63XX-move-code-touching-the-USB-private-regi.patch
new file mode 100644 (file)
index 0000000..4d00f0e
--- /dev/null
@@ -0,0 +1,151 @@
+From ac9b0b574d54be28b300bf99ffe092a2c589484f Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <florian@openwrt.org>
+Date: Mon, 28 Jan 2013 20:06:21 +0100
+Subject: [PATCH 03/11] MIPS: BCM63XX: move code touching the USB private
+ register
+
+This patch moves the code touching the USB private register in the
+bcm63xx USB gadget driver to arch/mips/bcm63xx/usb-common.c in
+preparation for adding support for OHCI and EHCI host controllers which
+will also touch the USB private register.
+
+Signed-off-by: Florian Fainelli <florian@openwrt.org>
+---
+ arch/mips/bcm63xx/Makefile                         |    2 +-
+ arch/mips/bcm63xx/usb-common.c                     |   53 ++++++++++++++++++++
+ .../include/asm/mach-bcm63xx/bcm63xx_usb_priv.h    |    9 ++++
+ drivers/usb/gadget/bcm63xx_udc.c                   |   27 ++--------
+ 4 files changed, 67 insertions(+), 24 deletions(-)
+ create mode 100644 arch/mips/bcm63xx/usb-common.c
+ create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_usb_priv.h
+
+--- a/arch/mips/bcm63xx/Makefile
++++ b/arch/mips/bcm63xx/Makefile
+@@ -1,7 +1,7 @@
+ obj-y         += clk.o cpu.o cs.o gpio.o irq.o nvram.o prom.o reset.o \
+                  setup.o timer.o dev-dsp.o dev-enet.o dev-flash.o \
+                  dev-pcmcia.o dev-rng.o dev-spi.o dev-uart.o dev-wdt.o \
+-                 dev-usb-usbd.o
++                 dev-usb-usbd.o usb-common.o
+ obj-$(CONFIG_EARLY_PRINTK)    += early_printk.o
+ obj-y         += boards/
+--- /dev/null
++++ b/arch/mips/bcm63xx/usb-common.c
+@@ -0,0 +1,53 @@
++/*
++ * Broadcom BCM63xx common USB device configuration code
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2012 Kevin Cernekee <cernekee@gmail.com>
++ * Copyright (C) 2012 Broadcom Corporation
++ *
++ */
++#include <linux/export.h>
++
++#include <bcm63xx_cpu.h>
++#include <bcm63xx_regs.h>
++#include <bcm63xx_io.h>
++#include <bcm63xx_usb_priv.h>
++
++void bcm63xx_usb_priv_select_phy_mode(u32 portmask, bool is_device)
++{
++      u32 val;
++
++      val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG);
++      if (is_device) {
++              val |= (portmask << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT);
++              val |= (portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT);
++      } else {
++              val &= ~(portmask << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT);
++              val &= ~(portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT);
++      }
++      bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_UTMI_CTL_6368_REG);
++
++      val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG);
++      if (is_device)
++              val |= USBH_PRIV_SWAP_USBD_MASK;
++      else
++              val &= ~USBH_PRIV_SWAP_USBD_MASK;
++      bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_SWAP_6368_REG);
++}
++EXPORT_SYMBOL(bcm63xx_usb_priv_select_phy_mode);
++
++void bcm63xx_usb_priv_select_pullup(u32 portmask, bool is_on)
++{
++      u32 val;
++
++      val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG);
++      if (is_on)
++              val &= ~(portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT);
++      else
++              val |= (portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT);
++      bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_UTMI_CTL_6368_REG);
++}
++EXPORT_SYMBOL(bcm63xx_usb_priv_select_pullup);
+--- /dev/null
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_usb_priv.h
+@@ -0,0 +1,9 @@
++#ifndef BCM63XX_USB_PRIV_H_
++#define BCM63XX_USB_PRIV_H_
++
++#include <linux/types.h>
++
++void bcm63xx_usb_priv_select_phy_mode(u32 portmask, bool is_device);
++void bcm63xx_usb_priv_select_pullup(u32 portmask, bool is_on);
++
++#endif /* BCM63XX_USB_PRIV_H_ */
+--- a/drivers/usb/gadget/bcm63xx_udc.c
++++ b/drivers/usb/gadget/bcm63xx_udc.c
+@@ -41,6 +41,7 @@
+ #include <bcm63xx_dev_usb_usbd.h>
+ #include <bcm63xx_io.h>
+ #include <bcm63xx_regs.h>
++#include <bcm63xx_usb_priv.h>
+ #define DRV_MODULE_NAME               "bcm63xx_udc"
+@@ -863,22 +864,7 @@ static void bcm63xx_select_phy_mode(stru
+               bcm_gpio_writel(val, GPIO_PINMUX_OTHR_REG);
+       }
+-      val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG);
+-      if (is_device) {
+-              val |= (portmask << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT);
+-              val |= (portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT);
+-      } else {
+-              val &= ~(portmask << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT);
+-              val &= ~(portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT);
+-      }
+-      bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_UTMI_CTL_6368_REG);
+-
+-      val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG);
+-      if (is_device)
+-              val |= USBH_PRIV_SWAP_USBD_MASK;
+-      else
+-              val &= ~USBH_PRIV_SWAP_USBD_MASK;
+-      bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_SWAP_6368_REG);
++      bcm63xx_usb_priv_select_phy_mode(portmask, is_device);
+ }
+ /**
+@@ -892,14 +878,9 @@ static void bcm63xx_select_phy_mode(stru
+  */
+ static void bcm63xx_select_pullup(struct bcm63xx_udc *udc, bool is_on)
+ {
+-      u32 val, portmask = BIT(udc->pd->port_no);
++      u32 portmask = BIT(udc->pd->port_no);
+-      val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG);
+-      if (is_on)
+-              val &= ~(portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT);
+-      else
+-              val |= (portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT);
+-      bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_UTMI_CTL_6368_REG);
++      bcm63xx_usb_priv_select_pullup(portmask, is_on);
+ }
+ /**
diff --git a/target/linux/brcm63xx/patches-3.9/103-MIPS-BCM63XX-add-OHCI-EHCI-configuration-bits-to-com.patch b/target/linux/brcm63xx/patches-3.9/103-MIPS-BCM63XX-add-OHCI-EHCI-configuration-bits-to-com.patch
new file mode 100644 (file)
index 0000000..40bbe08
--- /dev/null
@@ -0,0 +1,169 @@
+From 28758a9da77954ed323f86123ef448c6a563c037 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <florian@openwrt.org>
+Date: Mon, 28 Jan 2013 20:06:22 +0100
+Subject: [PATCH 04/11] MIPS: BCM63XX: add OHCI/EHCI configuration bits to
+ common USB code
+
+This patch updates the common USB code touching the USB private
+registers with the specific bits to properly enable OHCI and EHCI
+controllers on BCM63xx SoCs. As a result we now need to protect access
+to Read Modify Write sequences using a spinlock because we cannot
+guarantee that any of the exposed helper will not be called
+concurrently.
+
+Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
+Signed-off-by: Florian Fainelli <florian@openwrt.org>
+---
+ arch/mips/bcm63xx/usb-common.c                     |   97 ++++++++++++++++++++
+ .../include/asm/mach-bcm63xx/bcm63xx_usb_priv.h    |    2 +
+ 2 files changed, 99 insertions(+)
+
+--- a/arch/mips/bcm63xx/usb-common.c
++++ b/arch/mips/bcm63xx/usb-common.c
+@@ -5,10 +5,12 @@
+  * License.  See the file "COPYING" in the main directory of this archive
+  * for more details.
+  *
++ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
+  * Copyright (C) 2012 Kevin Cernekee <cernekee@gmail.com>
+  * Copyright (C) 2012 Broadcom Corporation
+  *
+  */
++#include <linux/spinlock.h>
+ #include <linux/export.h>
+ #include <bcm63xx_cpu.h>
+@@ -16,9 +18,14 @@
+ #include <bcm63xx_io.h>
+ #include <bcm63xx_usb_priv.h>
++static DEFINE_SPINLOCK(usb_priv_reg_lock);
++
+ void bcm63xx_usb_priv_select_phy_mode(u32 portmask, bool is_device)
+ {
+       u32 val;
++      unsigned long flags;
++
++      spin_lock_irqsave(&usb_priv_reg_lock, flags);
+       val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG);
+       if (is_device) {
+@@ -36,12 +43,17 @@ void bcm63xx_usb_priv_select_phy_mode(u3
+       else
+               val &= ~USBH_PRIV_SWAP_USBD_MASK;
+       bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_SWAP_6368_REG);
++
++      spin_unlock_irqrestore(&usb_priv_reg_lock, flags);
+ }
+ EXPORT_SYMBOL(bcm63xx_usb_priv_select_phy_mode);
+ void bcm63xx_usb_priv_select_pullup(u32 portmask, bool is_on)
+ {
+       u32 val;
++      unsigned long flags;
++
++      spin_lock_irqsave(&usb_priv_reg_lock, flags);
+       val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG);
+       if (is_on)
+@@ -49,5 +61,90 @@ void bcm63xx_usb_priv_select_pullup(u32
+       else
+               val |= (portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT);
+       bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_UTMI_CTL_6368_REG);
++
++      spin_unlock_irqrestore(&usb_priv_reg_lock, flags);
+ }
+ EXPORT_SYMBOL(bcm63xx_usb_priv_select_pullup);
++
++/* The following array represents the meaning of the DESC/DATA
++ * endian swapping with respect to the CPU configured endianness
++ *
++ * DATA       ENDN    mmio    descriptor
++ * 0  0       BE      invalid
++ * 0  1       BE      LE
++ * 1  0       BE      BE
++ * 1  1       BE      invalid
++ *
++ * Since BCM63XX SoCs are configured to be in big-endian mode
++ * we want configuration at line 3.
++ */
++void bcm63xx_usb_priv_ohci_cfg_set(void)
++{
++      u32 reg;
++      unsigned long flags;
++
++      spin_lock_irqsave(&usb_priv_reg_lock, flags);
++
++      if (BCMCPU_IS_6348())
++              bcm_rset_writel(RSET_OHCI_PRIV, 0, OHCI_PRIV_REG);
++      else if (BCMCPU_IS_6358()) {
++              reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6358_REG);
++              reg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK;
++              reg |= USBH_PRIV_SWAP_OHCI_DATA_MASK;
++              bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6358_REG);
++              /*
++               * The magic value comes for the original vendor BSP
++               * and is needed for USB to work. Datasheet does not
++               * help, so the magic value is used as-is.
++               */
++              bcm_rset_writel(RSET_USBH_PRIV, 0x1c0020,
++                              USBH_PRIV_TEST_6358_REG);
++
++      } else if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) {
++              reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG);
++              reg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK;
++              reg |= USBH_PRIV_SWAP_OHCI_DATA_MASK;
++              bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6368_REG);
++
++              reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG);
++              reg |= USBH_PRIV_SETUP_IOC_MASK;
++              bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG);
++      }
++
++      spin_unlock_irqrestore(&usb_priv_reg_lock, flags);
++}
++
++void bcm63xx_usb_priv_ehci_cfg_set(void)
++{
++      u32 reg;
++      unsigned long flags;
++
++      spin_lock_irqsave(&usb_priv_reg_lock, flags);
++
++      if (BCMCPU_IS_6358()) {
++              reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6358_REG);
++              reg &= ~USBH_PRIV_SWAP_EHCI_ENDN_MASK;
++              reg |= USBH_PRIV_SWAP_EHCI_DATA_MASK;
++              bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6358_REG);
++
++              /*
++               * The magic value comes for the original vendor BSP
++               * and is needed for USB to work. Datasheet does not
++               * help, so the magic value is used as-is.
++               */
++              bcm_rset_writel(RSET_USBH_PRIV, 0x1c0020,
++                              USBH_PRIV_TEST_6358_REG);
++
++      } else if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) {
++              reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG);
++              reg &= ~USBH_PRIV_SWAP_EHCI_ENDN_MASK;
++              reg |= USBH_PRIV_SWAP_EHCI_DATA_MASK;
++              bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6368_REG);
++
++              reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG);
++              reg |= USBH_PRIV_SETUP_IOC_MASK;
++              bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG);
++      }
++
++      spin_unlock_irqrestore(&usb_priv_reg_lock, flags);
++}
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_usb_priv.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_usb_priv.h
+@@ -5,5 +5,7 @@
+ void bcm63xx_usb_priv_select_phy_mode(u32 portmask, bool is_device);
+ void bcm63xx_usb_priv_select_pullup(u32 portmask, bool is_on);
++void bcm63xx_usb_priv_ohci_cfg_set(void);
++void bcm63xx_usb_priv_ehci_cfg_set(void);
+ #endif /* BCM63XX_USB_PRIV_H_ */
diff --git a/target/linux/brcm63xx/patches-3.9/104-MIPS-BCM63XX-introduce-BCM63XX_OHCI-configuration-sy.patch b/target/linux/brcm63xx/patches-3.9/104-MIPS-BCM63XX-introduce-BCM63XX_OHCI-configuration-sy.patch
new file mode 100644 (file)
index 0000000..f2134ba
--- /dev/null
@@ -0,0 +1,67 @@
+From 94ec618bd1a6b07fafbbfc9bcc54e7f9360ff9a0 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <florian@openwrt.org>
+Date: Mon, 28 Jan 2013 20:06:23 +0100
+Subject: [PATCH 05/11] MIPS: BCM63XX: introduce BCM63XX_OHCI configuration
+ symbol
+
+This configuration symbol can be used by CPUs supporting the on-chip
+OHCI controller, and ensures that all relevant OHCI-related
+configuration options are correctly selected. So far, OHCI support is
+available for the 6328, 6348, 6358 and 6358 SoCs.
+
+Signed-off-by: Florian Fainelli <florian@openwrt.org>
+---
+ arch/mips/bcm63xx/Kconfig |   15 ++++++++++-----
+ 1 file changed, 10 insertions(+), 5 deletions(-)
+
+--- a/arch/mips/bcm63xx/Kconfig
++++ b/arch/mips/bcm63xx/Kconfig
+@@ -1,37 +1,43 @@
+ menu "CPU support"
+       depends on BCM63XX
++config BCM63XX_OHCI
++      bool
++      select USB_ARCH_HAS_OHCI
++      select USB_OHCI_BIG_ENDIAN_DESC if USB_OHCI_HCD
++      select USB_OHCI_BIG_ENDIAN_MMIO if USB_OHCI_HCD
++
+ config BCM63XX_CPU_6328
+       bool "support 6328 CPU"
+       select HW_HAS_PCI
++      select BCM63XX_OHCI
+ config BCM63XX_CPU_6338
+       bool "support 6338 CPU"
+       select HW_HAS_PCI
+-      select USB_ARCH_HAS_OHCI
+-      select USB_OHCI_BIG_ENDIAN_DESC
+-      select USB_OHCI_BIG_ENDIAN_MMIO
+ config BCM63XX_CPU_6345
+       bool "support 6345 CPU"
+-      select USB_OHCI_BIG_ENDIAN_DESC
+-      select USB_OHCI_BIG_ENDIAN_MMIO
+ config BCM63XX_CPU_6348
+       bool "support 6348 CPU"
+       select HW_HAS_PCI
++      select BCM63XX_OHCI
+ config BCM63XX_CPU_6358
+       bool "support 6358 CPU"
+       select HW_HAS_PCI
++      select BCM63XX_OHCI
+ config BCM63XX_CPU_6362
+       bool "support 6362 CPU"
+       select HW_HAS_PCI
++      select BCM63XX_OHCI
+ config BCM63XX_CPU_6368
+       bool "support 6368 CPU"
+       select HW_HAS_PCI
++      select BCM63XX_OHCI
+ endmenu
+ source "arch/mips/bcm63xx/boards/Kconfig"
diff --git a/target/linux/brcm63xx/patches-3.9/105-MIPS-BCM63XX-add-support-for-the-on-chip-OHCI-contro.patch b/target/linux/brcm63xx/patches-3.9/105-MIPS-BCM63XX-add-support-for-the-on-chip-OHCI-contro.patch
new file mode 100644 (file)
index 0000000..732fe94
--- /dev/null
@@ -0,0 +1,138 @@
+From 30d22baef255c99a12c4858ce4ab0d45f0d8c9ae Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <florian@openwrt.org>
+Date: Mon, 28 Jan 2013 20:06:24 +0100
+Subject: [PATCH 06/11] MIPS: BCM63XX: add support for the on-chip OHCI
+ controller
+
+Broadcom BCM63XX SoCs include an on-chip OHCI controller which can be
+driven by the ohci-platform generic driver by using specific power
+on/off/suspend callback to manage clocks and hardware specific
+configuration.
+
+Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
+Signed-off-by: Florian Fainelli <florian@openwrt.org>
+---
+ arch/mips/bcm63xx/Makefile                         |    2 +-
+ arch/mips/bcm63xx/dev-usb-ohci.c                   |   94 ++++++++++++++++++++
+ .../asm/mach-bcm63xx/bcm63xx_dev_usb_ohci.h        |    6 ++
+ 3 files changed, 101 insertions(+), 1 deletion(-)
+ create mode 100644 arch/mips/bcm63xx/dev-usb-ohci.c
+ create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ohci.h
+
+--- a/arch/mips/bcm63xx/Makefile
++++ b/arch/mips/bcm63xx/Makefile
+@@ -1,7 +1,7 @@
+ obj-y         += clk.o cpu.o cs.o gpio.o irq.o nvram.o prom.o reset.o \
+                  setup.o timer.o dev-dsp.o dev-enet.o dev-flash.o \
+                  dev-pcmcia.o dev-rng.o dev-spi.o dev-uart.o dev-wdt.o \
+-                 dev-usb-usbd.o usb-common.o
++                 dev-usb-ohci.o dev-usb-usbd.o usb-common.o
+ obj-$(CONFIG_EARLY_PRINTK)    += early_printk.o
+ obj-y         += boards/
+--- /dev/null
++++ b/arch/mips/bcm63xx/dev-usb-ohci.c
+@@ -0,0 +1,94 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
++ * Copyright (C) 2013 Florian Fainelli <florian@openwrt.org>
++ */
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/platform_device.h>
++#include <linux/usb/ohci_pdriver.h>
++#include <linux/dma-mapping.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++
++#include <bcm63xx_cpu.h>
++#include <bcm63xx_regs.h>
++#include <bcm63xx_io.h>
++#include <bcm63xx_usb_priv.h>
++#include <bcm63xx_dev_usb_ohci.h>
++
++static struct resource ohci_resources[] = {
++      {
++              .start          = -1, /* filled at runtime */
++              .end            = -1, /* filled at runtime */
++              .flags          = IORESOURCE_MEM,
++      },
++      {
++              .start          = -1, /* filled at runtime */
++              .flags          = IORESOURCE_IRQ,
++      },
++};
++
++static u64 ohci_dmamask = DMA_BIT_MASK(32);
++
++static struct clk *usb_host_clock;
++
++static int bcm63xx_ohci_power_on(struct platform_device *pdev)
++{
++      usb_host_clock = clk_get(&pdev->dev, "usbh");
++      if (IS_ERR_OR_NULL(usb_host_clock))
++              return -ENODEV;
++
++      clk_prepare_enable(usb_host_clock);
++
++      bcm63xx_usb_priv_ohci_cfg_set();
++
++      return 0;
++}
++
++static void bcm63xx_ohci_power_off(struct platform_device *pdev)
++{
++      if (!IS_ERR_OR_NULL(usb_host_clock)) {
++              clk_disable_unprepare(usb_host_clock);
++              clk_put(usb_host_clock);
++      }
++}
++
++static struct usb_ohci_pdata bcm63xx_ohci_pdata = {
++      .big_endian_desc        = 1,
++      .big_endian_mmio        = 1,
++      .no_big_frame_no        = 1,
++      .num_ports              = 1,
++      .power_on               = bcm63xx_ohci_power_on,
++      .power_off              = bcm63xx_ohci_power_off,
++      .power_suspend          = bcm63xx_ohci_power_off,
++};
++
++static struct platform_device bcm63xx_ohci_device = {
++      .name           = "ohci-platform",
++      .id             = -1,
++      .num_resources  = ARRAY_SIZE(ohci_resources),
++      .resource       = ohci_resources,
++      .dev            = {
++              .platform_data          = &bcm63xx_ohci_pdata,
++              .dma_mask               = &ohci_dmamask,
++              .coherent_dma_mask      = DMA_BIT_MASK(32),
++      },
++};
++
++int __init bcm63xx_ohci_register(void)
++{
++      if (BCMCPU_IS_6345() || BCMCPU_IS_6338())
++              return -ENODEV;
++
++      ohci_resources[0].start = bcm63xx_regset_address(RSET_OHCI0);
++      ohci_resources[0].end = ohci_resources[0].start;
++      ohci_resources[0].end += RSET_OHCI_SIZE - 1;
++      ohci_resources[1].start = bcm63xx_get_irq_number(IRQ_OHCI0);
++
++      return platform_device_register(&bcm63xx_ohci_device);
++}
+--- /dev/null
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ohci.h
+@@ -0,0 +1,6 @@
++#ifndef BCM63XX_DEV_USB_OHCI_H_
++#define BCM63XX_DEV_USB_OHCI_H_
++
++int bcm63xx_ohci_register(void);
++
++#endif /* BCM63XX_DEV_USB_OHCI_H_ */
diff --git a/target/linux/brcm63xx/patches-3.9/106-MIPS-BCM63XX-register-OHCI-controller-if-board-enabl.patch b/target/linux/brcm63xx/patches-3.9/106-MIPS-BCM63XX-register-OHCI-controller-if-board-enabl.patch
new file mode 100644 (file)
index 0000000..11dafd6
--- /dev/null
@@ -0,0 +1,36 @@
+From 33ef960aed15f9a98a2c51d8d794cd72418e0be4 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <florian@openwrt.org>
+Date: Mon, 28 Jan 2013 20:06:25 +0100
+Subject: [PATCH 07/11] MIPS: BCM63XX: register OHCI controller if board
+ enables it
+
+BCM63XX-based boards can control the registration of the OHCI controller
+by setting their has_ohci0 flag to 1. Handle this in the generic
+code dealing with board registration and call the actual helper to
+register the OHCI controller.
+
+Signed-off-by: Florian Fainelli <florian@openwrt.org>
+---
+ arch/mips/bcm63xx/boards/board_bcm963xx.c |    4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+@@ -25,6 +25,7 @@
+ #include <bcm63xx_dev_flash.h>
+ #include <bcm63xx_dev_pcmcia.h>
+ #include <bcm63xx_dev_spi.h>
++#include <bcm63xx_dev_usb_ohci.h>
+ #include <bcm63xx_dev_usb_usbd.h>
+ #include <board_bcm963xx.h>
+@@ -848,6 +849,9 @@ int __init board_register_devices(void)
+       if (board.has_usbd)
+               bcm63xx_usbd_register(&board.usbd);
++      if (board.has_ohci0)
++              bcm63xx_ohci_register();
++
+       if (board.has_dsp)
+               bcm63xx_dsp_register(&board.dsp);
diff --git a/target/linux/brcm63xx/patches-3.9/107-MIPS-BCM63XX-introduce-BCM63XX_EHCI-configuration-sy.patch b/target/linux/brcm63xx/patches-3.9/107-MIPS-BCM63XX-introduce-BCM63XX_EHCI-configuration-sy.patch
new file mode 100644 (file)
index 0000000..104ff3c
--- /dev/null
@@ -0,0 +1,79 @@
+From 00da1683364e58c6430a4577123d01037f8faddc Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <florian@openwrt.org>
+Date: Mon, 28 Jan 2013 20:06:26 +0100
+Subject: [PATCH 08/11] MIPS: BCM63XX: introduce BCM63XX_EHCI configuration
+ symbol
+
+This configuration symbol can be used by CPUs supporting the on-chip
+EHCI controller, and ensures that all relevant EHCI-related
+configuration options are selected. So far BCM6328, BCM6358 and BCM6368
+have an EHCI controller and do select this symbol. Update
+drivers/usb/host/Kconfig with BCM63XX to update direct unmet
+dependencies.
+
+Signed-off-by: Florian Fainelli <florian@openwrt.org>
+---
+ arch/mips/bcm63xx/Kconfig |    9 +++++++++
+ drivers/usb/host/Kconfig  |    5 +++--
+ 2 files changed, 12 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/bcm63xx/Kconfig
++++ b/arch/mips/bcm63xx/Kconfig
+@@ -7,10 +7,17 @@ config BCM63XX_OHCI
+       select USB_OHCI_BIG_ENDIAN_DESC if USB_OHCI_HCD
+       select USB_OHCI_BIG_ENDIAN_MMIO if USB_OHCI_HCD
++config BCM63XX_EHCI
++      bool
++      select USB_ARCH_HAS_EHCI
++      select USB_EHCI_BIG_ENDIAN_DESC if USB_EHCI_HCD
++      select USB_EHCI_BIG_ENDIAN_MMIO if USB_EHCI_HCD
++
+ config BCM63XX_CPU_6328
+       bool "support 6328 CPU"
+       select HW_HAS_PCI
+       select BCM63XX_OHCI
++      select BCM63XX_EHCI
+ config BCM63XX_CPU_6338
+       bool "support 6338 CPU"
+@@ -28,16 +35,19 @@ config BCM63XX_CPU_6358
+       bool "support 6358 CPU"
+       select HW_HAS_PCI
+       select BCM63XX_OHCI
++      select BCM63XX_EHCI
+ config BCM63XX_CPU_6362
+       bool "support 6362 CPU"
+       select HW_HAS_PCI
+       select BCM63XX_OHCI
++      select BCM63XX_EHCI
+ config BCM63XX_CPU_6368
+       bool "support 6368 CPU"
+       select HW_HAS_PCI
+       select BCM63XX_OHCI
++      select BCM63XX_EHCI
+ endmenu
+ source "arch/mips/bcm63xx/boards/Kconfig"
+--- a/drivers/usb/host/Kconfig
++++ b/drivers/usb/host/Kconfig
+@@ -115,14 +115,15 @@ config USB_EHCI_BIG_ENDIAN_MMIO
+       depends on USB_EHCI_HCD && (PPC_CELLEB || PPC_PS3 || 440EPX || \
+                                   ARCH_IXP4XX || XPS_USB_HCD_XILINX || \
+                                   PPC_MPC512x || CPU_CAVIUM_OCTEON || \
+-                                  PMC_MSP || SPARC_LEON || MIPS_SEAD3)
++                                  PMC_MSP || SPARC_LEON || MIPS_SEAD3 || \
++                                  BCM63XX)
+       default y
+ config USB_EHCI_BIG_ENDIAN_DESC
+       bool
+       depends on USB_EHCI_HCD && (440EPX || ARCH_IXP4XX || XPS_USB_HCD_XILINX || \
+                                   PPC_MPC512x || PMC_MSP || SPARC_LEON || \
+-                                  MIPS_SEAD3)
++                                  MIPS_SEAD3 || BCM63XX)
+       default y
+ config XPS_USB_HCD_XILINX
diff --git a/target/linux/brcm63xx/patches-3.9/108-MIPS-BCM63XX-add-support-for-the-on-chip-EHCI-contro.patch b/target/linux/brcm63xx/patches-3.9/108-MIPS-BCM63XX-add-support-for-the-on-chip-EHCI-contro.patch
new file mode 100644 (file)
index 0000000..ef4ba17
--- /dev/null
@@ -0,0 +1,136 @@
+From e38f13bd6408769c0b565bb1079024f496eee121 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <florian@openwrt.org>
+Date: Mon, 28 Jan 2013 20:06:27 +0100
+Subject: [PATCH 09/11] MIPS: BCM63XX: add support for the on-chip EHCI
+ controller
+
+Broadcom BCM63XX SoCs include an on-chip EHCI controller which can be
+driven by the generic ehci-platform driver by using specific power
+on/off/suspend callbacks to manage clocks and hardware specific
+configuration.
+
+Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
+Signed-off-by: Florian Fainelli <florian@openwrt.org>
+---
+ arch/mips/bcm63xx/Makefile                         |    2 +-
+ arch/mips/bcm63xx/dev-usb-ehci.c                   |   92 ++++++++++++++++++++
+ .../asm/mach-bcm63xx/bcm63xx_dev_usb_ehci.h        |    6 ++
+ 3 files changed, 99 insertions(+), 1 deletion(-)
+ create mode 100644 arch/mips/bcm63xx/dev-usb-ehci.c
+ create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ehci.h
+
+--- a/arch/mips/bcm63xx/Makefile
++++ b/arch/mips/bcm63xx/Makefile
+@@ -1,7 +1,7 @@
+ obj-y         += clk.o cpu.o cs.o gpio.o irq.o nvram.o prom.o reset.o \
+                  setup.o timer.o dev-dsp.o dev-enet.o dev-flash.o \
+                  dev-pcmcia.o dev-rng.o dev-spi.o dev-uart.o dev-wdt.o \
+-                 dev-usb-ohci.o dev-usb-usbd.o usb-common.o
++                 dev-usb-ehci.o dev-usb-ohci.o dev-usb-usbd.o usb-common.o
+ obj-$(CONFIG_EARLY_PRINTK)    += early_printk.o
+ obj-y         += boards/
+--- /dev/null
++++ b/arch/mips/bcm63xx/dev-usb-ehci.c
+@@ -0,0 +1,92 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
++ * Copyright (C) 2013 Florian Fainelli <florian@openwrt.org>
++ */
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/platform_device.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/usb/ehci_pdriver.h>
++#include <linux/dma-mapping.h>
++
++#include <bcm63xx_cpu.h>
++#include <bcm63xx_regs.h>
++#include <bcm63xx_io.h>
++#include <bcm63xx_usb_priv.h>
++#include <bcm63xx_dev_usb_ehci.h>
++
++static struct resource ehci_resources[] = {
++      {
++              .start          = -1, /* filled at runtime */
++              .end            = -1, /* filled at runtime */
++              .flags          = IORESOURCE_MEM,
++      },
++      {
++              .start          = -1, /* filled at runtime */
++              .flags          = IORESOURCE_IRQ,
++      },
++};
++
++static u64 ehci_dmamask = DMA_BIT_MASK(32);
++
++static struct clk *usb_host_clock;
++
++static int bcm63xx_ehci_power_on(struct platform_device *pdev)
++{
++      usb_host_clock = clk_get(&pdev->dev, "usbh");
++      if (IS_ERR_OR_NULL(usb_host_clock))
++              return -ENODEV;
++
++      clk_prepare_enable(usb_host_clock);
++
++      bcm63xx_usb_priv_ehci_cfg_set();
++
++      return 0;
++}
++
++static void bcm63xx_ehci_power_off(struct platform_device *pdev)
++{
++      if (!IS_ERR_OR_NULL(usb_host_clock)) {
++              clk_disable_unprepare(usb_host_clock);
++              clk_put(usb_host_clock);
++      }
++}
++
++static struct usb_ehci_pdata bcm63xx_ehci_pdata = {
++      .big_endian_desc        = 1,
++      .big_endian_mmio        = 1,
++      .power_on               = bcm63xx_ehci_power_on,
++      .power_off              = bcm63xx_ehci_power_off,
++      .power_suspend          = bcm63xx_ehci_power_off,
++};
++
++static struct platform_device bcm63xx_ehci_device = {
++      .name           = "ehci-platform",
++      .id             = -1,
++      .num_resources  = ARRAY_SIZE(ehci_resources),
++      .resource       = ehci_resources,
++      .dev            = {
++              .platform_data          = &bcm63xx_ehci_pdata,
++              .dma_mask               = &ehci_dmamask,
++              .coherent_dma_mask      = DMA_BIT_MASK(32),
++      },
++};
++
++int __init bcm63xx_ehci_register(void)
++{
++      if (!BCMCPU_IS_6328() && !BCMCPU_IS_6358() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368())
++              return 0;
++
++      ehci_resources[0].start = bcm63xx_regset_address(RSET_EHCI0);
++      ehci_resources[0].end = ehci_resources[0].start;
++      ehci_resources[0].end += RSET_EHCI_SIZE - 1;
++      ehci_resources[1].start = bcm63xx_get_irq_number(IRQ_EHCI0);
++
++      return platform_device_register(&bcm63xx_ehci_device);
++}
+--- /dev/null
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ehci.h
+@@ -0,0 +1,6 @@
++#ifndef BCM63XX_DEV_USB_EHCI_H_
++#define BCM63XX_DEV_USB_EHCI_H_
++
++int bcm63xx_ehci_register(void);
++
++#endif /* BCM63XX_DEV_USB_EHCI_H_ */
diff --git a/target/linux/brcm63xx/patches-3.9/109-MIPS-BCM63XX-register-EHCI-controller-if-board-enabl.patch b/target/linux/brcm63xx/patches-3.9/109-MIPS-BCM63XX-register-EHCI-controller-if-board-enabl.patch
new file mode 100644 (file)
index 0000000..703f2a4
--- /dev/null
@@ -0,0 +1,36 @@
+From 709ef2034f5ba06da35f89856ad7baf2b7a41287 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <florian@openwrt.org>
+Date: Mon, 28 Jan 2013 20:06:28 +0100
+Subject: [PATCH 10/11] MIPS: BCM63XX: register EHCI controller if board
+ enables it
+
+BCM63XX-based board can control the registration of the EHCI controller
+by setting their has_ehci0 flag to 1. Handle this in the generic
+code dealing with board registration and call the actual helper to register
+the EHCI controller.
+
+Signed-off-by: Florian Fainelli <florian@openwrt.org>
+---
+ arch/mips/bcm63xx/boards/board_bcm963xx.c |    4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+@@ -25,6 +25,7 @@
+ #include <bcm63xx_dev_flash.h>
+ #include <bcm63xx_dev_pcmcia.h>
+ #include <bcm63xx_dev_spi.h>
++#include <bcm63xx_dev_usb_ehci.h>
+ #include <bcm63xx_dev_usb_ohci.h>
+ #include <bcm63xx_dev_usb_usbd.h>
+ #include <board_bcm963xx.h>
+@@ -849,6 +850,9 @@ int __init board_register_devices(void)
+       if (board.has_usbd)
+               bcm63xx_usbd_register(&board.usbd);
++      if (board.has_ehci0)
++              bcm63xx_ehci_register();
++
+       if (board.has_ohci0)
+               bcm63xx_ohci_register();
diff --git a/target/linux/brcm63xx/patches-3.9/110-MIPS-BCM63XX-EHCI-controller-does-not-support-overcu.patch b/target/linux/brcm63xx/patches-3.9/110-MIPS-BCM63XX-EHCI-controller-does-not-support-overcu.patch
new file mode 100644 (file)
index 0000000..6d91129
--- /dev/null
@@ -0,0 +1,24 @@
+From 111bbd770441ab34f9da5bb1d85767a9b75227b4 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <florian@openwrt.org>
+Date: Mon, 28 Jan 2013 20:06:30 +0100
+Subject: [PATCH 12/12] MIPS: BCM63XX: EHCI controller does not support
+ overcurrent
+
+This patch sets the ignore_oc flag for the BCM63XX EHCI controller as it
+does not support proper overcurrent reporting.
+
+Signed-off-by: Florian Fainelli <florian@openwrt.org>
+---
+ arch/mips/bcm63xx/dev-usb-ehci.c |    1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/mips/bcm63xx/dev-usb-ehci.c
++++ b/arch/mips/bcm63xx/dev-usb-ehci.c
+@@ -61,6 +61,7 @@ static void bcm63xx_ehci_power_off(struc
+ static struct usb_ehci_pdata bcm63xx_ehci_pdata = {
+       .big_endian_desc        = 1,
+       .big_endian_mmio        = 1,
++      .ignore_oc              = 1,
+       .power_on               = bcm63xx_ehci_power_on,
+       .power_off              = bcm63xx_ehci_power_off,
+       .power_suspend          = bcm63xx_ehci_power_off,
diff --git a/target/linux/brcm63xx/patches-3.9/201-SPI-Allow-specifying-the-parsers-for-SPI-flash.patch b/target/linux/brcm63xx/patches-3.9/201-SPI-Allow-specifying-the-parsers-for-SPI-flash.patch
new file mode 100644 (file)
index 0000000..00dc9c9
--- /dev/null
@@ -0,0 +1,38 @@
+From 3f650fc30aa0badf9d02842ce396cea3eef2eeaa Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jonas.gorski@gmail.com>
+Date: Fri, 1 Jul 2011 23:16:47 +0200
+Subject: [PATCH 49/79] SPI: Allow specifying the parsers for SPI flash
+
+Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
+---
+ include/linux/spi/flash.h |    5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/include/linux/spi/flash.h
++++ b/include/linux/spi/flash.h
+@@ -2,7 +2,7 @@
+ #define LINUX_SPI_FLASH_H
+ struct mtd_partition;
+-
++struct mtd_part_parser_data;
+ /**
+  * struct flash_platform_data: board-specific flash data
+  * @name: optional flash device name (eg, as used with mtdparts=)
+@@ -10,6 +10,8 @@ struct mtd_partition;
+  * @nr_parts: number of mtd_partitions for static partitoning
+  * @type: optional flash device type (e.g. m25p80 vs m25p64), for use
+  *    with chips that can't be queried for JEDEC or other IDs
++ * @part_probe_types: optional list of MTD parser names to use for
++ *    partitioning
+  *
+  * Board init code (in arch/.../mach-xxx/board-yyy.c files) can
+  * provide information about SPI flash parts (such as DataFlash) to
+@@ -25,6 +27,7 @@ struct flash_platform_data {
+       char            *type;
++      const char      **part_probe_types;
+       /* we'll likely add more ... use JEDEC IDs, etc */
+ };
diff --git a/target/linux/brcm63xx/patches-3.9/202-MTD-DEVICES-m25p80-use-parsers-if-provided-in-flash-.patch b/target/linux/brcm63xx/patches-3.9/202-MTD-DEVICES-m25p80-use-parsers-if-provided-in-flash-.patch
new file mode 100644 (file)
index 0000000..b5df076
--- /dev/null
@@ -0,0 +1,23 @@
+From c7c3c338cb25d7f55ddb3f6bfbf3572758ca3896 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jonas.gorski@gmail.com>
+Date: Thu, 10 Nov 2011 16:53:08 +0100
+Subject: [PATCH 50/79] MTD: DEVICES: m25p80: use parsers if provided in flash
+ platform data
+
+Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
+---
+ drivers/mtd/devices/m25p80.c |    3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/mtd/devices/m25p80.c
++++ b/drivers/mtd/devices/m25p80.c
+@@ -1088,7 +1088,8 @@ static int m25p_probe(struct spi_device
+       /* partitions should match sector boundaries; and it may be good to
+        * use readonly partitions for writeprotected sectors (BP2..BP0).
+        */
+-      return mtd_device_parse_register(&flash->mtd, NULL, &ppdata,
++      return mtd_device_parse_register(&flash->mtd,
++                      data ? data->part_probe_types : NULL, &ppdata,
+                       data ? data->parts : NULL,
+                       data ? data->nr_parts : 0);
+ }
diff --git a/target/linux/brcm63xx/patches-3.9/203-MTD-DEVICES-m25p80-add-support-for-limiting-reads.patch b/target/linux/brcm63xx/patches-3.9/203-MTD-DEVICES-m25p80-add-support-for-limiting-reads.patch
new file mode 100644 (file)
index 0000000..7ac1b2f
--- /dev/null
@@ -0,0 +1,92 @@
+From 5fb4e8d7287ac8fcb33aae8b1e9e22c5a3c392bd Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jonas.gorski@gmail.com>
+Date: Thu, 10 Nov 2011 17:33:40 +0100
+Subject: [PATCH 51/79] MTD: DEVICES: m25p80: add support for limiting reads
+
+Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
+---
+ drivers/mtd/devices/m25p80.c |   29 +++++++++++++++++++++++++++--
+ include/linux/spi/flash.h    |    4 ++++
+ 2 files changed, 31 insertions(+), 2 deletions(-)
+
+--- a/drivers/mtd/devices/m25p80.c
++++ b/drivers/mtd/devices/m25p80.c
+@@ -93,6 +93,7 @@ struct m25p {
+       u8                      erase_opcode;
+       u8                      *command;
+       bool                    fast_read;
++      int                     max_transfer_len;
+ };
+ static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
+@@ -337,10 +338,9 @@ static int m25p80_erase(struct mtd_info
+  * Read an address range from the flash chip.  The address range
+  * may be any size provided it is within the physical boundaries.
+  */
+-static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
++static int __m25p80_read(struct m25p *flash, loff_t from, size_t len,
+       size_t *retlen, u_char *buf)
+ {
+-      struct m25p *flash = mtd_to_m25p(mtd);
+       struct spi_transfer t[2];
+       struct spi_message m;
+       uint8_t opcode;
+@@ -392,6 +392,28 @@ static int m25p80_read(struct mtd_info *
+       return 0;
+ }
++static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
++      size_t *retlen, u_char *buf)
++{
++      struct m25p *flash = mtd_to_m25p(mtd);
++      size_t off;
++      size_t read_len = flash->max_transfer_len;
++      size_t part_len;
++      int ret = 0;
++
++      if (!read_len)
++              return __m25p80_read(flash, from, len, retlen, buf);
++
++      *retlen = 0;
++
++      for (off = 0; off < len && !ret; off += read_len) {
++              ret = __m25p80_read(flash, from + off, min(len - off, read_len),
++                                  &part_len, buf + off);
++                      *retlen += part_len;
++      }
++
++      return ret;
++}
+ /*
+  * Write an address range to the flash chip.  Data must be written in
+  * FLASH_PAGESIZE chunks.  The address range may be any size provided
+@@ -983,6 +1005,9 @@ static int m25p_probe(struct spi_device
+               return -ENOMEM;
+       }
++      if (data)
++              flash->max_transfer_len = data->max_transfer_len;
++
+       flash->spi = spi;
+       mutex_init(&flash->lock);
+       dev_set_drvdata(&spi->dev, flash);
+--- a/include/linux/spi/flash.h
++++ b/include/linux/spi/flash.h
+@@ -13,6 +13,8 @@ struct mtd_part_parser_data;
+  * @part_probe_types: optional list of MTD parser names to use for
+  *    partitioning
+  *
++ * @max_transfer_len: option maximum read/write length limitation for
++ *    SPI controllers not able to transfer any length commands.
+  * Board init code (in arch/.../mach-xxx/board-yyy.c files) can
+  * provide information about SPI flash parts (such as DataFlash) to
+  * help set up the device and its appropriate default partitioning.
+@@ -28,6 +30,8 @@ struct flash_platform_data {
+       char            *type;
+       const char      **part_probe_types;
++
++      unsigned int    max_transfer_len;
+       /* we'll likely add more ... use JEDEC IDs, etc */
+ };
diff --git a/target/linux/brcm63xx/patches-3.9/300-reset_buttons.patch b/target/linux/brcm63xx/patches-3.9/300-reset_buttons.patch
new file mode 100644 (file)
index 0000000..4415836
--- /dev/null
@@ -0,0 +1,116 @@
+--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+@@ -12,6 +12,8 @@
+ #include <linux/string.h>
+ #include <linux/platform_device.h>
+ #include <linux/ssb/ssb.h>
++#include <linux/gpio_keys.h>
++#include <linux/input.h>
+ #include <asm/addrspace.h>
+ #include <bcm63xx_board.h>
+ #include <bcm63xx_cpu.h>
+@@ -32,6 +34,9 @@
+ #define PFX   "board_bcm963xx: "
++#define BCM963XX_KEYS_POLL_INTERVAL   20
++#define BCM963XX_KEYS_DEBOUNCE_INTERVAL       (BCM963XX_KEYS_POLL_INTERVAL * 3)
++
+ static struct board_info board;
+ /*
+@@ -343,6 +348,16 @@ static struct board_info __initdata boar
+                       .active_low     = 1,
+               },
+       },
++      .buttons = {
++              {
++                      .desc           = "reset",
++                      .gpio           = 33,
++                      .active_low     = 1,
++                      .type           = EV_KEY,
++                      .code           = KEY_RESTART,
++                      .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL,
++              },
++      },
+ };
+ static struct board_info __initdata board_96348gw = {
+@@ -401,6 +416,16 @@ static struct board_info __initdata boar
+                       .active_low     = 1,
+               },
+       },
++      .buttons = {
++              {
++                      .desc           = "reset",
++                      .gpio           = 36,
++                      .active_low     = 1,
++                      .type           = EV_KEY,
++                      .code           = KEY_RESTART,
++                      .debounce_interval = BCM963XX_KEYS_DEBOUNCE_INTERVAL,
++              },
++      },
+ };
+ static struct board_info __initdata board_FAST2404 = {
+@@ -825,11 +850,23 @@ static struct platform_device bcm63xx_gp
+       .dev.platform_data      = &bcm63xx_led_data,
+ };
++static struct gpio_keys_platform_data bcm63xx_gpio_keys_data = {
++      .poll_interval  = BCM963XX_KEYS_POLL_INTERVAL,
++};
++
++static struct platform_device bcm63xx_gpio_keys_device = {
++      .name           = "gpio-keys-polled",
++      .id             = 0,
++      .dev.platform_data = &bcm63xx_gpio_keys_data,
++};
++
+ /*
+  * third stage init callback, register all board devices.
+  */
+ int __init board_register_devices(void)
+ {
++      int button_count = 0;
++
+       if (board.has_uart0)
+               bcm63xx_uart_register(0);
+@@ -881,5 +918,16 @@ int __init board_register_devices(void)
+       platform_device_register(&bcm63xx_gpio_leds);
++      /* count number of BUTTONs defined by this device */
++      while (button_count < ARRAY_SIZE(board.buttons) && board.buttons[button_count].desc)
++              button_count++;
++
++      if (button_count) {
++              bcm63xx_gpio_keys_data.nbuttons = button_count;
++              bcm63xx_gpio_keys_data.buttons = board.buttons;
++
++              platform_device_register(&bcm63xx_gpio_keys_device);
++      }
++
+       return 0;
+ }
+--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
+@@ -3,6 +3,7 @@
+ #include <linux/types.h>
+ #include <linux/gpio.h>
++#include <linux/gpio_keys.h>
+ #include <linux/leds.h>
+ #include <bcm63xx_dev_enet.h>
+ #include <bcm63xx_dev_usb_usbd.h>
+@@ -45,6 +46,9 @@ struct board_info {
+       /* GPIO LEDs */
+       struct gpio_led leds[5];
++
++      /* Buttons */
++      struct gpio_keys_button buttons[4];
+ };
+ #endif /* ! BOARD_BCM963XX_H_ */
diff --git a/target/linux/brcm63xx/patches-3.9/301-led_count.patch b/target/linux/brcm63xx/patches-3.9/301-led_count.patch
new file mode 100644 (file)
index 0000000..c85405a
--- /dev/null
@@ -0,0 +1,41 @@
+--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+@@ -866,6 +866,7 @@ static struct platform_device bcm63xx_gp
+ int __init board_register_devices(void)
+ {
+       int button_count = 0;
++      int led_count = 0;
+       if (board.has_uart0)
+               bcm63xx_uart_register(0);
+@@ -913,10 +914,16 @@ int __init board_register_devices(void)
+       bcm63xx_flash_register();
+-      bcm63xx_led_data.num_leds = ARRAY_SIZE(board.leds);
+-      bcm63xx_led_data.leds = board.leds;
++      /* count number of LEDs defined by this device */
++      while (led_count < ARRAY_SIZE(board.leds) && board.leds[led_count].name)
++              led_count++;
++
++      if (led_count) {
++              bcm63xx_led_data.num_leds = led_count;
++              bcm63xx_led_data.leds = board.leds;
+-      platform_device_register(&bcm63xx_gpio_leds);
++              platform_device_register(&bcm63xx_gpio_leds);
++      }
+       /* count number of BUTTONs defined by this device */
+       while (button_count < ARRAY_SIZE(board.buttons) && board.buttons[button_count].desc)
+--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
+@@ -45,7 +45,7 @@ struct board_info {
+       struct bcm63xx_dsp_platform_data dsp;
+       /* GPIO LEDs */
+-      struct gpio_led leds[5];
++      struct gpio_led leds[14];
+       /* Buttons */
+       struct gpio_keys_button buttons[4];
diff --git a/target/linux/brcm63xx/patches-3.9/302-extended-platform-devices.patch b/target/linux/brcm63xx/patches-3.9/302-extended-platform-devices.patch
new file mode 100644 (file)
index 0000000..54cddc4
--- /dev/null
@@ -0,0 +1,25 @@
+--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+@@ -912,6 +912,9 @@ int __init board_register_devices(void)
+       bcm63xx_spi_register();
++      if (board.num_devs)
++              platform_add_devices(board.devs, board.num_devs);
++
+       bcm63xx_flash_register();
+       /* count number of LEDs defined by this device */
+--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
+@@ -49,6 +49,10 @@ struct board_info {
+       /* Buttons */
+       struct gpio_keys_button buttons[4];
++
++      /* Additional platform devices */
++      struct platform_device **devs;
++      unsigned int    num_devs;
+ };
+ #endif /* ! BOARD_BCM963XX_H_ */
diff --git a/target/linux/brcm63xx/patches-3.9/303-spi-board-info.patch b/target/linux/brcm63xx/patches-3.9/303-spi-board-info.patch
new file mode 100644 (file)
index 0000000..a1ba0cc
--- /dev/null
@@ -0,0 +1,33 @@
+--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+@@ -14,6 +14,7 @@
+ #include <linux/ssb/ssb.h>
+ #include <linux/gpio_keys.h>
+ #include <linux/input.h>
++#include <linux/spi/spi.h>
+ #include <asm/addrspace.h>
+ #include <bcm63xx_board.h>
+ #include <bcm63xx_cpu.h>
+@@ -915,6 +916,9 @@ int __init board_register_devices(void)
+       if (board.num_devs)
+               platform_add_devices(board.devs, board.num_devs);
++      if (board.num_spis)
++              spi_register_board_info(board.spis, board.num_spis);
++
+       bcm63xx_flash_register();
+       /* count number of LEDs defined by this device */
+--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
+@@ -53,6 +53,10 @@ struct board_info {
+       /* Additional platform devices */
+       struct platform_device **devs;
+       unsigned int    num_devs;
++
++      /* Additional platform devices */
++      struct spi_board_info *spis;
++      unsigned int    num_spis;
+ };
+ #endif /* ! BOARD_BCM963XX_H_ */
diff --git a/target/linux/brcm63xx/patches-3.9/304-boardid_fixup.patch b/target/linux/brcm63xx/patches-3.9/304-boardid_fixup.patch
new file mode 100644 (file)
index 0000000..f29ad6f
--- /dev/null
@@ -0,0 +1,62 @@
+--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+@@ -33,11 +33,16 @@
+ #include <bcm63xx_dev_usb_usbd.h>
+ #include <board_bcm963xx.h>
++#include <uapi/linux/bcm963xx_tag.h>
++
+ #define PFX   "board_bcm963xx: "
+ #define BCM963XX_KEYS_POLL_INTERVAL   20
+ #define BCM963XX_KEYS_DEBOUNCE_INTERVAL       (BCM963XX_KEYS_POLL_INTERVAL * 3)
++#define CFE_OFFSET_64K                        0x10000
++#define CFE_OFFSET_128K                       0x20000
++
+ static struct board_info board;
+ /*
+@@ -742,6 +747,30 @@ const char *board_get_name(void)
+       return board.name;
+ }
++static void __init boardid_fixup(u8 *boot_addr)
++{
++      struct bcm_tag *tag = (struct bcm_tag *)(boot_addr + CFE_OFFSET_64K);
++      char *board_name = (char *)bcm63xx_nvram_get_name();
++
++      /* check if bcm_tag is at 64k offset */
++      if (strncmp(board_name, tag->board_id, BOARDID_LEN) != 0) {
++              /* else try 128k */
++              tag = (struct bcm_tag *)(boot_addr + CFE_OFFSET_128K);
++              if (strncmp(board_name, tag->board_id, BOARDID_LEN) != 0) {
++                      /* No tag found */
++                      printk(KERN_DEBUG "No bcm_tag found!\n");
++                      return;
++              }
++      }
++      /* check if we should override the boardid */
++      if (tag->information1[0] != '+')
++              return;
++
++      strncpy(board_name, &tag->information1[1], BOARDID_LEN);
++
++      printk(KERN_INFO "Overriding boardid with '%s'\n", board_name);
++}
++
+ /*
+  * early init callback, read nvram data from flash and checksum it
+  */
+@@ -775,6 +804,11 @@ void __init board_prom_init(void)
+       bcm63xx_nvram_init(boot_addr + BCM963XX_NVRAM_OFFSET);
++      if (strcmp(cfe_version, "unknown") != 0) {
++              /* cfe present */
++              boardid_fixup(boot_addr);
++      }
++
+       board_name = bcm63xx_nvram_get_name();
+       /* find board by name */
+       for (i = 0; i < ARRAY_SIZE(bcm963xx_boards); i++) {
diff --git a/target/linux/brcm63xx/patches-3.9/305-MIPS-BCM63XX-allow-second-UART-on-BCM6328.patch b/target/linux/brcm63xx/patches-3.9/305-MIPS-BCM63XX-allow-second-UART-on-BCM6328.patch
new file mode 100644 (file)
index 0000000..1418d65
--- /dev/null
@@ -0,0 +1,22 @@
+From c110865541e2d3782c412af9d48c016de5a64d9c Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jonas.gorski@gmail.com>
+Date: Tue, 14 Jun 2011 21:14:39 +0200
+Subject: [PATCH 42/79] MIPS: BCM63XX: allow second UART on BCM6328
+
+Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
+---
+ arch/mips/bcm63xx/dev-uart.c |    3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/bcm63xx/dev-uart.c
++++ b/arch/mips/bcm63xx/dev-uart.c
+@@ -54,7 +54,8 @@ int __init bcm63xx_uart_register(unsigne
+       if (id >= ARRAY_SIZE(bcm63xx_uart_devices))
+               return -ENODEV;
+-      if (id == 1 && (!BCMCPU_IS_6358() && !BCMCPU_IS_6368()))
++      if (id == 1 && !BCMCPU_IS_6328() && !BCMCPU_IS_6358() &&
++          !BCMCPU_IS_6368())
+               return -ENODEV;
+       if (id == 0) {
diff --git a/target/linux/brcm63xx/patches-3.9/306-MIPS-BCM63XX-expose-the-HS-SPI-clock.patch b/target/linux/brcm63xx/patches-3.9/306-MIPS-BCM63XX-expose-the-HS-SPI-clock.patch
new file mode 100644 (file)
index 0000000..6b3b980
--- /dev/null
@@ -0,0 +1,48 @@
+From 5aeb6273a610f8aab090b3499827177eb41311ba Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jonas.gorski@gmail.com>
+Date: Sat, 12 Nov 2011 12:19:09 +0100
+Subject: [PATCH 53/79] MIPS: BCM63XX: expose the HS SPI clock
+
+Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
+---
+ arch/mips/bcm63xx/clk.c |   22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+--- a/arch/mips/bcm63xx/clk.c
++++ b/arch/mips/bcm63xx/clk.c
+@@ -236,6 +236,26 @@ static struct clk clk_spi = {
+ };
+ /*
++ * SPI clock
++ */
++static void hsspi_set(struct clk *clk, int enable)
++{
++      u32 mask;
++
++      if (BCMCPU_IS_6328())
++              mask = CKCTL_6328_HSSPI_EN;
++      else
++              return;
++
++      bcm_hwclock_set(mask, enable);
++}
++
++static struct clk clk_hsspi = {
++      .set    = hsspi_set,
++};
++
++
++/*
+  * XTM clock
+  */
+ static void xtm_set(struct clk *clk, int enable)
+@@ -344,6 +364,8 @@ struct clk *clk_get(struct device *dev,
+               return &clk_usbd;
+       if (!strcmp(id, "spi"))
+               return &clk_spi;
++      if (!strcmp(id, "hsspi"))
++              return &clk_hsspi;
+       if (!strcmp(id, "xtm"))
+               return &clk_xtm;
+       if (!strcmp(id, "periph"))
diff --git a/target/linux/brcm63xx/patches-3.9/307-MIPS-BCM63XX-add-HSSPI-register-definitions.patch b/target/linux/brcm63xx/patches-3.9/307-MIPS-BCM63XX-add-HSSPI-register-definitions.patch
new file mode 100644 (file)
index 0000000..1749127
--- /dev/null
@@ -0,0 +1,211 @@
+From 70f970222bc1096689ae1bffeb9ed09a7c4bed07 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jonas.gorski@gmail.com>
+Date: Sat, 12 Nov 2011 12:19:55 +0100
+Subject: [PATCH 28/60] MIPS: BCM63XX: add HSSPI register definitions
+
+Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
+---
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h  |   18 ++++++++
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |   47 +++++++++++++++++++++
+ 2 files changed, 65 insertions(+), 0 deletions(-)
+
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+@@ -131,6 +131,7 @@ enum bcm63xx_regs_set {
+       RSET_UART1,
+       RSET_GPIO,
+       RSET_SPI,
++      RSET_HSSPI,
+       RSET_UDC0,
+       RSET_OHCI0,
+       RSET_OHCI_PRIV,
+@@ -176,6 +177,7 @@ enum bcm63xx_regs_set {
+ #define RSET_ENETDMA_SIZE             2048
+ #define RSET_ENETSW_SIZE              65536
+ #define RSET_UART_SIZE                        24
++#define RSET_HSSPI_SIZE                       1536
+ #define RSET_UDC_SIZE                 256
+ #define RSET_OHCI_SIZE                        256
+ #define RSET_EHCI_SIZE                        256
+@@ -201,6 +203,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6328_UART1_BASE           (0xb0000120)
+ #define BCM_6328_GPIO_BASE            (0xb0000080)
+ #define BCM_6328_SPI_BASE             (0xdeadbeef)
++#define BCM_6328_HSSPI_BASE           (0xb0001000)
+ #define BCM_6328_UDC0_BASE            (0xdeadbeef)
+ #define BCM_6328_USBDMA_BASE          (0xb000c000)
+ #define BCM_6328_OHCI0_BASE           (0xb0002600)
+@@ -247,6 +250,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6338_UART1_BASE           (0xdeadbeef)
+ #define BCM_6338_GPIO_BASE            (0xfffe0400)
+ #define BCM_6338_SPI_BASE             (0xfffe0c00)
++#define BCM_6338_HSSPI_BASE           (0xdeadbeef)
+ #define BCM_6338_UDC0_BASE            (0xdeadbeef)
+ #define BCM_6338_USBDMA_BASE          (0xfffe2400)
+ #define BCM_6338_OHCI0_BASE           (0xdeadbeef)
+@@ -294,6 +298,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6345_UART1_BASE           (0xdeadbeef)
+ #define BCM_6345_GPIO_BASE            (0xfffe0400)
+ #define BCM_6345_SPI_BASE             (0xdeadbeef)
++#define BCM_6345_HSSPI_BASE           (0xdeadbeef)
+ #define BCM_6345_UDC0_BASE            (0xdeadbeef)
+ #define BCM_6345_USBDMA_BASE          (0xfffe2800)
+ #define BCM_6345_ENET0_BASE           (0xfffe1800)
+@@ -340,6 +345,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6348_UART1_BASE           (0xdeadbeef)
+ #define BCM_6348_GPIO_BASE            (0xfffe0400)
+ #define BCM_6348_SPI_BASE             (0xfffe0c00)
++#define BCM_6348_HSSPI_BASE           (0xdeadbeef)
+ #define BCM_6348_UDC0_BASE            (0xfffe1000)
+ #define BCM_6348_USBDMA_BASE          (0xdeadbeef)
+ #define BCM_6348_OHCI0_BASE           (0xfffe1b00)
+@@ -385,6 +391,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6358_UART1_BASE           (0xfffe0120)
+ #define BCM_6358_GPIO_BASE            (0xfffe0080)
+ #define BCM_6358_SPI_BASE             (0xfffe0800)
++#define BCM_6358_HSSPI_BASE           (0xdeadbeef)
+ #define BCM_6358_UDC0_BASE            (0xfffe0800)
+ #define BCM_6358_USBDMA_BASE          (0xdeadbeef)
+ #define BCM_6358_OHCI0_BASE           (0xfffe1400)
+@@ -487,6 +494,7 @@ enum bcm63xx_regs_set {
+ #define BCM_6368_UART1_BASE           (0xb0000120)
+ #define BCM_6368_GPIO_BASE            (0xb0000080)
+ #define BCM_6368_SPI_BASE             (0xb0000800)
++#define BCM_6368_HSSPI_BASE           (0xdeadbeef)
+ #define BCM_6368_UDC0_BASE            (0xdeadbeef)
+ #define BCM_6368_USBDMA_BASE          (0xb0004800)
+ #define BCM_6368_OHCI0_BASE           (0xb0001600)
+@@ -538,6 +546,7 @@ extern const unsigned long *bcm63xx_regs
+       __GEN_RSET_BASE(__cpu, UART1)                                   \
+       __GEN_RSET_BASE(__cpu, GPIO)                                    \
+       __GEN_RSET_BASE(__cpu, SPI)                                     \
++      __GEN_RSET_BASE(__cpu, HSSPI)                                   \
+       __GEN_RSET_BASE(__cpu, UDC0)                                    \
+       __GEN_RSET_BASE(__cpu, OHCI0)                                   \
+       __GEN_RSET_BASE(__cpu, OHCI_PRIV)                               \
+@@ -581,6 +590,7 @@ extern const unsigned long *bcm63xx_regs
+       [RSET_UART1]            = BCM_## __cpu ##_UART1_BASE,           \
+       [RSET_GPIO]             = BCM_## __cpu ##_GPIO_BASE,            \
+       [RSET_SPI]              = BCM_## __cpu ##_SPI_BASE,             \
++      [RSET_HSSPI]            = BCM_## __cpu ##_HSSPI_BASE,           \
+       [RSET_UDC0]             = BCM_## __cpu ##_UDC0_BASE,            \
+       [RSET_OHCI0]            = BCM_## __cpu ##_OHCI0_BASE,           \
+       [RSET_OHCI_PRIV]        = BCM_## __cpu ##_OHCI_PRIV_BASE,       \
+@@ -658,6 +668,7 @@ enum bcm63xx_irq {
+       IRQ_ENET0,
+       IRQ_ENET1,
+       IRQ_ENET_PHY,
++      IRQ_HSSPI,
+       IRQ_OHCI0,
+       IRQ_EHCI0,
+       IRQ_USBD,
+@@ -700,6 +711,7 @@ enum bcm63xx_irq {
+ #define BCM_6328_ENET0_IRQ            0
+ #define BCM_6328_ENET1_IRQ            0
+ #define BCM_6328_ENET_PHY_IRQ         (IRQ_INTERNAL_BASE + 12)
++#define BCM_6328_HSSPI_IRQ            (IRQ_INTERNAL_BASE + 29)
+ #define BCM_6328_OHCI0_IRQ            (BCM_6328_HIGH_IRQ_BASE + 9)
+ #define BCM_6328_EHCI0_IRQ            (BCM_6328_HIGH_IRQ_BASE + 10)
+ #define BCM_6328_USBD_IRQ             (IRQ_INTERNAL_BASE + 4)
+@@ -745,6 +757,7 @@ enum bcm63xx_irq {
+ #define BCM_6338_ENET0_IRQ            (IRQ_INTERNAL_BASE + 8)
+ #define BCM_6338_ENET1_IRQ            0
+ #define BCM_6338_ENET_PHY_IRQ         (IRQ_INTERNAL_BASE + 9)
++#define BCM_6338_HSSPI_IRQ            0
+ #define BCM_6338_OHCI0_IRQ            0
+ #define BCM_6338_EHCI0_IRQ            0
+ #define BCM_6338_USBD_IRQ             0
+@@ -783,6 +796,7 @@ enum bcm63xx_irq {
+ #define BCM_6345_ENET0_IRQ            (IRQ_INTERNAL_BASE + 8)
+ #define BCM_6345_ENET1_IRQ            0
+ #define BCM_6345_ENET_PHY_IRQ         (IRQ_INTERNAL_BASE + 12)
++#define BCM_6345_HSSPI_IRQ            0
+ #define BCM_6345_OHCI0_IRQ            0
+ #define BCM_6345_EHCI0_IRQ            0
+ #define BCM_6345_USBD_IRQ             0
+@@ -821,6 +835,7 @@ enum bcm63xx_irq {
+ #define BCM_6348_ENET0_IRQ            (IRQ_INTERNAL_BASE + 8)
+ #define BCM_6348_ENET1_IRQ            (IRQ_INTERNAL_BASE + 7)
+ #define BCM_6348_ENET_PHY_IRQ         (IRQ_INTERNAL_BASE + 9)
++#define BCM_6348_HSSPI_IRQ            0
+ #define BCM_6348_OHCI0_IRQ            (IRQ_INTERNAL_BASE + 12)
+ #define BCM_6348_EHCI0_IRQ            0
+ #define BCM_6348_USBD_IRQ             0
+@@ -859,6 +874,7 @@ enum bcm63xx_irq {
+ #define BCM_6358_ENET0_IRQ            (IRQ_INTERNAL_BASE + 8)
+ #define BCM_6358_ENET1_IRQ            (IRQ_INTERNAL_BASE + 6)
+ #define BCM_6358_ENET_PHY_IRQ         (IRQ_INTERNAL_BASE + 9)
++#define BCM_6358_HSSPI_IRQ            0
+ #define BCM_6358_OHCI0_IRQ            (IRQ_INTERNAL_BASE + 5)
+ #define BCM_6358_EHCI0_IRQ            (IRQ_INTERNAL_BASE + 10)
+ #define BCM_6358_USBD_IRQ             0
+@@ -971,6 +987,7 @@ enum bcm63xx_irq {
+ #define BCM_6368_ENET0_IRQ            0
+ #define BCM_6368_ENET1_IRQ            0
+ #define BCM_6368_ENET_PHY_IRQ         (IRQ_INTERNAL_BASE + 15)
++#define BCM_6368_HSSPI_IRQ            0
+ #define BCM_6368_OHCI0_IRQ            (IRQ_INTERNAL_BASE + 5)
+ #define BCM_6368_EHCI0_IRQ            (IRQ_INTERNAL_BASE + 7)
+ #define BCM_6368_USBD_IRQ             (IRQ_INTERNAL_BASE + 8)
+@@ -1018,6 +1035,7 @@ extern const int *bcm63xx_irqs;
+       [IRQ_ENET0]             = BCM_## __cpu ##_ENET0_IRQ,            \
+       [IRQ_ENET1]             = BCM_## __cpu ##_ENET1_IRQ,            \
+       [IRQ_ENET_PHY]          = BCM_## __cpu ##_ENET_PHY_IRQ,         \
++      [IRQ_HSSPI]             = BCM_## __cpu ##_HSSPI_IRQ,            \
+       [IRQ_OHCI0]             = BCM_## __cpu ##_OHCI0_IRQ,            \
+       [IRQ_EHCI0]             = BCM_## __cpu ##_EHCI0_IRQ,            \
+       [IRQ_USBD]              = BCM_## __cpu ##_USBD_IRQ,             \
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -1434,4 +1434,51 @@
+ #define PCIE_DEVICE_OFFSET            0x8000
++/*************************************************************************
++ * _REG relative to RSET_HSSPI
++ *************************************************************************/
++
++#define HSSPI_GLOBAL_CTRL_REG                 0x0
++#define GLOBAL_CTRL_CLK_POLARITY              (1 << 17)
++#define GLOBAL_CTRL_CLK_GATE_SSOFF            (1 << 16)
++
++#define HSSPI_GLOBAL_EXT_TRIGGER_REG          0x4
++
++#define HSSPI_INT_STATUS_REG                  0x8
++#define HSSPI_INT_STATUS_MASKED_REG           0xc
++#define HSSPI_INT_MASK_REG                    0x10
++
++#define HSSPI_PING0_CMD_DONE                  (1 << 0)
++
++#define HSSPI_INT_CLEAR_ALL                   0xff001f1f
++
++#define HSSPI_PINGPONG_COMMAND_REG(x)         (0x80 + (x) * 0x40)
++#define PINGPONG_CMD_COMMAND_MASK             0xf
++#define PINGPONG_COMMAND_NOOP                 0
++#define PINGPONG_COMMAND_START_NOW            1
++#define PINGPONG_COMMAND_START_TRIGGER                2
++#define PINGPONG_COMMAND_HALT                 3
++#define PINGPONG_COMMAND_FLUSH                        4
++#define PINGPONG_CMD_PROFILE_SHIFT            8
++#define PINGPONG_CMD_SS_SHIFT                 12
++
++#define HSSPI_PINGPONG_STATUS_REG(x)          (0x84 + (x) * 0x40)
++
++#define HSSPI_PROFILE_CLK_CTRL_REG(x)         (0x100 + (x) * 0x20)
++#define CLK_CTRL_ACCUM_RST_ON_LOOP            (1 << 15)
++
++#define HSSPI_PROFILE_SIGNAL_CTRL_REG(x)      (0x104 + (x) * 0x20)
++#define SIGNAL_CTRL_LATCH_RISING              (1 << 12)
++#define SIGNAL_CTRL_LAUNCH_RISING             (1 << 13)
++#define SIGNAL_CTRL_ASYNC_INPUT_PATH          (1 << 16)
++
++#define HSSPI_PROFILE_MODE_CTRL_REG(x)                (0x108 + (x) * 0x20)
++#define MODE_CTRL_MULTIDATA_RD_STRT_SHIFT     8
++#define MODE_CTRL_MULTIDATA_WR_STRT_SHIFT     12
++#define MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT     16
++#define MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT     18
++#define MODE_CTRL_PREPENDBYTE_CNT_SHIFT               24
++
++#define HSSPI_FIFO_REG(x)                     (0x200 + (x) * 0x200)
++
+ #endif /* BCM63XX_REGS_H_ */
diff --git a/target/linux/brcm63xx/patches-3.9/308-board_leds_naming.patch b/target/linux/brcm63xx/patches-3.9/308-board_leds_naming.patch
new file mode 100644 (file)
index 0000000..c441bf1
--- /dev/null
@@ -0,0 +1,267 @@
+--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+@@ -112,28 +112,28 @@ static struct board_info __initdata boar
+       .leds = {
+               {
+-                      .name           = "adsl",
++                      .name           = "96338GW:green:adsl",
+                       .gpio           = 3,
+                       .active_low     = 1,
+               },
+               {
+-                      .name           = "ses",
++                      .name           = "96338GW:green:ses",
+                       .gpio           = 5,
+                       .active_low     = 1,
+               },
+               {
+-                      .name           = "ppp-fail",
++                      .name           = "96338GW:green:ppp-fail",
+                       .gpio           = 4,
+                       .active_low     = 1,
+               },
+               {
+-                      .name           = "power",
++                      .name           = "96338GW:green:power",
+                       .gpio           = 0,
+                       .active_low     = 1,
+                       .default_trigger = "default-on",
+               },
+               {
+-                      .name           = "stop",
++                      .name           = "96338GW:green:stop",
+                       .gpio           = 1,
+                       .active_low     = 1,
+               }
+@@ -153,28 +153,28 @@ static struct board_info __initdata boar
+       .leds = {
+               {
+-                      .name           = "adsl",
++                      .name           = "96338W:green:adsl",
+                       .gpio           = 3,
+                       .active_low     = 1,
+               },
+               {
+-                      .name           = "ses",
++                      .name           = "96338W:green:ses",
+                       .gpio           = 5,
+                       .active_low     = 1,
+               },
+               {
+-                      .name           = "ppp-fail",
++                      .name           = "96338W:green:ppp-fail",
+                       .gpio           = 4,
+                       .active_low     = 1,
+               },
+               {
+-                      .name           = "power",
++                      .name           = "96338W:green:power",
+                       .gpio           = 0,
+                       .active_low     = 1,
+                       .default_trigger = "default-on",
+               },
+               {
+-                      .name           = "stop",
++                      .name           = "96338W:green:stop",
+                       .gpio           = 1,
+                       .active_low     = 1,
+               },
+@@ -213,29 +213,29 @@ static struct board_info __initdata boar
+       .leds = {
+               {
+-                      .name           = "adsl-fail",
++                      .name           = "96348R:green:adsl-fail",
+                       .gpio           = 2,
+                       .active_low     = 1,
+               },
+               {
+-                      .name           = "ppp",
++                      .name           = "96348R:green:ppp",
+                       .gpio           = 3,
+                       .active_low     = 1,
+               },
+               {
+-                      .name           = "ppp-fail",
++                      .name           = "96348R:green:ppp-fail",
+                       .gpio           = 4,
+                       .active_low     = 1,
+               },
+               {
+-                      .name           = "power",
++                      .name           = "96348R:green:power",
+                       .gpio           = 0,
+                       .active_low     = 1,
+                       .default_trigger = "default-on",
+               },
+               {
+-                      .name           = "stop",
++                      .name           = "96348R:green:stop",
+                       .gpio           = 1,
+                       .active_low     = 1,
+               },
+@@ -274,28 +274,28 @@ static struct board_info __initdata boar
+       .leds = {
+               {
+-                      .name           = "adsl-fail",
++                      .name           = "96348GW-10:green:adsl-fail",
+                       .gpio           = 2,
+                       .active_low     = 1,
+               },
+               {
+-                      .name           = "ppp",
++                      .name           = "96348GW-10:green:ppp",
+                       .gpio           = 3,
+                       .active_low     = 1,
+               },
+               {
+-                      .name           = "ppp-fail",
++                      .name           = "96348GW-10:green:ppp-fail",
+                       .gpio           = 4,
+                       .active_low     = 1,
+               },
+               {
+-                      .name           = "power",
++                      .name           = "96348GW-10:green:power",
+                       .gpio           = 0,
+                       .active_low     = 1,
+                       .default_trigger = "default-on",
+               },
+               {
+-                      .name           = "stop",
++                      .name           = "96348GW-10:green:stop",
+                       .gpio           = 1,
+                       .active_low     = 1,
+               },
+@@ -328,28 +328,28 @@ static struct board_info __initdata boar
+       .leds = {
+               {
+-                      .name           = "adsl-fail",
++                      .name           = "96348GW-11:green:adsl-fail",
+                       .gpio           = 2,
+                       .active_low     = 1,
+               },
+               {
+-                      .name           = "ppp",
++                      .name           = "96348GW-11:green:ppp",
+                       .gpio           = 3,
+                       .active_low     = 1,
+               },
+               {
+-                      .name           = "ppp-fail",
++                      .name           = "96348GW-11:green:ppp-fail",
+                       .gpio           = 4,
+                       .active_low     = 1,
+               },
+               {
+-                      .name           = "power",
++                      .name           = "96348GW-11:green:power",
+                       .gpio           = 0,
+                       .active_low     = 1,
+                       .default_trigger = "default-on",
+               },
+               {
+-                      .name           = "stop",
++                      .name           = "96348GW-11:green:stop",
+                       .gpio           = 1,
+                       .active_low     = 1,
+               },
+@@ -396,28 +396,28 @@ static struct board_info __initdata boar
+       .leds = {
+               {
+-                      .name           = "adsl-fail",
++                      .name           = "96348GW:green:adsl-fail",
+                       .gpio           = 2,
+                       .active_low     = 1,
+               },
+               {
+-                      .name           = "ppp",
++                      .name           = "96348GW:green:ppp",
+                       .gpio           = 3,
+                       .active_low     = 1,
+               },
+               {
+-                      .name           = "ppp-fail",
++                      .name           = "96348GW:green:ppp-fail",
+                       .gpio           = 4,
+                       .active_low     = 1,
+               },
+               {
+-                      .name           = "power",
++                      .name           = "96348GW:green:power",
+                       .gpio           = 0,
+                       .active_low     = 1,
+                       .default_trigger = "default-on",
+               },
+               {
+-                      .name           = "stop",
++                      .name           = "96348GW:green:stop",
+                       .gpio           = 1,
+                       .active_low     = 1,
+               },
+@@ -549,27 +549,27 @@ static struct board_info __initdata boar
+       .leds = {
+               {
+-                      .name           = "adsl-fail",
++                      .name           = "96358VW:green:adsl-fail",
+                       .gpio           = 15,
+                       .active_low     = 1,
+               },
+               {
+-                      .name           = "ppp",
++                      .name           = "96358VW:green:ppp",
+                       .gpio           = 22,
+                       .active_low     = 1,
+               },
+               {
+-                      .name           = "ppp-fail",
++                      .name           = "96358VW:green:ppp-fail",
+                       .gpio           = 23,
+                       .active_low     = 1,
+               },
+               {
+-                      .name           = "power",
++                      .name           = "96358VW:green:power",
+                       .gpio           = 4,
+                       .default_trigger = "default-on",
+               },
+               {
+-                      .name           = "stop",
++                      .name           = "96358VW:green:stop",
+                       .gpio           = 5,
+               },
+       },
+@@ -601,22 +601,22 @@ static struct board_info __initdata boar
+       .leds = {
+               {
+-                      .name           = "adsl",
++                      .name           = "96358VW2:green:adsl",
+                       .gpio           = 22,
+                       .active_low     = 1,
+               },
+               {
+-                      .name           = "ppp-fail",
++                      .name           = "96358VW2:green:ppp-fail",
+                       .gpio           = 23,
+               },
+               {
+-                      .name           = "power",
++                      .name           = "96358VW2:green:power",
+                       .gpio           = 5,
+                       .active_low     = 1,
+                       .default_trigger = "default-on",
+               },
+               {
+-                      .name           = "stop",
++                      .name           = "96358VW2:green:stop",
+                       .gpio           = 4,
+                       .active_low     = 1,
+               },
diff --git a/target/linux/brcm63xx/patches-3.9/309-cfe_version_mod.patch b/target/linux/brcm63xx/patches-3.9/309-cfe_version_mod.patch
new file mode 100644 (file)
index 0000000..9482b6b
--- /dev/null
@@ -0,0 +1,11 @@
+--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+@@ -798,6 +798,8 @@ void __init board_prom_init(void)
+       if (!memcmp(cfe, "cfe-v", 5))
+               snprintf(cfe_version, sizeof(cfe_version), "%u.%u.%u-%u.%u",
+                        cfe[5], cfe[6], cfe[7], cfe[8], cfe[9]);
++      else if (!memcmp(cfe, "cfe-", 4))
++              snprintf(cfe_version, 16, "%s", (char *) &cfe[4]);
+       else
+               strcpy(cfe_version, "unknown");
+       printk(KERN_INFO PFX "CFE version: %s\n", cfe_version);
diff --git a/target/linux/brcm63xx/patches-3.9/310-BCM63XX-Add-SMP-support-to-prom.c.patch b/target/linux/brcm63xx/patches-3.9/310-BCM63XX-Add-SMP-support-to-prom.c.patch
new file mode 100644 (file)
index 0000000..7c9baf7
--- /dev/null
@@ -0,0 +1,71 @@
+From 10ea7fd6b854c3ecf745d053beba10c7e00c33c9 Mon Sep 17 00:00:00 2001
+From: Kevin Cernekee <cernekee@gmail.com>
+Date: Sat, 9 Jul 2011 12:15:06 -0700
+Subject: [PATCH 01/13] MIPS: BCM63XX: Add SMP support to prom.c
+
+This involves two changes to the BSP code:
+
+1) register_smp_ops() for BMIPS SMP
+
+2) The CPU1 boot vector on some of the BCM63xx platforms conflicts with
+the special interrupt vector (IV).  Move it to 0x8000_0380 at boot time,
+to resolve the conflict.
+
+Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
+[jogo@openwrt: move smp ops registration below #ifdef guard, don't enable
+ smp for 6328/6358]
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/prom.c |   33 +++++++++++++++++++++++++++++++++
+ 1 file changed, 33 insertions(+)
+
+--- a/arch/mips/bcm63xx/prom.c
++++ b/arch/mips/bcm63xx/prom.c
+@@ -8,7 +8,11 @@
+ #include <linux/init.h>
+ #include <linux/bootmem.h>
++#include <linux/smp.h>
+ #include <asm/bootinfo.h>
++#include <asm/bmips.h>
++#include <asm/smp-ops.h>
++#include <asm/mipsregs.h>
+ #include <bcm63xx_board.h>
+ #include <bcm63xx_cpu.h>
+ #include <bcm63xx_io.h>
+@@ -52,6 +56,35 @@ void __init prom_init(void)
+       /* do low level board init */
+       board_prom_init();
++
++#if defined(CONFIG_CPU_BMIPS4350) && defined(CONFIG_SMP)
++      /* set up SMP */
++      register_smp_ops(&bmips_smp_ops);
++
++      /*
++       * BCM6328 does not have its second CPU enabled, while BCM6358
++       * needs special handling for its shared TLB, so disable SMP for now.
++       */
++      if (BCMCPU_IS_6328() || BCMCPU_IS_6358()) {
++              bmips_smp_enabled = 0;
++              return;
++      }
++
++      /*
++       * The bootloader has set up the CPU1 reset vector at 0xa000_0200.
++       * This conflicts with the special interrupt vector (IV).
++       * The bootloader has also set up CPU1 to respond to the wrong
++       * IPI interrupt.
++       * Here we will start up CPU1 in the background and ask it to
++       * reconfigure itself then go back to sleep.
++       */
++      memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20);
++      __sync();
++      set_c0_cause(C_SW0);
++      cpumask_set_cpu(1, &bmips_booted_mask);
++
++      /* FIXME: we really should have some sort of hazard barrier here */
++#endif
+ }
+ void __init prom_free_prom_memory(void)
diff --git a/target/linux/brcm63xx/patches-3.9/311-MIPS-BCM63XX-Handle-SW-IRQs-0-1.patch b/target/linux/brcm63xx/patches-3.9/311-MIPS-BCM63XX-Handle-SW-IRQs-0-1.patch
new file mode 100644 (file)
index 0000000..f08c7ef
--- /dev/null
@@ -0,0 +1,28 @@
+From 8e0bd819cc0f8815cad99feea98664172c0b1fe4 Mon Sep 17 00:00:00 2001
+From: Kevin Cernekee <cernekee@gmail.com>
+Date: Mon, 31 Oct 2011 11:52:10 -0700
+Subject: [PATCH 02/13] MIPS: BCM63XX: Handle SW IRQs 0-1
+
+MIPS software IRQs 0 and 1 are used for interprocessor signaling (IPI)
+on BMIPS SMP.  Make the board support code aware of them.
+
+Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
+[jogo@openwrt.org: move sw irqs behind timer irq]
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/irq.c |    4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/arch/mips/bcm63xx/irq.c
++++ b/arch/mips/bcm63xx/irq.c
+@@ -294,6 +294,10 @@ asmlinkage void plat_irq_dispatch(void)
+               if (cause & CAUSEF_IP7)
+                       do_IRQ(7);
++              if (cause & CAUSEF_IP0)
++                      do_IRQ(0);
++              if (cause & CAUSEF_IP1)
++                      do_IRQ(1);
+               if (cause & CAUSEF_IP2)
+                       dispatch_internal();
+               if (!is_ext_irq_cascaded) {
diff --git a/target/linux/brcm63xx/patches-3.9/312-MIPS-BCM63XX-select-SYS_HAS_CPU_BMIPS4350-for-suppor.patch b/target/linux/brcm63xx/patches-3.9/312-MIPS-BCM63XX-select-SYS_HAS_CPU_BMIPS4350-for-suppor.patch
new file mode 100644 (file)
index 0000000..9376d56
--- /dev/null
@@ -0,0 +1,24 @@
+From 1923ce1435a5e89f9550e8c95db37a3ef1f92665 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Sun, 21 Apr 2013 14:44:00 +0200
+Subject: [PATCH 03/13] MIPS: BCM63XX: select SYS_HAS_CPU_BMIPS4350 for
+ supported SoCs
+
+BCM6338, BCM6345 and BCM6348 have a BMIPS3300, everything following
+has a BMIPS4350.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/Kconfig |    1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -129,6 +129,7 @@ config BCM63XX
+       select DMA_NONCOHERENT
+       select IRQ_CPU
+       select SYS_HAS_CPU_MIPS32_R1
++      select SYS_HAS_CPU_BMIPS4350 if !BCM63XX_CPU_6338 && !BCM63XX_CPU_6345 && !BCM63XX_CPU_6348
+       select SYS_SUPPORTS_32BIT_KERNEL
+       select SYS_SUPPORTS_BIG_ENDIAN
+       select SYS_HAS_EARLY_PRINTK
diff --git a/target/linux/brcm63xx/patches-3.9/313-MIPS-BCM63XX-rename-__dispatch_internal-to-__dispatc.patch b/target/linux/brcm63xx/patches-3.9/313-MIPS-BCM63XX-rename-__dispatch_internal-to-__dispatc.patch
new file mode 100644 (file)
index 0000000..f5b6071
--- /dev/null
@@ -0,0 +1,51 @@
+From bb2774da9598f3ea38099d3dcf753b585824a011 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Thu, 21 Mar 2013 17:05:15 +0100
+Subject: [PATCH 04/13] MIPS: BCM63XX: rename __dispatch_internal to
+ __dispatch_internal_32
+
+Make it follow the same naming convention as the other functions.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/irq.c |    8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/arch/mips/bcm63xx/irq.c
++++ b/arch/mips/bcm63xx/irq.c
+@@ -19,7 +19,7 @@
+ #include <bcm63xx_io.h>
+ #include <bcm63xx_irq.h>
+-static void __dispatch_internal(void) __maybe_unused;
++static void __dispatch_internal_32(void) __maybe_unused;
+ static void __dispatch_internal_64(void) __maybe_unused;
+ static void __internal_irq_mask_32(unsigned int irq) __maybe_unused;
+ static void __internal_irq_mask_64(unsigned int irq) __maybe_unused;
+@@ -106,7 +106,7 @@ static void __internal_irq_unmask_64(uns
+ #endif
+ #if irq_bits == 32
+-#define dispatch_internal                     __dispatch_internal
++#define dispatch_internal                     __dispatch_internal_32
+ #define internal_irq_mask                     __internal_irq_mask_32
+ #define internal_irq_unmask                   __internal_irq_unmask_32
+ #else
+@@ -207,7 +207,7 @@ static void bcm63xx_init_irq(void)
+       }
+       if (irq_bits == 32) {
+-              dispatch_internal = __dispatch_internal;
++              dispatch_internal = __dispatch_internal_32;
+               internal_irq_mask = __internal_irq_mask_32;
+               internal_irq_unmask = __internal_irq_unmask_32;
+       } else {
+@@ -240,7 +240,7 @@ static inline void handle_internal(int i
+  * will resume the loop where it ended the last time we left this
+  * function.
+  */
+-static void __dispatch_internal(void)
++static void __dispatch_internal_32(void)
+ {
+       u32 pending;
+       static int i;
diff --git a/target/linux/brcm63xx/patches-3.9/314-MIPS-BCM63XX-replace-irq-dispatch-code-with-a-generi.patch b/target/linux/brcm63xx/patches-3.9/314-MIPS-BCM63XX-replace-irq-dispatch-code-with-a-generi.patch
new file mode 100644 (file)
index 0000000..5fabd08
--- /dev/null
@@ -0,0 +1,167 @@
+From 661e02b8e2b9a4b48a809bc82dfe8f7b20ca750f Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Thu, 18 Apr 2013 21:14:49 +0200
+Subject: [PATCH 05/13] MIPS: BCM63XX: replace irq dispatch code with a
+ generic version
+
+The generic version uses a variable length of u32 registers of u32/u64.
+This allows easier support for longer registers without having to rewrite
+verything.
+
+This "generic" version is not slower than the old version in the best case
+(= i == next set bit), and twice as fast in the worst case in 64 bits.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/irq.c |  130 ++++++++++++++++++++---------------------------
+ 1 file changed, 56 insertions(+), 74 deletions(-)
+
+--- a/arch/mips/bcm63xx/irq.c
++++ b/arch/mips/bcm63xx/irq.c
+@@ -240,47 +240,65 @@ static inline void handle_internal(int i
+  * will resume the loop where it ended the last time we left this
+  * function.
+  */
+-static void __dispatch_internal_32(void)
+-{
+-      u32 pending;
+-      static int i;
+-
+-      pending = bcm_readl(irq_stat_addr) & bcm_readl(irq_mask_addr);
+-
+-      if (!pending)
+-              return ;
+-
+-      while (1) {
+-              int to_call = i;
+-              i = (i + 1) & 0x1f;
+-              if (pending & (1 << to_call)) {
+-                      handle_internal(to_call);
+-                      break;
+-              }
+-      }
++#define BUILD_IPIC_INTERNAL(width)                                    \
++void __dispatch_internal_##width(void)                                        \
++{                                                                     \
++      u32 pending[width / 32];                                        \
++      unsigned int src, tgt;                                          \
++      bool irqs_pending = false;                                      \
++      static int i;                                                   \
++                                                                      \
++      /* read registers in reverse order */                           \
++      for (src = 0, tgt = (width / 32); src < (width / 32); src++) {  \
++              u32 val;                                                \
++                                                                      \
++              val = bcm_readl(irq_stat_addr + src * sizeof(u32));     \
++              val &= bcm_readl(irq_mask_addr + src * sizeof(u32));    \
++              pending[--tgt] = val;                                   \
++                                                                      \
++              if (val)                                                \
++                      irqs_pending = true;                            \
++      }                                                               \
++                                                                      \
++      if (!irqs_pending)                                              \
++              return;                                                 \
++                                                                      \
++      while (1) {                                                     \
++              int to_call = i;                                        \
++                                                                      \
++              i = (i + 1) & (width - 1);                              \
++              if (pending[to_call / 32] & (1 << (to_call & 0x1f))) {  \
++                      handle_internal(to_call);                       \
++                      break;                                          \
++              }                                                       \
++      }                                                               \
++}                                                                     \
++                                                                      \
++static void __internal_irq_mask_##width(unsigned int irq)             \
++{                                                                     \
++      u32 val;                                                        \
++      unsigned reg = (irq / 32) ^ (width/32 - 1);                     \
++      unsigned bit = irq & 0x1f;                                      \
++                                                                      \
++      val = bcm_readl(irq_mask_addr + reg * sizeof(u32));             \
++      val &= ~(1 << bit);                                             \
++      bcm_writel(val, irq_mask_addr + reg * sizeof(u32));             \
++}                                                                     \
++                                                                      \
++static void __internal_irq_unmask_##width(unsigned int irq)           \
++{                                                                     \
++      u32 val;                                                        \
++      unsigned reg = (irq / 32) ^ (width/32 - 1);                     \
++      unsigned bit = irq & 0x1f;                                      \
++                                                                      \
++      val = bcm_readl(irq_mask_addr + reg * sizeof(u32));             \
++      val |= (1 << bit);                                              \
++      bcm_writel(val, irq_mask_addr + reg * sizeof(u32));             \
+ }
+-static void __dispatch_internal_64(void)
+-{
+-      u64 pending;
+-      static int i;
+-
+-      pending = bcm_readq(irq_stat_addr) & bcm_readq(irq_mask_addr);
+-
+-      if (!pending)
+-              return ;
+-
+-      while (1) {
+-              int to_call = i;
+-
+-              i = (i + 1) & 0x3f;
+-              if (pending & (1ull << to_call)) {
+-                      handle_internal(to_call);
+-                      break;
+-              }
+-      }
+-}
++BUILD_IPIC_INTERNAL(32);
++BUILD_IPIC_INTERNAL(64);
+ asmlinkage void plat_irq_dispatch(void)
+ {
+@@ -317,42 +335,6 @@ asmlinkage void plat_irq_dispatch(void)
+  * internal IRQs operations: only mask/unmask on PERF irq mask
+  * register.
+  */
+-static void __internal_irq_mask_32(unsigned int irq)
+-{
+-      u32 mask;
+-
+-      mask = bcm_readl(irq_mask_addr);
+-      mask &= ~(1 << irq);
+-      bcm_writel(mask, irq_mask_addr);
+-}
+-
+-static void __internal_irq_mask_64(unsigned int irq)
+-{
+-      u64 mask;
+-
+-      mask = bcm_readq(irq_mask_addr);
+-      mask &= ~(1ull << irq);
+-      bcm_writeq(mask, irq_mask_addr);
+-}
+-
+-static void __internal_irq_unmask_32(unsigned int irq)
+-{
+-      u32 mask;
+-
+-      mask = bcm_readl(irq_mask_addr);
+-      mask |= (1 << irq);
+-      bcm_writel(mask, irq_mask_addr);
+-}
+-
+-static void __internal_irq_unmask_64(unsigned int irq)
+-{
+-      u64 mask;
+-
+-      mask = bcm_readq(irq_mask_addr);
+-      mask |= (1ull << irq);
+-      bcm_writeq(mask, irq_mask_addr);
+-}
+-
+ static void bcm63xx_internal_irq_mask(struct irq_data *d)
+ {
+       internal_irq_mask(d->irq - IRQ_INTERNAL_BASE);
diff --git a/target/linux/brcm63xx/patches-3.9/315-MIPS-BCM63XX-append-cpu-number-to-irq_-stat-mask.patch b/target/linux/brcm63xx/patches-3.9/315-MIPS-BCM63XX-append-cpu-number-to-irq_-stat-mask.patch
new file mode 100644 (file)
index 0000000..98cd637
--- /dev/null
@@ -0,0 +1,258 @@
+From 6ec70ebfccd31ae3668d99b5703e5c9ce38384b4 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Thu, 25 Apr 2013 00:24:06 +0200
+Subject: [PATCH 06/13] MIPS: BCM63XX: append cpu number to irq_{stat,mask}*
+
+For SMP affinity support we need to discrimnate between the registers
+for both CPUs.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/irq.c                           |   78 ++++++++++-----------
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |   16 ++---
+ 2 files changed, 47 insertions(+), 47 deletions(-)
+
+--- a/arch/mips/bcm63xx/irq.c
++++ b/arch/mips/bcm63xx/irq.c
+@@ -28,8 +28,8 @@ static void __internal_irq_unmask_64(uns
+ #ifndef BCMCPU_RUNTIME_DETECT
+ #ifdef CONFIG_BCM63XX_CPU_6328
+-#define irq_stat_reg          PERF_IRQSTAT_6328_REG
+-#define irq_mask_reg          PERF_IRQMASK_6328_REG
++#define irq_stat_reg0         PERF_IRQSTAT_6328_REG(0)
++#define irq_mask_reg0         PERF_IRQMASK_6328_REG(0)
+ #define irq_bits              64
+ #define is_ext_irq_cascaded   1
+ #define ext_irq_start         (BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE)
+@@ -39,8 +39,8 @@ static void __internal_irq_unmask_64(uns
+ #define ext_irq_cfg_reg2      0
+ #endif
+ #ifdef CONFIG_BCM63XX_CPU_6338
+-#define irq_stat_reg          PERF_IRQSTAT_6338_REG
+-#define irq_mask_reg          PERF_IRQMASK_6338_REG
++#define irq_stat_reg0         PERF_IRQSTAT_6338_REG
++#define irq_mask_reg0         PERF_IRQMASK_6338_REG
+ #define irq_bits              32
+ #define is_ext_irq_cascaded   0
+ #define ext_irq_start         0
+@@ -50,8 +50,8 @@ static void __internal_irq_unmask_64(uns
+ #define ext_irq_cfg_reg2      0
+ #endif
+ #ifdef CONFIG_BCM63XX_CPU_6345
+-#define irq_stat_reg          PERF_IRQSTAT_6345_REG
+-#define irq_mask_reg          PERF_IRQMASK_6345_REG
++#define irq_stat_reg0         PERF_IRQSTAT_6345_REG
++#define irq_mask_reg0         PERF_IRQMASK_6345_REG
+ #define irq_bits              32
+ #define is_ext_irq_cascaded   0
+ #define ext_irq_start         0
+@@ -61,8 +61,8 @@ static void __internal_irq_unmask_64(uns
+ #define ext_irq_cfg_reg2      0
+ #endif
+ #ifdef CONFIG_BCM63XX_CPU_6348
+-#define irq_stat_reg          PERF_IRQSTAT_6348_REG
+-#define irq_mask_reg          PERF_IRQMASK_6348_REG
++#define irq_stat_reg0         PERF_IRQSTAT_6348_REG
++#define irq_mask_reg0         PERF_IRQMASK_6348_REG
+ #define irq_bits              32
+ #define is_ext_irq_cascaded   0
+ #define ext_irq_start         0
+@@ -72,8 +72,8 @@ static void __internal_irq_unmask_64(uns
+ #define ext_irq_cfg_reg2      0
+ #endif
+ #ifdef CONFIG_BCM63XX_CPU_6358
+-#define irq_stat_reg          PERF_IRQSTAT_6358_REG
+-#define irq_mask_reg          PERF_IRQMASK_6358_REG
++#define irq_stat_reg0         PERF_IRQSTAT_6358_REG(0)
++#define irq_mask_reg0         PERF_IRQMASK_6358_REG(0)
+ #define irq_bits              32
+ #define is_ext_irq_cascaded   1
+ #define ext_irq_start         (BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE)
+@@ -83,8 +83,8 @@ static void __internal_irq_unmask_64(uns
+ #define ext_irq_cfg_reg2      0
+ #endif
+ #ifdef CONFIG_BCM63XX_CPU_6362
+-#define irq_stat_reg          PERF_IRQSTAT_6362_REG
+-#define irq_mask_reg          PERF_IRQMASK_6362_REG
++#define irq_stat_reg0         PERF_IRQSTAT_6362_REG(0)
++#define irq_mask_reg0         PERF_IRQMASK_6362_REG(0)
+ #define irq_bits              64
+ #define is_ext_irq_cascaded   1
+ #define ext_irq_start         (BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE)
+@@ -94,8 +94,8 @@ static void __internal_irq_unmask_64(uns
+ #define ext_irq_cfg_reg2      0
+ #endif
+ #ifdef CONFIG_BCM63XX_CPU_6368
+-#define irq_stat_reg          PERF_IRQSTAT_6368_REG
+-#define irq_mask_reg          PERF_IRQMASK_6368_REG
++#define irq_stat_reg0         PERF_IRQSTAT_6368_REG(0)
++#define irq_mask_reg0         PERF_IRQMASK_6368_REG(0)
+ #define irq_bits              64
+ #define is_ext_irq_cascaded   1
+ #define ext_irq_start         (BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE)
+@@ -115,15 +115,15 @@ static void __internal_irq_unmask_64(uns
+ #define internal_irq_unmask                   __internal_irq_unmask_64
+ #endif
+-#define irq_stat_addr (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg)
+-#define irq_mask_addr (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg)
++#define irq_stat_addr0        (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg0)
++#define irq_mask_addr0        (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg0)
+ static inline void bcm63xx_init_irq(void)
+ {
+ }
+ #else /* ! BCMCPU_RUNTIME_DETECT */
+-static u32 irq_stat_addr, irq_mask_addr;
++static u32 irq_stat_addr0, irq_mask_addr0;
+ static void (*dispatch_internal)(void);
+ static int is_ext_irq_cascaded;
+ static unsigned int ext_irq_count;
+@@ -136,13 +136,13 @@ static void bcm63xx_init_irq(void)
+ {
+       int irq_bits;
+-      irq_stat_addr = bcm63xx_regset_address(RSET_PERF);
+-      irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
++      irq_stat_addr0 = bcm63xx_regset_address(RSET_PERF);
++      irq_mask_addr0 = bcm63xx_regset_address(RSET_PERF);
+       switch (bcm63xx_get_cpu_id()) {
+       case BCM6328_CPU_ID:
+-              irq_stat_addr += PERF_IRQSTAT_6328_REG;
+-              irq_mask_addr += PERF_IRQMASK_6328_REG;
++              irq_stat_addr0 += PERF_IRQSTAT_6328_REG(0);
++              irq_mask_addr0 += PERF_IRQMASK_6328_REG(0);
+               irq_bits = 64;
+               ext_irq_count = 4;
+               is_ext_irq_cascaded = 1;
+@@ -151,29 +151,29 @@ static void bcm63xx_init_irq(void)
+               ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
+               break;
+       case BCM6338_CPU_ID:
+-              irq_stat_addr += PERF_IRQSTAT_6338_REG;
+-              irq_mask_addr += PERF_IRQMASK_6338_REG;
++              irq_stat_addr0 += PERF_IRQSTAT_6338_REG;
++              irq_mask_addr0 += PERF_IRQMASK_6338_REG;
+               irq_bits = 32;
+               ext_irq_count = 4;
+               ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
+               break;
+       case BCM6345_CPU_ID:
+-              irq_stat_addr += PERF_IRQSTAT_6345_REG;
+-              irq_mask_addr += PERF_IRQMASK_6345_REG;
++              irq_stat_addr0 += PERF_IRQSTAT_6345_REG;
++              irq_mask_addr0 += PERF_IRQMASK_6345_REG;
+               irq_bits = 32;
+               ext_irq_count = 4;
+               ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
+               break;
+       case BCM6348_CPU_ID:
+-              irq_stat_addr += PERF_IRQSTAT_6348_REG;
+-              irq_mask_addr += PERF_IRQMASK_6348_REG;
++              irq_stat_addr0 += PERF_IRQSTAT_6348_REG;
++              irq_mask_addr0 += PERF_IRQMASK_6348_REG;
+               irq_bits = 32;
+               ext_irq_count = 4;
+               ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
+               break;
+       case BCM6358_CPU_ID:
+-              irq_stat_addr += PERF_IRQSTAT_6358_REG;
+-              irq_mask_addr += PERF_IRQMASK_6358_REG;
++              irq_stat_addr0 += PERF_IRQSTAT_6358_REG(0);
++              irq_mask_addr0 += PERF_IRQMASK_6358_REG(0);
+               irq_bits = 32;
+               ext_irq_count = 4;
+               is_ext_irq_cascaded = 1;
+@@ -182,8 +182,8 @@ static void bcm63xx_init_irq(void)
+               ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
+               break;
+       case BCM6362_CPU_ID:
+-              irq_stat_addr += PERF_IRQSTAT_6362_REG;
+-              irq_mask_addr += PERF_IRQMASK_6362_REG;
++              irq_stat_addr0 += PERF_IRQSTAT_6362_REG(0);
++              irq_mask_addr0 += PERF_IRQMASK_6362_REG(0);
+               irq_bits = 64;
+               ext_irq_count = 4;
+               is_ext_irq_cascaded = 1;
+@@ -192,8 +192,8 @@ static void bcm63xx_init_irq(void)
+               ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
+               break;
+       case BCM6368_CPU_ID:
+-              irq_stat_addr += PERF_IRQSTAT_6368_REG;
+-              irq_mask_addr += PERF_IRQMASK_6368_REG;
++              irq_stat_addr0 += PERF_IRQSTAT_6368_REG(0);
++              irq_mask_addr0 += PERF_IRQMASK_6368_REG(0);
+               irq_bits = 64;
+               ext_irq_count = 6;
+               is_ext_irq_cascaded = 1;
+@@ -253,8 +253,8 @@ void __dispatch_internal_##width(void)
+       for (src = 0, tgt = (width / 32); src < (width / 32); src++) {  \
+               u32 val;                                                \
+                                                                       \
+-              val = bcm_readl(irq_stat_addr + src * sizeof(u32));     \
+-              val &= bcm_readl(irq_mask_addr + src * sizeof(u32));    \
++              val = bcm_readl(irq_stat_addr0 + src * sizeof(u32));    \
++              val &= bcm_readl(irq_mask_addr0 + src * sizeof(u32));   \
+               pending[--tgt] = val;                                   \
+                                                                       \
+               if (val)                                                \
+@@ -281,9 +281,9 @@ static void __internal_irq_mask_##width(
+       unsigned reg = (irq / 32) ^ (width/32 - 1);                     \
+       unsigned bit = irq & 0x1f;                                      \
+                                                                       \
+-      val = bcm_readl(irq_mask_addr + reg * sizeof(u32));             \
++      val = bcm_readl(irq_mask_addr0 + reg * sizeof(u32));            \
+       val &= ~(1 << bit);                                             \
+-      bcm_writel(val, irq_mask_addr + reg * sizeof(u32));             \
++      bcm_writel(val, irq_mask_addr0 + reg * sizeof(u32));            \
+ }                                                                     \
+                                                                       \
+ static void __internal_irq_unmask_##width(unsigned int irq)           \
+@@ -292,9 +292,9 @@ static void __internal_irq_unmask_##widt
+       unsigned reg = (irq / 32) ^ (width/32 - 1);                     \
+       unsigned bit = irq & 0x1f;                                      \
+                                                                       \
+-      val = bcm_readl(irq_mask_addr + reg * sizeof(u32));             \
++      val = bcm_readl(irq_mask_addr0 + reg * sizeof(u32));            \
+       val |= (1 << bit);                                              \
+-      bcm_writel(val, irq_mask_addr + reg * sizeof(u32));             \
++      bcm_writel(val, irq_mask_addr0 + reg * sizeof(u32));            \
+ }
+ BUILD_IPIC_INTERNAL(32);
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -181,22 +181,22 @@
+ #define SYS_PLL_SOFT_RESET            0x1
+ /* Interrupt Mask register */
+-#define PERF_IRQMASK_6328_REG         0x20
++#define PERF_IRQMASK_6328_REG(x)      (0x20 + (x) * 0x10)
+ #define PERF_IRQMASK_6338_REG         0xc
+ #define PERF_IRQMASK_6345_REG         0xc
+ #define PERF_IRQMASK_6348_REG         0xc
+-#define PERF_IRQMASK_6358_REG         0xc
+-#define PERF_IRQMASK_6362_REG         0x20
+-#define PERF_IRQMASK_6368_REG         0x20
++#define PERF_IRQMASK_6358_REG(x)      (0xc + (x) * 0x2c)
++#define PERF_IRQMASK_6362_REG(x)      (0x20 + (x) * 0x10)
++#define PERF_IRQMASK_6368_REG(x)      (0x20 + (x) * 0x10)
+ /* Interrupt Status register */
+-#define PERF_IRQSTAT_6328_REG         0x28
++#define PERF_IRQSTAT_6328_REG(x)      (0x28 + (x) * 0x10)
+ #define PERF_IRQSTAT_6338_REG         0x10
+ #define PERF_IRQSTAT_6345_REG         0x10
+ #define PERF_IRQSTAT_6348_REG         0x10
+-#define PERF_IRQSTAT_6358_REG         0x10
+-#define PERF_IRQSTAT_6362_REG         0x28
+-#define PERF_IRQSTAT_6368_REG         0x28
++#define PERF_IRQSTAT_6358_REG(x)      (0x10 + (x) * 0x2c)
++#define PERF_IRQSTAT_6362_REG(x)      (0x28 + (x) * 0x10)
++#define PERF_IRQSTAT_6368_REG(x)      (0x28 + (x) * 0x10)
+ /* External Interrupt Configuration register */
+ #define PERF_EXTIRQ_CFG_REG_6328      0x18
diff --git a/target/linux/brcm63xx/patches-3.9/316-MIPS-BCM63XX-populate-irq_-stat-mask-_addr-for-secon.patch b/target/linux/brcm63xx/patches-3.9/316-MIPS-BCM63XX-populate-irq_-stat-mask-_addr-for-secon.patch
new file mode 100644 (file)
index 0000000..094eaa8
--- /dev/null
@@ -0,0 +1,138 @@
+From b14de5c78d32f8f98535a99ea56bb924beb66810 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Thu, 25 Apr 2013 00:31:29 +0200
+Subject: [PATCH 07/13] MIPS: BCM63XX: populate irq_{stat,mask}_addr for
+ second CPU
+
+Populate it for all platforms with a BMIPS4350.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/irq.c |   28 +++++++++++++++++++++++++++-
+ 1 file changed, 27 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/bcm63xx/irq.c
++++ b/arch/mips/bcm63xx/irq.c
+@@ -30,6 +30,8 @@ static void __internal_irq_unmask_64(uns
+ #ifdef CONFIG_BCM63XX_CPU_6328
+ #define irq_stat_reg0         PERF_IRQSTAT_6328_REG(0)
+ #define irq_mask_reg0         PERF_IRQMASK_6328_REG(0)
++#define irq_stat_reg1         PERF_IRQSTAT_6328_REG(1)
++#define irq_mask_reg1         PERF_IRQMASK_6328_REG(1)
+ #define irq_bits              64
+ #define is_ext_irq_cascaded   1
+ #define ext_irq_start         (BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE)
+@@ -41,6 +43,8 @@ static void __internal_irq_unmask_64(uns
+ #ifdef CONFIG_BCM63XX_CPU_6338
+ #define irq_stat_reg0         PERF_IRQSTAT_6338_REG
+ #define irq_mask_reg0         PERF_IRQMASK_6338_REG
++#define irq_stat_reg1         0
++#define irq_mask_reg1         0
+ #define irq_bits              32
+ #define is_ext_irq_cascaded   0
+ #define ext_irq_start         0
+@@ -52,6 +56,8 @@ static void __internal_irq_unmask_64(uns
+ #ifdef CONFIG_BCM63XX_CPU_6345
+ #define irq_stat_reg0         PERF_IRQSTAT_6345_REG
+ #define irq_mask_reg0         PERF_IRQMASK_6345_REG
++#define irq_stat_reg1         0
++#define irq_mask_reg1         0
+ #define irq_bits              32
+ #define is_ext_irq_cascaded   0
+ #define ext_irq_start         0
+@@ -63,6 +69,8 @@ static void __internal_irq_unmask_64(uns
+ #ifdef CONFIG_BCM63XX_CPU_6348
+ #define irq_stat_reg0         PERF_IRQSTAT_6348_REG
+ #define irq_mask_reg0         PERF_IRQMASK_6348_REG
++#define irq_stat_reg1         0
++#define irq_mask_reg1         0
+ #define irq_bits              32
+ #define is_ext_irq_cascaded   0
+ #define ext_irq_start         0
+@@ -74,6 +82,8 @@ static void __internal_irq_unmask_64(uns
+ #ifdef CONFIG_BCM63XX_CPU_6358
+ #define irq_stat_reg0         PERF_IRQSTAT_6358_REG(0)
+ #define irq_mask_reg0         PERF_IRQMASK_6358_REG(0)
++#define irq_stat_reg1         PERF_IRQSTAT_6358_REG(1)
++#define irq_mask_reg1         PERF_IRQMASK_6358_REG(1)
+ #define irq_bits              32
+ #define is_ext_irq_cascaded   1
+ #define ext_irq_start         (BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE)
+@@ -85,6 +95,8 @@ static void __internal_irq_unmask_64(uns
+ #ifdef CONFIG_BCM63XX_CPU_6362
+ #define irq_stat_reg0         PERF_IRQSTAT_6362_REG(0)
+ #define irq_mask_reg0         PERF_IRQMASK_6362_REG(0)
++#define irq_stat_reg1         PERF_IRQSTAT_6362_REG(1)
++#define irq_mask_reg1         PERF_IRQMASK_6362_REG(1)
+ #define irq_bits              64
+ #define is_ext_irq_cascaded   1
+ #define ext_irq_start         (BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE)
+@@ -96,6 +108,8 @@ static void __internal_irq_unmask_64(uns
+ #ifdef CONFIG_BCM63XX_CPU_6368
+ #define irq_stat_reg0         PERF_IRQSTAT_6368_REG(0)
+ #define irq_mask_reg0         PERF_IRQMASK_6368_REG(0)
++#define irq_stat_reg1         PERF_IRQSTAT_6368_REG(1)
++#define irq_mask_reg1         PERF_IRQMASK_6368_REG(1)
+ #define irq_bits              64
+ #define is_ext_irq_cascaded   1
+ #define ext_irq_start         (BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE)
+@@ -117,13 +131,15 @@ static void __internal_irq_unmask_64(uns
+ #define irq_stat_addr0        (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg0)
+ #define irq_mask_addr0        (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg0)
++#define irq_stat_addr1        (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg1)
++#define irq_mask_addr1        (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg1)
+ static inline void bcm63xx_init_irq(void)
+ {
+ }
+ #else /* ! BCMCPU_RUNTIME_DETECT */
+-static u32 irq_stat_addr0, irq_mask_addr0;
++static u32 irq_stat_addr0, irq_mask_addr0, irq_stat_addr1, irq_mask_addr1;
+ static void (*dispatch_internal)(void);
+ static int is_ext_irq_cascaded;
+ static unsigned int ext_irq_count;
+@@ -138,11 +154,15 @@ static void bcm63xx_init_irq(void)
+       irq_stat_addr0 = bcm63xx_regset_address(RSET_PERF);
+       irq_mask_addr0 = bcm63xx_regset_address(RSET_PERF);
++      irq_stat_addr1 = bcm63xx_regset_address(RSET_PERF);
++      irq_mask_addr1 = bcm63xx_regset_address(RSET_PERF);
+       switch (bcm63xx_get_cpu_id()) {
+       case BCM6328_CPU_ID:
+               irq_stat_addr0 += PERF_IRQSTAT_6328_REG(0);
+               irq_mask_addr0 += PERF_IRQMASK_6328_REG(0);
++              irq_stat_addr1 += PERF_IRQSTAT_6328_REG(1);
++              irq_stat_addr1 += PERF_IRQMASK_6328_REG(1);
+               irq_bits = 64;
+               ext_irq_count = 4;
+               is_ext_irq_cascaded = 1;
+@@ -174,6 +194,8 @@ static void bcm63xx_init_irq(void)
+       case BCM6358_CPU_ID:
+               irq_stat_addr0 += PERF_IRQSTAT_6358_REG(0);
+               irq_mask_addr0 += PERF_IRQMASK_6358_REG(0);
++              irq_stat_addr1 += PERF_IRQSTAT_6358_REG(1);
++              irq_mask_addr1 += PERF_IRQMASK_6358_REG(1);
+               irq_bits = 32;
+               ext_irq_count = 4;
+               is_ext_irq_cascaded = 1;
+@@ -184,6 +206,8 @@ static void bcm63xx_init_irq(void)
+       case BCM6362_CPU_ID:
+               irq_stat_addr0 += PERF_IRQSTAT_6362_REG(0);
+               irq_mask_addr0 += PERF_IRQMASK_6362_REG(0);
++              irq_stat_addr1 += PERF_IRQSTAT_6362_REG(1);
++              irq_mask_addr1 += PERF_IRQMASK_6362_REG(1);
+               irq_bits = 64;
+               ext_irq_count = 4;
+               is_ext_irq_cascaded = 1;
+@@ -194,6 +218,8 @@ static void bcm63xx_init_irq(void)
+       case BCM6368_CPU_ID:
+               irq_stat_addr0 += PERF_IRQSTAT_6368_REG(0);
+               irq_mask_addr0 += PERF_IRQMASK_6368_REG(0);
++              irq_stat_addr1 += PERF_IRQSTAT_6368_REG(1);
++              irq_mask_addr1 += PERF_IRQMASK_6368_REG(1);
+               irq_bits = 64;
+               ext_irq_count = 6;
+               is_ext_irq_cascaded = 1;
diff --git a/target/linux/brcm63xx/patches-3.9/317-MIPS-BCM63XX-use-a-helper-for-getting-the-right-regi.patch b/target/linux/brcm63xx/patches-3.9/317-MIPS-BCM63XX-use-a-helper-for-getting-the-right-regi.patch
new file mode 100644 (file)
index 0000000..3931b21
--- /dev/null
@@ -0,0 +1,80 @@
+From 7c9d3fe01034adbb890aab7c44534658f89c211b Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Thu, 25 Apr 2013 15:35:12 +0200
+Subject: [PATCH 08/13] MIPS: BCM63XX: use a helper for getting the right
+ register address
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/irq.c |   30 ++++++++++++++++++++++++------
+ 1 file changed, 24 insertions(+), 6 deletions(-)
+
+--- a/arch/mips/bcm63xx/irq.c
++++ b/arch/mips/bcm63xx/irq.c
+@@ -251,6 +251,20 @@ static inline u32 get_ext_irq_perf_reg(i
+       return ext_irq_cfg_reg2;
+ }
++static inline u32 get_irq_stat_addr(int cpu)
++{
++      if (cpu == 0)
++              return irq_stat_addr0;
++      return irq_stat_addr1;
++}
++
++static inline u32 get_irq_mask_addr(int cpu)
++{
++      if (cpu == 0)
++              return irq_mask_addr0;
++      return irq_mask_addr1;
++}
++
+ static inline void handle_internal(int intbit)
+ {
+       if (is_ext_irq_cascaded &&
+@@ -274,13 +288,15 @@ void __dispatch_internal_##width(void)
+       unsigned int src, tgt;                                          \
+       bool irqs_pending = false;                                      \
+       static int i;                                                   \
++      u32 irq_stat_addr = get_irq_stat_addr(0);                       \
++      u32 irq_mask_addr = get_irq_mask_addr(0);                       \
+                                                                       \
+       /* read registers in reverse order */                           \
+       for (src = 0, tgt = (width / 32); src < (width / 32); src++) {  \
+               u32 val;                                                \
+                                                                       \
+-              val = bcm_readl(irq_stat_addr0 + src * sizeof(u32));    \
+-              val &= bcm_readl(irq_mask_addr0 + src * sizeof(u32));   \
++              val = bcm_readl(irq_stat_addr + src * sizeof(u32));     \
++              val &= bcm_readl(irq_mask_addr + src * sizeof(u32));    \
+               pending[--tgt] = val;                                   \
+                                                                       \
+               if (val)                                                \
+@@ -306,10 +322,11 @@ static void __internal_irq_mask_##width(
+       u32 val;                                                        \
+       unsigned reg = (irq / 32) ^ (width/32 - 1);                     \
+       unsigned bit = irq & 0x1f;                                      \
++      u32 irq_mask_addr = get_irq_mask_addr(0);                       \
+                                                                       \
+-      val = bcm_readl(irq_mask_addr0 + reg * sizeof(u32));            \
++      val = bcm_readl(irq_mask_addr + reg * sizeof(u32));             \
+       val &= ~(1 << bit);                                             \
+-      bcm_writel(val, irq_mask_addr0 + reg * sizeof(u32));            \
++      bcm_writel(val, irq_mask_addr + reg * sizeof(u32));             \
+ }                                                                     \
+                                                                       \
+ static void __internal_irq_unmask_##width(unsigned int irq)           \
+@@ -317,10 +334,11 @@ static void __internal_irq_unmask_##widt
+       u32 val;                                                        \
+       unsigned reg = (irq / 32) ^ (width/32 - 1);                     \
+       unsigned bit = irq & 0x1f;                                      \
++      u32 irq_mask_addr = get_irq_mask_addr(0);                       \
+                                                                       \
+-      val = bcm_readl(irq_mask_addr0 + reg * sizeof(u32));            \
++      val = bcm_readl(irq_mask_addr + reg * sizeof(u32));             \
+       val |= (1 << bit);                                              \
+-      bcm_writel(val, irq_mask_addr0 + reg * sizeof(u32));            \
++      bcm_writel(val, irq_mask_addr + reg * sizeof(u32));             \
+ }
+ BUILD_IPIC_INTERNAL(32);
diff --git a/target/linux/brcm63xx/patches-3.9/318-MIPS-BCM63XX-add-cpu-argument-to-dispatch-internal.patch b/target/linux/brcm63xx/patches-3.9/318-MIPS-BCM63XX-add-cpu-argument-to-dispatch-internal.patch
new file mode 100644 (file)
index 0000000..081ec18
--- /dev/null
@@ -0,0 +1,59 @@
+From 398337c57ebe3c704e0df5f569e6bd860ffe8914 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Fri, 26 Apr 2013 11:21:16 +0200
+Subject: [PATCH 09/13] MIPS: BCM63XX: add cpu argument to dispatch internal
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/irq.c |   14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+--- a/arch/mips/bcm63xx/irq.c
++++ b/arch/mips/bcm63xx/irq.c
+@@ -19,8 +19,8 @@
+ #include <bcm63xx_io.h>
+ #include <bcm63xx_irq.h>
+-static void __dispatch_internal_32(void) __maybe_unused;
+-static void __dispatch_internal_64(void) __maybe_unused;
++static void __dispatch_internal_32(int cpu) __maybe_unused;
++static void __dispatch_internal_64(int cpu) __maybe_unused;
+ static void __internal_irq_mask_32(unsigned int irq) __maybe_unused;
+ static void __internal_irq_mask_64(unsigned int irq) __maybe_unused;
+ static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
+@@ -140,7 +140,7 @@ static inline void bcm63xx_init_irq(void
+ #else /* ! BCMCPU_RUNTIME_DETECT */
+ static u32 irq_stat_addr0, irq_mask_addr0, irq_stat_addr1, irq_mask_addr1;
+-static void (*dispatch_internal)(void);
++static void (*dispatch_internal)(int cpu);
+ static int is_ext_irq_cascaded;
+ static unsigned int ext_irq_count;
+ static unsigned int ext_irq_start, ext_irq_end;
+@@ -282,14 +282,14 @@ static inline void handle_internal(int i
+  */
+ #define BUILD_IPIC_INTERNAL(width)                                    \
+-void __dispatch_internal_##width(void)                                        \
++void __dispatch_internal_##width(int cpu)                             \
+ {                                                                     \
+       u32 pending[width / 32];                                        \
+       unsigned int src, tgt;                                          \
+       bool irqs_pending = false;                                      \
+       static int i;                                                   \
+-      u32 irq_stat_addr = get_irq_stat_addr(0);                       \
+-      u32 irq_mask_addr = get_irq_mask_addr(0);                       \
++      u32 irq_stat_addr = get_irq_stat_addr(cpu);                     \
++      u32 irq_mask_addr = get_irq_mask_addr(cpu);                     \
+                                                                       \
+       /* read registers in reverse order */                           \
+       for (src = 0, tgt = (width / 32); src < (width / 32); src++) {  \
+@@ -361,7 +361,7 @@ asmlinkage void plat_irq_dispatch(void)
+               if (cause & CAUSEF_IP1)
+                       do_IRQ(1);
+               if (cause & CAUSEF_IP2)
+-                      dispatch_internal();
++                      dispatch_internal(0);
+               if (!is_ext_irq_cascaded) {
+                       if (cause & CAUSEF_IP3)
+                               do_IRQ(IRQ_EXT_0);
diff --git a/target/linux/brcm63xx/patches-3.9/319-MIPS-BCM63XX-protect-irq-register-accesses-with-a-sp.patch b/target/linux/brcm63xx/patches-3.9/319-MIPS-BCM63XX-protect-irq-register-accesses-with-a-sp.patch
new file mode 100644 (file)
index 0000000..76e8c32
--- /dev/null
@@ -0,0 +1,174 @@
+From 7b8e7bc9806b61be2f07bf2bbb5e3ee6e0f333e9 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Sun, 21 Apr 2013 15:38:56 +0200
+Subject: [PATCH 10/13] MIPS: BCM63XX: protect irq register accesses with a
+ spinlock
+
+Since IRQs can be handled on both CPUs, we need to ensure that we
+don't try to modify the IRQ registers at the same time.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/irq.c |   47 ++++++++++++++++++++++++++++++++++++++++++-----
+ 1 file changed, 42 insertions(+), 5 deletions(-)
+
+--- a/arch/mips/bcm63xx/irq.c
++++ b/arch/mips/bcm63xx/irq.c
+@@ -12,6 +12,7 @@
+ #include <linux/interrupt.h>
+ #include <linux/module.h>
+ #include <linux/irq.h>
++#include <linux/spinlock.h>
+ #include <asm/irq_cpu.h>
+ #include <asm/mipsregs.h>
+ #include <bcm63xx_cpu.h>
+@@ -26,6 +27,9 @@ static void __internal_irq_mask_64(unsig
+ static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
+ static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
++static DEFINE_SPINLOCK(ipic_lock);
++static DEFINE_SPINLOCK(epic_lock);
++
+ #ifndef BCMCPU_RUNTIME_DETECT
+ #ifdef CONFIG_BCM63XX_CPU_6328
+ #define irq_stat_reg0         PERF_IRQSTAT_6328_REG(0)
+@@ -290,7 +294,9 @@ void __dispatch_internal_##width(int cpu
+       static int i;                                                   \
+       u32 irq_stat_addr = get_irq_stat_addr(cpu);                     \
+       u32 irq_mask_addr = get_irq_mask_addr(cpu);                     \
++      unsigned long flags;                                            \
+                                                                       \
++      spin_lock_irqsave(&ipic_lock, flags);                           \
+       /* read registers in reverse order */                           \
+       for (src = 0, tgt = (width / 32); src < (width / 32); src++) {  \
+               u32 val;                                                \
+@@ -302,6 +308,7 @@ void __dispatch_internal_##width(int cpu
+               if (val)                                                \
+                       irqs_pending = true;                            \
+       }                                                               \
++      spin_unlock_irqrestore(&ipic_lock, flags);                      \
+                                                                       \
+       if (!irqs_pending)                                              \
+               return;                                                 \
+@@ -381,12 +388,20 @@ asmlinkage void plat_irq_dispatch(void)
+  */
+ static void bcm63xx_internal_irq_mask(struct irq_data *d)
+ {
++      unsigned long flags;
++
++      spin_lock_irqsave(&ipic_lock, flags);
+       internal_irq_mask(d->irq - IRQ_INTERNAL_BASE);
++      spin_unlock_irqrestore(&ipic_lock, flags);
+ }
+ static void bcm63xx_internal_irq_unmask(struct irq_data *d)
+ {
++      unsigned long flags;
++
++      spin_lock_irqsave(&ipic_lock, flags);
+       internal_irq_unmask(d->irq - IRQ_INTERNAL_BASE);
++      spin_unlock_irqrestore(&ipic_lock, flags);
+ }
+ /*
+@@ -397,8 +412,11 @@ static void bcm63xx_external_irq_mask(st
+ {
+       unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
+       u32 reg, regaddr;
++      unsigned long flags;
+       regaddr = get_ext_irq_perf_reg(irq);
++
++      spin_lock_irqsave(&epic_lock, flags);
+       reg = bcm_perf_readl(regaddr);
+       if (BCMCPU_IS_6348())
+@@ -407,16 +425,24 @@ static void bcm63xx_external_irq_mask(st
+               reg &= ~EXTIRQ_CFG_MASK(irq % 4);
+       bcm_perf_writel(reg, regaddr);
+-      if (is_ext_irq_cascaded)
+-              internal_irq_mask(irq + ext_irq_start);
++      spin_unlock_irqrestore(&epic_lock, flags);
++
++      if (is_ext_irq_cascaded) {
++              struct irq_data *cd = irq_get_irq_data(irq + ext_irq_start);
++
++              bcm63xx_internal_irq_mask(cd);
++      }
+ }
+ static void bcm63xx_external_irq_unmask(struct irq_data *d)
+ {
+       unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
+       u32 reg, regaddr;
++      unsigned long flags;
+       regaddr = get_ext_irq_perf_reg(irq);
++
++      spin_lock_irqsave(&epic_lock, flags);
+       reg = bcm_perf_readl(regaddr);
+       if (BCMCPU_IS_6348())
+@@ -425,16 +451,22 @@ static void bcm63xx_external_irq_unmask(
+               reg |= EXTIRQ_CFG_MASK(irq % 4);
+       bcm_perf_writel(reg, regaddr);
++      spin_unlock_irqrestore(&epic_lock, flags);
++
++      if (is_ext_irq_cascaded) {
++              struct irq_data *cd = irq_get_irq_data(irq + ext_irq_start);
+-      if (is_ext_irq_cascaded)
+-              internal_irq_unmask(irq + ext_irq_start);
++              bcm63xx_internal_irq_unmask(cd);
++      }
+ }
+ static void bcm63xx_external_irq_clear(struct irq_data *d)
+ {
+       unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
+       u32 reg, regaddr;
++      unsigned long flags;
++      spin_lock_irqsave(&epic_lock, flags);
+       regaddr = get_ext_irq_perf_reg(irq);
+       reg = bcm_perf_readl(regaddr);
+@@ -444,6 +476,7 @@ static void bcm63xx_external_irq_clear(s
+               reg |= EXTIRQ_CFG_CLEAR(irq % 4);
+       bcm_perf_writel(reg, regaddr);
++      spin_unlock_irqrestore(&epic_lock, flags);
+ }
+ static int bcm63xx_external_irq_set_type(struct irq_data *d,
+@@ -452,6 +485,7 @@ static int bcm63xx_external_irq_set_type
+       unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
+       u32 reg, regaddr;
+       int levelsense, sense, bothedge;
++      unsigned long flags;
+       flow_type &= IRQ_TYPE_SENSE_MASK;
+@@ -486,9 +520,11 @@ static int bcm63xx_external_irq_set_type
+       }
+       regaddr = get_ext_irq_perf_reg(irq);
+-      reg = bcm_perf_readl(regaddr);
+       irq %= 4;
++      spin_lock_irqsave(&epic_lock, flags);
++      reg = bcm_perf_readl(regaddr);
++
+       switch (bcm63xx_get_cpu_id()) {
+       case BCM6348_CPU_ID:
+               if (levelsense)
+@@ -529,6 +565,7 @@ static int bcm63xx_external_irq_set_type
+       }
+       bcm_perf_writel(reg, regaddr);
++      spin_unlock_irqrestore(&epic_lock, flags);
+       irqd_set_trigger_type(d, flow_type);
+       if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
diff --git a/target/linux/brcm63xx/patches-3.9/320-MIPS-BCM63XX-wire-up-the-second-CPU-s-irq-line.patch b/target/linux/brcm63xx/patches-3.9/320-MIPS-BCM63XX-wire-up-the-second-CPU-s-irq-line.patch
new file mode 100644 (file)
index 0000000..2acbf30
--- /dev/null
@@ -0,0 +1,96 @@
+From 1baec3216529f795905b6376f9c8e4f14b114ba2 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Fri, 26 Apr 2013 12:03:15 +0200
+Subject: [PATCH 11/13] MIPS: BCM63XX: wire up the second CPU's irq line
+
+It's hardwired to IRQ3, so we don't need to actually check the CPU id.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/irq.c |   40 ++++++++++++++++++++++++++++++++--------
+ 1 file changed, 32 insertions(+), 8 deletions(-)
+
+--- a/arch/mips/bcm63xx/irq.c
++++ b/arch/mips/bcm63xx/irq.c
+@@ -329,11 +329,15 @@ static void __internal_irq_mask_##width(
+       u32 val;                                                        \
+       unsigned reg = (irq / 32) ^ (width/32 - 1);                     \
+       unsigned bit = irq & 0x1f;                                      \
+-      u32 irq_mask_addr = get_irq_mask_addr(0);                       \
++      int cpu;                                                        \
+                                                                       \
+-      val = bcm_readl(irq_mask_addr + reg * sizeof(u32));             \
+-      val &= ~(1 << bit);                                             \
+-      bcm_writel(val, irq_mask_addr + reg * sizeof(u32));             \
++      for_each_online_cpu(cpu) {                                      \
++              u32 irq_mask_addr = get_irq_mask_addr(cpu);             \
++                                                                      \
++              val = bcm_readl(irq_mask_addr + reg * sizeof(u32));     \
++              val &= ~(1 << bit);                                     \
++              bcm_writel(val, irq_mask_addr + reg * sizeof(u32));     \
++      }                                                               \
+ }                                                                     \
+                                                                       \
+ static void __internal_irq_unmask_##width(unsigned int irq)           \
+@@ -341,11 +345,15 @@ static void __internal_irq_unmask_##widt
+       u32 val;                                                        \
+       unsigned reg = (irq / 32) ^ (width/32 - 1);                     \
+       unsigned bit = irq & 0x1f;                                      \
+-      u32 irq_mask_addr = get_irq_mask_addr(0);                       \
++      int cpu;                                                        \
++                                                                      \
++      for_each_online_cpu(cpu) {                                      \
++              u32 irq_mask_addr = get_irq_mask_addr(cpu);             \
+                                                                       \
+-      val = bcm_readl(irq_mask_addr + reg * sizeof(u32));             \
+-      val |= (1 << bit);                                              \
+-      bcm_writel(val, irq_mask_addr + reg * sizeof(u32));             \
++              val = bcm_readl(irq_mask_addr + reg * sizeof(u32));     \
++              val |= (1 << bit);                                      \
++              bcm_writel(val, irq_mask_addr + reg * sizeof(u32));     \
++      }                                                               \
+ }
+ BUILD_IPIC_INTERNAL(32);
+@@ -369,6 +377,10 @@ asmlinkage void plat_irq_dispatch(void)
+                       do_IRQ(1);
+               if (cause & CAUSEF_IP2)
+                       dispatch_internal(0);
++#ifdef CONFIG_SMP
++              if (cause & CAUSEF_IP3)
++                      dispatch_internal(1);
++#else
+               if (!is_ext_irq_cascaded) {
+                       if (cause & CAUSEF_IP3)
+                               do_IRQ(IRQ_EXT_0);
+@@ -379,6 +391,7 @@ asmlinkage void plat_irq_dispatch(void)
+                       if (cause & CAUSEF_IP6)
+                               do_IRQ(IRQ_EXT_3);
+               }
++#endif
+       } while (1);
+ }
+@@ -598,6 +611,14 @@ static struct irqaction cpu_ip2_cascade_
+       .flags          = IRQF_NO_THREAD,
+ };
++#ifdef CONFIG_SMP
++static struct irqaction cpu_ip3_cascade_action = {
++      .handler        = no_action,
++      .name           = "cascade_ip3",
++      .flags          = IRQF_NO_THREAD,
++};
++#endif
++
+ static struct irqaction cpu_ext_cascade_action = {
+       .handler        = no_action,
+       .name           = "cascade_extirq",
+@@ -624,4 +645,7 @@ void __init arch_init_irq(void)
+       }
+       setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action);
++#ifdef CONFIG_SMP
++      setup_irq(MIPS_CPU_IRQ_BASE + 3, &cpu_ip3_cascade_action);
++#endif
+ }
diff --git a/target/linux/brcm63xx/patches-3.9/321-MIPS-BCM63XX-add-cpumask-argument-to-unmask.patch b/target/linux/brcm63xx/patches-3.9/321-MIPS-BCM63XX-add-cpumask-argument-to-unmask.patch
new file mode 100644 (file)
index 0000000..1047de3
--- /dev/null
@@ -0,0 +1,68 @@
+From 8679976d2ec08db4e4a14ecdd1ee022b70e51fc6 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Tue, 30 Apr 2013 11:26:53 +0200
+Subject: [PATCH 12/13] MIPS: BCM63XX: add cpumask argument to unmask
+
+Allow selective unmasking of IPIC irqs.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/irq.c |   19 +++++++++++++------
+ 1 file changed, 13 insertions(+), 6 deletions(-)
+
+--- a/arch/mips/bcm63xx/irq.c
++++ b/arch/mips/bcm63xx/irq.c
+@@ -24,8 +24,10 @@ static void __dispatch_internal_32(int c
+ static void __dispatch_internal_64(int cpu) __maybe_unused;
+ static void __internal_irq_mask_32(unsigned int irq) __maybe_unused;
+ static void __internal_irq_mask_64(unsigned int irq) __maybe_unused;
+-static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
+-static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
++static void __internal_irq_unmask_32(unsigned int irq,
++                                   const struct cpumask *dest) __maybe_unused;
++static void __internal_irq_unmask_64(unsigned int irq,
++                                   const struct cpumask *dest) __maybe_unused;
+ static DEFINE_SPINLOCK(ipic_lock);
+ static DEFINE_SPINLOCK(epic_lock);
+@@ -150,7 +152,8 @@ static unsigned int ext_irq_count;
+ static unsigned int ext_irq_start, ext_irq_end;
+ static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2;
+ static void (*internal_irq_mask)(unsigned int irq);
+-static void (*internal_irq_unmask)(unsigned int irq);
++static void (*internal_irq_unmask)(unsigned int irq,
++                                 const struct cpumask *dest);
+ static void bcm63xx_init_irq(void)
+ {
+@@ -340,7 +343,8 @@ static void __internal_irq_mask_##width(
+       }                                                               \
+ }                                                                     \
+                                                                       \
+-static void __internal_irq_unmask_##width(unsigned int irq)           \
++static void __internal_irq_unmask_##width(unsigned int irq,           \
++                                      const struct cpumask *dest)     \
+ {                                                                     \
+       u32 val;                                                        \
+       unsigned reg = (irq / 32) ^ (width/32 - 1);                     \
+@@ -351,7 +355,10 @@ static void __internal_irq_unmask_##widt
+               u32 irq_mask_addr = get_irq_mask_addr(cpu);             \
+                                                                       \
+               val = bcm_readl(irq_mask_addr + reg * sizeof(u32));     \
+-              val |= (1 << bit);                                      \
++              if (cpu_isset(cpu, *dest))                              \
++                      val |= (1 << bit);                              \
++              else                                                    \
++                      val &= ~(1 << bit);                             \
+               bcm_writel(val, irq_mask_addr + reg * sizeof(u32));     \
+       }                                                               \
+ }
+@@ -413,7 +420,7 @@ static void bcm63xx_internal_irq_unmask(
+       unsigned long flags;
+       spin_lock_irqsave(&ipic_lock, flags);
+-      internal_irq_unmask(d->irq - IRQ_INTERNAL_BASE);
++      internal_irq_unmask(d->irq - IRQ_INTERNAL_BASE, cpu_online_mask);
+       spin_unlock_irqrestore(&ipic_lock, flags);
+ }
diff --git a/target/linux/brcm63xx/patches-3.9/322-MIPS-BCM63XX-allow-setting-affinity-for-IPIC.patch b/target/linux/brcm63xx/patches-3.9/322-MIPS-BCM63XX-allow-setting-affinity-for-IPIC.patch
new file mode 100644 (file)
index 0000000..d976903
--- /dev/null
@@ -0,0 +1,61 @@
+From a8bb19e5ba9a3a73fe6a761295b67b641a7bc9df Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Fri, 26 Apr 2013 12:06:03 +0200
+Subject: [PATCH 13/13] MIPS: BCM63XX: allow setting affinity for IPIC
+
+Add support for setting the SMP affinity for the IPIC IRQs.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/irq.c |   27 ++++++++++++++++++++++++++-
+ 1 file changed, 26 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/bcm63xx/irq.c
++++ b/arch/mips/bcm63xx/irq.c
+@@ -418,9 +418,14 @@ static void bcm63xx_internal_irq_mask(st
+ static void bcm63xx_internal_irq_unmask(struct irq_data *d)
+ {
+       unsigned long flags;
++      const struct cpumask *dest = cpu_online_mask;
+       spin_lock_irqsave(&ipic_lock, flags);
+-      internal_irq_unmask(d->irq - IRQ_INTERNAL_BASE, cpu_online_mask);
++#ifdef CONFIG_SMP
++      if (irqd_affinity_was_set(d))
++              dest = d->affinity;
++#endif
++      internal_irq_unmask(d->irq - IRQ_INTERNAL_BASE, dest);
+       spin_unlock_irqrestore(&ipic_lock, flags);
+ }
+@@ -596,10 +601,30 @@ static int bcm63xx_external_irq_set_type
+       return IRQ_SET_MASK_OK_NOCOPY;
+ }
++#ifdef CONFIG_SMP
++static int bcm63xx_internal_set_affinity(struct irq_data *data,
++                                       const struct cpumask *dest,
++                                       bool force)
++{
++      unsigned int irq = data->irq - IRQ_INTERNAL_BASE;
++      unsigned long flags;
++
++      spin_lock_irqsave(&ipic_lock, flags);
++      if (!irqd_irq_disabled(data))
++              internal_irq_unmask(irq, dest);
++      spin_unlock_irqrestore(&ipic_lock, flags);
++
++      return 0;
++}
++#endif
++
+ static struct irq_chip bcm63xx_internal_irq_chip = {
+       .name           = "bcm63xx_ipic",
+       .irq_mask       = bcm63xx_internal_irq_mask,
+       .irq_unmask     = bcm63xx_internal_irq_unmask,
++#ifdef CONFIG_SMP
++      .irq_set_affinity = bcm63xx_internal_set_affinity,
++#endif
+ };
+ static struct irq_chip bcm63xx_external_irq_chip = {
diff --git a/target/linux/brcm63xx/patches-3.9/323-cfe_simplify_detection.patch b/target/linux/brcm63xx/patches-3.9/323-cfe_simplify_detection.patch
new file mode 100644 (file)
index 0000000..e05c91d
--- /dev/null
@@ -0,0 +1,20 @@
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_board.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_board.h
+@@ -1,6 +1,8 @@
+ #ifndef BCM63XX_BOARD_H_
+ #define BCM63XX_BOARD_H_
++#include <asm/bootinfo.h>
++
+ const char *board_get_name(void);
+ void board_prom_init(void);
+@@ -9,4 +11,8 @@ void board_setup(void);
+ int board_register_devices(void);
++static inline bool bcm63xx_is_cfe_present(void) {
++      return fw_arg3 == 0x43464531;
++}
++
+ #endif /* ! BCM63XX_BOARD_H_ */
diff --git a/target/linux/brcm63xx/patches-3.9/324-bcm63xxpart_use_cfedetection.patch b/target/linux/brcm63xx/patches-3.9/324-bcm63xxpart_use_cfedetection.patch
new file mode 100644 (file)
index 0000000..fd7d08a
--- /dev/null
@@ -0,0 +1,51 @@
+--- a/drivers/mtd/bcm63xxpart.c
++++ b/drivers/mtd/bcm63xxpart.c
+@@ -35,7 +35,7 @@
+ #include <linux/bcm963xx_tag.h>
+ #include <asm/mach-bcm63xx/bcm63xx_nvram.h>
+-#include <asm/mach-bcm63xx/board_bcm963xx.h>
++#include <asm/mach-bcm63xx/bcm63xx_board.h>
+ #define BCM63XX_EXTENDED_SIZE 0xBFC00000      /* Extended flash address */
+@@ -43,30 +43,6 @@
+ #define BCM63XX_CFE_MAGIC_OFFSET 0x4e0
+-static int bcm63xx_detect_cfe(struct mtd_info *master)
+-{
+-      char buf[9];
+-      int ret;
+-      size_t retlen;
+-
+-      ret = mtd_read(master, BCM963XX_CFE_VERSION_OFFSET, 5, &retlen,
+-                     (void *)buf);
+-      buf[retlen] = 0;
+-
+-      if (ret)
+-              return ret;
+-
+-      if (strncmp("cfe-v", buf, 5) == 0)
+-              return 0;
+-
+-      /* very old CFE's do not have the cfe-v string, so check for magic */
+-      ret = mtd_read(master, BCM63XX_CFE_MAGIC_OFFSET, 8, &retlen,
+-                     (void *)buf);
+-      buf[retlen] = 0;
+-
+-      return strncmp("CFE1CFE1", buf, 8);
+-}
+-
+ static int bcm63xx_parse_cfe_partitions(struct mtd_info *master,
+                                       struct mtd_partition **pparts,
+                                       struct mtd_part_parser_data *data)
+@@ -85,7 +61,7 @@ static int bcm63xx_parse_cfe_partitions(
+       u32 computed_crc;
+       bool rootfs_first = false;
+-      if (bcm63xx_detect_cfe(master))
++      if (!bcm63xx_is_cfe_present())
+               return -EINVAL;
+       cfe_erasesize = max_t(uint32_t, master->erasesize,
diff --git a/target/linux/brcm63xx/patches-3.9/400-bcm963xx_flashmap.patch b/target/linux/brcm63xx/patches-3.9/400-bcm963xx_flashmap.patch
new file mode 100644 (file)
index 0000000..1aadfff
--- /dev/null
@@ -0,0 +1,65 @@
+From a4d005c91d403d9f3d0272db6cc46202c06ec774 Mon Sep 17 00:00:00 2001
+From: Axel Gembe <ago@bastart.eu.org>
+Date: Mon, 12 May 2008 18:54:09 +0200
+Subject: [PATCH] bcm963xx: flashmap support
+
+Signed-off-by: Axel Gembe <ago@bastart.eu.org>
+---
+ arch/mips/bcm63xx/boards/board_bcm963xx.c |   19 +----------------
+ drivers/mtd/maps/bcm963xx-flash.c         |   32 ++++++++++++++++++++++++----
+ drivers/mtd/redboot.c                     |   13 +++++++++--
+ 3 files changed, 38 insertions(+), 26 deletions(-)
+
+--- a/arch/mips/bcm63xx/dev-flash.c
++++ b/arch/mips/bcm63xx/dev-flash.c
+@@ -30,7 +30,7 @@ static struct mtd_partition mtd_partitio
+       }
+ };
+-static const char *bcm63xx_part_types[] = { "bcm63xxpart", NULL };
++static const char *bcm63xx_part_types[] = { "bcm63xxpart", "RedBoot", NULL };
+ static struct physmap_flash_data flash_data = {
+       .width                  = 2,
+--- a/drivers/mtd/redboot.c
++++ b/drivers/mtd/redboot.c
+@@ -72,6 +72,7 @@ static int parse_redboot_partitions(stru
+       int nulllen = 0;
+       int numslots;
+       unsigned long offset;
++      unsigned long fis_origin = 0;
+ #ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED
+       static char nullstring[] = "unallocated";
+ #endif
+@@ -176,6 +177,16 @@ static int parse_redboot_partitions(stru
+               goto out;
+       }
++      if (data && data->origin) {
++              fis_origin = data->origin;
++      } else {
++              for (i = 0; i < numslots; i++) {
++                      if (!strncmp(buf[i].name, "RedBoot", 8)) {
++                              fis_origin = (buf[i].flash_base & (master->size << 1) - 1);
++                      }
++              }
++      }
++
+       for (i = 0; i < numslots; i++) {
+               struct fis_list *new_fl, **prev;
+@@ -196,10 +207,10 @@ static int parse_redboot_partitions(stru
+                       goto out;
+               }
+               new_fl->img = &buf[i];
+-              if (data && data->origin)
+-                      buf[i].flash_base -= data->origin;
+-              else
+-                      buf[i].flash_base &= master->size-1;
++              if (fis_origin)
++                      buf[i].flash_base -= fis_origin;
++
++              buf[i].flash_base &= (master->size << 1) - 1;
+               /* I'm sure the JFFS2 code has done me permanent damage.
+                * I now think the following is _normal_
diff --git a/target/linux/brcm63xx/patches-3.9/401-bcm963xx_real_rootfs_length.patch b/target/linux/brcm63xx/patches-3.9/401-bcm963xx_real_rootfs_length.patch
new file mode 100644 (file)
index 0000000..caf8b95
--- /dev/null
@@ -0,0 +1,27 @@
+--- a/include/uapi/linux/bcm963xx_tag.h
++++ b/include/uapi/linux/bcm963xx_tag.h
+@@ -85,8 +85,10 @@ struct bcm_tag {
+       __u32 rootfs_crc;
+       /* 224-227: CRC32 of kernel partition */
+       __u32 kernel_crc;
+-      /* 228-235: Unused at present */
+-      char reserved1[8];
++      /* 228-231: Image sequence number */
++      char image_sequence[4];
++      /* 222-235: Openwrt: real rootfs length */
++      __u32 real_rootfs_length;
+       /* 236-239: CRC32 of header excluding last 20 bytes */
+       __u32 header_crc;
+       /* 240-255: Unused at present */
+--- a/drivers/mtd/bcm63xxpart.c
++++ b/drivers/mtd/bcm63xxpart.c
+@@ -110,7 +110,8 @@ static int bcm63xx_parse_cfe_partitions(
+               } else {
+                       /* OpenWrt layout */
+                       rootfsaddr = kerneladdr + kernellen;
+-                      rootfslen = spareaddr - rootfsaddr;
++                      rootfslen = buf->real_rootfs_length;
++                      spareaddr = rootfsaddr + rootfslen;
+               }
+       } else {
+               pr_warn("CFE boot tag CRC invalid (expected %08x, actual %08x)\n",
diff --git a/target/linux/brcm63xx/patches-3.9/402_bcm63xx_enet_vlan_incoming_fixed.patch b/target/linux/brcm63xx/patches-3.9/402_bcm63xx_enet_vlan_incoming_fixed.patch
new file mode 100644 (file)
index 0000000..757d1b9
--- /dev/null
@@ -0,0 +1,11 @@
+--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+@@ -1514,7 +1514,7 @@ static int compute_hw_mtu(struct bcm_ene
+       actual_mtu = mtu;
+       /* add ethernet header + vlan tag size */
+-      actual_mtu += VLAN_ETH_HLEN;
++      actual_mtu += VLAN_ETH_HLEN + VLAN_HLEN;
+       if (actual_mtu < 64 || actual_mtu > BCMENET_MAX_MTU)
+               return -EINVAL;
diff --git a/target/linux/brcm63xx/patches-3.9/403-6358-enet1-external-mii-clk.patch b/target/linux/brcm63xx/patches-3.9/403-6358-enet1-external-mii-clk.patch
new file mode 100644 (file)
index 0000000..4ead53f
--- /dev/null
@@ -0,0 +1,22 @@
+--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+@@ -859,6 +859,8 @@ void __init board_prom_init(void)
+               if (BCMCPU_IS_6348())
+                       val |= GPIO_MODE_6348_G3_EXT_MII |
+                               GPIO_MODE_6348_G0_EXT_MII;
++              else if (BCMCPU_IS_6358())
++                      val |= GPIO_MODE_6358_ENET1_MII_CLK_INV;
+       }
+       bcm_gpio_writel(val, GPIO_MODE_REG);
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -578,6 +578,8 @@
+ #define GPIO_MODE_6358_EXTRA_SPI_SS   (1 << 7)
+ #define GPIO_MODE_6358_SERIAL_LED     (1 << 10)
+ #define GPIO_MODE_6358_UTOPIA         (1 << 12)
++#define GPIO_MODE_6358_ENET1_MII_CLK_INV (1 << 30)
++#define GPIO_MODE_6358_ENET0_MII_CLK_INV (1 << 31)
+ #define GPIO_MODE_6368_ANALOG_AFE_0   (1 << 0)
+ #define GPIO_MODE_6368_ANALOG_AFE_1   (1 << 1)
diff --git a/target/linux/brcm63xx/patches-3.9/404-NET-bcm63xx_enet-move-phy_-dis-connect-into-probe-re.patch b/target/linux/brcm63xx/patches-3.9/404-NET-bcm63xx_enet-move-phy_-dis-connect-into-probe-re.patch
new file mode 100644 (file)
index 0000000..defaa9c
--- /dev/null
@@ -0,0 +1,169 @@
+From b11218c750ab92cfab4408a0328f1b36ceec3f33 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jonas.gorski@gmail.com>
+Date: Fri, 6 Jan 2012 12:24:18 +0100
+Subject: [PATCH 19/63] NET: bcm63xx_enet: move phy_(dis)connect into probe/remove
+
+Only connect/disconnect the phy during probe and remove, not during any
+open/close. The phy seldom changes during the runtime, and disconnecting
+the phy during close will prevent it from keeping any configuration over
+a down/up cycle.
+
+Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
+---
+ drivers/net/ethernet/broadcom/bcm63xx_enet.c |   84 +++++++++++++-------------
+ 1 files changed, 41 insertions(+), 43 deletions(-)
+
+--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+@@ -784,10 +784,8 @@ static int bcm_enet_open(struct net_devi
+       struct bcm_enet_priv *priv;
+       struct sockaddr addr;
+       struct device *kdev;
+-      struct phy_device *phydev;
+       int i, ret;
+       unsigned int size;
+-      char phy_id[MII_BUS_ID_SIZE + 3];
+       void *p;
+       u32 val;
+@@ -795,40 +793,10 @@ static int bcm_enet_open(struct net_devi
+       kdev = &priv->pdev->dev;
+       if (priv->has_phy) {
+-              /* connect to PHY */
+-              snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
+-                       priv->mii_bus->id, priv->phy_id);
+-
+-              phydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link,
+-                                   PHY_INTERFACE_MODE_MII);
+-
+-              if (IS_ERR(phydev)) {
+-                      dev_err(kdev, "could not attach to PHY\n");
+-                      return PTR_ERR(phydev);
+-              }
+-
+-              /* mask with MAC supported features */
+-              phydev->supported &= (SUPPORTED_10baseT_Half |
+-                                    SUPPORTED_10baseT_Full |
+-                                    SUPPORTED_100baseT_Half |
+-                                    SUPPORTED_100baseT_Full |
+-                                    SUPPORTED_Autoneg |
+-                                    SUPPORTED_Pause |
+-                                    SUPPORTED_MII);
+-              phydev->advertising = phydev->supported;
+-
+-              if (priv->pause_auto && priv->pause_rx && priv->pause_tx)
+-                      phydev->advertising |= SUPPORTED_Pause;
+-              else
+-                      phydev->advertising &= ~SUPPORTED_Pause;
+-
+-              dev_info(kdev, "attached PHY at address %d [%s]\n",
+-                       phydev->addr, phydev->drv->name);
+-
++              /* Reset state */
+               priv->old_link = 0;
+               priv->old_duplex = -1;
+               priv->old_pause = -1;
+-              priv->phydev = phydev;
+       }
+       /* mask all interrupts and request them */
+@@ -838,7 +806,7 @@ static int bcm_enet_open(struct net_devi
+       ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
+       if (ret)
+-              goto out_phy_disconnect;
++              return ret;
+       ret = request_irq(priv->irq_rx, bcm_enet_isr_dma, IRQF_DISABLED,
+                         dev->name, dev);
+@@ -1023,9 +991,6 @@ out_freeirq_rx:
+ out_freeirq:
+       free_irq(dev->irq, dev);
+-out_phy_disconnect:
+-      phy_disconnect(priv->phydev);
+-
+       return ret;
+ }
+@@ -1130,12 +1095,6 @@ static int bcm_enet_stop(struct net_devi
+       free_irq(priv->irq_rx, dev);
+       free_irq(dev->irq, dev);
+-      /* release phy */
+-      if (priv->has_phy) {
+-              phy_disconnect(priv->phydev);
+-              priv->phydev = NULL;
+-      }
+-
+       return 0;
+ }
+@@ -1707,6 +1666,8 @@ static int bcm_enet_probe(struct platfor
+       /* MII bus registration */
+       if (priv->has_phy) {
++              struct phy_device *phydev;
++              char phy_id[MII_BUS_ID_SIZE + 3];
+               priv->mii_bus = mdiobus_alloc();
+               if (!priv->mii_bus) {
+@@ -1744,6 +1705,38 @@ static int bcm_enet_probe(struct platfor
+                       dev_err(&pdev->dev, "unable to register mdio bus\n");
+                       goto out_free_mdio;
+               }
++
++              /* connect to PHY */
++              snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
++                       priv->mii_bus->id, priv->phy_id);
++
++              phydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link,
++                                   PHY_INTERFACE_MODE_MII);
++
++              if (IS_ERR(phydev)) {
++                      dev_err(&pdev->dev, "could not attach to PHY\n");
++                      goto out_unregister_mdio;
++              }
++
++              /* mask with MAC supported features */
++              phydev->supported &= (SUPPORTED_10baseT_Half |
++                                    SUPPORTED_10baseT_Full |
++                                    SUPPORTED_100baseT_Half |
++                                    SUPPORTED_100baseT_Full |
++                                    SUPPORTED_Autoneg |
++                                    SUPPORTED_Pause |
++                                    SUPPORTED_MII);
++              phydev->advertising = phydev->supported;
++
++              if (priv->pause_auto && priv->pause_rx && priv->pause_tx)
++                      phydev->advertising |= SUPPORTED_Pause;
++              else
++                      phydev->advertising &= ~SUPPORTED_Pause;
++
++              dev_info(&pdev->dev, "attached PHY at address %d [%s]\n",
++                       phydev->addr, phydev->drv->name);
++
++              priv->phydev = phydev;
+       } else {
+               /* run platform code to initialize PHY device */
+@@ -1789,6 +1782,9 @@ static int bcm_enet_probe(struct platfor
+       return 0;
+ out_unregister_mdio:
++      if (priv->phydev)
++              phy_disconnect(priv->phydev);
++
+       if (priv->mii_bus)
+               mdiobus_unregister(priv->mii_bus);
+@@ -1830,6 +1826,8 @@ static int bcm_enet_remove(struct platfo
+       enet_writel(priv, 0, ENET_MIISC_REG);
+       if (priv->has_phy) {
++              phy_disconnect(priv->phydev);
++              priv->phydev = NULL;
+               mdiobus_unregister(priv->mii_bus);
+               mdiobus_free(priv->mii_bus);
+       } else {
diff --git a/target/linux/brcm63xx/patches-3.9/405-bcm63xx_enet-implement-reset_autoneg-ethtool.patch b/target/linux/brcm63xx/patches-3.9/405-bcm63xx_enet-implement-reset_autoneg-ethtool.patch
new file mode 100644 (file)
index 0000000..503b795
--- /dev/null
@@ -0,0 +1,40 @@
+From accc558f334662c8b16c121b4819931c028e8eb0 Mon Sep 17 00:00:00 2001
+From: Maxime Bizon <mbizon@freebox.fr>
+Date: Mon, 8 Jun 2009 16:12:10 +0200
+Subject: [PATCH 27/63] bcm63xx_enet: implement reset_autoneg ethtool.
+
+---
+ drivers/net/ethernet/broadcom/bcm63xx_enet.c |   15 +++++++++++++++
+ 1 files changed, 15 insertions(+), 0 deletions(-)
+
+--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+@@ -1289,6 +1289,20 @@ static void bcm_enet_get_ethtool_stats(s
+       mutex_unlock(&priv->mib_update_lock);
+ }
++static int bcm_enet_nway_reset(struct net_device *dev)
++{
++      struct bcm_enet_priv *priv;
++
++      priv = netdev_priv(dev);
++      if (priv->has_phy) {
++              if (!priv->phydev)
++                      return -ENODEV;
++              return genphy_restart_aneg(priv->phydev);
++      }
++
++      return -EOPNOTSUPP;
++}
++
+ static int bcm_enet_get_settings(struct net_device *dev,
+                                struct ethtool_cmd *cmd)
+ {
+@@ -1431,6 +1445,7 @@ static const struct ethtool_ops bcm_enet
+       .get_strings            = bcm_enet_get_strings,
+       .get_sset_count         = bcm_enet_get_sset_count,
+       .get_ethtool_stats      = bcm_enet_get_ethtool_stats,
++      .nway_reset             = bcm_enet_nway_reset,
+       .get_settings           = bcm_enet_get_settings,
+       .set_settings           = bcm_enet_set_settings,
+       .get_drvinfo            = bcm_enet_get_drvinfo,
diff --git a/target/linux/brcm63xx/patches-3.9/406-bcm63xx_enet-split-dma-registers-access.patch b/target/linux/brcm63xx/patches-3.9/406-bcm63xx_enet-split-dma-registers-access.patch
new file mode 100644 (file)
index 0000000..09257d0
--- /dev/null
@@ -0,0 +1,337 @@
+From 2e5b0197443fcb454ca88619e36bb33d7a79e3ea Mon Sep 17 00:00:00 2001
+From: Maxime Bizon <mbizon@freebox.fr>
+Date: Thu, 21 Jan 2010 17:50:54 +0100
+Subject: [PATCH] bcm63xx_enet: split dma registers access.
+
+---
+ arch/mips/bcm63xx/dev-enet.c                     |   23 +++-
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h |    4 +-
+ drivers/net/ethernet/broadcom/bcm63xx_enet.c     |  144 +++++++++++++---------
+ 3 files changed, 111 insertions(+), 62 deletions(-)
+
+--- a/arch/mips/bcm63xx/dev-enet.c
++++ b/arch/mips/bcm63xx/dev-enet.c
+@@ -19,6 +19,16 @@ static struct resource shared_res[] = {
+               .end            = -1, /* filled at runtime */
+               .flags          = IORESOURCE_MEM,
+       },
++      {
++              .start          = -1, /* filled at runtime */
++              .end            = -1, /* filled at runtime */
++              .flags          = IORESOURCE_MEM,
++      },
++      {
++              .start          = -1, /* filled at runtime */
++              .end            = -1, /* filled at runtime */
++              .flags          = IORESOURCE_MEM,
++      },
+ };
+ static struct platform_device bcm63xx_enet_shared_device = {
+@@ -110,10 +120,15 @@ int __init bcm63xx_enet_register(int uni
+       if (!shared_device_registered) {
+               shared_res[0].start = bcm63xx_regset_address(RSET_ENETDMA);
+               shared_res[0].end = shared_res[0].start;
+-              if (BCMCPU_IS_6338())
+-                      shared_res[0].end += (RSET_ENETDMA_SIZE / 2)  - 1;
+-              else
+-                      shared_res[0].end += (RSET_ENETDMA_SIZE)  - 1;
++              shared_res[0].end += (RSET_ENETDMA_SIZE)  - 1;
++
++              shared_res[1].start = bcm63xx_regset_address(RSET_ENETDMAC);
++              shared_res[1].end = shared_res[1].start;
++              shared_res[1].end += RSET_ENETDMAC_SIZE(16)  - 1;
++
++              shared_res[2].start = bcm63xx_regset_address(RSET_ENETDMAS);
++              shared_res[2].end = shared_res[2].start;
++              shared_res[2].end += RSET_ENETDMAS_SIZE(16)  - 1;
+               ret = platform_device_register(&bcm63xx_enet_shared_device);
+               if (ret)
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+@@ -174,7 +174,9 @@ enum bcm63xx_regs_set {
+ #define BCM_6358_RSET_SPI_SIZE                1804
+ #define BCM_6368_RSET_SPI_SIZE                1804
+ #define RSET_ENET_SIZE                        2048
+-#define RSET_ENETDMA_SIZE             2048
++#define RSET_ENETDMA_SIZE             256
++#define RSET_ENETDMAC_SIZE(chans)     (16 * (chans))
++#define RSET_ENETDMAS_SIZE(chans)     (16 * (chans))
+ #define RSET_ENETSW_SIZE              65536
+ #define RSET_UART_SIZE                        24
+ #define RSET_HSSPI_SIZE                       1536
+--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+@@ -41,8 +41,8 @@ static int copybreak __read_mostly = 128
+ module_param(copybreak, int, 0);
+ MODULE_PARM_DESC(copybreak, "Receive copy threshold");
+-/* io memory shared between all devices */
+-static void __iomem *bcm_enet_shared_base;
++/* io registers memory shared between all devices */
++static void __iomem *bcm_enet_shared_base[3];
+ /*
+  * io helpers to access mac registers
+@@ -63,13 +63,35 @@ static inline void enet_writel(struct bc
+  */
+ static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off)
+ {
+-      return bcm_readl(bcm_enet_shared_base + off);
++      return bcm_readl(bcm_enet_shared_base[0] + off);
+ }
+ static inline void enet_dma_writel(struct bcm_enet_priv *priv,
+                                      u32 val, u32 off)
+ {
+-      bcm_writel(val, bcm_enet_shared_base + off);
++      bcm_writel(val, bcm_enet_shared_base[0] + off);
++}
++
++static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off)
++{
++      return bcm_readl(bcm_enet_shared_base[1] + off);
++}
++
++static inline void enet_dmac_writel(struct bcm_enet_priv *priv,
++                                     u32 val, u32 off)
++{
++      bcm_writel(val, bcm_enet_shared_base[1] + off);
++}
++
++static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off)
++{
++      return bcm_readl(bcm_enet_shared_base[2] + off);
++}
++
++static inline void enet_dmas_writel(struct bcm_enet_priv *priv,
++                                     u32 val, u32 off)
++{
++      bcm_writel(val, bcm_enet_shared_base[2] + off);
+ }
+ /*
+@@ -353,8 +375,8 @@ static int bcm_enet_receive_queue(struct
+               bcm_enet_refill_rx(dev);
+               /* kick rx dma */
+-              enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
+-                              ENETDMA_CHANCFG_REG(priv->rx_chan));
++              enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
++                               ENETDMAC_CHANCFG_REG(priv->rx_chan));
+       }
+       return processed;
+@@ -429,10 +451,10 @@ static int bcm_enet_poll(struct napi_str
+       dev = priv->net_dev;
+       /* ack interrupts */
+-      enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
+-                      ENETDMA_IR_REG(priv->rx_chan));
+-      enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
+-                      ENETDMA_IR_REG(priv->tx_chan));
++      enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
++                       ENETDMAC_IR_REG(priv->rx_chan));
++      enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
++                       ENETDMAC_IR_REG(priv->tx_chan));
+       /* reclaim sent skb */
+       tx_work_done = bcm_enet_tx_reclaim(dev, 0);
+@@ -451,10 +473,10 @@ static int bcm_enet_poll(struct napi_str
+       napi_complete(napi);
+       /* restore rx/tx interrupt */
+-      enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
+-                      ENETDMA_IRMASK_REG(priv->rx_chan));
+-      enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
+-                      ENETDMA_IRMASK_REG(priv->tx_chan));
++      enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
++                       ENETDMAC_IRMASK_REG(priv->rx_chan));
++      enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
++                       ENETDMAC_IRMASK_REG(priv->tx_chan));
+       return rx_work_done;
+ }
+@@ -497,8 +519,8 @@ static irqreturn_t bcm_enet_isr_dma(int
+       priv = netdev_priv(dev);
+       /* mask rx/tx interrupts */
+-      enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
+-      enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
++      enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
++      enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
+       napi_schedule(&priv->napi);
+@@ -557,8 +579,8 @@ static int bcm_enet_start_xmit(struct sk
+       wmb();
+       /* kick tx dma */
+-      enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
+-                      ENETDMA_CHANCFG_REG(priv->tx_chan));
++      enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
++                       ENETDMAC_CHANCFG_REG(priv->tx_chan));
+       /* stop queue if no more desc available */
+       if (!priv->tx_desc_count)
+@@ -801,8 +823,8 @@ static int bcm_enet_open(struct net_devi
+       /* mask all interrupts and request them */
+       enet_writel(priv, 0, ENET_IRMASK_REG);
+-      enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
+-      enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
++      enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
++      enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
+       ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
+       if (ret)
+@@ -889,28 +911,28 @@ static int bcm_enet_open(struct net_devi
+       }
+       /* write rx & tx ring addresses */
+-      enet_dma_writel(priv, priv->rx_desc_dma,
+-                      ENETDMA_RSTART_REG(priv->rx_chan));
+-      enet_dma_writel(priv, priv->tx_desc_dma,
+-                      ENETDMA_RSTART_REG(priv->tx_chan));
++      enet_dmas_writel(priv, priv->rx_desc_dma,
++                       ENETDMAS_RSTART_REG(priv->rx_chan));
++      enet_dmas_writel(priv, priv->tx_desc_dma,
++                       ENETDMAS_RSTART_REG(priv->tx_chan));
+       /* clear remaining state ram for rx & tx channel */
+-      enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->rx_chan));
+-      enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->tx_chan));
+-      enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->rx_chan));
+-      enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->tx_chan));
+-      enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->rx_chan));
+-      enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->tx_chan));
++      enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->rx_chan));
++      enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->tx_chan));
++      enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->rx_chan));
++      enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->tx_chan));
++      enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->rx_chan));
++      enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->tx_chan));
+       /* set max rx/tx length */
+       enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
+       enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
+       /* set dma maximum burst len */
+-      enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
+-                      ENETDMA_MAXBURST_REG(priv->rx_chan));
+-      enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
+-                      ENETDMA_MAXBURST_REG(priv->tx_chan));
++      enet_dmac_writel(priv, BCMENET_DMA_MAXBURST,
++                       ENETDMAC_MAXBURST_REG(priv->rx_chan));
++      enet_dmac_writel(priv, BCMENET_DMA_MAXBURST,
++                       ENETDMAC_MAXBURST_REG(priv->tx_chan));
+       /* set correct transmit fifo watermark */
+       enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
+@@ -928,26 +950,26 @@ static int bcm_enet_open(struct net_devi
+       val |= ENET_CTL_ENABLE_MASK;
+       enet_writel(priv, val, ENET_CTL_REG);
+       enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
+-      enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
+-                      ENETDMA_CHANCFG_REG(priv->rx_chan));
++      enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
++                       ENETDMAC_CHANCFG_REG(priv->rx_chan));
+       /* watch "mib counters about to overflow" interrupt */
+       enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
+       enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
+       /* watch "packet transferred" interrupt in rx and tx */
+-      enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
+-                      ENETDMA_IR_REG(priv->rx_chan));
+-      enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
+-                      ENETDMA_IR_REG(priv->tx_chan));
++      enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
++                       ENETDMAC_IR_REG(priv->rx_chan));
++      enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
++                       ENETDMAC_IR_REG(priv->tx_chan));
+       /* make sure we enable napi before rx interrupt  */
+       napi_enable(&priv->napi);
+-      enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
+-                      ENETDMA_IRMASK_REG(priv->rx_chan));
+-      enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
+-                      ENETDMA_IRMASK_REG(priv->tx_chan));
++      enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
++                       ENETDMAC_IRMASK_REG(priv->rx_chan));
++      enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
++                       ENETDMAC_IRMASK_REG(priv->tx_chan));
+       if (priv->has_phy)
+               phy_start(priv->phydev);
+@@ -1024,14 +1046,14 @@ static void bcm_enet_disable_dma(struct
+ {
+       int limit;
+-      enet_dma_writel(priv, 0, ENETDMA_CHANCFG_REG(chan));
++      enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG_REG(chan));
+       limit = 1000;
+       do {
+               u32 val;
+-              val = enet_dma_readl(priv, ENETDMA_CHANCFG_REG(chan));
+-              if (!(val & ENETDMA_CHANCFG_EN_MASK))
++              val = enet_dmac_readl(priv, ENETDMAC_CHANCFG_REG(chan));
++              if (!(val & ENETDMAC_CHANCFG_EN_MASK))
+                       break;
+               udelay(1);
+       } while (limit--);
+@@ -1057,8 +1079,8 @@ static int bcm_enet_stop(struct net_devi
+       /* mask all interrupts */
+       enet_writel(priv, 0, ENET_IRMASK_REG);
+-      enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
+-      enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
++      enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
++      enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
+       /* make sure no mib update is scheduled */
+       cancel_work_sync(&priv->mib_update_task);
+@@ -1597,7 +1619,7 @@ static int bcm_enet_probe(struct platfor
+       /* stop if shared driver failed, assume driver->probe will be
+        * called in the same order we register devices (correct ?) */
+-      if (!bcm_enet_shared_base)
++      if (!bcm_enet_shared_base[0])
+               return -ENODEV;
+       res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+@@ -1882,14 +1904,24 @@ struct platform_driver bcm63xx_enet_driv
+ static int bcm_enet_shared_probe(struct platform_device *pdev)
+ {
+       struct resource *res;
++      void __iomem *p[3];
++      unsigned int i;
+-      res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+-      if (!res)
+-              return -ENODEV;
++      memset(bcm_enet_shared_base, 0, sizeof(bcm_enet_shared_base));
+-      bcm_enet_shared_base = devm_request_and_ioremap(&pdev->dev, res);
+-      if (!bcm_enet_shared_base)
+-              return -ENOMEM;
++      for (i = 0; i < 3; i++) {
++              res = platform_get_resource(pdev, IORESOURCE_MEM, i);
++              if (!res)
++                      return -EINVAL;
++
++              p[i] = devm_request_and_ioremap(&pdev->dev, res);
++              if (!p[i])
++                      return -ENOMEM;
++
++              bcm_enet_shared_base[i] = p;
++      }
++
++      memcpy(bcm_enet_shared_base, p, sizeof(bcm_enet_shared_base));
+       return 0;
+ }
diff --git a/target/linux/brcm63xx/patches-3.9/407-bcm63xx_enet-add-support-for-bcm6368-internal-ethern.patch b/target/linux/brcm63xx/patches-3.9/407-bcm63xx_enet-add-support-for-bcm6368-internal-ethern.patch
new file mode 100644 (file)
index 0000000..313927c
--- /dev/null
@@ -0,0 +1,1511 @@
+From d16c1a1410f6c35a835baaa445774b4421db6c96 Mon Sep 17 00:00:00 2001
+From: Maxime Bizon <mbizon@freebox.fr>
+Date: Sat, 23 Jan 2010 03:01:02 +0100
+Subject: [PATCH 8/8] bcm63xx_enet: add support for bcm6368 internal ethernet
+ switch.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/boards/board_bcm963xx.c          |    4 +
+ arch/mips/bcm63xx/dev-enet.c                       |  113 ++-
+ .../include/asm/mach-bcm63xx/bcm63xx_dev_enet.h    |   28 +
+ arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h  |   50 +
+ .../mips/include/asm/mach-bcm63xx/board_bcm963xx.h |    2 +
+ drivers/net/ethernet/broadcom/bcm63xx_enet.c       | 1018 +++++++++++++++++++-
+ drivers/net/ethernet/broadcom/bcm63xx_enet.h       |   75 ++
+ 8 files changed, 1239 insertions(+), 66 deletions(-)
+
+--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
+@@ -924,6 +924,10 @@ int __init board_register_devices(void)
+           !bcm63xx_nvram_get_mac_address(board.enet1.mac_addr))
+               bcm63xx_enet_register(1, &board.enet1);
++      if (board.has_enetsw &&
++          !bcm63xx_nvram_get_mac_address(board.enetsw.mac_addr))
++              bcm63xx_enetsw_register(&board.enetsw);
++
+       if (board.has_usbd)
+               bcm63xx_usbd_register(&board.usbd);
+--- a/arch/mips/bcm63xx/dev-enet.c
++++ b/arch/mips/bcm63xx/dev-enet.c
+@@ -104,6 +104,64 @@ static struct platform_device bcm63xx_en
+       },
+ };
++static struct resource enetsw_res[] = {
++      {
++              /* start & end filled at runtime */
++              .flags          = IORESOURCE_MEM,
++      },
++      {
++              /* start filled at runtime */
++              .flags          = IORESOURCE_IRQ,
++      },
++      {
++              /* start filled at runtime */
++              .flags          = IORESOURCE_IRQ,
++      },
++};
++
++static struct bcm63xx_enetsw_platform_data enetsw_pd;
++
++static struct platform_device bcm63xx_enetsw_device = {
++      .name           = "bcm63xx_enetsw",
++      .num_resources  = ARRAY_SIZE(enetsw_res),
++      .resource       = enetsw_res,
++      .dev            = {
++              .platform_data = &enetsw_pd,
++      },
++};
++
++static int __init register_shared(void)
++{
++      int ret, chan_count;
++
++      if (shared_device_registered)
++              return 0;
++
++      shared_res[0].start = bcm63xx_regset_address(RSET_ENETDMA);
++      shared_res[0].end = shared_res[0].start;
++      shared_res[0].end += (RSET_ENETDMA_SIZE)  - 1;
++
++      if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368())
++              chan_count = 32;
++      else
++              chan_count = 16;
++
++      shared_res[1].start = bcm63xx_regset_address(RSET_ENETDMAC);
++      shared_res[1].end = shared_res[1].start;
++      shared_res[1].end += RSET_ENETDMAC_SIZE(chan_count)  - 1;
++
++      shared_res[2].start = bcm63xx_regset_address(RSET_ENETDMAS);
++      shared_res[2].end = shared_res[2].start;
++      shared_res[2].end += RSET_ENETDMAS_SIZE(chan_count)  - 1;
++
++      ret = platform_device_register(&bcm63xx_enet_shared_device);
++      if (ret)
++              return ret;
++      shared_device_registered = 1;
++
++      return 0;
++}
++
+ int __init bcm63xx_enet_register(int unit,
+                                const struct bcm63xx_enet_platform_data *pd)
+ {
+@@ -117,24 +175,9 @@ int __init bcm63xx_enet_register(int uni
+       if (unit == 1 && BCMCPU_IS_6338())
+               return -ENODEV;
+-      if (!shared_device_registered) {
+-              shared_res[0].start = bcm63xx_regset_address(RSET_ENETDMA);
+-              shared_res[0].end = shared_res[0].start;
+-              shared_res[0].end += (RSET_ENETDMA_SIZE)  - 1;
+-
+-              shared_res[1].start = bcm63xx_regset_address(RSET_ENETDMAC);
+-              shared_res[1].end = shared_res[1].start;
+-              shared_res[1].end += RSET_ENETDMAC_SIZE(16)  - 1;
+-
+-              shared_res[2].start = bcm63xx_regset_address(RSET_ENETDMAS);
+-              shared_res[2].end = shared_res[2].start;
+-              shared_res[2].end += RSET_ENETDMAS_SIZE(16)  - 1;
+-
+-              ret = platform_device_register(&bcm63xx_enet_shared_device);
+-              if (ret)
+-                      return ret;
+-              shared_device_registered = 1;
+-      }
++      ret = register_shared();
++      if (ret)
++              return ret;
+       if (unit == 0) {
+               enet0_res[0].start = bcm63xx_regset_address(RSET_ENET0);
+@@ -175,3 +218,37 @@ int __init bcm63xx_enet_register(int uni
+               return ret;
+       return 0;
+ }
++
++int __init
++bcm63xx_enetsw_register(const struct bcm63xx_enetsw_platform_data *pd)
++{
++      int ret;
++
++      if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368())
++              return -ENODEV;
++
++      ret = register_shared();
++      if (ret)
++              return ret;
++
++      enetsw_res[0].start = bcm63xx_regset_address(RSET_ENETSW);
++      enetsw_res[0].end = enetsw_res[0].start;
++      enetsw_res[0].end += RSET_ENETSW_SIZE - 1;
++      enetsw_res[1].start = bcm63xx_get_irq_number(IRQ_ENETSW_RXDMA0);
++      enetsw_res[2].start = bcm63xx_get_irq_number(IRQ_ENETSW_TXDMA0);
++      if (!enetsw_res[2].start)
++              enetsw_res[2].start = -1;
++
++      memcpy(bcm63xx_enetsw_device.dev.platform_data, pd, sizeof(*pd));
++
++      if (BCMCPU_IS_6328())
++              enetsw_pd.num_ports = ENETSW_PORTS_6328;
++      else if (BCMCPU_IS_6362() || BCMCPU_IS_6368())
++              enetsw_pd.num_ports = ENETSW_PORTS_6368;
++
++      ret = platform_device_register(&bcm63xx_enetsw_device);
++      if (ret)
++              return ret;
++
++      return 0;
++}
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
+@@ -39,7 +39,35 @@ struct bcm63xx_enet_platform_data {
+                                           int phy_id, int reg, int val));
+ };
++/*
++ * on board ethernet switch platform data
++ */
++#define ENETSW_MAX_PORT       8
++#define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */
++#define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */
++
++#define ENETSW_RGMII_PORT0    4
++
++struct bcm63xx_enetsw_port {
++      int             used;
++      int             phy_id;
++
++      int             bypass_link;
++      int             force_speed;
++      int             force_duplex_full;
++
++      const char      *name;
++};
++
++struct bcm63xx_enetsw_platform_data {
++      char mac_addr[ETH_ALEN];
++      int num_ports;
++      struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
++};
++
+ int __init bcm63xx_enet_register(int unit,
+                                const struct bcm63xx_enet_platform_data *pd);
++int bcm63xx_enetsw_register(const struct bcm63xx_enetsw_platform_data *pd);
++
+ #endif /* ! BCM63XX_DEV_ENET_H_ */
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+@@ -832,10 +832,60 @@
+  * _REG relative to RSET_ENETSW
+  *************************************************************************/
++/* Port traffic control */
++#define ENETSW_PTCTRL_REG(x)          (0x0 + (x))
++#define ENETSW_PTCTRL_RXDIS_MASK      (1 << 0)
++#define ENETSW_PTCTRL_TXDIS_MASK      (1 << 1)
++
++/* Switch mode register */
++#define ENETSW_SWMODE_REG             (0xb)
++#define ENETSW_SWMODE_FWD_EN_MASK     (1 << 1)
++
++/* IMP override Register */
++#define ENETSW_IMPOV_REG              (0xe)
++#define ENETSW_IMPOV_FORCE_MASK               (1 << 7)
++#define ENETSW_IMPOV_TXFLOW_MASK      (1 << 5)
++#define ENETSW_IMPOV_RXFLOW_MASK      (1 << 4)
++#define ENETSW_IMPOV_1000_MASK                (1 << 3)
++#define ENETSW_IMPOV_100_MASK         (1 << 2)
++#define ENETSW_IMPOV_FDX_MASK         (1 << 1)
++#define ENETSW_IMPOV_LINKUP_MASK      (1 << 0)
++
++/* Port override Register */
++#define ENETSW_PORTOV_REG(x)          (0x58 + (x))
++#define ENETSW_PORTOV_ENABLE_MASK     (1 << 6)
++#define ENETSW_PORTOV_TXFLOW_MASK     (1 << 5)
++#define ENETSW_PORTOV_RXFLOW_MASK     (1 << 4)
++#define ENETSW_PORTOV_1000_MASK               (1 << 3)
++#define ENETSW_PORTOV_100_MASK                (1 << 2)
++#define ENETSW_PORTOV_FDX_MASK                (1 << 1)
++#define ENETSW_PORTOV_LINKUP_MASK     (1 << 0)
++
++/* MDIO control register */
++#define ENETSW_MDIOC_REG              (0xb0)
++#define ENETSW_MDIOC_EXT_MASK         (1 << 16)
++#define ENETSW_MDIOC_REG_SHIFT                20
++#define ENETSW_MDIOC_PHYID_SHIFT      25
++#define ENETSW_MDIOC_RD_MASK          (1 << 30)
++#define ENETSW_MDIOC_WR_MASK          (1 << 31)
++
++/* MDIO data register */
++#define ENETSW_MDIOD_REG              (0xb4)
++
++/* Global Management Configuration Register */
++#define ENETSW_GMCR_REG                       (0x200)
++#define ENETSW_GMCR_RST_MIB_MASK      (1 << 0)
++
+ /* MIB register */
+ #define ENETSW_MIB_REG(x)             (0x2800 + (x) * 4)
+ #define ENETSW_MIB_REG_COUNT          47
++/* Jumbo control register port mask register */
++#define ENETSW_JMBCTL_PORT_REG                (0x4004)
++
++/* Jumbo control mib good frame register */
++#define ENETSW_JMBCTL_MAXSIZE_REG     (0x4008)
++
+ /*************************************************************************
+  * _REG relative to RSET_OHCI_PRIV
+--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
++++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
+@@ -25,6 +25,7 @@ struct board_info {
+       /* enabled feature/device */
+       unsigned int    has_enet0:1;
+       unsigned int    has_enet1:1;
++      unsigned int    has_enetsw:1;
+       unsigned int    has_pci:1;
+       unsigned int    has_pccard:1;
+       unsigned int    has_ohci0:1;
+@@ -37,6 +38,7 @@ struct board_info {
+       /* ethernet config */
+       struct bcm63xx_enet_platform_data enet0;
+       struct bcm63xx_enet_platform_data enet1;
++      struct bcm63xx_enetsw_platform_data enetsw;
+       /* USB config */
+       struct bcm63xx_usbd_platform_data usbd;
+--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+@@ -59,6 +59,49 @@ static inline void enet_writel(struct bc
+ }
+ /*
++ * io helpers to access switch registers
++ */
++static inline u32 enetsw_readl(struct bcm_enet_priv *priv, u32 off)
++{
++      /* printk("enetsw_readl at %p\n", priv->base + off); */
++      return bcm_readl(priv->base + off);
++}
++
++static inline void enetsw_writel(struct bcm_enet_priv *priv,
++                               u32 val, u32 off)
++{
++      /* printk("enetsw_writel %08x at %p\n", val, priv->base + off); */
++      bcm_writel(val, priv->base + off);
++}
++
++static inline u16 enetsw_readw(struct bcm_enet_priv *priv, u32 off)
++{
++      /* printk("enetsw_readw  at %p\n", priv->base + off); */
++      return bcm_readw(priv->base + off);
++}
++
++static inline void enetsw_writew(struct bcm_enet_priv *priv,
++                               u16 val, u32 off)
++{
++      /* printk("enetsw_writew %04x at %p\n", val, priv->base + off); */
++      bcm_writew(val, priv->base + off);
++}
++
++static inline u8 enetsw_readb(struct bcm_enet_priv *priv, u32 off)
++{
++      /* printk("enetsw_readb  at %p\n", priv->base + off); */
++      return bcm_readb(priv->base + off);
++}
++
++static inline void enetsw_writeb(struct bcm_enet_priv *priv,
++                               u8 val, u32 off)
++{
++      /* printk("enetsw_writeb %02x at %p\n", val, priv->base + off); */
++      bcm_writeb(val, priv->base + off);
++}
++
++
++/*
+  * io helpers to access shared registers
+  */
+ static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off)
+@@ -218,7 +261,6 @@ static int bcm_enet_refill_rx(struct net
+                       if (!skb)
+                               break;
+                       priv->rx_skb[desc_idx] = skb;
+-
+                       p = dma_map_single(&priv->pdev->dev, skb->data,
+                                          priv->rx_skb_size,
+                                          DMA_FROM_DEVICE);
+@@ -321,7 +363,8 @@ static int bcm_enet_receive_queue(struct
+               }
+               /* recycle packet if it's marked as bad */
+-              if (unlikely(len_stat & DMADESC_ERR_MASK)) {
++              if (!priv->enet_is_sw &&
++                  unlikely(len_stat & DMADESC_ERR_MASK)) {
+                       dev->stats.rx_errors++;
+                       if (len_stat & DMADESC_OVSIZE_MASK)
+@@ -552,6 +595,26 @@ static int bcm_enet_start_xmit(struct sk
+               goto out_unlock;
+       }
++      /* pad small packets sent on a switch device */
++      if (priv->enet_is_sw && skb->len < 64) {
++              int needed = 64 - skb->len;
++              char *data;
++
++              if (unlikely(skb_tailroom(skb) < needed)) {
++                      struct sk_buff *nskb;
++
++                      nskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC);
++                      if (!nskb) {
++                              ret = NETDEV_TX_BUSY;
++                              goto out_unlock;
++                      }
++                      dev_kfree_skb(skb);
++                      skb = nskb;
++              }
++              data = skb_put(skb, needed);
++              memset(data, 0, needed);
++      }
++
+       /* point to the next available desc */
+       desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
+       priv->tx_skb[priv->tx_curr_desc] = skb;
+@@ -929,9 +992,9 @@ static int bcm_enet_open(struct net_devi
+       enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
+       /* set dma maximum burst len */
+-      enet_dmac_writel(priv, BCMENET_DMA_MAXBURST,
++      enet_dmac_writel(priv, priv->dma_maxburst,
+                        ENETDMAC_MAXBURST_REG(priv->rx_chan));
+-      enet_dmac_writel(priv, BCMENET_DMA_MAXBURST,
++      enet_dmac_writel(priv, priv->dma_maxburst,
+                        ENETDMAC_MAXBURST_REG(priv->tx_chan));
+       /* set correct transmit fifo watermark */
+@@ -1528,7 +1591,7 @@ static int compute_hw_mtu(struct bcm_ene
+        * it's appended
+        */
+       priv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN,
+-                                BCMENET_DMA_MAXBURST * 4);
++                                priv->dma_maxburst * 4);
+       return 0;
+ }
+@@ -1635,6 +1698,9 @@ static int bcm_enet_probe(struct platfor
+               return -ENOMEM;
+       priv = netdev_priv(dev);
++      priv->enet_is_sw = false;
++      priv->dma_maxburst = BCMENET_DMA_MAXBURST;
++
+       ret = compute_hw_mtu(priv, dev->mtu);
+       if (ret)
+               goto out;
+@@ -1899,65 +1965,928 @@ struct platform_driver bcm63xx_enet_driv
+ };
+ /*
+- * reserve & remap memory space shared between all macs
++ * switch mii access callbacks
+  */
+-static int bcm_enet_shared_probe(struct platform_device *pdev)
++static int bcmenet_sw_mdio_read(struct bcm_enet_priv *priv,
++                              int ext, int phy_id, int location)
+ {
+-      struct resource *res;
+-      void __iomem *p[3];
+-      unsigned int i;
++      u32 reg;
++      int ret;
+-      memset(bcm_enet_shared_base, 0, sizeof(bcm_enet_shared_base));
++      spin_lock_bh(&priv->enetsw_mdio_lock);
++      enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
+-      for (i = 0; i < 3; i++) {
+-              res = platform_get_resource(pdev, IORESOURCE_MEM, i);
+-              if (!res)
+-                      return -EINVAL;
++      reg = ENETSW_MDIOC_RD_MASK |
++              (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
++              (location << ENETSW_MDIOC_REG_SHIFT);
++
++      if (ext)
++              reg |= ENETSW_MDIOC_EXT_MASK;
++
++      enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
++      udelay(50);
++      ret = enetsw_readw(priv, ENETSW_MDIOD_REG);
++      spin_unlock_bh(&priv->enetsw_mdio_lock);
++      return ret;
++}
+-              p[i] = devm_request_and_ioremap(&pdev->dev, res);
+-              if (!p[i])
+-                      return -ENOMEM;
++static void bcmenet_sw_mdio_write(struct bcm_enet_priv *priv,
++                               int ext, int phy_id, int location,
++                               uint16_t data)
++{
++      u32 reg;
+-              bcm_enet_shared_base[i] = p;
+-      }
++      spin_lock_bh(&priv->enetsw_mdio_lock);
++      enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
+-      memcpy(bcm_enet_shared_base, p, sizeof(bcm_enet_shared_base));
++      reg = ENETSW_MDIOC_WR_MASK |
++              (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
++              (location << ENETSW_MDIOC_REG_SHIFT);
+-      return 0;
+-}
++      if (ext)
++              reg |= ENETSW_MDIOC_EXT_MASK;
+-static int bcm_enet_shared_remove(struct platform_device *pdev)
+-{
+-      return 0;
++      reg |= data;
++
++      enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
++      udelay(50);
++      spin_unlock_bh(&priv->enetsw_mdio_lock);
+ }
+ /*
+- * this "shared" driver is needed because both macs share a single
+- * address space
++ * enet sw PHY polling
+  */
+-struct platform_driver bcm63xx_enet_shared_driver = {
+-      .probe  = bcm_enet_shared_probe,
+-      .remove = bcm_enet_shared_remove,
+-      .driver = {
+-              .name   = "bcm63xx_enet_shared",
+-              .owner  = THIS_MODULE,
+-      },
+-};
++static void swphy_poll_timer(unsigned long data)
++{
++      struct bcm_enet_priv *priv = (struct bcm_enet_priv *)data;
++      unsigned int i;
++
++      for (i = 0; i < priv->num_ports; i++) {
++              struct bcm63xx_enetsw_port *port;
++              int val, j, up, advertise, lpa, lpa2, speed, duplex, media;
++              int external_phy = bcm_enet_port_is_rgmii(i);
++              u8 override;
++
++              port = &priv->used_ports[i];
++              if (!port->used)
++                      continue;
++
++              if (port->bypass_link)
++                      continue;
++
++              /* dummy read to clear */
++              for (j = 0; j < 2; j++)
++                      val = bcmenet_sw_mdio_read(priv, external_phy,
++                                                 port->phy_id, MII_BMSR);
++
++              if (val == 0xffff)
++                      continue;
++
++              up = (val & BMSR_LSTATUS) ? 1 : 0;
++              if (!(up ^ priv->sw_port_link[i]))
++                      continue;
++
++              priv->sw_port_link[i] = up;
++
++              /* link changed */
++              if (!up) {
++                      dev_info(&priv->pdev->dev, "link DOWN on %s\n",
++                               port->name);
++                      enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
++                                    ENETSW_PORTOV_REG(i));
++                      enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
++                                    ENETSW_PTCTRL_TXDIS_MASK,
++                                    ENETSW_PTCTRL_REG(i));
++                      continue;
++              }
++
++              advertise = bcmenet_sw_mdio_read(priv, external_phy,
++                                               port->phy_id, MII_ADVERTISE);
++
++              lpa = bcmenet_sw_mdio_read(priv, external_phy, port->phy_id,
++                                         MII_LPA);
++
++              lpa2 = bcmenet_sw_mdio_read(priv, external_phy, port->phy_id,
++                                          MII_STAT1000);
++
++              /* figure out media and duplex from advertise and LPA values */
++              media = mii_nway_result(lpa & advertise);
++              duplex = (media & ADVERTISE_FULL) ? 1 : 0;
++              if (lpa2 & LPA_1000FULL)
++                      duplex = 1;
++
++              if (lpa2 & (LPA_1000FULL | LPA_1000HALF))
++                      speed = 1000;
++              else {
++                      if (media & (ADVERTISE_100FULL | ADVERTISE_100HALF))
++                              speed = 100;
++                      else
++                              speed = 10;
++              }
++
++              dev_info(&priv->pdev->dev,
++                       "link UP on %s, %dMbps, %s-duplex\n",
++                       port->name, speed, duplex ? "full" : "half");
++
++              override = ENETSW_PORTOV_ENABLE_MASK |
++                      ENETSW_PORTOV_LINKUP_MASK;
++
++              if (speed == 1000)
++                      override |= ENETSW_IMPOV_1000_MASK;
++              else if (speed == 100)
++                      override |= ENETSW_IMPOV_100_MASK;
++              if (duplex)
++                      override |= ENETSW_IMPOV_FDX_MASK;
++
++              enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
++              enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
++      }
++
++      priv->swphy_poll.expires = jiffies + HZ;
++      add_timer(&priv->swphy_poll);
++}
+ /*
+- * entry point
++ * open callback, allocate dma rings & buffers and start rx operation
+  */
+-static int __init bcm_enet_init(void)
++static int bcm_enetsw_open(struct net_device *dev)
+ {
+-      int ret;
++      struct bcm_enet_priv *priv;
++      struct device *kdev;
++      int i, ret;
++      unsigned int size;
++      void *p;
++      u32 val;
+-      ret = platform_driver_register(&bcm63xx_enet_shared_driver);
+-      if (ret)
+-              return ret;
++      priv = netdev_priv(dev);
++      kdev = &priv->pdev->dev;
+-      ret = platform_driver_register(&bcm63xx_enet_driver);
++      /* mask all interrupts and request them */
++      enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
++      enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
++
++      ret = request_irq(priv->irq_rx, bcm_enet_isr_dma,
++                        IRQF_DISABLED, dev->name, dev);
+       if (ret)
+-              platform_driver_unregister(&bcm63xx_enet_shared_driver);
++              goto out_freeirq;
++
++      if (priv->irq_tx != -1) {
++              ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
++                                IRQF_DISABLED, dev->name, dev);
++              if (ret)
++                      goto out_freeirq_rx;
++      }
++
++      /* allocate rx dma ring */
++      size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
++      p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
++      if (!p) {
++              dev_err(kdev, "cannot allocate rx ring %u\n", size);
++              ret = -ENOMEM;
++              goto out_freeirq_tx;
++      }
++
++      memset(p, 0, size);
++      priv->rx_desc_alloc_size = size;
++      priv->rx_desc_cpu = p;
++
++      /* allocate tx dma ring */
++      size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
++      p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
++      if (!p) {
++              dev_err(kdev, "cannot allocate tx ring\n");
++              ret = -ENOMEM;
++              goto out_free_rx_ring;
++      }
++
++      memset(p, 0, size);
++      priv->tx_desc_alloc_size = size;
++      priv->tx_desc_cpu = p;
++
++      priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size,
++                             GFP_KERNEL);
++      if (!priv->tx_skb) {
++              dev_err(kdev, "cannot allocate rx skb queue\n");
++              ret = -ENOMEM;
++              goto out_free_tx_ring;
++      }
++
++      priv->tx_desc_count = priv->tx_ring_size;
++      priv->tx_dirty_desc = 0;
++      priv->tx_curr_desc = 0;
++      spin_lock_init(&priv->tx_lock);
++
++      /* init & fill rx ring with skbs */
++      priv->rx_skb = kzalloc(sizeof(struct sk_buff *) * priv->rx_ring_size,
++                             GFP_KERNEL);
++      if (!priv->rx_skb) {
++              dev_err(kdev, "cannot allocate rx skb queue\n");
++              ret = -ENOMEM;
++              goto out_free_tx_skb;
++      }
++
++      priv->rx_desc_count = 0;
++      priv->rx_dirty_desc = 0;
++      priv->rx_curr_desc = 0;
++
++      /* disable all ports */
++      for (i = 0; i < priv->num_ports; i++) {
++              enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
++                            ENETSW_PORTOV_REG(i));
++              enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
++                            ENETSW_PTCTRL_TXDIS_MASK,
++                            ENETSW_PTCTRL_REG(i));
++
++              priv->sw_port_link[i] = 0;
++      }
++
++      /* reset mib */
++      val = enetsw_readb(priv, ENETSW_GMCR_REG);
++      val |= ENETSW_GMCR_RST_MIB_MASK;
++      enetsw_writeb(priv, val, ENETSW_GMCR_REG);
++      mdelay(1);
++      val &= ~ENETSW_GMCR_RST_MIB_MASK;
++      enetsw_writeb(priv, val, ENETSW_GMCR_REG);
++      mdelay(1);
++
++      /* force CPU port state */
++      val = enetsw_readb(priv, ENETSW_IMPOV_REG);
++      val |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK;
++      enetsw_writeb(priv, val, ENETSW_IMPOV_REG);
++
++      /* enable switch forward engine */
++      val = enetsw_readb(priv, ENETSW_SWMODE_REG);
++      val |= ENETSW_SWMODE_FWD_EN_MASK;
++      enetsw_writeb(priv, val, ENETSW_SWMODE_REG);
++
++      /* enable jumbo on all ports */
++      enetsw_writel(priv, 0x1ff, ENETSW_JMBCTL_PORT_REG);
++      enetsw_writew(priv, 9728, ENETSW_JMBCTL_MAXSIZE_REG);
++
++      /* initialize flow control buffer allocation */
++      enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
++                      ENETDMA_BUFALLOC_REG(priv->rx_chan));
++
++      if (bcm_enet_refill_rx(dev)) {
++              dev_err(kdev, "cannot allocate rx skb queue\n");
++              ret = -ENOMEM;
++              goto out;
++      }
++
++      /* write rx & tx ring addresses */
++      enet_dmas_writel(priv, priv->rx_desc_dma,
++                       ENETDMAS_RSTART_REG(priv->rx_chan));
++      enet_dmas_writel(priv, priv->tx_desc_dma,
++                       ENETDMAS_RSTART_REG(priv->tx_chan));
++
++      /* clear remaining state ram for rx & tx channel */
++      enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->rx_chan));
++      enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->tx_chan));
++      enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->rx_chan));
++      enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->tx_chan));
++      enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->rx_chan));
++      enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->tx_chan));
++
++      /* set dma maximum burst len */
++      enet_dmac_writel(priv, priv->dma_maxburst,
++                       ENETDMAC_MAXBURST_REG(priv->rx_chan));
++      enet_dmac_writel(priv, priv->dma_maxburst,
++                       ENETDMAC_MAXBURST_REG(priv->tx_chan));
++
++      /* set flow control low/high threshold to 1/3 / 2/3 */
++      val = priv->rx_ring_size / 3;
++      enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
++      val = (priv->rx_ring_size * 2) / 3;
++      enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
++
++      /* all set, enable mac and interrupts, start dma engine and
++       * kick rx dma channel */
++      wmb();
++      enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
++      enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
++                       ENETDMAC_CHANCFG_REG(priv->rx_chan));
++
++      /* watch "packet transferred" interrupt in rx and tx */
++      enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
++                       ENETDMAC_IR_REG(priv->rx_chan));
++      enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
++                       ENETDMAC_IR_REG(priv->tx_chan));
++
++      /* make sure we enable napi before rx interrupt  */
++      napi_enable(&priv->napi);
++
++      enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
++                       ENETDMAC_IRMASK_REG(priv->rx_chan));
++      enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
++                       ENETDMAC_IRMASK_REG(priv->tx_chan));
++
++      netif_carrier_on(dev);
++      netif_start_queue(dev);
++
++      /*
++       * apply override config for bypass_link ports here.
++       */
++      for (i = 0; i < priv->num_ports; i++) {
++              struct bcm63xx_enetsw_port *port;
++              u8 override;
++              port = &priv->used_ports[i];
++              if (!port->used)
++                      continue;
++
++              if (!port->bypass_link)
++                      continue;
++
++              override = ENETSW_PORTOV_ENABLE_MASK |
++                      ENETSW_PORTOV_LINKUP_MASK;
++
<