[package] Add uboot for xburst package
authorLars-Peter Clausen <lars@metafoo.de>
Mon, 12 Apr 2010 18:17:26 +0000 (18:17 +0000)
committerLars-Peter Clausen <lars@metafoo.de>
Mon, 12 Apr 2010 18:17:26 +0000 (18:17 +0000)
SVN-Revision: 20832

49 files changed:
package/uboot-xburst/Makefile [new file with mode: 0644]
package/uboot-xburst/files/board/n516/Makefile [new file with mode: 0644]
package/uboot-xburst/files/board/n516/config.mk [new file with mode: 0644]
package/uboot-xburst/files/board/n516/flash.c [new file with mode: 0644]
package/uboot-xburst/files/board/n516/n516.c [new file with mode: 0644]
package/uboot-xburst/files/board/n516/u-boot-nand.lds [new file with mode: 0644]
package/uboot-xburst/files/board/n516/u-boot.lds [new file with mode: 0644]
package/uboot-xburst/files/board/nanonote/Makefile [new file with mode: 0644]
package/uboot-xburst/files/board/nanonote/config.mk [new file with mode: 0644]
package/uboot-xburst/files/board/nanonote/nanonote.c [new file with mode: 0644]
package/uboot-xburst/files/board/nanonote/u-boot-nand.lds [new file with mode: 0644]
package/uboot-xburst/files/board/nanonote/u-boot.lds [new file with mode: 0644]
package/uboot-xburst/files/board/sakc/Makefile [new file with mode: 0644]
package/uboot-xburst/files/board/sakc/config.mk [new file with mode: 0644]
package/uboot-xburst/files/board/sakc/sakc.c [new file with mode: 0644]
package/uboot-xburst/files/board/sakc/u-boot-nand.lds [new file with mode: 0644]
package/uboot-xburst/files/board/sakc/u-boot.lds [new file with mode: 0644]
package/uboot-xburst/files/cpu/mips/jz4740.c [new file with mode: 0644]
package/uboot-xburst/files/cpu/mips/jz4740_nand.c [new file with mode: 0644]
package/uboot-xburst/files/cpu/mips/jz_lcd.c [new file with mode: 0644]
package/uboot-xburst/files/cpu/mips/jz_lcd.h [new file with mode: 0644]
package/uboot-xburst/files/cpu/mips/jz_mmc.c [new file with mode: 0644]
package/uboot-xburst/files/cpu/mips/jz_mmc.c.orig [new file with mode: 0644]
package/uboot-xburst/files/cpu/mips/jz_mmc.h [new file with mode: 0644]
package/uboot-xburst/files/cpu/mips/jz_serial.c [new file with mode: 0644]
package/uboot-xburst/files/cpu/mips/mmc_protocol.h [new file with mode: 0644]
package/uboot-xburst/files/cpu/mips/nanonote_gpm940b0.c [new file with mode: 0644]
package/uboot-xburst/files/cpu/mips/nanonote_gpm940b0.h [new file with mode: 0644]
package/uboot-xburst/files/cpu/mips/usb_boot.S [new file with mode: 0644]
package/uboot-xburst/files/include/asm-mips/jz4740.h [new file with mode: 0644]
package/uboot-xburst/files/include/configs/avt2.h [new file with mode: 0644]
package/uboot-xburst/files/include/configs/n516.h [new file with mode: 0644]
package/uboot-xburst/files/include/configs/nanonote.h [new file with mode: 0644]
package/uboot-xburst/files/include/configs/qi_lb60.h [new file with mode: 0644]
package/uboot-xburst/files/include/configs/sakc.h [new file with mode: 0644]
package/uboot-xburst/files/nand_spl/board/n516/Makefile [new file with mode: 0644]
package/uboot-xburst/files/nand_spl/board/n516/config.mk [new file with mode: 0644]
package/uboot-xburst/files/nand_spl/board/n516/u-boot.lds [new file with mode: 0644]
package/uboot-xburst/files/nand_spl/board/nanonote/Makefile [new file with mode: 0644]
package/uboot-xburst/files/nand_spl/board/nanonote/config.mk [new file with mode: 0644]
package/uboot-xburst/files/nand_spl/board/nanonote/u-boot.lds [new file with mode: 0644]
package/uboot-xburst/files/nand_spl/board/sakc/Makefile [new file with mode: 0644]
package/uboot-xburst/files/nand_spl/board/sakc/config.mk [new file with mode: 0644]
package/uboot-xburst/files/nand_spl/board/sakc/u-boot.lds [new file with mode: 0644]
package/uboot-xburst/files/nand_spl/nand_boot_jz4740.c [new file with mode: 0644]
package/uboot-xburst/patches/001-xburst.patch [new file with mode: 0644]
package/uboot-xburst/patches/005-i2c.patch [new file with mode: 0644]
package/uboot-xburst/patches/009-n516.patch [new file with mode: 0644]
package/uboot-xburst/patches/010-sakc.patch [new file with mode: 0644]

diff --git a/package/uboot-xburst/Makefile b/package/uboot-xburst/Makefile
new file mode 100644 (file)
index 0000000..b7820a7
--- /dev/null
@@ -0,0 +1,102 @@
+#
+# Copyright (C) 2008 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/kernel.mk
+
+PKG_NAME:=u-boot
+PKG_VERSION:=2009.11
+PKG_RELEASE:=1
+
+PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
+PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
+PKG_SOURCE_URL:=ftp://ftp.denx.de/pub/u-boot
+PKG_MD5SUM:=
+PKG_TARGETS:=bin
+
+include $(INCLUDE_DIR)/package.mk
+
+define uboot/Default
+  TITLE:=
+  CONFIG:=
+  IMAGE:=
+endef
+
+define uboot/qi_lb60
+  TITLE:=U-boot for the qi_lb60 board
+endef
+
+define uboot/avt2
+  TITLE:=U-boot for the avt2 board
+endef
+
+define uboot/sakc
+  TITLE:=U-boot for the sakc board
+endef
+
+define uboot/n516
+  TITLE:=U-boot for the N516 e-book reader
+  CONFIG:=n516_nand
+endef
+
+UBOOTS:=qi_lb60 n516 avt2 sakc
+
+define Package/uboot/template
+define Package/uboot-xburst-$(1)
+  SECTION:=boot
+  CATEGORY:=Boot Loaders
+  DEPENDS:=@TARGET_xburst
+  TITLE:=$(2)
+  URL:=http://www.denx.de/wiki/UBoot/WebHome
+  VARIANT:=$(1)
+endef
+endef
+
+define BuildUbootPackage
+       $(eval $(uboot/Default))
+       $(eval $(uboot/$(1)))
+       $(call Package/uboot/template,$(1),$(TITLE))
+endef
+
+
+ifdef BUILD_VARIANT
+$(eval $(call uboot/$(BUILD_VARIANT)))
+UBOOT_CONFIG:=$(if $(CONFIG),$(CONFIG),$(BUILD_VARIANT))
+UBOOT_IMAGE:=$(if $(IMAGE),$(IMAGE),openwrt-$(BOARD)-$(BUILD_BARIANT)-u-boot.bin)
+endif
+
+define Build/Prepare
+       $(call Build/Prepare/Default)
+       $(CP) ./files/* $(PKG_BUILD_DIR)
+       find $(PKG_BUILD_DIR) -name .svn | $(XARGS) rm -rf
+endef
+
+define Build/Configure
+       $(MAKE) -C $(PKG_BUILD_DIR) \
+               $(UBOOT_CONFIG)_config
+endef
+
+define Build/Compile
+       $(MAKE) -C $(PKG_BUILD_DIR) \
+               CROSS_COMPILE=$(TARGET_CROSS)
+endef
+
+define Package/uboot/install/template
+define Package/uboot-xburst-$(1)/install
+       $(INSTALL_DIR) $$(1)
+       $(CP) $(PKG_BUILD_DIR)/u-boot-nand.bin $(BIN_DIR)/$(2)
+endef
+endef
+
+$(foreach u,$(UBOOTS), \
+       $(eval $(call Package/uboot/install/template,$(u),openwrt-$(BOARD)-$(u)-u-boot.bin)) \
+)
+
+$(foreach u,$(UBOOTS), \
+       $(eval $(call BuildUbootPackage,$(u))) \
+       $(eval $(call BuildPackage,uboot-xburst-$(u))) \
+)
diff --git a/package/uboot-xburst/files/board/n516/Makefile b/package/uboot-xburst/files/board/n516/Makefile
new file mode 100644 (file)
index 0000000..da3bb4c
--- /dev/null
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2006
+# Ingenic Semiconductor, <jlwei@ingenic.cn>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).a
+
+COBJS  = $(BOARD).o flash.o
+
+OBJS   = $(addprefix $(obj),$(COBJS))
+SOBJS  = 
+
+$(LIB):        $(obj).depend $(OBJS) $(SOBJS)
+       $(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+$(obj).depend: Makefile $(SOBJS:.o=.S) $(COBJS:.o=.c)
+               $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(COBJS:.o=.c) > $@
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/package/uboot-xburst/files/board/n516/config.mk b/package/uboot-xburst/files/board/n516/config.mk
new file mode 100644 (file)
index 0000000..4bfe680
--- /dev/null
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2006
+# Ingenic Semiconductor, <jlwei@ingenic.cn>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Hanvon n516 e-book, MIPS32 core
+#
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+# ROM version
+TEXT_BASE = 0x88000000
+
+# RAM version
+#TEXT_BASE = 0x80100000
+endif
diff --git a/package/uboot-xburst/files/board/n516/flash.c b/package/uboot-xburst/files/board/n516/flash.c
new file mode 100644 (file)
index 0000000..fd5f815
--- /dev/null
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2006
+ * Ingenic Semiconductor, <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];   /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+       return (0);
+}
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+       printf ("flash_erase not implemented\n");
+       return 0;
+}
+
+void flash_print_info (flash_info_t * info)
+{
+       printf ("flash_print_info not implemented\n");
+}
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+       printf ("write_buff not implemented\n");
+       return (-1);
+}
diff --git a/package/uboot-xburst/files/board/n516/n516.c b/package/uboot-xburst/files/board/n516/n516.c
new file mode 100644 (file)
index 0000000..d788596
--- /dev/null
@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2006
+ * Ingenic Semiconductor, <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/mipsregs.h>
+#include <asm/jz4740.h>
+#include <asm/addrspace.h>
+#include <asm/cacheops.h>
+
+void _machine_restart(void)
+{
+       __wdt_select_extalclk();
+       __wdt_select_clk_div64();
+       __wdt_set_data(100);
+       __wdt_set_count(0);
+       __tcu_start_wdt_clock();
+       __wdt_start();
+       while(1);
+
+}
+
+static void gpio_init(void)
+{
+
+       REG_GPIO_PXPES(0) = 0xffffffff;
+       REG_GPIO_PXPES(1) = 0xffffffff;
+       REG_GPIO_PXPES(2) = 0xffffffff;
+       REG_GPIO_PXPES(3) = 0xffffffff;
+
+       /*
+        * Initialize NAND Flash Pins
+        */
+       __gpio_as_nand();
+
+       /*
+        * Initialize SDRAM pins
+        */
+       __gpio_as_sdram_32bit();
+
+       /*
+        * Initialize UART0 pins
+        */
+       __gpio_as_uart0();
+
+       /*
+        * Initialize MSC pins
+        */
+       __gpio_as_msc();
+
+       /*
+        * Initialize LCD pins
+        */
+       __gpio_as_lcd_16bit();
+
+       /*
+        * Initialize Other pins
+        */
+       __gpio_as_output(GPIO_SD_VCC_EN_N);
+       __gpio_clear_pin(GPIO_SD_VCC_EN_N);
+
+       __gpio_as_input(GPIO_SD_CD_N);
+       __gpio_disable_pull(GPIO_SD_CD_N);
+
+       __gpio_as_output(GPIO_DISP_OFF_N);
+
+       __gpio_as_output(GPIO_LED_EN);
+       __gpio_set_pin(GPIO_LED_EN);
+
+       __gpio_as_input(127);
+}
+
+static void cpm_init(void)
+{
+       __cpm_stop_ipu();
+       __cpm_stop_cim();
+       __cpm_stop_i2c();
+       __cpm_stop_ssi();
+       __cpm_stop_uart1();
+       __cpm_stop_sadc();
+       __cpm_stop_uhc();
+       __cpm_stop_udc();
+       __cpm_stop_aic1();
+       __cpm_stop_aic2();
+       __cpm_suspend_udcphy();
+       __cpm_suspend_usbphy();
+}
+
+//----------------------------------------------------------------------
+// board early init routine
+
+void board_early_init(void)
+{
+       gpio_init();
+       cpm_init();
+}
+
+//----------------------------------------------------------------------
+// U-Boot common routines
+
+int checkboard (void)
+{
+       DECLARE_GLOBAL_DATA_PTR;
+
+       printf("Board: Hanvon n516 e-book (CPU Speed %d MHz)\n",
+              gd->cpu_clk/1000000);
+
+       return 0; /* success */
+}
diff --git a/package/uboot-xburst/files/board/n516/u-boot-nand.lds b/package/uboot-xburst/files/board/n516/u-boot-nand.lds
new file mode 100644 (file)
index 0000000..a15a96e
--- /dev/null
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2006
+ * Ingenic Semiconductor, <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
+
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+       . = 0x00000000;
+
+       . = ALIGN(4);
+       .text       :
+       {
+         *(.text)
+       }
+
+       . = ALIGN(4);
+       .rodata  : { *(.rodata) }
+
+       . = ALIGN(4);
+       .data  : { *(.data) }
+
+       . = ALIGN(4);
+       .sdata  : { *(.sdata) }
+
+       _gp = ALIGN(16);
+
+       __got_start = .;
+       .got  : { *(.got) }
+       __got_end = .;
+
+       .sdata  : { *(.sdata) }
+
+       __u_boot_cmd_start = .;
+       .u_boot_cmd : { *(.u_boot_cmd) }
+       __u_boot_cmd_end = .;
+
+       uboot_end_data = .;
+       num_got_entries = (__got_end - __got_start) >> 2;
+
+       . = ALIGN(4);
+       .sbss  : { *(.sbss) }
+       .bss  : { *(.bss) }
+       uboot_end = .;
+}
diff --git a/package/uboot-xburst/files/board/n516/u-boot.lds b/package/uboot-xburst/files/board/n516/u-boot.lds
new file mode 100644 (file)
index 0000000..a15a96e
--- /dev/null
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2006
+ * Ingenic Semiconductor, <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
+
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+       . = 0x00000000;
+
+       . = ALIGN(4);
+       .text       :
+       {
+         *(.text)
+       }
+
+       . = ALIGN(4);
+       .rodata  : { *(.rodata) }
+
+       . = ALIGN(4);
+       .data  : { *(.data) }
+
+       . = ALIGN(4);
+       .sdata  : { *(.sdata) }
+
+       _gp = ALIGN(16);
+
+       __got_start = .;
+       .got  : { *(.got) }
+       __got_end = .;
+
+       .sdata  : { *(.sdata) }
+
+       __u_boot_cmd_start = .;
+       .u_boot_cmd : { *(.u_boot_cmd) }
+       __u_boot_cmd_end = .;
+
+       uboot_end_data = .;
+       num_got_entries = (__got_end - __got_start) >> 2;
+
+       . = ALIGN(4);
+       .sbss  : { *(.sbss) }
+       .bss  : { *(.bss) }
+       uboot_end = .;
+}
diff --git a/package/uboot-xburst/files/board/nanonote/Makefile b/package/uboot-xburst/files/board/nanonote/Makefile
new file mode 100644 (file)
index 0000000..2c726a7
--- /dev/null
@@ -0,0 +1,38 @@
+#
+# (C) Copyright 2006
+# Ingenic Semiconductor, <jlwei@ingenic.cn>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = lib$(BOARD).a
+
+OBJS   = $(BOARD).o
+SOBJS  =
+
+$(LIB):        .depend $(OBJS) $(SOBJS)
+       $(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend:       Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+               $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/package/uboot-xburst/files/board/nanonote/config.mk b/package/uboot-xburst/files/board/nanonote/config.mk
new file mode 100644 (file)
index 0000000..858e6a2
--- /dev/null
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2006 Qi Hardware, Inc.
+# Author: Xiangfu Liu <xiangfu.z@gmail.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Qi Hardware, Inc. Ben NanoNote (QI_LB60)
+#
+
+ifndef TEXT_BASE
+# ROM version
+# TEXT_BASE = 0x88000000
+
+# RAM version
+TEXT_BASE = 0x80100000
+endif
diff --git a/package/uboot-xburst/files/board/nanonote/nanonote.c b/package/uboot-xburst/files/board/nanonote/nanonote.c
new file mode 100644 (file)
index 0000000..7defab8
--- /dev/null
@@ -0,0 +1,123 @@
+/*
+ * Authors: Xiangfu Liu <xiangfu.z@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 3 of the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/mipsregs.h>
+#include <asm/jz4740.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void gpio_init(void)
+{
+       /*
+        * Initialize NAND Flash Pins
+        */
+       __gpio_as_nand();
+
+       /*
+        * Initialize SDRAM pins
+        */
+       __gpio_as_sdram_32bit();
+
+       /*
+        * Initialize LCD pins
+        */
+       __gpio_as_lcd_18bit();
+
+       /*
+        * Initialize MSC pins
+        */
+       __gpio_as_msc();
+
+       /*
+        * Initialize Other pins
+        */
+       unsigned int i;
+       for (i = 0; i < 7; i++){
+               __gpio_as_input(GPIO_KEYIN_BASE + i);
+               __gpio_enable_pull(GPIO_KEYIN_BASE + i);
+       }
+
+       for (i = 0; i < 8; i++) {
+               __gpio_as_output(GPIO_KEYOUT_BASE + i);
+               __gpio_clear_pin(GPIO_KEYOUT_BASE + i);
+       }
+
+       /*
+        * Initialize UART0 pins, in Ben NanoNote uart0 and keyin8 use the
+        * same gpio, init the gpio as uart0 cause a keyboard bug. so for
+        * end user we disable the uart0
+        */
+       if (__gpio_get_pin(GPIO_KEYIN_BASE + 2) == 0){
+               /* if pressed [S] */
+               printf("[S] pressed, enable UART0\n");
+               gd->boot_option = 5;
+               __gpio_as_uart0();
+       } else {
+               printf("[S] not pressed, disable UART0\n");
+               __gpio_as_input(GPIO_KEYIN_8);
+               __gpio_enable_pull(GPIO_KEYIN_8);
+       }
+
+       __gpio_as_output(GPIO_AUDIO_POP);
+       __gpio_set_pin(GPIO_AUDIO_POP);
+
+       __gpio_as_output(GPIO_LCD_CS);
+       __gpio_clear_pin(GPIO_LCD_CS);
+
+       __gpio_as_output(GPIO_AMP_EN);
+       __gpio_clear_pin(GPIO_AMP_EN);
+
+       __gpio_as_output(GPIO_SDPW_EN);
+       __gpio_disable_pull(GPIO_SDPW_EN);
+       __gpio_clear_pin(GPIO_SDPW_EN);
+
+       __gpio_as_input(GPIO_SD_DETECT);
+       __gpio_disable_pull(GPIO_SD_DETECT);
+
+       __gpio_as_input(GPIO_USB_DETECT);
+       __gpio_enable_pull(GPIO_USB_DETECT);
+
+       if (__gpio_get_pin(GPIO_KEYIN_BASE + 3) == 0) {
+               printf("[M] pressed, boot from sd card\n");
+               gd->boot_option = 1;
+       }
+}
+
+static void cpm_init(void)
+{
+       __cpm_stop_ipu();
+       __cpm_stop_cim();
+       __cpm_stop_i2c();
+       __cpm_stop_ssi();
+       __cpm_stop_uart1();
+       __cpm_stop_sadc();
+       __cpm_stop_uhc();
+       __cpm_stop_udc();
+       __cpm_stop_aic1();
+/*     __cpm_stop_aic2();*/
+}
+
+void board_early_init(void)
+{
+       gpio_init();
+       cpm_init();
+}
+
+/* U-Boot common routines */
+
+int checkboard (void)
+{
+
+       printf("Board: Qi LB60 (Ingenic XBurst Jz4740 SoC, Speed %d MHz)\n",
+              gd->cpu_clk/1000000);
+
+       return 0; /* success */
+}
diff --git a/package/uboot-xburst/files/board/nanonote/u-boot-nand.lds b/package/uboot-xburst/files/board/nanonote/u-boot-nand.lds
new file mode 100644 (file)
index 0000000..a15a96e
--- /dev/null
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2006
+ * Ingenic Semiconductor, <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
+
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+       . = 0x00000000;
+
+       . = ALIGN(4);
+       .text       :
+       {
+         *(.text)
+       }
+
+       . = ALIGN(4);
+       .rodata  : { *(.rodata) }
+
+       . = ALIGN(4);
+       .data  : { *(.data) }
+
+       . = ALIGN(4);
+       .sdata  : { *(.sdata) }
+
+       _gp = ALIGN(16);
+
+       __got_start = .;
+       .got  : { *(.got) }
+       __got_end = .;
+
+       .sdata  : { *(.sdata) }
+
+       __u_boot_cmd_start = .;
+       .u_boot_cmd : { *(.u_boot_cmd) }
+       __u_boot_cmd_end = .;
+
+       uboot_end_data = .;
+       num_got_entries = (__got_end - __got_start) >> 2;
+
+       . = ALIGN(4);
+       .sbss  : { *(.sbss) }
+       .bss  : { *(.bss) }
+       uboot_end = .;
+}
diff --git a/package/uboot-xburst/files/board/nanonote/u-boot.lds b/package/uboot-xburst/files/board/nanonote/u-boot.lds
new file mode 100644 (file)
index 0000000..a15a96e
--- /dev/null
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2006
+ * Ingenic Semiconductor, <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
+
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+       . = 0x00000000;
+
+       . = ALIGN(4);
+       .text       :
+       {
+         *(.text)
+       }
+
+       . = ALIGN(4);
+       .rodata  : { *(.rodata) }
+
+       . = ALIGN(4);
+       .data  : { *(.data) }
+
+       . = ALIGN(4);
+       .sdata  : { *(.sdata) }
+
+       _gp = ALIGN(16);
+
+       __got_start = .;
+       .got  : { *(.got) }
+       __got_end = .;
+
+       .sdata  : { *(.sdata) }
+
+       __u_boot_cmd_start = .;
+       .u_boot_cmd : { *(.u_boot_cmd) }
+       __u_boot_cmd_end = .;
+
+       uboot_end_data = .;
+       num_got_entries = (__got_end - __got_start) >> 2;
+
+       . = ALIGN(4);
+       .sbss  : { *(.sbss) }
+       .bss  : { *(.bss) }
+       uboot_end = .;
+}
diff --git a/package/uboot-xburst/files/board/sakc/Makefile b/package/uboot-xburst/files/board/sakc/Makefile
new file mode 100644 (file)
index 0000000..470447d
--- /dev/null
@@ -0,0 +1,38 @@
+#
+# (C) Copyright 2006
+# Ingenic Semiconductor, <jlwei@ingenic.cn>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = lib$(BOARD).a
+
+OBJS   = $(BOARD).o 
+SOBJS  = 
+
+$(LIB):        .depend $(OBJS) $(SOBJS)
+       $(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend:       Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+               $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/package/uboot-xburst/files/board/sakc/config.mk b/package/uboot-xburst/files/board/sakc/config.mk
new file mode 100644 (file)
index 0000000..b254958
--- /dev/null
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2006 Qi Hardware, Inc.
+# Author: Xiangfu Liu <xiangfu.z@gmail.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# SAKC Board
+#
+
+ifndef TEXT_BASE
+# ROM version
+# TEXT_BASE = 0x88000000
+
+# RAM version
+TEXT_BASE = 0x80100000
+endif
diff --git a/package/uboot-xburst/files/board/sakc/sakc.c b/package/uboot-xburst/files/board/sakc/sakc.c
new file mode 100644 (file)
index 0000000..85763c7
--- /dev/null
@@ -0,0 +1,94 @@
+/*
+ * Authors: Xiangfu Liu <xiangfu.z@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 3 of the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/mipsregs.h>
+#include <asm/jz4740.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void gpio_init(void)
+{
+       /*
+        * Initialize NAND Flash Pins
+        */
+       __gpio_as_nand();
+
+       /*
+        * Initialize SDRAM pins
+        */     
+       __gpio_as_sdram_16bit_4725();
+
+       /*
+        * Initialize UART0 pins
+        */
+       __gpio_as_uart0();
+
+       /*
+        * Initialize LCD pins
+        */
+       __gpio_as_lcd_18bit();
+
+       /*
+        * Initialize MSC pins
+        */
+       __gpio_as_msc();
+
+       /*
+        * Initialize SSI pins
+        */
+       __gpio_as_ssi();
+
+       /*
+        * Initialize I2C pins
+        */
+       __gpio_as_i2c();
+
+       /*
+        * Initialize MSC pins
+        */
+       __gpio_as_msc();
+
+       /*
+        * Initialize Other pins
+        */
+       __gpio_as_input(GPIO_SD_DETECT);
+       __gpio_disable_pull(GPIO_SD_DETECT);
+}
+/* TODO SAKC
+static void cpm_init(void)
+{
+       __cpm_stop_ipu();
+       __cpm_stop_cim();
+       __cpm_stop_i2c();
+       __cpm_stop_ssi();
+       __cpm_stop_uart1();
+       __cpm_stop_sadc();
+       __cpm_stop_uhc();
+       __cpm_stop_aic1();
+       __cpm_stop_aic2();
+}*/
+
+void board_early_init(void)
+{
+       gpio_init();
+       //cpm_init(); //TODO SAKC
+}
+
+/* U-Boot common routines */
+
+int checkboard (void)
+{
+
+       printf("Board: SAKC (Ingenic XBurst Jz4725 SoC, Speed %d MHz)\n",
+              gd->cpu_clk/1000000);
+
+       return 0; /* success */
+}
diff --git a/package/uboot-xburst/files/board/sakc/u-boot-nand.lds b/package/uboot-xburst/files/board/sakc/u-boot-nand.lds
new file mode 100644 (file)
index 0000000..a15a96e
--- /dev/null
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2006
+ * Ingenic Semiconductor, <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
+
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+       . = 0x00000000;
+
+       . = ALIGN(4);
+       .text       :
+       {
+         *(.text)
+       }
+
+       . = ALIGN(4);
+       .rodata  : { *(.rodata) }
+
+       . = ALIGN(4);
+       .data  : { *(.data) }
+
+       . = ALIGN(4);
+       .sdata  : { *(.sdata) }
+
+       _gp = ALIGN(16);
+
+       __got_start = .;
+       .got  : { *(.got) }
+       __got_end = .;
+
+       .sdata  : { *(.sdata) }
+
+       __u_boot_cmd_start = .;
+       .u_boot_cmd : { *(.u_boot_cmd) }
+       __u_boot_cmd_end = .;
+
+       uboot_end_data = .;
+       num_got_entries = (__got_end - __got_start) >> 2;
+
+       . = ALIGN(4);
+       .sbss  : { *(.sbss) }
+       .bss  : { *(.bss) }
+       uboot_end = .;
+}
diff --git a/package/uboot-xburst/files/board/sakc/u-boot.lds b/package/uboot-xburst/files/board/sakc/u-boot.lds
new file mode 100644 (file)
index 0000000..a15a96e
--- /dev/null
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2006
+ * Ingenic Semiconductor, <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
+
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+       . = 0x00000000;
+
+       . = ALIGN(4);
+       .text       :
+       {
+         *(.text)
+       }
+
+       . = ALIGN(4);
+       .rodata  : { *(.rodata) }
+
+       . = ALIGN(4);
+       .data  : { *(.data) }
+
+       . = ALIGN(4);
+       .sdata  : { *(.sdata) }
+
+       _gp = ALIGN(16);
+
+       __got_start = .;
+       .got  : { *(.got) }
+       __got_end = .;
+
+       .sdata  : { *(.sdata) }
+
+       __u_boot_cmd_start = .;
+       .u_boot_cmd : { *(.u_boot_cmd) }
+       __u_boot_cmd_end = .;
+
+       uboot_end_data = .;
+       num_got_entries = (__got_end - __got_start) >> 2;
+
+       . = ALIGN(4);
+       .sbss  : { *(.sbss) }
+       .bss  : { *(.bss) }
+       uboot_end = .;
+}
diff --git a/package/uboot-xburst/files/cpu/mips/jz4740.c b/package/uboot-xburst/files/cpu/mips/jz4740.c
new file mode 100644 (file)
index 0000000..5ae5797
--- /dev/null
@@ -0,0 +1,559 @@
+/*
+ * Jz4740 common routines
+ *
+ *  Copyright (c) 2006
+ *  Ingenic Semiconductor, <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+#ifdef CONFIG_JZ4740
+#include <common.h>
+#include <command.h>
+#include <asm/jz4740.h>
+
+extern void board_early_init(void);
+
+/* PLL output clock = EXTAL * NF / (NR * NO)
+ *
+ * NF = FD + 2, NR = RD + 2
+ * NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3)
+ */
+void pll_init(void)
+{
+       register unsigned int cfcr, plcr1;
+       int n2FR[33] = {
+               0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
+               7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
+               9
+       };
+       int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */
+       int nf, pllout2;
+
+       cfcr = CPM_CPCCR_CLKOEN |
+               CPM_CPCCR_PCS |
+               (n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
+               (n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
+               (n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
+               (n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
+               (n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
+
+       pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2);
+
+       /* Init USB Host clock, pllout2 must be n*48MHz */
+       REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
+
+       nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL;
+       plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
+               (0 << CPM_CPPCR_PLLN_BIT) |     /* RD=0, NR=2 */
+               (0 << CPM_CPPCR_PLLOD_BIT) |    /* OD=0, NO=1 */
+               (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
+               CPM_CPPCR_PLLEN;                /* enable PLL */
+
+       /* init PLL */
+       REG_CPM_CPCCR = cfcr;
+       REG_CPM_CPPCR = plcr1;
+}
+
+void pll_add_test(int new_freq)
+{
+       register unsigned int cfcr, plcr1;
+       int n2FR[33] = {
+               0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
+               7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
+               9
+       };
+       int div[5] = {1, 4, 4, 4, 4}; /* divisors of I:S:P:M:L */
+       int nf, pllout2;
+
+       cfcr = CPM_CPCCR_CLKOEN |
+               (n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
+               (n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
+               (n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
+               (n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
+               (n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
+
+       pllout2 = (cfcr & CPM_CPCCR_PCS) ? new_freq : (new_freq / 2);
+
+       /* Init UHC clock */
+       REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
+
+       /* nf = new_freq * 2 / CONFIG_SYS_EXTAL; */
+       nf = new_freq / 1000000; /* step length is 1M */
+       plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
+               (10 << CPM_CPPCR_PLLN_BIT) |    /* RD=0, NR=2 */
+               (0 << CPM_CPPCR_PLLOD_BIT) |    /* OD=0, NO=1 */
+               (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
+               CPM_CPPCR_PLLEN;                /* enable PLL */
+
+       /* init PLL */
+       REG_CPM_CPCCR = cfcr;
+       REG_CPM_CPPCR = plcr1;
+}
+
+void calc_clocks_add_test(void)
+{
+       DECLARE_GLOBAL_DATA_PTR;
+
+       unsigned int pllout;
+       unsigned int div[10] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
+
+       pllout = __cpm_get_pllout();
+
+       gd->cpu_clk = pllout / div[__cpm_get_cdiv()];
+       gd->sys_clk = pllout / div[__cpm_get_hdiv()];
+       gd->per_clk = pllout / div[__cpm_get_pdiv()];
+       gd->mem_clk = pllout / div[__cpm_get_mdiv()];
+       gd->dev_clk = CONFIG_SYS_EXTAL;
+}
+
+void sdram_add_test(int new_freq)
+{
+       register unsigned int dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
+
+       unsigned int cas_latency_sdmr[2] = {
+               EMC_SDMR_CAS_2,
+               EMC_SDMR_CAS_3,
+       };
+
+       unsigned int cas_latency_dmcr[2] = {
+               1 << EMC_DMCR_TCL_BIT,  /* CAS latency is 2 */
+               2 << EMC_DMCR_TCL_BIT   /* CAS latency is 3 */
+       };
+
+       int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
+
+       cpu_clk = new_freq;
+       mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
+
+       REG_EMC_RTCSR = EMC_RTCSR_CKS_DISABLE;
+       REG_EMC_RTCOR = 0;
+       REG_EMC_RTCNT = 0;
+
+       /* Basic DMCR register value. */
+       dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
+               ((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
+               (SDRAM_BANK4<<EMC_DMCR_BA_BIT) |
+               (SDRAM_BW16<<EMC_DMCR_BW_BIT) |
+               EMC_DMCR_EPIN |
+               cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
+
+       /* SDRAM timimg parameters */
+       ns = 1000000000 / mem_clk;
+
+#if 0
+       tmp = SDRAM_TRAS/ns;
+       if (tmp < 4) tmp = 4;
+       if (tmp > 11) tmp = 11;
+       dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT);
+
+       tmp = SDRAM_RCD/ns;
+       if (tmp > 3) tmp = 3;
+       dmcr |= (tmp << EMC_DMCR_RCD_BIT);
+
+       tmp = SDRAM_TPC/ns;
+       if (tmp > 7) tmp = 7;
+       dmcr |= (tmp << EMC_DMCR_TPC_BIT);
+
+       tmp = SDRAM_TRWL/ns;
+       if (tmp > 3) tmp = 3;
+       dmcr |= (tmp << EMC_DMCR_TRWL_BIT);
+
+       tmp = (SDRAM_TRAS + SDRAM_TPC)/ns;
+       if (tmp > 14) tmp = 14;
+       dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT);
+#else
+       dmcr |= 0xfffc;
+#endif
+
+       /* First, precharge phase */
+       REG_EMC_DMCR = dmcr;
+
+       /* Set refresh registers */
+       tmp = SDRAM_TREF/ns;
+       tmp = tmp/64 + 1;
+       if (tmp > 0xff) tmp = 0xff;
+
+       REG_EMC_RTCOR = tmp;
+       REG_EMC_RTCSR = EMC_RTCSR_CKS_64;       /* Divisor is 64, CKO/64 */
+
+       /* SDRAM mode values */
+       sdmode = EMC_SDMR_BT_SEQ | 
+                EMC_SDMR_OM_NORMAL |
+                EMC_SDMR_BL_4 | 
+                cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
+
+       /* precharge all chip-selects */
+       REG8(EMC_SDMR0|sdmode) = 0;
+
+       /* wait for precharge, > 200us */
+       tmp = (cpu_clk / 1000000) * 200;
+       while (tmp--);
+
+       /* enable refresh and set SDRAM mode */
+       REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
+
+       /* write sdram mode register for each chip-select */
+       REG8(EMC_SDMR0|sdmode) = 0;
+
+       /* everything is ok now */
+}
+
+void sdram_init(void)
+{
+       register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
+
+       unsigned int cas_latency_sdmr[2] = {
+               EMC_SDMR_CAS_2,
+               EMC_SDMR_CAS_3,
+       };
+
+       unsigned int cas_latency_dmcr[2] = {
+               1 << EMC_DMCR_TCL_BIT,  /* CAS latency is 2 */
+               2 << EMC_DMCR_TCL_BIT   /* CAS latency is 3 */
+       };
+
+       int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
+
+       cpu_clk = CONFIG_SYS_CPU_SPEED;
+       mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
+
+       REG_EMC_BCR = 0;        /* Disable bus release */
+       REG_EMC_RTCSR = 0;      /* Disable clock for counting */
+
+       /* Fault DMCR value for mode register setting*/
+#define SDRAM_ROW0    11
+#define SDRAM_COL0     8
+#define SDRAM_BANK40   0
+
+       dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) |
+               ((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) |
+               (SDRAM_BANK40<<EMC_DMCR_BA_BIT) |
+               (SDRAM_BW16<<EMC_DMCR_BW_BIT) |
+               EMC_DMCR_EPIN |
+               cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
+
+       /* Basic DMCR value */
+       dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
+               ((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
+               (SDRAM_BANK4<<EMC_DMCR_BA_BIT) |
+               (SDRAM_BW16<<EMC_DMCR_BW_BIT) |
+               EMC_DMCR_EPIN |
+               cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
+
+       /* SDRAM timimg */
+       ns = 1000000000 / mem_clk;
+       tmp = SDRAM_TRAS/ns;
+       if (tmp < 4) tmp = 4;
+       if (tmp > 11) tmp = 11;
+       dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT);
+       tmp = SDRAM_RCD/ns;
+       if (tmp > 3) tmp = 3;
+       dmcr |= (tmp << EMC_DMCR_RCD_BIT);
+       tmp = SDRAM_TPC/ns;
+       if (tmp > 7) tmp = 7;
+       dmcr |= (tmp << EMC_DMCR_TPC_BIT);
+       tmp = SDRAM_TRWL/ns;
+       if (tmp > 3) tmp = 3;
+       dmcr |= (tmp << EMC_DMCR_TRWL_BIT);
+       tmp = (SDRAM_TRAS + SDRAM_TPC)/ns;
+       if (tmp > 14) tmp = 14;
+       dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT);
+
+       /* SDRAM mode value */
+       sdmode = EMC_SDMR_BT_SEQ | 
+                EMC_SDMR_OM_NORMAL |
+                EMC_SDMR_BL_4 | 
+                cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
+
+       /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
+       REG_EMC_DMCR = dmcr;
+       REG8(EMC_SDMR0|sdmode) = 0;
+
+       /* Wait for precharge, > 200us */
+       tmp = (cpu_clk / 1000000) * 1000;
+       while (tmp--);
+
+       /* Stage 2. Enable auto-refresh */
+       REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH;
+
+       tmp = SDRAM_TREF/ns;
+       tmp = tmp/64 + 1;
+       if (tmp > 0xff) tmp = 0xff;
+       REG_EMC_RTCOR = tmp;
+       REG_EMC_RTCNT = 0;
+       REG_EMC_RTCSR = EMC_RTCSR_CKS_64;       /* Divisor is 64, CKO/64 */
+
+       /* Wait for number of auto-refresh cycles */
+       tmp = (cpu_clk / 1000000) * 1000;
+       while (tmp--);
+
+       /* Stage 3. Mode Register Set */
+       REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
+       REG8(EMC_SDMR0|sdmode) = 0;
+
+        /* Set back to basic DMCR value */
+       REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
+
+       /* everything is ok now */
+}
+
+#ifndef CONFIG_NAND_SPL
+
+static void calc_clocks(void)
+{
+       DECLARE_GLOBAL_DATA_PTR;
+
+       unsigned int pllout;
+       unsigned int div[10] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
+
+       pllout = __cpm_get_pllout();
+
+       gd->cpu_clk = pllout / div[__cpm_get_cdiv()];
+       gd->sys_clk = pllout / div[__cpm_get_hdiv()];
+       gd->per_clk = pllout / div[__cpm_get_pdiv()];
+       gd->mem_clk = pllout / div[__cpm_get_mdiv()];
+       gd->dev_clk = CONFIG_SYS_EXTAL;
+}
+
+static void rtc_init(void)
+{
+       unsigned long rtcsta;
+
+       while ( !__rtc_write_ready()) ;
+       __rtc_enable_alarm();   /* enable alarm */
+
+       while ( !__rtc_write_ready())
+               ;
+       REG_RTC_RGR   = 0x00007fff; /* type value */
+
+       while ( !__rtc_write_ready())
+               ;
+       REG_RTC_HWFCR = 0x0000ffe0; /* Power on delay 2s */
+
+       while ( !__rtc_write_ready())
+               ;
+       REG_RTC_HRCR  = 0x00000fe0; /* reset delay 125ms */
+#if 0
+       while ( !__rtc_write_ready())
+               ;
+       rtcsta = REG_RTC_HWRSR;
+       while ( !__rtc_write_ready())
+               ;
+       if (rtcsta & 0x33) {
+               if (rtcsta & 0x10) {
+                       while ( !__rtc_write_ready())
+                               ;
+                       REG_RTC_RSR = 0x0;
+               }
+               while ( !__rtc_write_ready())
+                       ;
+               REG_RTC_HWRSR = 0x0;
+       }
+#endif
+}
+
+/*
+ * jz4740 board init routine
+ */
+int jz_board_init(void)
+{
+       board_early_init();  /* init gpio, pll etc. */
+#ifndef CONFIG_NAND_U_BOOT
+       pll_init();          /* init PLL */
+       sdram_init();        /* init sdram memory */
+#endif
+       calc_clocks();       /* calc the clocks */
+       rtc_init();             /* init rtc on any reset: */
+       return 0;
+}
+
+/* U-Boot common routines */
+phys_size_t initdram(int board_type)
+{
+       u32 dmcr;
+       u32 rows, cols, dw, banks;
+       ulong size;
+
+       dmcr = REG_EMC_DMCR;
+       rows = 11 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT);
+       cols = 8 + ((dmcr & EMC_DMCR_CA_MASK) >> EMC_DMCR_CA_BIT);
+       dw = (dmcr & EMC_DMCR_BW) ? 2 : 4;
+       banks = (dmcr & EMC_DMCR_BA) ? 4 : 2;
+
+       size = (1 << (rows + cols)) * dw * banks;
+
+       return size;
+}
+
+/*
+ * Timer routines 
+ */
+
+#define TIMER_CHAN  0
+#define TIMER_FDATA 0xffff  /* Timer full data value */
+#define TIMER_HZ    CONFIG_SYS_HZ
+
+#define READ_TIMER  REG_TCU_TCNT(TIMER_CHAN)  /* macro to read the 16 bit timer */
+
+static ulong timestamp;
+static ulong lastdec;
+
+void   reset_timer_masked      (void);
+ulong  get_timer_masked        (void);
+void   udelay_masked           (unsigned long usec);
+
+/*
+ * timer without interrupts
+ */
+
+int timer_init(void)
+{
+       REG_TCU_TCSR(TIMER_CHAN) = TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN;
+       REG_TCU_TCNT(TIMER_CHAN) = 0;
+       REG_TCU_TDHR(TIMER_CHAN) = 0;
+       REG_TCU_TDFR(TIMER_CHAN) = TIMER_FDATA;
+
+       REG_TCU_TMSR = (1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)); /* mask irqs */
+       REG_TCU_TSCR = (1 << TIMER_CHAN); /* enable timer clock */
+       REG_TCU_TESR = (1 << TIMER_CHAN); /* start counting up */
+
+       lastdec = 0;
+       timestamp = 0;
+
+       return 0;
+}
+
+void reset_timer(void)
+{
+       reset_timer_masked ();
+}
+
+ulong get_timer(ulong base)
+{
+       return get_timer_masked () - base;
+}
+
+void set_timer(ulong t)
+{
+       timestamp = t;
+}
+
+void udelay (unsigned long usec)
+{
+       ulong tmo,tmp;
+
+       /* normalize */
+       if (usec >= 1000) {
+               tmo = usec / 1000;
+               tmo *= TIMER_HZ;
+               tmo /= 1000;
+       }
+       else {
+               if (usec >= 1) {
+                       tmo = usec * TIMER_HZ;
+                       tmo /= (1000*1000);
+               }
+               else
+                       tmo = 1;
+       }
+
+       /* check for rollover during this delay */
+       tmp = get_timer (0);
+       if ((tmp + tmo) < tmp )
+               reset_timer_masked();  /* timer would roll over */
+       else
+               tmo += tmp;
+
+       while (get_timer_masked () < tmo);
+}
+
+void reset_timer_masked (void)
+{
+       /* reset time */
+       lastdec = READ_TIMER;
+       timestamp = 0;
+}
+
+ulong get_timer_masked (void)
+{
+       ulong now = READ_TIMER;
+
+       if (lastdec <= now) {
+               /* normal mode */
+               timestamp += (now - lastdec);
+       } else {
+               /* we have an overflow ... */
+               timestamp += TIMER_FDATA + now - lastdec;
+       }
+       lastdec = now;
+
+       return timestamp;
+}
+
+void udelay_masked (unsigned long usec)
+{
+       ulong tmo;
+       ulong endtime;
+       signed long diff;
+
+       /* normalize */
+       if (usec >= 1000) {
+               tmo = usec / 1000;
+               tmo *= TIMER_HZ;
+               tmo /= 1000;
+       } else {
+               if (usec > 1) {
+                       tmo = usec * TIMER_HZ;
+                       tmo /= (1000*1000);
+               } else {
+                       tmo = 1;
+               }
+       }
+
+       endtime = get_timer_masked () + tmo;
+
+       do {
+               ulong now = get_timer_masked ();
+               diff = endtime - now;
+       } while (diff >= 0);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On MIPS it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+       return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On MIPS it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+       return TIMER_HZ;
+}
+
+#endif /* CONFIG_NAND_SPL */
+
+/* End of timer routine. */
+
+#endif
diff --git a/package/uboot-xburst/files/cpu/mips/jz4740_nand.c b/package/uboot-xburst/files/cpu/mips/jz4740_nand.c
new file mode 100644 (file)
index 0000000..7877194
--- /dev/null
@@ -0,0 +1,199 @@
+/*
+ * Platform independend driver for JZ4740.
+ *
+ * Copyright (c) 2007 Ingenic Semiconductor Inc.
+ * Author: <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+#include <common.h>
+
+#if defined(CONFIG_CMD_NAND) && defined(CONFIG_JZ4740)
+
+#include <nand.h>
+#include <asm/jz4740.h>
+#include <asm/io.h>
+
+#define PAR_SIZE 9
+#define __nand_ecc_enable()    (REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST )
+#define __nand_ecc_disable()   (REG_EMC_NFECR &= ~EMC_NFECR_ECCE)
+
+#define __nand_select_rs_ecc() (REG_EMC_NFECR |= EMC_NFECR_RS)
+
+#define __nand_rs_ecc_encoding()       (REG_EMC_NFECR |= EMC_NFECR_RS_ENCODING)
+#define __nand_rs_ecc_decoding()       (REG_EMC_NFECR |= EMC_NFECR_RS_DECODING)
+#define __nand_ecc_encode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_ENCF))
+#define __nand_ecc_decode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_DECF))
+
+static void jz_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+       struct nand_chip *this = mtd->priv;
+       unsigned long nandaddr = (unsigned long)this->IO_ADDR_W;
+
+       if (ctrl & NAND_CTRL_CHANGE) {
+               /* Change this to use I/O accessors. */
+               if (ctrl & NAND_NCE)
+                       REG_EMC_NFCSR |= EMC_NFCSR_NFCE1; 
+               else
+                       REG_EMC_NFCSR &= ~EMC_NFCSR_NFCE1;
+       }
+
+       if (cmd == NAND_CMD_NONE)
+               return;
+
+       if (ctrl & NAND_CLE)
+               nandaddr |= 0x00008000;
+       else /* must be ALE */
+               nandaddr |= 0x00010000;
+
+       writeb(cmd, (uint8_t *)nandaddr);
+}
+
+static int jz_device_ready(struct mtd_info *mtd)
+{
+       int ready;
+       udelay(20);     /* FIXME: add 20us delay */
+       ready = (REG_GPIO_PXPIN(2) & 0x40000000) ? 1 : 0;
+       return ready;
+}
+
+/*
+ * EMC setup
+ */
+static void jz_device_setup(void)
+{
+       /* Set NFE bit */
+       REG_EMC_NFCSR |= EMC_NFCSR_NFE1;
+       REG_EMC_SMCR1 = 0x094c4400;
+       /* REG_EMC_SMCR3 = 0x04444400; */
+}
+
+void board_nand_select_device(struct nand_chip *nand, int chip)
+{
+       /*
+        * Don't use "chip" to address the NAND device,
+        * generate the cs from the address where it is encoded.
+        */
+}
+
+static int jzsoc_nand_calculate_rs_ecc(struct mtd_info* mtd, const u_char* dat,
+                               u_char* ecc_code)
+{
+       volatile u8 *paraddr = (volatile u8 *)EMC_NFPAR0;
+       short i;
+
+       __nand_ecc_encode_sync()
+       __nand_ecc_disable();
+
+       for(i = 0; i < PAR_SIZE; i++)
+               ecc_code[i] = *paraddr++;
+
+       return 0;
+}
+
+static void jzsoc_nand_enable_rs_hwecc(struct mtd_info* mtd, int mode)
+{
+       __nand_ecc_enable();
+       __nand_select_rs_ecc();
+
+       REG_EMC_NFINTS = 0x0;
+       if (NAND_ECC_READ == mode){
+               __nand_rs_ecc_decoding();
+       }
+       if (NAND_ECC_WRITE == mode){
+               __nand_rs_ecc_encoding();
+       }
+}
+
+/* Correct 1~9-bit errors in 512-bytes data */
+static void jzsoc_rs_correct(unsigned char *dat, int idx, int mask)
+{
+       int i;
+
+       idx--;
+
+       i = idx + (idx >> 3);
+       if (i >= 512)
+               return;
+
+       mask <<= (idx & 0x7);
+
+       dat[i] ^= mask & 0xff;
+       if (i < 511)
+               dat[i+1] ^= (mask >> 8) & 0xff;
+}
+
+static int jzsoc_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
+                                u_char *read_ecc, u_char *calc_ecc)
+{
+       volatile u8 *paraddr = (volatile u8 *)EMC_NFPAR0;
+       short k;
+       u32 stat;
+       /* Set PAR values */
+
+       for (k = 0; k < PAR_SIZE; k++) {
+               *paraddr++ = read_ecc[k];
+       }
+
+       /* Set PRDY */
+       REG_EMC_NFECR |= EMC_NFECR_PRDY;
+
+       /* Wait for completion */
+       __nand_ecc_decode_sync();
+       __nand_ecc_disable();
+
+       /* Check decoding */
+       stat = REG_EMC_NFINTS;
+       if (stat & EMC_NFINTS_ERR) {
+               if (stat & EMC_NFINTS_UNCOR) {
+                       printk("Uncorrectable error occurred\n");
+                       return -1;
+               }
+               else {
+                       u32 errcnt = (stat & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT;
+                       switch (errcnt) {
+                       case 4:
+                               jzsoc_rs_correct(dat, (REG_EMC_NFERR3 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR3 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
+                       case 3:
+                               jzsoc_rs_correct(dat, (REG_EMC_NFERR2 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR2 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
+                       case 2:
+                               jzsoc_rs_correct(dat, (REG_EMC_NFERR1 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR1 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
+                       case 1:
+                               jzsoc_rs_correct(dat, (REG_EMC_NFERR0 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR0 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
+                               return 0;
+                       default:
+                               break;
+                       }
+               }
+       }
+       /* no error need to be correct */
+       return 0;
+}
+
+/*
+ * Main initialization routine
+ */
+int board_nand_init(struct nand_chip *nand)
+{
+       jz_device_setup();
+
+       nand->cmd_ctrl =  jz_hwcontrol;
+       nand->dev_ready = jz_device_ready;
+
+       /* FIXME: should use NAND_ECC_SOFT */
+       nand->ecc.hwctl = jzsoc_nand_enable_rs_hwecc;
+       nand->ecc.correct = jzsoc_nand_rs_correct_data;
+       nand->ecc.calculate = jzsoc_nand_calculate_rs_ecc;
+       nand->ecc.mode = NAND_ECC_HW;
+       nand->ecc.size = 512;
+       nand->ecc.bytes = 9;
+
+       /* 20 us command delay time */
+       nand->chip_delay = 20;
+
+       return 0;
+}
+#endif /* (CONFIG_SYS_CMD_NAND) */
diff --git a/package/uboot-xburst/files/cpu/mips/jz_lcd.c b/package/uboot-xburst/files/cpu/mips/jz_lcd.c
new file mode 100644 (file)
index 0000000..927b82a
--- /dev/null
@@ -0,0 +1,484 @@
+/*
+ * JzRISC lcd controller
+ *
+ * xiangfu liu <xiangfu.z@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Fallowing macro may be used:
+ *  CONFIG_LCD                        : LCD support
+ *  LCD_BPP                           : Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8
+ *  CONFIG_LCD_LOGO                   : show logo
+ */
+
+#include <config.h>
+#include <common.h>
+#include <lcd.h>
+
+#include <asm/io.h>               /* virt_to_phys() */
+
+#if defined(CONFIG_LCD) && !defined(CONFIG_SLCD)
+
+#if defined(CONFIG_JZ4740)
+#include <asm/jz4740.h>
+#endif
+
+#include "jz_lcd.h"
+
+
+struct jzfb_info {
+       unsigned int cfg;       /* panel mode and pin usage etc. */
+       unsigned int w;
+       unsigned int h;
+       unsigned int bpp;       /* bit per pixel */
+       unsigned int fclk;      /* frame clk */
+       unsigned int hsw;       /* hsync width, in pclk */
+       unsigned int vsw;       /* vsync width, in line count */
+       unsigned int elw;       /* end of line, in pclk */
+       unsigned int blw;       /* begin of line, in pclk */
+       unsigned int efw;       /* end of frame, in line count */
+       unsigned int bfw;       /* begin of frame, in line count */
+};
+
+static struct jzfb_info jzfb = {
+   #if defined(CONFIG_NANONOTE)
+       MODE_8BIT_SERIAL_TFT | PCLK_N | HSYNC_N | VSYNC_N,
+       320, 240, 32, 70, 1, 1, 273, 140, 1, 20
+   #endif
+
+};
+
+/************************************************************************/
+
+vidinfo_t panel_info = {
+#if defined(CONFIG_JZLCD_FOXCONN_PT035TN01)
+       320, 240, LCD_BPP,
+#endif
+};
+
+/*----------------------------------------------------------------------*/
+
+int lcd_line_length;
+
+int lcd_color_fg;
+int lcd_color_bg;
+
+/*
+ * Frame buffer memory information
+ */
+void *lcd_base;                        /* Start of framebuffer memory  */
+void *lcd_console_address;     /* Start of console buffer      */
+
+short console_col;
+short console_row;
+
+/*----------------------------------------------------------------------*/
+
+void lcd_ctrl_init (void *lcdbase);
+
+void lcd_enable (void);
+void lcd_disable (void);
+
+/*----------------------------------------------------------------------*/
+
+static int  jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid);
+static void jz_lcd_desc_init(vidinfo_t *vid);
+static int  jz_lcd_hw_init( vidinfo_t *vid );
+extern int flush_cache_all(void);
+
+#if LCD_BPP == LCD_COLOR8
+void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue);
+#endif
+#if LCD_BPP == LCD_MONOCHROME
+void lcd_initcolregs (void);
+#endif
+
+/*-----------------------------------------------------------------------*/
+
+void lcd_ctrl_init (void *lcdbase)
+{
+       __lcd_display_pin_init();
+
+       jz_lcd_init_mem(lcdbase, &panel_info);
+       jz_lcd_desc_init(&panel_info);
+       jz_lcd_hw_init(&panel_info);
+
+       __lcd_display_on() ;
+}
+
+/*----------------------------------------------------------------------*/
+#if LCD_BPP == LCD_COLOR8
+void
+lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
+{
+}
+#endif
+/*----------------------------------------------------------------------*/
+
+#if LCD_BPP == LCD_MONOCHROME
+static
+void lcd_initcolregs (void)
+{
+}
+#endif
+
+/*
+ * Before enabled lcd controller, lcd registers should be configured correctly.
+ */
+
+void lcd_enable (void)
+{
+       REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */
+       REG_LCD_CTRL |= 1<<3;    /* LCDCTRL.ENA*/
+}
+
+void lcd_disable (void)
+{
+       REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */
+       /* REG_LCD_CTRL |= (1<<3); */  /* LCDCTRL.DIS, quikly disable */
+}
+
+static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
+{
+       u_long palette_mem_size;
+       struct jz_fb_info *fbi = &vid->jz_fb;
+       int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
+
+       fbi->screen = (u_long)lcdbase;
+       fbi->palette_size = 256;
+       palette_mem_size = fbi->palette_size * sizeof(u16);
+
+       debug("jz_lcd.c palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
+       /* locate palette and descs at end of page following fb */
+       fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
+
+       return 0;
+}
+
+static void jz_lcd_desc_init(vidinfo_t *vid)
+{
+       struct jz_fb_info * fbi;
+       fbi = &vid->jz_fb;
+       fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
+       fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
+       fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
+
+       #define BYTES_PER_PANEL  (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8)
+
+       /* populate descriptors */
+       fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow);
+       fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + BYTES_PER_PANEL));
+       fbi->dmadesc_fblow->fidr  = 0;
+       fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL / 4 ;
+
+       fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */
+
+       fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen); 
+       fbi->dmadesc_fbhigh->fidr = 0;
+       fbi->dmadesc_fbhigh->ldcmd =  BYTES_PER_PANEL / 4; /* length in word */
+
+       fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette);
+       fbi->dmadesc_palette->fidr  = 0;
+       fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28);
+
+       if( NBITS(vid->vl_bpix) < 12)
+       {
+               /* assume any mode with <12 bpp is palette driven */
+               fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh);
+               fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette);
+               /* flips back and forth between pal and fbhigh */
+               fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette);
+       } else {
+               /* palette shouldn't be loaded in true-color mode */
+               fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh);
+               fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */
+       }
+
+       flush_cache_all();
+}
+
+static int  jz_lcd_hw_init(vidinfo_t *vid)
+{
+       struct jz_fb_info *fbi = &vid->jz_fb;
+       unsigned int val = 0;
+       unsigned int pclk;
+       unsigned int stnH;
+#if defined(CONFIG_MIPS_JZ4740)
+       int pll_div;
+#endif
+
+       /* Setting Control register */
+       switch (jzfb.bpp) {
+       case 1:
+               val |= LCD_CTRL_BPP_1;
+               break;
+       case 2:
+               val |= LCD_CTRL_BPP_2;
+               break;
+       case 4:
+               val |= LCD_CTRL_BPP_4;
+               break;
+       case 8:
+               val |= LCD_CTRL_BPP_8;
+               break;
+       case 15:
+               val |= LCD_CTRL_RGB555;
+       case 16:
+               val |= LCD_CTRL_BPP_16;
+               break;
+#if defined(CONFIG_MIPS_JZ4740)
+       case 17 ... 32:
+               val |= LCD_CTRL_BPP_18_24;      /* target is 4bytes/pixel */
+               break;
+#endif
+       default:
+               printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp);
+               val |= LCD_CTRL_BPP_16;
+               break;
+       }
+
+       switch (jzfb.cfg & MODE_MASK) {
+       case MODE_STN_MONO_DUAL:
+       case MODE_STN_COLOR_DUAL:
+       case MODE_STN_MONO_SINGLE:
+       case MODE_STN_COLOR_SINGLE:
+               switch (jzfb.bpp) {
+               case 1:
+                       /* val |= LCD_CTRL_PEDN; */
+               case 2:
+                       val |= LCD_CTRL_FRC_2;
+                       break;
+               case 4:
+                       val |= LCD_CTRL_FRC_4;
+                       break;
+               case 8:
+               default:
+                       val |= LCD_CTRL_FRC_16;
+                       break;
+               }
+               break;
+       }
+
+       val |= LCD_CTRL_BST_16;         /* Burst Length is 16WORD=64Byte */
+       val |= LCD_CTRL_OFUP;           /* OutFIFO underrun protect */
+
+       switch (jzfb.cfg & MODE_MASK) {
+       case MODE_STN_MONO_DUAL:
+       case MODE_STN_COLOR_DUAL:
+       case MODE_STN_MONO_SINGLE:
+       case MODE_STN_COLOR_SINGLE:
+               switch (jzfb.cfg & STN_DAT_PINMASK) {
+#define align2(n) (n)=((((n)+1)>>1)<<1)
+#define align4(n) (n)=((((n)+3)>>2)<<2)
+#define align8(n) (n)=((((n)+7)>>3)<<3)
+               case STN_DAT_PIN1:
+                       /* Do not adjust the hori-param value. */
+                       break;
+               case STN_DAT_PIN2:
+                       align2(jzfb.hsw);
+                       align2(jzfb.elw);
+                       align2(jzfb.blw);
+                       break;
+               case STN_DAT_PIN4:
+                       align4(jzfb.hsw);
+                       align4(jzfb.elw);
+                       align4(jzfb.blw);
+                       break;
+               case STN_DAT_PIN8:
+                       align8(jzfb.hsw);
+                       align8(jzfb.elw);
+                       align8(jzfb.blw);
+                       break;
+               }
+               break;
+       }
+
+       REG_LCD_CTRL = val;
+
+       switch (jzfb.cfg & MODE_MASK) {
+       case MODE_STN_MONO_DUAL:
+       case MODE_STN_COLOR_DUAL:
+       case MODE_STN_MONO_SINGLE:
+       case MODE_STN_COLOR_SINGLE:
+               if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) ||
+                   ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
+                       stnH = jzfb.h >> 1;
+               else
+                       stnH = jzfb.h;
+
+               REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
+               REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw);
+
+               /* Screen setting */
+               REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw);
+               REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w);
+               REG_LCD_DAV = (0 << 16) | (stnH);
+
+               /* AC BIAs signal */
+               REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw);
+
+               break;
+
+       case MODE_TFT_GEN:
+       case MODE_TFT_SHARP:
+       case MODE_TFT_CASIO:
+       case MODE_TFT_SAMSUNG:
+       case MODE_8BIT_SERIAL_TFT:
+       case MODE_TFT_18BIT:
+               REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
+               REG_LCD_HSYNC = (0 << 16) | jzfb.hsw;
+#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42)
+               REG_LCD_DAV = (0 << 16) | ( jzfb.h );
+#else
+               REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h);
+#endif /*#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42)*/
+               REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w );
+               REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \
+                       | (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw);
+               break;
+       }
+
+       switch (jzfb.cfg & MODE_MASK) {
+       case MODE_TFT_SAMSUNG:
+       {
+               unsigned int total, tp_s, tp_e, ckv_s, ckv_e;
+               unsigned int rev_s, rev_e, inv_s, inv_e;
+
+               pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
+                       (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
+
+               total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
+               tp_s = jzfb.blw + jzfb.w + 1;
+               tp_e = tp_s + 1;
+               /* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */
+               ckv_s = tp_s - pclk/(1000000000/4100);
+               ckv_e = tp_s + total;
+               rev_s = tp_s - 11;      /* -11.5 clk */
+               rev_e = rev_s + total;
+               inv_s = tp_s;
+               inv_e = inv_s + total;
+               REG_LCD_CLS = (tp_s << 16) | tp_e;
+               REG_LCD_PS = (ckv_s << 16) | ckv_e;
+               REG_LCD_SPL = (rev_s << 16) | rev_e;
+               REG_LCD_REV = (inv_s << 16) | inv_e;
+               jzfb.cfg |= STFT_REVHI | STFT_SPLHI;
+               break;
+       }
+       case MODE_TFT_SHARP:
+       {
+               unsigned int total, cls_s, cls_e, ps_s, ps_e;
+               unsigned int spl_s, spl_e, rev_s, rev_e;
+               total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
+#if !defined(CONFIG_JZLCD_INNOLUX_AT080TN42)
+               spl_s = 1;
+               spl_e = spl_s + 1;
+               cls_s = 0;
+               cls_e = total - 60;     /* > 4us (pclk = 80ns) */
+               ps_s = cls_s;
+               ps_e = cls_e;
+               rev_s = total - 40;     /* > 3us (pclk = 80ns) */
+               rev_e = rev_s + total;
+               jzfb.cfg |= STFT_PSHI; 
+#else           /*#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42)*/
+               spl_s = total - 5; /* LD */
+               spl_e = total -3;
+               cls_s = 32;     /* CKV */
+               cls_e = 145;
+               ps_s  = 0;      /* OEV */
+               ps_e  = 45;
+               rev_s = 0;      /* POL */
+               rev_e = 0;
+#endif          /*#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42)*/
+               REG_LCD_SPL = (spl_s << 16) | spl_e;
+               REG_LCD_CLS = (cls_s << 16) | cls_e;
+               REG_LCD_PS = (ps_s << 16) | ps_e;
+               REG_LCD_REV = (rev_s << 16) | rev_e;
+               break;
+       }
+       case MODE_TFT_CASIO:
+               break;
+       }
+
+       /* Configure the LCD panel */
+       REG_LCD_CFG = jzfb.cfg;
+
+       /* Timing setting */
+       __cpm_stop_lcd();
+
+       val = jzfb.fclk; /* frame clk */
+       if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) {
+               pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
+                       (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
+       }
+       else {
+               /* serial mode: Hsync period = 3*Width_Pixel */
+               pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) *
+                       (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
+       }
+
+       if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
+           ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
+               pclk = (pclk * 3);
+
+       if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
+           ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
+           ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) ||
+           ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
+               pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4);
+
+       if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
+           ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
+               pclk >>= 1;
+
+       pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */
+       pll_div = pll_div ? 1 : 2 ;
+       val = ( __cpm_get_pllout()/pll_div ) / pclk;
+       val--;
+       if ( val > 0x1ff ) {
+               printf("CPM_LPCDR too large, set it to 0x1ff\n");
+               val = 0x1ff;
+       }
+       __cpm_set_pixdiv(val);
+
+       val = pclk * 3 ;        /* LCDClock > 2.5*Pixclock */
+       if ( val > 150000000 ) {
+               printf("Warning: LCDClock=%d\n, LCDClock must less or equal to 150MHz.\n", val);
+               printf("Change LCDClock to 150MHz\n");
+               val = 150000000;
+       }
+       val = ( __cpm_get_pllout()/pll_div ) / val;
+       val--;
+       if ( val > 0x1f ) {
+               printf("CPM_CPCCR.LDIV too large, set it to 0x1f\n");
+               val = 0x1f;
+       }
+       __cpm_set_ldiv( val );
+       REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */
+
+       __cpm_start_lcd();
+       udelay(1000);
+
+       REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/
+
+       if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
+           ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
+               REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/
+
+       return 0;
+}
+
diff --git a/package/uboot-xburst/files/cpu/mips/jz_lcd.h b/package/uboot-xburst/files/cpu/mips/jz_lcd.h
new file mode 100644 (file)
index 0000000..dfd63e0
--- /dev/null
@@ -0,0 +1,260 @@
+/*
+ * JzRISC lcd controller
+ *
+ * xiangfu liu <xiangfu.z@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __JZLCD_H__
+#define __JZLCD_H__
+
+#include <asm/io.h>
+/*
+ * change u-boot macro to celinux macro
+ */
+/* Chip type */
+#if defined(CONFIG_JZ4740)
+#define CONFIG_MIPS_JZ4740             1
+#endif
+
+/* board type */
+#if defined(CONFIG_NANONOTE)
+#define CONFIG_MIPS_JZ4740_PI          1
+#endif
+
+#define mdelay(n)              udelay((n)*1000)
+
+/*
+ * change u-boot macro to celinux macro
+ */
+
+#define NR_PALETTE     256
+
+struct lcd_desc{
+       unsigned int next_desc; /* LCDDAx */
+       unsigned int databuf;   /* LCDSAx */
+       unsigned int frame_id;  /* LCDFIDx */
+       unsigned int cmd;       /* LCDCMDx */
+};
+
+#define MODE_MASK              0x0f
+#define MODE_TFT_GEN           0x00
+#define MODE_TFT_SHARP         0x01
+#define MODE_TFT_CASIO         0x02
+#define MODE_TFT_SAMSUNG       0x03
+#define MODE_CCIR656_NONINT    0x04
+#define MODE_CCIR656_INT       0x05
+#define MODE_STN_COLOR_SINGLE  0x08
+#define MODE_STN_MONO_SINGLE   0x09
+#define MODE_STN_COLOR_DUAL    0x0a
+#define MODE_STN_MONO_DUAL     0x0b
+#define MODE_8BIT_SERIAL_TFT    0x0c
+
+#define MODE_TFT_18BIT          (1<<7)
+
+#define STN_DAT_PIN1   (0x00 << 4)
+#define STN_DAT_PIN2   (0x01 << 4)
+#define STN_DAT_PIN4   (0x02 << 4)
+#define STN_DAT_PIN8   (0x03 << 4)
+#define STN_DAT_PINMASK        STN_DAT_PIN8
+
+#define STFT_PSHI      (1 << 15)
+#define STFT_CLSHI     (1 << 14)
+#define STFT_SPLHI     (1 << 13)
+#define STFT_REVHI     (1 << 12)
+
+#define SYNC_MASTER    (0 << 16)
+#define SYNC_SLAVE     (1 << 16)
+
+#define DE_P           (0 << 9)
+#define DE_N           (1 << 9)
+
+#define PCLK_P         (0 << 10)
+#define PCLK_N         (1 << 10)
+
+#define HSYNC_P                (0 << 11)
+#define HSYNC_N                (1 << 11)
+
+#define VSYNC_P                (0 << 8)
+#define VSYNC_N                (1 << 8)
+
+#define DATA_NORMAL    (0 << 17)
+#define DATA_INVERSE   (1 << 17)
+
+
+/* Jz LCDFB supported I/O controls. */
+#define FBIOSETBACKLIGHT       0x4688
+#define FBIODISPON             0x4689
+#define FBIODISPOFF            0x468a
+#define FBIORESET              0x468b
+#define FBIOPRINT_REG          0x468c
+
+/*
+ * LCD panel specific definition
+ */
+
+#if defined(CONFIG_JZLCD_FOXCONN_PT035TN01) || defined(CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL)
+
+#if defined(CONFIG_JZLCD_FOXCONN_PT035TN01) /* board pmp */
+#define MODE 0xcd              /* 24bit parellel RGB */
+#endif
+#if defined(CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL)
+#define MODE 0xc9              /* 8bit serial RGB */
+#endif
+
+#if defined(CONFIG_MIPS_JZ4740_PI) /* board pavo */
+       #define SPEN    (32*2+21)       /*LCD_SPL */
+       #define SPCK    (32*2+23)       /*LCD_CLS */
+       #define SPDA    (32*2+22)       /*LCD_D12 */
+       #define LCD_RET (32*3+27) 
+#else
+#error "cpu/misp/Jzlcd.h, please define SPI pins on your board."
+#endif
+
+       #define __spi_write_reg1(reg, val) \
+       do { \
+               unsigned char no;\
+               unsigned short value;\
+               unsigned char a=0;\
+               unsigned char b=0;\
+               a=reg;\
+               b=val;\
+               __gpio_set_pin(SPEN);\
+               __gpio_set_pin(SPCK);\
+               __gpio_clear_pin(SPDA);\
+               __gpio_clear_pin(SPEN);\
+               udelay(25);\
+               value=((a<<8)|(b&0xFF));\
+               for(no=0;no<16;no++)\
+               {\
+                       __gpio_clear_pin(SPCK);\
+                       if((value&0x8000)==0x8000)\
+                       __gpio_set_pin(SPDA);\
+                       else\
+                       __gpio_clear_pin(SPDA);\
+                       udelay(25);\
+                       __gpio_set_pin(SPCK);\
+                       value=(value<<1); \
+                       udelay(25);\
+                }\
+               __gpio_set_pin(SPEN);\
+               udelay(100);\
+       } while (0)
+
+       #define __spi_write_reg(reg, val) \
+       do {\
+               __spi_write_reg1((reg<<2|2), val);\
+               udelay(100); \
+       }while(0)
+
+       
+       #define __lcd_special_pin_init() \
+       do { \
+               __gpio_as_output(SPEN); /* use SPDA */\
+               __gpio_as_output(SPCK); /* use SPCK */\
+               __gpio_as_output(SPDA); /* use SPDA */\
+               __gpio_as_output(LCD_RET);\
+       } while (0)
+
+#if defined(CONFIG_NANONOTE)
+       #define __lcd_special_on() \
+               do { \
+               udelay(50);\
+               __spi_write_reg1(0x05, 0x16); \
+               __spi_write_reg1(0x04, 0x0b); \
+               __spi_write_reg1(0x07, 0x8d); \
+               __spi_write_reg1(0x01, 0x95); \
+               __spi_write_reg1(0x08, 0xc0); \
+               __spi_write_reg1(0x03, 0x40); \
+               __spi_write_reg1(0x06, 0x15); \
+               __spi_write_reg1(0x05, 0xd7); \
+               } while (0)     /* reg 0x0a is control the display direction:DB0->horizontal level DB1->vertical level */
+
+       #define __lcd_special_off()                             \
+                         do {                                  \
+                                 __spi_write_reg1(0x05, 0x5e); \
+                         } while (0)
+#endif /* CONFIG_NANONOTE */
+#endif /* CONFIG_JZLCD_FOXCONN_PT035TN01 or CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL */
+
+#ifndef __lcd_special_pin_init
+#define __lcd_special_pin_init()
+#endif
+#ifndef __lcd_special_on
+#define __lcd_special_on()
+#endif
+#ifndef __lcd_special_off
+#define __lcd_special_off()
+#endif
+
+
+/*
+ * Platform specific definition
+ */
+
+#if defined(CONFIG_MIPS_JZ4740_PI)
+
+       /* 100 level: 0,1,...,100 */
+       #define __lcd_set_backlight_level(n)\
+       do { \
+       __gpio_as_output(32*3+27); \
+       __gpio_set_pin(32*3+27); \
+       } while (0)
+
+       #define __lcd_close_backlight() \
+       do { \
+       __gpio_as_output(GPIO_PWM); \
+       __gpio_clear_pin(GPIO_PWM); \
+       } while (0)
+
+       #define __lcd_display_pin_init() \
+       do { \
+               __gpio_as_output(GPIO_DISP_OFF_N); \
+               __cpm_start_tcu(); \
+               __lcd_special_pin_init(); \
+       } while (0)
+       /*      __lcd_set_backlight_level(100); \*/
+       #define __lcd_display_on() \
+       do { \
+               __gpio_set_pin(GPIO_DISP_OFF_N); \
+               __lcd_special_on(); \
+       } while (0)
+
+       #define __lcd_display_off() \
+       do { \
+               __lcd_special_off(); \
+               __gpio_clear_pin(GPIO_DISP_OFF_N); \
+       } while (0)
+
+#endif /* CONFIG_MIPS_JZ4740_PI) */
+
+/*****************************************************************************
+ * LCD display pin dummy macros
+ *****************************************************************************/
+#ifndef __lcd_display_pin_init
+#define __lcd_display_pin_init()
+#endif
+#ifndef __lcd_display_on
+#define __lcd_display_on()
+#endif
+#ifndef __lcd_display_off
+#define __lcd_display_off()
+#endif
+#ifndef __lcd_set_backlight_level
+#define __lcd_set_backlight_level(n)
+#endif
+
diff --git a/package/uboot-xburst/files/cpu/mips/jz_mmc.c b/package/uboot-xburst/files/cpu/mips/jz_mmc.c
new file mode 100644 (file)
index 0000000..b3c4e99
--- /dev/null
@@ -0,0 +1,1416 @@
+/*
+ * (C) Copyright 2003
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <part.h>
+
+#if defined CONFIG_JZ4740
+#include <asm-mips/jz4740.h>
+
+#include "jz_mmc.h"
+
+#define CFG_MMC_BASE           0x80600000
+static int sd2_0 = 0;
+
+/*
+ * GPIO definition
+ */
+#if defined(CONFIG_SAKC)
+
+#define __msc_init_io()                                \
+do {                                           \
+       __gpio_as_input(GPIO_SD_CD_N);          \
+} while (0)
+
+#else
+#define __msc_init_io()                                \
+do {                                           \
+       __gpio_as_output(GPIO_SD_VCC_EN_N);     \
+       __gpio_as_input(GPIO_SD_CD_N);          \
+} while (0)
+
+#define __msc_enable_power()                   \
+do {                                           \
+       __gpio_clear_pin(GPIO_SD_VCC_EN_N);     \
+} while (0)
+
+#define __msc_disable_power()                  \
+do {                                           \
+       __gpio_set_pin(GPIO_SD_VCC_EN_N);       \
+} while (0)
+       
+#endif /* CONFIG_SAKE */
+
+#define __msc_card_detected()                  \
+({                                             \
+       int detected = 1;                       \
+       __gpio_as_input(GPIO_SD_CD_N);          \
+       __gpio_disable_pull(GPIO_SD_CD_N);      \
+       if (!__gpio_get_pin(GPIO_SD_CD_N))      \
+               detected = 0;                   \
+       detected;                               \
+})
+
+/*
+ * Local functions
+ */
+
+#ifdef CONFIG_MMC
+extern int
+fat_register_device(block_dev_desc_t *dev_desc, int part_no);
+
+static block_dev_desc_t mmc_dev;
+
+block_dev_desc_t * mmc_get_dev(int dev)
+{
+       return ((block_dev_desc_t *)&mmc_dev);
+}
+
+/*
+ * FIXME needs to read cid and csd info to determine block size
+ * and other parameters
+ */
+static uchar mmc_buf[MMC_BLOCK_SIZE];
+static int mmc_ready = 0;
+static mmc_csd_t mmc_csd;
+static int use_4bit;                    /* Use 4-bit data bus */
+/*
+ *  MMC Events
+ */
+#define MMC_EVENT_NONE         0x00    /* No events */
+#define MMC_EVENT_RX_DATA_DONE 0x01    /* Rx data done */
+#define MMC_EVENT_TX_DATA_DONE 0x02    /* Tx data done */
+#define MMC_EVENT_PROG_DONE    0x04    /* Programming is done */
+
+
+#define MMC_IRQ_MASK()                         \
+do {                                           \
+       REG_MSC_IMASK = 0xffff;                 \
+       REG_MSC_IREG = 0xffff;                  \
+} while (0)
+
+/* Stop the MMC clock and wait while it happens */
+static inline int jz_mmc_stop_clock(void)
+{
+       int timeout = 1000;
+
+       REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP;
+
+       while (timeout && (REG_MSC_STAT & MSC_STAT_CLK_EN)) {
+               timeout--;
+               if (timeout == 0) {
+                       return MMC_ERROR_TIMEOUT;
+               }
+               udelay(1);
+       }
+        return MMC_NO_ERROR;
+}
+
+/* Start the MMC clock and operation */
+static inline int jz_mmc_start_clock(void)
+{
+       REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START | MSC_STRPCL_START_OP;
+       return MMC_NO_ERROR;
+}
+
+static inline u32 jz_mmc_calc_clkrt(int is_sd, u32 rate)
+{
+       u32 clkrt;
+       u32 clk_src = is_sd ? 24000000: 16000000;
+
+       clkrt = 0;
+       while (rate < clk_src)
+       {
+               clkrt ++;
+               clk_src >>= 1;
+       }
+       return clkrt;
+}
+
+/* Set the MMC clock frequency */
+void jz_mmc_set_clock(int sd, u32 rate)
+{
+       jz_mmc_stop_clock();
+
+       /* Select clock source of MSC */
+       __cpm_select_msc_clk(sd);
+
+       /* Set clock dividor of MSC */
+       REG_MSC_CLKRT = jz_mmc_calc_clkrt(sd, rate);
+}
+
+static int jz_mmc_check_status(struct mmc_request *request)
+{
+       u32 status = REG_MSC_STAT;
+
+       /* Checking for response or data timeout */
+       if (status & (MSC_STAT_TIME_OUT_RES | MSC_STAT_TIME_OUT_READ)) {
+               printf("MMC/SD timeout, MMC_STAT 0x%x CMD %d\n", status, request->cmd);
+               return MMC_ERROR_TIMEOUT;
+       }
+
+       /* Checking for CRC error */
+       if (status & (MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR | MSC_STAT_CRC_RES_ERR)) {
+               printf("MMC/CD CRC error, MMC_STAT 0x%x\n", status);
+               return MMC_ERROR_CRC;
+       }
+
+       return MMC_NO_ERROR;
+}
+
+/* Obtain response to the command and store it to response buffer */
+static void jz_mmc_get_response(struct mmc_request *request)
+{
+       int i;
+       u8 *buf;
+       u32 data;
+
+       DEBUG(3, "fetch response for request %d, cmd %d\n", request->rtype, request->cmd);
+
+       buf = request->response;
+       request->result = MMC_NO_ERROR;
+
+       switch (request->rtype) {
+       case RESPONSE_R1: case RESPONSE_R1B: case RESPONSE_R6:
+       case RESPONSE_R3: case RESPONSE_R4: case RESPONSE_R5:
+       {
+               data = REG_MSC_RES;
+               buf[0] = (data >> 8) & 0xff;
+               buf[1] = data & 0xff;
+               data = REG_MSC_RES;
+               buf[2] = (data >> 8) & 0xff;
+               buf[3] = data & 0xff;
+               data = REG_MSC_RES;
+               buf[4] = data & 0xff;
+
+               DEBUG(3, "request %d, response [%02x %02x %02x %02x %02x]\n",
+                     request->rtype, buf[0], buf[1], buf[2], buf[3], buf[4]);
+               break;
+       }
+       case RESPONSE_R2_CID: case RESPONSE_R2_CSD:
+       {
+               for (i = 0; i < 16; i += 2) {
+                       data = REG_MSC_RES;
+                       buf[i] = (data >> 8) & 0xff;
+                       buf[i+1] = data & 0xff;
+               }
+               DEBUG(3, "request %d, response [", request->rtype);
+#if CONFIG_MMC_DEBUG_VERBOSE > 2
+               if (g_mmc_debug >= 3) {
+                       int n;
+                       for (n = 0; n < 17; n++)
+                               printk("%02x ", buf[n]);
+                       printk("]\n");
+               }
+#endif
+               break;
+       }
+       case RESPONSE_NONE:
+               DEBUG(3, "No response\n");
+               break;
+
+       default:
+               DEBUG(3, "unhandled response type for request %d\n", request->rtype);
+               break;
+       }
+}
+
+static int jz_mmc_receive_data(struct mmc_request *req)
+{
+       u32  stat, timeout, data, cnt;
+       u8 *buf = req->buffer;
+       u32 wblocklen = (u32)(req->block_len + 3) >> 2; /* length in word */
+
+       timeout = 0x3ffffff;
+
+       while (timeout) {
+               timeout--;
+               stat = REG_MSC_STAT;
+
+               if (stat & MSC_STAT_TIME_OUT_READ)
+                       return MMC_ERROR_TIMEOUT;
+               else if (stat & MSC_STAT_CRC_READ_ERROR)
+                       return MMC_ERROR_CRC;
+               else if (!(stat & MSC_STAT_DATA_FIFO_EMPTY)
+                        || (stat & MSC_STAT_DATA_FIFO_AFULL)) {
+                       /* Ready to read data */
+                       break;
+               }
+               udelay(1);
+       }
+       if (!timeout)
+               return MMC_ERROR_TIMEOUT;
+
+       /* Read data from RXFIFO. It could be FULL or PARTIAL FULL */
+       cnt = wblocklen;
+       while (cnt) {
+               data = REG_MSC_RXFIFO;
+               {
+                       *buf++ = (u8)(data >> 0);
+                       *buf++ = (u8)(data >> 8);
+                       *buf++ = (u8)(data >> 16);
+                       *buf++ = (u8)(data >> 24);
+               }
+               cnt --;
+               while (cnt && (REG_MSC_STAT & MSC_STAT_DATA_FIFO_EMPTY))
+                       ;
+       }
+       return MMC_NO_ERROR;
+}
+
+static int jz_mmc_transmit_data(struct mmc_request *req)
+{
+#if 0
+       u32 nob = req->nob;
+       u32 wblocklen = (u32)(req->block_len + 3) >> 2; /* length in word */
+       u8 *buf = req->buffer;
+       u32 *wbuf = (u32 *)buf;
+       u32 waligned = (((u32)buf & 0x3) == 0); /* word aligned ? */
+       u32 stat, timeout, data, cnt;
+
+       for (nob; nob >= 1; nob--) {
+               timeout = 0x3FFFFFF;
+
+               while (timeout) {
+                       timeout--;
+                       stat = REG_MSC_STAT;
+
+                       if (stat & (MSC_STAT_CRC_WRITE_ERROR | MSC_STAT_CRC_WRITE_ERROR_NOSTS))
+                               return MMC_ERROR_CRC;
+                       else if (!(stat & MSC_STAT_DATA_FIFO_FULL)) {
+                               /* Ready to write data */
+                               break;
+                       }
+
+                       udelay(1);
+               }
+
+               if (!timeout)
+                       return MMC_ERROR_TIMEOUT;
+
+               /* Write data to TXFIFO */
+               cnt = wblocklen;
+               while (cnt) {
+                       while (REG_MSC_STAT & MSC_STAT_DATA_FIFO_FULL)
+                               ;
+
+                       if (waligned) {
+                               REG_MSC_TXFIFO = *wbuf++;
+                       }
+                       else {
+                               data = *buf++ | (*buf++ << 8) | (*buf++ << 16) | (*buf++ << 24);
+                               REG_MSC_TXFIFO = data;
+                       }
+
+                       cnt--;
+               }
+       }
+#endif
+       return MMC_NO_ERROR;
+}
+
+
+/*
+ * Name:         int jz_mmc_exec_cmd()
+ * Function:      send command to the card, and get a response
+ * Input:        struct mmc_request *req       : MMC/SD request
+ * Output:       0:  right             >0:  error code
+ */
+int jz_mmc_exec_cmd(struct mmc_request *request)
+{
+       u32 cmdat = 0, events = 0;
+       int retval, timeout = 0x3fffff;
+
+       /* Indicate we have no result yet */
+       request->result = MMC_NO_RESPONSE;
+       if (request->cmd == MMC_CIM_RESET) {
+               /* On reset, 1-bit bus width */
+               use_4bit = 0;
+
+               /* Reset MMC/SD controller */
+               __msc_reset();
+
+               /* On reset, drop MMC clock down */
+               jz_mmc_set_clock(0, MMC_CLOCK_SLOW);
+
+               /* On reset, stop MMC clock */
+               jz_mmc_stop_clock();
+       }
+       if (request->cmd == MMC_SEND_OP_COND) {
+               DEBUG(3, "Have an MMC card\n");
+               /* always use 1bit for MMC */
+               use_4bit = 0;
+       }
+       if (request->cmd == SET_BUS_WIDTH) {
+               if (request->arg == 0x2) {
+                       printf("Use 4-bit bus width\n");
+                       use_4bit = 1;
+               }
+               else {
+                       printf("Use 1-bit bus width\n");                        
+                       use_4bit = 0;
+               }
+       }
+
+       /* stop clock */
+       jz_mmc_stop_clock();
+
+       /* mask all interrupts */
+       REG_MSC_IMASK = 0xffff;
+
+       /* clear status */
+       REG_MSC_IREG = 0xffff;
+
+       /* use 4-bit bus width when possible */
+       if (use_4bit)
+               cmdat |= MSC_CMDAT_BUS_WIDTH_4BIT;
+
+        /* Set command type and events */
+       switch (request->cmd) {
+       /* MMC core extra command */
+       case MMC_CIM_RESET:
+               cmdat |= MSC_CMDAT_INIT; /* Initialization sequence sent prior to command */
+               break;
+
+       /* bc - broadcast - no response */
+       case MMC_GO_IDLE_STATE:
+       case MMC_SET_DSR:
+               break;
+
+       /* bcr - broadcast with response */
+       case MMC_SEND_OP_COND:
+       case MMC_ALL_SEND_CID:
+       case MMC_GO_IRQ_STATE:
+               break;
+
+       /* adtc - addressed with data transfer */
+       case MMC_READ_DAT_UNTIL_STOP:
+       case MMC_READ_SINGLE_BLOCK:
+       case MMC_READ_MULTIPLE_BLOCK:
+       case SEND_SCR:
+               cmdat |= MSC_CMDAT_DATA_EN | MSC_CMDAT_READ;
+               events = MMC_EVENT_RX_DATA_DONE;
+               break;
+
+       case MMC_WRITE_DAT_UNTIL_STOP:
+       case MMC_WRITE_BLOCK:
+       case MMC_WRITE_MULTIPLE_BLOCK:
+       case MMC_PROGRAM_CID:
+       case MMC_PROGRAM_CSD:
+       case MMC_SEND_WRITE_PROT:
+       case MMC_GEN_CMD:
+       case MMC_LOCK_UNLOCK:
+               cmdat |= MSC_CMDAT_DATA_EN | MSC_CMDAT_WRITE;
+               events = MMC_EVENT_TX_DATA_DONE | MMC_EVENT_PROG_DONE;
+
+               break;
+
+       case MMC_STOP_TRANSMISSION:
+               events = MMC_EVENT_PROG_DONE;
+               break;
+
+       /* ac - no data transfer */
+       default:
+               break;
+       }
+
+       /* Set response type */
+       switch (request->rtype) {
+       case RESPONSE_NONE:
+               break;
+
+       case RESPONSE_R1B:
+               cmdat |= MSC_CMDAT_BUSY;
+               /*FALLTHRU*/
+       case RESPONSE_R1:
+               cmdat |= MSC_CMDAT_RESPONSE_R1;
+               break;
+       case RESPONSE_R2_CID:
+       case RESPONSE_R2_CSD:
+               cmdat |= MSC_CMDAT_RESPONSE_R2;
+               break;
+       case RESPONSE_R3:
+               cmdat |= MSC_CMDAT_RESPONSE_R3;
+               break;
+       case RESPONSE_R4:
+               cmdat |= MSC_CMDAT_RESPONSE_R4;
+               break;
+       case RESPONSE_R5:
+               cmdat |= MSC_CMDAT_RESPONSE_R5;
+               break;
+       case RESPONSE_R6:
+               cmdat |= MSC_CMDAT_RESPONSE_R6;
+               break;
+       default:
+               break;
+       }
+
+       /* Set command index */
+       if (request->cmd == MMC_CIM_RESET) {
+               REG_MSC_CMD = MMC_GO_IDLE_STATE;
+       } else {
+               REG_MSC_CMD = request->cmd;
+       }
+
+        /* Set argument */
+       REG_MSC_ARG = request->arg;
+
+       /* Set block length and nob */
+       if (request->cmd == SEND_SCR) { /* get SCR from DataFIFO */
+               REG_MSC_BLKLEN = 8;
+               REG_MSC_NOB = 1;
+       } else {
+               REG_MSC_BLKLEN = request->block_len;
+               REG_MSC_NOB = request->nob;
+       }
+
+       /* Set command */
+       REG_MSC_CMDAT = cmdat;
+
+       DEBUG(1, "Send cmd %d cmdat: %x arg: %x resp %d\n", request->cmd,
+             cmdat, request->arg, request->rtype);
+
+        /* Start MMC/SD clock and send command to card */
+       jz_mmc_start_clock();
+
+       /* Wait for command completion */
+       while (timeout-- && !(REG_MSC_STAT & MSC_STAT_END_CMD_RES))
+               ;
+
+       if (timeout == 0)
+               return MMC_ERROR_TIMEOUT;
+
+       REG_MSC_IREG = MSC_IREG_END_CMD_RES; /* clear flag */
+
+       /* Check for status */
+       retval = jz_mmc_check_status(request);
+       if (retval) {
+               return retval;
+       }
+
+       /* Complete command with no response */
+       if (request->rtype == RESPONSE_NONE) {
+               return MMC_NO_ERROR;
+       }
+
+       /* Get response */
+       jz_mmc_get_response(request);
+
+       /* Start data operation */
+       if (events & (MMC_EVENT_RX_DATA_DONE | MMC_EVENT_TX_DATA_DONE)) {
+               if (events & MMC_EVENT_RX_DATA_DONE) {
+                       if (request->cmd == SEND_SCR) {
+                               /* SD card returns SCR register as data.
+                                  MMC core expect it in the response buffer,
+                                  after normal response. */
+                               request->buffer = (u8 *)((u32)request->response + 5);
+                       }
+                       jz_mmc_receive_data(request);
+               }
+
+               if (events & MMC_EVENT_TX_DATA_DONE) {
+                       jz_mmc_transmit_data(request);
+               }
+
+               /* Wait for Data Done */
+               while (!(REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE))
+                       ;
+               REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE; /* clear status */
+       }
+
+       /* Wait for Prog Done event */
+       if (events & MMC_EVENT_PROG_DONE) {
+               while (!(REG_MSC_IREG & MSC_IREG_PRG_DONE))
+                       ;
+               REG_MSC_IREG = MSC_IREG_PRG_DONE; /* clear status */
+       }
+
+       /* Command completed */
+
+       return MMC_NO_ERROR;                     /* return successfully */
+}
+
+int mmc_block_read(u8 *dst, ulong src, ulong len)
+{
+
+       struct mmc_request request;
+       struct mmc_response_r1 r1;
+       int retval;
+
+       if (len == 0) {
+               return 0;
+       }
+       mmc_simple_cmd(&request, MMC_SEND_STATUS, mmcinfo.rca, RESPONSE_R1);
+       retval = mmc_unpack_r1(&request, &r1, 0);
+       if (retval && (retval != MMC_ERROR_STATE_MISMATCH)) {
+               return retval;
+       }
+
+       mmc_simple_cmd(&request, MMC_SET_BLOCKLEN, len, RESPONSE_R1);
+       if ((retval = mmc_unpack_r1(&request, &r1, 0))) {
+               return retval;
+       }
+
+       if (sd2_0)
+               src /= len;
+
+       mmc_send_cmd(&request, MMC_READ_SINGLE_BLOCK, src, 1,len, RESPONSE_R1, dst);
+       if ((retval = mmc_unpack_r1(&request, &r1, 0))) {
+               return retval;
+       }
+       return retval;
+}
+
+int mmc_block_write(ulong dst, uchar *src, int len)
+{
+       return 0;
+}
+
+int mmc_read(ulong src, uchar *dst, int size)
+{
+       ulong end, part_start, part_end, part_len, aligned_start, aligned_end;
+       ulong mmc_block_size, mmc_block_address;
+
+       if (size == 0) {
+               return 0;
+       }
+
+       if (!mmc_ready) {
+               printf("MMC card is not ready\n");
+               return -1;
+       }
+
+       mmc_block_size = MMC_BLOCK_SIZE;
+       mmc_block_address = ~(mmc_block_size - 1);
+
+       src -= CFG_MMC_BASE;
+       end = src + size;
+       part_start = ~mmc_block_address & src;
+       part_end = ~mmc_block_address & end;
+       aligned_start = mmc_block_address & src;
+       aligned_end = mmc_block_address & end;
+       /* all block aligned accesses */
+       debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+       src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
+       if (part_start) {
+               part_len = mmc_block_size - part_start;
+               debug("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+               src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
+               if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) {
+                       return -1;
+               }
+               memcpy(dst, mmc_buf+part_start, part_len);
+               dst += part_len;
+               src += part_len;
+       }
+       debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+       src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
+       for (; src < aligned_end; src += mmc_block_size, dst += mmc_block_size) {
+               debug("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+               src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
+
+               if ((mmc_block_read((uchar *)(dst), src, mmc_block_size)) < 0) {
+                       return -1;
+               }
+       }
+       debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+       src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
+
+       if (part_end && src < end) {
+               if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) {
+                       return -1;
+               }
+               memcpy(dst, mmc_buf, part_end);
+       }
+       return 0;
+
+}
+
+int mmc_write(uchar *src, ulong dst, int size)
+{
+       ulong end, part_start, part_end, part_len, aligned_start, aligned_end;
+       ulong mmc_block_size, mmc_block_address;
+
+       if (size == 0) {
+               return 0;
+       }
+
+       if (!mmc_ready) {
+               printf("MMC card is not ready\n");
+               return -1;
+       }
+
+       mmc_block_size = MMC_BLOCK_SIZE;
+       mmc_block_address = ~(mmc_block_size - 1);
+
+       dst -= CFG_MMC_BASE;
+       end = dst + size;
+       part_start = ~mmc_block_address & dst;
+       part_end = ~mmc_block_address & end;
+       aligned_start = mmc_block_address & dst;
+       aligned_end = mmc_block_address & end;
+
+       /* all block aligned accesses */
+       debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+       src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
+       if (part_start) {
+               part_len = mmc_block_size - part_start;
+               debug("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+               (ulong)src, dst, end, part_start, part_end, aligned_start, aligned_end);
+               if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) {
+                       return -1;
+               }
+               memcpy(mmc_buf+part_start, src, part_len);
+               if ((mmc_block_write(aligned_start, mmc_buf, mmc_block_size)) < 0) {
+                       return -1;
+               }
+               dst += part_len;
+               src += part_len;
+       }
+       debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+       src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
+       for (; dst < aligned_end; src += mmc_block_size, dst += mmc_block_size) {
+               debug("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+               src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
+               if ((mmc_block_write(dst, (uchar *)src, mmc_block_size)) < 0) {
+                       return -1;
+               }
+       }
+       debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+       src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
+       if (part_end && dst < end) {
+               debug("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+               src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
+               if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) {
+                       return -1;
+               }
+               memcpy(mmc_buf, src, part_end);
+               if ((mmc_block_write(aligned_end, mmc_buf, mmc_block_size)) < 0) {
+                       return -1;
+               }
+       }
+       return 0;
+}
+
+ulong mmc_bread(int dev_num, ulong blknr, ulong blkcnt, ulong *dst)
+{
+       ulong src;
+       int mmc_block_size = MMC_BLOCK_SIZE;
+
+       src = blknr * mmc_block_size + CFG_MMC_BASE;
+       mmc_read(src, (uchar *)dst, blkcnt*mmc_block_size);
+       return blkcnt;
+}
+
+int mmc_select_card(void)
+{
+       struct mmc_request request;
+       struct mmc_response_r1 r1;
+       int retval;
+
+       mmc_simple_cmd(&request, MMC_SELECT_CARD, mmcinfo.rca, RESPONSE_R1B);
+       retval = mmc_unpack_r1(&request, &r1, 0);
+       if (retval) {
+               return retval;
+       }
+
+       if (mmcinfo.sd) {
+               mmc_simple_cmd(&request, MMC_APP_CMD,  mmcinfo.rca, RESPONSE_R1);
+               retval = mmc_unpack_r1(&request,&r1,0);
+               if (retval) {
+                       return retval;
+               }
+#if defined(MMC_BUS_WIDTH_1BIT)                
+               mmc_simple_cmd(&request, SET_BUS_WIDTH, 1, RESPONSE_R1);
+#else
+               mmc_simple_cmd(&request, SET_BUS_WIDTH, 2, RESPONSE_R1);
+#endif
+                retval = mmc_unpack_r1(&request,&r1,0);
+                if (retval) {
+                       return retval;
+               }
+       }
+       return 0;
+}
+
+/*
+ * Configure card
+ */
+static void mmc_configure_card(void)
+{
+       u32 rate;
+
+       /* Get card info */
+       if (sd2_0)
+               mmcinfo.block_num = (mmcinfo.csd.c_size + 1) << 10;
+       else
+               mmcinfo.block_num = (mmcinfo.csd.c_size + 1) * (1 << (mmcinfo.csd.c_size_mult + 2));
+
+       mmcinfo.block_len = 1 << mmcinfo.csd.read_bl_len;
+
+       /* Fix the clock rate */
+       rate = mmc_tran_speed(mmcinfo.csd.tran_speed);
+       if (rate < MMC_CLOCK_SLOW)
+               rate = MMC_CLOCK_SLOW;
+       if ((mmcinfo.sd == 0) && (rate > MMC_CLOCK_FAST))
+               rate = MMC_CLOCK_FAST;
+        if ((mmcinfo.sd) && (rate > SD_CLOCK_FAST))
+               rate = SD_CLOCK_FAST;
+
+       DEBUG(2,"mmc_configure_card: block_len=%d block_num=%d rate=%d\n", mmcinfo.block_len, mmcinfo.block_num, rate);
+
+       jz_mmc_set_clock(mmcinfo.sd, rate);
+}
+
+/*
+ * State machine routines to initialize card(s)
+ */
+
+/*
+  CIM_SINGLE_CARD_ACQ  (frequency at 400 kHz)
+  --- Must enter from GO_IDLE_STATE ---
+  1. SD_SEND_OP_COND (SD Card) [CMD55] + [CMD41]
+  2. SEND_OP_COND (Full Range) [CMD1]   {optional}
+  3. SEND_OP_COND (Set Range ) [CMD1]
+     If busy, delay and repeat step 2
+  4. ALL_SEND_CID              [CMD2]
+     If timeout, set an error (no cards found)
+  5. SET_RELATIVE_ADDR         [CMD3]
+  6. SEND_CSD                  [CMD9]
+  7. SET_DSR                   [CMD4]    Only call this if (csd.dsr_imp).
+  8. Set clock frequency (check available in csd.tran_speed)
+ */
+
+#define MMC_INIT_DOING   0
+#define MMC_INIT_PASSED  1
+#define MMC_INIT_FAILED  2
+
+static int mmc_init_card_state(struct mmc_request *request)
+{
+       struct mmc_response_r1 r1;
+       struct mmc_response_r3 r3;
+       int retval;
+       int ocr = 0x40300000;
+       int limit_41 = 0;
+
+       DEBUG(2,"mmc_init_card_state\n");
+
+       switch (request->cmd) {
+       case MMC_GO_IDLE_STATE: /* No response to parse */
+               if (mmcinfo.sd)
+                       mmc_simple_cmd(request, 8, 0x1aa, RESPONSE_R1);
+               else
+                       mmc_simple_cmd(request, MMC_SEND_OP_COND, MMC_OCR_ARG, RESPONSE_R3);
+               break;
+
+       case 8:
+               retval = mmc_unpack_r1(request,&r1,mmcinfo.state);
+               mmc_simple_cmd(request, MMC_APP_CMD,  0, RESPONSE_R1);
+               break;
+
+        case MMC_APP_CMD:
+               retval = mmc_unpack_r1(request,&r1,mmcinfo.state);
+               if (retval & (limit_41 < 100)) {
+                       DEBUG(0, "mmc_init_card_state: unable to MMC_APP_CMD error=%d (%s)\n", 
+                             retval, mmc_result_to_string(retval));
+                       limit_41++;
+                       mmc_simple_cmd(request, SD_SEND_OP_COND, ocr, RESPONSE_R3);
+               } else if (limit_41 < 100) {
+                       limit_41++;
+                       mmc_simple_cmd(request, SD_SEND_OP_COND, ocr, RESPONSE_R3);
+               } else{
+                       /* reset the card to idle*/
+                       mmc_simple_cmd(request, MMC_GO_IDLE_STATE, 0, RESPONSE_NONE);
+                       mmcinfo.sd = 0;
+               }
+               break;
+
+        case SD_SEND_OP_COND:
+                retval = mmc_unpack_r3(request, &r3);
+                if (retval) {
+                  /* Try MMC card */
+                    mmc_simple_cmd(request, MMC_SEND_OP_COND, MMC_OCR_ARG, RESPONSE_R3);
+                    break;
+               }
+
+                DEBUG(2,"mmc_init_card_state: read ocr value = 0x%08x\n", r3.ocr);
+
+               if(!(r3.ocr & MMC_CARD_BUSY || ocr == 0)){
+                       udelay(10000);
+                       mmc_simple_cmd(request, MMC_APP_CMD, 0, RESPONSE_R1);
+               }
+               else {
+                 /* Set the data bus width to 4 bits */
+                  mmcinfo.sd = 1; /* SD Card ready */
+                  mmcinfo.state = CARD_STATE_READY;
+                 mmc_simple_cmd(request, MMC_ALL_SEND_CID, 0, RESPONSE_R2_CID);
+               }
+               break;
+
+       case MMC_SEND_OP_COND:
+               retval = mmc_unpack_r3(request, &r3);
+               if (retval) {
+                       DEBUG(0,"mmc_init_card_state: failed SEND_OP_COND error=%d (%s)\n", 
+                             retval, mmc_result_to_string(retval));
+                       return MMC_INIT_FAILED;
+               }
+
+               DEBUG(2,"mmc_init_card_state: read ocr value = 0x%08x\n", r3.ocr);
+               if (!(r3.ocr & MMC_CARD_BUSY)) {
+                       mmc_simple_cmd(request, MMC_SEND_OP_COND, MMC_OCR_ARG, RESPONSE_R3);
+               }
+               else {
+                       mmcinfo.sd = 0; /* MMC Card ready */
+                       mmcinfo.state = CARD_STATE_READY;
+                       mmc_simple_cmd(request, MMC_ALL_SEND_CID, 0, RESPONSE_R2_CID);
+               }
+               break;
+
+       case MMC_ALL_SEND_CID: 
+               retval = mmc_unpack_cid( request, &mmcinfo.cid );
+               mmc_dev.if_type = IF_TYPE_MMC;
+               mmc_dev.part_type = PART_TYPE_DOS;
+               mmc_dev.dev = 0;
+               mmc_dev.lun = 0;
+               mmc_dev.type = 0;
+               /* FIXME fill in the correct size (is set to 32MByte) */
+               mmc_dev.blksz = 512;
+               mmc_dev.lba = 0x10000;
+               mmc_dev.removable = 0;
+
+               /*FIXME:ignore CRC error for CMD2/CMD9/CMD10 */
+               if ( retval && (retval != MMC_ERROR_CRC)) {
+                       DEBUG(0,"mmc_init_card_state: unable to ALL_SEND_CID error=%d (%s)\n", 
+                             retval, mmc_result_to_string(retval));
+                       return MMC_INIT_FAILED;
+               }
+               mmcinfo.state = CARD_STATE_IDENT;
+               if(mmcinfo.sd)
+                       mmc_simple_cmd(request, MMC_SET_RELATIVE_ADDR, 0, RESPONSE_R6);
+                else
+                       mmc_simple_cmd(request, MMC_SET_RELATIVE_ADDR, ID_TO_RCA(mmcinfo.id) << 16, RESPONSE_R1);
+               break;
+
+        case MMC_SET_RELATIVE_ADDR:
+               if (mmcinfo.sd) {
+                       retval = mmc_unpack_r6(request, &r1, mmcinfo.state, &mmcinfo.rca);
+                       mmcinfo.rca = mmcinfo.rca << 16; 
+                       DEBUG(2, "mmc_init_card_state: Get RCA from SD: 0x%04x Status: %x\n", mmcinfo.rca, r1.status);
+                } else {
+                       retval = mmc_unpack_r1(request,&r1,mmcinfo.state);
+                       mmcinfo.rca = ID_TO_RCA(mmcinfo.id) << 16;
+               }
+               if (retval) {
+                       DEBUG(0, "mmc_init_card_state: unable to SET_RELATIVE_ADDR error=%d (%s)\n", 
+                             retval, mmc_result_to_string(retval));
+                       return MMC_INIT_FAILED;
+               }
+
+               mmcinfo.state = CARD_STATE_STBY;
+                mmc_simple_cmd(request, MMC_SEND_CSD, mmcinfo.rca, RESPONSE_R2_CSD);
+
+               break;
+
+       case MMC_SEND_CSD:
+               retval = mmc_unpack_csd(request, &mmcinfo.csd);
+                       mmc_csd_t *csd = (mmc_csd_t *)retval;
+                       memcpy(&mmc_csd, csd, sizeof(csd));
+                       mmc_ready = 1;
+
+                       printf("MMC card is ready\n");
+                       /* FIXME add verbose printout for csd */
+
+               /*FIXME:ignore CRC error for CMD2/CMD9/CMD10 */
+               if (retval && (retval != MMC_ERROR_CRC)) {
+                       DEBUG(0, "mmc_init_card_state: unable to SEND_CSD error=%d (%s)\n", 
+                             retval, mmc_result_to_string(retval));
+                       return MMC_INIT_FAILED;
+               }
+               if (mmcinfo.csd.dsr_imp) {
+                       DEBUG(0, "mmc_init_card_state: driver doesn't support setting DSR\n");
+               }
+               mmc_configure_card();
+               return MMC_INIT_PASSED;
+
+       default:
+               DEBUG(0, "mmc_init_card_state: error!  Illegal last cmd %d\n", request->cmd);
+               return MMC_INIT_FAILED;
+       }
+
+       return MMC_INIT_DOING;
+}
+
+int mmc_init_card(void)
+{
+       struct mmc_request request;
+       int retval;
+
+       mmc_simple_cmd(&request, MMC_CIM_RESET, 0, RESPONSE_NONE); /* reset card */
+       mmc_simple_cmd(&request, MMC_GO_IDLE_STATE, 0, RESPONSE_NONE);
+       mmcinfo.sd = 1;  /* assuming a SD card */
+
+       while ((retval = mmc_init_card_state(&request)) == MMC_INIT_DOING)
+               ;
+
+       if (retval == MMC_INIT_PASSED)
+               return MMC_NO_ERROR;
+       else
+               return MMC_NO_RESPONSE;
+}
+
+int mmc_legacy_init(int verbose)
+{
+       if (!__msc_card_detected())
+               return 1;
+
+       printf("MMC card found\n");
+
+       /* Step-1: init GPIO */
+       __gpio_as_msc();
+
+       __msc_init_io();
+
+       /* Step-2: turn on power of card */
+#if !defined(CONFIG_SAKC)
+       __msc_enable_power();
+#endif
+
+       /* Step-3: Reset MSC Controller. */
+       __msc_reset();
+
+       /* Step-3: mask all IRQs. */
+       MMC_IRQ_MASK();
+
+       /* Step-4: stop MMC/SD clock */
+       jz_mmc_stop_clock();
+       mmc_init_card();
+       mmc_select_card();
+
+       mmc_dev.block_read = mmc_bread;
+       fat_register_device(&mmc_dev,1); /* partitions start counting with 1 */
+
+       return 0;
+}
+
+int mmc_ident(block_dev_desc_t *dev)
+{
+       return 0;
+}
+
+int mmc2info(ulong addr)
+{
+       /* FIXME hard codes to 32 MB device */
+       if (addr >= CFG_MMC_BASE && addr < CFG_MMC_BASE + 0x02000000) {
+       return 1;
+       }
+       return 0;
+}
+/*
+ * Debugging functions
+ */
+
+static char * mmc_result_strings[] = {
+       "NO_RESPONSE",
+       "NO_ERROR",
+       "ERROR_OUT_OF_RANGE",
+       "ERROR_ADDRESS",
+       "ERROR_BLOCK_LEN",
+       "ERROR_ERASE_SEQ",
+       "ERROR_ERASE_PARAM",
+       "ERROR_WP_VIOLATION",
+       "ERROR_CARD_IS_LOCKED",
+       "ERROR_LOCK_UNLOCK_FAILED",
+       "ERROR_COM_CRC",
+       "ERROR_ILLEGAL_COMMAND",
+       "ERROR_CARD_ECC_FAILED",
+       "ERROR_CC",
+       "ERROR_GENERAL",
+       "ERROR_UNDERRUN",
+       "ERROR_OVERRUN",
+       "ERROR_CID_CSD_OVERWRITE",
+       "ERROR_STATE_MISMATCH",
+       "ERROR_HEADER_MISMATCH",
+       "ERROR_TIMEOUT",
+       "ERROR_CRC",
+       "ERROR_DRIVER_FAILURE",
+};
+
+char * mmc_result_to_string(int i)
+{
+       return mmc_result_strings[i+1];
+}
+
+static char * card_state_strings[] = {
+       "empty",
+       "idle",
+       "ready",
+       "ident",
+       "stby",
+       "tran",
+       "data",
+       "rcv",
+       "prg",
+       "dis",
+};
+
+static inline char * card_state_to_string(int i)
+{
+       return card_state_strings[i+1];
+}
+
+/*
+ * Utility functions
+ */
+
+#define PARSE_U32(_buf,_index) \
+       (((u32)_buf[_index]) << 24) | (((u32)_buf[_index+1]) << 16) | \
+        (((u32)_buf[_index+2]) << 8) | ((u32)_buf[_index+3]);
+
+#define PARSE_U16(_buf,_index) \
+       (((u16)_buf[_index]) << 8) | ((u16)_buf[_index+1]);
+
+int mmc_unpack_csd(struct mmc_request *request, struct mmc_csd *csd)
+{
+       u8 *buf = request->response;
+       int num = 0;
+
+       if (request->result)
+               return request->result;
+
+       csd->csd_structure      = (buf[1] & 0xc0) >> 6;
+       if (csd->csd_structure)
+               sd2_0 = 1;
+       else
+               sd2_0 = 0;
+
+       switch (csd->csd_structure) {
+       case 0 :
+               csd->taac               = buf[2];
+               csd->nsac               = buf[3];
+               csd->tran_speed         = buf[4];
+               csd->ccc                = (((u16)buf[5]) << 4) | ((buf[6] & 0xf0) >> 4);
+               csd->read_bl_len        = buf[6] & 0x0f;
+               /* for support 2GB card*/
+               if (csd->read_bl_len >= 10)
+               {
+                       num = csd->read_bl_len - 9;
+                       csd->read_bl_len = 9;
+               }
+
+               csd->read_bl_partial    = (buf[7] & 0x80) ? 1 : 0;
+               csd->write_blk_misalign = (buf[7] & 0x40) ? 1 : 0;
+               csd->read_blk_misalign  = (buf[7] & 0x20) ? 1 : 0;
+               csd->dsr_imp            = (buf[7] & 0x10) ? 1 : 0;
+               csd->c_size             = ((((u16)buf[7]) & 0x03) << 10) | (((u16)buf[8]) << 2) | (((u16)buf[9]) & 0xc0) >> 6;
+
+               if (num)
+                       csd->c_size = csd->c_size << num;
+
+
+               csd->vdd_r_curr_min     = (buf[9] & 0x38) >> 3;
+               csd->vdd_r_curr_max     = buf[9] & 0x07;
+               csd->vdd_w_curr_min     = (buf[10] & 0xe0) >> 5;
+               csd->vdd_w_curr_max     = (buf[10] & 0x1c) >> 2;
+               csd->c_size_mult        = ((buf[10] & 0x03) << 1) | ((buf[11] & 0x80) >> 7);
+               switch (csd->csd_structure) {
+               case CSD_STRUCT_VER_1_0:
+               case CSD_STRUCT_VER_1_1:
+                       csd->erase.v22.sector_size    = (buf[11] & 0x7c) >> 2;
+                       csd->erase.v22.erase_grp_size = ((buf[11] & 0x03) << 3) | ((buf[12] & 0xe0) >> 5);
+
+                       break;
+               case CSD_STRUCT_VER_1_2:
+               default:
+                       csd->erase.v31.erase_grp_size = (buf[11] & 0x7c) >> 2;
+                       csd->erase.v31.erase_grp_mult = ((buf[11] & 0x03) << 3) | ((buf[12] & 0xe0) >> 5);
+                       break;
+               }
+               csd->wp_grp_size        = buf[12] & 0x1f;
+               csd->wp_grp_enable      = (buf[13] & 0x80) ? 1 : 0;
+               csd->default_ecc        = (buf[13] & 0x60) >> 5;
+               csd->r2w_factor         = (buf[13] & 0x1c) >> 2;
+               csd->write_bl_len       = ((buf[13] & 0x03) << 2) | ((buf[14] & 0xc0) >> 6);
+               if (csd->write_bl_len >= 10)
+                       csd->write_bl_len = 9;
+
+               csd->write_bl_partial   = (buf[14] & 0x20) ? 1 : 0;
+               csd->file_format_grp    = (buf[15] & 0x80) ? 1 : 0;
+               csd->copy               = (buf[15] & 0x40) ? 1 : 0;
+               csd->perm_write_protect = (buf[15] & 0x20) ? 1 : 0;
+               csd->tmp_write_protect  = (buf[15] & 0x10) ? 1 : 0;
+               csd->file_format        = (buf[15] & 0x0c) >> 2;
+               csd->ecc                = buf[15] & 0x03;
+
+               DEBUG(2,"  csd_structure=%d  spec_vers=%d  taac=%02x  nsac=%02x  tran_speed=%02x\n"
+                     "  ccc=%04x  read_bl_len=%d  read_bl_partial=%d  write_blk_misalign=%d\n"
+                     "  read_blk_misalign=%d  dsr_imp=%d  c_size=%d  vdd_r_curr_min=%d\n"
+                     "  vdd_r_curr_max=%d  vdd_w_curr_min=%d  vdd_w_curr_max=%d  c_size_mult=%d\n"
+                     "  wp_grp_size=%d  wp_grp_enable=%d  default_ecc=%d  r2w_factor=%d\n"
+                     "  write_bl_len=%d  write_bl_partial=%d  file_format_grp=%d  copy=%d\n"
+                     "  perm_write_protect=%d  tmp_write_protect=%d  file_format=%d  ecc=%d\n",
+                     csd->csd_structure, csd->spec_vers, 
+                     csd->taac, csd->nsac, csd->tran_speed,
+                     csd->ccc, csd->read_bl_len, 
+                     csd->read_bl_partial, csd->write_blk_misalign,
+                     csd->read_blk_misalign, csd->dsr_imp, 
+                     csd->c_size, csd->vdd_r_curr_min,
+                     csd->vdd_r_curr_max, csd->vdd_w_curr_min, 
+                     csd->vdd_w_curr_max, csd->c_size_mult,
+                     csd->wp_grp_size, csd->wp_grp_enable,
+                     csd->default_ecc, csd->r2w_factor, 
+                     csd->write_bl_len, csd->write_bl_partial,
+                     csd->file_format_grp, csd->copy, 
+                     csd->perm_write_protect, csd->tmp_write_protect,
+                     csd->file_format, csd->ecc);
+               switch (csd->csd_structure) {
+               case CSD_STRUCT_VER_1_0:
+               case CSD_STRUCT_VER_1_1:
+                       DEBUG(2," V22 sector_size=%d erase_grp_size=%d\n", 
+                             csd->erase.v22.sector_size, 
+                             csd->erase.v22.erase_grp_size);
+                       break;
+               case CSD_STRUCT_VER_1_2:
+               default:
+                       DEBUG(2," V31 erase_grp_size=%d erase_grp_mult=%d\n", 
+                             csd->erase.v31.erase_grp_size,
+                             csd->erase.v31.erase_grp_mult);
+                       break;
+
+               }
+               break;
+
+       case 1 :
+               csd->taac               = 0;
+               csd->nsac               = 0;
+               csd->tran_speed         = buf[4];
+               csd->ccc                = (((u16)buf[5]) << 4) | ((buf[6] & 0xf0) >> 4);
+
+               csd->read_bl_len        = 9;
+               csd->read_bl_partial    = 0;
+               csd->write_blk_misalign = 0;
+               csd->read_blk_misalign  = 0;
+               csd->dsr_imp            = (buf[7] & 0x10) ? 1 : 0;
+               csd->c_size             = ((((u16)buf[8]) & 0x3f) << 16) | (((u16)buf[9]) << 8) | ((u16)buf[10]) ;
+               switch (csd->csd_structure) {
+               case CSD_STRUCT_VER_1_0:
+               case CSD_STRUCT_VER_1_1:
+                       csd->erase.v22.sector_size    = 0x7f;
+                       csd->erase.v22.erase_grp_size = 0;
+                       break;
+               case CSD_STRUCT_VER_1_2:
+               default:
+                       csd->erase.v31.erase_grp_size = 0x7f;
+                       csd->erase.v31.erase_grp_mult = 0;
+                       break;
+               }
+               csd->wp_grp_size        = 0;
+               csd->wp_grp_enable      = 0;
+               csd->default_ecc        = (buf[13] & 0x60) >> 5;
+               csd->r2w_factor         = 4;/* Unused */
+               csd->write_bl_len       = 9;
+
+               csd->write_bl_partial   = 0;
+               csd->file_format_grp    = 0;
+               csd->copy               = (buf[15] & 0x40) ? 1 : 0;
+               csd->perm_write_protect = (buf[15] & 0x20) ? 1 : 0;
+               csd->tmp_write_protect  = (buf[15] & 0x10) ? 1 : 0;
+               csd->file_format        = 0;
+               csd->ecc                = buf[15] & 0x03;
+
+               DEBUG(2,"  csd_structure=%d  spec_vers=%d  taac=%02x  nsac=%02x  tran_speed=%02x\n"
+                     "  ccc=%04x  read_bl_len=%d  read_bl_partial=%d  write_blk_misalign=%d\n"
+                     "  read_blk_misalign=%d  dsr_imp=%d  c_size=%d  vdd_r_curr_min=%d\n"
+                     "  vdd_r_curr_max=%d  vdd_w_curr_min=%d  vdd_w_curr_max=%d  c_size_mult=%d\n"
+                     "  wp_grp_size=%d  wp_grp_enable=%d  default_ecc=%d  r2w_factor=%d\n"
+                     "  write_bl_len=%d  write_bl_partial=%d  file_format_grp=%d  copy=%d\n"
+                     "  perm_write_protect=%d  tmp_write_protect=%d  file_format=%d  ecc=%d\n",
+                     csd->csd_structure, csd->spec_vers, 
+                     csd->taac, csd->nsac, csd->tran_speed,
+                     csd->ccc, csd->read_bl_len, 
+                     csd->read_bl_partial, csd->write_blk_misalign,
+                     csd->read_blk_misalign, csd->dsr_imp, 
+                     csd->c_size, csd->vdd_r_curr_min,
+                     csd->vdd_r_curr_max, csd->vdd_w_curr_min, 
+                     csd->vdd_w_curr_max, csd->c_size_mult,
+                     csd->wp_grp_size, csd->wp_grp_enable,
+                     csd->default_ecc, csd->r2w_factor, 
+                     csd->write_bl_len, csd->write_bl_partial,
+                     csd->file_format_grp, csd->copy, 
+                     csd->perm_write_protect, csd->tmp_write_protect,
+                     csd->file_format, csd->ecc);
+               switch (csd->csd_structure) {
+               case CSD_STRUCT_VER_1_0:
+               case CSD_STRUCT_VER_1_1:
+                       DEBUG(2," V22 sector_size=%d erase_grp_size=%d\n", 
+                             csd->erase.v22.sector_size, 
+                             csd->erase.v22.erase_grp_size);
+                       break;
+               case CSD_STRUCT_VER_1_2:
+               default:
+                       DEBUG(2," V31 erase_grp_size=%d erase_grp_mult=%d\n", 
+                             csd->erase.v31.erase_grp_size,
+                             csd->erase.v31.erase_grp_mult);
+                       break;
+               }
+       }
+
+       if (buf[0] != 0x3f)  return MMC_ERROR_HEADER_MISMATCH;
+
+       return 0;
+}
+
+int mmc_unpack_r1(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state)
+{
+       u8 *buf = request->response;
+
+       if (request->result)        return request->result;
+
+       r1->cmd    = buf[0];
+       r1->status = PARSE_U32(buf,1);
+
+       DEBUG(2, "mmc_unpack_r1: cmd=%d status=%08x\n", r1->cmd, r1->status);
+
+       if (R1_STATUS(r1->status)) {
+               if (r1->status & R1_OUT_OF_RANGE)       return MMC_ERROR_OUT_OF_RANGE;
+               if (r1->status & R1_ADDRESS_ERROR)      return MMC_ERROR_ADDRESS;
+               if (r1->status & R1_BLOCK_LEN_ERROR)    return MMC_ERROR_BLOCK_LEN;
+               if (r1->status & R1_ERASE_SEQ_ERROR)    return MMC_ERROR_ERASE_SEQ;
+               if (r1->status & R1_ERASE_PARAM)        return MMC_ERROR_ERASE_PARAM;
+               if (r1->status & R1_WP_VIOLATION)       return MMC_ERROR_WP_VIOLATION;
+               /*if (r1->status & R1_CARD_IS_LOCKED)     return MMC_ERROR_CARD_IS_LOCKED; */
+               if (r1->status & R1_LOCK_UNLOCK_FAILED) return MMC_ERROR_LOCK_UNLOCK_FAILED;
+               if (r1->status & R1_COM_CRC_ERROR)      return MMC_ERROR_COM_CRC;
+               if (r1->status & R1_ILLEGAL_COMMAND)    return MMC_ERROR_ILLEGAL_COMMAND;
+               if (r1->status & R1_CARD_ECC_FAILED)    return MMC_ERROR_CARD_ECC_FAILED;
+               if (r1->status & R1_CC_ERROR)           return MMC_ERROR_CC;
+               if (r1->status & R1_ERROR)              return MMC_ERROR_GENERAL;
+               if (r1->status & R1_UNDERRUN)           return MMC_ERROR_UNDERRUN;
+               if (r1->status & R1_OVERRUN)            return MMC_ERROR_OVERRUN;
+               if (r1->status & R1_CID_CSD_OVERWRITE)  return MMC_ERROR_CID_CSD_OVERWRITE;
+       }
+
+       if (buf[0] != request->cmd) return MMC_ERROR_HEADER_MISMATCH;
+
+       /* This should be last - it's the least dangerous error */
+
+       return 0;
+}
+
+int mmc_unpack_scr(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state, u32 *scr)
+{
+        u8 *buf = request->response;
+       if (request->result)        return request->result;
+
+        *scr = PARSE_U32(buf, 5); /* Save SCR returned by the SD Card */
+        return mmc_unpack_r1(request, r1, state);
+
+}
+
+int mmc_unpack_r6(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state, int *rca)
+{
+       u8 *buf = request->response;
+
+       if (request->result)        return request->result;
+
+        *rca = PARSE_U16(buf,1);  /* Save RCA returned by the SD Card */
+
+        *(buf+1) = 0;
+        *(buf+2) = 0;
+
+        return mmc_unpack_r1(request, r1, state);
+}
+
+int mmc_unpack_cid(struct mmc_request *request, struct mmc_cid *cid)
+{
+       u8 *buf = request->response;
+       int i;
+
+       if (request->result) return request->result;
+
+       cid->mid = buf[1];
+       cid->oid = PARSE_U16(buf,2);
+       for (i = 0 ; i < 6 ; i++)
+               cid->pnm[i] = buf[4+i];
+       cid->pnm[6] = 0;
+       cid->prv = buf[10];
+       cid->psn = PARSE_U32(buf,11);
+       cid->mdt = buf[15];
+
+       DEBUG(2,"mmc_unpack_cid: mid=%d oid=%d pnm=%s prv=%d.%d psn=%08x mdt=%d/%d\n",
+             cid->mid, cid->oid, cid->pnm, 
+             (cid->prv>>4), (cid->prv&0xf), 
+             cid->psn, (cid->mdt>>4), (cid->mdt&0xf)+1997);
+
+       if (buf[0] != 0x3f)  return MMC_ERROR_HEADER_MISMATCH;
+       return 0;
+}
+
+int mmc_unpack_r3(struct mmc_request *request, struct mmc_response_r3 *r3)
+{
+       u8 *buf = request->response;
+
+       if (request->result) return request->result;
+
+       r3->ocr = PARSE_U32(buf,1);
+       DEBUG(2,"mmc_unpack_r3: ocr=%08x\n", r3->ocr);
+
+       if (buf[0] != 0x3f)  return MMC_ERROR_HEADER_MISMATCH;
+       return 0;
+}
+
+#define KBPS 1
+#define MBPS 1000
+
+static u32 ts_exp[] = { 100*KBPS, 1*MBPS, 10*MBPS, 100*MBPS, 0, 0, 0, 0 };
+static u32 ts_mul[] = { 0,    1000, 1200, 1300, 1500, 2000, 2500, 3000, 
+                       3500, 4000, 4500, 5000, 5500, 6000, 7000, 8000 };
+
+u32 mmc_tran_speed(u8 ts)
+{
+       u32 rate = ts_exp[(ts & 0x7)] * ts_mul[(ts & 0x78) >> 3];
+
+       if (rate <= 0) {
+               DEBUG(0, "mmc_tran_speed: error - unrecognized speed 0x%02x\n", ts);
+               return 1;
+       }
+
+       return rate;
+}
+
+void mmc_send_cmd(struct mmc_request *request, int cmd, u32 arg, 
+                  u16 nob, u16 block_len, enum mmc_rsp_t rtype, u8 *buffer)
+{
+       request->cmd       = cmd;
+       request->arg       = arg;
+       request->rtype     = rtype;
+       request->nob       = nob;
+       request->block_len = block_len;
+       request->buffer    = buffer;
+       request->cnt       = nob * block_len;
+
+       jz_mmc_exec_cmd(request);
+}
+
+#endif /* CONFIG_MMC */
+#endif  /* CONFIG_JZ4740 */
diff --git a/package/uboot-xburst/files/cpu/mips/jz_mmc.c.orig b/package/uboot-xburst/files/cpu/mips/jz_mmc.c.orig
new file mode 100644 (file)
index 0000000..114ff11
--- /dev/null
@@ -0,0 +1,1399 @@
+/*
+ * (C) Copyright 2003
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <part.h>
+
+#if defined CONFIG_JZ4740
+#include <asm-mips/jz4740.h>
+
+#include "jz_mmc.h"
+
+#define CFG_MMC_BASE           0x80600000
+static int sd2_0 = 0;
+
+/*
+ * GPIO definition
+ */
+#define __msc_init_io()                                \
+do {                                           \
+       __gpio_as_output(GPIO_SD_VCC_EN_N);     \
+       __gpio_as_input(GPIO_SD_CD_N);          \
+} while (0)
+
+#define __msc_enable_power()                   \
+do {                                           \
+       __gpio_clear_pin(GPIO_SD_VCC_EN_N);     \
+} while (0)
+
+#define __msc_disable_power()                  \
+do {                                           \
+       __gpio_set_pin(GPIO_SD_VCC_EN_N);       \
+} while (0)
+
+#define __msc_card_detected()                  \
+({                                             \
+       int detected = 1;                       \
+       __gpio_as_input(GPIO_SD_CD_N);          \
+       if (!__gpio_get_pin(GPIO_SD_CD_N))      \
+               detected = 0;                   \
+       detected;                               \
+})
+
+/*
+ * Local functions
+ */
+
+#ifdef CONFIG_MMC
+extern int
+fat_register_device(block_dev_desc_t *dev_desc, int part_no);
+
+static block_dev_desc_t mmc_dev;
+
+block_dev_desc_t * mmc_get_dev(int dev)
+{
+       return ((block_dev_desc_t *)&mmc_dev);
+}
+
+/*
+ * FIXME needs to read cid and csd info to determine block size
+ * and other parameters
+ */
+static uchar mmc_buf[MMC_BLOCK_SIZE];
+static int mmc_ready = 0;
+static mmc_csd_t mmc_csd;
+static int use_4bit;                    /* Use 4-bit data bus */
+/*
+ *  MMC Events
+ */
+#define MMC_EVENT_NONE         0x00    /* No events */
+#define MMC_EVENT_RX_DATA_DONE 0x01    /* Rx data done */
+#define MMC_EVENT_TX_DATA_DONE 0x02    /* Tx data done */
+#define MMC_EVENT_PROG_DONE    0x04    /* Programming is done */
+
+
+#define MMC_IRQ_MASK()                         \
+do {                                           \
+       REG_MSC_IMASK = 0xffff;                 \
+       REG_MSC_IREG = 0xffff;                  \
+} while (0)
+
+/* Stop the MMC clock and wait while it happens */
+static inline int jz_mmc_stop_clock(void)
+{
+       int timeout = 1000;
+
+       REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP;
+
+       while (timeout && (REG_MSC_STAT & MSC_STAT_CLK_EN)) {
+               timeout--;
+               if (timeout == 0) {
+                       return MMC_ERROR_TIMEOUT;
+               }
+               udelay(1);
+       }
+        return MMC_NO_ERROR;
+}
+
+/* Start the MMC clock and operation */
+static inline int jz_mmc_start_clock(void)
+{
+       REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START | MSC_STRPCL_START_OP;
+       return MMC_NO_ERROR;
+}
+
+static inline u32 jz_mmc_calc_clkrt(int is_sd, u32 rate)
+{
+       u32 clkrt;
+       u32 clk_src = is_sd ? 24000000: 16000000;
+
+       clkrt = 0;
+       while (rate < clk_src)
+       {
+               clkrt ++;
+               clk_src >>= 1;
+       }
+       return clkrt;
+}
+
+/* Set the MMC clock frequency */
+void jz_mmc_set_clock(int sd, u32 rate)
+{
+       jz_mmc_stop_clock();
+
+       /* Select clock source of MSC */
+       __cpm_select_msc_clk(sd);
+
+       /* Set clock dividor of MSC */
+       REG_MSC_CLKRT = jz_mmc_calc_clkrt(sd, rate);
+}
+
+static int jz_mmc_check_status(struct mmc_request *request)
+{
+       u32 status = REG_MSC_STAT;
+
+       /* Checking for response or data timeout */
+       if (status & (MSC_STAT_TIME_OUT_RES | MSC_STAT_TIME_OUT_READ)) {
+               printf("MMC/SD timeout, MMC_STAT 0x%x CMD %d\n", status, request->cmd);
+               return MMC_ERROR_TIMEOUT;
+       }
+
+       /* Checking for CRC error */
+       if (status & (MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR | MSC_STAT_CRC_RES_ERR)) {
+               printf("MMC/CD CRC error, MMC_STAT 0x%x\n", status);
+               return MMC_ERROR_CRC;
+       }
+
+       return MMC_NO_ERROR;
+}
+
+/* Obtain response to the command and store it to response buffer */
+static void jz_mmc_get_response(struct mmc_request *request)
+{
+       int i;
+       u8 *buf;
+       u32 data;
+
+       DEBUG(3, "fetch response for request %d, cmd %d\n", request->rtype, request->cmd);
+
+       buf = request->response;
+       request->result = MMC_NO_ERROR;
+
+       switch (request->rtype) {
+       case RESPONSE_R1: case RESPONSE_R1B: case RESPONSE_R6:
+       case RESPONSE_R3: case RESPONSE_R4: case RESPONSE_R5:
+       {
+               data = REG_MSC_RES;
+               buf[0] = (data >> 8) & 0xff;
+               buf[1] = data & 0xff;
+               data = REG_MSC_RES;
+               buf[2] = (data >> 8) & 0xff;
+               buf[3] = data & 0xff;
+               data = REG_MSC_RES;
+               buf[4] = data & 0xff;
+
+               DEBUG(3, "request %d, response [%02x %02x %02x %02x %02x]\n",
+                     request->rtype, buf[0], buf[1], buf[2], buf[3], buf[4]);
+               break;
+       }
+       case RESPONSE_R2_CID: case RESPONSE_R2_CSD:
+       {
+               for (i = 0; i < 16; i += 2) {
+                       data = REG_MSC_RES;
+                       buf[i] = (data >> 8) & 0xff;
+                       buf[i+1] = data & 0xff;
+               }
+               DEBUG(3, "request %d, response [", request->rtype);
+#if CONFIG_MMC_DEBUG_VERBOSE > 2
+               if (g_mmc_debug >= 3) {
+                       int n;
+                       for (n = 0; n < 17; n++)
+                               printk("%02x ", buf[n]);
+                       printk("]\n");
+               }
+#endif
+               break;
+       }
+       case RESPONSE_NONE:
+               DEBUG(3, "No response\n");
+               break;
+
+       default:
+               DEBUG(3, "unhandled response type for request %d\n", request->rtype);
+               break;
+       }
+}
+
+static int jz_mmc_receive_data(struct mmc_request *req)
+{
+       u32  stat, timeout, data, cnt;
+       u8 *buf = req->buffer;
+       u32 wblocklen = (u32)(req->block_len + 3) >> 2; /* length in word */
+
+       timeout = 0x3ffffff;
+
+       while (timeout) {
+               timeout--;
+               stat = REG_MSC_STAT;
+
+               if (stat & MSC_STAT_TIME_OUT_READ)
+                       return MMC_ERROR_TIMEOUT;
+               else if (stat & MSC_STAT_CRC_READ_ERROR)
+                       return MMC_ERROR_CRC;
+               else if (!(stat & MSC_STAT_DATA_FIFO_EMPTY)
+                        || (stat & MSC_STAT_DATA_FIFO_AFULL)) {
+                       /* Ready to read data */
+                       break;
+               }
+               udelay(1);
+       }
+       if (!timeout)
+               return MMC_ERROR_TIMEOUT;
+
+       /* Read data from RXFIFO. It could be FULL or PARTIAL FULL */
+       cnt = wblocklen;
+       while (cnt) {
+               data = REG_MSC_RXFIFO;
+               {
+                       *buf++ = (u8)(data >> 0);
+                       *buf++ = (u8)(data >> 8);
+                       *buf++ = (u8)(data >> 16);
+                       *buf++ = (u8)(data >> 24);
+               }
+               cnt --;
+               while (cnt && (REG_MSC_STAT & MSC_STAT_DATA_FIFO_EMPTY))
+                       ;
+       }
+       return MMC_NO_ERROR;
+}
+
+static int jz_mmc_transmit_data(struct mmc_request *req)
+{
+#if 0
+       u32 nob = req->nob;
+       u32 wblocklen = (u32)(req->block_len + 3) >> 2; /* length in word */
+       u8 *buf = req->buffer;
+       u32 *wbuf = (u32 *)buf;
+       u32 waligned = (((u32)buf & 0x3) == 0); /* word aligned ? */
+       u32 stat, timeout, data, cnt;
+
+       for (nob; nob >= 1; nob--) {
+               timeout = 0x3FFFFFF;
+
+               while (timeout) {
+                       timeout--;
+                       stat = REG_MSC_STAT;
+
+                       if (stat & (MSC_STAT_CRC_WRITE_ERROR | MSC_STAT_CRC_WRITE_ERROR_NOSTS))
+                               return MMC_ERROR_CRC;
+                       else if (!(stat & MSC_STAT_DATA_FIFO_FULL)) {
+                               /* Ready to write data */
+                               break;
+                       }
+
+                       udelay(1);
+               }
+
+               if (!timeout)
+                       return MMC_ERROR_TIMEOUT;
+
+               /* Write data to TXFIFO */
+               cnt = wblocklen;
+               while (cnt) {
+                       while (REG_MSC_STAT & MSC_STAT_DATA_FIFO_FULL)
+                               ;
+
+                       if (waligned) {
+                               REG_MSC_TXFIFO = *wbuf++;
+                       }
+                       else {
+                               data = *buf++ | (*buf++ << 8) | (*buf++ << 16) | (*buf++ << 24);
+                               REG_MSC_TXFIFO = data;
+                       }
+
+                       cnt--;
+               }
+       }
+#endif
+       return MMC_NO_ERROR;
+}
+
+
+/*
+ * Name:         int jz_mmc_exec_cmd()
+ * Function:      send command to the card, and get a response
+ * Input:        struct mmc_request *req       : MMC/SD request
+ * Output:       0:  right             >0:  error code
+ */
+int jz_mmc_exec_cmd(struct mmc_request *request)
+{
+       u32 cmdat = 0, events = 0;
+       int retval, timeout = 0x3fffff;
+
+       /* Indicate we have no result yet */
+       request->result = MMC_NO_RESPONSE;
+       if (request->cmd == MMC_CIM_RESET) {
+               /* On reset, 1-bit bus width */
+               use_4bit = 0;
+
+               /* Reset MMC/SD controller */
+               __msc_reset();
+
+               /* On reset, drop MMC clock down */
+               jz_mmc_set_clock(0, MMC_CLOCK_SLOW);
+
+               /* On reset, stop MMC clock */
+               jz_mmc_stop_clock();
+       }
+       if (request->cmd == MMC_SEND_OP_COND) {
+               DEBUG(3, "Have an MMC card\n");
+               /* always use 1bit for MMC */
+               use_4bit = 0;
+       }
+       if (request->cmd == SET_BUS_WIDTH) {
+               if (request->arg == 0x2) {
+                       DEBUG(2, "Use 4-bit bus width\n");
+                       use_4bit = 1;
+               }
+               else {
+                       DEBUG(2, "Use 1-bit bus width\n");
+                       use_4bit = 0;
+               }
+       }
+
+       /* stop clock */
+       jz_mmc_stop_clock();
+
+       /* mask all interrupts */
+       REG_MSC_IMASK = 0xffff;
+
+       /* clear status */
+       REG_MSC_IREG = 0xffff;
+
+       /* use 4-bit bus width when possible */
+       if (use_4bit)
+               cmdat |= MSC_CMDAT_BUS_WIDTH_4BIT;
+
+        /* Set command type and events */
+       switch (request->cmd) {
+       /* MMC core extra command */
+       case MMC_CIM_RESET:
+               cmdat |= MSC_CMDAT_INIT; /* Initialization sequence sent prior to command */
+               break;
+
+       /* bc - broadcast - no response */
+       case MMC_GO_IDLE_STATE:
+       case MMC_SET_DSR:
+               break;
+
+       /* bcr - broadcast with response */
+       case MMC_SEND_OP_COND:
+       case MMC_ALL_SEND_CID:
+       case MMC_GO_IRQ_STATE:
+               break;
+
+       /* adtc - addressed with data transfer */
+       case MMC_READ_DAT_UNTIL_STOP:
+       case MMC_READ_SINGLE_BLOCK:
+       case MMC_READ_MULTIPLE_BLOCK:
+       case SEND_SCR:
+               cmdat |= MSC_CMDAT_DATA_EN | MSC_CMDAT_READ;
+               events = MMC_EVENT_RX_DATA_DONE;
+               break;
+
+       case MMC_WRITE_DAT_UNTIL_STOP:
+       case MMC_WRITE_BLOCK:
+       case MMC_WRITE_MULTIPLE_BLOCK:
+       case MMC_PROGRAM_CID:
+       case MMC_PROGRAM_CSD:
+       case MMC_SEND_WRITE_PROT:
+       case MMC_GEN_CMD:
+       case MMC_LOCK_UNLOCK:
+               cmdat |= MSC_CMDAT_DATA_EN | MSC_CMDAT_WRITE;
+               events = MMC_EVENT_TX_DATA_DONE | MMC_EVENT_PROG_DONE;
+
+               break;
+
+       case MMC_STOP_TRANSMISSION:
+               events = MMC_EVENT_PROG_DONE;
+               break;
+
+       /* ac - no data transfer */
+       default:
+               break;
+       }
+
+       /* Set response type */
+       switch (request->rtype) {
+       case RESPONSE_NONE:
+               break;
+
+       case RESPONSE_R1B:
+               cmdat |= MSC_CMDAT_BUSY;
+               /*FALLTHRU*/
+       case RESPONSE_R1:
+               cmdat |= MSC_CMDAT_RESPONSE_R1;
+               break;
+       case RESPONSE_R2_CID:
+       case RESPONSE_R2_CSD:
+               cmdat |= MSC_CMDAT_RESPONSE_R2;
+               break;
+       case RESPONSE_R3:
+               cmdat |= MSC_CMDAT_RESPONSE_R3;
+               break;
+       case RESPONSE_R4:
+               cmdat |= MSC_CMDAT_RESPONSE_R4;
+               break;
+       case RESPONSE_R5:
+               cmdat |= MSC_CMDAT_RESPONSE_R5;
+               break;
+       case RESPONSE_R6:
+               cmdat |= MSC_CMDAT_RESPONSE_R6;
+               break;
+       default:
+               break;
+       }
+
+       /* Set command index */
+       if (request->cmd == MMC_CIM_RESET) {
+               REG_MSC_CMD = MMC_GO_IDLE_STATE;
+       } else {
+               REG_MSC_CMD = request->cmd;
+       }
+
+        /* Set argument */
+       REG_MSC_ARG = request->arg;
+
+       /* Set block length and nob */
+       if (request->cmd == SEND_SCR) { /* get SCR from DataFIFO */
+               REG_MSC_BLKLEN = 8;
+               REG_MSC_NOB = 1;
+       } else {
+               REG_MSC_BLKLEN = request->block_len;
+               REG_MSC_NOB = request->nob;
+       }
+
+       /* Set command */
+       REG_MSC_CMDAT = cmdat;
+
+       DEBUG(1, "Send cmd %d cmdat: %x arg: %x resp %d\n", request->cmd,
+             cmdat, request->arg, request->rtype);
+
+        /* Start MMC/SD clock and send command to card */
+       jz_mmc_start_clock();
+
+       /* Wait for command completion */
+       while (timeout-- && !(REG_MSC_STAT & MSC_STAT_END_CMD_RES))
+               ;
+
+       if (timeout == 0)
+               return MMC_ERROR_TIMEOUT;
+
+       REG_MSC_IREG = MSC_IREG_END_CMD_RES; /* clear flag */
+
+       /* Check for status */
+       retval = jz_mmc_check_status(request);
+       if (retval) {
+               return retval;
+       }
+
+       /* Complete command with no response */
+       if (request->rtype == RESPONSE_NONE) {
+               return MMC_NO_ERROR;
+       }
+
+       /* Get response */
+       jz_mmc_get_response(request);
+
+       /* Start data operation */
+       if (events & (MMC_EVENT_RX_DATA_DONE | MMC_EVENT_TX_DATA_DONE)) {
+               if (events & MMC_EVENT_RX_DATA_DONE) {
+                       if (request->cmd == SEND_SCR) {
+                               /* SD card returns SCR register as data.
+                                  MMC core expect it in the response buffer,
+                                  after normal response. */
+                               request->buffer = (u8 *)((u32)request->response + 5);
+                       }
+                       jz_mmc_receive_data(request);
+               }
+
+               if (events & MMC_EVENT_TX_DATA_DONE) {
+                       jz_mmc_transmit_data(request);
+               }
+
+               /* Wait for Data Done */
+               while (!(REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE))
+                       ;
+               REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE; /* clear status */
+       }
+
+       /* Wait for Prog Done event */
+       if (events & MMC_EVENT_PROG_DONE) {
+               while (!(REG_MSC_IREG & MSC_IREG_PRG_DONE))
+                       ;
+               REG_MSC_IREG = MSC_IREG_PRG_DONE; /* clear status */
+       }
+
+       /* Command completed */
+
+       return MMC_NO_ERROR;                     /* return successfully */
+}
+
+int mmc_block_read(u8 *dst, ulong src, ulong len)
+{
+
+       struct mmc_request request;
+       struct mmc_response_r1 r1;
+       int retval;
+
+       if (len == 0) {
+               return 0;
+       }
+       mmc_simple_cmd(&request, MMC_SEND_STATUS, mmcinfo.rca, RESPONSE_R1);
+       retval = mmc_unpack_r1(&request, &r1, 0);
+       if (retval && (retval != MMC_ERROR_STATE_MISMATCH)) {
+               return retval;
+       }
+
+       mmc_simple_cmd(&request, MMC_SET_BLOCKLEN, len, RESPONSE_R1);
+       if ((retval = mmc_unpack_r1(&request, &r1, 0))) {
+               return retval;
+       }
+
+       if (sd2_0)
+               src /= len;
+
+       mmc_send_cmd(&request, MMC_READ_SINGLE_BLOCK, src, 1,len, RESPONSE_R1, dst);
+       if ((retval = mmc_unpack_r1(&request, &r1, 0))) {
+               return retval;
+       }
+       return retval;
+}
+
+int mmc_block_write(ulong dst, uchar *src, int len)
+{
+       return 0;
+}
+
+int mmc_read(ulong src, uchar *dst, int size)
+{
+       ulong end, part_start, part_end, part_len, aligned_start, aligned_end;
+       ulong mmc_block_size, mmc_block_address;
+
+       if (size == 0) {
+               return 0;
+       }
+
+       if (!mmc_ready) {
+               printf("MMC card is not ready\n");
+               return -1;
+       }
+
+       mmc_block_size = MMC_BLOCK_SIZE;
+       mmc_block_address = ~(mmc_block_size - 1);
+
+       src -= CFG_MMC_BASE;
+       end = src + size;
+       part_start = ~mmc_block_address & src;
+       part_end = ~mmc_block_address & end;
+       aligned_start = mmc_block_address & src;
+       aligned_end = mmc_block_address & end;
+       /* all block aligned accesses */
+       debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+       src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
+       if (part_start) {
+               part_len = mmc_block_size - part_start;
+               debug("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+               src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
+               if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) {
+                       return -1;
+               }
+               memcpy(dst, mmc_buf+part_start, part_len);
+               dst += part_len;
+               src += part_len;
+       }
+       debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+       src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
+       for (; src < aligned_end; src += mmc_block_size, dst += mmc_block_size) {
+               debug("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+               src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
+
+               if ((mmc_block_read((uchar *)(dst), src, mmc_block_size)) < 0) {
+                       return -1;
+               }
+       }
+       debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+       src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
+
+       if (part_end && src < end) {
+               if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) {
+                       return -1;
+               }
+               memcpy(dst, mmc_buf, part_end);
+       }
+       return 0;
+
+}
+
+int mmc_write(uchar *src, ulong dst, int size)
+{
+       ulong end, part_start, part_end, part_len, aligned_start, aligned_end;
+       ulong mmc_block_size, mmc_block_address;
+
+       if (size == 0) {
+               return 0;
+       }
+
+       if (!mmc_ready) {
+               printf("MMC card is not ready\n");
+               return -1;
+       }
+
+       mmc_block_size = MMC_BLOCK_SIZE;
+       mmc_block_address = ~(mmc_block_size - 1);
+
+       dst -= CFG_MMC_BASE;
+       end = dst + size;
+       part_start = ~mmc_block_address & dst;
+       part_end = ~mmc_block_address & end;
+       aligned_start = mmc_block_address & dst;
+       aligned_end = mmc_block_address & end;
+
+       /* all block aligned accesses */
+       debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+       src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
+       if (part_start) {
+               part_len = mmc_block_size - part_start;
+               debug("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+               (ulong)src, dst, end, part_start, part_end, aligned_start, aligned_end);
+               if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) {
+                       return -1;
+               }
+               memcpy(mmc_buf+part_start, src, part_len);
+               if ((mmc_block_write(aligned_start, mmc_buf, mmc_block_size)) < 0) {
+                       return -1;
+               }
+               dst += part_len;
+               src += part_len;
+       }
+       debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+       src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
+       for (; dst < aligned_end; src += mmc_block_size, dst += mmc_block_size) {
+               debug("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+               src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
+               if ((mmc_block_write(dst, (uchar *)src, mmc_block_size)) < 0) {
+                       return -1;
+               }
+       }
+       debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+       src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
+       if (part_end && dst < end) {
+               debug("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+               src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
+               if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) {
+                       return -1;
+               }
+               memcpy(mmc_buf, src, part_end);
+               if ((mmc_block_write(aligned_end, mmc_buf, mmc_block_size)) < 0) {
+                       return -1;
+               }
+       }
+       return 0;
+}
+
+ulong mmc_bread(int dev_num, ulong blknr, ulong blkcnt, ulong *dst)
+{
+       ulong src;
+       int mmc_block_size = MMC_BLOCK_SIZE;
+
+       src = blknr * mmc_block_size + CFG_MMC_BASE;
+       mmc_read(src, (uchar *)dst, blkcnt*mmc_block_size);
+       return blkcnt;
+}
+
+int mmc_select_card(void)
+{
+       struct mmc_request request;
+       struct mmc_response_r1 r1;
+       int retval;
+
+       mmc_simple_cmd(&request, MMC_SELECT_CARD, mmcinfo.rca, RESPONSE_R1B);
+       retval = mmc_unpack_r1(&request, &r1, 0);
+       if (retval) {
+               return retval;
+       }
+
+       if (mmcinfo.sd) {
+               mmc_simple_cmd(&request, MMC_APP_CMD,  mmcinfo.rca, RESPONSE_R1);
+               retval = mmc_unpack_r1(&request,&r1,0);
+               if (retval) {
+                       return retval;
+               }
+               mmc_simple_cmd(&request, SET_BUS_WIDTH, 2, RESPONSE_R1);
+                retval = mmc_unpack_r1(&request,&r1,0);
+                if (retval) {
+                       return retval;
+               }
+       }
+       return 0;
+}
+
+/*
+ * Configure card
+ */
+static void mmc_configure_card(void)
+{
+       u32 rate;
+
+       /* Get card info */
+       if (sd2_0)
+               mmcinfo.block_num = (mmcinfo.csd.c_size + 1) << 10;
+       else
+               mmcinfo.block_num = (mmcinfo.csd.c_size + 1) * (1 << (mmcinfo.csd.c_size_mult + 2));
+
+       mmcinfo.block_len = 1 << mmcinfo.csd.read_bl_len;
+
+       /* Fix the clock rate */
+       rate = mmc_tran_speed(mmcinfo.csd.tran_speed);
+       if (rate < MMC_CLOCK_SLOW)
+               rate = MMC_CLOCK_SLOW;
+       if ((mmcinfo.sd == 0) && (rate > MMC_CLOCK_FAST))
+               rate = MMC_CLOCK_FAST;
+        if ((mmcinfo.sd) && (rate > SD_CLOCK_FAST))
+               rate = SD_CLOCK_FAST;
+
+       DEBUG(2,"mmc_configure_card: block_len=%d block_num=%d rate=%d\n", mmcinfo.block_len, mmcinfo.block_num, rate);
+
+       jz_mmc_set_clock(mmcinfo.sd, rate);
+}
+
+/*
+ * State machine routines to initialize card(s)
+ */
+
+/*
+  CIM_SINGLE_CARD_ACQ  (frequency at 400 kHz)
+  --- Must enter from GO_IDLE_STATE ---
+  1. SD_SEND_OP_COND (SD Card) [CMD55] + [CMD41]
+  2. SEND_OP_COND (Full Range) [CMD1]   {optional}
+  3. SEND_OP_COND (Set Range ) [CMD1]
+     If busy, delay and repeat step 2
+  4. ALL_SEND_CID              [CMD2]
+     If timeout, set an error (no cards found)
+  5. SET_RELATIVE_ADDR         [CMD3]
+  6. SEND_CSD                  [CMD9]
+  7. SET_DSR                   [CMD4]    Only call this if (csd.dsr_imp).
+  8. Set clock frequency (check available in csd.tran_speed)
+ */
+
+#define MMC_INIT_DOING   0
+#define MMC_INIT_PASSED  1
+#define MMC_INIT_FAILED  2
+
+static int mmc_init_card_state(struct mmc_request *request)
+{
+       struct mmc_response_r1 r1;
+       struct mmc_response_r3 r3;
+       int retval;
+       int ocr = 0x40300000;
+       int limit_41 = 0;
+
+       DEBUG(2,"mmc_init_card_state\n");
+
+       switch (request->cmd) {
+       case MMC_GO_IDLE_STATE: /* No response to parse */
+               if (mmcinfo.sd)
+                       mmc_simple_cmd(request, 8, 0x1aa, RESPONSE_R1);
+               else
+                       mmc_simple_cmd(request, MMC_SEND_OP_COND, MMC_OCR_ARG, RESPONSE_R3);
+               break;
+
+       case 8:
+               retval = mmc_unpack_r1(request,&r1,mmcinfo.state);
+               mmc_simple_cmd(request, MMC_APP_CMD,  0, RESPONSE_R1);
+               break;
+
+        case MMC_APP_CMD:
+               retval = mmc_unpack_r1(request,&r1,mmcinfo.state);
+               if (retval & (limit_41 < 100)) {
+                       DEBUG(0, "mmc_init_card_state: unable to MMC_APP_CMD error=%d (%s)\n", 
+                             retval, mmc_result_to_string(retval));
+                       limit_41++;
+                       mmc_simple_cmd(request, SD_SEND_OP_COND, ocr, RESPONSE_R3);
+               } else if (limit_41 < 100) {
+                       limit_41++;
+                       mmc_simple_cmd(request, SD_SEND_OP_COND, ocr, RESPONSE_R3);
+               } else{
+                       /* reset the card to idle*/
+                       mmc_simple_cmd(request, MMC_GO_IDLE_STATE, 0, RESPONSE_NONE);
+                       mmcinfo.sd = 0;
+               }
+               break;
+
+        case SD_SEND_OP_COND:
+                retval = mmc_unpack_r3(request, &r3);
+                if (retval) {
+                  /* Try MMC card */
+                    mmc_simple_cmd(request, MMC_SEND_OP_COND, MMC_OCR_ARG, RESPONSE_R3);
+                    break;
+               }
+
+                DEBUG(2,"mmc_init_card_state: read ocr value = 0x%08x\n", r3.ocr);
+
+               if(!(r3.ocr & MMC_CARD_BUSY || ocr == 0)){
+                       udelay(10000);
+                       mmc_simple_cmd(request, MMC_APP_CMD, 0, RESPONSE_R1);
+               }
+               else {
+                 /* Set the data bus width to 4 bits */
+                  mmcinfo.sd = 1; /* SD Card ready */
+                  mmcinfo.state = CARD_STATE_READY;
+                 mmc_simple_cmd(request, MMC_ALL_SEND_CID, 0, RESPONSE_R2_CID);
+               }
+               break;
+
+       case MMC_SEND_OP_COND:
+               retval = mmc_unpack_r3(request, &r3);
+               if (retval) {
+                       DEBUG(0,"mmc_init_card_state: failed SEND_OP_COND error=%d (%s)\n", 
+                             retval, mmc_result_to_string(retval));
+                       return MMC_INIT_FAILED;
+               }
+
+               DEBUG(2,"mmc_init_card_state: read ocr value = 0x%08x\n", r3.ocr);
+               if (!(r3.ocr & MMC_CARD_BUSY)) {
+                       mmc_simple_cmd(request, MMC_SEND_OP_COND, MMC_OCR_ARG, RESPONSE_R3);
+               }
+               else {
+                       mmcinfo.sd = 0; /* MMC Card ready */
+                       mmcinfo.state = CARD_STATE_READY;
+                       mmc_simple_cmd(request, MMC_ALL_SEND_CID, 0, RESPONSE_R2_CID);
+               }
+               break;
+
+       case MMC_ALL_SEND_CID: 
+               retval = mmc_unpack_cid( request, &mmcinfo.cid );
+               mmc_dev.if_type = IF_TYPE_MMC;
+               mmc_dev.part_type = PART_TYPE_DOS;
+               mmc_dev.dev = 0;
+               mmc_dev.lun = 0;
+               mmc_dev.type = 0;
+               /* FIXME fill in the correct size (is set to 32MByte) */
+               mmc_dev.blksz = 512;
+               mmc_dev.lba = 0x10000;
+               mmc_dev.removable = 0;
+
+               /*FIXME:ignore CRC error for CMD2/CMD9/CMD10 */
+               if ( retval && (retval != MMC_ERROR_CRC)) {
+                       DEBUG(0,"mmc_init_card_state: unable to ALL_SEND_CID error=%d (%s)\n", 
+                             retval, mmc_result_to_string(retval));
+                       return MMC_INIT_FAILED;
+               }
+               mmcinfo.state = CARD_STATE_IDENT;
+               if(mmcinfo.sd)
+                       mmc_simple_cmd(request, MMC_SET_RELATIVE_ADDR, 0, RESPONSE_R6);
+                else
+                       mmc_simple_cmd(request, MMC_SET_RELATIVE_ADDR, ID_TO_RCA(mmcinfo.id) << 16, RESPONSE_R1);
+               break;
+
+        case MMC_SET_RELATIVE_ADDR:
+               if (mmcinfo.sd) {
+                       retval = mmc_unpack_r6(request, &r1, mmcinfo.state, &mmcinfo.rca);
+                       mmcinfo.rca = mmcinfo.rca << 16; 
+                       DEBUG(2, "mmc_init_card_state: Get RCA from SD: 0x%04x Status: %x\n", mmcinfo.rca, r1.status);
+                } else {
+                       retval = mmc_unpack_r1(request,&r1,mmcinfo.state);
+                       mmcinfo.rca = ID_TO_RCA(mmcinfo.id) << 16;
+               }
+               if (retval) {
+                       DEBUG(0, "mmc_init_card_state: unable to SET_RELATIVE_ADDR error=%d (%s)\n", 
+                             retval, mmc_result_to_string(retval));
+                       return MMC_INIT_FAILED;
+               }
+
+               mmcinfo.state = CARD_STATE_STBY;
+                mmc_simple_cmd(request, MMC_SEND_CSD, mmcinfo.rca, RESPONSE_R2_CSD);
+
+               break;
+
+       case MMC_SEND_CSD:
+               retval = mmc_unpack_csd(request, &mmcinfo.csd);
+                       mmc_csd_t *csd = (mmc_csd_t *)retval;
+                       memcpy(&mmc_csd, csd, sizeof(csd));
+                       mmc_ready = 1;
+
+                       printf("MMC card is ready\n");
+                       /* FIXME add verbose printout for csd */
+
+               /*FIXME:ignore CRC error for CMD2/CMD9/CMD10 */
+               if (retval && (retval != MMC_ERROR_CRC)) {
+                       DEBUG(0, "mmc_init_card_state: unable to SEND_CSD error=%d (%s)\n", 
+                             retval, mmc_result_to_string(retval));
+                       return MMC_INIT_FAILED;
+               }
+               if (mmcinfo.csd.dsr_imp) {
+                       DEBUG(0, "mmc_init_card_state: driver doesn't support setting DSR\n");
+               }
+               mmc_configure_card();
+               return MMC_INIT_PASSED;
+
+       default:
+               DEBUG(0, "mmc_init_card_state: error!  Illegal last cmd %d\n", request->cmd);
+               return MMC_INIT_FAILED;
+       }
+
+       return MMC_INIT_DOING;
+}
+
+int mmc_init_card(void)
+{
+       struct mmc_request request;
+       int retval;
+
+       mmc_simple_cmd(&request, MMC_CIM_RESET, 0, RESPONSE_NONE); /* reset card */
+       mmc_simple_cmd(&request, MMC_GO_IDLE_STATE, 0, RESPONSE_NONE);
+       mmcinfo.sd = 1;  /* assuming a SD card */
+
+       while ((retval = mmc_init_card_state(&request)) == MMC_INIT_DOING)
+               ;
+
+       if (retval == MMC_INIT_PASSED)
+               return MMC_NO_ERROR;
+       else
+               return MMC_NO_RESPONSE;
+}
+
+int mmc_legacy_init(int verbose)
+{
+       if (!__msc_card_detected())
+               return 1;
+
+       printf("MMC card found\n");
+
+       /* Step-1: init GPIO */
+       __gpio_as_msc();
+
+       __msc_init_io();
+
+       /* Step-2: turn on power of card */
+       __msc_enable_power();
+
+       /* Step-3: Reset MSC Controller. */
+       __msc_reset();
+
+       /* Step-3: mask all IRQs. */
+       MMC_IRQ_MASK();
+
+       /* Step-4: stop MMC/SD clock */
+       jz_mmc_stop_clock();
+       mmc_init_card();
+       mmc_select_card();
+
+       mmc_dev.block_read = mmc_bread;
+       fat_register_device(&mmc_dev,1); /* partitions start counting with 1 */
+
+       return 0;
+}
+
+int mmc_ident(block_dev_desc_t *dev)
+{
+       return 0;
+}
+
+int mmc2info(ulong addr)
+{
+       /* FIXME hard codes to 32 MB device */
+       if (addr >= CFG_MMC_BASE && addr < CFG_MMC_BASE + 0x02000000) {
+       return 1;
+       }
+       return 0;
+}
+/*
+ * Debugging functions
+ */
+
+static char * mmc_result_strings[] = {
+       "NO_RESPONSE",
+       "NO_ERROR",
+       "ERROR_OUT_OF_RANGE",
+       "ERROR_ADDRESS",
+       "ERROR_BLOCK_LEN",
+       "ERROR_ERASE_SEQ",
+       "ERROR_ERASE_PARAM",
+       "ERROR_WP_VIOLATION",
+       "ERROR_CARD_IS_LOCKED",
+       "ERROR_LOCK_UNLOCK_FAILED",
+       "ERROR_COM_CRC",
+       "ERROR_ILLEGAL_COMMAND",
+       "ERROR_CARD_ECC_FAILED",
+       "ERROR_CC",
+       "ERROR_GENERAL",
+       "ERROR_UNDERRUN",
+       "ERROR_OVERRUN",
+       "ERROR_CID_CSD_OVERWRITE",
+       "ERROR_STATE_MISMATCH",
+       "ERROR_HEADER_MISMATCH",
+       "ERROR_TIMEOUT",
+       "ERROR_CRC",
+       "ERROR_DRIVER_FAILURE",
+};
+
+char * mmc_result_to_string(int i)
+{
+       return mmc_result_strings[i+1];
+}
+
+static char * card_state_strings[] = {
+       "empty",
+       "idle",
+       "ready",
+       "ident",
+       "stby",
+       "tran",
+       "data",
+       "rcv",
+       "prg",
+       "dis",
+};
+
+static inline char * card_state_to_string(int i)
+{
+       return card_state_strings[i+1];
+}
+
+/*
+ * Utility functions
+ */
+
+#define PARSE_U32(_buf,_index) \
+       (((u32)_buf[_index]) << 24) | (((u32)_buf[_index+1]) << 16) | \
+        (((u32)_buf[_index+2]) << 8) | ((u32)_buf[_index+3]);
+
+#define PARSE_U16(_buf,_index) \
+       (((u16)_buf[_index]) << 8) | ((u16)_buf[_index+1]);
+
+int mmc_unpack_csd(struct mmc_request *request, struct mmc_csd *csd)
+{
+       u8 *buf = request->response;
+       int num = 0;
+
+       if (request->result)
+               return request->result;
+
+       csd->csd_structure      = (buf[1] & 0xc0) >> 6;
+       if (csd->csd_structure)
+               sd2_0 = 1;
+       else
+               sd2_0 = 0;
+
+       switch (csd->csd_structure) {
+       case 0 :
+               csd->taac               = buf[2];
+               csd->nsac               = buf[3];
+               csd->tran_speed         = buf[4];
+               csd->ccc                = (((u16)buf[5]) << 4) | ((buf[6] & 0xf0) >> 4);
+               csd->read_bl_len        = buf[6] & 0x0f;
+               /* for support 2GB card*/
+               if (csd->read_bl_len >= 10)
+               {
+                       num = csd->read_bl_len - 9;
+                       csd->read_bl_len = 9;
+               }
+
+               csd->read_bl_partial    = (buf[7] & 0x80) ? 1 : 0;
+               csd->write_blk_misalign = (buf[7] & 0x40) ? 1 : 0;
+               csd->read_blk_misalign  = (buf[7] & 0x20) ? 1 : 0;
+               csd->dsr_imp            = (buf[7] & 0x10) ? 1 : 0;
+               csd->c_size             = ((((u16)buf[7]) & 0x03) << 10) | (((u16)buf[8]) << 2) | (((u16)buf[9]) & 0xc0) >> 6;
+
+               if (num)
+                       csd->c_size = csd->c_size << num;
+
+
+               csd->vdd_r_curr_min     = (buf[9] & 0x38) >> 3;
+               csd->vdd_r_curr_max     = buf[9] & 0x07;
+               csd->vdd_w_curr_min     = (buf[10] & 0xe0) >> 5;
+               csd->vdd_w_curr_max     = (buf[10] & 0x1c) >> 2;
+               csd->c_size_mult        = ((buf[10] & 0x03) << 1) | ((buf[11] & 0x80) >> 7);
+               switch (csd->csd_structure) {
+               case CSD_STRUCT_VER_1_0:
+               case CSD_STRUCT_VER_1_1:
+                       csd->erase.v22.sector_size    = (buf[11] & 0x7c) >> 2;
+                       csd->erase.v22.erase_grp_size = ((buf[11] & 0x03) << 3) | ((buf[12] & 0xe0) >> 5);
+
+                       break;
+               case CSD_STRUCT_VER_1_2:
+               default:
+                       csd->erase.v31.erase_grp_size = (buf[11] & 0x7c) >> 2;
+                       csd->erase.v31.erase_grp_mult = ((buf[11] & 0x03) << 3) | ((buf[12] & 0xe0) >> 5);
+                       break;
+               }
+               csd->wp_grp_size        = buf[12] & 0x1f;
+               csd->wp_grp_enable      = (buf[13] & 0x80) ? 1 : 0;
+               csd->default_ecc        = (buf[13] & 0x60) >> 5;
+               csd->r2w_factor         = (buf[13] & 0x1c) >> 2;
+               csd->write_bl_len       = ((buf[13] & 0x03) << 2) | ((buf[14] & 0xc0) >> 6);
+               if (csd->write_bl_len >= 10)
+                       csd->write_bl_len = 9;
+
+               csd->write_bl_partial   = (buf[14] & 0x20) ? 1 : 0;
+               csd->file_format_grp    = (buf[15] & 0x80) ? 1 : 0;
+               csd->copy               = (buf[15] & 0x40) ? 1 : 0;
+               csd->perm_write_protect = (buf[15] & 0x20) ? 1 : 0;
+               csd->tmp_write_protect  = (buf[15] & 0x10) ? 1 : 0;
+               csd->file_format        = (buf[15] & 0x0c) >> 2;
+               csd->ecc                = buf[15] & 0x03;
+
+               DEBUG(2,"  csd_structure=%d  spec_vers=%d  taac=%02x  nsac=%02x  tran_speed=%02x\n"
+                     "  ccc=%04x  read_bl_len=%d  read_bl_partial=%d  write_blk_misalign=%d\n"
+                     "  read_blk_misalign=%d  dsr_imp=%d  c_size=%d  vdd_r_curr_min=%d\n"
+                     "  vdd_r_curr_max=%d  vdd_w_curr_min=%d  vdd_w_curr_max=%d  c_size_mult=%d\n"
+                     "  wp_grp_size=%d  wp_grp_enable=%d  default_ecc=%d  r2w_factor=%d\n"
+                     "  write_bl_len=%d  write_bl_partial=%d  file_format_grp=%d  copy=%d\n"
+                     "  perm_write_protect=%d  tmp_write_protect=%d  file_format=%d  ecc=%d\n",
+                     csd->csd_structure, csd->spec_vers, 
+                     csd->taac, csd->nsac, csd->tran_speed,
+                     csd->ccc, csd->read_bl_len, 
+                     csd->read_bl_partial, csd->write_blk_misalign,
+                     csd->read_blk_misalign, csd->dsr_imp, 
+                     csd->c_size, csd->vdd_r_curr_min,
+                     csd->vdd_r_curr_max, csd->vdd_w_curr_min, 
+                     csd->vdd_w_curr_max, csd->c_size_mult,
+                     csd->wp_grp_size, csd->wp_grp_enable,
+                     csd->default_ecc, csd->r2w_factor, 
+                     csd->write_bl_len, csd->write_bl_partial,
+                     csd->file_format_grp, csd->copy, 
+                     csd->perm_write_protect, csd->tmp_write_protect,
+                     csd->file_format, csd->ecc);
+               switch (csd->csd_structure) {
+               case CSD_STRUCT_VER_1_0:
+               case CSD_STRUCT_VER_1_1:
+                       DEBUG(2," V22 sector_size=%d erase_grp_size=%d\n", 
+                             csd->erase.v22.sector_size, 
+                             csd->erase.v22.erase_grp_size);
+                       break;
+               case CSD_STRUCT_VER_1_2:
+               default:
+                       DEBUG(2," V31 erase_grp_size=%d erase_grp_mult=%d\n", 
+                             csd->erase.v31.erase_grp_size,
+                             csd->erase.v31.erase_grp_mult);
+                       break;
+
+               }
+               break;
+
+       case 1 :
+               csd->taac               = 0;
+               csd->nsac               = 0;
+               csd->tran_speed         = buf[4];
+               csd->ccc                = (((u16)buf[5]) << 4) | ((buf[6] & 0xf0) >> 4);
+
+               csd->read_bl_len        = 9;
+               csd->read_bl_partial    = 0;
+               csd->write_blk_misalign = 0;
+               csd->read_blk_misalign  = 0;
+               csd->dsr_imp            = (buf[7] & 0x10) ? 1 : 0;
+               csd->c_size             = ((((u16)buf[8]) & 0x3f) << 16) | (((u16)buf[9]) << 8) | ((u16)buf[10]) ;
+               switch (csd->csd_structure) {
+               case CSD_STRUCT_VER_1_0:
+               case CSD_STRUCT_VER_1_1:
+                       csd->erase.v22.sector_size    = 0x7f;
+                       csd->erase.v22.erase_grp_size = 0;
+                       break;
+               case CSD_STRUCT_VER_1_2:
+               default:
+                       csd->erase.v31.erase_grp_size = 0x7f;
+                       csd->erase.v31.erase_grp_mult = 0;
+                       break;
+               }
+               csd->wp_grp_size        = 0;
+               csd->wp_grp_enable      = 0;
+               csd->default_ecc        = (buf[13] & 0x60) >> 5;
+               csd->r2w_factor         = 4;/* Unused */
+               csd->write_bl_len       = 9;
+
+               csd->write_bl_partial   = 0;
+               csd->file_format_grp    = 0;
+               csd->copy               = (buf[15] & 0x40) ? 1 : 0;
+               csd->perm_write_protect = (buf[15] & 0x20) ? 1 : 0;
+               csd->tmp_write_protect  = (buf[15] & 0x10) ? 1 : 0;
+               csd->file_format        = 0;
+               csd->ecc                = buf[15] & 0x03;
+
+               DEBUG(2,"  csd_structure=%d  spec_vers=%d  taac=%02x  nsac=%02x  tran_speed=%02x\n"
+                     "  ccc=%04x  read_bl_len=%d  read_bl_partial=%d  write_blk_misalign=%d\n"
+                     "  read_blk_misalign=%d  dsr_imp=%d  c_size=%d  vdd_r_curr_min=%d\n"
+                     "  vdd_r_curr_max=%d  vdd_w_curr_min=%d  vdd_w_curr_max=%d  c_size_mult=%d\n"
+                     "  wp_grp_size=%d  wp_grp_enable=%d  default_ecc=%d  r2w_factor=%d\n"
+                     "  write_bl_len=%d  write_bl_partial=%d  file_format_grp=%d  copy=%d\n"
+                     "  perm_write_protect=%d  tmp_write_protect=%d  file_format=%d  ecc=%d\n",
+                     csd->csd_structure, csd->spec_vers, 
+                     csd->taac, csd->nsac, csd->tran_speed,
+                     csd->ccc, csd->read_bl_len, 
+                     csd->read_bl_partial, csd->write_blk_misalign,
+                     csd->read_blk_misalign, csd->dsr_imp, 
+                     csd->c_size, csd->vdd_r_curr_min,
+                     csd->vdd_r_curr_max, csd->vdd_w_curr_min, 
+                     csd->vdd_w_curr_max, csd->c_size_mult,
+                     csd->wp_grp_size, csd->wp_grp_enable,
+                     csd->default_ecc, csd->r2w_factor, 
+                     csd->write_bl_len, csd->write_bl_partial,
+                     csd->file_format_grp, csd->copy, 
+                     csd->perm_write_protect, csd->tmp_write_protect,
+                     csd->file_format, csd->ecc);
+               switch (csd->csd_structure) {
+               case CSD_STRUCT_VER_1_0:
+               case CSD_STRUCT_VER_1_1:
+                       DEBUG(2," V22 sector_size=%d erase_grp_size=%d\n", 
+                             csd->erase.v22.sector_size, 
+                             csd->erase.v22.erase_grp_size);
+                       break;
+               case CSD_STRUCT_VER_1_2:
+               default:
+                       DEBUG(2," V31 erase_grp_size=%d erase_grp_mult=%d\n", 
+                             csd->erase.v31.erase_grp_size,
+                             csd->erase.v31.erase_grp_mult);
+                       break;
+               }
+       }
+
+       if (buf[0] != 0x3f)  return MMC_ERROR_HEADER_MISMATCH;
+
+       return 0;
+}
+
+int mmc_unpack_r1(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state)
+{
+       u8 *buf = request->response;
+
+       if (request->result)        return request->result;
+
+       r1->cmd    = buf[0];
+       r1->status = PARSE_U32(buf,1);
+
+       DEBUG(2, "mmc_unpack_r1: cmd=%d status=%08x\n", r1->cmd, r1->status);
+
+       if (R1_STATUS(r1->status)) {
+               if (r1->status & R1_OUT_OF_RANGE)       return MMC_ERROR_OUT_OF_RANGE;
+               if (r1->status & R1_ADDRESS_ERROR)      return MMC_ERROR_ADDRESS;
+               if (r1->status & R1_BLOCK_LEN_ERROR)    return MMC_ERROR_BLOCK_LEN;
+               if (r1->status & R1_ERASE_SEQ_ERROR)    return MMC_ERROR_ERASE_SEQ;
+               if (r1->status & R1_ERASE_PARAM)        return MMC_ERROR_ERASE_PARAM;
+               if (r1->status & R1_WP_VIOLATION)       return MMC_ERROR_WP_VIOLATION;
+               /*if (r1->status & R1_CARD_IS_LOCKED)     return MMC_ERROR_CARD_IS_LOCKED; */
+               if (r1->status & R1_LOCK_UNLOCK_FAILED) return MMC_ERROR_LOCK_UNLOCK_FAILED;
+               if (r1->status & R1_COM_CRC_ERROR)      return MMC_ERROR_COM_CRC;
+               if (r1->status & R1_ILLEGAL_COMMAND)    return MMC_ERROR_ILLEGAL_COMMAND;
+               if (r1->status & R1_CARD_ECC_FAILED)    return MMC_ERROR_CARD_ECC_FAILED;
+               if (r1->status & R1_CC_ERROR)           return MMC_ERROR_CC;
+               if (r1->status & R1_ERROR)              return MMC_ERROR_GENERAL;
+               if (r1->status & R1_UNDERRUN)           return MMC_ERROR_UNDERRUN;
+               if (r1->status & R1_OVERRUN)            return MMC_ERROR_OVERRUN;
+               if (r1->status & R1_CID_CSD_OVERWRITE)  return MMC_ERROR_CID_CSD_OVERWRITE;
+       }
+
+       if (buf[0] != request->cmd) return MMC_ERROR_HEADER_MISMATCH;
+
+       /* This should be last - it's the least dangerous error */
+
+       return 0;
+}
+
+int mmc_unpack_scr(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state, u32 *scr)
+{
+        u8 *buf = request->response;
+       if (request->result)        return request->result;
+
+        *scr = PARSE_U32(buf, 5); /* Save SCR returned by the SD Card */
+        return mmc_unpack_r1(request, r1, state);
+
+}
+
+int mmc_unpack_r6(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state, int *rca)
+{
+       u8 *buf = request->response;
+
+       if (request->result)        return request->result;
+
+        *rca = PARSE_U16(buf,1);  /* Save RCA returned by the SD Card */
+
+        *(buf+1) = 0;
+        *(buf+2) = 0;
+
+        return mmc_unpack_r1(request, r1, state);
+}
+
+int mmc_unpack_cid(struct mmc_request *request, struct mmc_cid *cid)
+{
+       u8 *buf = request->response;
+       int i;
+
+       if (request->result) return request->result;
+
+       cid->mid = buf[1];
+       cid->oid = PARSE_U16(buf,2);
+       for (i = 0 ; i < 6 ; i++)
+               cid->pnm[i] = buf[4+i];
+       cid->pnm[6] = 0;
+       cid->prv = buf[10];
+       cid->psn = PARSE_U32(buf,11);
+       cid->mdt = buf[15];
+
+       DEBUG(2,"mmc_unpack_cid: mid=%d oid=%d pnm=%s prv=%d.%d psn=%08x mdt=%d/%d\n",
+             cid->mid, cid->oid, cid->pnm, 
+             (cid->prv>>4), (cid->prv&0xf), 
+             cid->psn, (cid->mdt>>4), (cid->mdt&0xf)+1997);
+
+       if (buf[0] != 0x3f)  return MMC_ERROR_HEADER_MISMATCH;
+       return 0;
+}
+
+int mmc_unpack_r3(struct mmc_request *request, struct mmc_response_r3 *r3)
+{
+       u8 *buf = request->response;
+
+       if (request->result) return request->result;
+
+       r3->ocr = PARSE_U32(buf,1);
+       DEBUG(2,"mmc_unpack_r3: ocr=%08x\n", r3->ocr);
+
+       if (buf[0] != 0x3f)  return MMC_ERROR_HEADER_MISMATCH;
+       return 0;
+}
+
+#define KBPS 1
+#define MBPS 1000
+
+static u32 ts_exp[] = { 100*KBPS, 1*MBPS, 10*MBPS, 100*MBPS, 0, 0, 0, 0 };
+static u32 ts_mul[] = { 0,    1000, 1200, 1300, 1500, 2000, 2500, 3000, 
+                       3500, 4000, 4500, 5000, 5500, 6000, 7000, 8000 };
+
+u32 mmc_tran_speed(u8 ts)
+{
+       u32 rate = ts_exp[(ts & 0x7)] * ts_mul[(ts & 0x78) >> 3];
+
+       if (rate <= 0) {
+               DEBUG(0, "mmc_tran_speed: error - unrecognized speed 0x%02x\n", ts);
+               return 1;
+       }
+
+       return rate;
+}
+
+void mmc_send_cmd(struct mmc_request *request, int cmd, u32 arg, 
+                  u16 nob, u16 block_len, enum mmc_rsp_t rtype, u8 *buffer)
+{
+       request->cmd       = cmd;
+       request->arg       = arg;
+       request->rtype     = rtype;
+       request->nob       = nob;
+       request->block_len = block_len;
+       request->buffer    = buffer;
+       request->cnt       = nob * block_len;
+
+       jz_mmc_exec_cmd(request);
+}
+
+#endif /* CONFIG_MMC */
+#endif  /* CONFIG_JZ4740 */
diff --git a/package/uboot-xburst/files/cpu/mips/jz_mmc.h b/package/uboot-xburst/files/cpu/mips/jz_mmc.h
new file mode 100644 (file)
index 0000000..0c7b70f
--- /dev/null
@@ -0,0 +1,113 @@
+/*
+ *  linux/drivers/mmc/jz_mmc.h
+ *
+ *  Author: Vladimir Shebordaev, Igor Oblakov
+ *  Copyright:  MontaVista Software Inc.
+ *
+ *  $Id: jz_mmc.h,v 1.3 2007-06-15 08:04:20 jlwei Exp $
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef __MMC_JZMMC_H__
+#define __MMC_JZMMC_H__
+
+#include "mmc_protocol.h"
+
+#define MMC_DEBUG_LEVEL                0               /* Enable Debug: 0 - no debug */
+
+#define MMC_BLOCK_SIZE         512             /* MMC/SD Block Size */
+
+#define ID_TO_RCA(x) ((x)+1)
+
+#define MMC_OCR_ARG            0x00ff8000      /* Argument of OCR */
+
+enum mmc_result_t {
+       MMC_NO_RESPONSE        = -1,
+       MMC_NO_ERROR           = 0,
+       MMC_ERROR_OUT_OF_RANGE,
+       MMC_ERROR_ADDRESS,
+       MMC_ERROR_BLOCK_LEN,
+       MMC_ERROR_ERASE_SEQ,
+       MMC_ERROR_ERASE_PARAM,
+       MMC_ERROR_WP_VIOLATION,
+       MMC_ERROR_CARD_IS_LOCKED,
+       MMC_ERROR_LOCK_UNLOCK_FAILED,
+       MMC_ERROR_COM_CRC,
+       MMC_ERROR_ILLEGAL_COMMAND,
+       MMC_ERROR_CARD_ECC_FAILED,
+       MMC_ERROR_CC,
+       MMC_ERROR_GENERAL,
+       MMC_ERROR_UNDERRUN,
+       MMC_ERROR_OVERRUN,
+       MMC_ERROR_CID_CSD_OVERWRITE,
+       MMC_ERROR_STATE_MISMATCH,
+       MMC_ERROR_HEADER_MISMATCH,
+       MMC_ERROR_TIMEOUT,
+       MMC_ERROR_CRC,
+       MMC_ERROR_DRIVER_FAILURE,
+};
+
+/* the information structure of MMC/SD Card */
+typedef struct MMC_INFO
+{
+       int             id;     /* Card index */
+        int             sd;     /* MMC or SD card */
+        int             rca;    /* RCA */
+        u32             scr;    /* SCR 63:32*/
+       int             flags;  /* Ejected, inserted */
+       enum card_state state;  /* empty, ident, ready, whatever */
+
+       /* Card specific information */
+       struct mmc_cid  cid;
+       struct mmc_csd  csd;
+       u32             block_num;
+       u32             block_len;
+       u32             erase_unit;
+} mmc_info;
+
+mmc_info mmcinfo;
+
+struct mmc_request {
+       int               index;      /* Slot index - used for CS lines */
+       int               cmd;        /* Command to send */
+       u32               arg;        /* Argument to send */
+       enum mmc_rsp_t    rtype;      /* Response type expected */
+
+       /* Data transfer (these may be modified at the low level) */
+       u16               nob;        /* Number of blocks to transfer*/
+       u16               block_len;  /* Block length */
+       u8               *buffer;     /* Data buffer */
+       u32               cnt;        /* Data length, for PIO */
+
+       /* Results */
+       u8                response[18]; /* Buffer to store response - CRC is optional */
+       enum mmc_result_t result;
+};
+
+char * mmc_result_to_string(int);
+int    mmc_unpack_csd(struct mmc_request *request, struct mmc_csd *csd);
+int    mmc_unpack_r1(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state);
+int    mmc_unpack_r6(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state, int *rca);
+int    mmc_unpack_scr(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state, u32 *scr);
+int    mmc_unpack_cid(struct mmc_request *request, struct mmc_cid *cid);
+int    mmc_unpack_r3(struct mmc_request *request, struct mmc_response_r3 *r3);
+
+void   mmc_send_cmd(struct mmc_request *request, int cmd, u32 arg, 
+                    u16 nob, u16 block_len, enum mmc_rsp_t rtype, u8 *buffer);
+u32    mmc_tran_speed(u8 ts);
+void   jz_mmc_set_clock(int sd, u32 rate);
+void   jz_mmc_hardware_init(void);
+
+static inline void mmc_simple_cmd(struct mmc_request *request, int cmd, u32 arg, enum mmc_rsp_t rtype)
+{
+       mmc_send_cmd( request, cmd, arg, 0, 0, rtype, 0);
+}
+
+int mmc_legacy_init(int verbose);
+int mmc_read(ulong src, uchar *dst, int size);
+int mmc_write(uchar *src, ulong dst, int size);
+int mmc2info(ulong addr);
+
+#endif /* __MMC_JZMMC_H__ */
diff --git a/package/uboot-xburst/files/cpu/mips/jz_serial.c b/package/uboot-xburst/files/cpu/mips/jz_serial.c
new file mode 100644 (file)
index 0000000..e9a18a1
--- /dev/null
@@ -0,0 +1,141 @@
+/*
+ * Jz47xx UART support
+ *
+ * Hardcoded to UART 0 for now
+ * Options also hardcoded to 8N1
+ *
+ *  Copyright (c) 2005
+ *  Ingenic Semiconductor, <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+#if defined(CONFIG_JZ4740)
+
+#include <common.h>
+
+#include <asm/jz4740.h>
+
+#undef UART_BASE
+#ifndef CONFIG_SYS_UART_BASE
+#define UART_BASE  UART0_BASE
+#else
+#define UART_BASE  CONFIG_SYS_UART_BASE
+#endif
+
+/******************************************************************************
+*
+* serial_init - initialize a channel
+*
+* This routine initializes the number of data bits, parity
+* and set the selected baud rate. Interrupts are disabled.
+* Set the modem control signals if the option is selected.
+*
+* RETURNS: N/A
+*/
+
+int serial_init (void)
+{
+#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+       volatile u8 *uart_fcr = (volatile u8 *)(UART_BASE + OFF_FCR);
+       volatile u8 *uart_lcr = (volatile u8 *)(UART_BASE + OFF_LCR);
+       volatile u8 *uart_ier = (volatile u8 *)(UART_BASE + OFF_IER);
+       volatile u8 *uart_sircr = (volatile u8 *)(UART_BASE + OFF_SIRCR);
+
+       /* Disable port interrupts while changing hardware */
+       *uart_ier = 0;
+
+       /* Disable UART unit function */
+       *uart_fcr = ~UART_FCR_UUE;
+
+       /* Set both receiver and transmitter in UART mode (not SIR) */
+       *uart_sircr = ~(SIRCR_RSIRE | SIRCR_TSIRE);
+
+       /* Set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
+       *uart_lcr = UART_LCR_WLEN_8 | UART_LCR_STOP_1;
+
+       /* Set baud rate */
+       serial_setbrg();
+
+       /* Enable UART unit, enable and clear FIFO */
+       *uart_fcr = UART_FCR_UUE | UART_FCR_FE | UART_FCR_TFLS | UART_FCR_RFLS;
+#endif
+       return 0;
+}
+
+void serial_setbrg (void)
+{
+       volatile u8 *uart_lcr = (volatile u8 *)(UART_BASE + OFF_LCR);
+       volatile u8 *uart_dlhr = (volatile u8 *)(UART_BASE + OFF_DLHR);
+       volatile u8 *uart_dllr = (volatile u8 *)(UART_BASE + OFF_DLLR);
+       u32 baud_div, tmp;
+
+       baud_div = CONFIG_SYS_EXTAL / 16 / CONFIG_BAUDRATE;
+
+       tmp = *uart_lcr;
+       tmp |= UART_LCR_DLAB;
+       *uart_lcr = tmp;
+
+       *uart_dlhr = (baud_div >> 8) & 0xff;
+       *uart_dllr = baud_div & 0xff;
+
+       tmp &= ~UART_LCR_DLAB;
+       *uart_lcr = tmp;
+}
+
+void serial_putc (const char c)
+{
+       volatile u8 *uart_lsr = (volatile u8 *)(UART_BASE + OFF_LSR);
+       volatile u8 *uart_tdr = (volatile u8 *)(UART_BASE + OFF_TDR);
+
+       if (c == '\n') serial_putc ('\r');
+
+       /* Wait for fifo to shift out some bytes */
+       while ( !((*uart_lsr & (UART_LSR_TDRQ | UART_LSR_TEMT)) == 0x60) );
+
+       *uart_tdr = (u8)c;
+}
+
+void serial_puts (const char *s)
+{
+       while (*s) {
+               serial_putc (*s++);
+       }
+}
+
+int serial_getc (void)
+{
+       volatile u8 *uart_rdr = (volatile u8 *)(UART_BASE + OFF_RDR);
+
+       while (!serial_tstc());
+
+       return *uart_rdr;
+}
+
+int serial_tstc (void)
+{
+       volatile u8 *uart_lsr = (volatile u8 *)(UART_BASE + OFF_LSR);
+
+       if (*uart_lsr & UART_LSR_DR) {
+               /* Data in rfifo */
+               return (1);
+       }
+       return 0;
+}
+
+#endif
diff --git a/package/uboot-xburst/files/cpu/mips/mmc_protocol.h b/package/uboot-xburst/files/cpu/mips/mmc_protocol.h
new file mode 100644 (file)
index 0000000..ebd5912
--- /dev/null
@@ -0,0 +1,273 @@
+/*
+**********************************************************************
+*
+*                            uC/MMC
+*
+*             (c) Copyright 2005 - 2007, Ingenic Semiconductor, Inc
+*                      All rights reserved.
+*
+***********************************************************************
+
+----------------------------------------------------------------------
+File        : mmc_protocol.h
+Purpose     : MMC protocol definitions.
+
+----------------------------------------------------------------------
+Version-Date-----Author-Explanation
+----------------------------------------------------------------------
+1.00.00 20060831 WeiJianli     First release
+
+----------------------------------------------------------------------
+Known problems or limitations with current version
+----------------------------------------------------------------------
+(none)
+---------------------------END-OF-HEADER------------------------------
+*/
+
+#ifndef __MMC_PROTOCOL__
+#define __MMC_PROTOCOL__
+
+/* Standard MMC/SD clock speeds */
+#define MMC_CLOCK_SLOW    400000      /* 400 kHz for initial setup */
+#define MMC_CLOCK_FAST  20000000      /* 20 MHz for maximum for normal operation */
+#define SD_CLOCK_FAST   24000000      /* 24 MHz for SD Cards */
+/* Extra MMC commands for state control */
+/* Use negative numbers to disambiguate */
+#define MMC_CIM_RESET            -1
+
+/* Standard MMC commands (3.1)           type  argument     response */
+   /* class 1 */
+#define        MMC_GO_IDLE_STATE         0   /* bc                          */
+#define MMC_SEND_OP_COND          1   /* bcr  [31:0] OCR         R3  */
+#define MMC_ALL_SEND_CID          2   /* bcr                     R2  */
+#define MMC_SET_RELATIVE_ADDR     3   /* ac   [31:16] RCA        R1  */
+#define MMC_SET_DSR               4   /* bc   [31:16] RCA            */
+#define MMC_SELECT_CARD           7   /* ac   [31:16] RCA        R1  */
+#define MMC_SEND_CSD              9   /* ac   [31:16] RCA        R2  */
+#define MMC_SEND_CID             10   /* ac   [31:16] RCA        R2  */
+#define MMC_READ_DAT_UNTIL_STOP  11   /* adtc [31:0] dadr        R1  */
+#define MMC_STOP_TRANSMISSION    12   /* ac                      R1b */
+#define MMC_SEND_STATUS                 13   /* ac   [31:16] RCA        R1  */
+#define MMC_GO_INACTIVE_STATE    15   /* ac   [31:16] RCA            */
+
+  /* class 2 */
+#define MMC_SET_BLOCKLEN         16   /* ac   [31:0] block len   R1  */
+#define MMC_READ_SINGLE_BLOCK    17   /* adtc [31:0] data addr   R1  */
+#define MMC_READ_MULTIPLE_BLOCK  18   /* adtc [31:0] data addr   R1  */
+
+  /* class 3 */
+#define MMC_WRITE_DAT_UNTIL_STOP 20   /* adtc [31:0] data addr   R1  */
+
+  /* class 4 */
+#define MMC_SET_BLOCK_COUNT      23   /* adtc [31:0] data addr   R1  */
+#define MMC_WRITE_BLOCK          24   /* adtc [31:0] data addr   R1  */
+#define MMC_WRITE_MULTIPLE_BLOCK 25   /* adtc                    R1  */
+#define MMC_PROGRAM_CID          26   /* adtc                    R1  */
+#define MMC_PROGRAM_CSD          27   /* adtc                    R1  */
+
+  /* class 6 */
+#define MMC_SET_WRITE_PROT       28   /* ac   [31:0] data addr   R1b */
+#define MMC_CLR_WRITE_PROT       29   /* ac   [31:0] data addr   R1b */
+#define MMC_SEND_WRITE_PROT      30   /* adtc [31:0] wpdata addr R1  */
+
+  /* class 5 */
+#define MMC_ERASE_GROUP_START    35   /* ac   [31:0] data addr   R1  */
+#define MMC_ERASE_GROUP_END      36   /* ac   [31:0] data addr   R1  */
+#define MMC_ERASE                37   /* ac                      R1b */
+
+  /* class 9 */
+#define MMC_FAST_IO              39   /* ac   <Complex>          R4  */
+#define MMC_GO_IRQ_STATE         40   /* bcr                     R5  */
+
+  /* class 7 */
+#define MMC_LOCK_UNLOCK          42   /* adtc                    R1b */
+
+  /* class 8 */
+#define MMC_APP_CMD              55   /* ac   [31:16] RCA        R1  */
+#define MMC_GEN_CMD              56   /* adtc [0] RD/WR          R1b */
+
+  /* SD class */
+#define SD_SEND_OP_COND          41   /* bcr  [31:0] OCR         R3  */
+#define SET_BUS_WIDTH            6    /* ac   [1:0] bus width    R1  */
+#define SEND_SCR                 51   /* adtc [31:0] staff       R1  */
+
+/* Don't change the order of these; they are used in dispatch tables */
+enum mmc_rsp_t {
+       RESPONSE_NONE   = 0,
+       RESPONSE_R1     = 1,
+       RESPONSE_R1B    = 2,
+       RESPONSE_R2_CID = 3,
+       RESPONSE_R2_CSD  = 4,
+       RESPONSE_R3      = 5,
+       RESPONSE_R4      = 6,
+       RESPONSE_R5      = 7,
+        RESPONSE_R6      = 8,
+};
+
+
+/*
+  MMC status in R1
+  Type
+       e : error bit
+       s : status bit
+       r : detected and set for the actual command response
+       x : detected and set during command execution. the host must poll
+            the card by sending status command in order to read these bits.
+  Clear condition
+       a : according to the card state
+       b : always related to the previous command. Reception of
+            a valid command will clear it (with a delay of one command)
+       c : clear by read
+ */
+
+#define R1_OUT_OF_RANGE                (1 << 31)       /* er, c */
+#define R1_ADDRESS_ERROR       (1 << 30)       /* erx, c */
+#define R1_BLOCK_LEN_ERROR     (1 << 29)       /* er, c */
+#define R1_ERASE_SEQ_ERROR      (1 << 28)      /* er, c */
+#define R1_ERASE_PARAM         (1 << 27)       /* ex, c */
+#define R1_WP_VIOLATION                (1 << 26)       /* erx, c */
+#define R1_CARD_IS_LOCKED      (1 << 25)       /* sx, a */
+#define R1_LOCK_UNLOCK_FAILED  (1 << 24)       /* erx, c */
+#define R1_COM_CRC_ERROR       (1 << 23)       /* er, b */
+#define R1_ILLEGAL_COMMAND     (1 << 22)       /* er, b */
+#define R1_CARD_ECC_FAILED     (1 << 21)       /* ex, c */
+#define R1_CC_ERROR            (1 << 20)       /* erx, c */
+#define R1_ERROR               (1 << 19)       /* erx, c */
+#define R1_UNDERRUN            (1 << 18)       /* ex, c */
+#define R1_OVERRUN             (1 << 17)       /* ex, c */
+#define R1_CID_CSD_OVERWRITE   (1 << 16)       /* erx, c, CID/CSD overwrite */
+#define R1_WP_ERASE_SKIP       (1 << 15)       /* sx, c */
+#define R1_CARD_ECC_DISABLED   (1 << 14)       /* sx, a */
+#define R1_ERASE_RESET         (1 << 13)       /* sr, c */
+#define R1_STATUS(x)            (x & 0xFFFFE000)
+#define R1_CURRENT_STATE(x)            ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */
+#define R1_READY_FOR_DATA      (1 << 8)        /* sx, a */
+#define R1_APP_CMD             (1 << 7)        /* sr, c */
+
+enum card_state {
+       CARD_STATE_EMPTY = -1,
+       CARD_STATE_IDLE  = 0,
+       CARD_STATE_READY = 1,
+       CARD_STATE_IDENT = 2,
+       CARD_STATE_STBY  = 3,
+       CARD_STATE_TRAN  = 4,
+       CARD_STATE_DATA  = 5,
+       CARD_STATE_RCV   = 6,
+       CARD_STATE_PRG   = 7,
+       CARD_STATE_DIS   = 8,
+};
+
+/* These are unpacked versions of the actual responses */
+
+ struct mmc_response_r1 {
+       u8  cmd;
+       u32 status;
+};
+
+typedef struct mmc_cid {
+       u8  mid;
+       u16 oid;
+       u8  pnm[7];   /* Product name (we null-terminate) */
+       u8  prv;
+       u32 psn;
+       u8  mdt;
+}mmc_cid_t;
+
+typedef struct mmc_csd {
+       u8  csd_structure;
+       u8  spec_vers;
+       u8  taac;
+       u8  nsac;
+       u8  tran_speed;
+       u16 ccc;
+       u8  read_bl_len;
+       u8  read_bl_partial;
+       u8  write_blk_misalign;
+       u8  read_blk_misalign;
+       u8  dsr_imp;
+       u16 c_size;
+       u8  vdd_r_curr_min;
+       u8  vdd_r_curr_max;
+       u8  vdd_w_curr_min;
+       u8  vdd_w_curr_max;
+       u8  c_size_mult;
+       union {
+               struct { /* MMC system specification version 3.1 */
+                       u8  erase_grp_size;
+                       u8  erase_grp_mult;
+               } v31;
+               struct { /* MMC system specification version 2.2 */
+                       u8  sector_size;
+                       u8  erase_grp_size;
+               } v22;
+       } erase;
+       u8  wp_grp_size;
+       u8  wp_grp_enable;
+       u8  default_ecc;
+       u8  r2w_factor;
+       u8  write_bl_len;
+       u8  write_bl_partial;
+       u8  file_format_grp;
+       u8  copy;
+       u8  perm_write_protect;
+       u8  tmp_write_protect;
+       u8  file_format;
+       u8  ecc;
+}mmc_csd_t;;
+
+struct mmc_response_r3 {
+       u32 ocr;
+};
+
+#define MMC_VDD_145_150        0x00000001      /* VDD voltage 1.45 - 1.50 */
+#define MMC_VDD_150_155        0x00000002      /* VDD voltage 1.50 - 1.55 */
+#define MMC_VDD_155_160        0x00000004      /* VDD voltage 1.55 - 1.60 */
+#define MMC_VDD_160_165        0x00000008      /* VDD voltage 1.60 - 1.65 */
+#define MMC_VDD_165_170        0x00000010      /* VDD voltage 1.65 - 1.70 */
+#define MMC_VDD_17_18  0x00000020      /* VDD voltage 1.7 - 1.8 */
+#define MMC_VDD_18_19  0x00000040      /* VDD voltage 1.8 - 1.9 */
+#define MMC_VDD_19_20  0x00000080      /* VDD voltage 1.9 - 2.0 */
+#define MMC_VDD_20_21  0x00000100      /* VDD voltage 2.0 ~ 2.1 */
+#define MMC_VDD_21_22  0x00000200      /* VDD voltage 2.1 ~ 2.2 */
+#define MMC_VDD_22_23  0x00000400      /* VDD voltage 2.2 ~ 2.3 */
+#define MMC_VDD_23_24  0x00000800      /* VDD voltage 2.3 ~ 2.4 */
+#define MMC_VDD_24_25  0x00001000      /* VDD voltage 2.4 ~ 2.5 */
+#define MMC_VDD_25_26  0x00002000      /* VDD voltage 2.5 ~ 2.6 */
+#define MMC_VDD_26_27  0x00004000      /* VDD voltage 2.6 ~ 2.7 */
+#define MMC_VDD_27_28  0x00008000      /* VDD voltage 2.7 ~ 2.8 */
+#define MMC_VDD_28_29  0x00010000      /* VDD voltage 2.8 ~ 2.9 */
+#define MMC_VDD_29_30  0x00020000      /* VDD voltage 2.9 ~ 3.0 */
+#define MMC_VDD_30_31  0x00040000      /* VDD voltage 3.0 ~ 3.1 */
+#define MMC_VDD_31_32  0x00080000      /* VDD voltage 3.1 ~ 3.2 */
+#define MMC_VDD_32_33  0x00100000      /* VDD voltage 3.2 ~ 3.3 */
+#define MMC_VDD_33_34  0x00200000      /* VDD voltage 3.3 ~ 3.4 */
+#define MMC_VDD_34_35  0x00400000      /* VDD voltage 3.4 ~ 3.5 */
+#define MMC_VDD_35_36  0x00800000      /* VDD voltage 3.5 ~ 3.6 */
+#define MMC_CARD_BUSY  0x80000000      /* Card Power up status bit */
+
+
+/* CSD field definitions */
+
+#define CSD_STRUCT_VER_1_0  0           /* Valid for system specification 1.0 - 1.2 */
+#define CSD_STRUCT_VER_1_1  1           /* Valid for system specification 1.4 - 2.2 */
+#define CSD_STRUCT_VER_1_2  2           /* Valid for system specification 3.1       */
+
+#define CSD_SPEC_VER_0      0           /* Implements system specification 1.0 - 1.2 */
+#define CSD_SPEC_VER_1      1           /* Implements system specification 1.4 */
+#define CSD_SPEC_VER_2      2           /* Implements system specification 2.0 - 2.2 */
+#define CSD_SPEC_VER_3      3           /* Implements system specification 3.1 */
+
+#if MMC_DEBUG_LEVEL
+
+#define DEBUG(n, args...)                      \
+    do {    \
+       if (n <=  MMC_DEBUG_LEVEL) {    \
+               printf(args);   \
+       }    \
+    } while(0)
+#else
+#define DEBUG(n, args...)
+#endif /* MMC_DEBUG_EN */
+
+#endif  /* __MMC_PROTOCOL__ */
diff --git a/package/uboot-xburst/files/cpu/mips/nanonote_gpm940b0.c b/package/uboot-xburst/files/cpu/mips/nanonote_gpm940b0.c
new file mode 100644 (file)
index 0000000..4c98d29
--- /dev/null
@@ -0,0 +1,420 @@
+/*
+ * JzRISC lcd controller
+ *
+ * xiangfu liu <xiangfu.z@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <lcd.h>
+
+#include <asm/io.h>               /* virt_to_phys() */
+
+#include <asm/jz4740.h>
+#include "nanonote_gpm940b0.h"
+
+#define align2(n) (n)=((((n)+1)>>1)<<1)
+#define align4(n) (n)=((((n)+3)>>2)<<2)
+#define align8(n) (n)=((((n)+7)>>3)<<3)
+
+struct jzfb_info {
+       unsigned int cfg;       /* panel mode and pin usage etc. */
+       unsigned int w;
+       unsigned int h;
+       unsigned int bpp;       /* bit per pixel */
+       unsigned int fclk;      /* frame clk */
+       unsigned int hsw;       /* hsync width, in pclk */
+       unsigned int vsw;       /* vsync width, in line count */
+       unsigned int elw;       /* end of line, in pclk */
+       unsigned int blw;       /* begin of line, in pclk */
+       unsigned int efw;       /* end of frame, in line count */
+       unsigned int bfw;       /* begin of frame, in line count */
+};
+
+static struct jzfb_info jzfb = {
+       MODE_8BIT_SERIAL_TFT | PCLK_N | HSYNC_N | VSYNC_N,
+       320, 240, 32, 70, 1, 1, 273, 140, 1, 20
+};
+
+vidinfo_t panel_info = {
+       320, 240, LCD_BPP,
+};
+
+int lcd_line_length;
+
+int lcd_color_fg;
+int lcd_color_bg;
+/*
+ * Frame buffer memory information
+ */
+void *lcd_base;                        /* Start of framebuffer memory  */
+void *lcd_console_address;     /* Start of console buffer      */
+
+short console_col;
+short console_row;
+
+void lcd_ctrl_init (void *lcdbase);
+void lcd_enable (void);
+void lcd_disable (void);
+
+static int  jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid);
+static void jz_lcd_desc_init(vidinfo_t *vid);
+static int  jz_lcd_hw_init( vidinfo_t *vid );
+extern int flush_cache_all(void);
+
+void lcd_ctrl_init (void *lcdbase)
+{
+       __lcd_display_pin_init();
+
+       jz_lcd_init_mem(lcdbase, &panel_info);
+       jz_lcd_desc_init(&panel_info);
+       jz_lcd_hw_init(&panel_info);
+
+       __lcd_display_on() ;
+}
+
+/*
+ * Before enabled lcd controller, lcd registers should be configured correctly.
+ */
+
+void lcd_enable (void)
+{
+       REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */
+       REG_LCD_CTRL |= 1<<3;    /* LCDCTRL.ENA*/
+}
+
+void lcd_disable (void)
+{
+       REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */
+       /* REG_LCD_CTRL |= (1<<3); */  /* LCDCTRL.DIS, quikly disable */
+}
+
+static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
+{
+       u_long palette_mem_size;
+       struct jz_fb_info *fbi = &vid->jz_fb;
+       int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
+
+       fbi->screen = (u_long)lcdbase;
+       fbi->palette_size = 256;
+       palette_mem_size = fbi->palette_size * sizeof(u16);
+
+       debug("jz_lcd.c palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
+       /* locate palette and descs at end of page following fb */
+       fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
+
+       return 0;
+}
+
+static void jz_lcd_desc_init(vidinfo_t *vid)
+{
+       struct jz_fb_info * fbi;
+       fbi = &vid->jz_fb;
+       fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
+       fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
+       fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
+
+       #define BYTES_PER_PANEL  (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8)
+
+       /* populate descriptors */
+       fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow);
+       fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + BYTES_PER_PANEL));
+       fbi->dmadesc_fblow->fidr  = 0;
+       fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL / 4 ;
+
+       fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */
+
+       fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen);
+       fbi->dmadesc_fbhigh->fidr = 0;
+       fbi->dmadesc_fbhigh->ldcmd =  BYTES_PER_PANEL / 4; /* length in word */
+
+       fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette);
+       fbi->dmadesc_palette->fidr  = 0;
+       fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28);
+
+       if(NBITS(vid->vl_bpix) < 12)
+       {
+               /* assume any mode with <12 bpp is palette driven */
+               fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh);
+               fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette);
+               /* flips back and forth between pal and fbhigh */
+               fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette);
+       } else {
+               /* palette shouldn't be loaded in true-color mode */
+               fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh);
+               fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */
+       }
+
+       flush_cache_all();
+}
+
+static int  jz_lcd_hw_init(vidinfo_t *vid)
+{
+       struct jz_fb_info *fbi = &vid->jz_fb;
+       unsigned int val = 0;
+       unsigned int pclk;
+       unsigned int stnH;
+       int pll_div;
+
+       /* Setting Control register */
+       switch (jzfb.bpp) {
+       case 1:
+               val |= LCD_CTRL_BPP_1;
+               break;
+       case 2:
+               val |= LCD_CTRL_BPP_2;
+               break;
+       case 4:
+               val |= LCD_CTRL_BPP_4;
+               break;
+       case 8:
+               val |= LCD_CTRL_BPP_8;
+               break;
+       case 15:
+               val |= LCD_CTRL_RGB555;
+       case 16:
+               val |= LCD_CTRL_BPP_16;
+               break;
+       case 17 ... 32:
+               val |= LCD_CTRL_BPP_18_24;      /* target is 4bytes/pixel */
+               break;
+
+       default:
+               printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp);
+               val |= LCD_CTRL_BPP_16;
+               break;
+       }
+
+       switch (jzfb.cfg & MODE_MASK) {
+       case MODE_STN_MONO_DUAL:
+       case MODE_STN_COLOR_DUAL:
+       case MODE_STN_MONO_SINGLE:
+       case MODE_STN_COLOR_SINGLE:
+               switch (jzfb.bpp) {
+               case 1:
+                       /* val |= LCD_CTRL_PEDN; */
+               case 2:
+                       val |= LCD_CTRL_FRC_2;
+                       break;
+               case 4:
+                       val |= LCD_CTRL_FRC_4;
+                       break;
+               case 8:
+               default:
+                       val |= LCD_CTRL_FRC_16;
+                       break;
+               }
+               break;
+       }
+
+       val |= LCD_CTRL_BST_16;         /* Burst Length is 16WORD=64Byte */
+       val |= LCD_CTRL_OFUP;           /* OutFIFO underrun protect */
+
+       switch (jzfb.cfg & MODE_MASK) {
+       case MODE_STN_MONO_DUAL:
+       case MODE_STN_COLOR_DUAL:
+       case MODE_STN_MONO_SINGLE:
+       case MODE_STN_COLOR_SINGLE:
+               switch (jzfb.cfg & STN_DAT_PINMASK) {
+               case STN_DAT_PIN1:
+                       /* Do not adjust the hori-param value. */
+                       break;
+               case STN_DAT_PIN2:
+                       align2(jzfb.hsw);
+                       align2(jzfb.elw);
+                       align2(jzfb.blw);
+                       break;
+               case STN_DAT_PIN4:
+                       align4(jzfb.hsw);
+                       align4(jzfb.elw);
+                       align4(jzfb.blw);
+                       break;
+               case STN_DAT_PIN8:
+                       align8(jzfb.hsw);
+                       align8(jzfb.elw);
+                       align8(jzfb.blw);
+                       break;
+               }
+               break;
+       }
+
+       REG_LCD_CTRL = val;
+
+       switch (jzfb.cfg & MODE_MASK) {
+       case MODE_STN_MONO_DUAL:
+       case MODE_STN_COLOR_DUAL:
+       case MODE_STN_MONO_SINGLE:
+       case MODE_STN_COLOR_SINGLE:
+               if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) ||
+                   ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
+                       stnH = jzfb.h >> 1;
+               else
+                       stnH = jzfb.h;
+
+               REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
+               REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw);
+
+               /* Screen setting */
+               REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw);
+               REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w);
+               REG_LCD_DAV = (0 << 16) | (stnH);
+
+               /* AC BIAs signal */
+               REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw);
+
+               break;
+
+       case MODE_TFT_GEN:
+       case MODE_TFT_SHARP:
+       case MODE_TFT_CASIO:
+       case MODE_TFT_SAMSUNG:
+       case MODE_8BIT_SERIAL_TFT:
+       case MODE_TFT_18BIT:
+               REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
+               REG_LCD_HSYNC = (0 << 16) | jzfb.hsw;
+               REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h);
+               REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w );
+               REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \
+                       | (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw);
+               break;
+       }
+
+       switch (jzfb.cfg & MODE_MASK) {
+       case MODE_TFT_SAMSUNG:
+       {
+               unsigned int total, tp_s, tp_e, ckv_s, ckv_e;
+               unsigned int rev_s, rev_e, inv_s, inv_e;
+
+               pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
+                       (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
+
+               total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
+               tp_s = jzfb.blw + jzfb.w + 1;
+               tp_e = tp_s + 1;
+               /* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */
+               ckv_s = tp_s - pclk/(1000000000/4100);
+               ckv_e = tp_s + total;
+               rev_s = tp_s - 11;      /* -11.5 clk */
+               rev_e = rev_s + total;
+               inv_s = tp_s;
+               inv_e = inv_s + total;
+               REG_LCD_CLS = (tp_s << 16) | tp_e;
+               REG_LCD_PS = (ckv_s << 16) | ckv_e;
+               REG_LCD_SPL = (rev_s << 16) | rev_e;
+               REG_LCD_REV = (inv_s << 16) | inv_e;
+               jzfb.cfg |= STFT_REVHI | STFT_SPLHI;
+               break;
+       }
+       case MODE_TFT_SHARP:
+       {
+               unsigned int total, cls_s, cls_e, ps_s, ps_e;
+               unsigned int spl_s, spl_e, rev_s, rev_e;
+               total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
+               spl_s = 1;
+               spl_e = spl_s + 1;
+               cls_s = 0;
+               cls_e = total - 60;     /* > 4us (pclk = 80ns) */
+               ps_s = cls_s;
+               ps_e = cls_e;
+               rev_s = total - 40;     /* > 3us (pclk = 80ns) */
+               rev_e = rev_s + total;
+               jzfb.cfg |= STFT_PSHI; 
+               REG_LCD_SPL = (spl_s << 16) | spl_e;
+               REG_LCD_CLS = (cls_s << 16) | cls_e;
+               REG_LCD_PS = (ps_s << 16) | ps_e;
+               REG_LCD_REV = (rev_s << 16) | rev_e;
+               break;
+       }
+       case MODE_TFT_CASIO:
+               break;
+       }
+
+       /* Configure the LCD panel */
+       REG_LCD_CFG = jzfb.cfg;
+
+       /* Timing setting */
+       __cpm_stop_lcd();
+
+       val = jzfb.fclk; /* frame clk */
+       if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) {
+               pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
+                       (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
+       } else {
+               /* serial mode: Hsync period = 3*Width_Pixel */
+               pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) *
+                       (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
+       }
+
+       if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
+           ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
+               pclk = (pclk * 3);
+
+       if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
+           ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
+           ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) ||
+           ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
+               pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4);
+
+       if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
+           ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
+               pclk >>= 1;
+
+       pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */
+       pll_div = pll_div ? 1 : 2 ;
+       val = ( __cpm_get_pllout()/pll_div ) / pclk;
+       val--;
+       if ( val > 0x1ff ) {
+               printf("CPM_LPCDR too large, set it to 0x1ff\n");
+               val = 0x1ff;
+       }
+       __cpm_set_pixdiv(val);
+
+       val = pclk * 3 ;        /* LCDClock > 2.5*Pixclock */
+       if ( val > 150000000 ) {
+               printf("Warning: LCDClock=%d\n, LCDClock must less or equal to 150MHz.\n", val);
+               printf("Change LCDClock to 150MHz\n");
+               val = 150000000;
+       }
+       val = ( __cpm_get_pllout()/pll_div ) / val;
+       val--;
+       if ( val > 0x1f ) {
+               printf("CPM_CPCCR.LDIV too large, set it to 0x1f\n");
+               val = 0x1f;
+       }
+       __cpm_set_ldiv( val );
+       REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */
+
+       __cpm_start_lcd();
+       udelay(1000);
+
+       REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/
+
+       if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
+           ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
+               REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/
+
+       return 0;
+}
+
+void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
+{
+}
+
+void lcd_initcolregs (void)
+{
+}
diff --git a/package/uboot-xburst/files/cpu/mips/nanonote_gpm940b0.h b/package/uboot-xburst/files/cpu/mips/nanonote_gpm940b0.h
new file mode 100644 (file)
index 0000000..932cee8
--- /dev/null
@@ -0,0 +1,231 @@
+/*
+ * JzRISC lcd controller
+ *
+ * xiangfu liu <xiangfu.z@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __QI_LB60_GPM940B0_H__
+#define __QI_LB60_GPM940B0_H__
+
+#include <asm/io.h>
+
+#define mdelay(n)      udelay((n)*1000)
+
+#define NR_PALETTE     256
+
+struct lcd_desc{
+       unsigned int next_desc; /* LCDDAx */
+       unsigned int databuf;   /* LCDSAx */
+       unsigned int frame_id;  /* LCDFIDx */ 
+       unsigned int cmd;       /* LCDCMDx */
+};
+
+#define MODE_MASK              0x0f
+#define MODE_TFT_GEN           0x00
+#define MODE_TFT_SHARP         0x01
+#define MODE_TFT_CASIO         0x02
+#define MODE_TFT_SAMSUNG       0x03
+#define MODE_CCIR656_NONINT    0x04
+#define MODE_CCIR656_INT       0x05
+#define MODE_STN_COLOR_SINGLE  0x08
+#define MODE_STN_MONO_SINGLE   0x09
+#define MODE_STN_COLOR_DUAL    0x0a
+#define MODE_STN_MONO_DUAL     0x0b
+#define MODE_8BIT_SERIAL_TFT    0x0c
+
+#define MODE_TFT_18BIT          (1<<7)
+
+#define STN_DAT_PIN1   (0x00 << 4)
+#define STN_DAT_PIN2   (0x01 << 4)
+#define STN_DAT_PIN4   (0x02 << 4)
+#define STN_DAT_PIN8   (0x03 << 4)
+#define STN_DAT_PINMASK        STN_DAT_PIN8
+
+#define STFT_PSHI      (1 << 15)
+#define STFT_CLSHI     (1 << 14)
+#define STFT_SPLHI     (1 << 13)
+#define STFT_REVHI     (1 << 12)
+
+#define SYNC_MASTER    (0 << 16)
+#define SYNC_SLAVE     (1 << 16)
+
+#define DE_P           (0 << 9)
+#define DE_N           (1 << 9)
+
+#define PCLK_P         (0 << 10)
+#define PCLK_N         (1 << 10)
+
+#define HSYNC_P                (0 << 11)
+#define HSYNC_N                (1 << 11)
+
+#define VSYNC_P                (0 << 8)
+#define VSYNC_N                (1 << 8)
+
+#define DATA_NORMAL    (0 << 17)
+#define DATA_INVERSE   (1 << 17)
+
+
+/* Jz LCDFB supported I/O controls. */
+#define FBIOSETBACKLIGHT       0x4688
+#define FBIODISPON             0x4689
+#define FBIODISPOFF            0x468a
+#define FBIORESET              0x468b
+#define FBIOPRINT_REG          0x468c
+
+/*
+ * LCD panel specific definition
+ */
+#define MODE   0xc9            /* 8bit serial RGB */
+#define SPEN   (32*2+21)       /*LCD_SPL */
+#define SPCK   (32*2+23)       /*LCD_CLS */
+#define SPDA   (32*2+22)       /*LCD_D12 */
+#define LCD_RET (32*3+27) 
+
+#define __spi_write_reg1(reg, val) \
+do { \
+       unsigned char no;\
+       unsigned short value;\
+       unsigned char a=0;\
+       unsigned char b=0;\
+       a=reg;\
+       b=val;\
+       __gpio_set_pin(SPEN);\
+       __gpio_set_pin(SPCK);\
+       __gpio_clear_pin(SPDA);\
+       __gpio_clear_pin(SPEN);\
+       udelay(25);\
+       value=((a<<8)|(b&0xFF));\
+       for(no=0;no<16;no++)\
+       {\
+               __gpio_clear_pin(SPCK);\
+               if((value&0x8000)==0x8000)\
+               __gpio_set_pin(SPDA);\
+               else\
+               __gpio_clear_pin(SPDA);\
+               udelay(25);\
+               __gpio_set_pin(SPCK);\
+               value=(value<<1); \
+               udelay(25);\
+        }\
+       __gpio_set_pin(SPEN);\
+       udelay(100);\
+} while (0)
+
+#define __spi_write_reg(reg, val) \
+do {\
+       __spi_write_reg1((reg<<2|2), val);\
+       udelay(100); \
+}while(0)
+
+#define __lcd_special_pin_init() \
+do { \
+       __gpio_as_output(SPEN); /* use SPDA */\
+       __gpio_as_output(SPCK); /* use SPCK */\
+       __gpio_as_output(SPDA); /* use SPDA */\
+       __gpio_as_output(LCD_RET);\
+} while (0)
+
+#define __lcd_special_on() \
+do { \
+       udelay(50);\
+       __spi_write_reg1(0x05, 0x16); \
+       __spi_write_reg1(0x04, 0x0b); \
+       __spi_write_reg1(0x07, 0x8d); \
+       __spi_write_reg1(0x01, 0x95); \
+       __spi_write_reg1(0x08, 0xc0); \
+       __spi_write_reg1(0x03, 0x40); \
+       __spi_write_reg1(0x06, 0x75); \
+       __spi_write_reg1(0x13, 0x01); \
+       __spi_write_reg1(0x05, 0x57); \
+} while (0)
+
+#define __lcd_special_off() \
+do {                                   \
+       __spi_write_reg1(0x05, 0x5e);   \
+} while (0)
+
+#define __lcd_display_pin_init() \
+do { \
+       __lcd_special_pin_init();\
+       __gpio_as_pwm();\
+       __lcd_set_backlight_level(8);\
+} while (0)
+
+#define __lcd_display_on() \
+do { \
+       __lcd_set_backlight_level(8); \
+       __lcd_special_on();\
+} while (0)
+
+#define __lcd_display_off() \
+do { \
+       __lcd_set_backlight_level(0); \
+       __lcd_special_off();\
+} while (0)
+
+#define __lcd_set_backlight_level(n)\
+do { \
+       __gpio_as_output(LCD_RET); \
+       __gpio_set_pin(LCD_RET); \
+} while (0)
+
+#if defined(CONFIG_SAKC)
+#define __lcd_close_backlight() \
+do { \
+       __gpio_as_output(GPIO_PWM); \
+       __gpio_clear_pin(GPIO_PWM); \
+} while (0)
+#endif
+
+#if defined(CONFIG_SAKC)
+#define __lcd_display_pin_init() \
+do { \
+       __cpm_start_tcu(); \
+       __lcd_special_pin_init(); \
+} while (0)
+
+#define __lcd_display_on() \
+do { \
+       __lcd_special_on(); \
+} while (0)
+
+#define __lcd_display_off() \
+do { \
+       __lcd_special_off(); \
+} while (0)
+#else
+#define __lcd_display_pin_init() \
+do { \
+       __cpm_start_tcu(); \
+       __lcd_special_pin_init(); \
+} while (0)
+
+#define __lcd_display_on() \
+do { \
+       __gpio_set_pin(GPIO_DISP_OFF_N); \
+       __lcd_special_on(); \
+} while (0)
+
+#define __lcd_display_off() \
+do { \
+       __lcd_special_off(); \
+       __gpio_clear_pin(GPIO_DISP_OFF_N); \
+} while (0)
+#endif
+
+#endif /* __QI_LB60_GPM940B0_H__ */
diff --git a/package/uboot-xburst/files/cpu/mips/usb_boot.S b/package/uboot-xburst/files/cpu/mips/usb_boot.S
new file mode 100644 (file)
index 0000000..107b928
--- /dev/null
@@ -0,0 +1,880 @@
+/*
+ *  for jz4740 usb boot
+ *
+ *  Copyright (c) 2009 Xiangfu Liu <xiangfu.z@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+    .set noreorder
+    .globl usb_boot
+    .text
+
+//----------------------------------------------------------------------
+// Both NAND and USB boot load data to D-Cache first, then transfer
+// data from D-Cache to I-Cache, and jump to execute the code in I-Cache.
+// So init caches first and then dispatch to a proper boot routine.
+//----------------------------------------------------------------------
+
+.macro load_addr reg addr
+       li \reg, 0x80000000
+       addiu \reg, \reg, \addr
+       la $2, usbboot_begin
+       subu \reg, \reg, $2
+.endm
+
+usb_boot:
+       //--------------------------------------------------------------
+       // Initialize PLL: set ICLK to 84MHz and HCLK to 42MHz.
+       //--------------------------------------------------------------
+       la      $9, 0xB0000000          // CPCCR: Clock Control Register
+       la      $8, 0x42041110          // I:S:M:P=1:2:2:2
+       sw      $8, 0($9)
+
+       la      $9, 0xB0000010          // CPPCR: PLL Control Register
+       la      $8, 0x06000120          // M=12 N=0 D=0 CLK=12*(M+2)/(N+2)
+       sw      $8, 0($9)
+
+       mtc0    $0, $26                 // CP0_ERRCTL, restore WST reset state
+       nop
+
+       mtc0    $0, $16                 // CP0_CONFIG
+       nop
+
+       // Relocate code to beginning of the ram
+
+       la $2, usbboot_begin
+       la $3, usbboot_end
+       li $4, 0x80000000
+
+1:
+       lw $5, 0($2)
+       sw $5, 0($4)
+       addiu $2, $2, 4
+       bne $2, $3, 1b
+       addiu $4, $4, 4
+
+       li $2, 0x80000000
+       ori $3, $2, 0
+       addiu $3, $3, usbboot_end
+       la $4, usbboot_begin
+       subu $3, $3, $4
+
+
+2:
+       cache   0x0, 0($2)              // Index_Invalidate_I
+       cache   0x1, 0($2)              // Index_Writeback_Inv_D
+       addiu   $2, $2, 32
+       subu $4, $3, $2
+       bgtz    $4, 2b
+       nop
+
+       load_addr $3, usb_boot_return
+
+       jr $3
+
+usbboot_begin:
+
+init_caches:
+       li      $2, 3                   // cacheable for kseg0 access
+       mtc0    $2, $16                 // CP0_CONFIG
+       nop
+
+       li      $2, 0x20000000          // enable idx-store-data cache insn
+       mtc0    $2, $26                 // CP0_ERRCTL
+
+       ori     $2, $28, 0              // start address
+       ori     $3, $2, 0x3fe0          // end address, total 16KB
+       mtc0    $0, $28, 0              // CP0_TAGLO
+       mtc0    $0, $28, 1              // CP0_DATALO
+cache_clear_a_line:
+       cache   0x8, 0($2)              // Index_Store_Tag_I
+       cache   0x9, 0($2)              // Index_Store_Tag_D
+       bne     $2, $3, cache_clear_a_line
+       addiu   $2, $2, 32              // increment CACHE_LINE_SIZE
+
+       ori     $2, $28, 0              // start address
+       ori     $3, $2, 0x3fe0          // end address, total 16KB
+       la      $4, 0x1ffff000          // physical address and 4KB page mask
+cache_alloc_a_line:
+       and     $5, $2, $4
+       ori     $5, $5, 1               // V bit of the physical tag
+       mtc0    $5, $28, 0              // CP0_TAGLO
+       cache   0x8, 0($2)              // Index_Store_Tag_I
+       cache   0x9, 0($2)              // Index_Store_Tag_D
+       bne     $2, $3, cache_alloc_a_line
+       addiu   $2, $2, 32              // increment CACHE_LINE_SIZE
+
+       nop
+       nop
+       nop
+       //--------------------------------------------------------------
+       // Transfer data from dcache to icache, then jump to icache.
+       //
+       // Input parameters:
+       //
+       // $19: data length in bytes
+       // $20: jump target address
+       //--------------------------------------------------------------
+xfer_d2i:
+
+       ori     $8, $20, 0
+       addu    $9, $8, $19             // total 16KB
+
+1:
+       cache   0x0, 0($8)              // Index_Invalidate_I
+       cache   0x1, 0($8)              // Index_Writeback_Inv_D
+       bne     $8, $9, 1b
+       addiu   $8, $8, 32
+
+       // flush write-buffer
+       sync
+
+       // Invalidate BTB
+       mfc0    $8, $16, 7              // CP0_CONFIG
+       nop
+       ori     $8, 2
+       mtc0    $8, $16, 7
+       nop
+
+       // Overwrite config to disable ram initalisation
+       li $2, 0xff
+       sb $2, 20($20)
+
+       jalr    $20
+       nop
+
+icache_return:
+       //--------------------------------------------------------------
+       // User code can return to here after executing itself in 
+       // icache, by jumping to $31.
+       //--------------------------------------------------------------
+       b       usb_boot_return
+       nop
+
+
+usb_boot_return:
+       //--------------------------------------------------------------
+       // Enable the USB PHY
+       //--------------------------------------------------------------
+       la      $9, 0xB0000024          // CPM_SCR
+       lw      $8, 0($9)
+       ori     $8, 0x40                // USBPHY_ENABLE
+       sw      $8, 0($9)
+
+       //--------------------------------------------------------------
+       // Initialize USB registers
+       //--------------------------------------------------------------
+       la      $27, 0xb3040000         // USB registers base address
+
+       sb      $0, 0x0b($27)           // INTRUSBE: disable common USB interrupts
+       sh      $0, 0x06($27)           // INTRINE: disable EPIN interrutps
+       sh      $0, 0x08($27)           // INTROUTE: disable EPOUT interrutps
+
+       li      $9, 0x61
+       sb      $9, 0x01($27)           // POWER: HSENAB | SUSPENDM | SOFTCONN
+
+       //--------------------------------------------------------------
+       // Initialize USB states
+       //--------------------------------------------------------------
+       li      $22, 0                  // set EP0 to IDLE state
+       li      $23, 1                  // no data stage
+
+       //--------------------------------------------------------------
+       // Main loop of polling the usb commands
+       //--------------------------------------------------------------
+usb_command_loop:
+       lbu     $9, 0x0a($27)           // read INTRUSB
+       andi    $9, 0x04                // check USB_INTR_RESET
+       beqz    $9, check_intr_ep0in
+       nop
+
+       //--------------------------------------------------------------
+       // 1. Handle USB reset interrupt
+       //--------------------------------------------------------------
+handle_reset_intr:
+       lbu     $9, 0x01($27)           // read POWER
+       andi    $9, 0x10                // test HS_MODE
+       bnez    $9, _usb_set_maxpktsize
+       li      $9, 512                 // max packet size of HS mode
+       li      $9, 64                  // max packet size of FS mode
+
+_usb_set_maxpktsize:
+       li      $8, 1
+       sb      $8, 0x0e($27)           // set INDEX 1
+
+       sh      $9, 0x10($27)           // INMAXP
+       sb      $0, 0x13($27)           // INCSRH
+       sh      $9, 0x14($27)           // OUTMAXP
+       sb      $0, 0x17($27)           // OUTCSRH
+
+_usb_flush_fifo:
+       li      $8, 0x48                // INCSR_CDT && INCSR_FF
+       sb      $8, 0x12($27)           // INCSR
+       li      $8, 0x90                // OUTCSR_CDT && OUTCSR_FF
+       sb      $8, 0x16($27)           // OUTCSR
+
+       li      $22, 0                  // set EP0 to IDLE state
+       li      $23, 1                  // no data stage
+
+       //--------------------------------------------------------------
+       // 2. Check and handle EP0 interrupt
+       //--------------------------------------------------------------
+check_intr_ep0in:
+       lhu     $10, 0x02($27)          // read INTRIN
+       andi    $9, $10, 0x1            // check EP0 interrupt
+       beqz    $9, check_intr_ep1in
+       nop
+
+handle_ep0_intr:
+       sb      $0, 0x0e($27)           // set INDEX 0
+       lbu     $11, 0x12($27)          // read CSR0
+
+       andi    $9, $11, 0x04           // check SENTSTALL
+       beqz    $9, _ep0_setupend
+       nop
+
+_ep0_sentstall:
+       andi    $9, $11, 0xdb
+       sb      $9, 0x12($27)           // clear SENDSTALL and SENTSTALL
+       li      $22, 0                  // set EP0 to IDLE state
+
+_ep0_setupend:
+       andi    $9, $11, 0x10           // check SETUPEND
+       beqz    $9, ep0_idle_state
+       nop
+
+       ori     $9, $11, 0x80
+       sb      $9, 0x12($27)           // set SVDSETUPEND
+       li      $22, 0                  // set EP0 to IDLE state
+
+ep0_idle_state:
+       bnez    $22, ep0_tx_state
+       nop
+
+       //--------------------------------------------------------------
+       // 2.1 Handle EP0 IDLE state interrupt
+       //--------------------------------------------------------------
+       andi    $9, $11, 0x01           // check OUTPKTRDY
+       beqz    $9, check_intr_ep1in
+       nop
+
+       //--------------------------------------------------------------
+       // Read 8-bytes setup packet from the FIFO
+       //--------------------------------------------------------------
+       lw      $25, 0x20($27)          // first word of setup packet
+       lw      $26, 0x20($27)          // second word of setup packet
+
+       andi    $9, $25, 0x60           // bRequestType & USB_TYPE_MASK
+       beqz    $9, _ep0_std_req
+       nop
+
+       //--------------------------------------------------------------
+       // 2.1.1 Vendor-specific setup request
+       //--------------------------------------------------------------
+_ep0_vend_req:
+       li      $22, 0                  // set EP0 to IDLE state
+       li      $23, 1                  // NoData = 1
+
+       andi    $9, $25, 0xff00         // check bRequest
+       srl     $9, $9, 8
+       beqz    $9, __ep0_get_cpu_info
+       sub     $8, $9, 0x1
+       beqz    $8, __ep0_set_data_address
+       sub     $8, $9, 0x2
+       beqz    $8, __ep0_set_data_length
+       sub     $8, $9, 0x3
+       beqz    $8, __ep0_flush_caches
+       sub     $8, $9, 0x4
+       beqz    $8, __ep0_prog_start1
+       sub     $8, $9, 0x5
+       beqz    $8, __ep0_prog_start2
+       nop
+       b       _ep0_idle_state_fini    // invalid request
+       nop
+
+__ep0_get_cpu_info:
+       load_addr $20, cpu_info_data    // data pointer to transfer
+       li      $21, 8                  // bytes left to transfer
+       li      $22, 1                  // set EP0 to TX state
+       li      $23, 0                  // NoData = 0
+
+       b       _ep0_idle_state_fini
+       nop
+
+__ep0_set_data_address:
+       li      $9, 0xffff0000
+       and     $9, $25, $9
+       andi    $8, $26, 0xffff
+       or      $20, $9, $8             // data address of next transfer
+
+       b       _ep0_idle_state_fini
+       nop
+
+__ep0_set_data_length:
+       li      $9, 0xffff0000
+       and     $9, $25, $9
+       andi    $8, $26, 0xffff
+       or      $21, $9, $8             // data length of next transfer
+
+       li      $9, 0x48                // SVDOUTPKTRDY and DATAEND
+       sb      $9, 0x12($27)           // CSR0
+
+       // We must write packet to FIFO before EP1-IN interrupt here.
+       b       handle_epin1_intr
+       nop
+
+__ep0_flush_caches:
+       // Flush dcache and invalidate icache.
+       li      $8, 0x80000000
+       addi    $9, $8, 0x3fe0          // total 16KB
+
+1:
+       cache   0x0, 0($8)              // Index_Invalidate_I
+       cache   0x1, 0($8)              // Index_Writeback_Inv_D
+       bne     $8, $9, 1b
+       addiu   $8, $8, 32
+
+       // flush write-buffer
+       sync
+
+       // Invalidate BTB
+       mfc0    $8, $16, 7              // CP0_CONFIG
+       nop
+       ori     $8, 2
+       mtc0    $8, $16, 7
+       nop
+
+       b       _ep0_idle_state_fini
+       nop
+
+__ep0_prog_start1:
+       li      $9, 0x48                // SVDOUTPKTRDY and DATAEND
+       sb      $9, 0x12($27)           // CSR0
+
+       li      $9, 0xffff0000
+       and     $9, $25, $9
+       andi    $8, $26, 0xffff
+       or      $20, $9, $8             // target address
+
+       b       xfer_d2i
+       li      $19, 0x2000             // 16KB data length
+
+__ep0_prog_start2:
+       li      $9, 0x48                // SVDOUTPKTRDY and DATAEND
+       sb      $9, 0x12($27)           // CSR0
+
+       li      $9, 0xffff0000
+       and     $9, $25, $9
+       andi    $8, $26, 0xffff
+       or      $20, $9, $8             // target address
+
+       jalr    $20                     // jump, and place the return address in $31
+       nop
+
+__ep0_prog_start2_return:
+       // User code can return to here after executing itself, by jumping to $31.
+       b       usb_boot_return
+       nop
+
+       //--------------------------------------------------------------
+       // 2.1.2 Standard setup request
+       //--------------------------------------------------------------
+_ep0_std_req:
+       andi    $12, $25, 0xff00        // check bRequest
+       srl     $12, $12, 8
+       sub     $9, $12, 0x05           // check USB_REQ_SET_ADDRESS
+       bnez    $9, __ep0_req_set_config
+       nop
+
+       //--------------------------------------------------------------
+       // Handle USB_REQ_SET_ADDRESS
+       //--------------------------------------------------------------
+__ep0_req_set_addr:
+       srl     $9, $25, 16             // get wValue
+       sb      $9, 0x0($27)            // set FADDR
+       li      $23, 1                  // NoData = 1
+       b       _ep0_idle_state_fini
+       nop
+
+__ep0_req_set_config:
+       sub     $9, $12, 0x09           // check USB_REQ_SET_CONFIGURATION
+       bnez    $9, __ep0_req_get_desc
+       nop
+
+       //--------------------------------------------------------------
+       // Handle USB_REQ_SET_CONFIGURATION
+       //--------------------------------------------------------------
+       li      $23, 1                  // NoData = 1
+       b       _ep0_idle_state_fini
+       nop
+
+__ep0_req_get_desc:
+       sub     $9, $12, 0x06           // check USB_REQ_GET_DESCRIPTOR
+       bnez    $9, _ep0_idle_state_fini
+       li      $23, 1                  // NoData = 1
+
+       //--------------------------------------------------------------
+       // Handle USB_REQ_GET_DESCRIPTOR
+       //--------------------------------------------------------------
+       li      $23, 0                  // NoData = 0
+
+       srl     $9, $25, 24             // wValue >> 8
+       sub     $8, $9, 0x01            // check USB_DT_DEVICE
+       beqz    $8, ___ep0_get_dev_desc
+       srl     $21, $26, 16            // get wLength
+       sub     $8, $9, 0x02            // check USB_DT_CONFIG
+       beqz    $8, ___ep0_get_conf_desc
+       sub     $8, $9, 0x03            // check USB_DT_STRING
+       beqz    $8, ___ep0_get_string_desc
+       sub     $8, $9, 0x06            // check USB_DT_DEVICE_QUALIFIER
+       beqz    $8, ___ep0_get_dev_qualifier
+       nop
+       b       _ep0_idle_state_fini
+       nop
+
+___ep0_get_dev_desc:
+       load_addr       $20, device_desc        // data pointer
+       li      $22, 1                  // set EP0 to TX state
+       sub     $8, $21, 18
+       blez    $8, _ep0_idle_state_fini // wLength <= 18
+       nop
+       li      $21, 18                 // max length of device_desc
+       b       _ep0_idle_state_fini
+       nop
+
+___ep0_get_dev_qualifier:
+       load_addr       $20, dev_qualifier      // data pointer
+       li      $22, 1                  // set EP0 to TX state
+       sub     $8, $21, 10
+       blez    $8, _ep0_idle_state_fini // wLength <= 10
+       nop
+       li      $21, 10                 // max length of dev_qualifier
+       b       _ep0_idle_state_fini
+       nop
+
+___ep0_get_conf_desc:
+       load_addr       $20, config_desc_fs     // data pointer of FS mode
+       lbu     $8, 0x01($27)           // read POWER
+       andi    $8, 0x10                // test HS_MODE
+       beqz    $8, ___ep0_get_conf_desc2
+       nop
+       load_addr $20, config_desc_hs   // data pointer of HS mode
+
+___ep0_get_conf_desc2:
+       li      $22, 1                  // set EP0 to TX state
+       sub     $8, $21, 32
+       blez    $8, _ep0_idle_state_fini // wLength <= 32
+       nop
+       li      $21, 32                 // max length of config_desc
+       b       _ep0_idle_state_fini
+       nop
+
+___ep0_get_string_desc:
+       li      $22, 1                  // set EP0 to TX state
+
+       srl     $9, $25, 16             // wValue & 0xff
+       andi    $9, 0xff
+
+       sub     $8, $9, 1
+       beqz    $8, ___ep0_get_string_manufacture
+       sub     $8, $9, 2
+       beqz    $8, ___ep0_get_string_product
+       nop
+
+___ep0_get_string_lang_ids:
+       load_addr       $20, string_lang_ids    // data pointer
+       b       _ep0_idle_state_fini
+       li      $21, 4                  // data length
+
+___ep0_get_string_manufacture:
+       load_addr       $20, string_manufacture // data pointer
+       b       _ep0_idle_state_fini
+       li      $21, 16                 // data length
+
+___ep0_get_string_product:
+       load_addr       $20, string_product     // data pointer
+       b       _ep0_idle_state_fini
+       li      $21, 46                 // data length
+
+_ep0_idle_state_fini:
+       li      $9, 0x40                // SVDOUTPKTRDY
+       beqz    $23, _ep0_idle_state_fini2
+       nop
+       ori     $9, $9, 0x08            // DATAEND
+_ep0_idle_state_fini2:
+       sb      $9, 0x12($27)           // CSR0
+       beqz    $22, check_intr_ep1in
+       nop
+
+       //--------------------------------------------------------------
+       // 2.2 Handle EP0 TX state interrupt
+       //--------------------------------------------------------------
+ep0_tx_state:
+       sub     $9, $22, 1
+       bnez    $9, check_intr_ep1in
+       nop
+
+       sub     $9, $21, 64             // max packetsize
+       blez    $9, _ep0_tx_state2      // data count <= 64
+       ori     $19, $21, 0
+       li      $19, 64
+
+_ep0_tx_state2:
+       beqz    $19, _ep0_tx_state3     // send ZLP
+       ori     $18, $19, 0             // record bytes to be transferred
+       sub     $21, $21, $19           // decrement data count
+
+_ep0_fifo_write_loop:
+       lbu     $9, 0($20)              // read data
+       sb      $9, 0x20($27)           // load FIFO
+       sub     $19, $19, 1             // decrement counter
+       bnez    $19, _ep0_fifo_write_loop
+       addi    $20, $20, 1             // increment data pointer
+
+       sub     $9, $18, 64             // max packetsize
+       beqz    $9, _ep0_tx_state4
+       nop
+
+_ep0_tx_state3:
+       // transferred bytes < max packetsize
+       li      $9, 0x0a                // set INPKTRDY and DATAEND
+       sb      $9, 0x12($27)           // CSR0
+       li      $22, 0                  // set EP0 to IDLE state
+       b       check_intr_ep1in
+       nop
+
+_ep0_tx_state4:
+       // transferred bytes == max packetsize
+       li      $9, 0x02                // set INPKTRDY
+       sb      $9, 0x12($27)           // CSR0
+       b       check_intr_ep1in
+       nop
+
+       //--------------------------------------------------------------
+       // 3. Check and handle EP1 BULK-IN interrupt
+       //--------------------------------------------------------------
+check_intr_ep1in:
+       andi    $9, $10, 0x2            // check EP1 IN interrupt
+       beqz    $9, check_intr_ep1out
+       nop
+
+handle_epin1_intr:
+       li      $9, 1
+       sb      $9, 0x0e($27)           // set INDEX 1
+       lbu     $9, 0x12($27)           // read INCSR
+
+       andi    $8, $9, 0x2             // check INCSR_FFNOTEMPT
+       bnez    $8, _epin1_tx_state4
+       nop
+
+_epin1_write_fifo:
+       lhu     $9, 0x10($27)           // get INMAXP
+       sub     $8, $21, $9
+       blez    $8, _epin1_tx_state1    // bytes left <= INMAXP
+       ori     $19, $21, 0
+       ori     $19, $9, 0
+
+_epin1_tx_state1:
+       beqz    $19, _epin1_tx_state4   // No data
+       nop
+
+       sub     $21, $21, $19           // decrement data count
+
+       srl     $5, $19, 2              // # of word
+       andi    $6, $19, 0x3            // # of byte
+       beqz    $5, _epin1_tx_state2
+       nop
+
+_epin1_fifo_write_word:
+       lw      $9, 0($20)              // read data from source address
+       sw      $9, 0x24($27)           // write FIFO
+       sub     $5, $5, 1               // decrement counter
+       bnez    $5, _epin1_fifo_write_word
+       addiu   $20, $20, 4             // increment dest address
+
+_epin1_tx_state2:
+       beqz    $6, _epin1_tx_state3
+       nop
+
+_epin1_fifo_write_byte:
+       lbu     $9, 0($20)              // read data from source address
+       sb      $9, 0x24($27)           // write FIFO
+       sub     $6, $6, 1               // decrement counter
+       bnez    $6, _epin1_fifo_write_byte
+       addiu   $20, $20, 1             // increment dest address
+
+_epin1_tx_state3:
+       li      $9, 0x1
+       sb      $9, 0x12($27)           // INCSR, set INPKTRDY
+
+_epin1_tx_state4:
+       // nop
+
+       //--------------------------------------------------------------
+       // 4. Check and handle EP1 BULK-OUT interrupt
+       //--------------------------------------------------------------
+check_intr_ep1out:
+       lhu     $9, 0x04($27)           // read INTROUT
+       andi    $9, 0x2
+       beqz    $9, check_status_next
+       nop
+
+handle_epout1_intr:
+       li      $9, 1
+       sb      $9, 0x0e($27)           // set INDEX 1
+
+       lbu     $9, 0x16($27)           // read OUTCSR
+       andi    $9, 0x1                 // check OUTPKTRDY
+       beqz    $9, check_status_next
+       nop
+
+_epout1_read_fifo:
+       lhu     $19, 0x18($27)          // read OUTCOUNT
+       srl     $5, $19, 2              // # of word
+       andi    $6, $19, 0x3            // # of byte
+       beqz    $5, _epout1_rx_state1
+       nop
+
+_epout1_fifo_read_word:
+       lw      $9, 0x24($27)           // read FIFO
+       sw      $9, 0($20)              // store to dest address
+       sub     $5, $5, 1               // decrement counter
+       bnez    $5, _epout1_fifo_read_word
+       addiu   $20, $20, 4             // increment dest address
+
+_epout1_rx_state1:
+       beqz    $6, _epout1_rx_state2
+       nop
+
+_epout1_fifo_read_byte:
+       lbu     $9, 0x24($27)           // read FIFO
+       sb      $9, 0($20)              // store to dest address
+       sub     $6, $6, 1               // decrement counter
+       bnez    $6, _epout1_fifo_read_byte
+       addiu   $20, $20, 1             // increment dest address
+
+_epout1_rx_state2:
+       sb      $0, 0x16($27)           // clear OUTPKTRDY
+
+check_status_next:
+       b       usb_command_loop
+       nop
+
+//--------------------------------------------------------------
+// Device/Configuration/Interface/Endpoint/String Descriptors
+//--------------------------------------------------------------
+
+       .align  2
+device_desc:
+       .byte   0x12            // bLength
+       .byte   0x01            // bDescriptorType
+       .byte   0x00            // bcdUSB
+       .byte   0x02            // bcdUSB
+       .byte   0x00            // bDeviceClass
+       .byte   0x00            // bDeviceSubClass
+       .byte   0x00            // bDeviceProtocol
+       .byte   0x40            // bMaxPacketSize0
+       .byte   0x1a            // idVendor
+       .byte   0x60            // idVendor
+       .byte   0x40            // idProduct
+       .byte   0x47            // idProduct
+       .byte   0x00            // bcdDevice
+       .byte   0x01            // bcdDevice
+       .byte   0x01            // iManufacturer
+       .byte   0x02            // iProduct
+       .byte   0x00            // iSerialNumber
+       .byte   0x01            // bNumConfigurations
+
+       .align  2
+dev_qualifier:
+       .byte   0x0a            // bLength
+       .byte   0x06            // bDescriptorType
+       .byte   0x00            // bcdUSB
+       .byte   0x02            // bcdUSB
+       .byte   0x00            // bDeviceClass
+       .byte   0x00            // bDeviceSubClass
+       .byte   0x00            // bDeviceProtocol
+       .byte   0x40            // bMaxPacketSize0
+       .byte   0x01            // bNumConfigurations
+       .byte   0x00            // bRESERVED
+
+       .align  2
+config_desc_hs:
+       .byte   0x09            // bLength
+       .byte   0x02            // bDescriptorType
+       .byte   0x20            // wTotalLength
+       .byte   0x00            // wTotalLength
+       .byte   0x01            // bNumInterfaces
+       .byte   0x01            // bConfigurationValue
+       .byte   0x00            // iConfiguration
+       .byte   0xc0            // bmAttributes
+       .byte   0x01            // MaxPower
+intf_desc_hs:
+       .byte   0x09            // bLength
+       .byte   0x04            // bDescriptorType
+       .byte   0x00            // bInterfaceNumber
+       .byte   0x00            // bAlternateSetting
+       .byte   0x02            // bNumEndpoints
+       .byte   0xff            // bInterfaceClass
+       .byte   0x00            // bInterfaceSubClass
+       .byte   0x50            // bInterfaceProtocol
+       .byte   0x00            // iInterface
+ep1_desc_hs:
+       .byte   0x07            // bLength
+       .byte   0x05            // bDescriptorType
+       .byte   0x01            // bEndpointAddress
+       .byte   0x02            // bmAttributes
+       .byte   0x00            // wMaxPacketSize
+       .byte   0x02            // wMaxPacketSize
+       .byte   0x00            // bInterval
+ep2_desc_hs:
+       .byte   0x07            // bLength
+       .byte   0x05            // bDescriptorType
+       .byte   0x81            // bEndpointAddress
+       .byte   0x02            // bmAttributes
+       .byte   0x00            // wMaxPacketSize
+       .byte   0x02            // wMaxPacketSize
+       .byte   0x00            // bInterval
+
+       .align  2
+config_desc_fs:
+       .byte   0x09            // bLength
+       .byte   0x02            // bDescriptorType
+       .byte   0x20            // wTotalLength
+       .byte   0x00            // wTotalLength
+       .byte   0x01            // bNumInterfaces
+       .byte   0x01            // bConfigurationValue
+       .byte   0x00            // iConfiguration
+       .byte   0xc0            // bmAttributes
+       .byte   0x01            // MaxPower
+intf_desc_fs:
+       .byte   0x09            // bLength
+       .byte   0x04            // bDescriptorType
+       .byte   0x00            // bInterfaceNumber
+       .byte   0x00            // bAlternateSetting
+       .byte   0x02            // bNumEndpoints
+       .byte   0xff            // bInterfaceClass
+       .byte   0x00            // bInterfaceSubClass
+       .byte   0x50            // bInterfaceProtocol
+       .byte   0x00            // iInterface
+ep1_desc_fs:
+       .byte   0x07            // bLength
+       .byte   0x05            // bDescriptorType
+       .byte   0x01            // bEndpointAddress
+       .byte   0x02            // bmAttributes
+       .byte   0x40            // wMaxPacketSize
+       .byte   0x00            // wMaxPacketSize
+       .byte   0x00            // bInterval
+ep2_desc_fs:
+       .byte   0x07            // bLength
+       .byte   0x05            // bDescriptorType
+       .byte   0x81            // bEndpointAddress
+       .byte   0x02            // bmAttributes
+       .byte   0x40            // wMaxPacketSize
+       .byte   0x00            // wMaxPacketSize
+       .byte   0x00            // bInterval
+
+       .align  2
+string_lang_ids:
+       .byte   0x04
+       .byte   0x03
+       .byte   0x09
+       .byte   0x04
+
+       .align  2
+string_manufacture:
+       .byte   0x10
+       .byte   0x03
+       .byte   0x49
+       .byte   0x00
+       .byte   0x6e
+       .byte   0x00
+       .byte   0x67
+       .byte   0x00
+       .byte   0x65
+       .byte   0x00
+       .byte   0x6e
+       .byte   0x00
+       .byte   0x69
+       .byte   0x00
+       .byte   0x63
+       .byte   0x00
+
+       .align  2
+string_product:
+       .byte   0x2e
+       .byte   0x03
+       .byte   0x4a
+       .byte   0x00
+       .byte   0x5a
+       .byte   0x00
+       .byte   0x34
+       .byte   0x00
+       .byte   0x37
+       .byte   0x00
+       .byte   0x34
+       .byte   0x00
+       .byte   0x30
+       .byte   0x00
+       .byte   0x20
+       .byte   0x00
+       .byte   0x55
+       .byte   0x00
+       .byte   0x53
+       .byte   0x00
+       .byte   0x42
+       .byte   0x00
+       .byte   0x20
+       .byte   0x00
+       .byte   0x42
+       .byte   0x00
+       .byte   0x6f
+       .byte   0x00
+       .byte   0x6f
+       .byte   0x00
+       .byte   0x74
+       .byte   0x00
+       .byte   0x20
+       .byte   0x00
+       .byte   0x44
+       .byte   0x00
+       .byte   0x65
+       .byte   0x00
+       .byte   0x76
+       .byte   0x00
+       .byte   0x69
+       .byte   0x00
+       .byte   0x63
+       .byte   0x00
+       .byte   0x65
+       .byte   0x00
+
+       .align  2
+cpu_info_data:
+       .byte   0x4a
+       .byte   0x5a
+       .byte   0x34
+       .byte   0x37
+       .byte   0x34
+       .byte   0x30
+       .byte   0x56
+       .byte   0x31
+usbboot_end:
+
+    .set reorder
diff --git a/package/uboot-xburst/files/include/asm-mips/jz4740.h b/package/uboot-xburst/files/include/asm-mips/jz4740.h
new file mode 100644 (file)
index 0000000..a752dcc
--- /dev/null
@@ -0,0 +1,4882 @@
+/*
+ * Include file for Ingenic Semiconductor's JZ4740 CPU.
+ */
+#ifndef __JZ4740_H__
+#define __JZ4740_H__
+
+#ifndef __ASSEMBLY__
+#define UCOS_CSP 0
+
+#if UCOS_CSP
+#define __KERNEL__
+#include <bsp.h>
+#include <types.h>
+
+#include <sysdefs.h>
+#include <cacheops.h>
+#define KSEG0 KSEG0BASE
+#else
+#include <asm/addrspace.h>
+#include <asm/cacheops.h>
+#endif
+
+#define cache_unroll(base,op)                  \
+       __asm__ __volatile__("                  \
+               .set noreorder;                 \
+               .set mips3;                     \
+               cache %1, (%0);                 \
+               .set mips0;                     \
+               .set reorder"                   \
+               :                               \
+               : "r" (base),                   \
+                 "i" (op));
+
+static inline void jz_flush_dcache(void)
+{
+       unsigned long start;
+       unsigned long end;
+
+       start = KSEG0;
+       end = start + CONFIG_SYS_DCACHE_SIZE;
+       while (start < end) {
+               cache_unroll(start,Index_Writeback_Inv_D);
+               start += CONFIG_SYS_CACHELINE_SIZE;
+       }
+}
+
+static inline void jz_flush_icache(void)
+{
+       unsigned long start;
+       unsigned long end;
+
+       start = KSEG0;
+       end = start + CONFIG_SYS_ICACHE_SIZE;
+       while(start < end) {
+               cache_unroll(start,Index_Invalidate_I);
+               start += CONFIG_SYS_CACHELINE_SIZE;
+       }
+}
+
+/* cpu pipeline flush */
+static inline void jz_sync(void)
+{
+       __asm__ volatile ("sync");
+}
+
+static inline void jz_writeb(u32 address, u8 value)
+{
+       *((volatile u8 *)address) = value;
+}
+
+static inline void jz_writew(u32 address, u16 value)
+{
+       *((volatile u16 *)address) = value;
+}
+
+static inline void jz_writel(u32 address, u32 value)
+{
+       *((volatile u32 *)address) = value;
+}
+
+static inline u8 jz_readb(u32 address)
+{
+       return *((volatile u8 *)address);
+}
+
+static inline u16 jz_readw(u32 address)
+{
+       return *((volatile u16 *)address);
+}
+
+static inline u32 jz_readl(u32 address)
+{
+       return *((volatile u32 *)address);
+}
+
+#define REG8(addr)     *((volatile u8 *)(addr))
+#define REG16(addr)    *((volatile u16 *)(addr))
+#define REG32(addr)    *((volatile u32 *)(addr))
+
+#else
+
+#define REG8(addr)     (addr)
+#define REG16(addr)    (addr)
+#define REG32(addr)    (addr)
+
+#endif /* !ASSEMBLY */
+
+/* Boot ROM Specification  */
+/* NOR Boot config */
+#define JZ4740_NORBOOT_8BIT    0x00000000      /* 8-bit data bus flash */
+#define JZ4740_NORBOOT_16BIT   0x10101010      /* 16-bit data bus flash */
+#define JZ4740_NORBOOT_32BIT   0x20202020      /* 32-bit data bus flash */
+
+/* NAND Boot config */
+#define JZ4740_NANDBOOT_B8R3   0xffffffff      /* 8-bit bus & 3 row cycles */
+#define JZ4740_NANDBOOT_B8R2   0xf0f0f0f0      /* 8-bit bus & 2 row cycles */
+#define JZ4740_NANDBOOT_B16R3  0x0f0f0f0f      /* 16-bit bus & 3 row cycles */
+#define JZ4740_NANDBOOT_B16R2  0x00000000      /* 16-bit bus & 2 row cycles */
+
+
+/* Register Definitions */
+#define        CPM_BASE        0xB0000000
+#define        INTC_BASE       0xB0001000
+#define        TCU_BASE        0xB0002000
+#define        WDT_BASE        0xB0002000
+#define        RTC_BASE        0xB0003000
+#define        GPIO_BASE       0xB0010000
+#define        AIC_BASE        0xB0020000
+#define        ICDC_BASE       0xB0020000
+#define        MSC_BASE        0xB0021000
+#define        UART0_BASE      0xB0030000
+#define        I2C_BASE        0xB0042000
+#define        SSI_BASE        0xB0043000
+#define        SADC_BASE       0xB0070000
+#define        EMC_BASE        0xB3010000
+#define        DMAC_BASE       0xB3020000
+#define        UHC_BASE        0xB3030000
+#define        UDC_BASE        0xB3040000
+#define        LCD_BASE        0xB3050000
+#define        SLCD_BASE       0xB3050000
+#define        CIM_BASE        0xB3060000
+#define        ETH_BASE        0xB3100000
+
+
+/*
+ * INTC (Interrupt Controller)
+ */
+#define INTC_ISR       (INTC_BASE + 0x00)
+#define INTC_IMR       (INTC_BASE + 0x04)
+#define INTC_IMSR      (INTC_BASE + 0x08)
+#define INTC_IMCR      (INTC_BASE + 0x0c)
+#define INTC_IPR       (INTC_BASE + 0x10)
+
+#define REG_INTC_ISR   REG32(INTC_ISR)
+#define REG_INTC_IMR   REG32(INTC_IMR)
+#define REG_INTC_IMSR  REG32(INTC_IMSR)
+#define REG_INTC_IMCR  REG32(INTC_IMCR)
+#define REG_INTC_IPR   REG32(INTC_IPR)
+
+/* 1st-level interrupts */
+#define IRQ_I2C                1
+#define IRQ_UHC                3
+#define IRQ_UART0      9
+#define IRQ_SADC       12
+#define IRQ_MSC                14
+#define IRQ_RTC                15
+#define IRQ_SSI                16
+#define IRQ_CIM                17
+#define IRQ_AIC                18
+#define IRQ_ETH                19
+#define IRQ_DMAC       20
+#define IRQ_TCU2       21
+#define IRQ_TCU1       22
+#define IRQ_TCU0       23
+#define IRQ_UDC        24
+#define IRQ_GPIO3      25
+#define IRQ_GPIO2      26
+#define IRQ_GPIO1      27
+#define IRQ_GPIO0      28
+#define IRQ_IPU                29
+#define IRQ_LCD                30
+
+/* 2nd-level interrupts */
+#define IRQ_DMA_0      32  /* 32 to 37 for DMAC channel 0 to 5 */
+#define IRQ_GPIO_0     48  /* 48 to 175 for GPIO pin 0 to 127 */
+
+
+/*
+ * RTC
+ */
+#define RTC_RCR                (RTC_BASE + 0x00) /* RTC Control Register */
+#define RTC_RSR                (RTC_BASE + 0x04) /* RTC Second Register */
+#define RTC_RSAR       (RTC_BASE + 0x08) /* RTC Second Alarm Register */
+#define RTC_RGR                (RTC_BASE + 0x0c) /* RTC Regulator Register */
+
+#define RTC_HCR                (RTC_BASE + 0x20) /* Hibernate Control Register */
+#define RTC_HWFCR      (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */
+#define RTC_HRCR       (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */
+#define RTC_HWCR       (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */
+#define RTC_HWRSR      (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */
+#define RTC_HSPR       (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */
+
+#define REG_RTC_RCR    REG32(RTC_RCR)
+#define REG_RTC_RSR    REG32(RTC_RSR)
+#define REG_RTC_RSAR   REG32(RTC_RSAR)
+#define REG_RTC_RGR    REG32(RTC_RGR)
+#define REG_RTC_HCR    REG32(RTC_HCR)
+#define REG_RTC_HWFCR  REG32(RTC_HWFCR)
+#define REG_RTC_HRCR   REG32(RTC_HRCR)
+#define REG_RTC_HWCR   REG32(RTC_HWCR)
+#define REG_RTC_HWRSR  REG32(RTC_HWRSR)
+#define REG_RTC_HSPR   REG32(RTC_HSPR)
+
+/* RTC Control Register */
+#define RTC_RCR_WRDY   (1 << 7)  /* Write Ready Flag */
+#define RTC_RCR_HZ     (1 << 6)  /* 1Hz Flag */
+#define RTC_RCR_HZIE   (1 << 5)  /* 1Hz Interrupt Enable */
+#define RTC_RCR_AF     (1 << 4)  /* Alarm Flag */
+#define RTC_RCR_AIE    (1 << 3)  /* Alarm Interrupt Enable */
+#define RTC_RCR_AE     (1 << 2)  /* Alarm Enable */
+#define RTC_RCR_RTCE   (1 << 0)  /* RTC Enable */
+
+/* RTC Regulator Register */
+#define RTC_RGR_LOCK           (1 << 31) /* Lock Bit */
+#define RTC_RGR_ADJC_BIT       16
+#define RTC_RGR_ADJC_MASK      (0x3ff << RTC_RGR_ADJC_BIT)
+#define RTC_RGR_NC1HZ_BIT      0
+#define RTC_RGR_NC1HZ_MASK     (0xffff << RTC_RGR_NC1HZ_BIT)
+
+/* Hibernate Control Register */
+#define RTC_HCR_PD             (1 << 0)  /* Power Down */
+
+/* Hibernate Wakeup Filter Counter Register */
+#define RTC_HWFCR_BIT          5
+#define RTC_HWFCR_MASK         (0x7ff << RTC_HWFCR_BIT)
+
+/* Hibernate Reset Counter Register */
+#define RTC_HRCR_BIT           5
+#define RTC_HRCR_MASK          (0x7f << RTC_HRCR_BIT)
+
+/* Hibernate Wakeup Control Register */
+#define RTC_HWCR_EALM          (1 << 0)  /* RTC alarm wakeup enable */
+
+/* Hibernate Wakeup Status Register */
+#define RTC_HWRSR_HR           (1 << 5)  /* Hibernate reset */
+#define RTC_HWRSR_PPR          (1 << 4)  /* PPR reset */
+#define RTC_HWRSR_PIN          (1 << 1)  /* Wakeup pin status bit */
+#define RTC_HWRSR_ALM          (1 << 0)  /* RTC alarm status bit */
+
+
+/*************************************************************************
+ * CPM (Clock reset and Power control Management)
+ *************************************************************************/
+#define CPM_CPCCR      (CPM_BASE+0x00)
+#define CPM_CPPCR      (CPM_BASE+0x10)
+#define CPM_I2SCDR     (CPM_BASE+0x60)
+#define CPM_LPCDR      (CPM_BASE+0x64)
+#define CPM_MSCCDR     (CPM_BASE+0x68)
+#define CPM_UHCCDR     (CPM_BASE+0x6C)
+
+#define CPM_LCR                (CPM_BASE+0x04)
+#define CPM_CLKGR      (CPM_BASE+0x20)
+#define CPM_SCR                (CPM_BASE+0x24)
+
+#define CPM_HCR                (CPM_BASE+0x30)
+#define CPM_HWFCR      (CPM_BASE+0x34)
+#define CPM_HRCR       (CPM_BASE+0x38)
+#define CPM_HWCR       (CPM_BASE+0x3c)
+#define CPM_HWSR       (CPM_BASE+0x40)
+#define CPM_HSPR       (CPM_BASE+0x44)
+
+#define CPM_RSR                (CPM_BASE+0x08)
+
+
+#define REG_CPM_CPCCR  REG32(CPM_CPCCR)
+#define REG_CPM_CPPCR  REG32(CPM_CPPCR)
+#define REG_CPM_I2SCDR REG32(CPM_I2SCDR)
+#define REG_CPM_LPCDR  REG32(CPM_LPCDR)
+#define REG_CPM_MSCCDR REG32(CPM_MSCCDR)
+#define REG_CPM_UHCCDR REG32(CPM_UHCCDR)
+
+#define REG_CPM_LCR    REG32(CPM_LCR)
+#define REG_CPM_CLKGR  REG32(CPM_CLKGR)
+#define REG_CPM_SCR    REG32(CPM_SCR)
+#define REG_CPM_HCR    REG32(CPM_HCR)
+#define REG_CPM_HWFCR  REG32(CPM_HWFCR)
+#define REG_CPM_HRCR   REG32(CPM_HRCR)
+#define REG_CPM_HWCR   REG32(CPM_HWCR)
+#define REG_CPM_HWSR   REG32(CPM_HWSR)
+#define REG_CPM_HSPR   REG32(CPM_HSPR)
+
+#define REG_CPM_RSR    REG32(CPM_RSR)
+
+
+/* Clock Control Register */
+#define CPM_CPCCR_I2CS         (1 << 31)
+#define CPM_CPCCR_CLKOEN       (1 << 30)
+#define CPM_CPCCR_UCS          (1 << 29)
+#define CPM_CPCCR_UDIV_BIT     23
+#define CPM_CPCCR_UDIV_MASK    (0x3f << CPM_CPCCR_UDIV_BIT)
+#define CPM_CPCCR_CE           (1 << 22)
+#define CPM_CPCCR_PCS          (1 << 21)
+#define CPM_CPCCR_LDIV_BIT     16
+#define CPM_CPCCR_LDIV_MASK    (0x1f << CPM_CPCCR_LDIV_BIT)
+#define CPM_CPCCR_MDIV_BIT     12
+#define CPM_CPCCR_MDIV_MASK    (0x0f << CPM_CPCCR_MDIV_BIT)
+#define CPM_CPCCR_PDIV_BIT     8
+#define CPM_CPCCR_PDIV_MASK    (0x0f << CPM_CPCCR_PDIV_BIT)
+#define CPM_CPCCR_HDIV_BIT     4
+#define CPM_CPCCR_HDIV_MASK    (0x0f << CPM_CPCCR_HDIV_BIT)
+#define CPM_CPCCR_CDIV_BIT     0
+#define CPM_CPCCR_CDIV_MASK    (0x0f << CPM_CPCCR_CDIV_BIT)
+
+/* I2S Clock Divider Register */
+#define CPM_I2SCDR_I2SDIV_BIT  0
+#define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT)
+
+/* LCD Pixel Clock Divider Register */
+#define CPM_LPCDR_PIXDIV_BIT   0
+#define CPM_LPCDR_PIXDIV_MASK  (0x1ff << CPM_LPCDR_PIXDIV_BIT)
+
+/* MSC Clock Divider Register */
+#define CPM_MSCCDR_MSCDIV_BIT  0
+#define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT)
+
+/* PLL Control Register */
+#define CPM_CPPCR_PLLM_BIT     23
+#define CPM_CPPCR_PLLM_MASK    (0x1ff << CPM_CPPCR_PLLM_BIT)
+#define CPM_CPPCR_PLLN_BIT     18
+#define CPM_CPPCR_PLLN_MASK    (0x1f << CPM_CPPCR_PLLN_BIT)
+#define CPM_CPPCR_PLLOD_BIT    16
+#define CPM_CPPCR_PLLOD_MASK   (0x03 << CPM_CPPCR_PLLOD_BIT)
+#define CPM_CPPCR_PLLS         (1 << 10)
+#define CPM_CPPCR_PLLBP                (1 << 9)
+#define CPM_CPPCR_PLLEN                (1 << 8)
+#define CPM_CPPCR_PLLST_BIT    0
+#define CPM_CPPCR_PLLST_MASK   (0xff << CPM_CPPCR_PLLST_BIT)
+
+/* Low Power Control Register */
+#define CPM_LCR_DOZE_DUTY_BIT  3
+#define CPM_LCR_DOZE_DUTY_MASK         (0x1f << CPM_LCR_DOZE_DUTY_BIT)
+#define CPM_LCR_DOZE_ON                (1 << 2)
+#define CPM_LCR_LPM_BIT                0
+#define CPM_LCR_LPM_MASK       (0x3 << CPM_LCR_LPM_BIT)
+  #define CPM_LCR_LPM_IDLE     (0x0 << CPM_LCR_LPM_BIT)
+  #define CPM_LCR_LPM_SLEEP    (0x1 << CPM_LCR_LPM_BIT)
+
+/* Clock Gate Register */
+#define CPM_CLKGR_UART1                (1 << 15)
+#define CPM_CLKGR_UHC          (1 << 14)
+#define CPM_CLKGR_IPU          (1 << 13)
+#define CPM_CLKGR_DMAC         (1 << 12)
+#define CPM_CLKGR_UDC          (1 << 11)
+#define CPM_CLKGR_LCD          (1 << 10)
+#define CPM_CLKGR_CIM          (1 << 9)
+#define CPM_CLKGR_SADC         (1 << 8)
+#define CPM_CLKGR_MSC          (1 << 7)
+#define CPM_CLKGR_AIC1         (1 << 6)
+#define CPM_CLKGR_AIC2         (1 << 5)
+#define CPM_CLKGR_SSI          (1 << 4)
+#define CPM_CLKGR_I2C          (1 << 3)
+#define CPM_CLKGR_RTC          (1 << 2)
+#define CPM_CLKGR_TCU          (1 << 1)
+#define CPM_CLKGR_UART0                (1 << 0)
+
+/* Sleep Control Register */
+#define CPM_SCR_O1ST_BIT       8
+#define CPM_SCR_O1ST_MASK      (0xff << CPM_SCR_O1ST_BIT)
+#define CPM_SCR_UDCPHY_ENABLE  (1 << 6)
+#define CPM_SCR_USBPHY_DISABLE (1 << 7)
+#define CPM_SCR_OSC_ENABLE     (1 << 4)
+
+/* Hibernate Control Register */
+#define CPM_HCR_PD             (1 << 0)
+
+/* Wakeup Filter Counter Register in Hibernate Mode */
+#define CPM_HWFCR_TIME_BIT     0
+#define CPM_HWFCR_TIME_MASK    (0x3ff << CPM_HWFCR_TIME_BIT)
+
+/* Reset Counter Register in Hibernate Mode */
+#define CPM_HRCR_TIME_BIT      0
+#define CPM_HRCR_TIME_MASK     (0x7f << CPM_HRCR_TIME_BIT)
+
+/* Wakeup Control Register in Hibernate Mode */
+#define CPM_HWCR_WLE_LOW       (0 << 2)
+#define CPM_HWCR_WLE_HIGH      (1 << 2)
+#define CPM_HWCR_PIN_WAKEUP    (1 << 1)
+#define CPM_HWCR_RTC_WAKEUP    (1 << 0)
+
+/* Wakeup Status Register in Hibernate Mode */
+#define CPM_HWSR_WSR_PIN       (1 << 1)
+#define CPM_HWSR_WSR_RTC       (1 << 0)
+
+/* Reset Status Register */
+#define CPM_RSR_HR             (1 << 2)
+#define CPM_RSR_WR             (1 << 1)
+#define CPM_RSR_PR             (1 << 0)
+
+
+/*************************************************************************
+ * TCU (Timer Counter Unit)
+ *************************************************************************/
+#define TCU_TSR                (TCU_BASE + 0x1C) /* Timer Stop Register */
+#define TCU_TSSR       (TCU_BASE + 0x2C) /* Timer Stop Set Register */
+#define TCU_TSCR       (TCU_BASE + 0x3C) /* Timer Stop Clear Register */
+#define TCU_TER                (TCU_BASE + 0x10) /* Timer Counter Enable Register */
+#define TCU_TESR       (TCU_BASE + 0x14) /* Timer Counter Enable Set Register */
+#define TCU_TECR       (TCU_BASE + 0x18) /* Timer Counter Enable Clear Register */
+#define TCU_TFR                (TCU_BASE + 0x20) /* Timer Flag Register */
+#define TCU_TFSR       (TCU_BASE + 0x24) /* Timer Flag Set Register */
+#define TCU_TFCR       (TCU_BASE + 0x28) /* Timer Flag Clear Register */
+#define TCU_TMR                (TCU_BASE + 0x30) /* Timer Mask Register */
+#define TCU_TMSR       (TCU_BASE + 0x34) /* Timer Mask Set Register */
+#define TCU_TMCR       (TCU_BASE + 0x38) /* Timer Mask Clear Register */
+#define TCU_TDFR0      (TCU_BASE + 0x40) /* Timer Data Full Register */
+#define TCU_TDHR0      (TCU_BASE + 0x44) /* Timer Data Half Register */
+#define TCU_TCNT0      (TCU_BASE + 0x48) /* Timer Counter Register */
+#define TCU_TCSR0      (TCU_BASE + 0x4C) /* Timer Control Register */
+#define TCU_TDFR1      (TCU_BASE + 0x50)
+#define TCU_TDHR1      (TCU_BASE + 0x54)
+#define TCU_TCNT1      (TCU_BASE + 0x58)
+#define TCU_TCSR1      (TCU_BASE + 0x5C)
+#define TCU_TDFR2      (TCU_BASE + 0x60)
+#define TCU_TDHR2      (TCU_BASE + 0x64)
+#define TCU_TCNT2      (TCU_BASE + 0x68)
+#define TCU_TCSR2      (TCU_BASE + 0x6C)
+#define TCU_TDFR3      (TCU_BASE + 0x70)
+#define TCU_TDHR3      (TCU_BASE + 0x74)
+#define TCU_TCNT3      (TCU_BASE + 0x78)
+#define TCU_TCSR3      (TCU_BASE + 0x7C)
+#define TCU_TDFR4      (TCU_BASE + 0x80)
+#define TCU_TDHR4      (TCU_BASE + 0x84)
+#define TCU_TCNT4      (TCU_BASE + 0x88)
+#define TCU_TCSR4      (TCU_BASE + 0x8C)
+#define TCU_TDFR5      (TCU_BASE + 0x90)
+#define TCU_TDHR5      (TCU_BASE + 0x94)
+#define TCU_TCNT5      (TCU_BASE + 0x98)
+#define TCU_TCSR5      (TCU_BASE + 0x9C)
+
+#define REG_TCU_TSR    REG32(TCU_TSR)
+#define REG_TCU_TSSR   REG32(TCU_TSSR)
+#define REG_TCU_TSCR   REG32(TCU_TSCR)
+#define REG_TCU_TER    REG8(TCU_TER)
+#define REG_TCU_TESR   REG8(TCU_TESR)
+#define REG_TCU_TECR   REG8(TCU_TECR)
+#define REG_TCU_TFR    REG32(TCU_TFR)
+#define REG_TCU_TFSR   REG32(TCU_TFSR)
+#define REG_TCU_TFCR   REG32(TCU_TFCR)
+#define REG_TCU_TMR    REG32(TCU_TMR)
+#define REG_TCU_TMSR   REG32(TCU_TMSR)
+#define REG_TCU_TMCR   REG32(TCU_TMCR)
+#define REG_TCU_TDFR0  REG16(TCU_TDFR0)
+#define REG_TCU_TDHR0  REG16(TCU_TDHR0)
+#define REG_TCU_TCNT0  REG16(TCU_TCNT0)
+#define REG_TCU_TCSR0  REG16(TCU_TCSR0)
+#define REG_TCU_TDFR1  REG16(TCU_TDFR1)
+#define REG_TCU_TDHR1  REG16(TCU_TDHR1)
+#define REG_TCU_TCNT1  REG16(TCU_TCNT1)
+#define REG_TCU_TCSR1  REG16(TCU_TCSR1)
+#define REG_TCU_TDFR2  REG16(TCU_TDFR2)
+#define REG_TCU_TDHR2  REG16(TCU_TDHR2)
+#define REG_TCU_TCNT2  REG16(TCU_TCNT2)
+#define REG_TCU_TCSR2  REG16(TCU_TCSR2)
+#define REG_TCU_TDFR3  REG16(TCU_TDFR3)
+#define REG_TCU_TDHR3  REG16(TCU_TDHR3)
+#define REG_TCU_TCNT3  REG16(TCU_TCNT3)
+#define REG_TCU_TCSR3  REG16(TCU_TCSR3)
+#define REG_TCU_TDFR4  REG16(TCU_TDFR4)
+#define REG_TCU_TDHR4  REG16(TCU_TDHR4)
+#define REG_TCU_TCNT4  REG16(TCU_TCNT4)
+#define REG_TCU_TCSR4  REG16(TCU_TCSR4)
+
+/* n = 0,1,2,3,4,5 */
+#define TCU_TDFR(n)    (TCU_BASE + (0x40 + (n)*0x10)) /* Timer Data Full Reg */
+#define TCU_TDHR(n)    (TCU_BASE + (0x44 + (n)*0x10)) /* Timer Data Half Reg */
+#define TCU_TCNT(n)    (TCU_BASE + (0x48 + (n)*0x10)) /* Timer Counter Reg */
+#define TCU_TCSR(n)    (TCU_BASE + (0x4C + (n)*0x10)) /* Timer Control Reg */
+
+#define REG_TCU_TDFR(n)        REG16(TCU_TDFR((n)))
+#define REG_TCU_TDHR(n)        REG16(TCU_TDHR((n)))
+#define REG_TCU_TCNT(n)        REG16(TCU_TCNT((n)))
+#define REG_TCU_TCSR(n)        REG16(TCU_TCSR((n)))
+
+/* Register definitions */
+#define TCU_TCSR_PWM_SD                (1 << 9)
+#define TCU_TCSR_PWM_INITL_HIGH        (1 << 8)
+#define TCU_TCSR_PWM_EN                (1 << 7)
+#define TCU_TCSR_PRESCALE_BIT  3
+#define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT)
+#define TCU_TCSR_PRESCALE1     (0x0 << TCU_TCSR_PRESCALE_BIT)
+#define TCU_TCSR_PRESCALE4     (0x1 << TCU_TCSR_PRESCALE_BIT)
+#define TCU_TCSR_PRESCALE16    (0x2 << TCU_TCSR_PRESCALE_BIT)
+#define TCU_TCSR_PRESCALE64    (0x3 << TCU_TCSR_PRESCALE_BIT)
+#define TCU_TCSR_PRESCALE256   (0x4 << TCU_TCSR_PRESCALE_BIT)
+#define TCU_TCSR_PRESCALE1024  (0x5 << TCU_TCSR_PRESCALE_BIT)
+#define TCU_TCSR_EXT_EN                (1 << 2)
+#define TCU_TCSR_RTC_EN                (1 << 1)
+#define TCU_TCSR_PCK_EN                (1 << 0)
+
+#define TCU_TER_TCEN5          (1 << 5)
+#define TCU_TER_TCEN4          (1 << 4)
+#define TCU_TER_TCEN3          (1 << 3)
+#define TCU_TER_TCEN2          (1 << 2)
+#define TCU_TER_TCEN1          (1 << 1)
+#define TCU_TER_TCEN0          (1 << 0)
+
+#define TCU_TESR_TCST5         (1 << 5)
+#define TCU_TESR_TCST4         (1 << 4)
+#define TCU_TESR_TCST3         (1 << 3)
+#define TCU_TESR_TCST2         (1 << 2)
+#define TCU_TESR_TCST1         (1 << 1)
+#define TCU_TESR_TCST0         (1 << 0)
+
+#define TCU_TECR_TCCL5         (1 << 5)
+#define TCU_TECR_TCCL4         (1 << 4)
+#define TCU_TECR_TCCL3         (1 << 3)
+#define TCU_TECR_TCCL2         (1 << 2)
+#define TCU_TECR_TCCL1         (1 << 1)
+#define TCU_TECR_TCCL0         (1 << 0)
+
+#define TCU_TFR_HFLAG5         (1 << 21)
+#define TCU_TFR_HFLAG4         (1 << 20)
+#define TCU_TFR_HFLAG3         (1 << 19)
+#define TCU_TFR_HFLAG2         (1 << 18)
+#define TCU_TFR_HFLAG1         (1 << 17)
+#define TCU_TFR_HFLAG0         (1 << 16)
+#define TCU_TFR_FFLAG5         (1 << 5)
+#define TCU_TFR_FFLAG4         (1 << 4)
+#define TCU_TFR_FFLAG3         (1 << 3)
+#define TCU_TFR_FFLAG2         (1 << 2)
+#define TCU_TFR_FFLAG1         (1 << 1)
+#define TCU_TFR_FFLAG0         (1 << 0)
+
+#define TCU_TFSR_HFLAG5                (1 << 21)
+#define TCU_TFSR_HFLAG4                (1 << 20)
+#define TCU_TFSR_HFLAG3                (1 << 19)
+#define TCU_TFSR_HFLAG2                (1 << 18)
+#define TCU_TFSR_HFLAG1                (1 << 17)
+#define TCU_TFSR_HFLAG0                (1 << 16)
+#define TCU_TFSR_FFLAG5                (1 << 5)
+#define TCU_TFSR_FFLAG4                (1 << 4)
+#define TCU_TFSR_FFLAG3                (1 << 3)
+#define TCU_TFSR_FFLAG2                (1 << 2)
+#define TCU_TFSR_FFLAG1                (1 << 1)
+#define TCU_TFSR_FFLAG0                (1 << 0)
+
+#define TCU_TFCR_HFLAG5                (1 << 21)
+#define TCU_TFCR_HFLAG4                (1 << 20)
+#define TCU_TFCR_HFLAG3                (1 << 19)
+#define TCU_TFCR_HFLAG2                (1 << 18)
+#define TCU_TFCR_HFLAG1                (1 << 17)
+#define TCU_TFCR_HFLAG0                (1 << 16)
+#define TCU_TFCR_FFLAG5                (1 << 5)
+#define TCU_TFCR_FFLAG4                (1 << 4)
+#define TCU_TFCR_FFLAG3                (1 << 3)
+#define TCU_TFCR_FFLAG2                (1 << 2)
+#define TCU_TFCR_FFLAG1                (1 << 1)
+#define TCU_TFCR_FFLAG0                (1 << 0)
+
+#define TCU_TMR_HMASK5         (1 << 21)
+#define TCU_TMR_HMASK4         (1 << 20)
+#define TCU_TMR_HMASK3         (1 << 19)
+#define TCU_TMR_HMASK2         (1 << 18)
+#define TCU_TMR_HMASK1         (1 << 17)
+#define TCU_TMR_HMASK0         (1 << 16)
+#define TCU_TMR_FMASK5         (1 << 5)
+#define TCU_TMR_FMASK4         (1 << 4)
+#define TCU_TMR_FMASK3         (1 << 3)
+#define TCU_TMR_FMASK2         (1 << 2)
+#define TCU_TMR_FMASK1         (1 << 1)
+#define TCU_TMR_FMASK0         (1 << 0)
+
+#define TCU_TMSR_HMST5         (1 << 21)
+#define TCU_TMSR_HMST4         (1 << 20)
+#define TCU_TMSR_HMST3         (1 << 19)
+#define TCU_TMSR_HMST2         (1 << 18)
+#define TCU_TMSR_HMST1         (1 << 17)
+#define TCU_TMSR_HMST0         (1 << 16)
+#define TCU_TMSR_FMST5         (1 << 5)
+#define TCU_TMSR_FMST4         (1 << 4)
+#define TCU_TMSR_FMST3         (1 << 3)
+#define TCU_TMSR_FMST2         (1 << 2)
+#define TCU_TMSR_FMST1         (1 << 1)
+#define TCU_TMSR_FMST0         (1 << 0)
+
+#define TCU_TMCR_HMCL5         (1 << 21)
+#define TCU_TMCR_HMCL4         (1 << 20)
+#define TCU_TMCR_HMCL3         (1 << 19)
+#define TCU_TMCR_HMCL2         (1 << 18)
+#define TCU_TMCR_HMCL1         (1 << 17)
+#define TCU_TMCR_HMCL0         (1 << 16)
+#define TCU_TMCR_FMCL5         (1 << 5)
+#define TCU_TMCR_FMCL4         (1 << 4)
+#define TCU_TMCR_FMCL3         (1 << 3)
+#define TCU_TMCR_FMCL2         (1 << 2)
+#define TCU_TMCR_FMCL1         (1 << 1)
+#define TCU_TMCR_FMCL0         (1 << 0)
+
+#define TCU_TSR_WDTS           (1 << 16)
+#define TCU_TSR_STOP5          (1 << 5)
+#define TCU_TSR_STOP4          (1 << 4)
+#define TCU_TSR_STOP3          (1 << 3)
+#define TCU_TSR_STOP2          (1 << 2)
+#define TCU_TSR_STOP1          (1 << 1)
+#define TCU_TSR_STOP0          (1 << 0)
+
+#define TCU_TSSR_WDTSS         (1 << 16)
+#define TCU_TSSR_STPS5         (1 << 5)
+#define TCU_TSSR_STPS4         (1 << 4)
+#define TCU_TSSR_STPS3         (1 << 3)
+#define TCU_TSSR_STPS2         (1 << 2)
+#define TCU_TSSR_STPS1         (1 << 1)
+#define TCU_TSSR_STPS0         (1 << 0)
+
+#define TCU_TSSR_WDTSC         (1 << 16)
+#define TCU_TSSR_STPC5         (1 << 5)
+#define TCU_TSSR_STPC4         (1 << 4)
+#define TCU_TSSR_STPC3         (1 << 3)
+#define TCU_TSSR_STPC2         (1 << 2)
+#define TCU_TSSR_STPC1         (1 << 1)
+#define TCU_TSSR_STPC0         (1 << 0)
+
+
+/*
+ * WDT (WatchDog Timer)
+ */
+#define WDT_TDR                (WDT_BASE + 0x00)
+#define WDT_TCER       (WDT_BASE + 0x04)
+#define WDT_TCNT       (WDT_BASE + 0x08)
+#define WDT_TCSR       (WDT_BASE + 0x0C)
+
+#define REG_WDT_TDR    REG16(WDT_TDR)
+#define REG_WDT_TCER   REG8(WDT_TCER)
+#define REG_WDT_TCNT   REG16(WDT_TCNT)
+#define REG_WDT_TCSR   REG16(WDT_TCSR)
+
+/* Register definition */
+#define WDT_TCSR_PRESCALE_BIT  3
+#define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT)
+  #define WDT_TCSR_PRESCALE1   (0x0 << WDT_TCSR_PRESCALE_BIT)
+  #define WDT_TCSR_PRESCALE4   (0x1 << WDT_TCSR_PRESCALE_BIT)
+  #define WDT_TCSR_PRESCALE16  (0x2 << WDT_TCSR_PRESCALE_BIT)
+  #define WDT_TCSR_PRESCALE64  (0x3 << WDT_TCSR_PRESCALE_BIT)
+  #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT)
+  #define WDT_TCSR_PRESCALE1024        (0x5 << WDT_TCSR_PRESCALE_BIT)
+#define WDT_TCSR_EXT_EN                (1 << 2)
+#define WDT_TCSR_RTC_EN                (1 << 1)
+#define WDT_TCSR_PCK_EN                (1 << 0)
+
+#define WDT_TCER_TCEN          (1 << 0)
+
+
+/*
+ * DMAC (DMA Controller)
+ */
+
+#define MAX_DMA_NUM    6  /* max 6 channels */
+
+#define DMAC_DSAR(n)   (DMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */
+#define DMAC_DTAR(n)   (DMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */
+#define DMAC_DTCR(n)   (DMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */
+#define DMAC_DRSR(n)   (DMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */
+#define DMAC_DCCSR(n)  (DMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */
+#define DMAC_DCMD(n)   (DMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */
+#define DMAC_DDA(n)    (DMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */
+#define DMAC_DMACR     (DMAC_BASE + 0x0300)              /* DMA control register */
+#define DMAC_DMAIPR    (DMAC_BASE + 0x0304)              /* DMA interrupt pending */
+#define DMAC_DMADBR    (DMAC_BASE + 0x0308)              /* DMA doorbell */
+#define DMAC_DMADBSR   (DMAC_BASE + 0x030C)              /* DMA doorbell set */
+
+/* channel 0 */
+#define DMAC_DSAR0      DMAC_DSAR(0)
+#define DMAC_DTAR0      DMAC_DTAR(0)
+#define DMAC_DTCR0      DMAC_DTCR(0)
+#define DMAC_DRSR0      DMAC_DRSR(0)
+#define DMAC_DCCSR0     DMAC_DCCSR(0)
+#define DMAC_DCMD0     DMAC_DCMD(0)
+#define DMAC_DDA0      DMAC_DDA(0)
+
+/* channel 1 */
+#define DMAC_DSAR1      DMAC_DSAR(1)
+#define DMAC_DTAR1      DMAC_DTAR(1)
+#define DMAC_DTCR1      DMAC_DTCR(1)
+#define DMAC_DRSR1      DMAC_DRSR(1)
+#define DMAC_DCCSR1     DMAC_DCCSR(1)
+#define DMAC_DCMD1     DMAC_DCMD(1)
+#define DMAC_DDA1      DMAC_DDA(1)
+
+/* channel 2 */
+#define DMAC_DSAR2      DMAC_DSAR(2)
+#define DMAC_DTAR2      DMAC_DTAR(2)
+#define DMAC_DTCR2      DMAC_DTCR(2)
+#define DMAC_DRSR2      DMAC_DRSR(2)
+#define DMAC_DCCSR2     DMAC_DCCSR(2)
+#define DMAC_DCMD2     DMAC_DCMD(2)
+#define DMAC_DDA2      DMAC_DDA(2)
+
+/* channel 3 */
+#define DMAC_DSAR3      DMAC_DSAR(3)
+#define DMAC_DTAR3      DMAC_DTAR(3)
+#define DMAC_DTCR3      DMAC_DTCR(3)
+#define DMAC_DRSR3      DMAC_DRSR(3)
+#define DMAC_DCCSR3     DMAC_DCCSR(3)
+#define DMAC_DCMD3     DMAC_DCMD(3)
+#define DMAC_DDA3      DMAC_DDA(3)
+
+/* channel 4 */
+#define DMAC_DSAR4      DMAC_DSAR(4)
+#define DMAC_DTAR4      DMAC_DTAR(4)
+#define DMAC_DTCR4      DMAC_DTCR(4)
+#define DMAC_DRSR4      DMAC_DRSR(4)
+#define DMAC_DCCSR4     DMAC_DCCSR(4)
+#define DMAC_DCMD4     DMAC_DCMD(4)
+#define DMAC_DDA4      DMAC_DDA(4)
+
+/* channel 5 */
+#define DMAC_DSAR5      DMAC_DSAR(5)
+#define DMAC_DTAR5      DMAC_DTAR(5)
+#define DMAC_DTCR5      DMAC_DTCR(5)
+#define DMAC_DRSR5      DMAC_DRSR(5)
+#define DMAC_DCCSR5     DMAC_DCCSR(5)
+#define DMAC_DCMD5     DMAC_DCMD(5)
+#define DMAC_DDA5      DMAC_DDA(5)
+
+#define REG_DMAC_DSAR(n)       REG32(DMAC_DSAR((n)))
+#define REG_DMAC_DTAR(n)       REG32(DMAC_DTAR((n)))
+#define REG_DMAC_DTCR(n)       REG32(DMAC_DTCR((n)))
+#define REG_DMAC_DRSR(n)       REG32(DMAC_DRSR((n)))
+#define REG_DMAC_DCCSR(n)      REG32(DMAC_DCCSR((n)))
+#define REG_DMAC_DCMD(n)       REG32(DMAC_DCMD((n)))
+#define REG_DMAC_DDA(n)                REG32(DMAC_DDA((n)))
+#define REG_DMAC_DMACR         REG32(DMAC_DMACR)
+#define REG_DMAC_DMAIPR                REG32(DMAC_DMAIPR)
+#define REG_DMAC_DMADBR                REG32(DMAC_DMADBR)
+#define REG_DMAC_DMADBSR       REG32(DMAC_DMADBSR)
+
+/* DMA request source register */
+#define DMAC_DRSR_RS_BIT       0
+#define DMAC_DRSR_RS_MASK      (0x1f << DMAC_DRSR_RS_BIT)
+#define DMAC_DRSR_RS_AUTO      (8 << DMAC_DRSR_RS_BIT)
+#define DMAC_DRSR_RS_UART0OUT  (20 << DMAC_DRSR_RS_BIT)
+#define DMAC_DRSR_RS_UART0IN   (21 << DMAC_DRSR_RS_BIT)
+#define DMAC_DRSR_RS_SSIOUT    (22 << DMAC_DRSR_RS_BIT)
+#define DMAC_DRSR_RS_SSIIN     (23 << DMAC_DRSR_RS_BIT)
+#define DMAC_DRSR_RS_AICOUT    (24 << DMAC_DRSR_RS_BIT)
+#define DMAC_DRSR_RS_AICIN     (25 << DMAC_DRSR_RS_BIT)
+#define DMAC_DRSR_RS_MSCOUT    (26 << DMAC_DRSR_RS_BIT)
+#define DMAC_DRSR_RS_MSCIN     (27 << DMAC_DRSR_RS_BIT)
+#define DMAC_DRSR_RS_TCU       (28 << DMAC_DRSR_RS_BIT)
+#define DMAC_DRSR_RS_SADC      (29 << DMAC_DRSR_RS_BIT)
+#define DMAC_DRSR_RS_SLCD      (30 << DMAC_DRSR_RS_BIT)
+
+/* DMA channel control/status register */
+#define DMAC_DCCSR_NDES                (1 << 31) /* descriptor (0) or not (1) ? */
+#define DMAC_DCCSR_CDOA_BIT    16        /* copy of DMA offset address */
+#define DMAC_DCCSR_CDOA_MASK   (0xff << DMAC_DCCSR_CDOA_BIT)
+#define DMAC_DCCSR_INV         (1 << 6)  /* descriptor invalid */
+#define DMAC_DCCSR_AR          (1 << 4)  /* address error */
+#define DMAC_DCCSR_TT          (1 << 3)  /* transfer terminated */
+#define DMAC_DCCSR_HLT         (1 << 2)  /* DMA halted */
+#define DMAC_DCCSR_CT          (1 << 1)  /* count terminated */
+#define DMAC_DCCSR_EN          (1 << 0)  /* channel enable bit */
+
+/* DMA channel command register  */
+#define DMAC_DCMD_SAI          (1 << 23) /* source address increment */
+#define DMAC_DCMD_DAI          (1 << 22) /* dest address increment */
+#define DMAC_DCMD_RDIL_BIT     16        /* request detection interval length */
+#define DMAC_DCMD_RDIL_MASK    (0x0f << DMAC_DCMD_RDIL_BIT)
+  #define DMAC_DCMD_RDIL_IGN   (0 << DMAC_DCMD_RDIL_BIT)
+  #define DMAC_DCMD_RDIL_2     (1 << DMAC_DCMD_RDIL_BIT)
+  #define DMAC_DCMD_RDIL_4     (2 << DMAC_DCMD_RDIL_BIT)
+  #define DMAC_DCMD_RDIL_8     (3 << DMAC_DCMD_RDIL_BIT)
+  #define DMAC_DCMD_RDIL_12    (4 << DMAC_DCMD_RDIL_BIT)
+  #define DMAC_DCMD_RDIL_16    (5 << DMAC_DCMD_RDIL_BIT)
+  #define DMAC_DCMD_RDIL_20    (6 << DMAC_DCMD_RDIL_BIT)
+  #define DMAC_DCMD_RDIL_24    (7 << DMAC_DCMD_RDIL_BIT)
+  #define DMAC_DCMD_RDIL_28    (8 << DMAC_DCMD_RDIL_BIT)
+  #define DMAC_DCMD_RDIL_32    (9 << DMAC_DCMD_RDIL_BIT)
+  #define DMAC_DCMD_RDIL_48    (10 << DMAC_DCMD_RDIL_BIT)
+  #define DMAC_DCMD_RDIL_60    (11 << DMAC_DCMD_RDIL_BIT)
+  #define DMAC_DCMD_RDIL_64    (12 << DMAC_DCMD_RDIL_BIT)
+  #define DMAC_DCMD_RDIL_124   (13 << DMAC_DCMD_RDIL_BIT)
+  #define DMAC_DCMD_RDIL_128   (14 << DMAC_DCMD_RDIL_BIT)
+  #define DMAC_DCMD_RDIL_200   (15 << DMAC_DCMD_RDIL_BIT)
+#define DMAC_DCMD_SWDH_BIT     14  /* source port width */
+#define DMAC_DCMD_SWDH_MASK    (0x03 << DMAC_DCMD_SWDH_BIT)
+  #define DMAC_DCMD_SWDH_32    (0 << DMAC_DCMD_SWDH_BIT)
+  #define DMAC_DCMD_SWDH_8     (1 << DMAC_DCMD_SWDH_BIT)
+  #define DMAC_DCMD_SWDH_16    (2 << DMAC_DCMD_SWDH_BIT)
+#define DMAC_DCMD_DWDH_BIT     12  /* dest port width */
+#define DMAC_DCMD_DWDH_MASK    (0x03 << DMAC_DCMD_DWDH_BIT)
+  #define DMAC_DCMD_DWDH_32    (0 << DMAC_DCMD_DWDH_BIT)
+  #define DMAC_DCMD_DWDH_8     (1 << DMAC_DCMD_DWDH_BIT)
+  #define DMAC_DCMD_DWDH_16    (2 << DMAC_DCMD_DWDH_BIT)
+#define DMAC_DCMD_DS_BIT       8  /* transfer data size of a data unit */
+#define DMAC_DCMD_DS_MASK      (0x07 << DMAC_DCMD_DS_BIT)
+  #define DMAC_DCMD_DS_32BIT   (0 << DMAC_DCMD_DS_BIT)
+  #define DMAC_DCMD_DS_8BIT    (1 << DMAC_DCMD_DS_BIT)
+  #define DMAC_DCMD_DS_16BIT   (2 << DMAC_DCMD_DS_BIT)
+  #define DMAC_DCMD_DS_16BYTE  (3 << DMAC_DCMD_DS_BIT)
+  #define DMAC_DCMD_DS_32BYTE  (4 << DMAC_DCMD_DS_BIT)
+#define DMAC_DCMD_TM           (1 << 7)  /* transfer mode: 0-single 1-block */
+#define DMAC_DCMD_DES_V                (1 << 4)  /* descriptor valid flag */
+#define DMAC_DCMD_DES_VM       (1 << 3)  /* descriptor valid mask: 1:support V-bit */
+#define DMAC_DCMD_DES_VIE      (1 << 2)  /* DMA valid error interrupt enable */
+#define DMAC_DCMD_TIE          (1 << 1)  /* DMA transfer interrupt enable */
+#define DMAC_DCMD_LINK         (1 << 0)  /* descriptor link enable */
+
+/* DMA descriptor address register */
+#define DMAC_DDA_BASE_BIT      12  /* descriptor base address */
+#define DMAC_DDA_BASE_MASK     (0x0fffff << DMAC_DDA_BASE_BIT)
+#define DMAC_DDA_OFFSET_BIT    4  /* descriptor offset address */
+#define DMAC_DDA_OFFSET_MASK   (0x0ff << DMAC_DDA_OFFSET_BIT)
+
+/* DMA control register */
+#define DMAC_DMACR_PR_BIT      8  /* channel priority mode */
+#define DMAC_DMACR_PR_MASK     (0x03 << DMAC_DMACR_PR_BIT)
+  #define DMAC_DMACR_PR_012345 (0 << DMAC_DMACR_PR_BIT)
+  #define DMAC_DMACR_PR_023145 (1 << DMAC_DMACR_PR_BIT)
+  #define DMAC_DMACR_PR_201345 (2 << DMAC_DMACR_PR_BIT)
+  #define DMAC_DMACR_PR_RR     (3 << DMAC_DMACR_PR_BIT) /* round robin */
+#define DMAC_DMACR_HLT         (1 << 3)  /* DMA halt flag */
+#define DMAC_DMACR_AR          (1 << 2)  /* address error flag */
+#define DMAC_DMACR_DMAE                (1 << 0)  /* DMA enable bit */
+
+/* DMA doorbell register */
+#define DMAC_DMADBR_DB5                (1 << 5)  /* doorbell for channel 5 */
+#define DMAC_DMADBR_DB4                (1 << 5)  /* doorbell for channel 4 */
+#define DMAC_DMADBR_DB3                (1 << 5)  /* doorbell for channel 3 */
+#define DMAC_DMADBR_DB2                (1 << 5)  /* doorbell for channel 2 */
+#define DMAC_DMADBR_DB1                (1 << 5)  /* doorbell for channel 1 */
+#define DMAC_DMADBR_DB0                (1 << 5)  /* doorbell for channel 0 */
+
+/* DMA doorbell set register */
+#define DMAC_DMADBSR_DBS5      (1 << 5)  /* enable doorbell for channel 5 */
+#define DMAC_DMADBSR_DBS4      (1 << 5)  /* enable doorbell for channel 4 */
+#define DMAC_DMADBSR_DBS3      (1 << 5)  /* enable doorbell for channel 3 */
+#define DMAC_DMADBSR_DBS2      (1 << 5)  /* enable doorbell for channel 2 */
+#define DMAC_DMADBSR_DBS1      (1 << 5)  /* enable doorbell for channel 1 */
+#define DMAC_DMADBSR_DBS0      (1 << 5)  /* enable doorbell for channel 0 */
+
+/* DMA interrupt pending register */
+#define DMAC_DMAIPR_CIRQ5      (1 << 5)  /* irq pending status for channel 5 */
+#define DMAC_DMAIPR_CIRQ4      (1 << 4)  /* irq pending status for channel 4 */
+#define DMAC_DMAIPR_CIRQ3      (1 << 3)  /* irq pending status for channel 3 */
+#define DMAC_DMAIPR_CIRQ2      (1 << 2)  /* irq pending status for channel 2 */
+#define DMAC_DMAIPR_CIRQ1      (1 << 1)  /* irq pending status for channel 1 */
+#define DMAC_DMAIPR_CIRQ0      (1 << 0)  /* irq pending status for channel 0 */
+
+
+/*************************************************************************
+ * GPIO (General-Purpose I/O Ports)
+ *************************************************************************/
+#define MAX_GPIO_NUM   128
+
+/*  = 0,1,2,3 */
+#define GPIO_PXPIN(n)  (GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */
+#define GPIO_PXDAT(n)  (GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */
+#define GPIO_PXDATS(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */
+#define GPIO_PXDATC(n) (GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */
+#define GPIO_PXIM(n)   (GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */
+#define GPIO_PXIMS(n)  (GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */
+#define GPIO_PXIMC(n)  (GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */
+#define GPIO_PXPE(n)   (GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */
+#define GPIO_PXPES(n)  (GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */
+#define GPIO_PXPEC(n)  (GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */
+#define GPIO_PXFUN(n)  (GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */
+#define GPIO_PXFUNS(n) (GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */
+#define GPIO_PXFUNC(n) (GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */
+#define GPIO_PXSEL(n)  (GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */
+#define GPIO_PXSELS(n) (GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */
+#define GPIO_PXSELC(n) (GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */
+#define GPIO_PXDIR(n)  (GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */
+#define GPIO_PXDIRS(n) (GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */
+#define GPIO_PXDIRC(n) (GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */
+#define GPIO_PXTRG(n)  (GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */
+#define GPIO_PXTRGS(n) (GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */
+#define GPIO_PXTRGC(n) (GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Set Register */
+#define GPIO_PXFLG(n)  (GPIO_BASE + (0x80 + (n)*0x100)) /* Port Flag Register */
+#define GPIO_PXFLGC(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Flag clear Register */
+
+#define REG_GPIO_PXPIN(n)      REG32(GPIO_PXPIN((n)))  /* PIN level */
+#define REG_GPIO_PXDAT(n)      REG32(GPIO_PXDAT((n)))  /* 1: interrupt pending */
+#define REG_GPIO_PXDATS(n)     REG32(GPIO_PXDATS((n)))
+#define REG_GPIO_PXDATC(n)     REG32(GPIO_PXDATC((n)))
+#define REG_GPIO_PXIM(n)       REG32(GPIO_PXIM((n)))   /* 1: mask pin interrupt */
+#define REG_GPIO_PXIMS(n)      REG32(GPIO_PXIMS((n)))
+#define REG_GPIO_PXIMC(n)      REG32(GPIO_PXIMC((n)))
+#define REG_GPIO_PXPE(n)       REG32(GPIO_PXPE((n)))   /* 1: disable pull up/down */
+#define REG_GPIO_PXPES(n)      REG32(GPIO_PXPES((n)))
+#define REG_GPIO_PXPEC(n)      REG32(GPIO_PXPEC((n)))
+#define REG_GPIO_PXFUN(n)      REG32(GPIO_PXFUN((n)))  /* 0:GPIO or intr, 1:FUNC */
+#define REG_GPIO_PXFUNS(n)     REG32(GPIO_PXFUNS((n)))
+#define REG_GPIO_PXFUNC(n)     REG32(GPIO_PXFUNC((n)))
+#define REG_GPIO_PXSEL(n)      REG32(GPIO_PXSEL((n))) /* 0:GPIO/Fun0,1:intr/fun1*/
+#define REG_GPIO_PXSELS(n)     REG32(GPIO_PXSELS((n)))
+#define REG_GPIO_PXSELC(n)     REG32(GPIO_PXSELC((n)))
+#define REG_GPIO_PXDIR(n)      REG32(GPIO_PXDIR((n))) /* 0:input/low-level-trig/falling-edge-trig, 1:output/high-level-trig/rising-edge-trig */
+#define REG_GPIO_PXDIRS(n)     REG32(GPIO_PXDIRS((n)))
+#define REG_GPIO_PXDIRC(n)     REG32(GPIO_PXDIRC((n)))
+#define REG_GPIO_PXTRG(n)      REG32(GPIO_PXTRG((n))) /* 0:level-trigger, 1:edge-trigger */
+#define REG_GPIO_PXTRGS(n)     REG32(GPIO_PXTRGS((n)))
+#define REG_GPIO_PXTRGC(n)     REG32(GPIO_PXTRGC((n)))
+#define REG_GPIO_PXFLG(n)      REG32(GPIO_PXFLG((n))) /* interrupt flag */
+#define REG_GPIO_PXFLGC(n)     REG32(GPIO_PXFLGC((n))) /* interrupt flag */
+
+
+/*************************************************************************
+ * UART
+ *************************************************************************/
+
+#define IRDA_BASE      UART0_BASE
+#define UART_BASE      UART0_BASE
+#define UART_OFF       0x1000
+
+/* Register Offset */
+#define OFF_RDR                (0x00)  /* R  8b H'xx */
+#define OFF_TDR                (0x00)  /* W  8b H'xx */
+#define OFF_DLLR       (0x00)  /* RW 8b H'00 */
+#define OFF_DLHR       (0x04)  /* RW 8b H'00 */
+#define OFF_IER                (0x04)  /* RW 8b H'00 */
+#define OFF_ISR                (0x08)  /* R  8b H'01 */
+#define OFF_FCR                (0x08)  /* W  8b H'00 */
+#define OFF_LCR                (0x0C)  /* RW 8b H'00 */
+#define OFF_MCR                (0x10)  /* RW 8b H'00 */
+#define OFF_LSR                (0x14)  /* R  8b H'00 */
+#define OFF_MSR                (0x18)  /* R  8b H'00 */
+#define OFF_SPR                (0x1C)  /* RW 8b H'00 */
+#define OFF_SIRCR      (0x20)  /* RW 8b H'00, UART0 */
+#define OFF_UMR                (0x24)  /* RW 8b H'00, UART M Register */
+#define OFF_UACR       (0x28)  /* RW 8b H'00, UART Add Cycle Register */
+
+/* Register Address */
+#define UART0_RDR      (UART0_BASE + OFF_RDR)
+#define UART0_TDR      (UART0_BASE + OFF_TDR)
+#define UART0_DLLR     (UART0_BASE + OFF_DLLR)
+#define UART0_DLHR     (UART0_BASE + OFF_DLHR)
+#define UART0_IER      (UART0_BASE + OFF_IER)
+#define UART0_ISR      (UART0_BASE + OFF_ISR)
+#define UART0_FCR      (UART0_BASE + OFF_FCR)
+#define UART0_LCR      (UART0_BASE + OFF_LCR)
+#define UART0_MCR      (UART0_BASE + OFF_MCR)
+#define UART0_LSR      (UART0_BASE + OFF_LSR)
+#define UART0_MSR      (UART0_BASE + OFF_MSR)
+#define UART0_SPR      (UART0_BASE + OFF_SPR)
+#define UART0_SIRCR    (UART0_BASE + OFF_SIRCR)
+#define UART0_UMR      (UART0_BASE + OFF_UMR)
+#define UART0_UACR     (UART0_BASE + OFF_UACR)
+
+/*
+ * Define macros for UART_IER
+ * UART Interrupt Enable Register
+ */
+#define UART_IER_RIE   (1 << 0)        /* 0: receive fifo "full" interrupt disable */
+#define UART_IER_TIE   (1 << 1)        /* 0: transmit fifo "empty" interrupt disable */
+#define UART_IER_RLIE  (1 << 2)        /* 0: receive line status interrupt disable */
+#define UART_IER_MIE   (1 << 3)        /* 0: modem status interrupt disable */
+#define UART_IER_RTIE  (1 << 4)        /* 0: receive timeout interrupt disable */
+
+/*
+ * Define macros for UART_ISR
+ * UART Interrupt Status Register
+ */
+#define UART_ISR_IP    (1 << 0)        /* 0: interrupt is pending  1: no interrupt */
+#define UART_ISR_IID   (7 << 1)        /* Source of Interrupt */
+#define UART_ISR_IID_MSI               (0 << 1)        /* Modem status interrupt */
+#define UART_ISR_IID_THRI      (1 << 1)        /* Transmitter holding register empty */
+#define UART_ISR_IID_RDI               (2 << 1)        /* Receiver data interrupt */
+#define UART_ISR_IID_RLSI      (3 << 1)        /* Receiver line status interrupt */
+#define UART_ISR_FFMS  (3 << 6)        /* FIFO mode select, set when UART_FCR.FE is set to 1 */
+#define UART_ISR_FFMS_NO_FIFO  (0 << 6)
+#define UART_ISR_FFMS_FIFO_MODE        (3 << 6)
+
+/*
+ * Define macros for UART_FCR
+ * UART FIFO Control Register
+ */
+#define UART_FCR_FE    (1 << 0)        /* 0: non-FIFO mode  1: FIFO mode */
+#define UART_FCR_RFLS  (1 << 1)        /* write 1 to flush receive FIFO */
+#define UART_FCR_TFLS  (1 << 2)        /* write 1 to flush transmit FIFO */
+#define UART_FCR_DMS   (1 << 3)        /* 0: disable DMA mode */
+#define UART_FCR_UUE   (1 << 4)        /* 0: disable UART */
+#define UART_FCR_RTRG  (3 << 6)        /* Receive FIFO Data Trigger */
+#define UART_FCR_RTRG_1        (0 << 6)
+#define UART_FCR_RTRG_4