revert some breakage
authorJohn Crispin <john@openwrt.org>
Sat, 12 Jan 2008 12:07:33 +0000 (12:07 +0000)
committerJohn Crispin <john@openwrt.org>
Sat, 12 Jan 2008 12:07:33 +0000 (12:07 +0000)
SVN-Revision: 10176

target/linux/ifxmips/files/arch/mips/ifxmips/prom.c
target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h

index a3b62f0..514c879 100644 (file)
 #include <asm/bootinfo.h>
 #include <asm/ifxmips/ifxmips.h>
 
-#ifdef CONFIG_IFXMIPS_USE_CONSOLE0
-#define ASC_OFFSET                                                     0
-#elif CONFIG_IFXMIPS_USE_CONSOLE1
-#define ASC_OFFSET                                                     IFXMIPS_ASC1_BASE_OFFSET
-#else
-#error a tty for the console must be selected
-#endif
 static char buf[1024];
 
 void
@@ -46,11 +39,11 @@ prom_free_prom_memory (void)
 void
 prom_putchar (char c)
 {
-       while ((readl(IFXMIPS_ASC0_FSTAT + ASC_OFFSET) & ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF);
+       while ((readl(IFXMIPS_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF);
 
        if (c == '\n')
-               writel('\r', IFXMIPS_ASC0_TBUF + ASC_OFFSET);
-       writel(c, IFXMIPS_ASC0_TBUF + ASC_OFFSET);
+               writel('\r', IFXMIPS_ASC1_TBUF);
+       writel(c, IFXMIPS_ASC1_TBUF);
 }
 
 void
index c9fa3d4..3575596 100644 (file)
 #define IFXMIPS_FLASH_MAX       0x2000000
 
 
-/*------------ ASC0 */
+/*------------ ASC1 */
 
-#define IFXMIPS_ASC0_BASE_ADDR         (KSEG1 + 0x1E400C00)
-#define IFXMIPS_ASC1_BASE_OFFSET       ((0x1E100C00 - 0x1E400C00) / sizeof(u32))
+#define IFXMIPS_ASC1_BASE_ADDR (KSEG1 + 0x1E100C00)
 
 /* FIFO status register */
-#define IFXMIPS_ASC0_FSTAT             ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x0048))
+#define IFXMIPS_ASC1_FSTAT             ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0048))
 #define ASCFSTAT_TXFFLMASK             0x3F00
 #define ASCFSTAT_TXFFLOFF              8
 
 /* ASC1 transmit buffer */
-#define IFXMIPS_ASC0_TBUF              ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x0020))
+#define IFXMIPS_ASC1_TBUF              ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0020))
 
 /* channel operating modes */
 #define ASCOPT_CSIZE                   0x3
 #define ASCOPT_CREAD                   0x20
 
 /* hardware modified control register */
-#define IFXMIPS_ASC0_WHBSTATE  ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x0018))
+#define IFXMIPS_ASC1_WHBSTATE  ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0018))
 
 /* receive buffer register */
-#define IFXMIPS_ASC0_RBUF              ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x0024))
+#define IFXMIPS_ASC1_RBUF              ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0024))
 
 /* status register */
-#define IFXMIPS_ASC0_STATE             ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x0014))
+#define IFXMIPS_ASC1_STATE             ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0014))
 
 /* interrupt control */
-#define IFXMIPS_ASC0_IRNCR             ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x00F8))
+#define IFXMIPS_ASC1_IRNCR             ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x00F8))
 
 #define ASC_IRNCR_TIR                  0x4
 #define ASC_IRNCR_RIR                  0x2
 #define ASC_IRNCR_EIR                  0x4
 
 /* clock control */
-#define IFXMIPS_ASC0_CLC                       ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x0000))
+#define IFXMIPS_ASC1_CLC                       ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0000))
 
-#define IFXMIPS_ASC0_CLC_DISS  0x2
+#define IFXMIPS_ASC1_CLC_DISS  0x2
 
 /* port input select register */
-#define IFXMIPS_ASC0_PISEL             ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x0004))
+#define IFXMIPS_ASC1_PISEL             ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0004))
 
 /* tx fifo */
-#define IFXMIPS_ASC0_TXFCON            ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x0044))
+#define IFXMIPS_ASC1_TXFCON            ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0044))
 
 /* rx fifo */
-#define IFXMIPS_ASC0_RXFCON            ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x0040))
+#define IFXMIPS_ASC1_RXFCON            ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0040))
 
 /* control */
-#define IFXMIPS_ASC0_CON                       ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x0010))
+#define IFXMIPS_ASC1_CON                       ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0010))
 
 /* timer reload */
-#define IFXMIPS_ASC0_BG                        ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x0050))
+#define IFXMIPS_ASC1_BG                        ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x0050))
 
 /* int enable */
-#define IFXMIPS_ASC0_IRNREN            ((u32*)(IFXMIPS_ASC0_BASE_ADDR + 0x00F4))
+#define IFXMIPS_ASC1_IRNREN            ((u32*)(IFXMIPS_ASC1_BASE_ADDR + 0x00F4))
 
 #define ASC_IRNREN_RX_BUF              0x8
 #define ASC_IRNREN_TX_BUF              0x4