ar71xx: add support for Compex WPJ342
authorJohn Crispin <john@openwrt.org>
Sat, 9 Apr 2016 10:26:41 +0000 (10:26 +0000)
committerJohn Crispin <john@openwrt.org>
Sat, 9 Apr 2016 10:26:41 +0000 (10:26 +0000)
OpenWrt can be flashed with following uboot commands:

tftpboot 0x80500000 openwrt-ar71xx-generic-wpj342-16M-squashfs-sysupgrade.bin
erase 0x9f030000 +$filesize
cp.b $fileaddr 0x9f030000 $filesize

Signed-off-by: Christian Mehlis <christian@m3hlis.de>
SVN-Revision: 49157

13 files changed:
target/linux/ar71xx/base-files/etc/board.d/02_network
target/linux/ar71xx/base-files/etc/diag.sh
target/linux/ar71xx/base-files/lib/ar71xx.sh
target/linux/ar71xx/base-files/lib/upgrade/platform.sh
target/linux/ar71xx/config-4.1
target/linux/ar71xx/config-4.4
target/linux/ar71xx/files/arch/mips/ath79/Kconfig.openwrt
target/linux/ar71xx/files/arch/mips/ath79/Makefile
target/linux/ar71xx/files/arch/mips/ath79/mach-wpj342.c [new file with mode: 0644]
target/linux/ar71xx/files/arch/mips/ath79/machtypes.h
target/linux/ar71xx/generic/profiles/compex.mk
target/linux/ar71xx/image/Makefile
target/linux/ar71xx/mikrotik/config-default

index bd488a2..c6a2014 100755 (executable)
@@ -405,6 +405,11 @@ gl-ar300)
                "0@eth1" "1:lan" "2:lan" "3:lan" "4:lan"
        ;;
 
+wpj342)
+       ucidef_add_switch "switch0" \
+               "0@eth0" "1:lan" "2:wan"
+       ;;
+
 wpj344)
        ucidef_add_switch "switch0" \
                "0@eth0" "3:lan" "2:wan"
index 783a4e6..1cf6e4c 100644 (file)
@@ -389,6 +389,9 @@ get_status_led() {
        wp543)
                status_led="wp543:green:diag"
                ;;
+       wpj342)
+               status_led="wpj342:green:sig3"
+               ;;
        wpj344)
                status_led="wpj344:green:status"
                ;;
index 9c19e23..b3eda6c 100755 (executable)
@@ -967,6 +967,9 @@ ar71xx_board_detect() {
        *WPE72)
                name="wpe72"
                ;;
+       *WPJ342)
+               name="wpj342"
+               ;;
        *WPJ344)
                name="wpj344"
                ;;
index 2d61638..86375a9 100755 (executable)
@@ -255,6 +255,7 @@ platform_check_image() {
        rw2458n | \
        wpj531 | \
        wndap360 | \
+       wpj342 | \
        wpj344 | \
        wzr-hp-g300nh2 | \
        wzr-hp-g300nh | \
index 087f027..4dbb6ae 100644 (file)
@@ -178,6 +178,7 @@ CONFIG_ATH79_MACH_WNR2000_V4=y
 CONFIG_ATH79_MACH_WNR2200=y
 CONFIG_ATH79_MACH_WP543=y
 CONFIG_ATH79_MACH_WPE72=y
+CONFIG_ATH79_MACH_WPJ342=y
 CONFIG_ATH79_MACH_WPJ344=y
 CONFIG_ATH79_MACH_WPJ531=y
 CONFIG_ATH79_MACH_WPJ558=y
index b684292..ec04c28 100644 (file)
@@ -181,6 +181,7 @@ CONFIG_ATH79_MACH_WNR2000_V4=y
 CONFIG_ATH79_MACH_WNR2200=y
 CONFIG_ATH79_MACH_WP543=y
 CONFIG_ATH79_MACH_WPE72=y
+CONFIG_ATH79_MACH_WPJ342=y
 CONFIG_ATH79_MACH_WPJ344=y
 CONFIG_ATH79_MACH_WPJ531=y
 CONFIG_ATH79_MACH_WPJ558=y
index 1d6c4d6..a884f35 100644 (file)
@@ -346,6 +346,16 @@ config ATH79_MACH_WPE72
        select ATH79_DEV_USB
        select MYLOADER
 
+config ATH79_MACH_WPJ342
+       bool "Compex WPJ342 board support"
+       select SOC_AS934X
+       select ATH79_DEV_ETH
+       select ATH79_DEV_GPIO_BUTTONS
+       select ATH79_DEV_LEDS_GPIO
+       select ATH79_DEV_M25P80
+       select ATH79_DEV_USB
+       select ATH79_DEV_WMAC
+
 config ATH79_MACH_WPJ344
        bool "Compex WPJ344 board support"
        select SOC_AS934X
index 75f1670..59cc507 100644 (file)
@@ -185,6 +185,7 @@ obj-$(CONFIG_ATH79_MACH_WNR2000_V4) += mach-wnr2000-v4.o
 obj-$(CONFIG_ATH79_MACH_WNR2200)       += mach-wnr2200.o
 obj-$(CONFIG_ATH79_MACH_WP543)         += mach-wp543.o
 obj-$(CONFIG_ATH79_MACH_WPE72)         += mach-wpe72.o
+obj-$(CONFIG_ATH79_MACH_WPJ342)        += mach-wpj342.o
 obj-$(CONFIG_ATH79_MACH_WPJ344)        += mach-wpj344.o
 obj-$(CONFIG_ATH79_MACH_WPJ531)        += mach-wpj531.o
 obj-$(CONFIG_ATH79_MACH_WPJ558)        += mach-wpj558.o
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj342.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-wpj342.c
new file mode 100644 (file)
index 0000000..8cc1e70
--- /dev/null
@@ -0,0 +1,178 @@
+/*
+ * Compex WPJ342 board support
+ *
+ * Copyright (c) 2011 Qualcomm Atheros
+ * Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include <linux/irq.h>
+#include <linux/pci.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+#include <linux/ath9k_platform.h>
+#include <linux/ar8216_platform.h>
+#include <linux/export.h>
+
+#include <asm/mach-ath79/ar71xx_regs.h>
+
+#include "pci.h"
+#include "common.h"
+#include "dev-ap9x-pci.h"
+#include "dev-eth.h"
+#include "dev-gpio-buttons.h"
+#include "dev-leds-gpio.h"
+#include "dev-m25p80.h"
+#include "dev-nfc.h"
+#include "dev-spi.h"
+#include "dev-usb.h"
+#include "dev-wmac.h"
+#include "machtypes.h"
+
+#define WPJ342_GPIO_LED_STATUS         11
+#define WPJ342_GPIO_LED_SIG1           14
+#define WPJ342_GPIO_LED_SIG2           13
+#define WPJ342_GPIO_LED_SIG3           12
+#define WPJ342_GPIO_LED_SIG4           11
+#define WPJ342_GPIO_BUZZER                     15
+
+#define WPJ342_GPIO_BTN_RESET          17
+
+#define WPJ342_KEYS_POLL_INTERVAL      20 /* msecs */
+#define WPJ342_KEYS_DEBOUNCE_INTERVAL  (3 * WPJ342_KEYS_POLL_INTERVAL)
+
+#define WPJ342_MAC0_OFFSET             0x10
+#define WPJ342_MAC1_OFFSET             0x18
+#define WPJ342_WMAC_CALDATA_OFFSET     0x1000
+#define WPJ342_PCIE_CALDATA_OFFSET     0x5000
+
+#define WPJ342_ART_SIZE                0x8000
+
+static struct gpio_led wpj342_leds_gpio[] __initdata = {
+       {
+               .name           = "wpj342:red:sig1",
+               .gpio           = WPJ342_GPIO_LED_SIG1,
+               .active_low     = 1,
+       },
+       {
+               .name           = "wpj342:yellow:sig2",
+               .gpio           = WPJ342_GPIO_LED_SIG2,
+               .active_low     = 1,
+       },
+       {
+               .name           = "wpj342:green:sig3",
+               .gpio           = WPJ342_GPIO_LED_SIG3,
+               .active_low     = 1,
+       },
+       {
+               .name           = "wpj342:green:sig4",
+               .gpio           = WPJ342_GPIO_LED_SIG4,
+               .active_low     = 1,
+       },
+       {
+               .name           = "wpj342:buzzer",
+               .gpio           = WPJ342_GPIO_BUZZER,
+               .active_low     = 0,
+       }
+};
+
+static struct gpio_keys_button wpj342_gpio_keys[] __initdata = {
+       {
+               .desc           = "reset",
+               .type           = EV_KEY,
+               .code           = KEY_RESTART,
+               .debounce_interval = WPJ342_KEYS_DEBOUNCE_INTERVAL,
+               .gpio           = WPJ342_GPIO_BTN_RESET,
+               .active_low     = 1,
+       },
+};
+
+static struct ar8327_pad_cfg wpj342_ar8327_pad0_cfg = {
+       .mode = AR8327_PAD_MAC_RGMII,
+       .txclk_delay_en = true,
+       .rxclk_delay_en = true,
+       .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
+       .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
+};
+
+static struct ar8327_led_cfg wpj342_ar8327_led_cfg = {
+       .led_ctrl0 = 0x00000000,
+       .led_ctrl1 = 0xc737c737,
+       .led_ctrl2 = 0x00000000,
+       .led_ctrl3 = 0x00c30c00,
+       .open_drain = true,
+};
+
+static struct ar8327_platform_data wpj342_ar8327_data = {
+       .pad0_cfg = &wpj342_ar8327_pad0_cfg,
+       .port0_cfg = {
+               .force_link = 1,
+               .speed = AR8327_PORT_SPEED_1000,
+               .duplex = 1,
+               .txpause = 1,
+               .rxpause = 1,
+       },
+       .led_cfg = &wpj342_ar8327_led_cfg,
+};
+
+static struct mdio_board_info wpj342_mdio0_info[] = {
+       {
+               .bus_id = "ag71xx-mdio.0",
+               .phy_addr = 0,
+               .platform_data = &wpj342_ar8327_data,
+       },
+};
+
+
+static void __init wpj342_setup(void)
+{
+       u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
+       u8 *mac = (u8 *) KSEG1ADDR(0x1f02e000);
+
+       ath79_register_m25p80(NULL);
+       ath79_register_leds_gpio(-1, ARRAY_SIZE(wpj342_leds_gpio),
+                               wpj342_leds_gpio);
+
+       ath79_register_gpio_keys_polled(-1, WPJ342_KEYS_POLL_INTERVAL,
+                                       ARRAY_SIZE(wpj342_gpio_keys),
+                                       wpj342_gpio_keys);
+
+       ath79_register_usb();
+
+       ath79_register_wmac(art + WPJ342_WMAC_CALDATA_OFFSET, NULL);
+
+       ath79_register_pci();
+
+       mdiobus_register_board_info(wpj342_mdio0_info,
+                               ARRAY_SIZE(wpj342_mdio0_info));
+
+       ath79_register_mdio(1, 0x0);
+       ath79_register_mdio(0, 0x0);
+
+       ath79_init_mac(ath79_eth0_data.mac_addr, mac + WPJ342_MAC0_OFFSET, 0);
+       ath79_init_mac(ath79_eth1_data.mac_addr, mac + WPJ342_MAC1_OFFSET, 0);
+
+       ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_MII_GMAC0);
+
+       /* GMAC0 is connected to an AR8236 switch */
+       ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
+       ath79_eth0_data.phy_mask = BIT(0);
+       ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
+       ath79_eth0_pll_data.pll_1000 = 0x06000000;
+
+       ath79_register_eth(0);
+}
+
+MIPS_MACHINE(ATH79_MACH_WPJ342, "WPJ342", "Compex WPJ342", wpj342_setup);
index bcc13ec..15e3264 100644 (file)
@@ -239,6 +239,7 @@ enum ath79_mach_type {
        ATH79_MACH_WPN824N,             /* NETGEAR WPN824N */
        ATH79_MACH_WP543,               /* Compex WP543 */
        ATH79_MACH_WPE72,               /* Compex WPE72 */
+       ATH79_MACH_WPJ342,              /* Compex WPJ342 */
        ATH79_MACH_WPJ344,              /* Compex WPJ344 */
        ATH79_MACH_WPJ531,              /* Compex WPJ531 */
        ATH79_MACH_WPJ558,              /* Compex WPJ558 */
index 2f6e0b2..54d8503 100644 (file)
@@ -27,6 +27,16 @@ endef
 
 $(eval $(call Profile,WPE72))
 
+define Profile/WPJ342
+       NAME:=Compex WPJ342
+endef
+
+define Profile/WPJ342/Description
+       Package set optimized for the Compex WPJ342 board.
+endef
+
+$(eval $(call Profile,WPJ342))
+
 define Profile/WPJ344
        NAME:=Compex WPJ344
 endef
index eb7a7f0..cacdd50 100644 (file)
@@ -1621,6 +1621,7 @@ uap_pro_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,1536k(kernel)
 ubdev_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,7488k(firmware),64k(certs),256k(cfg)ro,64k(EEPROM)ro
 whrhpg300n_mtdlayout=mtdparts=spi0.0:248k(u-boot)ro,8k(u-boot-env)ro,3712k(firmware),64k(art)ro
 wlr8100_mtdlayout=mtdparts=spi0.0:192k(u-boot)ro,64k(u-boot-env)ro,1408k(kernel),14080k(rootfs),192k(unknown)ro,64k(art)ro,384k(unknown2)ro,15488k@0x40000(firmware)
+wpj342_mtdlayout_16M=mtdparts=spi0.0:192k(u-boot)ro,16128k(firmware),64k(art)ro
 wpj344_mtdlayout_16M=mtdparts=spi0.0:192k(u-boot)ro,16128k(firmware),64k(art)ro
 dr344_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,6336k(rootfs),1408k(kernel),64k(nvram),64k(art)ro,7744k@0x50000(firmware)
 wpj531_mtdlayout_16M=mtdparts=spi0.0:192k(u-boot)ro,16128k(firmware),64k(art)ro
@@ -2395,6 +2396,7 @@ $(eval $(call SingleProfile,AthLzma,64k,MR16,mr16,MR16,ttyS0,115200,$$(mr16_mtdl
 $(eval $(call SingleProfile,AthLzma,64k,PB92,pb92,PB92,ttyS0,115200,$$(pb92_mtdlayout),KRuImage))
 $(eval $(call SingleProfile,AthLzma,64k,TUBE2H16M,tube2h-16M,TUBE2H,ttyATH0,115200,$$(alfa_mtdlayout_16M),KRuImage,65536))
 $(eval $(call SingleProfile,AthLzma,64k,WLR8100,wlr8100,WLR8100,ttyS0,115200,$$(wlr8100_mtdlayout),KRuImage))
+$(eval $(call SingleProfile,AthLzma,64k,WPJ342_16M,wpj342-16M,WPJ342,ttyS0,115200,$$(wpj342_mtdlayout_16M),KRuImage,65536))
 $(eval $(call SingleProfile,AthLzma,64k,WPJ344_16M,wpj344-16M,WPJ344,ttyS0,115200,$$(wpj344_mtdlayout_16M),KRuImage,65536))
 $(eval $(call SingleProfile,AthLzma,64k,DR344,dr344,DR344,ttyS0,115200,$$(dr344_mtdlayout),RKuImage))
 $(eval $(call SingleProfile,AthLzma,64k,WPJ531_16M,wpj531-16M,WPJ531,ttyS0,115200,$$(wpj531_mtdlayout_16M),KRuImage,65536))
@@ -2526,6 +2528,7 @@ $(eval $(call MultiProfile,WNR612V2,REALWNR612V2 N150R))
 $(eval $(call MultiProfile,WNR1000V2,REALWNR1000V2 WNR1000V2_VC))
 $(eval $(call MultiProfile,WP543,WP543_2M WP543_4M WP543_8M WP543_16M))
 $(eval $(call MultiProfile,WPE72,WPE72_4M WPE72_8M WPE72_16M))
+$(eval $(call MultiProfile,WPJ342,WPJ342_16M))
 $(eval $(call MultiProfile,WPJ344,WPJ344_16M))
 $(eval $(call MultiProfile,WPJ531,WPJ531_16M))
 $(eval $(call MultiProfile,WPJ558,WPJ558_16M))
index 3b9431e..094f2ae 100644 (file)
@@ -117,6 +117,7 @@ CONFIG_ATH79_MACH_RBSXTLITE=y
 # CONFIG_ATH79_MACH_WNR2200 is not set
 # CONFIG_ATH79_MACH_WP543 is not set
 # CONFIG_ATH79_MACH_WPE72 is not set
+# CONFIG_ATH79_MACH_WPJ342 is not set
 # CONFIG_ATH79_MACH_WPJ344 is not set
 # CONFIG_ATH79_MACH_WPJ531 is not set
 # CONFIG_ATH79_MACH_WPJ558 is not set