New: mac80211-based bcm43xx driver from the wireless-dev tree
authorPeter Denison <openwrt@marshadder.org>
Thu, 21 Jun 2007 20:45:45 +0000 (20:45 +0000)
committerPeter Denison <openwrt@marshadder.org>
Thu, 21 Jun 2007 20:45:45 +0000 (20:45 +0000)
SVN-Revision: 7693

31 files changed:
package/bcm43xx-mac80211/Makefile [new file with mode: 0644]
package/bcm43xx-mac80211/src/Kconfig [new file with mode: 0644]
package/bcm43xx-mac80211/src/Makefile [new file with mode: 0644]
package/bcm43xx-mac80211/src/README [new file with mode: 0644]
package/bcm43xx-mac80211/src/bcm43xx/Kconfig [new file with mode: 0644]
package/bcm43xx-mac80211/src/bcm43xx/Makefile [new file with mode: 0644]
package/bcm43xx-mac80211/src/bcm43xx/bcm43xx.h [new file with mode: 0644]
package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_debugfs.c [new file with mode: 0644]
package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_debugfs.h [new file with mode: 0644]
package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_dma.c [new file with mode: 0644]
package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_dma.h [new file with mode: 0644]
package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_leds.c [new file with mode: 0644]
package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_leds.h [new file with mode: 0644]
package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_lo.c [new file with mode: 0644]
package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_lo.h [new file with mode: 0644]
package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_main.c [new file with mode: 0644]
package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_main.h [new file with mode: 0644]
package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_pcmcia.c [new file with mode: 0644]
package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_pcmcia.h [new file with mode: 0644]
package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_phy.c [new file with mode: 0644]
package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_phy.h [new file with mode: 0644]
package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_pio.c [new file with mode: 0644]
package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_pio.h [new file with mode: 0644]
package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_power.c [new file with mode: 0644]
package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_power.h [new file with mode: 0644]
package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_sysfs.c [new file with mode: 0644]
package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_sysfs.h [new file with mode: 0644]
package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_tables.c [new file with mode: 0644]
package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_tables.h [new file with mode: 0644]
package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_xmit.c [new file with mode: 0644]
package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_xmit.h [new file with mode: 0644]

diff --git a/package/bcm43xx-mac80211/Makefile b/package/bcm43xx-mac80211/Makefile
new file mode 100644 (file)
index 0000000..d423620
--- /dev/null
@@ -0,0 +1,53 @@
+#
+# Copyright (C) 2007 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+# 
+# $Id: Makefile 7440 2007-06-02 02:22:01Z nbd $
+
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/kernel.mk
+
+PKG_NAME:=bcm43xx-mac80211
+PKG_RELEASE:=1
+
+PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)
+
+include $(INCLUDE_DIR)/package.mk
+
+# This horrible, horrible hack is because I can't work out ow to add
+# CONFIG_* definitions to a kernel config from an external module dir.
+# It should come from a proper configuration based on the Kconfig in the src
+# directory.
+MAKE_CONFIGS=CONFIG_BCM43XX_MAC80211=m CONFIG_BCM43XX_MAC80211_PCI=y \
+       CONFIG_BCM43XX_MAC80211_DEBUG=y CONFIG_BCM43XX_MAC80211_DMA=y \
+       CONFIG_BCM43XX_MAC80211_PIO=y CONFIG_BCM43XX_MAC80211_DMA_AND_PIO_MODE=y
+
+BUILDFLAGS+=$(patsubst CONFIG_%, -DCONFIG_%, $(MAKE_CONFIGS))
+
+define KernelPackage/bcm43xx-mac80211
+  TITLE:=Broadcom 43xx wireless support
+  DESCRIPTION:=Kernel module for Broadcom 43xx wireless support (mac80211)
+  VERSION:=$(PKG_RELEASE)+$(LINUX_VERSION)-$(BOARD)-$(LINUX_RELEASE)
+  DEPENDS:=@LINUX_2_6 +kmod-mac80211
+  SUBMENU:=Wireless Drivers
+#  AUTOLOAD:=$(call AutoLoad,30,bcm43xx-mac80211)
+  FILES:=$(PKG_BUILD_DIR)/bcm43xx-mac80211.$(LINUX_KMOD_SUFFIX)
+endef
+
+define Build/Prepare
+       mkdir -p $(PKG_BUILD_DIR)
+       $(CP) ./src/bcm43xx/* $(PKG_BUILD_DIR)/
+endef
+
+define Build/Compile
+       $(MAKE) $(MAKE_CONFIGS) -C "$(LINUX_DIR)" \
+               CROSS_COMPILE="$(TARGET_CROSS)" \
+               ARCH="$(LINUX_KARCH)" \
+               EXTRA_CFLAGS="$(BUILDFLAGS)" \
+               SUBDIRS="$(PKG_BUILD_DIR)" \
+               modules
+endef
+
+$(eval $(call KernelPackage,bcm43xx-mac80211))
diff --git a/package/bcm43xx-mac80211/src/Kconfig b/package/bcm43xx-mac80211/src/Kconfig
new file mode 100644 (file)
index 0000000..475a3d5
--- /dev/null
@@ -0,0 +1 @@
+source "drivers/net/wireless/mac80211/bcm43xx/Kconfig"
diff --git a/package/bcm43xx-mac80211/src/Makefile b/package/bcm43xx-mac80211/src/Makefile
new file mode 100644 (file)
index 0000000..16c1803
--- /dev/null
@@ -0,0 +1 @@
+obj-$(CONFIG_BCM43XX_MAC80211) += bcm43xx/
diff --git a/package/bcm43xx-mac80211/src/README b/package/bcm43xx-mac80211/src/README
new file mode 100644 (file)
index 0000000..da9551e
--- /dev/null
@@ -0,0 +1,2 @@
+This directory contains IEEE 802.11 wireless LAN drivers that are using
+Devicescape IEEE 802.11 stack (net/mac80211).
diff --git a/package/bcm43xx-mac80211/src/bcm43xx/Kconfig b/package/bcm43xx-mac80211/src/bcm43xx/Kconfig
new file mode 100644 (file)
index 0000000..8f9df0e
--- /dev/null
@@ -0,0 +1,101 @@
+config BCM43XX_MAC80211
+       tristate "Broadcom BCM43xx wireless support (mac80211 stack)"
+       depends on MAC80211 && WLAN_80211 && EXPERIMENTAL
+       select FW_LOADER
+       select SSB
+       select HW_RANDOM
+       ---help---
+         This is an experimental driver for the Broadcom 43xx wireless chip,
+         found in the Apple Airport Extreme and various other devices.
+
+config BCM43XX_MAC80211_PCI
+       bool "BCM43xx PCI device support"
+       depends on BCM43XX_MAC80211 && PCI
+       select SSB_PCIHOST
+       select SSB_DRIVER_PCICORE
+       default y
+       ---help---
+         Broadcom 43xx PCI device support.
+
+         Say Y, if you have a BCM43xx device connected through the PCI bus.
+         Please note that most PC-CARD devices are (to the kernel) PCI devices,
+         too and not PCMCIA.
+         It's safe to select Y here, even if you don't have a BCM43xx PCI device.
+
+config BCM43XX_MAC80211_PCMCIA
+       bool "BCM43xx PCMCIA device support"
+       depends on BCM43XX_MAC80211 && PCMCIA
+       select SSB_PCMCIAHOST
+       ---help---
+         Broadcom 43xx PCMCIA device support.
+
+         Support for 16bit PCMCIA devices.
+         Please note that most PC-CARD devices are _NOT_ 16bit PCMCIA
+         devices, but 32bit CardBUS devices. CardBUS devices are supported
+         by "BCM43xx PCI device support".
+
+         With this config option you can drive bcm43xx cards in
+         CompactFlash formfactor in a PCMCIA adaptor.
+         CF bcm43xx cards can sometimes be found in handheld PCs.
+
+         It's safe to select Y here, even if you don't have a BCM43xx PCMCIA device.
+
+         If unsure, say N.
+
+config BCM43XX_MAC80211_DEBUG
+       bool "Broadcom BCM43xx debugging (RECOMMENDED)"
+       depends on BCM43XX_MAC80211
+       select SSB_DEBUG if !SSB_SILENT
+       default y
+       ---help---
+         Broadcom 43xx debugging messages.
+         Say Y, because the driver is still very experimental and
+         this will help you get it running.
+
+config BCM43XX_MAC80211_DMA
+       bool
+       depends on BCM43XX_MAC80211
+config BCM43XX_MAC80211_PIO
+       bool
+       depends on BCM43XX_MAC80211
+
+choice
+       prompt "BCM43xx data transfer mode"
+       depends on BCM43XX_MAC80211
+       default BCM43XX_MAC80211_DMA_AND_PIO_MODE
+
+config BCM43XX_MAC80211_DMA_AND_PIO_MODE
+       bool "DMA + PIO"
+       select BCM43XX_MAC80211_DMA
+       select BCM43XX_MAC80211_PIO
+       ---help---
+         Include both, Direct Memory Access (DMA) and Programmed I/O (PIO)
+         data transfer modes.
+         The actually used mode is selectable through the module
+         parameter "pio". If the module parameter is pio=0, DMA is used.
+         Otherwise PIO is used. DMA is default.
+
+         If unsure, choose this option.
+
+config BCM43XX_MAC80211_DMA_MODE
+       bool "DMA (Direct Memory Access) only"
+       select BCM43XX_MAC80211_DMA
+       ---help---
+         Only include Direct Memory Access (DMA).
+         This reduces the size of the driver module, by omitting the PIO code.
+
+config BCM43XX_MAC80211_PIO_MODE
+       bool "PIO (Programmed I/O) only"
+       select BCM43XX_MAC80211_PIO
+       ---help---
+         Only include Programmed I/O (PIO).
+         This reduces the size of the driver module, by omitting the DMA code.
+         Please note that PIO transfers are slow (compared to DMA).
+
+         Also note that not all devices of the 43xx series support PIO.
+         The 4306 (Apple Airport Extreme and others) supports PIO, while
+         the 4318 is known to _not_ support PIO.
+
+         Only use PIO, if DMA does not work for you.
+
+endchoice
diff --git a/package/bcm43xx-mac80211/src/bcm43xx/Makefile b/package/bcm43xx-mac80211/src/bcm43xx/Makefile
new file mode 100644 (file)
index 0000000..ce66b7b
--- /dev/null
@@ -0,0 +1,18 @@
+obj-$(CONFIG_BCM43XX_MAC80211) += bcm43xx-mac80211.o
+
+bcm43xx-mac80211-obj-$(CONFIG_BCM43XX_MAC80211_PCMCIA) += bcm43xx_pcmcia.o
+
+bcm43xx-mac80211-obj-$(CONFIG_BCM43XX_MAC80211_DEBUG) += bcm43xx_debugfs.o
+
+bcm43xx-mac80211-obj-$(CONFIG_BCM43XX_MAC80211_DMA) += bcm43xx_dma.o
+bcm43xx-mac80211-obj-$(CONFIG_BCM43XX_MAC80211_PIO) += bcm43xx_pio.o
+
+bcm43xx-mac80211-objs := bcm43xx_main.o \
+                        bcm43xx_tables.o \
+                        bcm43xx_phy.o \
+                        bcm43xx_power.o \
+                        bcm43xx_sysfs.o \
+                        bcm43xx_leds.o \
+                        bcm43xx_xmit.o \
+                        bcm43xx_lo.o \
+                        $(bcm43xx-mac80211-obj-y)
diff --git a/package/bcm43xx-mac80211/src/bcm43xx/bcm43xx.h b/package/bcm43xx-mac80211/src/bcm43xx/bcm43xx.h
new file mode 100644 (file)
index 0000000..63eddaf
--- /dev/null
@@ -0,0 +1,885 @@
+#ifndef BCM43xx_H_
+#define BCM43xx_H_
+
+#include <linux/hw_random.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/stringify.h>
+#include <linux/netdevice.h>
+#include <linux/pci.h>
+#include <asm/atomic.h>
+#include <asm/io.h>
+
+#include <linux/ssb/ssb.h>
+#include <linux/ssb/ssb_driver_chipcommon.h>
+
+#include <linux/wireless.h>
+#include <net/mac80211.h>
+
+#include "bcm43xx_debugfs.h"
+#include "bcm43xx_leds.h"
+#include "bcm43xx_lo.h"
+#include "bcm43xx_phy.h"
+
+
+#define PFX                            KBUILD_MODNAME ": "
+
+#define BCM43xx_IRQWAIT_MAX_RETRIES    50
+
+#define BCM43xx_IO_SIZE                        8192
+
+#define BCM43xx_RX_MAX_SSI             60
+
+/* MMIO offsets */
+#define BCM43xx_MMIO_DMA0_REASON       0x20
+#define BCM43xx_MMIO_DMA0_IRQ_MASK     0x24
+#define BCM43xx_MMIO_DMA1_REASON       0x28
+#define BCM43xx_MMIO_DMA1_IRQ_MASK     0x2C
+#define BCM43xx_MMIO_DMA2_REASON       0x30
+#define BCM43xx_MMIO_DMA2_IRQ_MASK     0x34
+#define BCM43xx_MMIO_DMA3_REASON       0x38
+#define BCM43xx_MMIO_DMA3_IRQ_MASK     0x3C
+#define BCM43xx_MMIO_DMA4_REASON       0x40
+#define BCM43xx_MMIO_DMA4_IRQ_MASK     0x44
+#define BCM43xx_MMIO_DMA5_REASON       0x48
+#define BCM43xx_MMIO_DMA5_IRQ_MASK     0x4C
+#define BCM43xx_MMIO_MACCTL            0x120
+#define BCM43xx_MMIO_STATUS_BITFIELD   0x120//TODO replace all instances by MACCTL
+#define BCM43xx_MMIO_STATUS2_BITFIELD  0x124
+#define BCM43xx_MMIO_GEN_IRQ_REASON    0x128
+#define BCM43xx_MMIO_GEN_IRQ_MASK      0x12C
+#define BCM43xx_MMIO_RAM_CONTROL       0x130
+#define BCM43xx_MMIO_RAM_DATA          0x134
+#define BCM43xx_MMIO_PS_STATUS         0x140
+#define BCM43xx_MMIO_RADIO_HWENABLED_HI        0x158
+#define BCM43xx_MMIO_SHM_CONTROL       0x160
+#define BCM43xx_MMIO_SHM_DATA          0x164
+#define BCM43xx_MMIO_SHM_DATA_UNALIGNED        0x166
+#define BCM43xx_MMIO_XMITSTAT_0                0x170
+#define BCM43xx_MMIO_XMITSTAT_1                0x174
+#define BCM43xx_MMIO_REV3PLUS_TSF_LOW  0x180 /* core rev >= 3 only */
+#define BCM43xx_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */
+
+/* 32-bit DMA */
+#define BCM43xx_MMIO_DMA32_BASE0       0x200
+#define BCM43xx_MMIO_DMA32_BASE1       0x220
+#define BCM43xx_MMIO_DMA32_BASE2       0x240
+#define BCM43xx_MMIO_DMA32_BASE3       0x260
+#define BCM43xx_MMIO_DMA32_BASE4       0x280
+#define BCM43xx_MMIO_DMA32_BASE5       0x2A0
+/* 64-bit DMA */
+#define BCM43xx_MMIO_DMA64_BASE0       0x200
+#define BCM43xx_MMIO_DMA64_BASE1       0x240
+#define BCM43xx_MMIO_DMA64_BASE2       0x280
+#define BCM43xx_MMIO_DMA64_BASE3       0x2C0
+#define BCM43xx_MMIO_DMA64_BASE4       0x300
+#define BCM43xx_MMIO_DMA64_BASE5       0x340
+/* PIO */
+#define BCM43xx_MMIO_PIO1_BASE         0x300
+#define BCM43xx_MMIO_PIO2_BASE         0x310
+#define BCM43xx_MMIO_PIO3_BASE         0x320
+#define BCM43xx_MMIO_PIO4_BASE         0x330
+
+#define BCM43xx_MMIO_PHY_VER           0x3E0
+#define BCM43xx_MMIO_PHY_RADIO         0x3E2
+#define BCM43xx_MMIO_PHY0              0x3E6
+#define BCM43xx_MMIO_ANTENNA           0x3E8
+#define BCM43xx_MMIO_CHANNEL           0x3F0
+#define BCM43xx_MMIO_CHANNEL_EXT       0x3F4
+#define BCM43xx_MMIO_RADIO_CONTROL     0x3F6
+#define BCM43xx_MMIO_RADIO_DATA_HIGH   0x3F8
+#define BCM43xx_MMIO_RADIO_DATA_LOW    0x3FA
+#define BCM43xx_MMIO_PHY_CONTROL       0x3FC
+#define BCM43xx_MMIO_PHY_DATA          0x3FE
+#define BCM43xx_MMIO_MACFILTER_CONTROL 0x420
+#define BCM43xx_MMIO_MACFILTER_DATA    0x422
+#define BCM43xx_MMIO_RCMTA_COUNT       0x43C
+#define BCM43xx_MMIO_RADIO_HWENABLED_LO        0x49A
+#define BCM43xx_MMIO_GPIO_CONTROL      0x49C
+#define BCM43xx_MMIO_GPIO_MASK         0x49E
+#define BCM43xx_MMIO_TSF_0             0x632 /* core rev < 3 only */
+#define BCM43xx_MMIO_TSF_1             0x634 /* core rev < 3 only */
+#define BCM43xx_MMIO_TSF_2             0x636 /* core rev < 3 only */
+#define BCM43xx_MMIO_TSF_3             0x638 /* core rev < 3 only */
+#define BCM43xx_MMIO_RNG               0x65A
+#define BCM43xx_MMIO_POWERUP_DELAY     0x6A8
+
+/* SPROM boardflags_lo values */
+#define BCM43xx_BFL_BTCOEXIST          0x0001 /* implements Bluetooth coexistance */
+#define BCM43xx_BFL_PACTRL             0x0002 /* GPIO 9 controlling the PA */
+#define BCM43xx_BFL_AIRLINEMODE                0x0004 /* implements GPIO 13 radio disable indication */
+#define BCM43xx_BFL_RSSI               0x0008 /* software calculates nrssi slope. */
+#define BCM43xx_BFL_ENETSPI            0x0010 /* has ephy roboswitch spi */
+#define BCM43xx_BFL_XTAL_NOSLOW                0x0020 /* no slow clock available */
+#define BCM43xx_BFL_CCKHIPWR           0x0040 /* can do high power CCK transmission */
+#define BCM43xx_BFL_ENETADM            0x0080 /* has ADMtek switch */
+#define BCM43xx_BFL_ENETVLAN           0x0100 /* can do vlan */
+#define BCM43xx_BFL_AFTERBURNER                0x0200 /* supports Afterburner mode */
+#define BCM43xx_BFL_NOPCI              0x0400 /* leaves PCI floating */
+#define BCM43xx_BFL_FEM                        0x0800 /* supports the Front End Module */
+#define BCM43xx_BFL_EXTLNA             0x1000 /* has an external LNA */
+#define BCM43xx_BFL_HGPA               0x2000 /* had high gain PA */
+#define BCM43xx_BFL_BTCMOD             0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
+#define BCM43xx_BFL_ALTIQ              0x8000 /* alternate I/Q settings */
+
+/* GPIO register offset, in both ChipCommon and PCI core. */
+#define BCM43xx_GPIO_CONTROL           0x6c
+
+/* SHM Routing */
+enum {
+       BCM43xx_SHM_UCODE,      /* Microcode memory */
+       BCM43xx_SHM_SHARED,     /* Shared memory */
+       BCM43xx_SHM_SCRATCH,    /* Scratch memory */
+       BCM43xx_SHM_HW,         /* Internal hardware register */
+       BCM43xx_SHM_RCMTA,      /* Receive match transmitter address (rev >= 5 only) */
+};
+/* SHM Routing modifiers */
+#define BCM43xx_SHM_AUTOINC_R          0x0200 /* Auto-increment address on read */
+#define BCM43xx_SHM_AUTOINC_W          0x0100 /* Auto-increment address on write */
+#define BCM43xx_SHM_AUTOINC_RW         (BCM43xx_SHM_AUTOINC_R | \
+                                        BCM43xx_SHM_AUTOINC_W)
+
+/* Misc SHM_SHARED offsets */
+#define BCM43xx_SHM_SH_WLCOREREV       0x0016 /* 802.11 core revision */
+#define BCM43xx_SHM_SH_PCTLWDPOS       0x0008
+#define BCM43xx_SHM_SH_RXPADOFF                0x0034 /* RX Padding data offset (PIO only) */
+#define BCM43xx_SHM_SH_PHYVER          0x0050 /* PHY version */
+#define BCM43xx_SHM_SH_PHYTYPE         0x0052 /* PHY type */
+#define BCM43xx_SHM_SH_ANTSWAP         0x005C /* Antenna swap threshold */
+#define BCM43xx_SHM_SH_HOSTFLO         0x005E /* Hostflags for ucode options (low) */
+#define BCM43xx_SHM_SH_HOSTFHI         0x0060 /* Hostflags for ucode options (high) */
+#define BCM43xx_SHM_SH_RADAR           0x0066 /* Radar register */
+#define BCM43xx_SHM_SH_PHYTXNOI                0x006E /* PHY noise directly after TX (lower 8bit only) */
+#define BCM43xx_SHM_SH_RFRXSP1         0x0072 /* RF RX SP Register 1 */
+#define BCM43xx_SHM_SH_CHAN            0x00A0 /* Current channel (low 8bit only) */
+#define  BCM43xx_SHM_SH_CHAN_5GHZ      0x0100 /* Bit set, if 5Ghz channel */
+#define BCM43xx_SHM_SH_BCMCFIFOID      0x0108 /* Last posted cookie to the bcast/mcast FIFO */
+/* SHM_SHARED TX FIFO variables */
+#define BCM43xx_SHM_SH_SIZE01          0x0098 /* TX FIFO size for FIFO 0 (low) and 1 (high) */
+#define BCM43xx_SHM_SH_SIZE23          0x009A /* TX FIFO size for FIFO 2 and 3 */
+#define BCM43xx_SHM_SH_SIZE45          0x009C /* TX FIFO size for FIFO 4 and 5 */
+#define BCM43xx_SHM_SH_SIZE67          0x009E /* TX FIFO size for FIFO 6 and 7 */
+/* SHM_SHARED background noise */
+#define BCM43xx_SHM_SH_JSSI0           0x0088 /* Measure JSSI 0 */
+#define BCM43xx_SHM_SH_JSSI1           0x008A /* Measure JSSI 1 */
+#define BCM43xx_SHM_SH_JSSIAUX         0x008C /* Measure JSSI AUX */
+/* SHM_SHARED crypto engine */
+#define BCM43xx_SHM_SH_DEFAULTIV       0x003C /* Default IV location */
+#define BCM43xx_SHM_SH_NRRXTRANS       0x003E /* # of soft RX transmitter addresses (max 8) */
+#define BCM43xx_SHM_SH_KTP             0x0056 /* Key table pointer */
+#define BCM43xx_SHM_SH_TKIPTSCTTAK     0x0318
+#define BCM43xx_SHM_SH_KEYIDXBLOCK     0x05D4 /* Key index/algorithm block (v4 firmware) */
+#define BCM43xx_SHM_SH_PSM             0x05F4 /* PSM transmitter address match block (rev < 5) */
+/* SHM_SHARED WME variables */
+#define BCM43xx_SHM_SH_EDCFSTAT                0x000E /* EDCF status */
+#define BCM43xx_SHM_SH_TXFCUR          0x0030 /* TXF current index */
+#define BCM43xx_SHM_SH_EDCFQ           0x0240 /* EDCF Q info */
+/* SHM_SHARED powersave mode related */
+#define BCM43xx_SHM_SH_SLOTT           0x0010 /* Slot time */
+#define BCM43xx_SHM_SH_DTIMPER         0x0012 /* DTIM period */
+#define BCM43xx_SHM_SH_NOSLPZNATDTIM   0x004C /* NOSLPZNAT DTIM */
+/* SHM_SHARED beacon variables */
+#define BCM43xx_SHM_SH_BTL0            0x0018 /* Beacon template length 0 */
+#define BCM43xx_SHM_SH_BTL1            0x001A /* Beacon template length 1 */
+#define BCM43xx_SHM_SH_BTSFOFF         0x001C /* Beacon TSF offset */
+#define BCM43xx_SHM_SH_TIMBPOS         0x001E /* TIM B position in beacon */
+#define BCM43xx_SHM_SH_SFFBLIM         0x0044 /* Short frame fallback retry limit */
+#define BCM43xx_SHM_SH_LFFBLIM         0x0046 /* Long frame fallback retry limit */
+#define BCM43xx_SHM_SH_BEACPHYCTL      0x0054 /* Beacon PHY TX control word (see PHY TX control) */
+/* SHM_SHARED ACK/CTS control */
+#define BCM43xx_SHM_SH_ACKCTSPHYCTL    0x0022 /* ACK/CTS PHY control word (see PHY TX control) */
+/* SHM_SHARED probe response variables */
+#define BCM43xx_SHM_SH_PRSSID          0x0160 /* Probe Response SSID */
+#define BCM43xx_SHM_SH_PRSSIDLEN       0x0048 /* Probe Response SSID length */
+#define BCM43xx_SHM_SH_PRTLEN          0x004A /* Probe Response template length */
+#define BCM43xx_SHM_SH_PRMAXTIME       0x0074 /* Probe Response max time */
+#define BCM43xx_SHM_SH_PRPHYCTL                0x0188 /* Probe Response PHY TX control word */
+/* SHM_SHARED rate tables */
+#define BCM43xx_SHM_SH_OFDMDIRECT      0x01C0 /* Pointer to OFDM direct map */
+#define BCM43xx_SHM_SH_OFDMBASIC       0x01E0 /* Pointer to OFDM basic rate map */
+#define BCM43xx_SHM_SH_CCKDIRECT       0x0200 /* Pointer to CCK direct map */
+#define BCM43xx_SHM_SH_CCKBASIC                0x0220 /* Pointer to CCK basic rate map */
+/* SHM_SHARED microcode soft registers */
+#define BCM43xx_SHM_SH_UCODEREV                0x0000 /* Microcode revision */
+#define BCM43xx_SHM_SH_UCODEPATCH      0x0002 /* Microcode patchlevel */
+#define BCM43xx_SHM_SH_UCODEDATE       0x0004 /* Microcode date */
+#define BCM43xx_SHM_SH_UCODETIME       0x0006 /* Microcode time */
+#define BCM43xx_SHM_SH_UCODESTAT       0x0040 /* Microcode debug status code */
+#define  BCM43xx_SHM_SH_UCODESTAT_INVALID      0
+#define  BCM43xx_SHM_SH_UCODESTAT_INIT         1
+#define  BCM43xx_SHM_SH_UCODESTAT_ACTIVE       2
+#define  BCM43xx_SHM_SH_UCODESTAT_SUSP         3 /* suspended */
+#define  BCM43xx_SHM_SH_UCODESTAT_SLEEP                4 /* asleep (PS) */
+#define BCM43xx_SHM_SH_MAXBFRAMES      0x0080 /* Maximum number of frames in a burst */
+#define BCM43xx_SHM_SH_SPUWKUP         0x0094 /* pre-wakeup for synth PU in us */
+#define BCM43xx_SHM_SH_PRETBTT         0x0096 /* pre-TBTT in us */
+
+/* SHM_SCRATCH offsets */
+#define BCM43xx_SHM_SC_MINCONT         0x0003 /* Minimum contention window */
+#define BCM43xx_SHM_SC_MAXCONT         0x0004 /* Maximum contention window */
+#define BCM43xx_SHM_SC_CURCONT         0x0005 /* Current contention window */
+#define BCM43xx_SHM_SC_SRLIMIT         0x0006 /* Short retry count limit */
+#define BCM43xx_SHM_SC_LRLIMIT         0x0007 /* Long retry count limit */
+#define BCM43xx_SHM_SC_DTIMC           0x0008 /* Current DTIM count */
+#define BCM43xx_SHM_SC_BTL0LEN         0x0015 /* Beacon 0 template length */
+#define BCM43xx_SHM_SC_BTL1LEN         0x0016 /* Beacon 1 template length */
+#define BCM43xx_SHM_SC_SCFB            0x0017 /* Short frame transmit count threshold for rate fallback */
+#define BCM43xx_SHM_SC_LCFB            0x0018 /* Long frame transmit count threshold for rate fallback */
+
+
+/* Hardware Radio Enable masks */
+#define BCM43xx_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)
+#define BCM43xx_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
+
+/* HostFlags. See bcm43xx_hf_read/write() */
+#define BCM43xx_HF_ANTDIVHELP          0x00000001 /* ucode antenna div helper */
+#define BCM43xx_HF_SYMW                        0x00000002 /* G-PHY SYM workaround */
+#define BCM43xx_HF_RXPULLW             0x00000004 /* RX pullup workaround */
+#define BCM43xx_HF_CCKBOOST            0x00000008 /* 4dB CCK power boost (exclusive with OFDM boost) */
+#define BCM43xx_HF_BTCOEX              0x00000010 /* Bluetooth coexistance */
+#define BCM43xx_HF_GDCW                        0x00000020 /* G-PHY DV canceller filter bw workaround */
+#define BCM43xx_HF_OFDMPABOOST         0x00000040 /* Enable PA gain boost for OFDM */
+#define BCM43xx_HF_ACPR                        0x00000080 /* Disable for Japan, channel 14 */
+#define BCM43xx_HF_EDCF                        0x00000100 /* on if WME and MAC suspended */
+#define BCM43xx_HF_TSSIRPSMW           0x00000200 /* TSSI reset PSM ucode workaround */
+#define BCM43xx_HF_DSCRQ               0x00000400 /* Disable slow clock request in ucode */
+#define BCM43xx_HF_ACIW                        0x00000800 /* ACI workaround: shift bits by 2 on PHY CRS */
+#define BCM43xx_HF_2060W               0x00001000 /* 2060 radio workaround */
+#define BCM43xx_HF_RADARW              0x00002000 /* Radar workaround */
+#define BCM43xx_HF_USEDEFKEYS          0x00004000 /* Enable use of default keys */
+#define BCM43xx_HF_BT4PRIOCOEX         0x00010000 /* Bluetooth 2-priority coexistance */
+#define BCM43xx_HF_FWKUP               0x00020000 /* Fast wake-up ucode */
+#define BCM43xx_HF_VCORECALC           0x00040000 /* Force VCO recalculation when powering up synthpu */
+#define BCM43xx_HF_PCISCW              0x00080000 /* PCI slow clock workaround */
+#define BCM43xx_HF_4318TSSI            0x00200000 /* 4318 TSSI */
+#define BCM43xx_HF_FBCMCFIFO           0x00400000 /* Flush bcast/mcast FIFO immediately */
+#define BCM43xx_HF_HWPCTL              0x00800000 /* Enable hardwarre power control */
+#define BCM43xx_HF_BTCOEXALT           0x01000000 /* Bluetooth coexistance in alternate pins */
+#define BCM43xx_HF_TXBTCHECK           0x02000000 /* Bluetooth check during transmission */
+#define BCM43xx_HF_SKCFPUP             0x04000000 /* Skip CFP update */
+
+
+/* MacFilter offsets. */
+#define BCM43xx_MACFILTER_SELF         0x0000
+#define BCM43xx_MACFILTER_ASSOC                0x0003
+
+/* PowerControl */
+#define BCM43xx_PCTL_IN                        0xB0
+#define BCM43xx_PCTL_OUT               0xB4
+#define BCM43xx_PCTL_OUTENABLE         0xB8
+#define BCM43xx_PCTL_XTAL_POWERUP      0x40
+#define BCM43xx_PCTL_PLL_POWERDOWN     0x80
+
+/* PowerControl Clock Modes */
+#define BCM43xx_PCTL_CLK_FAST          0x00
+#define BCM43xx_PCTL_CLK_SLOW          0x01
+#define BCM43xx_PCTL_CLK_DYNAMIC       0x02
+
+#define BCM43xx_PCTL_FORCE_SLOW                0x0800
+#define BCM43xx_PCTL_FORCE_PLL         0x1000
+#define BCM43xx_PCTL_DYN_XTAL          0x2000
+
+/* PHYVersioning */
+#define BCM43xx_PHYTYPE_A              0x00
+#define BCM43xx_PHYTYPE_B              0x01
+#define BCM43xx_PHYTYPE_G              0x02
+
+/* PHYRegisters */
+#define BCM43xx_PHY_ILT_A_CTRL         0x0072
+#define BCM43xx_PHY_ILT_A_DATA1                0x0073
+#define BCM43xx_PHY_ILT_A_DATA2                0x0074
+#define BCM43xx_PHY_G_LO_CONTROL       0x0810
+#define BCM43xx_PHY_ILT_G_CTRL         0x0472
+#define BCM43xx_PHY_ILT_G_DATA1                0x0473
+#define BCM43xx_PHY_ILT_G_DATA2                0x0474
+#define BCM43xx_PHY_A_PCTL             0x007B
+#define BCM43xx_PHY_G_PCTL             0x0029
+#define BCM43xx_PHY_A_CRS              0x0029
+#define BCM43xx_PHY_RADIO_BITFIELD     0x0401
+#define BCM43xx_PHY_G_CRS              0x0429
+#define BCM43xx_PHY_NRSSILT_CTRL       0x0803
+#define BCM43xx_PHY_NRSSILT_DATA       0x0804
+
+/* RadioRegisters */
+#define BCM43xx_RADIOCTL_ID            0x01
+
+/* MAC Control bitfield */
+#define BCM43xx_MACCTL_ENABLED         0x00000001 /* MAC Enabled */
+#define BCM43xx_MACCTL_PSM_RUN         0x00000002 /* Run Microcode */
+#define BCM43xx_MACCTL_PSM_JMP0                0x00000004 /* Microcode jump to 0 */
+#define BCM43xx_MACCTL_SHM_ENABLED     0x00000100 /* SHM Enabled */
+#define BCM43xx_MACCTL_SHM_UPPER       0x00000200 /* SHM Upper */
+#define BCM43xx_MACCTL_IHR_ENABLED     0x00000400 /* IHR Region Enabled */
+#define BCM43xx_MACCTL_PSM_DBG         0x00002000 /* Microcode debugging enabled */
+#define BCM43xx_MACCTL_GPOUTSMSK       0x0000C000 /* GPOUT Select Mask */
+#define BCM43xx_MACCTL_BE              0x00010000 /* Big Endian mode */
+#define BCM43xx_MACCTL_INFRA           0x00020000 /* Infrastructure mode */
+#define BCM43xx_MACCTL_AP              0x00040000 /* AccessPoint mode */
+#define BCM43xx_MACCTL_RADIOLOCK       0x00080000 /* Radio lock */
+#define BCM43xx_MACCTL_BEACPROMISC     0x00100000 /* Beacon Promiscuous */
+#define BCM43xx_MACCTL_KEEP_BADPLCP    0x00200000 /* Keep frames with bad PLCP */
+#define BCM43xx_MACCTL_KEEP_CTL                0x00400000 /* Keep control frames */
+#define BCM43xx_MACCTL_KEEP_BAD                0x00800000 /* Keep bad frames (FCS) */
+#define BCM43xx_MACCTL_PROMISC         0x01000000 /* Promiscuous mode */
+#define BCM43xx_MACCTL_HWPS            0x02000000 /* Hardware Power Saving */
+#define BCM43xx_MACCTL_AWAKE           0x04000000 /* Device is awake */
+#define BCM43xx_MACCTL_CLOSEDNET       0x08000000 /* Closed net (no SSID bcast) */
+#define BCM43xx_MACCTL_TBTTHOLD                0x10000000 /* TBTT Hold */
+#define BCM43xx_MACCTL_DISCTXSTAT      0x20000000 /* Discard TX status */
+#define BCM43xx_MACCTL_DISCPMQ         0x40000000 /* Discard Power Management Queue */
+#define BCM43xx_MACCTL_GMODE           0x80000000 /* G Mode */
+
+/* StatusBitField *///FIXME rename these all
+#define BCM43xx_SBF_MAC_ENABLED                0x00000001
+#define BCM43xx_SBF_2                  0x00000002 /*FIXME: fix name*/
+#define BCM43xx_SBF_CORE_READY         0x00000004
+#define BCM43xx_SBF_400                        0x00000400 /*FIXME: fix name*/
+#define BCM43xx_SBF_4000               0x00004000 /*FIXME: fix name*/
+#define BCM43xx_SBF_8000               0x00008000 /*FIXME: fix name*/
+#define BCM43xx_SBF_XFER_REG_BYTESWAP  0x00010000
+#define BCM43xx_SBF_MODE_NOTADHOC      0x00020000
+#define BCM43xx_SBF_MODE_AP            0x00040000
+#define BCM43xx_SBF_RADIOREG_LOCK      0x00080000
+#define BCM43xx_SBF_MODE_MONITOR       0x00400000
+#define BCM43xx_SBF_MODE_PROMISC       0x01000000
+#define BCM43xx_SBF_PS1                        0x02000000
+#define BCM43xx_SBF_PS2                        0x04000000
+#define BCM43xx_SBF_NO_SSID_BCAST      0x08000000
+#define BCM43xx_SBF_TIME_UPDATE                0x10000000
+#define BCM43xx_SBF_80000000           0x80000000 /*FIXME: fix name*/
+
+/* 802.11 core specific TM State Low flags */
+#define BCM43xx_TMSLOW_GMODE           0x20000000 /* G Mode Enable */
+#define BCM43xx_TMSLOW_PLLREFSEL       0x00200000 /* PLL Frequency Reference Select */
+#define BCM43xx_TMSLOW_MACPHYCLKEN     0x00100000 /* MAC PHY Clock Control Enable (rev >= 5) */
+#define BCM43xx_TMSLOW_PHYRESET                0x00080000 /* PHY Reset */
+#define BCM43xx_TMSLOW_PHYCLKEN                0x00040000 /* PHY Clock Enable */
+
+/* 802.11 core specific TM State High flags */
+#define BCM43xx_TMSHIGH_FCLOCK         0x00040000 /* Fast Clock Available (rev >= 5)*/
+#define BCM43xx_TMSHIGH_APHY           0x00020000 /* A-PHY available (rev >= 5) */
+#define BCM43xx_TMSHIGH_GPHY           0x00010000 /* G-PHY available (rev >= 5) */
+
+/* Generic-Interrupt reasons. */
+#define BCM43xx_IRQ_MAC_SUSPENDED      0x00000001
+#define BCM43xx_IRQ_BEACON             0x00000002
+#define BCM43xx_IRQ_TBTT_INDI          0x00000004
+#define BCM43xx_IRQ_BEACON_TX_OK       0x00000008
+#define BCM43xx_IRQ_BEACON_CANCEL      0x00000010
+#define BCM43xx_IRQ_ATIM_END           0x00000020
+#define BCM43xx_IRQ_PMQ                        0x00000040
+#define BCM43xx_IRQ_PIO_WORKAROUND     0x00000100
+#define BCM43xx_IRQ_MAC_TXERR          0x00000200
+#define BCM43xx_IRQ_PHY_TXERR          0x00000800
+#define BCM43xx_IRQ_PMEVENT            0x00001000
+#define BCM43xx_IRQ_TIMER0             0x00002000
+#define BCM43xx_IRQ_TIMER1             0x00004000
+#define BCM43xx_IRQ_DMA                        0x00008000
+#define BCM43xx_IRQ_TXFIFO_FLUSH_OK    0x00010000
+#define BCM43xx_IRQ_CCA_MEASURE_OK     0x00020000
+#define BCM43xx_IRQ_NOISESAMPLE_OK     0x00040000
+#define BCM43xx_IRQ_UCODE_DEBUG                0x08000000
+#define BCM43xx_IRQ_RFKILL             0x10000000
+#define BCM43xx_IRQ_TX_OK              0x20000000
+#define BCM43xx_IRQ_PHY_G_CHANGED      0x40000000
+#define BCM43xx_IRQ_TIMEOUT            0x80000000
+
+#define BCM43xx_IRQ_ALL                        0xFFFFFFFF
+#define BCM43xx_IRQ_MASKTEMPLATE       (BCM43xx_IRQ_MAC_SUSPENDED |    \
+                                        BCM43xx_IRQ_BEACON |           \
+                                        BCM43xx_IRQ_TBTT_INDI |        \
+                                        BCM43xx_IRQ_ATIM_END |         \
+                                        BCM43xx_IRQ_PMQ |              \
+                                        BCM43xx_IRQ_MAC_TXERR |        \
+                                        BCM43xx_IRQ_PHY_TXERR |        \
+                                        BCM43xx_IRQ_DMA |              \
+                                        BCM43xx_IRQ_TXFIFO_FLUSH_OK |  \
+                                        BCM43xx_IRQ_NOISESAMPLE_OK |   \
+                                        BCM43xx_IRQ_UCODE_DEBUG |      \
+                                        BCM43xx_IRQ_RFKILL |           \
+                                        BCM43xx_IRQ_TX_OK)
+
+/* Device specific rate values.
+ * The actual values defined here are (rate_in_mbps * 2).
+ * Some code depends on this. Don't change it. */
+#define BCM43xx_CCK_RATE_1MB           0x02
+#define BCM43xx_CCK_RATE_2MB           0x04
+#define BCM43xx_CCK_RATE_5MB           0x0B
+#define BCM43xx_CCK_RATE_11MB          0x16
+#define BCM43xx_OFDM_RATE_6MB          0x0C
+#define BCM43xx_OFDM_RATE_9MB          0x12
+#define BCM43xx_OFDM_RATE_12MB         0x18
+#define BCM43xx_OFDM_RATE_18MB         0x24
+#define BCM43xx_OFDM_RATE_24MB         0x30
+#define BCM43xx_OFDM_RATE_36MB         0x48
+#define BCM43xx_OFDM_RATE_48MB         0x60
+#define BCM43xx_OFDM_RATE_54MB         0x6C
+/* Convert a bcm43xx rate value to a rate in 100kbps */
+#define BCM43xx_RATE_TO_BASE100KBPS(rate)      (((rate) * 10) / 2)
+
+
+#define BCM43xx_DEFAULT_SHORT_RETRY_LIMIT      7
+#define BCM43xx_DEFAULT_LONG_RETRY_LIMIT       4
+
+/* Max size of a security key */
+#define BCM43xx_SEC_KEYSIZE                    16
+/* Security algorithms. */
+enum {
+       BCM43xx_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */
+       BCM43xx_SEC_ALGO_WEP40,
+       BCM43xx_SEC_ALGO_TKIP,
+       BCM43xx_SEC_ALGO_AES,
+       BCM43xx_SEC_ALGO_WEP104,
+       BCM43xx_SEC_ALGO_AES_LEGACY,
+};
+
+
+#ifdef assert
+# undef assert
+#endif
+#ifdef CONFIG_BCM43XX_MAC80211_DEBUG
+# define assert(expr) \
+       do {                                                                    \
+               if (unlikely(!(expr))) {                                        \
+               printk(KERN_ERR PFX "ASSERTION FAILED (%s) at: %s:%d:%s()\n",   \
+                       #expr, __FILE__, __LINE__, __FUNCTION__);               \
+               }                                                               \
+       } while (0)
+# define BCM43xx_DEBUG 1
+#else
+# define assert(expr)  do { /* nothing */ } while (0)
+# define BCM43xx_DEBUG 0
+#endif
+
+/* rate limited printk(). */
+#ifdef printkl
+# undef printkl
+#endif
+#define printkl(f, x...)  do { if (printk_ratelimit()) printk(f ,##x); } while (0)
+/* rate limited printk() for debugging */
+#ifdef dprintkl
+# undef dprintkl
+#endif
+#ifdef CONFIG_BCM43XX_MAC80211_DEBUG
+# define dprintkl              printkl
+#else
+# define dprintkl(f, x...)     do { /* nothing */ } while (0)
+#endif
+
+/* debugging printk() */
+#ifdef dprintk
+# undef dprintk
+#endif
+#ifdef CONFIG_BCM43XX_MAC80211_DEBUG
+# define dprintk(f, x...)  do { printk(f ,##x); } while (0)
+#else
+# define dprintk(f, x...)  do { /* nothing */ } while (0)
+#endif
+
+
+struct net_device;
+struct pci_dev;
+struct bcm43xx_dmaring;
+struct bcm43xx_pioqueue;
+
+struct bcm43xx_initval {
+       u16 offset;
+       u16 size;
+       u32 value;
+} __attribute__((__packed__));
+
+#define BCM43xx_PHYMODE(phytype)       (1 << (phytype))
+#define BCM43xx_PHYMODE_A              BCM43xx_PHYMODE(BCM43xx_PHYTYPE_A)
+#define BCM43xx_PHYMODE_B              BCM43xx_PHYMODE(BCM43xx_PHYTYPE_B)
+#define BCM43xx_PHYMODE_G              BCM43xx_PHYMODE(BCM43xx_PHYTYPE_G)
+
+struct bcm43xx_phy {
+       /* Possible PHYMODEs on this PHY */
+       u8 possible_phymodes;
+       /* GMODE bit enabled? */
+       u8 gmode;
+       /* Possible ieee80211 subsystem hwmodes for this PHY.
+        * Which mode is selected, depends on thr GMODE enabled bit */
+#define BCM43xx_MAX_PHYHWMODES 2
+       struct ieee80211_hw_mode hwmodes[BCM43xx_MAX_PHYHWMODES];
+
+       /* Analog Type */
+       u8 analog;
+       /* BCM43xx_PHYTYPE_ */
+       u8 type;
+       /* PHY revision number. */
+       u8 rev;
+
+       /* Radio versioning */
+       u16 radio_manuf;        /* Radio manufacturer */
+       u16 radio_ver;          /* Radio version */
+       u8 radio_rev;           /* Radio revision */
+
+       u8 radio_on:1;          /* Radio switched on/off */
+       u8 locked:1;            /* Only used in bcm43xx_phy_{un}lock() */
+       u8 dyn_tssi_tbl:1;      /* tssi2dbm is kmalloc()ed. */
+
+       /* ACI (adjacent channel interference) flags. */
+       u8 aci_enable:1;
+       u8 aci_wlan_automatic:1;
+       u8 aci_hw_rssi:1;
+
+       u16 minlowsig[2];
+       u16 minlowsigpos[2];
+
+       /* TSSI to dBm table in use */
+       const s8 *tssi2dbm;
+       /* Target idle TSSI */
+       int tgt_idle_tssi;
+       /* Current idle TSSI */
+       int cur_idle_tssi;
+
+       /* LocalOscillator control values. */
+       struct bcm43xx_txpower_lo_control *lo_control;
+       /* Values from bcm43xx_calc_loopback_gain() */
+       s16 max_lb_gain;        /* Maximum Loopback gain in hdB */
+       s16 trsw_rx_gain;       /* TRSW RX gain in hdB */
+       s16 lna_lod_gain;       /* LNA lod */
+       s16 lna_gain;           /* LNA */
+       s16 pga_gain;           /* PGA */
+
+       /* PHY lock for core.rev < 3
+        * This lock is only used by bcm43xx_phy_{un}lock()
+        */
+       spinlock_t lock;
+
+       /* Desired TX power level (in dBm).
+        * This is set by the user and adjusted in bcm43xx_phy_xmitpower(). */
+       u8 power_level;
+       /* TX Power control values. */
+       /* B/G PHY */
+       struct {
+               /* Current Radio Attenuation for TXpower recalculation. */
+               u16 rfatt;
+               /* Current Baseband Attenuation for TXpower recalculation. */
+               u16 bbatt;
+               /* Current TXpower control value for TXpower recalculation. */
+               u16 txctl1;
+       };
+       /* A PHY */
+       struct {
+               u16 txpwr_offset;
+       };
+
+       /* Current Interference Mitigation mode */
+       int interfmode;
+       /* Stack of saved values from the Interference Mitigation code.
+        * Each value in the stack is layed out as follows:
+        * bit 0-11:  offset
+        * bit 12-15: register ID
+        * bit 16-32: value
+        * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
+        */
+#define BCM43xx_INTERFSTACK_SIZE       26
+       u32 interfstack[BCM43xx_INTERFSTACK_SIZE];//FIXME: use a data structure
+
+       /* Saved values from the NRSSI Slope calculation */
+       s16 nrssi[2];
+       s32 nrssislope;
+       /* In memory nrssi lookup table. */
+       s8 nrssi_lt[64];
+
+       /* current channel */
+       u8 channel;
+
+       u16 lofcal;
+
+       u16 initval;//FIXME rename?
+};
+
+/* Data structures for DMA transmission, per 80211 core. */
+struct bcm43xx_dma {
+       struct bcm43xx_dmaring *tx_ring0;
+       struct bcm43xx_dmaring *tx_ring1;
+       struct bcm43xx_dmaring *tx_ring2;
+       struct bcm43xx_dmaring *tx_ring3;
+       struct bcm43xx_dmaring *tx_ring4;
+       struct bcm43xx_dmaring *tx_ring5;
+
+       struct bcm43xx_dmaring *rx_ring0;
+       struct bcm43xx_dmaring *rx_ring3; /* only available on core.rev < 5 */
+};
+
+/* Data structures for PIO transmission, per 80211 core. */
+struct bcm43xx_pio {
+       struct bcm43xx_pioqueue *queue0;
+       struct bcm43xx_pioqueue *queue1;
+       struct bcm43xx_pioqueue *queue2;
+       struct bcm43xx_pioqueue *queue3;
+};
+
+/* Context information for a noise calculation (Link Quality). */
+struct bcm43xx_noise_calculation {
+       u8 channel_at_start;
+       u8 calculation_running:1;
+       u8 nr_samples;
+       s8 samples[8][4];
+};
+
+struct bcm43xx_stats {
+       u8 link_noise;
+       /* Store the last TX/RX times here for updating the leds. */
+       unsigned long last_tx;
+       unsigned long last_rx;
+};
+
+struct bcm43xx_key {
+       u8 enabled;
+       u8 algorithm;
+       u8 address[6];
+};
+
+struct bcm43xx_wldev;
+
+/* Data structure for the WLAN parts (802.11 cores) of the bcm43xx chip. */
+struct bcm43xx_wl {
+       /* Pointer to the active wireless device on this chip */
+       struct bcm43xx_wldev *current_dev;
+       /* Pointer to the ieee80211 hardware data structure */
+       struct ieee80211_hw *hw;
+
+       spinlock_t irq_lock;
+       struct mutex mutex;
+       spinlock_t leds_lock;
+
+       /* We can only have one operating interface (802.11 core)
+        * at a time. General information about this interface follows.
+        */
+
+       /* Opaque ID of the operating interface (!= monitor
+        * interface) from the ieee80211 subsystem.
+        * Do not modify.
+        */
+       int if_id;
+       /* MAC address. */
+       u8 *mac_addr;
+       /* Current BSSID (if any). */
+       u8 *bssid;
+       /* Interface type. (IEEE80211_IF_TYPE_XXX) */
+       int if_type;
+       /* Counter of active monitor interfaces. */
+       int monitor;
+       /* Is the card operating in AP, STA or IBSS mode? */
+       unsigned int operating:1;
+       /* Promisc mode active?
+        * Note that (monitor != 0) implies promisc.
+        */
+       unsigned int promisc:1;
+       /* Stats about the wireless interface */
+       struct ieee80211_low_level_stats ieee_stats;
+
+       struct hwrng rng;
+       u8 rng_initialized;
+       char rng_name[30 + 1];
+
+       /* List of all wireless devices on this chip */
+       struct list_head devlist;
+       u8 nr_devs;
+};
+
+/* Pointers to the firmware data and meta information about it. */
+struct bcm43xx_firmware {
+       /* Microcode */
+       const struct firmware *ucode;
+       /* PCM code */
+       const struct firmware *pcm;
+       /* Initial MMIO values 0 */
+       const struct firmware *initvals0;
+       /* Initial MMIO values 1 */
+       const struct firmware *initvals1;
+       /* Firmware revision */
+       u16 rev;
+       /* Firmware patchlevel */
+       u16 patch;
+};
+
+/* Device (802.11 core) initialization status. */
+enum {
+       BCM43xx_STAT_UNINIT,            /* Uninitialized. */
+       BCM43xx_STAT_INITIALIZING,      /* bcm43xx_wireless_core_init() in progress. */
+       BCM43xx_STAT_INITIALIZED,       /* Initialized. Note that this doesn't mean it's started. */
+};
+#define bcm43xx_status(bcm)            atomic_read(&(bcm)->init_status)
+#define bcm43xx_set_status(bcm, stat)  do {                    \
+               atomic_set(&(bcm)->init_status, (stat));        \
+               smp_wmb();                                      \
+                                       } while (0)
+
+/* XXX---   HOW LOCKING WORKS IN BCM43xx   ---XXX
+ *
+ * You should always acquire both, wl->mutex and wl->irq_lock unless:
+ * - You don't need to acquire wl->irq_lock, if the interface is stopped.
+ * - You don't need to acquire wl->mutex in the IRQ handler, IRQ tasklet
+ *   and packet TX path (and _ONLY_ there.)
+ */
+
+/* Data structure for one wireless device (802.11 core) */
+struct bcm43xx_wldev {
+       struct ssb_device *dev;
+       struct bcm43xx_wl *wl;
+
+       /* Driver initialization status BCM43xx_STAT_*** */
+       atomic_t init_status;
+       /* Interface started? (bcm43xx_wireless_core_start()) */
+       u8 started;
+
+       u16 was_initialized:1,          /* for suspend/resume. */
+           was_started:1,              /* for suspend/resume. */
+           __using_pio:1,              /* Internal, use bcm43xx_using_pio(). */
+           bad_frames_preempt:1,       /* Use "Bad Frames Preemption" (default off) */
+           reg124_set_0x4:1,           /* Some variable to keep track of IRQ stuff. */
+           short_preamble:1,           /* TRUE, if short preamble is enabled. */
+           short_slot:1,               /* TRUE, if short slot timing is enabled. */
+           radio_hw_enable:1;          /* saved state of radio hardware enabled state */
+
+       /* PHY/Radio device. */
+       struct bcm43xx_phy phy;
+       union {
+               /* DMA engines. */
+               struct bcm43xx_dma dma;
+               /* PIO engines. */
+               struct bcm43xx_pio pio;
+       };
+
+       /* Various statistics about the physical device. */
+       struct bcm43xx_stats stats;
+
+#define BCM43xx_NR_LEDS                4
+       struct bcm43xx_led leds[BCM43xx_NR_LEDS];
+
+       /* Reason code of the last interrupt. */
+       u32 irq_reason;
+       u32 dma_reason[6];
+       /* saved irq enable/disable state bitfield. */
+       u32 irq_savedstate;
+       /* Link Quality calculation context. */
+       struct bcm43xx_noise_calculation noisecalc;
+       /* if > 0 MAC is suspended. if == 0 MAC is enabled. */
+       int mac_suspended;
+
+       /* Interrupt Service Routine tasklet (bottom-half) */
+       struct tasklet_struct isr_tasklet;
+
+       /* Periodic tasks */
+       struct delayed_work periodic_work;
+       unsigned int periodic_state;
+
+       struct work_struct restart_work;
+
+       /* encryption/decryption */
+       u16 ktp; /* Key table pointer */
+       u8 max_nr_keys;
+       struct bcm43xx_key key[58];
+
+       /* Cached beacon template while uploading the template. */
+       struct sk_buff *cached_beacon;
+
+       /* Firmware data */
+       struct bcm43xx_firmware fw;
+
+       /* Devicelist in struct bcm43xx_wl (all 802.11 cores) */
+       struct list_head list;
+
+       /* Debugging stuff follows. */
+#ifdef CONFIG_BCM43XX_MAC80211_DEBUG
+       struct bcm43xx_dfsentry *dfsentry;
+#endif
+};
+
+
+static inline
+struct bcm43xx_wl * hw_to_bcm43xx_wl(struct ieee80211_hw *hw)
+{
+       return hw->priv;
+}
+
+/* Helper function, which returns a boolean.
+ * TRUE, if PIO is used; FALSE, if DMA is used.
+ */
+#if defined(CONFIG_BCM43XX_MAC80211_DMA) && defined(CONFIG_BCM43XX_MAC80211_PIO)
+static inline
+int bcm43xx_using_pio(struct bcm43xx_wldev *dev)
+{
+       return dev->__using_pio;
+}
+#elif defined(CONFIG_BCM43XX_MAC80211_DMA)
+static inline
+int bcm43xx_using_pio(struct bcm43xx_wldev *dev)
+{
+       return 0;
+}
+#elif defined(CONFIG_BCM43XX_MAC80211_PIO)
+static inline
+int bcm43xx_using_pio(struct bcm43xx_wldev *dev)
+{
+       return 1;
+}
+#else
+# error "Using neither DMA nor PIO? Confused..."
+#endif
+
+
+static inline
+struct bcm43xx_wldev * dev_to_bcm43xx_wldev(struct device *dev)
+{
+       struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
+       return ssb_get_drvdata(ssb_dev);
+}
+
+/* Is the device operating in a specified mode (IEEE80211_IF_TYPE_XXX). */
+static inline
+int bcm43xx_is_mode(struct bcm43xx_wl *wl, int type)
+{
+       if (type == IEEE80211_IF_TYPE_MNTR)
+               return !!(wl->monitor);
+       return (wl->operating &&
+               wl->if_type == type);
+}
+
+static inline
+u16 bcm43xx_read16(struct bcm43xx_wldev *dev, u16 offset)
+{
+       return ssb_read16(dev->dev, offset);
+}
+
+static inline
+void bcm43xx_write16(struct bcm43xx_wldev *dev, u16 offset, u16 value)
+{
+       ssb_write16(dev->dev, offset, value);
+}
+
+static inline
+u32 bcm43xx_read32(struct bcm43xx_wldev *dev, u16 offset)
+{
+       return ssb_read32(dev->dev, offset);
+}
+
+static inline
+void bcm43xx_write32(struct bcm43xx_wldev *dev, u16 offset, u32 value)
+{
+       ssb_write32(dev->dev, offset, value);
+}
+
+/** Limit a value between two limits */
+#ifdef limit_value
+# undef limit_value
+#endif
+#define limit_value(value, min, max)  \
+       ({                                              \
+               typeof(value) __value = (value);        \
+               typeof(value) __min = (min);            \
+               typeof(value) __max = (max);            \
+               if (__value < __min)                    \
+                       __value = __min;                \
+               else if (__value > __max)               \
+                       __value = __max;                \
+               __value;                                \
+       })
+
+#endif /* BCM43xx_H_ */
diff --git a/package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_debugfs.c b/package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_debugfs.c
new file mode 100644 (file)
index 0000000..b24bf63
--- /dev/null
@@ -0,0 +1,433 @@
+/*
+
+  Broadcom BCM43xx wireless driver
+
+  debugfs driver debugging code
+
+  Copyright (c) 2005 Michael Buesch <mb@bu3sch.de>
+
+  This program is free software; you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation; either version 2 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program; see the file COPYING.  If not, write to
+  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
+  Boston, MA 02110-1301, USA.
+
+*/
+
+
+
+#include <linux/fs.h>
+#include <linux/debugfs.h>
+#include <linux/slab.h>
+#include <linux/netdevice.h>
+#include <linux/pci.h>
+#include <linux/mutex.h>
+
+#include "bcm43xx.h"
+#include "bcm43xx_main.h"
+#include "bcm43xx_debugfs.h"
+#include "bcm43xx_dma.h"
+#include "bcm43xx_pio.h"
+#include "bcm43xx_xmit.h"
+
+#define REALLY_BIG_BUFFER_SIZE (1024*256)
+
+static struct bcm43xx_debugfs fs;
+static char big_buffer[1024*256];
+static DEFINE_MUTEX(big_buffer_mutex);
+
+
+static ssize_t write_file_dummy(struct file *file, const char __user *buf,
+                               size_t count, loff_t *ppos)
+{
+       return count;
+}
+
+static int open_file_generic(struct inode *inode, struct file *file)
+{
+       file->private_data = inode->i_private;
+       return 0;
+}
+
+#define fappend(fmt, x...)     pos += snprintf(buf + pos, len - pos, fmt , ##x)
+
+static ssize_t drvinfo_read_file(struct file *file, char __user *userbuf,
+                                size_t count, loff_t *ppos)
+{
+       const size_t len = ARRAY_SIZE(big_buffer);
+       char *buf = big_buffer;
+       size_t pos = 0;
+       ssize_t res;
+
+       mutex_lock(&big_buffer_mutex);
+       /* This is where the information is written to the "driver" file */
+       fappend(KBUILD_MODNAME " driver\n");
+       fappend("Compiled at: %s %s\n", __DATE__, __TIME__);
+       res = simple_read_from_buffer(userbuf, count, ppos, buf, pos);
+       mutex_unlock(&big_buffer_mutex);
+
+       return res;
+}
+
+static ssize_t tsf_read_file(struct file *file, char __user *userbuf,
+                            size_t count, loff_t *ppos)
+{
+       struct bcm43xx_wldev *dev = file->private_data;
+       const size_t len = ARRAY_SIZE(big_buffer);
+       char *buf = big_buffer;
+       size_t pos = 0;
+       ssize_t res;
+       unsigned long flags;
+       u64 tsf;
+
+       mutex_lock(&big_buffer_mutex);
+       mutex_lock(&dev->wl->mutex);
+       spin_lock_irqsave(&dev->wl->irq_lock, flags);
+       if (bcm43xx_status(dev) != BCM43xx_STAT_INITIALIZED) {
+               fappend("Board not initialized.\n");
+               goto out;
+       }
+       bcm43xx_tsf_read(dev, &tsf);
+       fappend("0x%08x%08x\n",
+               (unsigned int)((tsf & 0xFFFFFFFF00000000ULL) >> 32),
+               (unsigned int)(tsf & 0xFFFFFFFFULL));
+
+out:
+       spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
+       mutex_unlock(&dev->wl->mutex);
+       res = simple_read_from_buffer(userbuf, count, ppos, buf, pos);
+       mutex_unlock(&big_buffer_mutex);
+
+       return res;
+}
+
+static ssize_t tsf_write_file(struct file *file, const char __user *user_buf,
+                             size_t count, loff_t *ppos)
+{
+       struct bcm43xx_wldev *dev = file->private_data;
+       char *buf = big_buffer;
+       ssize_t buf_size;
+       ssize_t res;
+       unsigned long flags;
+       u64 tsf;
+
+       mutex_lock(&big_buffer_mutex);
+       buf_size = min(count, ARRAY_SIZE(big_buffer) - 1);
+       if (copy_from_user(buf, user_buf, buf_size)) {
+               res = -EFAULT;
+               goto out_unlock_bb;
+       }
+       mutex_lock(&dev->wl->mutex);
+       spin_lock_irqsave(&dev->wl->irq_lock, flags);
+       if (bcm43xx_status(dev) != BCM43xx_STAT_INITIALIZED) {
+               printk(KERN_INFO PFX "debugfs: Board not initialized.\n");
+               res = -EFAULT;
+               goto out_unlock;
+       }
+       if (sscanf(buf, "%llu", (unsigned long long *)(&tsf)) != 1) {
+               printk(KERN_INFO PFX "debugfs: invalid values for \"tsf\"\n");
+               res = -EINVAL;
+               goto out_unlock;
+       }
+       bcm43xx_tsf_write(dev, tsf);
+       mmiowb();
+       res = buf_size;
+
+out_unlock:
+       spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
+       mutex_unlock(&dev->wl->mutex);
+out_unlock_bb:
+       mutex_unlock(&big_buffer_mutex);
+
+       return res;
+}
+
+static ssize_t txstat_read_file(struct file *file, char __user *userbuf,
+                               size_t count, loff_t *ppos)
+{
+       struct bcm43xx_wldev *dev = file->private_data;
+       struct bcm43xx_dfsentry *e = dev->dfsentry;
+       struct bcm43xx_txstatus_log *log = &e->txstatlog;
+       unsigned long flags;
+       char *buf = log->printbuf;
+       const size_t len = ARRAY_SIZE(log->printbuf);
+       size_t pos = 0;
+       ssize_t res;
+       int i, idx;
+       struct bcm43xx_txstatus *stat;
+
+       mutex_lock(&big_buffer_mutex);
+       spin_lock_irqsave(&log->lock, flags);
+       if (!log->printing) {
+               log->printing = 1;
+               fappend("bcm43xx TX status reports:\n\n"
+                       "index | cookie | seq | phy_stat | frame_count | "
+                       "rts_count | supp_reason | pm_indicated | "
+                       "intermediate | for_ampdu | acked\n"
+                       "---\n");
+               i = log->end + 1;
+               idx = 0;
+               while (1) {
+                       if (i == BCM43xx_NR_LOGGED_TXSTATUS)
+                               i = 0;
+                       stat = &(log->log[i]);
+                       if (stat->cookie) {
+                               fappend("%03d | "
+                                       "0x%04X | 0x%04X | 0x%02X | "
+                                       "0x%X | 0x%X | "
+                                       "%u | %u | "
+                                       "%u | %u | %u\n",
+                                       idx,
+                                       stat->cookie, stat->seq, stat->phy_stat,
+                                       stat->frame_count, stat->rts_count,
+                                       stat->supp_reason, stat->pm_indicated,
+                                       stat->intermediate, stat->for_ampdu,
+                                       stat->acked);
+                               idx++;
+                       }
+                       if (i == log->end)
+                               break;
+                       i++;
+               }
+               log->buf_avail = pos;
+       }
+       memcpy(big_buffer, buf,
+              min(log->buf_avail, ARRAY_SIZE(big_buffer)));
+       spin_unlock_irqrestore(&log->lock, flags);
+
+       res = simple_read_from_buffer(userbuf, count, ppos,
+                                     big_buffer,
+                                     log->buf_avail);
+       if (*ppos == log->buf_avail) {
+               spin_lock_irqsave(&log->lock, flags);
+               log->printing = 0;
+               spin_unlock_irqrestore(&log->lock, flags);
+       }
+       mutex_unlock(&big_buffer_mutex);
+
+       return res;
+}
+
+static ssize_t restart_write_file(struct file *file, const char __user *user_buf,
+                                 size_t count, loff_t *ppos)
+{
+       struct bcm43xx_wldev *dev = file->private_data;
+       char *buf = big_buffer;
+       ssize_t buf_size;
+       ssize_t res;
+       unsigned long flags;
+
+       mutex_lock(&big_buffer_mutex);
+       buf_size = min(count, ARRAY_SIZE(big_buffer) - 1);
+       if (copy_from_user(buf, user_buf, buf_size)) {
+               res = -EFAULT;
+               goto out_unlock_bb;
+       }
+       mutex_lock(&dev->wl->mutex);
+       spin_lock_irqsave(&dev->wl->irq_lock, flags);
+       if (bcm43xx_status(dev) != BCM43xx_STAT_INITIALIZED) {
+               printk(KERN_INFO PFX "debugfs: Board not initialized.\n");
+               res = -EFAULT;
+               goto out_unlock;
+       }
+       if (count > 0 && buf[0] == '1') {
+               bcm43xx_controller_restart(dev, "manually restarted");
+               res = count;
+       } else
+               res = -EINVAL;
+
+out_unlock:
+       spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
+       mutex_unlock(&dev->wl->mutex);
+out_unlock_bb:
+       mutex_unlock(&big_buffer_mutex);
+
+       return res;
+}
+
+#undef fappend
+
+
+static struct file_operations drvinfo_fops = {
+       .read = drvinfo_read_file,
+       .write = write_file_dummy,
+       .open = open_file_generic,
+};
+
+static struct file_operations tsf_fops = {
+       .read = tsf_read_file,
+       .write = tsf_write_file,
+       .open = open_file_generic,
+};
+
+static struct file_operations txstat_fops = {
+       .read = txstat_read_file,
+       .write = write_file_dummy,
+       .open = open_file_generic,
+};
+
+static struct file_operations restart_fops = {
+       .write = restart_write_file,
+       .open = open_file_generic,
+};
+
+
+void bcm43xx_debugfs_add_device(struct bcm43xx_wldev *dev)
+{
+       struct bcm43xx_dfsentry *e;
+       struct bcm43xx_txstatus_log *log;
+       char devdir[16];
+
+       assert(dev);
+       e = kzalloc(sizeof(*e), GFP_KERNEL);
+       if (!e) {
+               printk(KERN_ERR PFX "out of memory\n");
+               return;
+       }
+       e->dev = dev;
+       log = &e->txstatlog;
+       log->log = kcalloc(BCM43xx_NR_LOGGED_TXSTATUS,
+                          sizeof(struct bcm43xx_txstatus),
+                          GFP_KERNEL);
+       if (!log->log) {
+               printk(KERN_ERR PFX "debugfs txstatus log OOM\n");
+               kfree(e);
+               return;
+       }
+       log->end = -1;
+       spin_lock_init(&log->lock);
+
+       dev->dfsentry = e;
+
+       snprintf(devdir, sizeof(devdir), "%s", wiphy_name(dev->wl->hw->wiphy));
+       e->subdir = debugfs_create_dir(devdir, fs.root);
+       e->dentry_tsf = debugfs_create_file("tsf", 0666, e->subdir,
+                                           dev, &tsf_fops);
+       if (!e->dentry_tsf)
+               printk(KERN_ERR PFX "debugfs: creating \"tsf\" for \"%s\" failed!\n", devdir);
+       e->dentry_txstat = debugfs_create_file("tx_status", 0444, e->subdir,
+                                               dev, &txstat_fops);
+       if (!e->dentry_txstat)
+               printk(KERN_ERR PFX "debugfs: creating \"tx_status\" for \"%s\" failed!\n", devdir);
+       e->dentry_restart = debugfs_create_file("restart", 0222, e->subdir,
+                                               dev, &restart_fops);
+       if (!e->dentry_restart)
+               printk(KERN_ERR PFX "debugfs: creating \"restart\" for \"%s\" failed!\n", devdir);
+}
+
+void bcm43xx_debugfs_remove_device(struct bcm43xx_wldev *dev)
+{
+       struct bcm43xx_dfsentry *e;
+
+       if (!dev)
+               return;
+
+       e = dev->dfsentry;
+       assert(e);
+       debugfs_remove(e->dentry_tsf);
+       debugfs_remove(e->dentry_txstat);
+       debugfs_remove(e->dentry_restart);
+       debugfs_remove(e->subdir);
+       kfree(e->txstatlog.log);
+       kfree(e);
+}
+
+void bcm43xx_debugfs_log_txstat(struct bcm43xx_wldev *dev,
+                               const struct bcm43xx_txstatus *status)
+{
+       struct bcm43xx_dfsentry *e = dev->dfsentry;
+       struct bcm43xx_txstatus_log *log;
+       struct bcm43xx_txstatus *cur;
+       int i;
+
+       log = &e->txstatlog;
+       assert(irqs_disabled());
+       spin_lock(&log->lock);
+       i = log->end + 1;
+       if (i == BCM43xx_NR_LOGGED_TXSTATUS)
+               i = 0;
+       log->end = i;
+       cur = &(log->log[i]);
+       memcpy(cur, status, sizeof(*cur));
+       spin_unlock(&log->lock);
+}
+
+void bcm43xx_debugfs_init(void)
+{
+       memset(&fs, 0, sizeof(fs));
+       fs.root = debugfs_create_dir(KBUILD_MODNAME, NULL);
+       if (!fs.root)
+               printk(KERN_ERR PFX "debugfs: creating \"" KBUILD_MODNAME "\" subdir failed!\n");
+       fs.dentry_driverinfo = debugfs_create_file("driver", 0444, fs.root, NULL, &drvinfo_fops);
+       if (!fs.dentry_driverinfo)
+               printk(KERN_ERR PFX "debugfs: creating \"" KBUILD_MODNAME "/driver\" failed!\n");
+}
+
+void bcm43xx_debugfs_exit(void)
+{
+       debugfs_remove(fs.dentry_driverinfo);
+       debugfs_remove(fs.root);
+}
+
+void bcm43xx_printk_dump(const char *data,
+                        size_t size,
+                        const char *description)
+{
+       unsigned int i;
+       char c;
+
+       printk(KERN_INFO PFX "Data dump (%s, %lu bytes):",
+              description, (unsigned long)size);
+       for (i = 0; i < size; i++) {
+               c = data[i];
+               if (i % 8 == 0)
+                       printk("\n" KERN_INFO PFX "0x%08x:  0x%02x, ", i, c & 0xff);
+               else
+                       printk("0x%02x, ", c & 0xff);
+       }
+       printk("\n");
+}
+
+void bcm43xx_printk_bitdump(const unsigned char *data,
+                           size_t bytes, int msb_to_lsb,
+                           const char *description)
+{
+       unsigned int i;
+       int j;
+       const unsigned char *d;
+
+       printk(KERN_INFO PFX "*** Bitdump (%s, %lu bytes, %s) ***",
+              description, (unsigned long)bytes,
+              msb_to_lsb ? "MSB to LSB" : "LSB to MSB");
+       for (i = 0; i < bytes; i++) {
+               d = data + i;
+               if (i % 8 == 0)
+                       printk("\n" KERN_INFO PFX "0x%08x:  ", i);
+               if (msb_to_lsb) {
+                       for (j = 7; j >= 0; j--) {
+                               if (*d & (1 << j))
+                                       printk("1");
+                               else
+                                       printk("0");
+                       }
+               } else {
+                       for (j = 0; j < 8; j++) {
+                               if (*d & (1 << j))
+                                       printk("1");
+                               else
+                                       printk("0");
+                       }
+               }
+               printk(" ");
+       }
+       printk("\n");
+}
diff --git a/package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_debugfs.h b/package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_debugfs.h
new file mode 100644 (file)
index 0000000..42c3062
--- /dev/null
@@ -0,0 +1,110 @@
+#ifndef BCM43xx_DEBUGFS_H_
+#define BCM43xx_DEBUGFS_H_
+
+struct bcm43xx_wldev;
+struct bcm43xx_txstatus;
+
+#ifdef CONFIG_BCM43XX_MAC80211_DEBUG
+
+struct dentry;
+
+#define BCM43xx_NR_LOGGED_TXSTATUS     100
+
+struct bcm43xx_txstatus_log {
+       struct bcm43xx_txstatus *log;
+       int end;
+       int printing;
+       char printbuf[(BCM43xx_NR_LOGGED_TXSTATUS * 70) + 200];
+       size_t buf_avail;
+       spinlock_t lock;
+};
+
+struct bcm43xx_dfsentry {
+       struct dentry *subdir;
+       struct dentry *dentry_tsf;
+       struct dentry *dentry_txstat;
+       struct dentry *dentry_restart;
+
+       struct bcm43xx_wldev *dev;
+
+       struct bcm43xx_txstatus_log txstatlog;
+};
+
+struct bcm43xx_debugfs {
+       struct dentry *root;
+       struct dentry *dentry_driverinfo;
+};
+
+void bcm43xx_debugfs_init(void);
+void bcm43xx_debugfs_exit(void);
+void bcm43xx_debugfs_add_device(struct bcm43xx_wldev *dev);
+void bcm43xx_debugfs_remove_device(struct bcm43xx_wldev *dev);
+void bcm43xx_debugfs_log_txstat(struct bcm43xx_wldev *dev,
+                               const struct bcm43xx_txstatus *status);
+
+/* Debug helper: Dump binary data through printk. */
+void bcm43xx_printk_dump(const char *data,
+                        size_t size,
+                        const char *description);
+/* Debug helper: Dump bitwise binary data through printk. */
+void bcm43xx_printk_bitdump(const unsigned char *data,
+                           size_t bytes, int msb_to_lsb,
+                           const char *description);
+#define bcm43xx_printk_bitdumpt(pointer, msb_to_lsb, description) \
+       do {                                                                    \
+               bcm43xx_printk_bitdump((const unsigned char *)(pointer),        \
+                                      sizeof(*(pointer)),                      \
+                                      (msb_to_lsb),                            \
+                                      (description));                          \
+       } while (0)
+
+#else /* CONFIG_BCM43XX_MAC80211_DEBUG*/
+
+static inline
+void bcm43xx_debugfs_init(void) { }
+static inline
+void bcm43xx_debugfs_exit(void) { }
+static inline
+void bcm43xx_debugfs_add_device(struct bcm43xx_wldev *dev) { }
+static inline
+void bcm43xx_debugfs_remove_device(struct bcm43xx_wldev *dev) { }
+static inline
+void bcm43xx_debugfs_log_txstat(struct bcm43xx_wldev *dev,
+                               const struct bcm43xx_txstatus *status) { }
+
+static inline
+void bcm43xx_printk_dump(const char *data,
+                        size_t size,
+                        const char *description)
+{
+}
+static inline
+void bcm43xx_printk_bitdump(const unsigned char *data,
+                           size_t bytes, int msb_to_lsb,
+                           const char *description)
+{
+}
+#define bcm43xx_printk_bitdumpt(pointer, msb_to_lsb, description)  do { /* nothing */ } while (0)
+
+#endif /* CONFIG_BCM43XX_MAC80211_DEBUG*/
+
+/* Ugly helper macros to make incomplete code more verbose on runtime */
+#ifdef TODO
+# undef TODO
+#endif
+#define TODO()  \
+       do {                                                                            \
+               printk(KERN_INFO PFX "TODO: Incomplete code in %s() at %s:%d\n",        \
+                      __FUNCTION__, __FILE__, __LINE__);                               \
+       } while (0)
+
+#ifdef FIXME
+# undef FIXME
+#endif
+#define FIXME()  \
+       do {                                                                            \
+               printk(KERN_INFO PFX "FIXME: Possibly broken code in %s() at %s:%d\n",  \
+                      __FUNCTION__, __FILE__, __LINE__);                               \
+       } while (0)
+
+#endif /* BCM43xx_DEBUGFS_H_ */
diff --git a/package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_dma.c b/package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_dma.c
new file mode 100644 (file)
index 0000000..0f66db5
--- /dev/null
@@ -0,0 +1,1383 @@
+/*
+
+  Broadcom BCM43xx wireless driver
+
+  DMA ringbuffer and descriptor allocation/management
+
+  Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
+
+  Some code in this file is derived from the b44.c driver
+  Copyright (C) 2002 David S. Miller
+  Copyright (C) Pekka Pietikainen
+
+  This program is free software; you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation; either version 2 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program; see the file COPYING.  If not, write to
+  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
+  Boston, MA 02110-1301, USA.
+
+*/
+
+#include "bcm43xx.h"
+#include "bcm43xx_dma.h"
+#include "bcm43xx_main.h"
+#include "bcm43xx_debugfs.h"
+#include "bcm43xx_power.h"
+#include "bcm43xx_xmit.h"
+
+#include <linux/dma-mapping.h>
+#include <linux/pci.h>
+#include <linux/delay.h>
+#include <linux/skbuff.h>
+
+
+/* 32bit DMA ops. */
+static
+struct bcm43xx_dmadesc_generic * op32_idx2desc(struct bcm43xx_dmaring *ring,
+                                              int slot,
+                                              struct bcm43xx_dmadesc_meta **meta)
+{
+       struct bcm43xx_dmadesc32 *desc;
+
+       *meta = &(ring->meta[slot]);
+       desc = ring->descbase;
+       desc = &(desc[slot]);
+
+       return (struct bcm43xx_dmadesc_generic *)desc;
+}
+
+static void op32_fill_descriptor(struct bcm43xx_dmaring *ring,
+                                struct bcm43xx_dmadesc_generic *desc,
+                                dma_addr_t dmaaddr, u16 bufsize,
+                                int start, int end, int irq)
+{
+       struct bcm43xx_dmadesc32 *descbase = ring->descbase;
+       int slot;
+       u32 ctl;
+       u32 addr;
+       u32 addrext;
+
+       slot = (int)(&(desc->dma32) - descbase);
+       assert(slot >= 0 && slot < ring->nr_slots);
+
+       addr = (u32)(dmaaddr & ~SSB_DMA_TRANSLATION_MASK);
+       addrext = (u32)(dmaaddr & SSB_DMA_TRANSLATION_MASK)
+                  >> SSB_DMA_TRANSLATION_SHIFT;
+       addr |= ssb_dma_translation(ring->dev->dev);
+       ctl = (bufsize - ring->frameoffset)
+             & BCM43xx_DMA32_DCTL_BYTECNT;
+       if (slot == ring->nr_slots - 1)
+               ctl |= BCM43xx_DMA32_DCTL_DTABLEEND;
+       if (start)
+               ctl |= BCM43xx_DMA32_DCTL_FRAMESTART;
+       if (end)
+               ctl |= BCM43xx_DMA32_DCTL_FRAMEEND;
+       if (irq)
+               ctl |= BCM43xx_DMA32_DCTL_IRQ;
+       ctl |= (addrext << BCM43xx_DMA32_DCTL_ADDREXT_SHIFT)
+              & BCM43xx_DMA32_DCTL_ADDREXT_MASK;
+
+       desc->dma32.control = cpu_to_le32(ctl);
+       desc->dma32.address = cpu_to_le32(addr);
+}
+
+static void op32_poke_tx(struct bcm43xx_dmaring *ring, int slot)
+{
+       bcm43xx_dma_write(ring, BCM43xx_DMA32_TXINDEX,
+                         (u32)(slot * sizeof(struct bcm43xx_dmadesc32)));
+}
+
+static void op32_tx_suspend(struct bcm43xx_dmaring *ring)
+{
+       bcm43xx_dma_write(ring, BCM43xx_DMA32_TXCTL,
+                         bcm43xx_dma_read(ring, BCM43xx_DMA32_TXCTL)
+                         | BCM43xx_DMA32_TXSUSPEND);
+}
+
+static void op32_tx_resume(struct bcm43xx_dmaring *ring)
+{
+       bcm43xx_dma_write(ring, BCM43xx_DMA32_TXCTL,
+                         bcm43xx_dma_read(ring, BCM43xx_DMA32_TXCTL)
+                         & ~BCM43xx_DMA32_TXSUSPEND);
+}
+
+static int op32_get_current_rxslot(struct bcm43xx_dmaring *ring)
+{
+       u32 val;
+
+       val = bcm43xx_dma_read(ring, BCM43xx_DMA32_RXSTATUS);
+       val &= BCM43xx_DMA32_RXDPTR;
+
+       return (val / sizeof(struct bcm43xx_dmadesc32));
+}
+
+static void op32_set_current_rxslot(struct bcm43xx_dmaring *ring,
+                                   int slot)
+{
+       bcm43xx_dma_write(ring, BCM43xx_DMA32_RXINDEX,
+                         (u32)(slot * sizeof(struct bcm43xx_dmadesc32)));
+}
+
+static const struct bcm43xx_dma_ops dma32_ops = {
+       .idx2desc               = op32_idx2desc,
+       .fill_descriptor        = op32_fill_descriptor,
+       .poke_tx                = op32_poke_tx,
+       .tx_suspend             = op32_tx_suspend,
+       .tx_resume              = op32_tx_resume,
+       .get_current_rxslot     = op32_get_current_rxslot,
+       .set_current_rxslot     = op32_set_current_rxslot,
+};
+
+/* 64bit DMA ops. */
+static
+struct bcm43xx_dmadesc_generic * op64_idx2desc(struct bcm43xx_dmaring *ring,
+                                              int slot,
+                                              struct bcm43xx_dmadesc_meta **meta)
+{
+       struct bcm43xx_dmadesc64 *desc;
+
+       *meta = &(ring->meta[slot]);
+       desc = ring->descbase;
+       desc = &(desc[slot]);
+
+       return (struct bcm43xx_dmadesc_generic *)desc;
+}
+
+static void op64_fill_descriptor(struct bcm43xx_dmaring *ring,
+                                struct bcm43xx_dmadesc_generic *desc,
+                                dma_addr_t dmaaddr, u16 bufsize,
+                                int start, int end, int irq)
+{
+       struct bcm43xx_dmadesc64 *descbase = ring->descbase;
+       int slot;
+       u32 ctl0 = 0, ctl1 = 0;
+       u32 addrlo, addrhi;
+       u32 addrext;
+
+       slot = (int)(&(desc->dma64) - descbase);
+       assert(slot >= 0 && slot < ring->nr_slots);
+
+       addrlo = (u32)(dmaaddr & 0xFFFFFFFF);
+       addrhi = (((u64)dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK);
+       addrext = (((u64)dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK)
+                 >> SSB_DMA_TRANSLATION_SHIFT;
+       addrhi |= ssb_dma_translation(ring->dev->dev);
+       if (slot == ring->nr_slots - 1)
+               ctl0 |= BCM43xx_DMA64_DCTL0_DTABLEEND;
+       if (start)
+               ctl0 |= BCM43xx_DMA64_DCTL0_FRAMESTART;
+       if (end)
+               ctl0 |= BCM43xx_DMA64_DCTL0_FRAMEEND;
+       if (irq)
+               ctl0 |= BCM43xx_DMA64_DCTL0_IRQ;
+       ctl1 |= (bufsize - ring->frameoffset)
+               & BCM43xx_DMA64_DCTL1_BYTECNT;
+       ctl1 |= (addrext << BCM43xx_DMA64_DCTL1_ADDREXT_SHIFT)
+               & BCM43xx_DMA64_DCTL1_ADDREXT_MASK;
+
+       desc->dma64.control0 = cpu_to_le32(ctl0);
+       desc->dma64.control1 = cpu_to_le32(ctl1);
+       desc->dma64.address_low = cpu_to_le32(addrlo);
+       desc->dma64.address_high = cpu_to_le32(addrhi);
+}
+
+static void op64_poke_tx(struct bcm43xx_dmaring *ring, int slot)
+{
+       bcm43xx_dma_write(ring, BCM43xx_DMA64_TXINDEX,
+                         (u32)(slot * sizeof(struct bcm43xx_dmadesc64)));
+}
+
+static void op64_tx_suspend(struct bcm43xx_dmaring *ring)
+{
+       bcm43xx_dma_write(ring, BCM43xx_DMA64_TXCTL,
+                         bcm43xx_dma_read(ring, BCM43xx_DMA64_TXCTL)
+                         | BCM43xx_DMA64_TXSUSPEND);
+}
+
+static void op64_tx_resume(struct bcm43xx_dmaring *ring)
+{
+       bcm43xx_dma_write(ring, BCM43xx_DMA64_TXCTL,
+                         bcm43xx_dma_read(ring, BCM43xx_DMA64_TXCTL)
+                         & ~BCM43xx_DMA64_TXSUSPEND);
+}
+
+static int op64_get_current_rxslot(struct bcm43xx_dmaring *ring)
+{
+       u32 val;
+
+       val = bcm43xx_dma_read(ring, BCM43xx_DMA64_RXSTATUS);
+       val &= BCM43xx_DMA64_RXSTATDPTR;
+
+       return (val / sizeof(struct bcm43xx_dmadesc64));
+}
+
+static void op64_set_current_rxslot(struct bcm43xx_dmaring *ring,
+                                   int slot)
+{
+       bcm43xx_dma_write(ring, BCM43xx_DMA64_RXINDEX,
+                         (u32)(slot * sizeof(struct bcm43xx_dmadesc64)));
+}
+
+static const struct bcm43xx_dma_ops dma64_ops = {
+       .idx2desc               = op64_idx2desc,
+       .fill_descriptor        = op64_fill_descriptor,
+       .poke_tx                = op64_poke_tx,
+       .tx_suspend             = op64_tx_suspend,
+       .tx_resume              = op64_tx_resume,
+       .get_current_rxslot     = op64_get_current_rxslot,
+       .set_current_rxslot     = op64_set_current_rxslot,
+};
+
+
+static inline int free_slots(struct bcm43xx_dmaring *ring)
+{
+       return (ring->nr_slots - ring->used_slots);
+}
+
+static inline int next_slot(struct bcm43xx_dmaring *ring, int slot)
+{
+       assert(slot >= -1 && slot <= ring->nr_slots - 1);
+       if (slot == ring->nr_slots - 1)
+               return 0;
+       return slot + 1;
+}
+
+static inline int prev_slot(struct bcm43xx_dmaring *ring, int slot)
+{
+       assert(slot >= 0 && slot <= ring->nr_slots - 1);
+       if (slot == 0)
+               return ring->nr_slots - 1;
+       return slot - 1;
+}
+
+/* Request a slot for usage. */
+static inline
+int request_slot(struct bcm43xx_dmaring *ring)
+{
+       int slot;
+
+       assert(ring->tx);
+       assert(!ring->stopped);
+       assert(free_slots(ring) != 0);
+
+       slot = next_slot(ring, ring->current_slot);
+       ring->current_slot = slot;
+       ring->used_slots++;
+
+#ifdef CONFIG_BCM43XX_MAC80211_DEBUG
+       if (ring->used_slots > ring->max_used_slots)
+               ring->max_used_slots = ring->used_slots;
+#endif /* CONFIG_BCM43XX_MAC80211_DEBUG*/
+
+       return slot;
+}
+
+/* Return a slot to the free slots. */
+static inline
+void return_slot(struct bcm43xx_dmaring *ring, int slot)
+{
+       assert(ring->tx);
+
+       ring->used_slots--;
+}
+
+u16 bcm43xx_dmacontroller_base(int dma64bit, int controller_idx)
+{
+       static const u16 map64[] = {
+               BCM43xx_MMIO_DMA64_BASE0,
+               BCM43xx_MMIO_DMA64_BASE1,
+               BCM43xx_MMIO_DMA64_BASE2,
+               BCM43xx_MMIO_DMA64_BASE3,
+               BCM43xx_MMIO_DMA64_BASE4,
+               BCM43xx_MMIO_DMA64_BASE5,
+       };
+       static const u16 map32[] = {
+               BCM43xx_MMIO_DMA32_BASE0,
+               BCM43xx_MMIO_DMA32_BASE1,
+               BCM43xx_MMIO_DMA32_BASE2,
+               BCM43xx_MMIO_DMA32_BASE3,
+               BCM43xx_MMIO_DMA32_BASE4,
+               BCM43xx_MMIO_DMA32_BASE5,
+       };
+
+       if (dma64bit) {
+               assert(controller_idx >= 0 &&
+                      controller_idx < ARRAY_SIZE(map64));
+               return map64[controller_idx];
+       }
+       assert(controller_idx >= 0 &&
+              controller_idx < ARRAY_SIZE(map32));
+       return map32[controller_idx];
+}
+
+static inline
+dma_addr_t map_descbuffer(struct bcm43xx_dmaring *ring,
+                         unsigned char *buf,
+                         size_t len,
+                         int tx)
+{
+       dma_addr_t dmaaddr;
+
+       if (tx) {
+               dmaaddr = dma_map_single(ring->dev->dev->dev,
+                                        buf, len,
+                                        DMA_TO_DEVICE);
+       } else {
+               dmaaddr = dma_map_single(ring->dev->dev->dev,
+                                        buf, len,
+                                        DMA_FROM_DEVICE);
+       }
+
+       return dmaaddr;
+}
+
+static inline
+void unmap_descbuffer(struct bcm43xx_dmaring *ring,
+                     dma_addr_t addr,
+                     size_t len,
+                     int tx)
+{
+       if (tx) {
+               dma_unmap_single(ring->dev->dev->dev,
+                                addr, len,
+                                DMA_TO_DEVICE);
+       } else {
+               dma_unmap_single(ring->dev->dev->dev,
+                                addr, len,
+                                DMA_FROM_DEVICE);
+       }
+}
+
+static inline
+void sync_descbuffer_for_cpu(struct bcm43xx_dmaring *ring,
+                            dma_addr_t addr,
+                            size_t len)
+{
+       assert(!ring->tx);
+
+       dma_sync_single_for_cpu(ring->dev->dev->dev,
+                               addr, len, DMA_FROM_DEVICE);
+}
+
+static inline
+void sync_descbuffer_for_device(struct bcm43xx_dmaring *ring,
+                               dma_addr_t addr,
+                               size_t len)
+{
+       assert(!ring->tx);
+
+       dma_sync_single_for_device(ring->dev->dev->dev,
+                                  addr, len, DMA_FROM_DEVICE);
+}
+
+static inline
+void free_descriptor_buffer(struct bcm43xx_dmaring *ring,
+                           struct bcm43xx_dmadesc_meta *meta,
+                           int irq_context)
+{
+       if (meta->skb) {
+               if (irq_context)
+                       dev_kfree_skb_irq(meta->skb);
+               else
+                       dev_kfree_skb(meta->skb);
+               meta->skb = NULL;
+       }
+}
+
+static int alloc_ringmemory(struct bcm43xx_dmaring *ring)
+{
+       struct device *dev = ring->dev->dev->dev;
+
+       ring->descbase = dma_alloc_coherent(dev, BCM43xx_DMA_RINGMEMSIZE,
+                                           &(ring->dmabase), GFP_KERNEL);
+       if (!ring->descbase) {
+               printk(KERN_ERR PFX "DMA ringmemory allocation failed\n");
+               return -ENOMEM;
+       }
+       memset(ring->descbase, 0, BCM43xx_DMA_RINGMEMSIZE);
+
+       return 0;
+}
+
+static void free_ringmemory(struct bcm43xx_dmaring *ring)
+{
+       struct device *dev = ring->dev->dev->dev;
+
+       dma_free_coherent(dev, BCM43xx_DMA_RINGMEMSIZE,
+                         ring->descbase, ring->dmabase);
+}
+
+/* Reset the RX DMA channel */
+int bcm43xx_dmacontroller_rx_reset(struct bcm43xx_wldev *dev,
+                                  u16 mmio_base, int dma64)
+{
+       int i;
+       u32 value;
+       u16 offset;
+
+       offset = dma64 ? BCM43xx_DMA64_RXCTL : BCM43xx_DMA32_RXCTL;
+       bcm43xx_write32(dev, mmio_base + offset, 0);
+       for (i = 0; i < 1000; i++) {
+               offset = dma64 ? BCM43xx_DMA64_RXSTATUS : BCM43xx_DMA32_RXSTATUS;
+               value = bcm43xx_read32(dev, mmio_base + offset);
+               if (dma64) {
+                       value &= BCM43xx_DMA64_RXSTAT;
+                       if (value == BCM43xx_DMA64_RXSTAT_DISABLED) {
+                               i = -1;
+                               break;
+                       }
+               } else {
+                       value &= BCM43xx_DMA32_RXSTATE;
+                       if (value == BCM43xx_DMA32_RXSTAT_DISABLED) {
+                               i = -1;
+                               break;
+                       }
+               }
+               udelay(10);
+       }
+       if (i != -1) {
+               printk(KERN_ERR PFX "Error: Wait on DMA RX status timed out.\n");
+               return -ENODEV;
+       }
+
+       return 0;
+}
+
+/* Reset the RX DMA channel */
+int bcm43xx_dmacontroller_tx_reset(struct bcm43xx_wldev *dev,
+                                  u16 mmio_base, int dma64)
+{
+       int i;
+       u32 value;
+       u16 offset;
+
+       for (i = 0; i < 1000; i++) {
+               offset = dma64 ? BCM43xx_DMA64_TXSTATUS : BCM43xx_DMA32_TXSTATUS;
+               value = bcm43xx_read32(dev, mmio_base + offset);
+               if (dma64) {
+                       value &= BCM43xx_DMA64_TXSTAT;
+                       if (value == BCM43xx_DMA64_TXSTAT_DISABLED ||
+                           value == BCM43xx_DMA64_TXSTAT_IDLEWAIT ||
+                           value == BCM43xx_DMA64_TXSTAT_STOPPED)
+                               break;
+               } else {
+                       value &= BCM43xx_DMA32_TXSTATE;
+                       if (value == BCM43xx_DMA32_TXSTAT_DISABLED ||
+                           value == BCM43xx_DMA32_TXSTAT_IDLEWAIT ||
+                           value == BCM43xx_DMA32_TXSTAT_STOPPED)
+                               break;
+               }
+               udelay(10);
+       }
+       offset = dma64 ? BCM43xx_DMA64_TXCTL : BCM43xx_DMA32_TXCTL;
+       bcm43xx_write32(dev, mmio_base + offset, 0);
+       for (i = 0; i < 1000; i++) {
+               offset = dma64 ? BCM43xx_DMA64_TXSTATUS : BCM43xx_DMA32_TXSTATUS;
+               value = bcm43xx_read32(dev, mmio_base + offset);
+               if (dma64) {
+                       value &= BCM43xx_DMA64_TXSTAT;
+                       if (value == BCM43xx_DMA64_TXSTAT_DISABLED) {
+                               i = -1;
+                               break;
+                       }
+               } else {
+                       value &= BCM43xx_DMA32_TXSTATE;
+                       if (value == BCM43xx_DMA32_TXSTAT_DISABLED) {
+                               i = -1;
+                               break;
+                       }
+               }
+               udelay(10);
+       }
+       if (i != -1) {
+               printk(KERN_ERR PFX "Error: Wait on DMA TX status timed out.\n");
+               return -ENODEV;
+       }
+       /* ensure the reset is completed. */
+       udelay(300);
+
+       return 0;
+}
+
+static int setup_rx_descbuffer(struct bcm43xx_dmaring *ring,
+                              struct bcm43xx_dmadesc_generic *desc,
+                              struct bcm43xx_dmadesc_meta *meta,
+                              gfp_t gfp_flags)
+{
+       struct bcm43xx_rxhdr_fw4 *rxhdr;
+       struct bcm43xx_hwtxstatus *txstat;
+       dma_addr_t dmaaddr;
+       struct sk_buff *skb;
+
+       assert(!ring->tx);
+
+       skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
+       if (unlikely(!skb))
+               return -ENOMEM;
+       dmaaddr = map_descbuffer(ring, skb->data,
+                                ring->rx_buffersize, 0);
+       if (dma_mapping_error(dmaaddr)) {
+               /* ugh. try to realloc in zone_dma */
+               gfp_flags |= GFP_DMA;
+
+               dev_kfree_skb_any(skb);
+
+               skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
+               if (unlikely(!skb))
+                       return -ENOMEM;
+               dmaaddr = map_descbuffer(ring, skb->data,
+                                        ring->rx_buffersize, 0);
+       }
+
+       if (dma_mapping_error(dmaaddr)) {
+               dev_kfree_skb_any(skb);
+               return -EIO;
+       }
+
+       meta->skb = skb;
+       meta->dmaaddr = dmaaddr;
+       ring->ops->fill_descriptor(ring, desc, dmaaddr,
+                                  ring->rx_buffersize, 0, 0, 0);
+
+       rxhdr = (struct bcm43xx_rxhdr_fw4 *)(skb->data);
+       rxhdr->frame_len = 0;
+       txstat = (struct bcm43xx_hwtxstatus *)(skb->data);
+       txstat->cookie = 0;
+
+       return 0;
+}
+
+/* Allocate the initial descbuffers.
+ * This is used for an RX ring only.
+ */
+static int alloc_initial_descbuffers(struct bcm43xx_dmaring *ring)
+{
+       int i, err = -ENOMEM;
+       struct bcm43xx_dmadesc_generic *desc;
+       struct bcm43xx_dmadesc_meta *meta;
+
+       for (i = 0; i < ring->nr_slots; i++) {
+               desc = ring->ops->idx2desc(ring, i, &meta);
+
+               err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
+               if (err) {
+                       printk(KERN_ERR PFX "Failed to allocate initial descbuffers\n");
+                       goto err_unwind;
+               }
+       }
+       mb();
+       ring->used_slots = ring->nr_slots;
+       err = 0;
+out:
+       return err;
+
+err_unwind:
+       for (i--; i >= 0; i--) {
+               desc = ring->ops->idx2desc(ring, i, &meta);
+
+               unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
+               dev_kfree_skb(meta->skb);
+       }
+       goto out;
+}
+
+/* Do initial setup of the DMA controller.
+ * Reset the controller, write the ring busaddress
+ * and switch the "enable" bit on.
+ */
+static int dmacontroller_setup(struct bcm43xx_dmaring *ring)
+{
+       int err = 0;
+       u32 value;
+       u32 addrext;
+       u32 trans = ssb_dma_translation(ring->dev->dev);
+
+       if (ring->tx) {
+               if (ring->dma64) {
+                       u64 ringbase = (u64)(ring->dmabase);
+
+                       addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
+                                 >> SSB_DMA_TRANSLATION_SHIFT;
+                       value = BCM43xx_DMA64_TXENABLE;
+                       value |= (addrext << BCM43xx_DMA64_TXADDREXT_SHIFT)
+                               & BCM43xx_DMA64_TXADDREXT_MASK;
+                       bcm43xx_dma_write(ring, BCM43xx_DMA64_TXCTL, value);
+                       bcm43xx_dma_write(ring, BCM43xx_DMA64_TXRINGLO,
+                                       (ringbase & 0xFFFFFFFF));
+                       bcm43xx_dma_write(ring, BCM43xx_DMA64_TXRINGHI,
+                                       ((ringbase >> 32) & ~SSB_DMA_TRANSLATION_MASK)
+                                       | trans);
+               } else {
+                       u32 ringbase = (u32)(ring->dmabase);
+
+                       addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
+                                 >> SSB_DMA_TRANSLATION_SHIFT;
+                       value = BCM43xx_DMA32_TXENABLE;
+                       value |= (addrext << BCM43xx_DMA32_TXADDREXT_SHIFT)
+                               & BCM43xx_DMA32_TXADDREXT_MASK;
+                       bcm43xx_dma_write(ring, BCM43xx_DMA32_TXCTL, value);
+                       bcm43xx_dma_write(ring, BCM43xx_DMA32_TXRING,
+                                       (ringbase & ~SSB_DMA_TRANSLATION_MASK)
+                                       | trans);
+               }
+       } else {
+               err = alloc_initial_descbuffers(ring);
+               if (err)
+                       goto out;
+               if (ring->dma64) {
+                       u64 ringbase = (u64)(ring->dmabase);
+
+                       addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
+                                 >> SSB_DMA_TRANSLATION_SHIFT;
+                       value = (ring->frameoffset << BCM43xx_DMA64_RXFROFF_SHIFT);
+                       value |= BCM43xx_DMA64_RXENABLE;
+                       value |= (addrext << BCM43xx_DMA64_RXADDREXT_SHIFT)
+                               & BCM43xx_DMA64_RXADDREXT_MASK;
+                       bcm43xx_dma_write(ring, BCM43xx_DMA64_RXCTL, value);
+                       bcm43xx_dma_write(ring, BCM43xx_DMA64_RXRINGLO,
+                                       (ringbase & 0xFFFFFFFF));
+                       bcm43xx_dma_write(ring, BCM43xx_DMA64_RXRINGHI,
+                                       ((ringbase >> 32) & ~SSB_DMA_TRANSLATION_MASK)
+                                       | trans);
+                       bcm43xx_dma_write(ring, BCM43xx_DMA64_RXINDEX, 200);
+               } else {
+                       u32 ringbase = (u32)(ring->dmabase);
+
+                       addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
+                                 >> SSB_DMA_TRANSLATION_SHIFT;
+                       value = (ring->frameoffset << BCM43xx_DMA32_RXFROFF_SHIFT);
+                       value |= BCM43xx_DMA32_RXENABLE;
+                       value |= (addrext << BCM43xx_DMA32_RXADDREXT_SHIFT)
+                               & BCM43xx_DMA32_RXADDREXT_MASK;
+                       bcm43xx_dma_write(ring, BCM43xx_DMA32_RXCTL, value);
+                       bcm43xx_dma_write(ring, BCM43xx_DMA32_RXRING,
+                                       (ringbase & ~SSB_DMA_TRANSLATION_MASK)
+                                       | trans);
+                       bcm43xx_dma_write(ring, BCM43xx_DMA32_RXINDEX, 200);
+               }
+       }
+
+out:
+       return err;
+}
+
+/* Shutdown the DMA controller. */
+static void dmacontroller_cleanup(struct bcm43xx_dmaring *ring)
+{
+       if (ring->tx) {
+               bcm43xx_dmacontroller_tx_reset(ring->dev, ring->mmio_base, ring->dma64);
+               if (ring->dma64) {
+                       bcm43xx_dma_write(ring, BCM43xx_DMA64_TXRINGLO, 0);
+                       bcm43xx_dma_write(ring, BCM43xx_DMA64_TXRINGHI, 0);
+               } else
+                       bcm43xx_dma_write(ring, BCM43xx_DMA32_TXRING, 0);
+       } else {
+               bcm43xx_dmacontroller_rx_reset(ring->dev, ring->mmio_base, ring->dma64);
+               if (ring->dma64) {
+                       bcm43xx_dma_write(ring, BCM43xx_DMA64_RXRINGLO, 0);
+                       bcm43xx_dma_write(ring, BCM43xx_DMA64_RXRINGHI, 0);
+               } else
+                       bcm43xx_dma_write(ring, BCM43xx_DMA32_RXRING, 0);
+       }
+}
+
+static void free_all_descbuffers(struct bcm43xx_dmaring *ring)
+{
+       struct bcm43xx_dmadesc_generic *desc;
+       struct bcm43xx_dmadesc_meta *meta;
+       int i;
+
+       if (!ring->used_slots)
+               return;
+       for (i = 0; i < ring->nr_slots; i++) {
+               desc = ring->ops->idx2desc(ring, i, &meta);
+
+               if (!meta->skb) {
+                       assert(ring->tx);
+                       continue;
+               }
+               if (ring->tx) {
+                       unmap_descbuffer(ring, meta->dmaaddr,
+                                       meta->skb->len, 1);
+               } else {
+                       unmap_descbuffer(ring, meta->dmaaddr,
+                                       ring->rx_buffersize, 0);
+               }
+               free_descriptor_buffer(ring, meta, 0);
+       }
+}
+
+static u64 supported_dma_mask(struct bcm43xx_wldev *dev)
+{
+       u32 tmp;
+       u16 mmio_base;
+
+       tmp = bcm43xx_read32(dev, SSB_TMSHIGH);
+       if (tmp & SSB_TMSHIGH_DMA64)
+               return DMA_64BIT_MASK;
+       mmio_base = bcm43xx_dmacontroller_base(0, 0);
+       bcm43xx_write32(dev,
+                       mmio_base + BCM43xx_DMA32_TXCTL,
+                       BCM43xx_DMA32_TXADDREXT_MASK);
+       tmp = bcm43xx_read32(dev,
+                            mmio_base + BCM43xx_DMA32_TXCTL);
+       if (tmp & BCM43xx_DMA32_TXADDREXT_MASK)
+               return DMA_32BIT_MASK;
+
+       return DMA_30BIT_MASK;
+}
+
+/* Main initialization function. */
+static
+struct bcm43xx_dmaring * bcm43xx_setup_dmaring(struct bcm43xx_wldev *dev,
+                                              int controller_index,
+                                              int for_tx,
+                                              int dma64)
+{
+       struct bcm43xx_dmaring *ring;
+       int err;
+       int nr_slots;
+       dma_addr_t dma_test;
+
+       ring = kzalloc(sizeof(*ring), GFP_KERNEL);
+       if (!ring)
+               goto out;
+
+       nr_slots = BCM43xx_RXRING_SLOTS;
+       if (for_tx)
+               nr_slots = BCM43xx_TXRING_SLOTS;
+
+       ring->meta = kcalloc(nr_slots, sizeof(struct bcm43xx_dmadesc_meta),
+                            GFP_KERNEL);
+       if (!ring->meta)
+               goto err_kfree_ring;
+       if (for_tx) {
+               ring->txhdr_cache = kcalloc(nr_slots,
+                                           sizeof(struct bcm43xx_txhdr_fw4),
+                                           GFP_KERNEL);
+               if (!ring->txhdr_cache)
+                       goto err_kfree_meta;
+
+               /* test for ability to dma to txhdr_cache */
+               dma_test = dma_map_single(dev->dev->dev,
+                               ring->txhdr_cache, sizeof(struct bcm43xx_txhdr_fw4),
+                               DMA_TO_DEVICE);
+
+               if (dma_mapping_error(dma_test)) {
+                       /* ugh realloc */
+                       kfree(ring->txhdr_cache);
+                       ring->txhdr_cache = kcalloc(nr_slots,
+                                                       sizeof(struct bcm43xx_txhdr_fw4),
+                                                       GFP_KERNEL | GFP_DMA);
+                       if (!ring->txhdr_cache)
+                               goto err_kfree_meta;
+
+                       dma_test = dma_map_single(dev->dev->dev,
+                                       ring->txhdr_cache, sizeof(struct bcm43xx_txhdr_fw4),
+                                       DMA_TO_DEVICE);
+
+                       if (dma_mapping_error(dma_test))
+                               goto err_kfree_txhdr_cache;
+               }
+
+               dma_unmap_single(dev->dev->dev,
+                               dma_test, sizeof(struct bcm43xx_txhdr_fw4),
+                               DMA_TO_DEVICE);
+       }
+
+       ring->dev = dev;
+       ring->nr_slots = nr_slots;
+       ring->mmio_base = bcm43xx_dmacontroller_base(dma64, controller_index);
+       ring->index = controller_index;
+       ring->dma64 = !!dma64;
+       if (dma64)
+               ring->ops = &dma64_ops;
+       else
+               ring->ops = &dma32_ops;
+       if (for_tx) {
+               ring->tx = 1;
+               ring->current_slot = -1;
+       } else {
+               if (ring->index == 0) {
+                       ring->rx_buffersize = BCM43xx_DMA0_RX_BUFFERSIZE;
+                       ring->frameoffset = BCM43xx_DMA0_RX_FRAMEOFFSET;
+               } else if (ring->index == 3) {
+                       ring->rx_buffersize = BCM43xx_DMA3_RX_BUFFERSIZE;
+                       ring->frameoffset = BCM43xx_DMA3_RX_FRAMEOFFSET;
+               } else
+                       assert(0);
+       }
+
+       err = alloc_ringmemory(ring);
+       if (err)
+               goto err_kfree_txhdr_cache;
+       err = dmacontroller_setup(ring);
+       if (err)
+               goto err_free_ringmemory;
+
+out:
+       return ring;
+
+err_free_ringmemory:
+       free_ringmemory(ring);
+err_kfree_txhdr_cache:
+       kfree(ring->txhdr_cache);
+err_kfree_meta:
+       kfree(ring->meta);
+err_kfree_ring:
+       kfree(ring);
+       ring = NULL;
+       goto out;
+}
+
+/* Main cleanup function. */
+static void bcm43xx_destroy_dmaring(struct bcm43xx_dmaring *ring)
+{
+       if (!ring)
+               return;
+
+       dprintk(KERN_INFO PFX "DMA-%s 0x%04X (%s) max used slots: %d/%d\n",
+               (ring->dma64) ? "64" : "32",
+               ring->mmio_base,
+               (ring->tx) ? "TX" : "RX",
+               ring->max_used_slots, ring->nr_slots);
+       /* Device IRQs are disabled prior entering this function,
+        * so no need to take care of concurrency with rx handler stuff.
+        */
+       dmacontroller_cleanup(ring);
+       free_all_descbuffers(ring);
+       free_ringmemory(ring);
+
+       kfree(ring->txhdr_cache);
+       kfree(ring->meta);
+       kfree(ring);
+}
+
+void bcm43xx_dma_free(struct bcm43xx_wldev *dev)
+{
+       struct bcm43xx_dma *dma;
+
+       if (bcm43xx_using_pio(dev))
+               return;
+       dma = &dev->dma;
+
+       bcm43xx_destroy_dmaring(dma->rx_ring3);
+       dma->rx_ring3 = NULL;
+       bcm43xx_destroy_dmaring(dma->rx_ring0);
+       dma->rx_ring0 = NULL;
+
+       bcm43xx_destroy_dmaring(dma->tx_ring5);
+       dma->tx_ring5 = NULL;
+       bcm43xx_destroy_dmaring(dma->tx_ring4);
+       dma->tx_ring4 = NULL;
+       bcm43xx_destroy_dmaring(dma->tx_ring3);
+       dma->tx_ring3 = NULL;
+       bcm43xx_destroy_dmaring(dma->tx_ring2);
+       dma->tx_ring2 = NULL;
+       bcm43xx_destroy_dmaring(dma->tx_ring1);
+       dma->tx_ring1 = NULL;
+       bcm43xx_destroy_dmaring(dma->tx_ring0);
+       dma->tx_ring0 = NULL;
+}
+
+int bcm43xx_dma_init(struct bcm43xx_wldev *dev)
+{
+       struct bcm43xx_dma *dma = &dev->dma;
+       struct bcm43xx_dmaring *ring;
+       int err;
+       u64 dmamask;
+       int dma64 = 0;
+
+       dmamask = supported_dma_mask(dev);
+       if (dmamask == DMA_64BIT_MASK)
+               dma64 = 1;
+
+       err = ssb_dma_set_mask(dev->dev, dmamask);
+       if (err) {
+#ifdef BCM43XX_MAC80211_PIO
+               printk(KERN_WARNING PFX "DMA for this device not supported. "
+                                       "Falling back to PIO\n");
+               dev->__using_pio = 1;
+               return -EAGAIN;
+#else
+               printk(KERN_ERR PFX "DMA for this device not supported and "
+                                   "no PIO support compiled in\n");
+               return -EOPNOTSUPP;
+#endif
+       }
+
+       err = -ENOMEM;
+       /* setup TX DMA channels. */
+       ring = bcm43xx_setup_dmaring(dev, 0, 1, dma64);
+       if (!ring)
+               goto out;
+       dma->tx_ring0 = ring;
+
+       ring = bcm43xx_setup_dmaring(dev, 1, 1, dma64);
+       if (!ring)
+               goto err_destroy_tx0;
+       dma->tx_ring1 = ring;
+
+       ring = bcm43xx_setup_dmaring(dev, 2, 1, dma64);
+       if (!ring)
+               goto err_destroy_tx1;
+       dma->tx_ring2 = ring;
+
+       ring = bcm43xx_setup_dmaring(dev, 3, 1, dma64);
+       if (!ring)
+               goto err_destroy_tx2;
+       dma->tx_ring3 = ring;
+
+       ring = bcm43xx_setup_dmaring(dev, 4, 1, dma64);
+       if (!ring)
+               goto err_destroy_tx3;
+       dma->tx_ring4 = ring;
+
+       ring = bcm43xx_setup_dmaring(dev, 5, 1, dma64);
+       if (!ring)
+               goto err_destroy_tx4;
+       dma->tx_ring5 = ring;
+
+       /* setup RX DMA channels. */
+       ring = bcm43xx_setup_dmaring(dev, 0, 0, dma64);
+       if (!ring)
+               goto err_destroy_tx5;
+       dma->rx_ring0 = ring;
+
+       if (dev->dev->id.revision < 5) {
+               ring = bcm43xx_setup_dmaring(dev, 3, 0, dma64);
+               if (!ring)
+                       goto err_destroy_rx0;
+               dma->rx_ring3 = ring;
+       }
+
+       dprintk(KERN_INFO PFX "%d-bit DMA initialized\n",
+               (dmamask == DMA_64BIT_MASK) ? 64 :
+               (dmamask == DMA_32BIT_MASK) ? 32 : 30);
+       err = 0;
+out:
+       return err;
+
+err_destroy_rx0:
+       bcm43xx_destroy_dmaring(dma->rx_ring0);
+       dma->rx_ring0 = NULL;
+err_destroy_tx5:
+       bcm43xx_destroy_dmaring(dma->tx_ring5);
+       dma->tx_ring5 = NULL;
+err_destroy_tx4:
+       bcm43xx_destroy_dmaring(dma->tx_ring4);
+       dma->tx_ring4 = NULL;
+err_destroy_tx3:
+       bcm43xx_destroy_dmaring(dma->tx_ring3);
+       dma->tx_ring3 = NULL;
+err_destroy_tx2:
+       bcm43xx_destroy_dmaring(dma->tx_ring2);
+       dma->tx_ring2 = NULL;
+err_destroy_tx1:
+       bcm43xx_destroy_dmaring(dma->tx_ring1);
+       dma->tx_ring1 = NULL;
+err_destroy_tx0:
+       bcm43xx_destroy_dmaring(dma->tx_ring0);
+       dma->tx_ring0 = NULL;
+       goto out;
+}
+
+/* Generate a cookie for the TX header. */
+static u16 generate_cookie(struct bcm43xx_dmaring *ring,
+                          int slot)
+{
+       u16 cookie = 0x1000;
+
+       /* Use the upper 4 bits of the cookie as
+        * DMA controller ID and store the slot number
+        * in the lower 12 bits.
+        * Note that the cookie must never be 0, as this
+        * is a special value used in RX path.
+        */
+       switch (ring->index) {
+       case 0:
+               cookie = 0xA000;
+               break;
+       case 1:
+               cookie = 0xB000;
+               break;
+       case 2:
+               cookie = 0xC000;
+               break;
+       case 3:
+               cookie = 0xD000;
+               break;
+       case 4:
+               cookie = 0xE000;
+               break;
+       case 5:
+               cookie = 0xF000;
+               break;
+       }
+       assert(((u16)slot & 0xF000) == 0x0000);
+       cookie |= (u16)slot;
+
+       return cookie;
+}
+
+/* Inspect a cookie and find out to which controller/slot it belongs. */
+static
+struct bcm43xx_dmaring * parse_cookie(struct bcm43xx_wldev *dev,
+                                     u16 cookie, int *slot)
+{
+       struct bcm43xx_dma *dma = &dev->dma;
+       struct bcm43xx_dmaring *ring = NULL;
+
+       switch (cookie & 0xF000) {
+       case 0xA000:
+               ring = dma->tx_ring0;
+               break;
+       case 0xB000:
+               ring = dma->tx_ring1;
+               break;
+       case 0xC000:
+               ring = dma->tx_ring2;
+               break;
+       case 0xD000:
+               ring = dma->tx_ring3;
+               break;
+       case 0xE000:
+               ring = dma->tx_ring4;
+               break;
+       case 0xF000:
+               ring = dma->tx_ring5;
+               break;
+       default:
+               assert(0);
+       }
+       *slot = (cookie & 0x0FFF);
+       assert(ring && *slot >= 0 && *slot < ring->nr_slots);
+
+       return ring;
+}
+
+static int dma_tx_fragment(struct bcm43xx_dmaring *ring,
+                           struct sk_buff *skb,
+                           struct ieee80211_tx_control *ctl)
+{
+       const struct bcm43xx_dma_ops *ops = ring->ops;
+       u8 *header;
+       int slot;
+       int err;
+       struct bcm43xx_dmadesc_generic *desc;
+       struct bcm43xx_dmadesc_meta *meta;
+       struct bcm43xx_dmadesc_meta *meta_hdr;
+       struct sk_buff *bounce_skb;
+
+#define SLOTS_PER_PACKET  2
+       assert(skb_shinfo(skb)->nr_frags == 0);
+
+       /* Get a slot for the header. */
+       slot = request_slot(ring);
+       desc = ops->idx2desc(ring, slot, &meta_hdr);
+       memset(meta_hdr, 0, sizeof(*meta_hdr));
+
+       header = &(ring->txhdr_cache[slot * sizeof(struct bcm43xx_txhdr_fw4)]);
+       bcm43xx_generate_txhdr(ring->dev, header,
+                              skb->data, skb->len, ctl,
+                              generate_cookie(ring, slot));
+
+       meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
+                                      sizeof(struct bcm43xx_txhdr_fw4), 1);
+       if (dma_mapping_error(meta_hdr->dmaaddr))
+               return -EIO;
+       ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr,
+                            sizeof(struct bcm43xx_txhdr_fw4), 1, 0, 0);
+
+       /* Get a slot for the payload. */
+       slot = request_slot(ring);
+       desc = ops->idx2desc(ring, slot, &meta);
+       memset(meta, 0, sizeof(*meta));
+
+       memcpy(&meta->txstat.control, ctl, sizeof(*ctl));
+       meta->skb = skb;
+       meta->is_last_fragment = 1;
+
+       meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
+       /* create a bounce buffer in zone_dma on mapping failure. */
+       if (dma_mapping_error(meta->dmaaddr)) {
+               bounce_skb = __dev_alloc_skb(skb->len, GFP_ATOMIC | GFP_DMA);
+               if (!bounce_skb) {
+                       err = -ENOMEM;
+                       goto out_unmap_hdr;
+               }
+
+               memcpy(skb_put(bounce_skb, skb->len), skb->data, skb->len);
+               dev_kfree_skb_any(skb);
+               skb = bounce_skb;
+               meta->skb = skb;
+               meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
+               if (dma_mapping_error(meta->dmaaddr)) {
+                       err = -EIO;
+                       goto out_free_bounce;
+               }
+       }
+
+       ops->fill_descriptor(ring, desc, meta->dmaaddr,
+                            skb->len, 0, 1, 1);
+
+       /* Now transfer the whole frame. */
+       wmb();
+       ops->poke_tx(ring, next_slot(ring, slot));
+       return 0;
+
+out_free_bounce:
+       dev_kfree_skb_any(skb);
+out_unmap_hdr:
+       unmap_descbuffer(ring, meta_hdr->dmaaddr,
+                       sizeof(struct bcm43xx_txhdr_fw4), 1);
+       return err;
+}
+
+int bcm43xx_dma_tx(struct bcm43xx_wldev *dev,
+                  struct sk_buff *skb,
+                  struct ieee80211_tx_control *ctl)
+{
+       struct bcm43xx_dmaring *ring = dev->dma.tx_ring1;
+       int err = 0;
+
+       assert(ring->tx);
+       if (unlikely(free_slots(ring) < SLOTS_PER_PACKET)) {
+               /* This should never trigger, as we call
+                * ieee80211_stop_queue() when it's full.
+                */
+               printkl(KERN_ERR PFX "DMA queue overflow\n");
+               return NETDEV_TX_BUSY;
+       }
+
+       err = dma_tx_fragment(ring, skb, ctl);
+       if (unlikely(err)) {
+               printkl(KERN_ERR PFX "DMA tx mapping failure\n");
+               return NETDEV_TX_BUSY;
+       }
+
+       ring->nr_tx_packets++;
+       if (free_slots(ring) < SLOTS_PER_PACKET) {
+               /* FIXME: we currently only have one queue */
+               ieee80211_stop_queue(dev->wl->hw, 0);
+               ring->stopped = 1;
+       }
+
+       return 0;
+}
+
+void bcm43xx_dma_handle_txstatus(struct bcm43xx_wldev *dev,
+                                const struct bcm43xx_txstatus *status)
+{
+       const struct bcm43xx_dma_ops *ops;
+       struct bcm43xx_dmaring *ring;
+       struct bcm43xx_dmadesc_generic *desc;
+       struct bcm43xx_dmadesc_meta *meta;
+       int slot;
+
+       ring = parse_cookie(dev, status->cookie, &slot);
+       if (unlikely(!ring))
+               return;
+       assert(ring->tx);
+       ops = ring->ops;
+       while (1) {
+               assert(slot >= 0 && slot < ring->nr_slots);
+               desc = ops->idx2desc(ring, slot, &meta);
+
+               if (meta->skb)
+                       unmap_descbuffer(ring, meta->dmaaddr, meta->skb->len, 1);
+               else
+                       unmap_descbuffer(ring, meta->dmaaddr, sizeof(struct bcm43xx_txhdr_fw4), 1);
+
+               if (meta->is_last_fragment) {
+                       assert(meta->skb);
+                       /* Call back to inform the ieee80211 subsystem about the
+                        * status of the transmission.
+                        * Some fields of txstat are already filled in dma_tx().
+                        */
+                       if (status->acked)
+                               meta->txstat.flags |= IEEE80211_TX_STATUS_ACK;
+                       meta->txstat.retry_count = status->frame_count - 1;
+                       ieee80211_tx_status_irqsafe(dev->wl->hw, meta->skb, &(meta->txstat));
+                       /* skb is freed by ieee80211_tx_status_irqsafe() */
+                       meta->skb = NULL;
+               } else {
+                       /* No need to call free_descriptor_buffer here, as
+                        * this is only the txhdr, which is not allocated.
+                        */
+                       assert(meta->skb == NULL);
+               }
+               /* Everything belonging to the slot is unmapped
+                * and freed, so we can return it.
+                */
+               return_slot(ring, slot);
+
+               if (meta->is_last_fragment)
+                       break;
+               slot = next_slot(ring, slot);
+       }
+       dev->stats.last_tx = jiffies;
+       if (ring->stopped) {
+               assert(free_slots(ring) >= SLOTS_PER_PACKET);
+               /* FIXME: we currently only have one queue */
+               ieee80211_wake_queue(dev->wl->hw, 0);
+               ring->stopped = 0;
+       }
+}
+
+void bcm43xx_dma_get_tx_stats(struct bcm43xx_wldev *dev,
+                             struct ieee80211_tx_queue_stats *stats)
+{
+       struct bcm43xx_dma *dma = &dev->dma;
+       struct bcm43xx_dmaring *ring;
+       struct ieee80211_tx_queue_stats_data *data;
+
+       ring = dma->tx_ring1;
+       data = &(stats->data[0]);
+       data->len = ring->used_slots / SLOTS_PER_PACKET;
+       data->limit = ring->nr_slots / SLOTS_PER_PACKET;
+       data->count = ring->nr_tx_packets;
+}
+
+static void dma_rx(struct bcm43xx_dmaring *ring,
+                  int *slot)
+{
+       const struct bcm43xx_dma_ops *ops = ring->ops;
+       struct bcm43xx_dmadesc_generic *desc;
+       struct bcm43xx_dmadesc_meta *meta;
+       struct bcm43xx_rxhdr_fw4 *rxhdr;
+       struct sk_buff *skb;
+       u16 len;
+       int err;
+       dma_addr_t dmaaddr;
+
+       desc = ops->idx2desc(ring, *slot, &meta);
+
+       sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize);
+       skb = meta->skb;
+
+       if (ring->index == 3) {
+               /* We received an xmit status. */
+               struct bcm43xx_hwtxstatus *hw = (struct bcm43xx_hwtxstatus *)skb->data;
+               int i = 0;
+
+               while (hw->cookie == 0) {
+                       if (i > 100)
+                               break;
+                       i++;
+                       udelay(2);
+                       barrier();
+               }
+               bcm43xx_handle_hwtxstatus(ring->dev, hw);
+               /* recycle the descriptor buffer. */
+               sync_descbuffer_for_device(ring, meta->dmaaddr, ring->rx_buffersize);
+
+               return;
+       }
+       rxhdr = (struct bcm43xx_rxhdr_fw4 *)skb->data;
+       len = le16_to_cpu(rxhdr->frame_len);
+       if (len == 0) {
+               int i = 0;
+
+               do {
+                       udelay(2);
+                       barrier();
+                       len = le16_to_cpu(rxhdr->frame_len);
+               } while (len == 0 && i++ < 5);
+               if (unlikely(len == 0)) {
+                       /* recycle the descriptor buffer. */
+                       sync_descbuffer_for_device(ring, meta->dmaaddr,
+                                                  ring->rx_buffersize);
+                       goto drop;
+               }
+       }
+       if (unlikely(len > ring->rx_buffersize)) {
+               /* The data did not fit into one descriptor buffer
+                * and is split over multiple buffers.
+                * This should never happen, as we try to allocate buffers
+                * big enough. So simply ignore this packet.
+                */
+               int cnt = 0;
+               s32 tmp = len;
+
+               while (1) {
+                       desc = ops->idx2desc(ring, *slot, &meta);
+                       /* recycle the descriptor buffer. */
+                       sync_descbuffer_for_device(ring, meta->dmaaddr,
+                                                  ring->rx_buffersize);
+                       *slot = next_slot(ring, *slot);
+                       cnt++;
+                       tmp -= ring->rx_buffersize;
+                       if (tmp <= 0)
+                               break;
+               }
+               printkl(KERN_ERR PFX "DMA RX buffer too small "
+                       "(len: %u, buffer: %u, nr-dropped: %d)\n",
+                       len, ring->rx_buffersize, cnt);
+               goto drop;
+       }
+
+       dmaaddr = meta->dmaaddr;
+       err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
+       if (unlikely(err)) {
+               dprintkl(KERN_ERR PFX "DMA RX: setup_rx_descbuffer() failed\n");
+               sync_descbuffer_for_device(ring, dmaaddr,
+                                          ring->rx_buffersize);
+               goto drop;
+       }
+
+       unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
+       skb_put(skb, len + ring->frameoffset);
+       skb_pull(skb, ring->frameoffset);
+
+       bcm43xx_rx(ring->dev, skb, rxhdr);
+drop:
+       return;
+}
+
+void bcm43xx_dma_rx(struct bcm43xx_dmaring *ring)
+{
+       const struct bcm43xx_dma_ops *ops = ring->ops;
+       int slot, current_slot;
+#ifdef CONFIG_BCM43XX_MAC80211_DEBUG
+       int used_slots = 0;
+#endif
+
+       assert(!ring->tx);
+       current_slot = ops->get_current_rxslot(ring);
+       assert(current_slot >= 0 && current_slot < ring->nr_slots);
+
+       slot = ring->current_slot;
+       for ( ; slot != current_slot; slot = next_slot(ring, slot)) {
+               dma_rx(ring, &slot);
+#ifdef CONFIG_BCM43XX_MAC80211_DEBUG
+               if (++used_slots > ring->max_used_slots)
+                       ring->max_used_slots = used_slots;
+#endif
+       }
+       ops->set_current_rxslot(ring, slot);
+       ring->current_slot = slot;
+}
+
+void bcm43xx_dma_tx_suspend(struct bcm43xx_dmaring *ring)
+{
+       assert(ring->tx);
+       bcm43xx_power_saving_ctl_bits(ring->dev, -1, 1);
+       ring->ops->tx_suspend(ring);
+}
+
+void bcm43xx_dma_tx_resume(struct bcm43xx_dmaring *ring)
+{
+       assert(ring->tx);
+       ring->ops->tx_resume(ring);
+       bcm43xx_power_saving_ctl_bits(ring->dev, -1, -1);
+}
diff --git a/package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_dma.h b/package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_dma.h
new file mode 100644 (file)
index 0000000..94fac2a
--- /dev/null
@@ -0,0 +1,361 @@
+#ifndef BCM43xx_DMA_H_
+#define BCM43xx_DMA_H_
+
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <linux/workqueue.h>
+#include <linux/linkage.h>
+#include <asm/atomic.h>
+
+#include "bcm43xx.h"
+
+
+/* DMA-Interrupt reasons. */
+#define BCM43xx_DMAIRQ_FATALMASK       ((1 << 10) | (1 << 11) | (1 << 12) \
+                                        | (1 << 14) | (1 << 15))
+#define BCM43xx_DMAIRQ_NONFATALMASK    (1 << 13)
+#define BCM43xx_DMAIRQ_RX_DONE         (1 << 16)
+
+
+/*** 32-bit DMA Engine. ***/
+
+/* 32-bit DMA controller registers. */
+#define BCM43xx_DMA32_TXCTL                            0x00
+#define                BCM43xx_DMA32_TXENABLE                  0x00000001
+#define                BCM43xx_DMA32_TXSUSPEND                 0x00000002
+#define                BCM43xx_DMA32_TXLOOPBACK                0x00000004
+#define                BCM43xx_DMA32_TXFLUSH                   0x00000010
+#define                BCM43xx_DMA32_TXADDREXT_MASK            0x00030000
+#define                BCM43xx_DMA32_TXADDREXT_SHIFT           16
+#define BCM43xx_DMA32_TXRING                           0x04
+#define BCM43xx_DMA32_TXINDEX                          0x08
+#define BCM43xx_DMA32_TXSTATUS                         0x0C
+#define                BCM43xx_DMA32_TXDPTR                    0x00000FFF
+#define                BCM43xx_DMA32_TXSTATE                   0x0000F000
+#define                        BCM43xx_DMA32_TXSTAT_DISABLED   0x00000000
+#define                        BCM43xx_DMA32_TXSTAT_ACTIVE     0x00001000
+#define                        BCM43xx_DMA32_TXSTAT_IDLEWAIT   0x00002000
+#define                        BCM43xx_DMA32_TXSTAT_STOPPED    0x00003000
+#define                        BCM43xx_DMA32_TXSTAT_SUSP       0x00004000
+#define                BCM43xx_DMA32_TXERROR                   0x000F0000
+#define                        BCM43xx_DMA32_TXERR_NOERR       0x00000000
+#define                        BCM43xx_DMA32_TXERR_PROT        0x00010000
+#define                        BCM43xx_DMA32_TXERR_UNDERRUN    0x00020000
+#define                        BCM43xx_DMA32_TXERR_BUFREAD     0x00030000
+#define                        BCM43xx_DMA32_TXERR_DESCREAD    0x00040000
+#define                BCM43xx_DMA32_TXACTIVE                  0xFFF00000
+#define BCM43xx_DMA32_RXCTL                            0x10
+#define                BCM43xx_DMA32_RXENABLE                  0x00000001
+#define                BCM43xx_DMA32_RXFROFF_MASK              0x000000FE
+#define                BCM43xx_DMA32_RXFROFF_SHIFT             1
+#define                BCM43xx_DMA32_RXDIRECTFIFO              0x00000100
+#define                BCM43xx_DMA32_RXADDREXT_MASK            0x00030000
+#define                BCM43xx_DMA32_RXADDREXT_SHIFT           16
+#define BCM43xx_DMA32_RXRING                           0x14
+#define BCM43xx_DMA32_RXINDEX                          0x18
+#define BCM43xx_DMA32_RXSTATUS                         0x1C
+#define                BCM43xx_DMA32_RXDPTR                    0x00000FFF
+#define                BCM43xx_DMA32_RXSTATE                   0x0000F000
+#define                        BCM43xx_DMA32_RXSTAT_DISABLED   0x00000000
+#define                        BCM43xx_DMA32_RXSTAT_ACTIVE     0x00001000
+#define                        BCM43xx_DMA32_RXSTAT_IDLEWAIT   0x00002000
+#define                        BCM43xx_DMA32_RXSTAT_STOPPED    0x00003000
+#define                BCM43xx_DMA32_RXERROR                   0x000F0000
+#define                        BCM43xx_DMA32_RXERR_NOERR       0x00000000
+#define                        BCM43xx_DMA32_RXERR_PROT        0x00010000
+#define                        BCM43xx_DMA32_RXERR_OVERFLOW    0x00020000
+#define                        BCM43xx_DMA32_RXERR_BUFWRITE    0x00030000
+#define                        BCM43xx_DMA32_RXERR_DESCREAD    0x00040000
+#define                BCM43xx_DMA32_RXACTIVE                  0xFFF00000
+
+/* 32-bit DMA descriptor. */
+struct bcm43xx_dmadesc32 {
+       __le32 control;
+       __le32 address;
+} __attribute__((__packed__));
+#define BCM43xx_DMA32_DCTL_BYTECNT             0x00001FFF
+#define BCM43xx_DMA32_DCTL_ADDREXT_MASK                0x00030000
+#define BCM43xx_DMA32_DCTL_ADDREXT_SHIFT       16
+#define BCM43xx_DMA32_DCTL_DTABLEEND           0x10000000
+#define BCM43xx_DMA32_DCTL_IRQ                 0x20000000
+#define BCM43xx_DMA32_DCTL_FRAMEEND            0x40000000
+#define BCM43xx_DMA32_DCTL_FRAMESTART          0x80000000
+
+
+
+/*** 64-bit DMA Engine. ***/
+
+/* 64-bit DMA controller registers. */
+#define BCM43xx_DMA64_TXCTL                            0x00
+#define                BCM43xx_DMA64_TXENABLE                  0x00000001
+#define                BCM43xx_DMA64_TXSUSPEND                 0x00000002
+#define                BCM43xx_DMA64_TXLOOPBACK                0x00000004
+#define                BCM43xx_DMA64_TXFLUSH                   0x00000010
+#define                BCM43xx_DMA64_TXADDREXT_MASK            0x00030000
+#define                BCM43xx_DMA64_TXADDREXT_SHIFT           16
+#define BCM43xx_DMA64_TXINDEX                          0x04
+#define BCM43xx_DMA64_TXRINGLO                         0x08
+#define BCM43xx_DMA64_TXRINGHI                         0x0C
+#define BCM43xx_DMA64_TXSTATUS                         0x10
+#define                BCM43xx_DMA64_TXSTATDPTR                0x00001FFF
+#define                BCM43xx_DMA64_TXSTAT                    0xF0000000
+#define                        BCM43xx_DMA64_TXSTAT_DISABLED   0x00000000
+#define                        BCM43xx_DMA64_TXSTAT_ACTIVE     0x10000000
+#define                        BCM43xx_DMA64_TXSTAT_IDLEWAIT   0x20000000
+#define                        BCM43xx_DMA64_TXSTAT_STOPPED    0x30000000
+#define                        BCM43xx_DMA64_TXSTAT_SUSP       0x40000000
+#define BCM43xx_DMA64_TXERROR                          0x14
+#define                BCM43xx_DMA64_TXERRDPTR                 0x0001FFFF
+#define                BCM43xx_DMA64_TXERR                     0xF0000000
+#define                        BCM43xx_DMA64_TXERR_NOERR       0x00000000
+#define                        BCM43xx_DMA64_TXERR_PROT        0x10000000
+#define                        BCM43xx_DMA64_TXERR_UNDERRUN    0x20000000
+#define                        BCM43xx_DMA64_TXERR_TRANSFER    0x30000000
+#define                        BCM43xx_DMA64_TXERR_DESCREAD    0x40000000
+#define                        BCM43xx_DMA64_TXERR_CORE        0x50000000
+#define BCM43xx_DMA64_RXCTL                            0x20
+#define                BCM43xx_DMA64_RXENABLE                  0x00000001
+#define                BCM43xx_DMA64_RXFROFF_MASK              0x000000FE
+#define                BCM43xx_DMA64_RXFROFF_SHIFT             1
+#define                BCM43xx_DMA64_RXDIRECTFIFO              0x00000100
+#define                BCM43xx_DMA64_RXADDREXT_MASK            0x00030000
+#define                BCM43xx_DMA64_RXADDREXT_SHIFT           16
+#define BCM43xx_DMA64_RXINDEX                          0x24
+#define BCM43xx_DMA64_RXRINGLO                         0x28
+#define BCM43xx_DMA64_RXRINGHI                         0x2C
+#define BCM43xx_DMA64_RXSTATUS                         0x30
+#define                BCM43xx_DMA64_RXSTATDPTR                0x00001FFF
+#define                BCM43xx_DMA64_RXSTAT                    0xF0000000
+#define                        BCM43xx_DMA64_RXSTAT_DISABLED   0x00000000
+#define                        BCM43xx_DMA64_RXSTAT_ACTIVE     0x10000000
+#define                        BCM43xx_DMA64_RXSTAT_IDLEWAIT   0x20000000
+#define                        BCM43xx_DMA64_RXSTAT_STOPPED    0x30000000
+#define                        BCM43xx_DMA64_RXSTAT_SUSP       0x40000000
+#define BCM43xx_DMA64_RXERROR                          0x34
+#define                BCM43xx_DMA64_RXERRDPTR                 0x0001FFFF
+#define                BCM43xx_DMA64_RXERR                     0xF0000000
+#define                        BCM43xx_DMA64_RXERR_NOERR       0x00000000
+#define                        BCM43xx_DMA64_RXERR_PROT        0x10000000
+#define                        BCM43xx_DMA64_RXERR_UNDERRUN    0x20000000
+#define                        BCM43xx_DMA64_RXERR_TRANSFER    0x30000000
+#define                        BCM43xx_DMA64_RXERR_DESCREAD    0x40000000
+#define                        BCM43xx_DMA64_RXERR_CORE        0x50000000
+
+/* 64-bit DMA descriptor. */
+struct bcm43xx_dmadesc64 {
+       __le32 control0;
+       __le32 control1;
+       __le32 address_low;
+       __le32 address_high;
+} __attribute__((__packed__));
+#define BCM43xx_DMA64_DCTL0_DTABLEEND          0x10000000
+#define BCM43xx_DMA64_DCTL0_IRQ                        0x20000000
+#define BCM43xx_DMA64_DCTL0_FRAMEEND           0x40000000
+#define BCM43xx_DMA64_DCTL0_FRAMESTART         0x80000000
+#define BCM43xx_DMA64_DCTL1_BYTECNT            0x00001FFF
+#define BCM43xx_DMA64_DCTL1_ADDREXT_MASK       0x00030000
+#define BCM43xx_DMA64_DCTL1_ADDREXT_SHIFT      16
+
+
+
+struct bcm43xx_dmadesc_generic {
+       union {
+               struct bcm43xx_dmadesc32 dma32;
+               struct bcm43xx_dmadesc64 dma64;
+       } __attribute__((__packed__));
+} __attribute__((__packed__));
+
+
+/* Misc DMA constants */
+#define BCM43xx_DMA_RINGMEMSIZE                PAGE_SIZE
+#define BCM43xx_DMA0_RX_FRAMEOFFSET    30
+#define BCM43xx_DMA3_RX_FRAMEOFFSET    0
+
+
+/* DMA engine tuning knobs */
+#define BCM43xx_TXRING_SLOTS           128
+#define BCM43xx_RXRING_SLOTS           64
+#define BCM43xx_DMA0_RX_BUFFERSIZE     (2304 + 100)
+#define BCM43xx_DMA3_RX_BUFFERSIZE     16
+
+
+
+#ifdef CONFIG_BCM43XX_MAC80211_DMA
+
+
+struct sk_buff;
+struct bcm43xx_private;
+struct bcm43xx_txstatus;
+
+
+struct bcm43xx_dmadesc_meta {
+       /* The kernel DMA-able buffer. */
+       struct sk_buff *skb;
+       /* DMA base bus-address of the descriptor buffer. */
+       dma_addr_t dmaaddr;
+       /* ieee80211 TX status. Only used once per 802.11 frag. */
+       u8 is_last_fragment;
+       struct ieee80211_tx_status txstat;
+};
+
+struct bcm43xx_dmaring;
+
+/* Lowlevel DMA operations that differ between 32bit and 64bit DMA. */
+struct bcm43xx_dma_ops {
+       struct bcm43xx_dmadesc_generic * (*idx2desc)(struct bcm43xx_dmaring *ring,
+                                                    int slot,
+                                                    struct bcm43xx_dmadesc_meta **meta);
+       void (*fill_descriptor)(struct bcm43xx_dmaring *ring,
+                               struct bcm43xx_dmadesc_generic *desc,
+                               dma_addr_t dmaaddr, u16 bufsize,
+                               int start, int end, int irq);
+       void (*poke_tx)(struct bcm43xx_dmaring *ring, int slot);
+       void (*tx_suspend)(struct bcm43xx_dmaring *ring);
+       void (*tx_resume)(struct bcm43xx_dmaring *ring);
+       int (*get_current_rxslot)(struct bcm43xx_dmaring *ring);
+       void (*set_current_rxslot)(struct bcm43xx_dmaring *ring, int slot);
+};
+
+struct bcm43xx_dmaring {
+       /* Lowlevel DMA ops. */
+       const struct bcm43xx_dma_ops *ops;
+       /* Kernel virtual base address of the ring memory. */
+       void *descbase;
+       /* Meta data about all descriptors. */
+       struct bcm43xx_dmadesc_meta *meta;
+       /* Cache of TX headers for each slot.
+        * This is to avoid an allocation on each TX.
+        * This is NULL for an RX ring.
+        */
+       u8 *txhdr_cache;
+       /* (Unadjusted) DMA base bus-address of the ring memory. */
+       dma_addr_t dmabase;
+       /* Number of descriptor slots in the ring. */
+       int nr_slots;
+       /* Number of used descriptor slots. */
+       int used_slots;
+       /* Currently used slot in the ring. */
+       int current_slot;
+       /* Total number of packets sent. Statistics only. */
+       unsigned int nr_tx_packets;
+       /* Frameoffset in octets. */
+       u32 frameoffset;
+       /* Descriptor buffer size. */
+       u16 rx_buffersize;
+       /* The MMIO base register of the DMA controller. */
+       u16 mmio_base;
+       /* DMA controller index number (0-5). */
+       int index;
+       /* Boolean. Is this a TX ring? */
+       u8 tx;
+       /* Boolean. 64bit DMA if true, 32bit DMA otherwise. */
+       u8 dma64;
+       /* Boolean. Is this ring stopped at ieee80211 level? */
+       u8 stopped;
+       struct bcm43xx_wldev *dev;
+#ifdef CONFIG_BCM43XX_MAC80211_DEBUG
+       /* Maximum number of used slots. */
+       int max_used_slots;
+#endif /* CONFIG_BCM43XX_MAC80211_DEBUG*/
+};
+
+
+static inline
+u32 bcm43xx_dma_read(struct bcm43xx_dmaring *ring,
+                    u16 offset)
+{
+       return bcm43xx_read32(ring->dev, ring->mmio_base + offset);
+}
+
+static inline
+void bcm43xx_dma_write(struct bcm43xx_dmaring *ring,
+                      u16 offset, u32 value)
+{
+       bcm43xx_write32(ring->dev, ring->mmio_base + offset, value);
+}
+
+
+int bcm43xx_dma_init(struct bcm43xx_wldev *dev);
+void bcm43xx_dma_free(struct bcm43xx_wldev *dev);
+
+int bcm43xx_dmacontroller_rx_reset(struct bcm43xx_wldev *dev,
+                                  u16 dmacontroller_mmio_base,
+                                  int dma64);
+int bcm43xx_dmacontroller_tx_reset(struct bcm43xx_wldev *dev,
+                                  u16 dmacontroller_mmio_base,
+                                  int dma64);
+
+u16 bcm43xx_dmacontroller_base(int dma64bit, int dmacontroller_idx);
+
+void bcm43xx_dma_tx_suspend(struct bcm43xx_dmaring *ring);
+void bcm43xx_dma_tx_resume(struct bcm43xx_dmaring *ring);
+
+void bcm43xx_dma_get_tx_stats(struct bcm43xx_wldev *dev,
+                             struct ieee80211_tx_queue_stats *stats);
+
+int bcm43xx_dma_tx(struct bcm43xx_wldev *dev,
+                  struct sk_buff *skb,
+                  struct ieee80211_tx_control *ctl);
+void bcm43xx_dma_handle_txstatus(struct bcm43xx_wldev *dev,
+                                const struct bcm43xx_txstatus *status);
+
+void bcm43xx_dma_rx(struct bcm43xx_dmaring *ring);
+
+#else /* CONFIG_BCM43XX_MAC80211_DMA */
+
+
+static inline
+int bcm43xx_dma_init(struct bcm43xx_wldev *dev)
+{
+       return 0;
+}
+static inline
+void bcm43xx_dma_free(struct bcm43xx_wldev *dev)
+{
+}
+static inline
+int bcm43xx_dmacontroller_rx_reset(struct bcm43xx_wldev *dev,
+                                  u16 dmacontroller_mmio_base,
+                                  int dma64)
+{
+       return 0;
+}
+static inline
+int bcm43xx_dmacontroller_tx_reset(struct bcm43xx_wldev *dev,
+                                  u16 dmacontroller_mmio_base,
+                                  int dma64)
+{
+       return 0;
+}
+static inline
+void bcm43xx_dma_get_tx_stats(struct bcm43xx_wldev *dev,
+                             struct ieee80211_tx_queue_stats *stats)
+{
+}
+static inline
+int bcm43xx_dma_tx(struct bcm43xx_wldev *dev,
+                  struct sk_buff *skb,
+                  struct ieee80211_tx_control *ctl)
+{
+       return 0;
+}
+static inline
+void bcm43xx_dma_handle_txstatus(struct bcm43xx_wldev *dev,
+                                const struct bcm43xx_txstatus *status)
+{
+}
+static inline
+void bcm43xx_dma_rx(struct bcm43xx_dmaring *ring)
+{
+}
+static inline
+void bcm43xx_dma_tx_suspend(struct bcm43xx_dmaring *ring)
+{
+}
+static inline
+void bcm43xx_dma_tx_resume(struct bcm43xx_dmaring *ring)
+{
+}
+
+#endif /* CONFIG_BCM43XX_MAC80211_DMA */
+#endif /* BCM43xx_DMA_H_ */
diff --git a/package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_leds.c b/package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_leds.c
new file mode 100644 (file)
index 0000000..dfa0121
--- /dev/null
@@ -0,0 +1,300 @@
+/*
+
+  Broadcom BCM43xx wireless driver
+
+  Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
+                     Stefano Brivio <st3@riseup.net>
+                     Michael Buesch <mb@bu3sch.de>
+                     Danny van Dyk <kugelfang@gentoo.org>
+                     Andreas Jaggi <andreas.jaggi@waterwave.ch>
+
+  This program is free software; you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation; either version 2 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program; see the file COPYING.  If not, write to
+  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
+  Boston, MA 02110-1301, USA.
+
+*/
+
+#include "bcm43xx_leds.h"
+#include "bcm43xx.h"
+#include "bcm43xx_main.h"
+
+static void bcm43xx_led_changestate(struct bcm43xx_led *led)
+{
+       struct bcm43xx_wldev *dev = led->dev;
+       const int index = bcm43xx_led_index(led);
+       const u16 mask = (1 << index);
+       u16 ledctl;
+
+       assert(index >= 0 && index < BCM43xx_NR_LEDS);
+       assert(led->blink_interval);
+       ledctl = bcm43xx_read16(dev, BCM43xx_MMIO_GPIO_CONTROL);
+       ledctl = (ledctl & mask) ? (ledctl & ~mask) : (ledctl | mask);
+       bcm43xx_write16(dev, BCM43xx_MMIO_GPIO_CONTROL, ledctl);
+}
+
+static void bcm43xx_led_blink(unsigned long d)
+{
+       struct bcm43xx_led *led = (struct bcm43xx_led *)d;
+       struct bcm43xx_wldev *dev = led->dev;
+       unsigned long flags;
+
+       spin_lock_irqsave(&dev->wl->leds_lock, flags);
+       if (led->blink_interval) {
+               bcm43xx_led_changestate(led);
+               mod_timer(&led->blink_timer, jiffies + led->blink_interval);
+       }
+       spin_unlock_irqrestore(&dev->wl->leds_lock, flags);
+}
+
+static void bcm43xx_led_blink_start(struct bcm43xx_led *led,
+                                   unsigned long interval)
+{
+       if (led->blink_interval)
+               return;
+       led->blink_interval = interval;
+       bcm43xx_led_changestate(led);
+       led->blink_timer.expires = jiffies + interval;
+       add_timer(&led->blink_timer);
+}
+
+static void bcm43xx_led_blink_stop(struct bcm43xx_led *led, int sync)
+{
+       struct bcm43xx_wldev *dev = led->dev;
+       const int index = bcm43xx_led_index(led);
+       u16 ledctl;
+
+       if (!led->blink_interval)
+               return;
+       if (unlikely(sync))
+               del_timer_sync(&led->blink_timer);
+       else
+               del_timer(&led->blink_timer);
+       led->blink_interval = 0;
+
+       /* Make sure the LED is turned off. */
+       assert(index >= 0 && index < BCM43xx_NR_LEDS);
+       ledctl = bcm43xx_read16(dev, BCM43xx_MMIO_GPIO_CONTROL);
+       if (led->activelow)
+               ledctl |= (1 << index);
+       else
+               ledctl &= ~(1 << index);
+       bcm43xx_write16(dev, BCM43xx_MMIO_GPIO_CONTROL, ledctl);
+}
+
+static void bcm43xx_led_init_hardcoded(struct bcm43xx_wldev *dev,
+                                      struct bcm43xx_led *led,
+                                      int led_index)
+{
+       struct ssb_bus *bus = dev->dev->bus;
+
+       /* This function is called, if the behaviour (and activelow)
+        * information for a LED is missing in the SPROM.
+        * We hardcode the behaviour values for various devices here.
+        * Note that the BCM43xx_LED_TEST_XXX behaviour values can
+        * be used to figure out which led is mapped to which index.
+        */
+
+       switch (led_index) {
+       case 0:
+               led->behaviour = BCM43xx_LED_ACTIVITY;
+               led->activelow = 1;
+               if (bus->board_vendor == PCI_VENDOR_ID_COMPAQ)
+                       led->behaviour = BCM43xx_LED_RADIO_ALL;
+               break;
+       case 1:
+               led->behaviour = BCM43xx_LED_RADIO_B;
+               if (bus->board_vendor == PCI_VENDOR_ID_ASUSTEK)
+                       led->behaviour = BCM43xx_LED_ASSOC;
+               break;
+       case 2:
+               led->behaviour = BCM43xx_LED_RADIO_A;
+               break;
+       case 3:
+               led->behaviour = BCM43xx_LED_OFF;
+               break;
+       default:
+               assert(0);
+       }
+}
+
+int bcm43xx_leds_init(struct bcm43xx_wldev *dev)
+{
+       struct bcm43xx_led *led;
+       u8 sprom[4];
+       int i;
+
+       sprom[0] = dev->dev->bus->sprom.r1.gpio0;
+       sprom[1] = dev->dev->bus->sprom.r1.gpio1;
+       sprom[2] = dev->dev->bus->sprom.r1.gpio2;
+       sprom[3] = dev->dev->bus->sprom.r1.gpio3;
+
+       for (i = 0; i < BCM43xx_NR_LEDS; i++) {
+               led = &(dev->leds[i]);
+               led->dev = dev;
+               setup_timer(&led->blink_timer,
+                           bcm43xx_led_blink,
+                           (unsigned long)led);
+
+               if (sprom[i] == 0xFF) {
+                       bcm43xx_led_init_hardcoded(dev, led, i);
+               } else {
+                       led->behaviour = sprom[i] & BCM43xx_LED_BEHAVIOUR;
+                       led->activelow = !!(sprom[i] & BCM43xx_LED_ACTIVELOW);
+               }
+       }
+
+       return 0;
+}
+
+void bcm43xx_leds_exit(struct bcm43xx_wldev *dev)
+{
+       struct bcm43xx_led *led;
+       int i;
+
+       for (i = 0; i < BCM43xx_NR_LEDS; i++) {
+               led = &(dev->leds[i]);
+               bcm43xx_led_blink_stop(led, 1);
+       }
+       bcm43xx_leds_switch_all(dev, 0);
+}
+
+void bcm43xx_leds_update(struct bcm43xx_wldev *dev, int activity)
+{
+       struct bcm43xx_led *led;
+       struct bcm43xx_phy *phy = &dev->phy;
+       const int transferring = (jiffies - dev->stats.last_tx) < BCM43xx_LED_XFER_THRES;
+       int i, turn_on;
+       unsigned long interval = 0;
+       u16 ledctl;
+       unsigned long flags;
+
+       spin_lock_irqsave(&dev->wl->leds_lock, flags);
+       ledctl = bcm43xx_read16(dev, BCM43xx_MMIO_GPIO_CONTROL);
+       for (i = 0; i < BCM43xx_NR_LEDS; i++) {
+               led = &(dev->leds[i]);
+
+               turn_on = 0;
+               switch (led->behaviour) {
+               case BCM43xx_LED_INACTIVE:
+                       continue;
+               case BCM43xx_LED_OFF:
+                       break;
+               case BCM43xx_LED_ON:
+                       turn_on = 1;
+                       break;
+               case BCM43xx_LED_ACTIVITY:
+                       turn_on = activity;
+                       break;
+               case BCM43xx_LED_RADIO_ALL:
+                       turn_on = phy->radio_on && bcm43xx_is_hw_radio_enabled(dev);
+                       break;
+               case BCM43xx_LED_RADIO_A:
+                       turn_on = (phy->radio_on && bcm43xx_is_hw_radio_enabled(dev)
+                                  && phy->type == BCM43xx_PHYTYPE_A);
+                       break;
+               case BCM43xx_LED_RADIO_B:
+                       turn_on = (phy->radio_on && bcm43xx_is_hw_radio_enabled(dev) &&
+                                  (phy->type == BCM43xx_PHYTYPE_B ||
+                                   phy->type == BCM43xx_PHYTYPE_G));
+                       break;
+               case BCM43xx_LED_MODE_BG:
+                       if (phy->type == BCM43xx_PHYTYPE_G && bcm43xx_is_hw_radio_enabled(dev) &&
+                           1/*FIXME: using G rates.*/)
+                               turn_on = 1;
+                       break;
+               case BCM43xx_LED_TRANSFER:
+                       if (transferring)
+                               bcm43xx_led_blink_start(led, BCM43xx_LEDBLINK_MEDIUM);
+                       else
+                               bcm43xx_led_blink_stop(led, 0);
+                       continue;
+               case BCM43xx_LED_APTRANSFER:
+                       if (bcm43xx_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
+                               if (transferring) {
+                                       interval = BCM43xx_LEDBLINK_FAST;
+                                       turn_on = 1;
+                               }
+                       } else {
+                               turn_on = 1;
+                               if (0/*TODO: not assoc*/)
+                                       interval = BCM43xx_LEDBLINK_SLOW;
+                               else if (transferring)
+                                       interval = BCM43xx_LEDBLINK_FAST;
+                               else
+                                       turn_on = 0;
+                       }
+                       if (turn_on)
+                               bcm43xx_led_blink_start(led, interval);
+                       else
+                               bcm43xx_led_blink_stop(led, 0);
+                       continue;
+               case BCM43xx_LED_WEIRD:
+                       //TODO
+                       break;
+               case BCM43xx_LED_ASSOC:
+                       if (1/*dev->softmac->associated*/)
+                               turn_on = 1;
+                       break;
+#ifdef CONFIG_BCM43XX_DEBUG
+               case BCM43xx_LED_TEST_BLINKSLOW:
+                       bcm43xx_led_blink_start(led, BCM43xx_LEDBLINK_SLOW);
+                       continue;
+               case BCM43xx_LED_TEST_BLINKMEDIUM:
+                       bcm43xx_led_blink_start(led, BCM43xx_LEDBLINK_MEDIUM);
+                       continue;
+               case BCM43xx_LED_TEST_BLINKFAST:
+                       bcm43xx_led_blink_start(led, BCM43xx_LEDBLINK_FAST);
+                       continue;
+#endif /* CONFIG_BCM43XX_DEBUG */
+               default:
+                       assert(0);
+               };
+
+               if (led->activelow)
+                       turn_on = !turn_on;
+               if (turn_on)
+                       ledctl |= (1 << i);
+               else
+                       ledctl &= ~(1 << i);
+       }
+       bcm43xx_write16(dev, BCM43xx_MMIO_GPIO_CONTROL, ledctl);
+       spin_unlock_irqrestore(&dev->wl->leds_lock, flags);
+}
+
+void bcm43xx_leds_switch_all(struct bcm43xx_wldev *dev, int on)
+{
+       struct bcm43xx_led *led;
+       u16 ledctl;
+       int i;
+       int bit_on;
+       unsigned long flags;
+
+       spin_lock_irqsave(&dev->wl->leds_lock, flags);
+       ledctl = bcm43xx_read16(dev, BCM43xx_MMIO_GPIO_CONTROL);
+       for (i = 0; i < BCM43xx_NR_LEDS; i++) {
+               led = &(dev->leds[i]);
+               if (led->behaviour == BCM43xx_LED_INACTIVE)
+                       continue;
+               if (on)
+                       bit_on = led->activelow ? 0 : 1;
+               else
+                       bit_on = led->activelow ? 1 : 0;
+               if (bit_on)
+                       ledctl |= (1 << i);
+               else
+                       ledctl &= ~(1 << i);
+       }
+       bcm43xx_write16(dev, BCM43xx_MMIO_GPIO_CONTROL, ledctl);
+       spin_unlock_irqrestore(&dev->wl->leds_lock, flags);
+}
diff --git a/package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_leds.h b/package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_leds.h
new file mode 100644 (file)
index 0000000..ad35047
--- /dev/null
@@ -0,0 +1,56 @@
+#ifndef BCM43xx_LEDS_H_
+#define BCM43xx_LEDS_H_
+
+#include <linux/types.h>
+#include <linux/timer.h>
+
+
+struct bcm43xx_led {
+       u8 behaviour:7;
+       u8 activelow:1;
+
+       struct bcm43xx_wldev *dev;
+       struct timer_list blink_timer;
+       unsigned long blink_interval;
+};
+#define bcm43xx_led_index(led) ((int)((led) - (led)->dev->leds))
+
+/* Delay between state changes when blinking in jiffies */
+#define BCM43xx_LEDBLINK_SLOW          (HZ / 1)
+#define BCM43xx_LEDBLINK_MEDIUM                (HZ / 4)
+#define BCM43xx_LEDBLINK_FAST          (HZ / 8)
+
+#define BCM43xx_LED_XFER_THRES         (HZ / 100)
+
+#define BCM43xx_LED_BEHAVIOUR          0x7F
+#define BCM43xx_LED_ACTIVELOW          0x80
+enum { /* LED behaviour values */
+       BCM43xx_LED_OFF,
+       BCM43xx_LED_ON,
+       BCM43xx_LED_ACTIVITY,
+       BCM43xx_LED_RADIO_ALL,
+       BCM43xx_LED_RADIO_A,
+       BCM43xx_LED_RADIO_B,
+       BCM43xx_LED_MODE_BG,
+       BCM43xx_LED_TRANSFER,
+       BCM43xx_LED_APTRANSFER,
+       BCM43xx_LED_WEIRD,//FIXME
+       BCM43xx_LED_ASSOC,
+       BCM43xx_LED_INACTIVE,
+
+       /* Behaviour values for testing.
+        * With these values it is easier to figure out
+        * the real behaviour of leds, in case the SPROM
+        * is missing information.
+        */
+       BCM43xx_LED_TEST_BLINKSLOW,
+       BCM43xx_LED_TEST_BLINKMEDIUM,
+       BCM43xx_LED_TEST_BLINKFAST,
+};
+
+int bcm43xx_leds_init(struct bcm43xx_wldev *dev);
+void bcm43xx_leds_exit(struct bcm43xx_wldev *dev);
+void bcm43xx_leds_update(struct bcm43xx_wldev *dev, int activity);
+void bcm43xx_leds_switch_all(struct bcm43xx_wldev *dev, int on);
+
+#endif /* BCM43xx_LEDS_H_ */
diff --git a/package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_lo.c b/package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_lo.c
new file mode 100644 (file)
index 0000000..a221034
--- /dev/null
@@ -0,0 +1,1111 @@
+/*
+
+  Broadcom BCM43xx wireless driver
+
+  G PHY LO (LocalOscillator) Measuring and Control routines
+
+  Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
+  Copyright (c) 2005, 2006 Stefano Brivio <st3@riseup.net>
+  Copyright (c) 2005-2007 Michael Buesch <mb@bu3sch.de>
+  Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
+  Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
+
+  This program is free software; you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation; either version 2 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program; see the file COPYING.  If not, write to
+  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
+  Boston, MA 02110-1301, USA.
+
+*/
+
+#include "bcm43xx.h"
+#include "bcm43xx_lo.h"
+#include "bcm43xx_phy.h"
+#include "bcm43xx_main.h"
+
+#include <linux/delay.h>
+
+
+/* Write the LocalOscillator Control (adjust) value-pair. */
+static void bcm43xx_lo_write(struct bcm43xx_wldev *dev,
+                            struct bcm43xx_loctl *control)
+{
+       struct bcm43xx_phy *phy = &dev->phy;
+       u16 value;
+       u16 reg;
+
+       if (BCM43xx_DEBUG) {
+               if (unlikely(abs(control->i) > 16 ||
+                            abs(control->q) > 16)) {
+                       printk(KERN_ERR PFX "ERROR: Invalid LO control pair "
+                                           "(I: %d, Q: %d)\n",
+                              control->i, control->q);
+                       dump_stack();
+                       return;
+               }
+       }
+
+       value = (u8)(control->q);
+       value |= ((u8)(control->i)) << 8;
+
+       reg = (phy->type == BCM43xx_PHYTYPE_B) ? 0x002F : BCM43xx_PHY_LO_CTL;
+       bcm43xx_phy_write(dev, reg, value);
+}
+
+static inline
+void assert_rfatt_and_bbatt(const struct bcm43xx_rfatt *rfatt,
+                           const struct bcm43xx_bbatt *bbatt)
+{
+       if (BCM43xx_DEBUG) {
+               int err = 0;
+
+               if (unlikely(rfatt->att >= 16)) {
+                       dprintk(KERN_ERR PFX "ERROR: invalid rf_att: %u\n",
+                               rfatt->att);
+                       err = 1;
+               }
+               if (unlikely(bbatt->att >= 9)) {
+                       dprintk(KERN_ERR PFX "ERROR: invalid bband_att: %u\n",
+                               bbatt->att);
+                       err = 1;
+               }
+               if (unlikely(err))
+                       dump_stack();
+       }
+}
+
+static
+struct bcm43xx_loctl * bcm43xx_get_lo_g_ctl_nopadmix(struct bcm43xx_wldev *dev,
+                                                 const struct bcm43xx_rfatt *rfatt,
+                                                 const struct bcm43xx_bbatt *bbatt)
+{
+       struct bcm43xx_phy *phy = &dev->phy;
+       struct bcm43xx_txpower_lo_control *lo = phy->lo_control;
+
+       assert_rfatt_and_bbatt(rfatt, bbatt);
+       return &(lo->no_padmix[bbatt->att][rfatt->att]);
+}
+
+struct bcm43xx_loctl * bcm43xx_get_lo_g_ctl(struct bcm43xx_wldev *dev,
+                                        const struct bcm43xx_rfatt *rfatt,
+                                        const struct bcm43xx_bbatt *bbatt)
+{
+       struct bcm43xx_phy *phy = &dev->phy;
+       struct bcm43xx_txpower_lo_control *lo = phy->lo_control;
+       struct bcm43xx_loctl *ret;
+
+       assert_rfatt_and_bbatt(rfatt, bbatt);
+       if (rfatt->with_padmix)
+               ret = &(lo->with_padmix[bbatt->att][rfatt->att]);
+       else
+               ret = &(lo->no_padmix[bbatt->att][rfatt->att]);
+
+       return ret;
+}
+
+/* Call a function for every possible LO control value-pair. */
+static int bcm43xx_call_for_each_loctl(struct bcm43xx_wldev *dev,
+                                      int (*func)(struct bcm43xx_wldev *,
+                                                  struct bcm43xx_loctl *))
+{
+       struct bcm43xx_phy *phy = &dev->phy;
+       struct bcm43xx_txpower_lo_control *ctl = phy->lo_control;
+       int i, j;
+       int err;
+
+       for (i = 0; i < BCM43xx_NR_BB; i++) {
+               for (j = 0; j < BCM43xx_NR_RF; j++) {
+                       err = func(dev, &(ctl->with_padmix[i][j]));
+                       if (unlikely(err))
+                               return err;
+               }
+       }
+       for (i = 0; i < BCM43xx_NR_BB; i++) {
+               for (j = 0; j < BCM43xx_NR_RF; j++) {
+                       err = func(dev, &(ctl->no_padmix[i][j]));
+                       if (unlikely(err))
+                               return err;
+               }
+       }
+
+       return 0;
+}
+
+static u16 lo_b_r15_loop(struct bcm43xx_wldev *dev)
+{
+       int i;
+       u16 ret = 0;
+
+       for (i = 0; i < 10; i++){
+               bcm43xx_phy_write(dev, 0x0015, 0xAFA0);
+               udelay(1);
+               bcm43xx_phy_write(dev, 0x0015, 0xEFA0);
+               udelay(10);
+               bcm43xx_phy_write(dev, 0x0015, 0xFFA0);
+               udelay(40);
+               ret += bcm43xx_phy_read(dev, 0x002C);
+       }
+
+       return ret;
+}
+
+void bcm43xx_lo_b_measure(struct bcm43xx_wldev *dev)
+{
+       struct bcm43xx_phy *phy = &dev->phy;
+       u16 regstack[12] = { 0 };
+       u16 mls;
+       u16 fval;
+       int i, j;
+
+       regstack[0] = bcm43xx_phy_read(dev, 0x0015);
+       regstack[1] = bcm43xx_radio_read16(dev, 0x0052) & 0xFFF0;
+
+       if (phy->radio_ver == 0x2053) {
+               regstack[2] = bcm43xx_phy_read(dev, 0x000A);
+               regstack[3] = bcm43xx_phy_read(dev, 0x002A);
+               regstack[4] = bcm43xx_phy_read(dev, 0x0035);
+               regstack[5] = bcm43xx_phy_read(dev, 0x0003);
+               regstack[6] = bcm43xx_phy_read(dev, 0x0001);
+               regstack[7] = bcm43xx_phy_read(dev, 0x0030);
+
+               regstack[8] = bcm43xx_radio_read16(dev, 0x0043);
+               regstack[9] = bcm43xx_radio_read16(dev, 0x007A);
+               regstack[10] = bcm43xx_read16(dev, 0x03EC);
+               regstack[11] = bcm43xx_radio_read16(dev, 0x0052) & 0x00F0;
+
+               bcm43xx_phy_write(dev, 0x0030, 0x00FF);
+               bcm43xx_write16(dev, 0x03EC, 0x3F3F);
+               bcm43xx_phy_write(dev, 0x0035, regstack[4] & 0xFF7F);
+               bcm43xx_radio_write16(dev, 0x007A, regstack[9] & 0xFFF0);
+       }
+       bcm43xx_phy_write(dev, 0x0015, 0xB000);
+       bcm43xx_phy_write(dev, 0x002B, 0x0004);
+
+       if (phy->radio_ver == 0x2053) {
+               bcm43xx_phy_write(dev, 0x002B, 0x0203);
+               bcm43xx_phy_write(dev, 0x002A, 0x08A3);
+       }
+
+       phy->minlowsig[0] = 0xFFFF;
+
+       for (i = 0; i < 4; i++) {
+               bcm43xx_radio_write16(dev, 0x0052, regstack[1] | i);
+               lo_b_r15_loop(dev);
+       }
+       for (i = 0; i < 10; i++) {
+               bcm43xx_radio_write16(dev, 0x0052, regstack[1] | i);
+               mls = lo_b_r15_loop(dev) / 10;
+               if (mls < phy->minlowsig[0]) {
+                       phy->minlowsig[0] = mls;
+                       phy->minlowsigpos[0] = i;
+               }
+       }
+       bcm43xx_radio_write16(dev, 0x0052, regstack[1] | phy->minlowsigpos[0]);
+
+       phy->minlowsig[1] = 0xFFFF;
+
+       for (i = -4; i < 5; i += 2) {
+               for (j = -4; j < 5; j += 2) {
+                       if (j < 0)
+                               fval = (0x0100 * i) + j + 0x0100;
+                       else
+                               fval = (0x0100 * i) + j;
+                       bcm43xx_phy_write(dev, 0x002F, fval);
+                       mls = lo_b_r15_loop(dev) / 10;
+                       if (mls < phy->minlowsig[1]) {
+                               phy->minlowsig[1] = mls;
+                               phy->minlowsigpos[1] = fval;
+                       }
+               }
+       }
+       phy->minlowsigpos[1] += 0x0101;
+
+       bcm43xx_phy_write(dev, 0x002F, phy->minlowsigpos[1]);
+       if (phy->radio_ver == 0x2053) {
+               bcm43xx_phy_write(dev, 0x000A, regstack[2]);
+               bcm43xx_phy_write(dev, 0x002A, regstack[3]);
+               bcm43xx_phy_write(dev, 0x0035, regstack[4]);
+               bcm43xx_phy_write(dev, 0x0003, regstack[5]);
+               bcm43xx_phy_write(dev, 0x0001, regstack[6]);
+               bcm43xx_phy_write(dev, 0x0030, regstack[7]);
+
+               bcm43xx_radio_write16(dev, 0x0043, regstack[8]);
+               bcm43xx_radio_write16(dev, 0x007A, regstack[9]);
+
+               bcm43xx_radio_write16(dev, 0x0052,
+                                     (bcm43xx_radio_read16(dev, 0x0052) & 0x000F)
+                                     | regstack[11]);
+
+               bcm43xx_write16(dev, 0x03EC, regstack[10]);
+       }
+       bcm43xx_phy_write(dev, 0x0015, regstack[0]);
+}
+
+static u16 lo_measure_feedthrough(struct bcm43xx_wldev *dev,
+                                 u16 lna, u16 pga, u16 trsw_rx)
+{
+       struct bcm43xx_phy *phy = &dev->phy;
+       u16 rfover;
+
+       if (phy->gmode) {
+               lna <<= BCM43xx_PHY_RFOVERVAL_LNA_SHIFT;
+               pga <<= BCM43xx_PHY_RFOVERVAL_PGA_SHIFT;
+
+               assert((lna & ~BCM43xx_PHY_RFOVERVAL_LNA) == 0);
+               assert((pga & ~BCM43xx_PHY_RFOVERVAL_PGA) == 0);
+/*FIXME This assertion fails           assert((trsw_rx & ~(BCM43xx_PHY_RFOVERVAL_TRSWRX |
+                                   BCM43xx_PHY_RFOVERVAL_BW)) == 0);
+*/
+trsw_rx &= (BCM43xx_PHY_RFOVERVAL_TRSWRX | BCM43xx_PHY_RFOVERVAL_BW);
+
+               /* Construct the RF Override Value */
+               rfover = BCM43xx_PHY_RFOVERVAL_UNK;
+               rfover |= pga;
+               rfover |= lna;
+               rfover |= trsw_rx;
+               if ((dev->dev->bus->sprom.r1.boardflags_lo & BCM43xx_BFL_EXTLNA) &&
+                   phy->rev > 6)
+                       rfover |= BCM43xx_PHY_RFOVERVAL_EXTLNA;
+
+               bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, 0xE300);
+               bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL, rfover);
+               udelay(10);
+               rfover |= BCM43xx_PHY_RFOVERVAL_BW_LBW;
+               bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL, rfover);
+               udelay(10);
+               rfover |= BCM43xx_PHY_RFOVERVAL_BW_LPF;
+               bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL, rfover);
+               udelay(10);
+               bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, 0xF300);
+       } else {
+               pga |= BCM43xx_PHY_PGACTL_UNKNOWN;
+               bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, pga);
+               udelay(10);
+               pga |= BCM43xx_PHY_PGACTL_LOWBANDW;
+               bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, pga);
+               udelay(10);
+               pga |= BCM43xx_PHY_PGACTL_LPF;
+               bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, pga);
+       }
+       udelay(21);
+
+       return bcm43xx_phy_read(dev, BCM43xx_PHY_LO_LEAKAGE);
+}
+
+/* TXCTL Register and Value Table.
+ * Returns the "TXCTL Register".
+ * "value" is the "TXCTL Value".
+ * "pad_mix_gain" is the PAD Mixer Gain.
+ */
+static u16 lo_txctl_register_table(struct bcm43xx_wldev *dev,
+                                  u16 *value, u16 *pad_mix_gain)
+{
+       struct bcm43xx_phy *phy = &dev->phy;
+       u16 reg, v, padmix;
+
+       if (phy->type == BCM43xx_PHYTYPE_B) {
+               v = 0x30;
+               if (phy->radio_rev <= 5) {
+                       reg = 0x43;
+                       padmix = 0;
+               } else {
+                       reg = 0x52;
+                       padmix = 5;
+               }
+       } else {
+               if (phy->rev >= 2 && phy->radio_rev == 8) {
+                       reg = 0x43;
+                       v = 0x10;
+                       padmix = 2;
+               } else {
+                       reg = 0x52;
+                       v = 0x30;
+                       padmix = 5;
+               }
+       }
+       if (value)
+               *value = v;
+       if (pad_mix_gain)
+               *pad_mix_gain = padmix;
+
+       return reg;
+}
+
+static void lo_measure_txctl_values(struct bcm43xx_wldev *dev)
+{
+       struct bcm43xx_phy *phy = &dev->phy;
+       struct bcm43xx_txpower_lo_control *lo = phy->lo_control;
+       u16 reg, mask;
+       u16 trsw_rx, pga;
+       u16 radio_pctl_reg;
+
+       static const u8 tx_bias_values[] = {
+               0x09, 0x08, 0x0A, 0x01, 0x00,
+               0x02, 0x05, 0x04, 0x06,
+       };
+       static const u8 tx_magn_values[] = {
+               0x70, 0x40,
+       };
+
+       if (!has_loopback_gain(phy)) {
+               radio_pctl_reg = 6;
+               trsw_rx = 2;
+               pga = 0;
+       } else {
+               int lb_gain; /* Loopback gain (in dB) */
+
+               trsw_rx = 0;
+               lb_gain = phy->max_lb_gain / 2;
+               if (lb_gain > 10) {
+                       radio_pctl_reg = 0;
+                       pga = abs(10 - lb_gain) / 6;
+                       pga = limit_value(pga, 0, 15);
+               } else {
+                       int cmp_val;
+                       int tmp;
+
+                       pga = 0;
+                       cmp_val = 0x24;
+                       if ((phy->rev >= 2) &&
+                           (phy->radio_ver == 0x2050) &&
+                           (phy->radio_rev == 8))
+                               cmp_val = 0x3C;
+                       tmp = lb_gain;
+                       if ((10 - lb_gain) < cmp_val)
+                               tmp = (10 - lb_gain);
+                       if (tmp < 0)
+                               tmp += 6;
+                       else
+                               tmp += 3;
+                       cmp_val /= 4;
+                       tmp /= 4;
+                       if (tmp >= cmp_val)
+                               radio_pctl_reg = cmp_val;
+                       else
+                               radio_pctl_reg = tmp;
+               }
+       }
+       bcm43xx_radio_write16(dev, 0x43,
+                             (bcm43xx_radio_read16(dev, 0x43)
+                              & 0xFFF0) | radio_pctl_reg);
+       bcm43xx_phy_set_baseband_attenuation(dev, 2);
+
+       reg = lo_txctl_register_table(dev, &mask, NULL);
+       mask = ~mask;
+       bcm43xx_radio_write16(dev, reg,
+                             bcm43xx_radio_read16(dev, reg)
+                             & mask);
+
+       if (has_tx_magnification(phy)) {
+               int i, j;
+               int feedthrough;
+               int min_feedth = 0xFFFF;
+               u8 tx_magn, tx_bias;
+
+               for (i = 0; i < ARRAY_SIZE(tx_magn_values); i++) {
+                       tx_magn = tx_magn_values[i];
+                       bcm43xx_radio_write16(dev, 0x52,
+                                             (bcm43xx_radio_read16(dev, 0x52)
+                                              & 0xFF0F) | tx_magn);
+                       for (j = 0; j < ARRAY_SIZE(tx_bias_values); j++) {
+                               tx_bias = tx_bias_values[j];
+                               bcm43xx_radio_write16(dev, 0x52,
+                                                     (bcm43xx_radio_read16(dev, 0x52)
+                                                      & 0xFFF0) | tx_bias);
+                               feedthrough = lo_measure_feedthrough(dev, 0, pga, trsw_rx);
+                               if (feedthrough < min_feedth) {
+                                       lo->tx_bias = tx_bias;
+                                       lo->tx_magn = tx_magn;
+                                       min_feedth = feedthrough;
+                               }
+                               if (lo->tx_bias == 0)
+                                       break;
+                       }
+                       bcm43xx_radio_write16(dev, 0x52,
+                                             (bcm43xx_radio_read16(dev, 0x52)
+                                              & 0xFF00) | lo->tx_bias | lo->tx_magn);
+               }
+       } else {
+               lo->tx_magn = 0; /* FIXME */
+               lo->tx_bias = 0;
+               bcm43xx_radio_write16(dev, 0x52,
+                                     bcm43xx_radio_read16(dev, 0x52)
+                                     & 0xFFF0); /* TX bias == 0 */
+       }
+}
+
+static void lo_read_power_vector(struct bcm43xx_wldev *dev)
+{
+       struct bcm43xx_phy *phy = &dev->phy;
+       struct bcm43xx_txpower_lo_control *lo = phy->lo_control;
+       u16 i;
+       u64 tmp;
+       u64 power_vector = 0;
+       int rf_offset, bb_offset;
+       struct bcm43xx_loctl *loctl;
+
+       for (i = 0; i < 8; i += 2) {
+               tmp = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
+                                        0x310 + i);
+               /* Clear the top byte. We get holes in the bitmap... */
+               tmp &= 0xFF;
+               power_vector |= (tmp << (i * 8));
+               /* Clear the vector on the device. */
+               bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
+                                   0x310 + i, 0);
+       }
+
+       if (power_vector)
+               lo->power_vector = power_vector;
+       power_vector = lo->power_vector;
+
+       for (i = 0; i < 64; i++) {
+               if (power_vector & ((u64)1ULL << i)) {
+                       /* Now figure out which bcm43xx_loctl corresponds
+                        * to this bit.
+                        */
+                       rf_offset = i / lo->rfatt_list.len;
+                       bb_offset = i % lo->rfatt_list.len;//FIXME?
+                       loctl = bcm43xx_get_lo_g_ctl(dev, &lo->rfatt_list.list[rf_offset],
+                                                 &lo->bbatt_list.list[bb_offset]);
+                       /* And mark it as "used", as the device told us
+                        * through the bitmap it is using it.
+                        */
+                       loctl->used = 1;
+               }
+       }
+}
+
+/* 802.11/LO/GPHY/MeasuringGains */
+static void lo_measure_gain_values(struct bcm43xx_wldev *dev,
+                                  s16 max_rx_gain,
+                                  int use_trsw_rx)
+{
+       struct bcm43xx_phy *phy = &dev->phy;
+       u16 tmp;
+
+       if (max_rx_gain < 0)
+               max_rx_gain = 0;
+
+       if (has_loopback_gain(phy)) {
+               int trsw_rx = 0;
+               int trsw_rx_gain;
+
+               if (use_trsw_rx) {
+                       trsw_rx_gain = phy->trsw_rx_gain / 2;
+                       if (max_rx_gain >= trsw_rx_gain) {
+                               trsw_rx_gain = max_rx_gain - trsw_rx_gain;
+                               trsw_rx = 0x20;
+                       }
+               } else
+                       trsw_rx_gain = max_rx_gain;
+               if (trsw_rx_gain < 9) {
+                       phy->lna_lod_gain = 0;
+               } else {
+                       phy->lna_lod_gain = 1;
+                       trsw_rx_gain -= 8;
+               }
+               trsw_rx_gain = limit_value(trsw_rx_gain, 0, 0x2D);
+               phy->pga_gain = trsw_rx_gain / 3;
+               if (phy->pga_gain >= 5) {
+                       phy->pga_gain -= 5;
+                       phy->lna_gain = 2;
+               } else
+                       phy->lna_gain = 0;
+       } else {
+               phy->lna_gain = 0;
+               phy->trsw_rx_gain = 0x20;
+               if (max_rx_gain >= 0x14) {
+                       phy->lna_lod_gain = 1;
+                       phy->pga_gain = 2;
+               } else if (max_rx_gain >= 0x12) {
+                       phy->lna_lod_gain = 1;
+                       phy->pga_gain = 1;
+               } else if (max_rx_gain >= 0xF) {
+                       phy->lna_lod_gain = 1;
+                       phy->pga_gain = 0;
+               } else {
+                       phy->lna_lod_gain = 0;
+                       phy->pga_gain = 0;
+               }
+       }
+
+       tmp = bcm43xx_radio_read16(dev, 0x7A);
+       if (phy->lna_lod_gain == 0)
+               tmp &= ~0x0008;
+       else
+               tmp |= 0x0008;
+       bcm43xx_radio_write16(dev, 0x7A, tmp);
+}
+
+struct lo_g_saved_values {
+       u8 old_channel;
+
+       /* Core registers */
+       u16 reg_3F4;
+       u16 reg_3E2;
+
+       /* PHY registers */
+       u16 phy_lo_mask;
+       u16 phy_extg_01;
+       u16 phy_dacctl_hwpctl;
+       u16 phy_dacctl;
+       u16 phy_base_14;
+       u16 phy_hpwr_tssictl;
+       u16 phy_analogover;
+       u16 phy_analogoverval;
+       u16 phy_rfover;
+       u16 phy_rfoverval;
+       u16 phy_classctl;
+       u16 phy_base_3E;
+       u16 phy_crs0;
+       u16 phy_pgactl;
+       u16 phy_base_2A;
+       u16 phy_syncctl;
+       u16 phy_base_30;
+       u16 phy_base_06;
+
+       /* Radio registers */
+       u16 radio_43;
+       u16 radio_7A;
+       u16 radio_52;
+};
+
+static void lo_measure_setup(struct bcm43xx_wldev *dev,
+                            struct lo_g_saved_values *sav)
+{
+       struct ssb_sprom *sprom = &dev->dev->bus->sprom;
+       struct bcm43xx_phy *phy = &dev->phy;
+       struct bcm43xx_txpower_lo_control *lo = phy->lo_control;
+       u16 tmp;
+
+       if (has_hardware_pctl(phy)) {
+               sav->phy_lo_mask = bcm43xx_phy_read(dev, BCM43xx_PHY_LO_MASK);
+               sav->phy_extg_01 = bcm43xx_phy_read(dev, BCM43xx_PHY_EXTG(0x01));
+               sav->phy_dacctl_hwpctl = bcm43xx_phy_read(dev, BCM43xx_PHY_DACCTL);
+               sav->phy_base_14 = bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x14));
+               sav->phy_hpwr_tssictl = bcm43xx_phy_read(dev, BCM43xx_PHY_HPWR_TSSICTL);
+
+               bcm43xx_phy_write(dev, BCM43xx_PHY_HPWR_TSSICTL,
+                                 bcm43xx_phy_read(dev, BCM43xx_PHY_HPWR_TSSICTL)
+                                 | 0x100);
+               bcm43xx_phy_write(dev, BCM43xx_PHY_EXTG(0x01),
+                                 bcm43xx_phy_read(dev, BCM43xx_PHY_EXTG(0x01))
+                                 | 0x40);
+               bcm43xx_phy_write(dev, BCM43xx_PHY_DACCTL,
+                                 bcm43xx_phy_read(dev, BCM43xx_PHY_DACCTL)
+                                 | 0x40);
+               bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x14),
+                                 bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x14))
+                                 | 0x200);
+       }
+       if (phy->type == BCM43xx_PHYTYPE_B &&
+           phy->radio_ver == 0x2050 &&
+           phy->radio_rev < 6) {
+               bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x16), 0x410);
+               bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x17), 0x820);
+       }
+       if (!lo->rebuild && has_hardware_pctl(phy))
+               lo_read_power_vector(dev);
+       if (phy->rev >= 2) {
+               sav->phy_analogover = bcm43xx_phy_read(dev, BCM43xx_PHY_ANALOGOVER);
+               sav->phy_analogoverval = bcm43xx_phy_read(dev, BCM43xx_PHY_ANALOGOVERVAL);
+               sav->phy_rfover = bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVER);
+               sav->phy_rfoverval = bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVERVAL);
+               sav->phy_classctl = bcm43xx_phy_read(dev, BCM43xx_PHY_CLASSCTL);
+               sav->phy_base_3E = bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x3E));
+               sav->phy_crs0 = bcm43xx_phy_read(dev, BCM43xx_PHY_CRS0);
+
+               bcm43xx_phy_write(dev, BCM43xx_PHY_CLASSCTL,
+                                 bcm43xx_phy_read(dev, BCM43xx_PHY_CLASSCTL)
+                                 & 0xFFFC);
+               bcm43xx_phy_write(dev, BCM43xx_PHY_CRS0,
+                                 bcm43xx_phy_read(dev, BCM43xx_PHY_CRS0)
+                                 & 0x7FFF);
+               bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVER,
+                                 bcm43xx_phy_read(dev, BCM43xx_PHY_ANALOGOVER)
+                                 | 0x0003);
+               bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVERVAL,
+                                 bcm43xx_phy_read(dev, BCM43xx_PHY_ANALOGOVERVAL)
+                                 & 0xFFFC);
+               if (phy->type == BCM43xx_PHYTYPE_G) {
+                       if ((phy->rev >= 7) &&
+                           (sprom->r1.boardflags_lo & BCM43xx_BFL_EXTLNA)) {
+                               bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVER, 0x933);
+                       } else {
+                               bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVER, 0x133);
+                       }
+               } else {
+                       bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVER, 0);
+               }
+               bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x3E), 0);
+       }
+       sav->reg_3F4 = bcm43xx_read16(dev, 0x3F4);
+       sav->reg_3E2 = bcm43xx_read16(dev, 0x3E2);
+       sav->radio_43 = bcm43xx_radio_read16(dev, 0x43);
+       sav->radio_7A = bcm43xx_radio_read16(dev, 0x7A);
+       sav->phy_pgactl = bcm43xx_phy_read(dev, BCM43xx_PHY_PGACTL);
+       sav->phy_base_2A = bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x2A));
+       sav->phy_syncctl = bcm43xx_phy_read(dev, BCM43xx_PHY_SYNCCTL);
+       sav->phy_dacctl = bcm43xx_phy_read(dev, BCM43xx_PHY_DACCTL);
+
+       if (!has_tx_magnification(phy)) {
+               sav->radio_52 = bcm43xx_radio_read16(dev, 0x52);
+               sav->radio_52 &= 0x00F0;
+       }
+       if (phy->type == BCM43xx_PHYTYPE_B) {
+               sav->phy_base_30 = bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x30));
+               sav->phy_base_06 = bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x06));
+               bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x30), 0x00FF);
+               bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x06), 0x3F3F);
+       } else {
+               bcm43xx_write16(dev, 0x3E2,
+                               bcm43xx_read16(dev, 0x3E2)
+                               | 0x8000);
+       }
+       bcm43xx_write16(dev, 0x3F4,
+                       bcm43xx_read16(dev, 0x3F4)
+                       & 0xF000);
+
+       tmp = (phy->type == BCM43xx_PHYTYPE_G) ? BCM43xx_PHY_LO_MASK : BCM43xx_PHY_BASE(0x2E);
+       bcm43xx_phy_write(dev, tmp, 0x007F);
+
+       tmp = sav->phy_syncctl;
+       bcm43xx_phy_write(dev, BCM43xx_PHY_SYNCCTL, tmp & 0xFF7F);
+       tmp = sav->radio_7A;
+       bcm43xx_radio_write16(dev, 0x007A, tmp & 0xFFF0);
+
+       bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2A), 0x8A3);
+       if (phy->type == BCM43xx_PHYTYPE_G ||
+           (phy->type == BCM43xx_PHYTYPE_B &&
+            phy->radio_ver == 0x2050 &&
+            phy->radio_rev >= 6)) {
+               bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2B), 0x1003);
+       } else
+               bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2B), 0x0802);
+       if (phy->rev >= 2)
+               bcm43xx_dummy_transmission(dev);
+       bcm43xx_radio_selectchannel(dev, 6, 0);
+       bcm43xx_radio_read16(dev, 0x51); /* dummy read */
+       if (phy->type == BCM43xx_PHYTYPE_G)
+               bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2F), 0);
+       if (lo->rebuild)
+               lo_measure_txctl_values(dev);
+       if (phy->type == BCM43xx_PHYTYPE_G && phy->rev >= 3) {
+               bcm43xx_phy_write(dev, BCM43xx_PHY_LO_MASK, 0xC078);
+       } else {
+               if (phy->type == BCM43xx_PHYTYPE_B)
+                       bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2E), 0x8078);
+               else
+                       bcm43xx_phy_write(dev, BCM43xx_PHY_LO_MASK, 0x8078);
+       }
+}
+
+static void lo_measure_restore(struct bcm43xx_wldev *dev,
+                              struct lo_g_saved_values *sav)
+{
+       struct bcm43xx_phy *phy = &dev->phy;
+       struct bcm43xx_txpower_lo_control *lo = phy->lo_control;
+       u16 tmp;
+
+       if (phy->rev >= 2) {
+               bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, 0xE300);
+               tmp = (phy->pga_gain << 8);
+               bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL, tmp | 0xA0);
+               udelay(5);
+               bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL, tmp | 0xA2);
+               udelay(2);
+               bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL, tmp | 0xA3);
+       } else {
+               tmp = (phy->pga_gain | 0xEFA0);
+               bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, tmp);
+       }
+       if (has_hardware_pctl(phy)) {
+               bcm43xx_gphy_dc_lt_init(dev);
+       } else {
+               if (lo->rebuild)
+                       bcm43xx_lo_g_adjust_to(dev, 3, 2, 0);
+               else
+                       bcm43xx_lo_g_adjust(dev);
+       }
+       if (phy->type == BCM43xx_PHYTYPE_G) {
+               if (phy->rev >= 3)
+                       bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2E), 0xC078);
+               else
+                       bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2E), 0x8078);
+               if (phy->rev >= 2)
+                       bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2F), 0x0202);
+               else
+                       bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2F), 0x0101);
+       }
+       bcm43xx_write16(dev, 0x3F4, sav->reg_3F4);
+       bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, sav->phy_pgactl);
+       bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2A), sav->phy_base_2A);
+       bcm43xx_phy_write(dev, BCM43xx_PHY_SYNCCTL, sav->phy_syncctl);
+       bcm43xx_phy_write(dev, BCM43xx_PHY_DACCTL, sav->phy_dacctl);
+       bcm43xx_radio_write16(dev, 0x43, sav->radio_43);
+       bcm43xx_radio_write16(dev, 0x7A, sav->radio_7A);
+       if (!has_tx_magnification(phy)) {
+               tmp = sav->radio_52;
+               bcm43xx_radio_write16(dev, 0x52,
+                                     (bcm43xx_radio_read16(dev, 0x52)
+                                      & 0xFF0F) | tmp);
+       }
+       bcm43xx_write16(dev, 0x3E2, sav->reg_3E2);
+       if (phy->type == BCM43xx_PHYTYPE_B &&
+           phy->radio_ver == 0x2050 &&
+           phy->radio_rev <= 5) {
+               bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x30), sav->phy_base_30);
+               bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x06), sav->phy_base_06);
+       }
+       if (phy->rev >= 2) {
+               bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVER, sav->phy_analogover);
+               bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVERVAL, sav->phy_analogoverval);
+               bcm43xx_phy_write(dev, BCM43xx_PHY_CLASSCTL, sav->phy_classctl);
+               bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVER, sav->phy_rfover);
+               bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL, sav->phy_rfoverval);
+               bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x3E), sav->phy_base_3E);
+               bcm43xx_phy_write(dev, BCM43xx_PHY_CRS0, sav->phy_crs0);
+       }
+       if (has_hardware_pctl(phy)) {
+               tmp = (sav->phy_lo_mask & 0xBFFF);
+               bcm43xx_phy_write(dev, BCM43xx_PHY_LO_MASK, tmp);
+               bcm43xx_phy_write(dev, BCM43xx_PHY_EXTG(0x01), sav->phy_extg_01);
+               bcm43xx_phy_write(dev, BCM43xx_PHY_DACCTL, sav->phy_dacctl_hwpctl);
+               bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x14), sav->phy_base_14);
+               bcm43xx_phy_write(dev, BCM43xx_PHY_HPWR_TSSICTL, sav->phy_hpwr_tssictl);
+       }
+       bcm43xx_radio_selectchannel(dev, sav->old_channel, 1);
+}
+
+struct bcm43xx_lo_g_statemachine {
+       int current_state;
+       int nr_measured;
+       int state_val_multiplier;
+       u16 lowest_feedth;
+       struct bcm43xx_loctl min_loctl;
+};
+
+/* Loop over each possible value in this state. */
+static int lo_probe_possible_loctls(struct bcm43xx_wldev *dev,
+                                   struct bcm43xx_loctl *probe_loctl,
+                                   struct bcm43xx_lo_g_statemachine *d)
+{
+       struct bcm43xx_phy *phy = &dev->phy;
+       struct bcm43xx_txpower_lo_control *lo = phy->lo_control;
+       struct bcm43xx_loctl test_loctl;
+       struct bcm43xx_loctl orig_loctl;
+       struct bcm43xx_loctl prev_loctl = {
+               .i = -100,
+               .q = -100,
+       };
+       int i;
+       int begin, end;
+       int found_lower = 0;
+       u16 feedth;
+
+       static const struct bcm43xx_loctl modifiers[] = {
+               { .i =  1,  .q =  1, },
+               { .i =  1,  .q =  0, },
+               { .i =  1,  .q = -1, },
+               { .i =  0,  .q = -1, },
+               { .i = -1,  .q = -1, },
+               { .i = -1,  .q =  0, },
+               { .i = -1,  .q =  1, },
+               { .i =  0,  .q =  1, },
+       };
+
+       if (d->current_state == 0) {
+               begin = 1;
+               end = 8;
+       } else if (d->current_state % 2 == 0) {
+               begin = d->current_state - 1;
+               end = d->current_state + 1;
+       } else {
+               begin = d->current_state - 2;
+               end = d->current_state + 2;
+       }
+       if (begin < 1)
+               begin += 8;
+       if (end > 8)
+               end -= 8;
+
+       memcpy(&orig_loctl, probe_loctl, sizeof(struct bcm43xx_loctl));
+       i = begin;
+       d->current_state = i;
+       while (1) {
+               assert(i >= 1 && i <= 8);
+               memcpy(&test_loctl, &orig_loctl, sizeof(struct bcm43xx_loctl));
+               test_loctl.i += modifiers[i - 1].i * d->state_val_multiplier;
+               test_loctl.q += modifiers[i - 1].q * d->state_val_multiplier;
+               if ((test_loctl.i != prev_loctl.i ||
+                    test_loctl.q != prev_loctl.q) &&
+                   (abs(test_loctl.i) <= 16 &&
+                    abs(test_loctl.q) <= 16)) {
+                       bcm43xx_lo_write(dev, &test_loctl);
+                       feedth = lo_measure_feedthrough(dev, phy->lna_gain,
+                                                       phy->pga_gain,
+                                                       phy->trsw_rx_gain);
+                       if (feedth < d->lowest_feedth) {
+                               memcpy(probe_loctl, &test_loctl, sizeof(struct bcm43xx_loctl));
+                               found_lower = 1;
+                               d->lowest_feedth = feedth;
+                               if ((d->nr_measured < 2) &&
+                                   (!has_loopback_gain(phy) || lo->rebuild))
+                                       break;
+                       }
+               }
+               memcpy(&prev_loctl, &test_loctl, sizeof(prev_loctl));
+               if (i == end)
+                       break;
+               if (i == 8)
+                       i = 1;
+               else
+                       i++;
+               d->current_state = i;
+       }
+
+       return found_lower;
+}
+
+static void lo_probe_loctls_statemachine(struct bcm43xx_wldev *dev,
+                                        struct bcm43xx_loctl *loctl,
+                                        int *max_rx_gain)
+{
+       struct bcm43xx_phy *phy = &dev->phy;
+       struct bcm43xx_txpower_lo_control *lo = phy->lo_control;
+       struct bcm43xx_lo_g_statemachine d;
+       u16 feedth;
+       int found_lower;
+       struct bcm43xx_loctl probe_loctl;
+       int max_repeat = 1, repeat_cnt = 0;
+
+       d.nr_measured = 0;
+       d.state_val_multiplier = 1;
+       if (has_loopback_gain(phy) && !lo->rebuild)
+               d.state_val_multiplier = 3;
+
+       memcpy(&d.min_loctl, loctl, sizeof(struct bcm43xx_loctl));
+       if (has_loopback_gain(phy) && lo->rebuild)
+               max_repeat = 4;
+       do {
+               bcm43xx_lo_write(dev, &d.min_loctl);
+               feedth = lo_measure_feedthrough(dev, phy->lna_gain,
+                                               phy->pga_gain,
+                                               phy->trsw_rx_gain);
+               if (!lo->rebuild && feedth < 0x258) {
+                       if (feedth >= 0x12C)
+                               *max_rx_gain += 6;
+                       else
+                               *max_rx_gain += 3;
+                       feedth = lo_measure_feedthrough(dev, phy->lna_gain,
+                                                       phy->pga_gain,
+                                                       phy->trsw_rx_gain);
+               }
+               d.lowest_feedth = feedth;
+
+               d.current_state = 0;
+               do {
+                       assert(d.current_state >= 0 && d.current_state <= 8);
+                       memcpy(&probe_loctl, &d.min_loctl, sizeof(struct bcm43xx_loctl));
+                       found_lower = lo_probe_possible_loctls(dev, &probe_loctl, &d);
+                       if (!found_lower)
+                               break;
+                       if ((probe_loctl.i == d.min_loctl.i) &&
+                           (probe_loctl.q == d.min_loctl.q))
+                               break;
+                       memcpy(&d.min_loctl, &probe_loctl, sizeof(struct bcm43xx_loctl));
+                       d.nr_measured++;
+               } while (d.nr_measured < 24);
+               memcpy(loctl, &d.min_loctl, sizeof(struct bcm43xx_loctl));
+
+               if (has_loopback_gain(phy)) {
+                       if (d.lowest_feedth > 0x1194)
+                               *max_rx_gain -= 6;
+                       else if (d.lowest_feedth < 0x5DC)
+                               *max_rx_gain += 3;
+                       if (repeat_cnt == 0) {
+                               if (d.lowest_feedth <= 0x5DC) {
+                                       d.state_val_multiplier = 1;
+                                       repeat_cnt++;
+                               } else
+                                       d.state_val_multiplier = 2;
+                       } else if (repeat_cnt == 2)
+                               d.state_val_multiplier = 1;
+               }
+               lo_measure_gain_values(dev, *max_rx_gain, has_loopback_gain(phy));
+       } while (++repeat_cnt < max_repeat);
+}
+
+static void lo_measure(struct bcm43xx_wldev *dev)
+{
+       struct bcm43xx_phy *phy = &dev->phy;
+       struct bcm43xx_txpower_lo_control *lo = phy->lo_control;
+       struct bcm43xx_loctl loctl = {
+               .i      = 0,
+               .q      = 0,
+       };
+       struct bcm43xx_loctl *ploctl;
+       int max_rx_gain;
+       int rfidx, bbidx;
+
+       /* Values from the "TXCTL Register and Value Table" */
+       u16 txctl_reg;
+       u16 txctl_value;
+       u16 pad_mix_gain;
+
+       txctl_reg = lo_txctl_register_table(dev, &txctl_value, &pad_mix_gain);
+
+       for (rfidx = 0; rfidx < lo->rfatt_list.len; rfidx++) {
+
+               bcm43xx_radio_write16(dev, 0x43,
+                                     (bcm43xx_radio_read16(dev, 0x43)
+                                      & 0xFFF0) | lo->rfatt_list.list[rfidx].att);
+               bcm43xx_radio_write16(dev, txctl_reg,
+                                     (bcm43xx_radio_read16(dev, txctl_reg)
+                                      & ~txctl_value)
+                                     | (lo->rfatt_list.list[rfidx].with_padmix ? txctl_value : 0));
+
+               for (bbidx = 0; bbidx < lo->bbatt_list.len; bbidx++) {
+                       if (lo->rebuild) {
+                               ploctl = bcm43xx_get_lo_g_ctl_nopadmix(dev,
+                                                       &lo->rfatt_list.list[rfidx],
+                                                       &lo->bbatt_list.list[bbidx]);
+                       } else {
+                               ploctl = bcm43xx_get_lo_g_ctl(dev, &lo->rfatt_list.list[rfidx],
+                                                          &lo->bbatt_list.list[bbidx]);
+                               if (!ploctl->used)
+                                       continue;
+                       }
+                       memcpy(&loctl, ploctl, sizeof(loctl));
+
+                       max_rx_gain = lo->rfatt_list.list[rfidx].att * 2;
+                       max_rx_gain += lo->bbatt_list.list[bbidx].att / 2;
+                       if (lo->rfatt_list.list[rfidx].with_padmix)
+                               max_rx_gain -= pad_mix_gain;
+                       if (has_loopback_gain(phy))
+                               max_rx_gain += phy->max_lb_gain;
+                       lo_measure_gain_values(dev, max_rx_gain, has_loopback_gain(phy));
+
+                       bcm43xx_phy_set_baseband_attenuation(dev, lo->bbatt_list.list[bbidx].att);
+                       lo_probe_loctls_statemachine(dev, &loctl, &max_rx_gain);
+                       if (phy->type == BCM43xx_PHYTYPE_B) {
+                               loctl.i++;
+                               loctl.q++;
+                       }
+                       memcpy(ploctl, &loctl, sizeof(loctl));
+               }
+       }
+}
+
+#if BCM43xx_DEBUG
+static int do_validate_loctl(struct bcm43xx_wldev *dev,
+                            struct bcm43xx_loctl *control)
+{
+       const int is_initializing = (bcm43xx_status(dev) == BCM43xx_STAT_INITIALIZING);
+
+       if (unlikely(abs(control->i) > 16 ||
+                    abs(control->q) > 16 ||
+                    (is_initializing && control->used))) {
+               printk(KERN_ERR PFX "ERROR: LO control pair validation failed "
+                                   "(first: %d, second: %d, used %u)\n",
+                      control->i, control->q, control->used);
+       }
+       return 0;
+}
+static void validate_all_loctls(struct bcm43xx_wldev *dev)
+{
+       bcm43xx_call_for_each_loctl(dev, do_validate_loctl);
+}
+#else /* BCM43xx_DEBUG */
+static inline void validate_all_loctls(struct bcm43xx_wldev *dev) { }
+#endif /* BCM43xx_DEBUG */
+
+void bcm43xx_lo_g_measure(struct bcm43xx_wldev *dev)
+{
+       struct bcm43xx_phy *phy = &dev->phy;
+       struct lo_g_saved_values sav;
+
+       assert(phy->type == BCM43xx_PHYTYPE_B ||
+              phy->type == BCM43xx_PHYTYPE_G);
+
+       sav.old_channel = phy->channel;
+       lo_measure_setup(dev, &sav);
+       lo_measure(dev);
+       lo_measure_restore(dev, &sav);
+
+       validate_all_loctls(dev);
+
+       phy->lo_control->lo_measured = 1;
+       phy->lo_control->rebuild = 0;
+}
+
+void bcm43xx_lo_g_adjust(struct bcm43xx_wldev *dev)
+{
+       bcm43xx_lo_write(dev, bcm43xx_lo_g_ctl_current(dev));
+}
+
+static inline void fixup_rfatt_for_txctl1(struct bcm43xx_rfatt *rf,
+                                         u16 txctl1)
+{
+       if ((rf->att < 5) && (txctl1 & 0x0001))
+               rf->att = 4;
+}
+
+void bcm43xx_lo_g_adjust_to(struct bcm43xx_wldev *dev,
+                         u16 rfatt, u16 bbatt, u16 txctl1)
+{
+       struct bcm43xx_rfatt rf;
+       struct bcm43xx_bbatt bb;
+       struct bcm43xx_loctl *loctl;
+
+       memset(&rf, 0, sizeof(rf));
+       memset(&bb, 0, sizeof(bb));
+       rf.att = rfatt;
+       bb.att = bbatt;
+       fixup_rfatt_for_txctl1(&rf, txctl1);
+       loctl = bcm43xx_get_lo_g_ctl(dev, &rf, &bb);
+       bcm43xx_lo_write(dev, loctl);
+}
+
+struct bcm43xx_loctl * bcm43xx_lo_g_ctl_current(struct bcm43xx_wldev *dev)
+{
+       struct bcm43xx_phy *phy = &dev->phy;
+       struct bcm43xx_txpower_lo_control *lo = phy->lo_control;
+       struct bcm43xx_rfatt rf;
+
+       memcpy(&rf, &lo->rfatt, sizeof(rf));
+       fixup_rfatt_for_txctl1(&rf, phy->txctl1);
+
+       return bcm43xx_get_lo_g_ctl(dev, &rf, &lo->bbatt);
+}
+
+static int do_mark_unused(struct bcm43xx_wldev *dev,
+                         struct bcm43xx_loctl *control)
+{
+       control->used = 0;
+       return 0;
+}
+
+void bcm43xx_lo_g_ctl_mark_all_unused(struct bcm43xx_wldev *dev)
+{
+       struct bcm43xx_phy *phy = &dev->phy;
+       struct bcm43xx_txpower_lo_control *lo = phy->lo_control;
+
+       bcm43xx_call_for_each_loctl(dev, do_mark_unused);
+       lo->rebuild = 1;
+}
+
+void bcm43xx_lo_g_ctl_mark_cur_used(struct bcm43xx_wldev *dev)
+{
+       bcm43xx_lo_g_ctl_current(dev)->used = 1;
+}
diff --git a/package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_lo.h b/package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_lo.h
new file mode 100644 (file)
index 0000000..e9d4d59
--- /dev/null
@@ -0,0 +1,92 @@
+#ifndef BCM43xx_LO_H_
+#define BCM43xx_LO_H_
+
+#include "bcm43xx_phy.h"
+
+struct bcm43xx_wldev;
+
+/* Local Oscillator control value-pair. */
+struct bcm43xx_loctl {
+       /* Control values. */
+       s8 i;
+       s8 q;
+       /* "Used by hardware" flag. */
+       u8 used;
+};
+
+/* TX Power LO Control Array.
+ * Value-pairs to adjust the LocalOscillator are stored
+ * in this structure.
+ * There are two different set of values. One for "Flag is Set"
+ * and one for "Flag is Unset".
+ * By "Flag" the flag in struct bcm43xx_rfatt is meant.
+ * The Value arrays are two-dimensional. The first index
+ * is the baseband attenuation and the second index
+ * is the radio attenuation.
+ * Use bcm43xx_get_lo_g_ctl() to retrieve a value from the lists.
+ */
+struct bcm43xx_txpower_lo_control {
+#define BCM43xx_NR_BB  9
+#define BCM43xx_NR_RF  16
+       /* LO Control values, with PAD Mixer */
+       struct bcm43xx_loctl with_padmix[ BCM43xx_NR_BB ][ BCM43xx_NR_RF ];
+       /* LO Control values, without PAD Mixer */
+       struct bcm43xx_loctl no_padmix[ BCM43xx_NR_BB ][ BCM43xx_NR_RF ];
+
+       /* Flag to indicate a complete rebuild of the two tables above
+        * to the LO measuring code. */
+       u8 rebuild;
+
+       /* Lists of valid RF and BB attenuation values for this device. */
+       struct bcm43xx_rfatt_list rfatt_list;
+       struct bcm43xx_bbatt_list bbatt_list;
+
+       /* Current RF and BB attenuation and LO control values. */
+       struct bcm43xx_rfatt rfatt;
+       struct bcm43xx_bbatt bbatt;
+
+       /* Current TX Bias value */
+       u8 tx_bias;
+       /* Current TX Magnification Value (if used by the device) */
+       u8 tx_magn;
+
+       /* GPHY LO is measured. */
+       u8 lo_measured;
+
+       /* Saved device PowerVector */
+       u64 power_vector;
+};
+
+
+/* Measure the BPHY Local Oscillator. */
+void bcm43xx_lo_b_measure(struct bcm43xx_wldev *dev);
+/* Measure the BPHY/GPHY Local Oscillator. */
+void bcm43xx_lo_g_measure(struct bcm43xx_wldev *dev);
+
+/* Adjust the Local Oscillator to the saved attenuation
+ * and txctl values.
+ */
+void bcm43xx_lo_g_adjust(struct bcm43xx_wldev *dev);
+/* Adjust to specific values. */
+void bcm43xx_lo_g_adjust_to(struct bcm43xx_wldev *dev,
+                         u16 rfatt, u16 bbatt, u16 txctl1);
+
+/* Returns the bcm43xx_lo_g_ctl corresponding to the current
+ * attenuation values.
+ */
+struct bcm43xx_loctl * bcm43xx_lo_g_ctl_current(struct bcm43xx_wldev *dev);
+/* Mark all possible bcm43xx_lo_g_ctl as "unused" */
+void bcm43xx_lo_g_ctl_mark_all_unused(struct bcm43xx_wldev *dev);
+/* Mark the bcm43xx_lo_g_ctl corresponding to the current
+ * attenuation values as used.
+ */
+void bcm43xx_lo_g_ctl_mark_cur_used(struct bcm43xx_wldev *dev);
+
+/* Get a reference to a LO Control value pair in the
+ * TX Power LO Control Array.
+ */
+struct bcm43xx_loctl * bcm43xx_get_lo_g_ctl(struct bcm43xx_wldev *dev,
+                                        const struct bcm43xx_rfatt *rfatt,
+                                        const struct bcm43xx_bbatt *bbatt);
+
+#endif /* BCM43xx_LO_H_ */
diff --git a/package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_main.c b/package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_main.c
new file mode 100644 (file)
index 0000000..032e31a
--- /dev/null
@@ -0,0 +1,4022 @@
+/*
+
+  Broadcom BCM43xx wireless driver
+
+  Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
+  Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
+  Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
+  Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
+  Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
+
+  Some parts of the code in this file are derived from the ipw2200
+  driver  Copyright(c) 2003 - 2004 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation; either version 2 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program; see the file COPYING.  If not, write to
+  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
+  Boston, MA 02110-1301, USA.
+
+*/
+
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/moduleparam.h>
+#include <linux/if_arp.h>
+#include <linux/etherdevice.h>
+#include <linux/version.h>
+#include <linux/firmware.h>
+#include <linux/wireless.h>
+#include <linux/workqueue.h>
+#include <linux/skbuff.h>
+#include <linux/dma-mapping.h>
+
+#include "bcm43xx.h"
+#include "bcm43xx_main.h"
+#include "bcm43xx_debugfs.h"
+#include "bcm43xx_phy.h"
+#include "bcm43xx_dma.h"
+#include "bcm43xx_pio.h"
+#include "bcm43xx_power.h"
+#include "bcm43xx_sysfs.h"
+#include "bcm43xx_xmit.h"
+#include "bcm43xx_sysfs.h"
+#include "bcm43xx_lo.h"
+#include "bcm43xx_pcmcia.h"
+
+
+MODULE_DESCRIPTION("Broadcom BCM43xx wireless driver");
+MODULE_AUTHOR("Martin Langer");
+MODULE_AUTHOR("Stefano Brivio");
+MODULE_AUTHOR("Michael Buesch");
+MODULE_LICENSE("GPL");
+
+
+extern char *nvram_get(char *name);
+
+
+#if defined(CONFIG_BCM43XX_MAC80211_DMA) && defined(CONFIG_BCM43XX_MAC80211_PIO)
+static int modparam_pio;
+module_param_named(pio, modparam_pio, int, 0444);
+MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
+#elif defined(CONFIG_BCM43XX_MAC80211_DMA)
+# define modparam_pio  0
+#elif defined(CONFIG_BCM43XX_MAC80211_PIO)
+# define modparam_pio  1
+#endif
+
+static int modparam_bad_frames_preempt;
+module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
+MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames Preemption");
+
+static int modparam_short_retry = BCM43xx_DEFAULT_SHORT_RETRY_LIMIT;
+module_param_named(short_retry, modparam_short_retry, int, 0444);
+MODULE_PARM_DESC(short_retry, "Short-Retry-Limit (0 - 15)");
+
+static int modparam_long_retry = BCM43xx_DEFAULT_LONG_RETRY_LIMIT;
+module_param_named(long_retry, modparam_long_retry, int, 0444);
+MODULE_PARM_DESC(long_retry, "Long-Retry-Limit (0 - 15)");
+
+static int modparam_noleds;
+module_param_named(noleds, modparam_noleds, int, 0444);
+MODULE_PARM_DESC(noleds, "Turn off all LED activity");
+
+static char modparam_fwpostfix[16];
+module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
+MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
+
+static int modparam_mon_keep_bad;
+module_param_named(mon_keep_bad, modparam_mon_keep_bad, int, 0444);
+MODULE_PARM_DESC(mon_keep_bad, "Keep bad frames in monitor mode");
+
+static int modparam_mon_keep_badplcp;
+module_param_named(mon_keep_badplcp, modparam_mon_keep_bad, int, 0444);
+MODULE_PARM_DESC(mon_keep_badplcp, "Keep frames with bad PLCP in monitor mode");
+
+
+static const struct ssb_device_id bcm43xx_ssb_tbl[] = {
+       SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, SSB_ANY_REV),
+       SSB_DEVTABLE_END
+};
+MODULE_DEVICE_TABLE(ssb, bcm43xx_ssb_tbl);
+
+
+/* Channel and ratetables are shared for all devices.
+ * They can't be const, because ieee80211 puts some precalculated
+ * data in there. This data is the same for all devices, so we don't
+ * get concurrency issues */
+#define RATETAB_ENT(_rateid, _flags) \
+       {                                                       \
+               .rate   = BCM43xx_RATE_TO_BASE100KBPS(_rateid), \
+               .val    = (_rateid),                            \
+               .val2   = (_rateid),                            \
+               .flags  = (_flags),                             \
+       }
+static struct ieee80211_rate __bcm43xx_ratetable[] = {
+       RATETAB_ENT(BCM43xx_CCK_RATE_1MB, IEEE80211_RATE_CCK),
+       RATETAB_ENT(BCM43xx_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
+       RATETAB_ENT(BCM43xx_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
+       RATETAB_ENT(BCM43xx_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
+       RATETAB_ENT(BCM43xx_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
+       RATETAB_ENT(BCM43xx_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
+       RATETAB_ENT(BCM43xx_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
+       RATETAB_ENT(BCM43xx_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
+       RATETAB_ENT(BCM43xx_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
+       RATETAB_ENT(BCM43xx_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
+       RATETAB_ENT(BCM43xx_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
+       RATETAB_ENT(BCM43xx_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
+};
+#define bcm43xx_a_ratetable            (__bcm43xx_ratetable + 4)
+#define bcm43xx_a_ratetable_size       8
+#define bcm43xx_b_ratetable            (__bcm43xx_ratetable + 0)
+#define bcm43xx_b_ratetable_size       4
+#define bcm43xx_g_ratetable            (__bcm43xx_ratetable + 0)
+#define bcm43xx_g_ratetable_size       12
+
+#define CHANTAB_ENT(_chanid, _freq) \
+       {                                                       \
+               .chan   = (_chanid),                            \
+               .freq   = (_freq),                              \
+               .val    = (_chanid),                            \
+               .flag   = IEEE80211_CHAN_W_SCAN |               \
+                         IEEE80211_CHAN_W_ACTIVE_SCAN |        \
+                         IEEE80211_CHAN_W_IBSS,                \
+               .power_level    = 0xFF,                         \
+               .antenna_max    = 0xFF,                         \
+       }
+static struct ieee80211_channel bcm43xx_bg_chantable[] = {
+       CHANTAB_ENT(1, 2412),
+       CHANTAB_ENT(2, 2417),
+       CHANTAB_ENT(3, 2422),
+       CHANTAB_ENT(4, 2427),
+       CHANTAB_ENT(5, 2432),
+       CHANTAB_ENT(6, 2437),
+       CHANTAB_ENT(7, 2442),
+       CHANTAB_ENT(8, 2447),
+       CHANTAB_ENT(9, 2452),
+       CHANTAB_ENT(10, 2457),
+       CHANTAB_ENT(11, 2462),
+       CHANTAB_ENT(12, 2467),
+       CHANTAB_ENT(13, 2472),
+       CHANTAB_ENT(14, 2484),
+};
+#define bcm43xx_bg_chantable_size      ARRAY_SIZE(bcm43xx_bg_chantable)
+static struct ieee80211_channel bcm43xx_a_chantable[] = {
+       CHANTAB_ENT(36, 5180),
+       CHANTAB_ENT(40, 5200),
+       CHANTAB_ENT(44, 5220),
+       CHANTAB_ENT(48, 5240),
+       CHANTAB_ENT(52, 5260),
+       CHANTAB_ENT(56, 5280),
+       CHANTAB_ENT(60, 5300),
+       CHANTAB_ENT(64, 5320),
+       CHANTAB_ENT(149, 5745),
+       CHANTAB_ENT(153, 5765),
+       CHANTAB_ENT(157, 5785),
+       CHANTAB_ENT(161, 5805),
+       CHANTAB_ENT(165, 5825),
+};
+#define bcm43xx_a_chantable_size       ARRAY_SIZE(bcm43xx_a_chantable)
+
+
+static void bcm43xx_wireless_core_exit(struct bcm43xx_wldev *dev);
+static int bcm43xx_wireless_core_init(struct bcm43xx_wldev *dev);
+static void bcm43xx_wireless_core_stop(struct bcm43xx_wldev *dev);
+static int bcm43xx_wireless_core_start(struct bcm43xx_wldev *dev);
+
+
+static void bcm43xx_ram_write(struct bcm43xx_wldev *dev, u16 offset, u32 val)
+{
+       u32 status;
+
+       assert(offset % 4 == 0);
+
+       status = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD);
+       if (status & BCM43xx_SBF_XFER_REG_BYTESWAP)
+               val = swab32(val);
+
+       bcm43xx_write32(dev, BCM43xx_MMIO_RAM_CONTROL, offset);
+       mmiowb();
+       bcm43xx_write32(dev, BCM43xx_MMIO_RAM_DATA, val);
+}
+
+static inline
+void bcm43xx_shm_control_word(struct bcm43xx_wldev *dev,
+                             u16 routing, u16 offset)
+{
+       u32 control;
+
+       /* "offset" is the WORD offset. */
+
+       control = routing;
+       control <<= 16;
+       control |= offset;
+       bcm43xx_write32(dev, BCM43xx_MMIO_SHM_CONTROL, control);
+}
+
+u32 bcm43xx_shm_read32(struct bcm43xx_wldev *dev,
+                      u16 routing, u16 offset)
+{
+       u32 ret;
+
+       if (routing == BCM43xx_SHM_SHARED) {
+               assert((offset & 0x0001) == 0);
+               if (offset & 0x0003) {
+                       /* Unaligned access */
+                       bcm43xx_shm_control_word(dev, routing, offset >> 2);
+                       ret = bcm43xx_read16(dev,
+                                            BCM43xx_MMIO_SHM_DATA_UNALIGNED);
+                       ret <<= 16;
+                       bcm43xx_shm_control_word(dev, routing, (offset >> 2) + 1);
+                       ret |= bcm43xx_read16(dev,
+                                             BCM43xx_MMIO_SHM_DATA);
+
+                       return ret;
+               }
+               offset >>= 2;
+       }
+       bcm43xx_shm_control_word(dev, routing, offset);
+       ret = bcm43xx_read32(dev, BCM43xx_MMIO_SHM_DATA);
+
+       return ret;
+}
+
+u16 bcm43xx_shm_read16(struct bcm43xx_wldev *dev,
+                      u16 routing, u16 offset)
+{
+       u16 ret;
+
+       if (routing == BCM43xx_SHM_SHARED) {
+               assert((offset & 0x0001) == 0);
+               if (offset & 0x0003) {
+                       /* Unaligned access */
+                       bcm43xx_shm_control_word(dev, routing, offset >> 2);
+                       ret = bcm43xx_read16(dev,
+                                            BCM43xx_MMIO_SHM_DATA_UNALIGNED);
+
+                       return ret;
+               }
+               offset >>= 2;
+       }
+       bcm43xx_shm_control_word(dev, routing, offset);
+       ret = bcm43xx_read16(dev, BCM43xx_MMIO_SHM_DATA);
+
+       return ret;
+}
+
+void bcm43xx_shm_write32(struct bcm43xx_wldev *dev,
+                        u16 routing, u16 offset,
+                        u32 value)
+{
+       if (routing == BCM43xx_SHM_SHARED) {
+               assert((offset & 0x0001) == 0);
+               if (offset & 0x0003) {
+                       /* Unaligned access */
+                       bcm43xx_shm_control_word(dev, routing, offset >> 2);
+                       mmiowb();
+                       bcm43xx_write16(dev, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
+                                       (value >> 16) & 0xffff);
+                       mmiowb();
+                       bcm43xx_shm_control_word(dev, routing, (offset >> 2) + 1);
+                       mmiowb();
+                       bcm43xx_write16(dev, BCM43xx_MMIO_SHM_DATA,
+                                       value & 0xffff);
+                       return;
+               }
+               offset >>= 2;
+       }
+       bcm43xx_shm_control_word(dev, routing, offset);
+       mmiowb();
+       bcm43xx_write32(dev, BCM43xx_MMIO_SHM_DATA, value);
+}
+
+void bcm43xx_shm_write16(struct bcm43xx_wldev *dev,
+                        u16 routing, u16 offset,
+                        u16 value)
+{
+       if (routing == BCM43xx_SHM_SHARED) {
+               assert((offset & 0x0001) == 0);
+               if (offset & 0x0003) {
+                       /* Unaligned access */
+                       bcm43xx_shm_control_word(dev, routing, offset >> 2);
+                       mmiowb();
+                       bcm43xx_write16(dev, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
+                                       value);
+                       return;
+               }
+               offset >>= 2;
+       }
+       bcm43xx_shm_control_word(dev, routing, offset);
+       mmiowb();
+       bcm43xx_write16(dev, BCM43xx_MMIO_SHM_DATA, value);
+}
+
+/* Read HostFlags */
+u32 bcm43xx_hf_read(struct bcm43xx_wldev *dev)
+{
+       u32 ret;
+
+       ret = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
+                                BCM43xx_SHM_SH_HOSTFHI);
+       ret <<= 16;
+       ret |= bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
+                                 BCM43xx_SHM_SH_HOSTFLO);
+
+       return ret;
+}
+
+/* Write HostFlags */
+void bcm43xx_hf_write(struct bcm43xx_wldev *dev, u32 value)
+{
+       bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
+                           BCM43xx_SHM_SH_HOSTFLO,
+                           (value & 0x0000FFFF));
+       bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
+                           BCM43xx_SHM_SH_HOSTFHI,
+                           ((value & 0xFFFF0000) >> 16));
+}
+
+void bcm43xx_tsf_read(struct bcm43xx_wldev *dev, u64 *tsf)
+{
+       /* We need to be careful. As we read the TSF from multiple
+        * registers, we should take care of register overflows.
+        * In theory, the whole tsf read process should be atomic.
+        * We try to be atomic here, by restaring the read process,
+        * if any of the high registers changed (overflew).
+        */
+       if (dev->dev->id.revision >= 3) {
+               u32 low, high, high2;
+
+               do {
+                       high = bcm43xx_read32(dev, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
+                       low = bcm43xx_read32(dev, BCM43xx_MMIO_REV3PLUS_TSF_LOW);
+                       high2 = bcm43xx_read32(dev, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
+               } while (unlikely(high != high2));
+
+               *tsf = high;
+               *tsf <<= 32;
+               *tsf |= low;
+       } else {
+               u64 tmp;
+               u16 v0, v1, v2, v3;
+               u16 test1, test2, test3;
+
+               do {
+                       v3 = bcm43xx_read16(dev, BCM43xx_MMIO_TSF_3);
+                       v2 = bcm43xx_read16(dev, BCM43xx_MMIO_TSF_2);
+                       v1 = bcm43xx_read16(dev, BCM43xx_MMIO_TSF_1);
+                       v0 = bcm43xx_read16(dev, BCM43xx_MMIO_TSF_0);
+
+                       test3 = bcm43xx_read16(dev, BCM43xx_MMIO_TSF_3);
+                       test2 = bcm43xx_read16(dev, BCM43xx_MMIO_TSF_2);
+                       test1 = bcm43xx_read16(dev, BCM43xx_MMIO_TSF_1);
+               } while (v3 != test3 || v2 != test2 || v1 != test1);
+
+               *tsf = v3;
+               *tsf <<= 48;
+               tmp = v2;
+               tmp <<= 32;
+               *tsf |= tmp;
+               tmp = v1;
+               tmp <<= 16;
+               *tsf |= tmp;
+               *tsf |= v0;
+       }
+}
+
+static void bcm43xx_time_lock(struct bcm43xx_wldev *dev)
+{
+       u32 status;
+
+       status = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD);
+       status |= BCM43xx_SBF_TIME_UPDATE;
+       bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD, status);
+       mmiowb();
+}
+
+static void bcm43xx_time_unlock(struct bcm43xx_wldev *dev)
+{
+       u32 status;
+
+       status = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD);
+       status &= ~BCM43xx_SBF_TIME_UPDATE;
+       bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD, status);
+}
+
+static void bcm43xx_tsf_write_locked(struct bcm43xx_wldev *dev, u64 tsf)
+{
+       /* Be careful with the in-progress timer.
+        * First zero out the low register, so we have a full
+        * register-overflow duration to complete the operation.
+        */
+       if (dev->dev->id.revision >= 3) {
+               u32 lo = (tsf & 0x00000000FFFFFFFFULL);
+               u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
+
+               bcm43xx_write32(dev, BCM43xx_MMIO_REV3PLUS_TSF_LOW, 0);
+               mmiowb();
+               bcm43xx_write32(dev, BCM43xx_MMIO_REV3PLUS_TSF_HIGH, hi);
+               mmiowb();
+               bcm43xx_write32(dev, BCM43xx_MMIO_REV3PLUS_TSF_LOW, lo);
+       } else {
+               u16 v0 = (tsf & 0x000000000000FFFFULL);
+               u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
+               u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
+               u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
+
+               bcm43xx_write16(dev, BCM43xx_MMIO_TSF_0, 0);
+               mmiowb();
+               bcm43xx_write16(dev, BCM43xx_MMIO_TSF_3, v3);
+               mmiowb();
+               bcm43xx_write16(dev, BCM43xx_MMIO_TSF_2, v2);
+               mmiowb();
+               bcm43xx_write16(dev, BCM43xx_MMIO_TSF_1, v1);
+               mmiowb();
+               bcm43xx_write16(dev, BCM43xx_MMIO_TSF_0, v0);
+       }
+}
+
+void bcm43xx_tsf_write(struct bcm43xx_wldev *dev, u64 tsf)
+{
+       bcm43xx_time_lock(dev);
+       bcm43xx_tsf_write_locked(dev, tsf);
+       bcm43xx_time_unlock(dev);
+}
+
+static void bcm43xx_measure_channel_change_time(struct bcm43xx_wldev *dev)
+{
+       u64 start, stop;
+       unsigned long flags;
+       u8 oldchan, testchan;
+
+       /* We (ab)use the bcm43xx TSF timer to measure the time needed
+        * to switch channels. This information is handed over to
+        * the ieee80211 subsystem.
+        * Time is measured in microseconds.
+        */
+
+       spin_lock_irqsave(&dev->wl->irq_lock, flags);
+       oldchan = dev->phy.channel;
+       testchan = (oldchan == 6) ? 7 : 6;
+       bcm43xx_tsf_read(dev, &start);
+       bcm43xx_radio_selectchannel(dev, testchan, 0);
+       bcm43xx_tsf_read(dev, &stop);
+       bcm43xx_radio_selectchannel(dev, oldchan, 0);
+       spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
+
+       assert(stop > start);
+       dev->wl->hw->channel_change_time = stop - start;
+}
+
+static
+void bcm43xx_macfilter_set(struct bcm43xx_wldev *dev,
+                          u16 offset,
+                          const u8 *mac)
+{
+       u16 data;
+
+       offset |= 0x0020;
+       bcm43xx_write16(dev, BCM43xx_MMIO_MACFILTER_CONTROL, offset);
+
+       data = mac[0];
+       data |= mac[1] << 8;
+       bcm43xx_write16(dev, BCM43xx_MMIO_MACFILTER_DATA, data);
+       data = mac[2];
+       data |= mac[3] << 8;
+       bcm43xx_write16(dev, BCM43xx_MMIO_MACFILTER_DATA, data);
+       data = mac[4];
+       data |= mac[5] << 8;
+       bcm43xx_write16(dev, BCM43xx_MMIO_MACFILTER_DATA, data);
+}
+
+static void bcm43xx_macfilter_clear(struct bcm43xx_wldev *dev,
+                                   u16 offset)
+{
+       static const u8 zero_addr[ETH_ALEN] = { 0 };
+
+       bcm43xx_macfilter_set(dev, offset, zero_addr);
+}
+
+static void bcm43xx_write_mac_bssid_templates(struct bcm43xx_wldev *dev)
+{
+       static const u8 zero_addr[ETH_ALEN] = { 0 };
+       const u8 *mac;
+       const u8 *bssid;
+       u8 mac_bssid[ETH_ALEN * 2];
+       int i;
+       u32 tmp;
+
+       bssid = dev->wl->bssid;
+       if (!bssid)
+               bssid = zero_addr;
+       mac = dev->wl->mac_addr;
+       if (!mac)
+               mac = zero_addr;
+
+       memcpy(mac_bssid, mac, ETH_ALEN);
+       memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
+
+       /* Write our MAC address and BSSID to template ram */
+       for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
+               tmp =  (u32)(mac_bssid[i + 0]);
+               tmp |= (u32)(mac_bssid[i + 1]) << 8;
+               tmp |= (u32)(mac_bssid[i + 2]) << 16;
+               tmp |= (u32)(mac_bssid[i + 3]) << 24;
+               bcm43xx_ram_write(dev, 0x20 + i, tmp);
+       }
+}
+
+static void bcm43xx_set_slot_time(struct bcm43xx_wldev *dev, u16 slot_time)
+{
+       /* slot_time is in usec. */
+       if (dev->phy.type != BCM43xx_PHYTYPE_G)
+               return;
+       bcm43xx_write16(dev, 0x684, 510 + slot_time);
+       bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x0010, slot_time);
+}
+
+static void bcm43xx_short_slot_timing_enable(struct bcm43xx_wldev *dev)
+{
+       bcm43xx_set_slot_time(dev, 9);
+       dev->short_slot = 1;
+}
+
+static void bcm43xx_short_slot_timing_disable(struct bcm43xx_wldev *dev)
+{
+       bcm43xx_set_slot_time(dev, 20);
+       dev->short_slot = 0;
+}
+
+/* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
+ * Returns the _previously_ enabled IRQ mask.
+ */
+static inline u32 bcm43xx_interrupt_enable(struct bcm43xx_wldev *dev, u32 mask)
+{
+       u32 old_mask;
+
+       old_mask = bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_MASK);
+       bcm43xx_write32(dev, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask | mask);
+
+       return old_mask;
+}
+
+/* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
+ * Returns the _previously_ enabled IRQ mask.
+ */
+static inline u32 bcm43xx_interrupt_disable(struct bcm43xx_wldev *dev, u32 mask)
+{
+       u32 old_mask;
+
+       old_mask = bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_MASK);
+       bcm43xx_write32(dev, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
+
+       return old_mask;
+}
+
+/* Synchronize IRQ top- and bottom-half.
+ * IRQs must be masked before calling this.
+ * This must not be called with the irq_lock held.
+ */
+static void bcm43xx_synchronize_irq(struct bcm43xx_wldev *dev)
+{
+       synchronize_irq(dev->dev->irq);
+       tasklet_kill(&dev->isr_tasklet);
+}
+
+/* DummyTransmission function, as documented on
+ * http://bcm-specs.sipsolutions.net/DummyTransmission
+ */
+void bcm43xx_dummy_transmission(struct bcm43xx_wldev *dev)
+{
+       struct bcm43xx_phy *phy = &dev->phy;
+       unsigned int i, max_loop;
+       u16 value;
+       u32 buffer[5] = {
+               0x00000000,
+               0x00D40000,
+               0x00000000,
+               0x01000000,
+               0x00000000,
+       };
+
+       switch (phy->type) {
+       case BCM43xx_PHYTYPE_A:
+               max_loop = 0x1E;
+               buffer[0] = 0x000201CC;
+               break;
+       case BCM43xx_PHYTYPE_B:
+       case BCM43xx_PHYTYPE_G:
+               max_loop = 0xFA;
+               buffer[0] = 0x000B846E;
+               break;
+       default:
+               assert(0);
+               return;
+       }
+
+       for (i = 0; i < 5; i++)
+               bcm43xx_ram_write(dev, i * 4, buffer[i]);
+
+       bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
+
+       bcm43xx_write16(dev, 0x0568, 0x0000);
+       bcm43xx_write16(dev, 0x07C0, 0x0000);
+       value = ((phy->type == BCM43xx_PHYTYPE_A) ? 1 : 0);
+       bcm43xx_write16(dev, 0x050C, value);
+       bcm43xx_write16(dev, 0x0508, 0x0000);
+       bcm43xx_write16(dev, 0x050A, 0x0000);
+       bcm43xx_write16(dev, 0x054C, 0x0000);
+       bcm43xx_write16(dev, 0x056A, 0x0014);
+       bcm43xx_write16(dev, 0x0568, 0x0826);
+       bcm43xx_write16(dev, 0x0500, 0x0000);
+       bcm43xx_write16(dev, 0x0502, 0x0030);
+
+       if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
+               bcm43xx_radio_write16(dev, 0x0051, 0x0017);
+       for (i = 0x00; i < max_loop; i++) {
+               value = bcm43xx_read16(dev, 0x050E);
+               if (value & 0x0080)
+                       break;
+               udelay(10);
+       }
+       for (i = 0x00; i < 0x0A; i++) {
+               value = bcm43xx_read16(dev, 0x050E);
+               if (value & 0x0400)
+                       break;
+               udelay(10);
+       }
+       for (i = 0x00; i < 0x0A; i++) {
+               value = bcm43xx_read16(dev, 0x0690);
+               if (!(value & 0x0100))
+                       break;
+               udelay(10);
+       }
+       if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
+               bcm43xx_radio_write16(dev, 0x0051, 0x0037);
+}
+
+static void key_write(struct bcm43xx_wldev *dev,
+                     u8 index, u8 algorithm, const u8 *key)
+{
+       unsigned int i;
+       u32 offset;
+       u16 value;
+       u16 kidx;
+
+       /* Key index/algo block */
+       kidx = bcm43xx_kidx_to_fw(dev, index);
+       value = ((kidx << 4) | algorithm);
+       bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
+                           BCM43xx_SHM_SH_KEYIDXBLOCK +
+                           (kidx * 2), value);
+
+       /* Write the key to the Key Table Pointer offset */
+       offset = dev->ktp + (index * BCM43xx_SEC_KEYSIZE);
+       for (i = 0; i < BCM43xx_SEC_KEYSIZE; i += 2) {
+               value = key[i];
+               value |= (u16)(key[i + 1]) << 8;
+               bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
+                                   offset + i, value);
+       }
+}
+
+static void keymac_write(struct bcm43xx_wldev *dev,
+                        u8 index, const u8 *addr)
+{
+       u32 addrtmp[2];
+
+       assert(index >= 4 + 4);
+       memcpy(dev->key[index].address, addr, 6);
+       /* We have two default TX keys and two default RX keys.
+        * Physical mac 0 is mapped to physical key 8.
+        * So we must adjust the index here.
+        */
+       index -= 8;
+
+       addrtmp[0] = addr[0];
+       addrtmp[0] |= ((u32)(addr[1]) << 8);
+       addrtmp[0] |= ((u32)(addr[2]) << 16);
+       addrtmp[0] |= ((u32)(addr[3]) << 24);
+       addrtmp[1] = addr[4];
+       addrtmp[1] |= ((u32)(addr[5]) << 8);
+
+       if (dev->dev->id.revision >= 5) {
+               /* Receive match transmitter address mechanism */
+               bcm43xx_shm_write32(dev, BCM43xx_SHM_RCMTA,
+                                   (index * 2) + 0, addrtmp[0]);
+               bcm43xx_shm_write16(dev, BCM43xx_SHM_RCMTA,
+                                   (index * 2) + 1, addrtmp[1]);
+       } else {
+               /* RXE (Receive Engine) and
+                * PSM (Programmable State Machine) mechanism
+                */
+               if (index < 8) {
+                       /* TODO write to RCM 16, 19, 22 and 25 */
+                       TODO();
+               } else {
+                       bcm43xx_shm_write32(dev, BCM43xx_SHM_SHARED,
+                                           BCM43xx_SHM_SH_PSM + (index * 6) + 0,
+                                           addrtmp[0]);
+                       bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
+                                           BCM43xx_SHM_SH_PSM + (index * 6) + 4,
+                                           addrtmp[1]);
+               }
+       }
+}
+
+static void do_key_write(struct bcm43xx_wldev *dev,
+                        u8 index, u8 algorithm,
+                        const u8 *key, size_t key_len,
+                        const u8 *mac_addr)
+{
+       u8 buf[BCM43xx_SEC_KEYSIZE];
+
+       assert(index < dev->max_nr_keys);
+       assert(key_len <= BCM43xx_SEC_KEYSIZE);
+
+       memset(buf, 0, sizeof(buf));
+       if (index >= 8)
+               keymac_write(dev, index, buf); /* First zero out mac. */
+       memcpy(buf, key, key_len);
+       key_write(dev, index, algorithm, buf);
+       if (index >= 8)
+               keymac_write(dev, index, mac_addr);
+
+       dev->key[index].algorithm = algorithm;
+}
+
+static int bcm43xx_key_write(struct bcm43xx_wldev *dev,
+                            int index, u8 algorithm,
+                            const u8 *key, size_t key_len,
+                            const u8 *mac_addr,
+                            struct ieee80211_key_conf *keyconf)
+{
+       int i;
+       int sta_keys_start;
+
+       if (key_len > BCM43xx_SEC_KEYSIZE)
+               return -EINVAL;
+       if (index < 0) {
+               /* Per station key with associated MAC address.
+                * Look if it already exists, if yes update, otherwise
+                * allocate a new key.
+                */
+               if (bcm43xx_new_kidx_api(dev))
+                       sta_keys_start = 4;
+               else
+                       sta_keys_start = 8;
+               for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
+                       if (compare_ether_addr(dev->key[i].address, mac_addr) == 0) {
+                               /* found existing */
+                               index = i;
+                               break;
+                       }
+               }
+               if (index < 0) {
+                       for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
+                               if (!dev->key[i].enabled) {
+                                       /* found empty */
+                                       index = i;
+                                       break;
+                               }
+                       }
+               }
+               if (index < 0) {
+                       dprintk(KERN_ERR PFX "Out of hw key memory\n");
+                       return -ENOBUFS;
+               }
+       } else
+               assert(index <= 3);
+
+       do_key_write(dev, index, algorithm, key, key_len, mac_addr);
+       if ((index <= 3) && !bcm43xx_new_kidx_api(dev)) {
+               /* Default RX key */
+               assert(mac_addr == NULL);
+               do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
+       }
+       keyconf->hw_key_idx = index;
+
+       return 0;
+}
+
+static void bcm43xx_clear_keys(struct bcm43xx_wldev *dev)
+{
+       static const u8 zero[BCM43xx_SEC_KEYSIZE] = { 0 };
+       unsigned int i;
+
+       BUILD_BUG_ON(BCM43xx_SEC_KEYSIZE < ETH_ALEN);
+       for (i = 0; i < dev->max_nr_keys; i++) {
+               do_key_write(dev, i, BCM43xx_SEC_ALGO_NONE,
+                            zero, BCM43xx_SEC_KEYSIZE,
+                            zero);
+               dev->key[i].enabled = 0;
+       }
+}
+
+/* Turn the Analog ON/OFF */
+static void bcm43xx_switch_analog(struct bcm43xx_wldev *dev, int on)
+{
+       bcm43xx_write16(dev, BCM43xx_MMIO_PHY0, on ? 0 : 0xF4);
+}
+
+void bcm43xx_wireless_core_reset(struct bcm43xx_wldev *dev, u32 flags)
+{
+       u32 tmslow;
+       u32 macctl;
+
+       flags |= BCM43xx_TMSLOW_PHYCLKEN;
+       flags |= BCM43xx_TMSLOW_PHYRESET;
+       ssb_device_enable(dev->dev, flags);
+       msleep(2); /* Wait for the PLL to turn on. */
+
+       /* Now take the PHY out of Reset again */
+       tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
+       tmslow |= SSB_TMSLOW_FGC;
+       tmslow &= ~BCM43xx_TMSLOW_PHYRESET;
+       ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
+       ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
+       msleep(1);
+       tmslow &= ~SSB_TMSLOW_FGC;
+       ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
+       ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
+       msleep(1);
+
+       /* Turn Analog ON */
+       bcm43xx_switch_analog(dev, 1);
+
+       macctl = bcm43xx_read32(dev, BCM43xx_MMIO_MACCTL);
+       macctl &= ~BCM43xx_MACCTL_GMODE;
+       if (flags & BCM43xx_TMSLOW_GMODE)
+               macctl |= BCM43xx_MACCTL_GMODE;
+       macctl |= BCM43xx_MACCTL_IHR_ENABLED;
+       bcm43xx_write32(dev, BCM43xx_MMIO_MACCTL, macctl);
+}
+
+static void handle_irq_transmit_status(struct bcm43xx_wldev *dev)
+{
+       u32 v0, v1;
+       u16 tmp;
+       struct bcm43xx_txstatus stat;
+
+       while (1) {
+               v0 = bcm43xx_read32(dev, BCM43xx_MMIO_XMITSTAT_0);
+               if (!(v0 & 0x00000001))
+                       break;
+               v1 = bcm43xx_read32(dev, BCM43xx_MMIO_XMITSTAT_1);
+
+               stat.cookie = (v0 >> 16);
+               stat.seq = (v1 & 0x0000FFFF);
+               stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
+               tmp = (v0 & 0x0000FFFF);
+               stat.frame_count = ((tmp & 0xF000) >> 12);
+               stat.rts_count = ((tmp & 0x0F00) >> 8);
+               stat.supp_reason = ((tmp & 0x001C) >> 2);
+               stat.pm_indicated = !!(tmp & 0x0080);
+               stat.intermediate = !!(tmp & 0x0040);
+               stat.for_ampdu = !!(tmp & 0x0020);
+               stat.acked = !!(tmp & 0x0002);
+
+               bcm43xx_handle_txstatus(dev, &stat);
+       }
+}
+
+static void drain_txstatus_queue(struct bcm43xx_wldev *dev)
+{
+       u32 dummy;
+
+       if (dev->dev->id.revision < 5)
+               return;
+       /* Read all entries from the microcode TXstatus FIFO
+        * and throw them away.
+        */
+       while (1) {
+               dummy = bcm43xx_read32(dev, BCM43xx_MMIO_XMITSTAT_0);
+               if (!(dummy & 0x00000001))
+                       break;
+               dummy = bcm43xx_read32(dev, BCM43xx_MMIO_XMITSTAT_1);
+       }
+}
+
+static u32 bcm43xx_jssi_read(struct bcm43xx_wldev *dev)
+{
+       u32 val = 0;
+
+       val = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED, 0x08A);
+       val <<= 16;
+       val |= bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED, 0x088);
+
+       return val;
+}
+
+static void bcm43xx_jssi_write(struct bcm43xx_wldev *dev, u32 jssi)
+{
+       bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x088,
+                           (jssi & 0x0000FFFF));
+       bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x08A,
+                           (jssi & 0xFFFF0000) >> 16);
+}
+
+static void bcm43xx_generate_noise_sample(struct bcm43xx_wldev *dev)
+{
+       bcm43xx_jssi_write(dev, 0x7F7F7F7F);
+       bcm43xx_write32(dev, BCM43xx_MMIO_STATUS2_BITFIELD,
+                       bcm43xx_read32(dev, BCM43xx_MMIO_STATUS2_BITFIELD)
+                       | (1 << 4));
+       assert(dev->noisecalc.channel_at_start == dev->phy.channel);
+}
+
+static void bcm43xx_calculate_link_quality(struct bcm43xx_wldev *dev)
+{
+       /* Top half of Link Quality calculation. */
+
+       if (dev->noisecalc.calculation_running)
+               return;
+       dev->noisecalc.channel_at_start = dev->phy.channel;
+       dev->noisecalc.calculation_running = 1;
+       dev->noisecalc.nr_samples = 0;
+
+       bcm43xx_generate_noise_sample(dev);
+}
+
+static void handle_irq_noise(struct bcm43xx_wldev *dev)
+{
+       struct bcm43xx_phy *phy = &dev->phy;
+       u16 tmp;
+       u8 noise[4];
+       u8 i, j;
+       s32 average;
+
+       /* Bottom half of Link Quality calculation. */
+
+       assert(dev->noisecalc.calculation_running);
+       if (dev->noisecalc.channel_at_start != phy->channel)
+               goto drop_calculation;
+       *((u32 *)noise) = cpu_to_le32(bcm43xx_jssi_read(dev));
+       if (noise[0] == 0x7F || noise[1] == 0x7F ||
+           noise[2] == 0x7F || noise[3] == 0x7F)
+               goto generate_new;
+
+       /* Get the noise samples. */
+       assert(dev->noisecalc.nr_samples < 8);
+       i = dev->noisecalc.nr_samples;
+       noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
+       noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
+       noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
+       noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
+       dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
+       dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
+       dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
+       dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
+       dev->noisecalc.nr_samples++;
+       if (dev->noisecalc.nr_samples == 8) {
+               /* Calculate the Link Quality by the noise samples. */
+               average = 0;
+               for (i = 0; i < 8; i++) {
+                       for (j = 0; j < 4; j++)
+                               average += dev->noisecalc.samples[i][j];
+               }
+               average /= (8 * 4);
+               average *= 125;
+               average += 64;
+               average /= 128;
+               tmp = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED, 0x40C);
+               tmp = (tmp / 128) & 0x1F;
+               if (tmp >= 8)
+                       average += 2;
+               else
+                       average -= 25;
+               if (tmp == 8)
+                       average -= 72;
+               else
+                       average -= 48;
+
+               dev->stats.link_noise = average;
+drop_calculation:
+               dev->noisecalc.calculation_running = 0;
+               return;
+       }
+generate_new:
+       bcm43xx_generate_noise_sample(dev);
+}
+
+static void handle_irq_tbtt_indication(struct bcm43xx_wldev *dev)
+{
+       if (bcm43xx_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
+               ///TODO: PS TBTT
+       } else {
+               if (1/*FIXME: the last PSpoll frame was sent successfully */)
+                       bcm43xx_power_saving_ctl_bits(dev, -1, -1);
+       }
+       dev->reg124_set_0x4 = 0;
+       if (bcm43xx_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
+               dev->reg124_set_0x4 = 1;
+}
+
+static void handle_irq_atim_end(struct bcm43xx_wldev *dev)
+{
+       if (!dev->reg124_set_0x4 /*FIXME rename this variable*/)
+               return;
+       bcm43xx_write32(dev, BCM43xx_MMIO_STATUS2_BITFIELD,
+                       bcm43xx_read32(dev, BCM43xx_MMIO_STATUS2_BITFIELD)
+                       | 0x4);
+}
+
+static void handle_irq_pmq(struct bcm43xx_wldev *dev)
+{
+       u32 tmp;
+
+       //TODO: AP mode.
+
+       while (1) {
+               tmp = bcm43xx_read32(dev, BCM43xx_MMIO_PS_STATUS);
+               if (!(tmp & 0x00000008))
+                       break;
+       }
+       /* 16bit write is odd, but correct. */
+       bcm43xx_write16(dev, BCM43xx_MMIO_PS_STATUS, 0x0002);
+}
+
+static void bcm43xx_write_template_common(struct bcm43xx_wldev *dev,
+                                         const u8* data, u16 size,
+                                         u16 ram_offset,
+                                         u16 shm_size_offset, u8 rate)
+{
+       u32 i, tmp;
+       struct bcm43xx_plcp_hdr4 plcp;
+
+       plcp.data = 0;
+       bcm43xx_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
+       bcm43xx_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
+       ram_offset += sizeof(u32);
+       /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
+        * So leave the first two bytes of the next write blank.
+        */
+       tmp = (u32)(data[0]) << 16;
+       tmp |= (u32)(data[1]) << 24;
+       bcm43xx_ram_write(dev, ram_offset, tmp);
+       ram_offset += sizeof(u32);
+       for (i = 2; i < size; i += sizeof(u32)) {
+               tmp = (u32)(data[i + 0]);
+               if (i + 1 < size)
+                       tmp |= (u32)(data[i + 1]) << 8;
+               if (i + 2 < size)
+                       tmp |= (u32)(data[i + 2]) << 16;
+               if (i + 3 < size)
+                       tmp |= (u32)(data[i + 3]) << 24;
+               bcm43xx_ram_write(dev, ram_offset + i - 2, tmp);
+       }
+       bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, shm_size_offset,
+                           size + sizeof(struct bcm43xx_plcp_hdr6));
+}
+
+static void bcm43xx_write_beacon_template(struct bcm43xx_wldev *dev,
+                                         u16 ram_offset,
+                                         u16 shm_size_offset, u8 rate)
+{
+       int len;
+       const u8 *data;
+
+       assert(dev->cached_beacon);
+       len = min((size_t)dev->cached_beacon->len,
+                 0x200 - sizeof(struct bcm43xx_plcp_hdr6));
+       data = (const u8 *)(dev->cached_beacon->data);
+       bcm43xx_write_template_common(dev, data,
+                                     len, ram_offset,
+                                     shm_size_offset, rate);
+}
+
+static void bcm43xx_write_probe_resp_plcp(struct bcm43xx_wldev *dev,
+                                         u16 shm_offset, u16 size, u8 rate)
+{
+       struct bcm43xx_plcp_hdr4 plcp;
+       u32 tmp;
+       u16 packet_time;
+
+       plcp.data = 0;
+       bcm43xx_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
+       /*
+        * 144 + 48 + 10 = preamble + PLCP + SIFS,
+        * taken from mac80211 timings calculation.
+        *
+        * FIXME: long preamble assumed!
+        *
+        */
+       packet_time = 202 + (size + FCS_LEN) * 16 / rate;
+       if ((size + FCS_LEN) * 16 % rate >= rate / 2)
+               ++packet_time;
+
+       /* Write PLCP in two parts and timing for packet transfer */
+       tmp = le32_to_cpu(plcp.data);
+       bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, shm_offset,
+                           tmp & 0xFFFF);
+       bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, shm_offset + 2,
+                           tmp >> 16);
+       bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, shm_offset + 6,
+                           packet_time);
+}
+
+/* Instead of using custom probe response template, this function
+ * just patches custom beacon template by:
+ * 1) Changing packet type
+ * 2) Patching duration field
+ * 3) Stripping TIM
+ */
+static u8 * bcm43xx_generate_probe_resp(struct bcm43xx_wldev *dev,
+                                       u16* dest_size, u8 rate)
+{
+       const u8 *src_data;
+       u8 *dest_data;
+       u16 src_size, elem_size, src_pos, dest_pos, tmp;
+
+       assert(dev->cached_beacon);
+       src_size = dev->cached_beacon->len;
+       src_data = (const u8*)dev->cached_beacon->data;
+
+       if (unlikely(src_size < 0x24)) {
+               dprintk(KERN_ERR PFX "bcm43xx_generate_probe_resp: "
+                                    "invalid beacon\n");
+               return NULL;
+       }
+
+       dest_data = kmalloc(src_size, GFP_ATOMIC);
+       if (unlikely(!dest_data))
+               return NULL;
+
+       /* 0x24 is offset of first variable-len Information-Element
+        * in beacon frame.
+        */
+       memcpy(dest_data, src_data, 0x24);
+       src_pos = dest_pos = 0x24;
+       for ( ; src_pos < src_size - 2; src_pos += elem_size) {
+               elem_size = src_data[src_pos + 1] + 2;
+               if (src_data[src_pos] != 0x05) { /* TIM */
+                       memcpy(dest_data + dest_pos, src_data + src_pos,
+                              elem_size);
+                       dest_pos += elem_size;
+               }
+       }
+       *dest_size = dest_pos;
+
+       /* Set the frame control. */
+       dest_data[0] = (IEEE80211_FTYPE_MGMT |
+                       IEEE80211_STYPE_PROBE_RESP);
+       dest_data[1] = 0;
+
+       /* Set the duration field.
+        *
+        * 144 + 48 + 10 = preamble + PLCP + SIFS,
+        * taken from mac80211 timings calculation.
+        *
+        * FIXME: long preamble assumed!
+        *
+        */
+       tmp = 202 + (14 + FCS_LEN) * 16 / rate;
+       if ((14 + FCS_LEN) * 16 % rate >= rate / 2)
+               ++tmp;
+
+       dest_data[2] = tmp & 0xFF;
+       dest_data[3] = (tmp >> 8) & 0xFF;
+
+       return dest_data;
+}
+
+static void bcm43xx_write_probe_resp_template(struct bcm43xx_wldev *dev,
+                                             u16 ram_offset,
+                                             u16 shm_size_offset, u8 rate)
+{
+       u8* probe_resp_data;
+       u16 size;
+
+       assert(dev->cached_beacon);
+       size = dev->cached_beacon->len;
+       probe_resp_data = bcm43xx_generate_probe_resp(dev, &size, rate);
+       if (unlikely(!probe_resp_data))
+               return;
+
+       /* Looks like PLCP headers plus packet timings are stored for
+        * all possible basic rates
+        */
+       bcm43xx_write_probe_resp_plcp(dev, 0x31A, size,
+                                     BCM43xx_CCK_RATE_1MB);
+       bcm43xx_write_probe_resp_plcp(dev, 0x32C, size,
+                                     BCM43xx_CCK_RATE_2MB);
+       bcm43xx_write_probe_resp_plcp(dev, 0x33E, size,
+                                     BCM43xx_CCK_RATE_5MB);
+       bcm43xx_write_probe_resp_plcp(dev, 0x350, size,
+                                     BCM43xx_CCK_RATE_11MB);
+
+       size = min((size_t)size,
+                  0x200 - sizeof(struct bcm43xx_plcp_hdr6));
+       bcm43xx_write_template_common(dev, probe_resp_data,
+                                     size, ram_offset,
+                                     shm_size_offset, rate);
+       kfree(probe_resp_data);
+}
+
+static int bcm43xx_refresh_cached_beacon(struct bcm43xx_wldev *dev,
+                                        struct sk_buff *beacon)
+{
+       if (dev->cached_beacon)
+               kfree_skb(dev->cached_beacon);
+       dev->cached_beacon = beacon;
+
+       return 0;
+}
+
+static void bcm43xx_update_templates(struct bcm43xx_wldev *dev)
+{
+       u32 status;
+
+       assert(dev->cached_beacon);
+
+       bcm43xx_write_beacon_template(dev, 0x68, 0x18,
+                                     BCM43xx_CCK_RATE_1MB);
+       bcm43xx_write_beacon_template(dev, 0x468, 0x1A,
+                                     BCM43xx_CCK_RATE_1MB);
+       bcm43xx_write_probe_resp_template(dev, 0x268, 0x4A,
+                                         BCM43xx_CCK_RATE_11MB);
+
+       status = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS2_BITFIELD);
+       status |= 0x03;
+       bcm43xx_write32(dev, BCM43xx_MMIO_STATUS2_BITFIELD, status);
+}
+
+static void bcm43xx_refresh_templates(struct bcm43xx_wldev *dev,
+                                     struct sk_buff *beacon)
+{
+       int err;
+
+       err = bcm43xx_refresh_cached_beacon(dev, beacon);
+       if (unlikely(err))
+               return;
+       bcm43xx_update_templates(dev);
+}
+
+static void bcm43xx_set_ssid(struct bcm43xx_wldev *dev,
+                            const u8 *ssid, u8 ssid_len)
+{
+       u32 tmp;
+       u16 i, len;
+
+       len = min((u16)ssid_len, (u16)0x100);
+       for (i = 0; i < len; i += sizeof(u32)) {
+               tmp = (u32)(ssid[i + 0]);
+               if (i + 1 < len)
+                       tmp |= (u32)(ssid[i + 1]) << 8;
+               if (i + 2 < len)
+                       tmp |= (u32)(ssid[i + 2]) << 16;
+               if (i + 3 < len)
+                       tmp |= (u32)(ssid[i + 3]) << 24;
+               bcm43xx_shm_write32(dev, BCM43xx_SHM_SHARED,
+                                   0x380 + i, tmp);
+       }
+       bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
+                           0x48, len);
+}
+
+static void bcm43xx_set_beacon_int(struct bcm43xx_wldev *dev, u16 beacon_int)
+{
+       bcm43xx_time_lock(dev);
+       if (dev->dev->id.revision >= 3) {
+               bcm43xx_write32(dev, 0x188, (beacon_int << 16));
+       } else {
+               bcm43xx_write16(dev, 0x606, (beacon_int >> 6));
+               bcm43xx_write16(dev, 0x610, beacon_int);
+       }
+       bcm43xx_time_unlock(dev);
+}
+
+static void handle_irq_beacon(struct bcm43xx_wldev *dev)
+{
+       u32 status;
+
+       if (!bcm43xx_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
+               return;
+
+       dev->irq_savedstate &= ~BCM43xx_IRQ_BEACON;
+       status = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS2_BITFIELD);
+
+       if (!dev->cached_beacon || ((status & 0x1) && (status & 0x2))) {
+               /* ACK beacon IRQ. */
+               bcm43xx_write32(dev, BCM43xx_MMIO_GEN_IRQ_REASON,
+                               BCM43xx_IRQ_BEACON);
+               dev->irq_savedstate |= BCM43xx_IRQ_BEACON;
+               if (dev->cached_beacon)
+                       kfree_skb(dev->cached_beacon);
+               dev->cached_beacon = NULL;
+               return;
+       }
+       if (!(status & 0x1)) {
+               bcm43xx_write_beacon_template(dev, 0x68, 0x18,
+                                             BCM43xx_CCK_RATE_1MB);
+               status |= 0x1;
+               bcm43xx_write32(dev, BCM43xx_MMIO_STATUS2_BITFIELD,
+                               status);
+       }
+       if (!(status & 0x2)) {
+               bcm43xx_write_beacon_template(dev, 0x468, 0x1A,
+                                             BCM43xx_CCK_RATE_1MB);
+               status |= 0x2;
+               bcm43xx_write32(dev, BCM43xx_MMIO_STATUS2_BITFIELD,
+                               status);
+       }
+}
+
+static void handle_irq_ucode_debug(struct bcm43xx_wldev *dev)
+{
+       //TODO
+}
+
+/* Interrupt handler bottom-half */
+static void bcm43xx_interrupt_tasklet(struct bcm43xx_wldev *dev)
+{
+       u32 reason;
+       u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
+       u32 merged_dma_reason = 0;
+       int i, activity = 0;
+       unsigned long flags;
+
+       spin_lock_irqsave(&dev->wl->irq_lock, flags);
+
+       assert(bcm43xx_status(dev) == BCM43xx_STAT_INITIALIZED);
+       assert(dev->started);
+
+       reason = dev->irq_reason;
+       for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
+               dma_reason[i] = dev->dma_reason[i];
+               merged_dma_reason |= dma_reason[i];
+       }
+
+       if (unlikely(reason & BCM43xx_IRQ_MAC_TXERR))
+               printkl(KERN_ERR PFX "MAC transmission error\n");
+
+       if (unlikely(reason & BCM43xx_IRQ_PHY_TXERR))
+               printkl(KERN_ERR PFX "PHY transmission error\n");
+
+       if (unlikely(merged_dma_reason & (BCM43xx_DMAIRQ_FATALMASK |
+                                         BCM43xx_DMAIRQ_NONFATALMASK))) {
+               if (merged_dma_reason & BCM43xx_DMAIRQ_FATALMASK) {
+                       printkl(KERN_ERR PFX "FATAL ERROR: Fatal DMA error: "
+                                            "0x%08X, 0x%08X, 0x%08X, "
+                                            "0x%08X, 0x%08X, 0x%08X\n",
+                               dma_reason[0], dma_reason[1],
+                               dma_reason[2], dma_reason[3],
+                               dma_reason[4], dma_reason[5]);
+                       bcm43xx_controller_restart(dev, "DMA error");
+                       mmiowb();
+                       spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
+                       return;
+               }
+               if (merged_dma_reason & BCM43xx_DMAIRQ_NONFATALMASK) {
+                       printkl(KERN_ERR PFX "DMA error: "
+                                            "0x%08X, 0x%08X, 0x%08X, "
+                                            "0x%08X, 0x%08X, 0x%08X\n",
+                               dma_reason[0], dma_reason[1],
+                               dma_reason[2], dma_reason[3],
+                               dma_reason[4], dma_reason[5]);
+               }
+       }
+
+       if (unlikely(reason & BCM43xx_IRQ_UCODE_DEBUG))
+               handle_irq_ucode_debug(dev);
+       if (reason & BCM43xx_IRQ_TBTT_INDI)
+               handle_irq_tbtt_indication(dev);
+       if (reason & BCM43xx_IRQ_ATIM_END)
+               handle_irq_atim_end(dev);
+       if (reason & BCM43xx_IRQ_BEACON)
+               handle_irq_beacon(dev);
+       if (reason & BCM43xx_IRQ_PMQ)
+               handle_irq_pmq(dev);
+       if (reason & BCM43xx_IRQ_TXFIFO_FLUSH_OK)
+               ;/*TODO*/
+       if (reason & BCM43xx_IRQ_NOISESAMPLE_OK)
+               handle_irq_noise(dev);
+
+       /* Check the DMA reason registers for received data. */
+       if (dma_reason[0] & BCM43xx_DMAIRQ_RX_DONE) {
+               if (bcm43xx_using_pio(dev))
+                       bcm43xx_pio_rx(dev->pio.queue0);
+               else
+                       bcm43xx_dma_rx(dev->dma.rx_ring0);
+               /* We intentionally don't set "activity" to 1, here. */
+       }
+       assert(!(dma_reason[1] & BCM43xx_DMAIRQ_RX_DONE));
+       assert(!(dma_reason[2] & BCM43xx_DMAIRQ_RX_DONE));
+       if (dma_reason[3] & BCM43xx_DMAIRQ_RX_DONE) {
+               if (bcm43xx_using_pio(dev))
+                       bcm43xx_pio_rx(dev->pio.queue3);
+               else
+                       bcm43xx_dma_rx(dev->dma.rx_ring3);
+               activity = 1;
+       }
+       assert(!(dma_reason[4] & BCM43xx_DMAIRQ_RX_DONE));
+       assert(!(dma_reason[5] & BCM43xx_DMAIRQ_RX_DONE));
+
+       if (reason & BCM43xx_IRQ_TX_OK) {
+               handle_irq_transmit_status(dev);
+               activity = 1;
+               //TODO: In AP mode, this also causes sending of powersave responses.
+       }
+
+       if (!modparam_noleds)
+               bcm43xx_leds_update(dev, activity);
+       bcm43xx_interrupt_enable(dev, dev->irq_savedstate);
+       mmiowb();
+       spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
+}
+
+static void pio_irq_workaround(struct bcm43xx_wldev *dev,
+                              u16 base, int queueidx)
+{
+       u16 rxctl;
+
+       rxctl = bcm43xx_read16(dev, base + BCM43xx_PIO_RXCTL);
+       if (rxctl & BCM43xx_PIO_RXCTL_DATAAVAILABLE)
+               dev->dma_reason[queueidx] |= BCM43xx_DMAIRQ_RX_DONE;
+       else
+               dev->dma_reason[queueidx] &= ~BCM43xx_DMAIRQ_RX_DONE;
+}
+
+static void bcm43xx_interrupt_ack(struct bcm43xx_wldev *dev, u32 reason)
+{
+       if (bcm43xx_using_pio(dev) &&
+           (dev->dev->id.revision < 3) &&
+           (!(reason & BCM43xx_IRQ_PIO_WORKAROUND))) {
+               /* Apply a PIO specific workaround to the dma_reasons */
+               pio_irq_workaround(dev, BCM43xx_MMIO_PIO1_BASE, 0);
+               pio_irq_workaround(dev, BCM43xx_MMIO_PIO2_BASE, 1);
+               pio_irq_workaround(dev, BCM43xx_MMIO_PIO3_BASE, 2);
+               pio_irq_workaround(dev, BCM43xx_MMIO_PIO4_BASE, 3);
+       }
+
+       bcm43xx_write32(dev, BCM43xx_MMIO_GEN_IRQ_REASON, reason);
+
+       bcm43xx_write32(dev, BCM43xx_MMIO_DMA0_REASON,
+                       dev->dma_reason[0]);
+       bcm43xx_write32(dev, BCM43xx_MMIO_DMA1_REASON,
+                       dev->dma_reason[1]);
+       bcm43xx_write32(dev, BCM43xx_MMIO_DMA2_REASON,
+                       dev->dma_reason[2]);
+       bcm43xx_write32(dev, BCM43xx_MMIO_DMA3_REASON,
+                       dev->dma_reason[3]);
+       bcm43xx_write32(dev, BCM43xx_MMIO_DMA4_REASON,
+                       dev->dma_reason[4]);
+       bcm43xx_write32(dev, BCM43xx_MMIO_DMA5_REASON,
+                       dev->dma_reason[5]);
+}
+
+/* Interrupt handler top-half */
+static irqreturn_t bcm43xx_interrupt_handler(int irq, void *dev_id)
+{
+       irqreturn_t ret = IRQ_HANDLED;
+       struct bcm43xx_wldev *dev = dev_id;
+       u32 reason;
+
+       if (!dev)
+               return IRQ_NONE;
+
+       spin_lock(&dev->wl->irq_lock);
+
+       reason = bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_REASON);
+       if (reason == 0xffffffff) {
+               /* irq not for us (shared irq) */
+               ret = IRQ_NONE;
+               goto out;
+       }
+       reason &= bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_MASK);
+       if (!reason)
+               goto out;
+
+       assert(bcm43xx_status(dev) == BCM43xx_STAT_INITIALIZED);
+       assert(dev->started);
+
+       dev->dma_reason[0] = bcm43xx_read32(dev, BCM43xx_MMIO_DMA0_REASON)
+                            & 0x0001DC00;
+       dev->dma_reason[1] = bcm43xx_read32(dev, BCM43xx_MMIO_DMA1_REASON)
+                            & 0x0000DC00;
+       dev->dma_reason[2] = bcm43xx_read32(dev, BCM43xx_MMIO_DMA2_REASON)
+                            & 0x0000DC00;
+       dev->dma_reason[3] = bcm43xx_read32(dev, BCM43xx_MMIO_DMA3_REASON)
+                            & 0x0001DC00;
+       dev->dma_reason[4] = bcm43xx_read32(dev, BCM43xx_MMIO_DMA4_REASON)
+                            & 0x0000DC00;
+       dev->dma_reason[5] = bcm43xx_read32(dev, BCM43xx_MMIO_DMA5_REASON)
+                            & 0x0000DC00;
+
+       bcm43xx_interrupt_ack(dev, reason);
+       /* disable all IRQs. They are enabled again in the bottom half. */
+       dev->irq_savedstate = bcm43xx_interrupt_disable(dev, BCM43xx_IRQ_ALL);
+       /* save the reason code and call our bottom half. */
+       dev->irq_reason = reason;
+       tasklet_schedule(&dev->isr_tasklet);
+out:
+       mmiowb();
+       spin_unlock(&dev->wl->irq_lock);
+
+       return ret;
+}
+
+static void bcm43xx_release_firmware(struct bcm43xx_wldev *dev)
+{
+       release_firmware(dev->fw.ucode);
+       dev->fw.ucode = NULL;
+       release_firmware(dev->fw.pcm);
+       dev->fw.pcm = NULL;
+       release_firmware(dev->fw.initvals0);
+       dev->fw.initvals0 = NULL;
+       release_firmware(dev->fw.initvals1);
+       dev->fw.initvals1 = NULL;
+}
+
+static int bcm43xx_request_firmware(struct bcm43xx_wldev *dev)
+{
+       u8 rev = dev->dev->id.revision;
+       int err = 0;
+       int nr;
+       char buf[22 + sizeof(modparam_fwpostfix) - 1] = { 0 };
+
+       if (!dev->fw.ucode) {
+               snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_microcode%d%s.fw",
+                        (rev >= 5 ? 5 : rev),
+                        modparam_fwpostfix);
+               err = request_firmware(&dev->fw.ucode, buf, dev->dev->dev);
+               if (err) {
+                       printk(KERN_ERR PFX
+                              "Error: Microcode \"%s\" not available or load failed.\n",
+                               buf);
+                       goto error;
+               }
+       }
+
+       if (!dev->fw.pcm) {
+               snprintf(buf, ARRAY_SIZE(buf),
+                        "bcm43xx_pcm%d%s.fw",
+                        (rev < 5 ? 4 : 5),
+                        modparam_fwpostfix);
+               err = request_firmware(&dev->fw.pcm, buf, dev->dev->dev);
+               if (err) {
+                       printk(KERN_ERR PFX
+                              "Error: PCM \"%s\" not available or load failed.\n",
+                              buf);
+                       goto error;
+               }
+       }
+
+       if (!dev->fw.initvals0) {
+               if (rev == 2 || rev == 4) {
+                       switch (dev->phy.type) {
+                       case BCM43xx_PHYTYPE_A:
+                               nr = 3;
+                               break;
+                       case BCM43xx_PHYTYPE_B:
+                       case BCM43xx_PHYTYPE_G:
+                               nr = 1;
+                               break;
+                       default:
+                               goto err_noinitval;
+                       }
+
+               } else if (rev >= 5) {
+                       switch (dev->phy.type) {
+                       case BCM43xx_PHYTYPE_A:
+                               nr = 7;
+                               break;
+                       case BCM43xx_PHYTYPE_B:
+                       case BCM43xx_PHYTYPE_G:
+                               nr = 5;
+                               break;
+                       default:
+                               goto err_noinitval;
+                       }
+               } else
+                       goto err_noinitval;
+               snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
+                        nr, modparam_fwpostfix);
+
+               err = request_firmware(&dev->fw.initvals0, buf, dev->dev->dev);
+               if (err) {
+                       printk(KERN_ERR PFX
+                              "Error: InitVals \"%s\" not available or load failed.\n",
+                               buf);
+                       goto error;
+               }
+               if (dev->fw.initvals0->size % sizeof(struct bcm43xx_initval)) {
+                       printk(KERN_ERR PFX "InitVals fileformat error.\n");
+                       goto error;
+               }
+       }
+
+       if (!dev->fw.initvals1) {
+               if (rev >= 5) {
+                       u32 sbtmstatehigh;
+
+                       switch (dev->phy.type) {
+                       case BCM43xx_PHYTYPE_A:
+                               sbtmstatehigh = ssb_read32(dev->dev, SSB_TMSHIGH);
+                               if (sbtmstatehigh & 0x00010000)
+                                       nr = 9;
+                               else
+                                       nr = 10;
+                               break;
+                       case BCM43xx_PHYTYPE_B:
+                       case BCM43xx_PHYTYPE_G:
+                                       nr = 6;
+                               break;
+                       default:
+                               goto err_noinitval;
+                       }
+                       snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
+                                nr, modparam_fwpostfix);
+
+                       err = request_firmware(&dev->fw.initvals1, buf, dev->dev->dev);
+                       if (err) {
+                               printk(KERN_ERR PFX
+                                      "Error: InitVals \"%s\" not available or load failed.\n",
+                                       buf);
+                               goto error;
+                       }
+                       if (dev->fw.initvals1->size % sizeof(struct bcm43xx_initval)) {
+                               printk(KERN_ERR PFX "InitVals fileformat error.\n");
+                               goto error;
+                       }
+               }
+       }
+
+out:
+       return err;
+error:
+       bcm43xx_release_firmware(dev);
+       goto out;
+err_noinitval:
+       printk(KERN_ERR PFX "Error: No InitVals available!\n");
+       err = -ENOENT;
+       goto error;
+}
+
+static int bcm43xx_upload_microcode(struct bcm43xx_wldev *dev)
+{
+       const __be32 *data;
+       unsigned int i, len;
+       u16 fwrev, fwpatch, fwdate, fwtime;
+       u32 tmp;
+       int err = 0;
+
+       /* Upload Microcode. */
+       data = (__be32 *)(dev->fw.ucode->data);
+       len = dev->fw.ucode->size / sizeof(__be32);
+       bcm43xx_shm_control_word(dev,
+                                BCM43xx_SHM_UCODE | BCM43xx_SHM_AUTOINC_W,
+                                0x0000);
+       for (i = 0; i < len; i++) {
+               bcm43xx_write32(dev, BCM43xx_MMIO_SHM_DATA,
+                               be32_to_cpu(data[i]));
+               udelay(10);
+       }
+
+       /* Upload PCM data. */
+       data = (__be32 *)(dev->fw.pcm->data);
+       len = dev->fw.pcm->size / sizeof(__be32);
+       bcm43xx_shm_control_word(dev, BCM43xx_SHM_HW, 0x01EA);
+       bcm43xx_write32(dev, BCM43xx_MMIO_SHM_DATA, 0x00004000);
+       /* No need for autoinc bit in SHM_HW */
+       bcm43xx_shm_control_word(dev, BCM43xx_SHM_HW, 0x01EB);
+       for (i = 0; i < len; i++) {
+               bcm43xx_write32(dev, BCM43xx_MMIO_SHM_DATA,
+                               be32_to_cpu(data[i]));
+               udelay(10);
+       }
+
+       bcm43xx_write32(dev, BCM43xx_MMIO_GEN_IRQ_REASON, BCM43xx_IRQ_ALL);
+       bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD, 0x00020402);
+
+       /* Wait for the microcode to load and respond */
+       i = 0;
+       while (1) {
+               tmp = bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_REASON);
+               if (tmp == BCM43xx_IRQ_MAC_SUSPENDED)
+                       break;
+               i++;
+               if (i >= BCM43xx_IRQWAIT_MAX_RETRIES) {
+                       printk(KERN_ERR PFX "Microcode not responding\n");
+                       err = -ENODEV;
+                       goto out;
+               }
+               udelay(10);
+       }
+       bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
+
+       /* Get and check the revisions. */
+       fwrev = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
+                                  BCM43xx_SHM_SH_UCODEREV);
+       fwpatch = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
+                                    BCM43xx_SHM_SH_UCODEPATCH);
+       fwdate = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
+                                   BCM43xx_SHM_SH_UCODEDATE);
+       fwtime = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
+                                   BCM43xx_SHM_SH_UCODETIME);
+
+       if (fwrev <= 0x128) {
+               printk(KERN_ERR PFX "YOUR FIRMWARE IS TOO OLD. Firmware from "
+                      "binary drivers older than version 4.x is unsupported. "
+                      "You must upgrade your firmware files.\n");
+               bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD, 0);
+               err = -EOPNOTSUPP;
+               goto out;
+       }
+       printk(KERN_DEBUG PFX "Loading firmware version %u.%u "
+                             "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
+              fwrev, fwpatch,
+              (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
+              (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
+
+       dev->fw.rev = fwrev;
+       dev->fw.patch = fwpatch;
+
+out:
+       return err;
+}
+
+static int bcm43xx_write_initvals(struct bcm43xx_wldev *dev,
+                                 const struct bcm43xx_initval *data,
+                                 const unsigned int len)
+{
+       u16 offset, size;
+       u32 value;
+       unsigned int i;
+
+       for (i = 0; i < len; i++) {
+               offset = be16_to_cpu(data[i].offset);
+               size = be16_to_cpu(data[i].size);
+               value = be32_to_cpu(data[i].value);
+
+               if (unlikely(offset >= 0x1000))
+                       goto err_format;
+               if (size == 2) {
+                       if (unlikely(value & 0xFFFF0000))
+                               goto err_format;
+                       bcm43xx_write16(dev, offset, (u16)value);
+               } else if (size == 4) {
+                       bcm43xx_write32(dev, offset, value);
+               } else
+                       goto err_format;
+       }
+
+       return 0;
+
+err_format:
+       printk(KERN_ERR PFX "InitVals (bcm43xx_initvalXX.fw) file-format error. "
+                           "Please fix your bcm43xx firmware files.\n");
+       return -EPROTO;
+}
+
+static int bcm43xx_upload_initvals(struct bcm43xx_wldev *dev)
+{
+       int err;
+
+       err = bcm43xx_write_initvals(dev, (struct bcm43xx_initval *)dev->fw.initvals0->data,
+                                    dev->fw.initvals0->size / sizeof(struct bcm43xx_initval));
+       if (err)
+               goto out;
+       if (dev->fw.initvals1) {
+               err = bcm43xx_write_initvals(dev, (struct bcm43xx_initval *)dev->fw.initvals1->data,
+                                            dev->fw.initvals1->size / sizeof(struct bcm43xx_initval));
+               if (err)
+                       goto out;
+       }
+out:
+       return err;
+}
+
+/* Initialize the GPIOs
+ * http://bcm-specs.sipsolutions.net/GPIO
+ */
+static int bcm43xx_gpio_init(struct bcm43xx_wldev *dev)
+{
+       struct ssb_bus *bus = dev->dev->bus;
+       struct ssb_device *gpiodev, *pcidev = NULL;
+       u32 mask, set;
+
+       bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD,
+                       bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD)
+                       & 0xFFFF3FFF);
+
+       bcm43xx_leds_switch_all(dev, 0);
+       bcm43xx_write16(dev, BCM43xx_MMIO_GPIO_MASK,
+                       bcm43xx_read16(dev, BCM43xx_MMIO_GPIO_MASK)
+                       | 0x000F);
+
+       mask = 0x0000001F;
+       set = 0x0000000F;
+       if (dev->dev->bus->chip_id == 0x4301) {
+               mask |= 0x0060;
+               set |= 0x0060;
+       }
+       if (0 /* FIXME: conditional unknown */) {
+               bcm43xx_write16(dev, BCM43xx_MMIO_GPIO_MASK,
+                               bcm43xx_read16(dev, BCM43xx_MMIO_GPIO_MASK)
+                               | 0x0100);
+               mask |= 0x0180;
+               set |= 0x0180;
+       }
+       if (dev->dev->bus->sprom.r1.boardflags_lo & BCM43xx_BFL_PACTRL) {
+               bcm43xx_write16(dev, BCM43xx_MMIO_GPIO_MASK,
+                               bcm43xx_read16(dev, BCM43xx_MMIO_GPIO_MASK)
+                               | 0x0200);
+               mask |= 0x0200;
+               set |= 0x0200;
+       }
+       if (dev->dev->id.revision >= 2)
+               mask  |= 0x0010; /* FIXME: This is redundant. */
+
+#ifdef CONFIG_SSB_DRIVER_PCICORE
+       pcidev = bus->pcicore.dev;
+#endif
+       gpiodev = bus->chipco.dev ? : pcidev;
+       if (!gpiodev)
+               return 0;
+       ssb_write32(gpiodev, BCM43xx_GPIO_CONTROL,
+                   (ssb_read32(gpiodev, BCM43xx_GPIO_CONTROL)
+                    & mask) | set);
+
+       return 0;
+}
+
+/* Turn off all GPIO stuff. Call this on module unload, for example. */
+static void bcm43xx_gpio_cleanup(struct bcm43xx_wldev *dev)
+{
+       struct ssb_bus *bus = dev->dev->bus;
+       struct ssb_device *gpiodev, *pcidev = NULL;
+
+#ifdef CONFIG_SSB_DRIVER_PCICORE
+       pcidev = bus->pcicore.dev;
+#endif
+       gpiodev = bus->chipco.dev ? : pcidev;
+       if (!gpiodev)
+               return;
+       ssb_write32(gpiodev, BCM43xx_GPIO_CONTROL, 0);
+}
+
+/* http://bcm-specs.sipsolutions.net/EnableMac */
+void bcm43xx_mac_enable(struct bcm43xx_wldev *dev)
+{
+       dev->mac_suspended--;
+       assert(dev->mac_suspended >= 0);
+       if (dev->mac_suspended == 0) {
+               bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD,
+                               bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD)
+                               | BCM43xx_SBF_MAC_ENABLED);
+               bcm43xx_write32(dev, BCM43xx_MMIO_GEN_IRQ_REASON,
+                               BCM43xx_IRQ_MAC_SUSPENDED);
+               bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
+               bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
+               bcm43xx_power_saving_ctl_bits(dev, -1, -1);
+       }
+}
+
+/* http://bcm-specs.sipsolutions.net/SuspendMAC */
+void bcm43xx_mac_suspend(struct bcm43xx_wldev *dev)
+{
+       int i;
+       u32 tmp;
+
+       assert(dev->mac_suspended >= 0);
+       if (dev->mac_suspended == 0) {
+               bcm43xx_power_saving_ctl_bits(dev, -1, 1);
+               bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD,
+                               bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD)
+                               & ~BCM43xx_SBF_MAC_ENABLED);
+               bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
+               for (i = 10000; i; i--) {
+                       tmp = bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_REASON);
+                       if (tmp & BCM43xx_IRQ_MAC_SUSPENDED)
+                               goto out;
+                       udelay(1);
+               }
+               printkl(KERN_ERR PFX "MAC suspend failed\n");
+       }
+out:
+       dev->mac_suspended++;
+}
+
+static void bcm43xx_adjust_opmode(struct bcm43xx_wldev *dev)
+{
+       struct bcm43xx_wl *wl = dev->wl;
+       u32 ctl;
+       u16 cfp_pretbtt;
+
+       ctl = bcm43xx_read32(dev, BCM43xx_MMIO_MACCTL);
+       /* Reset status to STA infrastructure mode. */
+       ctl &= ~BCM43xx_MACCTL_AP;
+       ctl &= ~BCM43xx_MACCTL_KEEP_CTL;
+       ctl &= ~BCM43xx_MACCTL_KEEP_BADPLCP;
+       ctl &= ~BCM43xx_MACCTL_KEEP_BAD;
+       ctl &= ~BCM43xx_MACCTL_PROMISC;
+       ctl |= BCM43xx_MACCTL_INFRA;
+
+       if (wl->operating) {
+               switch (wl->if_type) {
+               case IEEE80211_IF_TYPE_AP:
+                       ctl |= BCM43xx_MACCTL_AP;
+                       break;
+               case IEEE80211_IF_TYPE_IBSS:
+                       ctl &= ~BCM43xx_MACCTL_INFRA;
+                       break;
+               case IEEE80211_IF_TYPE_STA:
+               case IEEE80211_IF_TYPE_MNTR:
+               case IEEE80211_IF_TYPE_WDS:
+                       break;
+               default:
+                       assert(0);
+               }
+       }
+       if (wl->monitor) {
+               ctl |= BCM43xx_MACCTL_PROMISC;
+               ctl |= BCM43xx_MACCTL_KEEP_CTL;
+               if (modparam_mon_keep_bad)
+                       ctl |= BCM43xx_MACCTL_KEEP_BAD;
+               if (modparam_mon_keep_badplcp)
+                       ctl |= BCM43xx_MACCTL_KEEP_BADPLCP;
+       }
+       if (wl->promisc)
+               ctl |= BCM43xx_MACCTL_PROMISC;
+
+       bcm43xx_write32(dev, BCM43xx_MMIO_MACCTL, ctl);
+
+       cfp_pretbtt = 2;
+       if ((ctl & BCM43xx_MACCTL_INFRA) &&
+           !(ctl & BCM43xx_MACCTL_AP)) {
+               if (dev->dev->bus->chip_id == 0x4306 &&
+                   dev->dev->bus->chip_rev == 3)
+                       cfp_pretbtt = 100;
+               else
+                       cfp_pretbtt = 50;
+       }
+       bcm43xx_write16(dev, 0x612, cfp_pretbtt);
+}
+
+static void bcm43xx_rate_memory_write(struct bcm43xx_wldev *dev,
+                                     u16 rate,
+                                     int is_ofdm)
+{
+       u16 offset;
+
+       if (is_ofdm) {
+               offset = 0x480;
+               offset += (bcm43xx_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
+       } else {
+               offset = 0x4C0;
+               offset += (bcm43xx_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
+       }
+       bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, offset + 0x20,
+                           bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED, offset));
+}
+
+static void bcm43xx_rate_memory_init(struct bcm43xx_wldev *dev)
+{
+       switch (dev->phy.type) {
+       case BCM43xx_PHYTYPE_A:
+       case BCM43xx_PHYTYPE_G:
+               bcm43xx_rate_memory_write(dev, BCM43xx_OFDM_RATE_6MB, 1);
+               bcm43xx_rate_memory_write(dev, BCM43xx_OFDM_RATE_12MB, 1);
+               bcm43xx_rate_memory_write(dev, BCM43xx_OFDM_RATE_18MB, 1);
+               bcm43xx_rate_memory_write(dev, BCM43xx_OFDM_RATE_24MB, 1);
+               bcm43xx_rate_memory_write(dev, BCM43xx_OFDM_RATE_36MB, 1);
+               bcm43xx_rate_memory_write(dev, BCM43xx_OFDM_RATE_48MB, 1);
+               bcm43xx_rate_memory_write(dev, BCM43xx_OFDM_RATE_54MB, 1);
+       case BCM43xx_PHYTYPE_B:
+               bcm43xx_rate_memory_write(dev, BCM43xx_CCK_RATE_1MB, 0);
+               bcm43xx_rate_memory_write(dev, BCM43xx_CCK_RATE_2MB, 0);
+               bcm43xx_rate_memory_write(dev, BCM43xx_CCK_RATE_5MB, 0);
+               bcm43xx_rate_memory_write(dev, BCM43xx_CCK_RATE_11MB, 0);
+               break;
+       default:
+               assert(0);
+       }
+}
+
+/* Set the TX-Antenna for management frames sent by firmware. */
+static void bcm43xx_mgmtframe_txantenna(struct bcm43xx_wldev *dev,
+                                       int antenna)
+{
+       u16 ant = 0;
+       u16 tmp;
+
+       switch (antenna) {
+       case BCM43xx_ANTENNA0:
+               ant |= BCM43xx_TX4_PHY_ANT0;
+               break;
+       case BCM43xx_ANTENNA1:
+               ant |= BCM43xx_TX4_PHY_ANT1;
+               break;
+       case BCM43xx_ANTENNA_AUTO:
+               ant |= BCM43xx_TX4_PHY_ANTLAST;
+               break;
+       default:
+               assert(0);
+       }
+
+       /* FIXME We also need to set the other flags of the PHY control field somewhere. */
+
+       /* For Beacons */
+       tmp = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
+                                BCM43xx_SHM_SH_BEACPHYCTL);
+       tmp = (tmp & ~BCM43xx_TX4_PHY_ANT) | ant;
+       bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
+                           BCM43xx_SHM_SH_BEACPHYCTL, tmp);
+       /* For ACK/CTS */
+       tmp = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
+                                BCM43xx_SHM_SH_ACKCTSPHYCTL);
+       tmp = (tmp & ~BCM43xx_TX4_PHY_ANT) | ant;
+       bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
+                           BCM43xx_SHM_SH_ACKCTSPHYCTL, tmp);
+       /* For Probe Resposes */
+       tmp = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
+                                BCM43xx_SHM_SH_PRPHYCTL);
+       tmp = (tmp & ~BCM43xx_TX4_PHY_ANT) | ant;
+       bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
+                           BCM43xx_SHM_SH_PRPHYCTL, tmp);
+}
+
+/* This is the opposite of bcm43xx_chip_init() */
+static void bcm43xx_chip_exit(struct bcm43xx_wldev *dev)
+{
+       bcm43xx_radio_turn_off(dev);
+       if (!modparam_noleds)
+               bcm43xx_leds_exit(dev);
+       bcm43xx_gpio_cleanup(dev);
+       /* firmware is released later */
+}
+
+/* Initialize the chip
+ * http://bcm-specs.sipsolutions.net/ChipInit
+ */
+static int bcm43xx_chip_init(struct bcm43xx_wldev *dev)
+{
+       struct bcm43xx_phy *phy = &dev->phy;
+       int err, tmp;
+       u32 value32;
+       u16 value16;
+
+       bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD,
+                       BCM43xx_SBF_CORE_READY
+                       | BCM43xx_SBF_400);
+
+       err = bcm43xx_request_firmware(dev);
+       if (err)
+               goto out;
+       err = bcm43xx_upload_microcode(dev);
+       if (err)
+               goto out; /* firmware is released later */
+
+       err = bcm43xx_gpio_init(dev);
+       if (err)
+               goto out; /* firmware is released later */
+       err = bcm43xx_upload_initvals(dev);
+       if (err)
+               goto err_gpio_cleanup;
+       bcm43xx_radio_turn_on(dev);
+       dev->radio_hw_enable = bcm43xx_is_hw_radio_enabled(dev);
+       dprintk(KERN_INFO PFX "Radio %s by hardware\n",
+               (dev->radio_hw_enable == 0) ? "disabled" : "enabled");
+
+       bcm43xx_write16(dev, 0x03E6, 0x0000);
+       err = bcm43xx_phy_init(dev);
+       if (err)
+               goto err_radio_off;
+
+       /* Select initial Interference Mitigation. */
+       tmp = phy->interfmode;
+       phy->interfmode = BCM43xx_INTERFMODE_NONE;
+       bcm43xx_radio_set_interference_mitigation(dev, tmp);
+
+       bcm43xx_set_rx_antenna(dev, BCM43xx_ANTENNA_DEFAULT);
+       bcm43xx_mgmtframe_txantenna(dev, BCM43xx_ANTENNA_DEFAULT);
+
+       if (phy->type == BCM43xx_PHYTYPE_B) {
+               value16 = bcm43xx_read16(dev, 0x005E);
+               value16 |= 0x0004;
+               bcm43xx_write16(dev, 0x005E, value16);
+       }
+       bcm43xx_write32(dev, 0x0100, 0x01000000);
+       if (dev->dev->id.revision < 5)
+               bcm43xx_write32(dev, 0x010C, 0x01000000);
+
+       value32 = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD);
+       value32 &= ~ BCM43xx_SBF_MODE_NOTADHOC;
+       bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD, value32);
+       value32 = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD);
+       value32 |= BCM43xx_SBF_MODE_NOTADHOC;
+       bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD, value32);
+
+       value32 = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD);
+       value32 |= 0x100000;
+       bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD, value32);
+
+       if (bcm43xx_using_pio(dev)) {
+               bcm43xx_write32(dev, 0x0210, 0x00000100);
+               bcm43xx_write32(dev, 0x0230, 0x00000100);
+               bcm43xx_write32(dev, 0x0250, 0x00000100);
+               bcm43xx_write32(dev, 0x0270, 0x00000100);
+               bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x0034, 0x0000);
+       }
+
+       /* Probe Response Timeout value */
+       /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
+       bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x0074, 0x0000);
+
+       /* Initially set the wireless operation mode. */
+       bcm43xx_adjust_opmode(dev);
+
+       if (dev->dev->id.revision < 3) {
+               bcm43xx_write16(dev, 0x060E, 0x0000);
+               bcm43xx_write16(dev, 0x0610, 0x8000);
+               bcm43xx_write16(dev, 0x0604, 0x0000);
+               bcm43xx_write16(dev, 0x0606, 0x0200);
+       } else {
+               bcm43xx_write32(dev, 0x0188, 0x80000000);
+               bcm43xx_write32(dev, 0x018C, 0x02000000);
+       }
+       bcm43xx_write32(dev, BCM43xx_MMIO_GEN_IRQ_REASON, 0x00004000);
+       bcm43xx_write32(dev, BCM43xx_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
+       bcm43xx_write32(dev, BCM43xx_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
+       bcm43xx_write32(dev, BCM43xx_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
+       bcm43xx_write32(dev, BCM43xx_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
+       bcm43xx_write32(dev, BCM43xx_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
+       bcm43xx_write32(dev, BCM43xx_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
+
+       value32 = ssb_read32(dev->dev, SSB_TMSLOW);
+       value32 |= 0x00100000;
+       ssb_write32(dev->dev, SSB_TMSLOW, value32);
+
+       bcm43xx_write16(dev, BCM43xx_MMIO_POWERUP_DELAY,
+                       dev->dev->bus->chipco.fast_pwrup_delay);
+
+       assert(err == 0);
+       dprintk(KERN_INFO PFX "Chip initialized\n");
+out:
+       return err;
+
+err_radio_off:
+       bcm43xx_radio_turn_off(dev);
+err_gpio_cleanup:
+       bcm43xx_gpio_cleanup(dev);
+       goto out;
+}
+
+static void bcm43xx_periodic_every120sec(struct bcm43xx_wldev *dev)
+{
+       struct bcm43xx_phy *phy = &dev->phy;
+
+       if (phy->type != BCM43xx_PHYTYPE_G || phy->rev < 2)
+               return;
+
+       bcm43xx_mac_suspend(dev);
+       bcm43xx_lo_g_measure(dev);
+       bcm43xx_mac_enable(dev);
+}
+
+static void bcm43xx_periodic_every60sec(struct bcm43xx_wldev *dev)
+{
+       bcm43xx_lo_g_ctl_mark_all_unused(dev);
+       if (dev->dev->bus->sprom.r1.boardflags_lo & BCM43xx_BFL_RSSI) {
+               bcm43xx_mac_suspend(dev);
+               bcm43xx_calc_nrssi_slope(dev);
+               bcm43xx_mac_enable(dev);
+       }
+}
+
+static void bcm43xx_periodic_every30sec(struct bcm43xx_wldev *dev)
+{
+       /* Update device statistics. */
+       bcm43xx_calculate_link_quality(dev);
+}
+
+static void bcm43xx_periodic_every15sec(struct bcm43xx_wldev *dev)
+{
+       struct bcm43xx_phy *phy = &dev->phy;
+
+       if (phy->type == BCM43xx_PHYTYPE_G) {
+               //TODO: update_aci_moving_average
+               if (phy->aci_enable && phy->aci_wlan_automatic) {
+                       bcm43xx_mac_suspend(dev);
+                       if (!phy->aci_enable && 1 /*TODO: not scanning? */) {
+                               if (0 /*TODO: bunch of conditions*/) {
+                                       bcm43xx_radio_set_interference_mitigation(dev,
+                                                                                 BCM43xx_INTERFMODE_MANUALWLAN);
+                               }
+                       } else if (1/*TODO*/) {
+                               /*
+                               if ((aci_average > 1000) && !(bcm43xx_radio_aci_scan(dev))) {
+                                       bcm43xx_radio_set_interference_mitigation(dev,
+                                                                                 BCM43xx_INTERFMODE_NONE);
+                               }
+                               */
+                       }
+                       bcm43xx_mac_enable(dev);
+               } else if (phy->interfmode == BCM43xx_INTERFMODE_NONWLAN &&
+                          phy->rev == 1) {
+                       //TODO: implement rev1 workaround
+               }
+       }
+       bcm43xx_phy_xmitpower(dev); //FIXME: unless scanning?
+       //TODO for APHY (temperature?)
+}
+
+static void bcm43xx_periodic_every1sec(struct bcm43xx_wldev *dev)
+{
+       int radio_hw_enable;
+
+       /* check if radio hardware enabled status changed */
+       radio_hw_enable = bcm43xx_is_hw_radio_enabled(dev);
+       if (unlikely(dev->radio_hw_enable != radio_hw_enable)) {
+               dev->radio_hw_enable = radio_hw_enable;
+               dprintk(KERN_INFO PFX "Radio hardware status changed to %s\n",
+                       (radio_hw_enable == 0) ? "disabled" : "enabled");
+               bcm43xx_leds_update(dev, 0);
+       }
+}
+
+static void do_periodic_work(struct bcm43xx_wldev *dev)
+{
+       unsigned int state;
+
+       state = dev->periodic_state;
+       if (state % 120 == 0)
+               bcm43xx_periodic_every120sec(dev);
+       if (state % 60 == 0)
+               bcm43xx_periodic_every60sec(dev);
+       if (state % 30 == 0)
+               bcm43xx_periodic_every30sec(dev);
+       if (state % 15 == 0)
+               bcm43xx_periodic_every15sec(dev);
+       bcm43xx_periodic_every1sec(dev);
+
+       dev->periodic_state = state + 1;
+
+       schedule_delayed_work(&dev->periodic_work, HZ);
+}
+
+/* Estimate a "Badness" value based on the periodic work
+ * state-machine state. "Badness" is worse (bigger), if the
+ * periodic work will take longer.
+ */
+static int estimate_periodic_work_badness(unsigned int state)
+{
+       int badness = 0;
+
+       if (state % 120 == 0) /* every 120 sec */
+               badness += 10;
+       if (state % 60 == 0) /* every 60 sec */
+               badness += 5;
+       if (state % 30 == 0) /* every 30 sec */
+               badness += 1;
+       if (state % 15 == 0) /* every 15 sec */
+               badness += 1;
+
+#define BADNESS_LIMIT  4
+       return badness;
+}
+
+static void bcm43xx_periodic_work_handler(struct work_struct *work)
+{
+       struct bcm43xx_wldev *dev =
+               container_of(work, struct bcm43xx_wldev, periodic_work.work);
+       unsigned long flags;
+       u32 savedirqs = 0;
+       int badness;
+
+       mutex_lock(&dev->wl->mutex);
+       badness = estimate_periodic_work_badness(dev->periodic_state);
+       if (badness > BADNESS_LIMIT) {
+               /* Periodic work will take a long time, so we want it to
+                * be preemtible.
+                */
+               ieee80211_stop_queues(dev->wl->hw);
+               spin_lock_irqsave(&dev->wl->irq_lock, flags);
+               bcm43xx_mac_suspend(dev);
+               if (bcm43xx_using_pio(dev))
+                       bcm43xx_pio_freeze_txqueues(dev);
+               savedirqs = bcm43xx_interrupt_disable(dev, BCM43xx_IRQ_ALL);
+               spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
+               bcm43xx_synchronize_irq(dev);
+       } else {
+               /* Periodic work should take short time, so we want low
+                * locking overhead.
+                */
+               spin_lock_irqsave(&dev->wl->irq_lock, flags);
+       }
+
+       do_periodic_work(dev);
+
+       if (badness > BADNESS_LIMIT) {
+               spin_lock_irqsave(&dev->wl->irq_lock, flags);
+               bcm43xx_interrupt_enable(dev, savedirqs);
+               if (bcm43xx_using_pio(dev))
+                       bcm43xx_pio_thaw_txqueues(dev);
+               bcm43xx_mac_enable(dev);
+               ieee80211_start_queues(dev->wl->hw);
+       }
+       mmiowb();
+       spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
+       mutex_unlock(&dev->wl->mutex);
+}
+
+static void bcm43xx_periodic_tasks_delete(struct bcm43xx_wldev *dev)
+{
+       cancel_rearming_delayed_work(&dev->periodic_work);
+}
+
+static void bcm43xx_periodic_tasks_setup(struct bcm43xx_wldev *dev)
+{
+       struct delayed_work *work = &dev->periodic_work;
+
+       assert(bcm43xx_status(dev) == BCM43xx_STAT_INITIALIZED);
+       dev->periodic_state = 0;
+       INIT_DELAYED_WORK(work, bcm43xx_periodic_work_handler);
+       schedule_delayed_work(work, 0);
+}
+
+/* Validate access to the chip (SHM) */
+static int bcm43xx_validate_chipaccess(struct bcm43xx_wldev *dev)
+{
+       u32 value;
+       u32 shm_backup;
+
+       shm_backup = bcm43xx_shm_read32(dev, BCM43xx_SHM_SHARED, 0);
+       bcm43xx_shm_write32(dev, BCM43xx_SHM_SHARED, 0, 0xAA5555AA);
+       if (bcm43xx_shm_read32(dev, BCM43xx_SHM_SHARED, 0) != 0xAA5555AA)
+               goto error;
+       bcm43xx_shm_write32(dev, BCM43xx_SHM_SHARED, 0, 0x55AAAA55);
+       if (bcm43xx_shm_read32(dev, BCM43xx_SHM_SHARED, 0) != 0x55AAAA55)
+               goto error;
+       bcm43xx_shm_write32(dev, BCM43xx_SHM_SHARED, 0, shm_backup);
+
+       value = bcm43xx_read32(dev, BCM43xx_MMIO_MACCTL);
+       if ((value | BCM43xx_MACCTL_GMODE) !=
+           (BCM43xx_MACCTL_GMODE | BCM43xx_MACCTL_IHR_ENABLED))
+               goto error;
+
+       value = bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_REASON);
+       if (value)
+               goto error;
+
+       return 0;
+error:
+       printk(KERN_ERR PFX "Failed to validate the chipaccess\n");
+       return -ENODEV;
+}
+
+static void bcm43xx_security_init(struct bcm43xx_wldev *dev)
+{
+       dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
+       assert(dev->max_nr_keys <= ARRAY_SIZE(dev->key));
+       dev->ktp = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
+                                     BCM43xx_SHM_SH_KTP);
+       /* KTP is a word address, but we address SHM bytewise.
+        * So multiply by two.
+        */
+       dev->ktp *= 2;
+       if (dev->dev->id.revision >= 5) {
+               /* Number of RCMTA address slots */
+               bcm43xx_write16(dev, BCM43xx_MMIO_RCMTA_COUNT,
+                               dev->max_nr_keys - 8);
+       }
+       bcm43xx_clear_keys(dev);
+}
+
+static int bcm43xx_rng_read(struct hwrng *rng, u32 *data)
+{
+       struct bcm43xx_wl *wl = (struct bcm43xx_wl *)rng->priv;
+       unsigned long flags;
+
+       /* Don't take wl->mutex here, as it could deadlock with
+        * hwrng internal locking. It's not needed to take
+        * wl->mutex here, anyway. */
+
+       spin_lock_irqsave(&wl->irq_lock, flags);
+       *data = bcm43xx_read16(wl->current_dev, BCM43xx_MMIO_RNG);
+       spin_unlock_irqrestore(&wl->irq_lock, flags);
+
+       return (sizeof(u16));
+}
+
+static void bcm43xx_rng_exit(struct bcm43xx_wl *wl)
+{
+       if (wl->rng_initialized)
+               hwrng_unregister(&wl->rng);
+}
+
+static int bcm43xx_rng_init(struct bcm43xx_wl *wl)
+{
+       int err;
+
+       snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
+                "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
+       wl->rng.name = wl->rng_name;
+       wl->rng.data_read = bcm43xx_rng_read;
+       wl->rng.priv = (unsigned long)wl;
+       wl->rng_initialized = 1;
+       err = hwrng_register(&wl->rng);
+       if (err) {
+               wl->rng_initialized = 0;
+               printk(KERN_ERR PFX "Failed to register the random "
+                      "number generator (%d)\n", err);
+       }
+
+       return err;
+}
+
+static int bcm43xx_tx(struct ieee80211_hw *hw,
+                     struct sk_buff *skb,
+                     struct ieee80211_tx_control *ctl)
+{
+       struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
+       struct bcm43xx_wldev *dev = wl->current_dev;
+       int err = -ENODEV;
+       unsigned long flags;
+
+       if (unlikely(!dev))
+               goto out;
+       spin_lock_irqsave(&wl->irq_lock, flags);
+       if (likely(bcm43xx_status(dev) == BCM43xx_STAT_INITIALIZED)) {
+               if (bcm43xx_using_pio(dev))
+                       err = bcm43xx_pio_tx(dev, skb, ctl);
+               else
+                       err = bcm43xx_dma_tx(dev, skb, ctl);
+       }
+       spin_unlock_irqrestore(&wl->irq_lock, flags);
+out:
+       if (unlikely(err))
+               return NETDEV_TX_BUSY;
+       return NETDEV_TX_OK;
+}
+
+static int bcm43xx_conf_tx(struct ieee80211_hw *hw,
+                          int queue,
+                          const struct ieee80211_tx_queue_params *params)
+{
+       return 0;
+}
+
+static int bcm43xx_get_tx_stats(struct ieee80211_hw *hw,
+                               struct ieee80211_tx_queue_stats *stats)
+{
+       struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
+       struct bcm43xx_wldev *dev = wl->current_dev;
+       unsigned long flags;
+       int err = -ENODEV;
+
+       if (!dev)
+               goto out;
+       spin_lock_irqsave(&wl->irq_lock, flags);
+       if (likely(bcm43xx_status(dev) == BCM43xx_STAT_INITIALIZED)) {
+               if (bcm43xx_using_pio(dev))
+                       bcm43xx_pio_get_tx_stats(dev, stats);
+               else
+                       bcm43xx_dma_get_tx_stats(dev, stats);
+               err = 0;
+       }
+       spin_unlock_irqrestore(&wl->irq_lock, flags);
+out:
+       return err;
+}
+
+static int bcm43xx_get_stats(struct ieee80211_hw *hw,
+                            struct ieee80211_low_level_stats *stats)
+{
+       struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
+       unsigned long flags;
+
+       spin_lock_irqsave(&wl->irq_lock, flags);
+       memcpy(stats, &wl->ieee_stats, sizeof(*stats));
+       spin_unlock_irqrestore(&wl->irq_lock, flags);
+
+       return 0;
+}
+
+static int bcm43xx_dev_reset(struct ieee80211_hw *hw)
+{
+       struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
+       struct bcm43xx_wldev *dev = wl->current_dev;
+       unsigned long flags;
+
+       if (!dev)
+               return -ENODEV;
+       spin_lock_irqsave(&wl->irq_lock, flags);
+       bcm43xx_controller_restart(dev, "Reset by ieee80211 subsystem");
+       spin_unlock_irqrestore(&wl->irq_lock, flags);
+
+       return 0;
+}
+
+static const char * phymode_to_string(unsigned int phymode)
+{
+       switch (phymode) {
+       case BCM43xx_PHYMODE_A:
+               return "A";
+       case BCM43xx_PHYMODE_B:
+               return "B";
+       case BCM43xx_PHYMODE_G:
+               return "G";
+       default:
+               assert(0);
+       }
+       return "";
+}
+
+static int find_wldev_for_phymode(struct bcm43xx_wl *wl,
+                                 unsigned int phymode,
+                                 struct bcm43xx_wldev **dev,
+                                 int *gmode)
+{
+       struct bcm43xx_wldev *d;
+
+       list_for_each_entry(d, &wl->devlist, list) {
+               if (d->phy.possible_phymodes & phymode) {
+                       /* Ok, this device supports the PHY-mode.
+                        * Now figure out how the gmode bit has to be
+                        * set to support it. */
+                       if (phymode == BCM43xx_PHYMODE_A)
+                               *gmode = 0;
+                       else
+                               *gmode = 1;
+                       *dev = d;
+
+                       return 0;
+               }
+       }
+
+       return -ESRCH;
+}
+
+static void bcm43xx_put_phy_into_reset(struct bcm43xx_wldev *dev)
+{
+       struct ssb_device *sdev = dev->dev;
+       u32 tmslow;
+
+       tmslow = ssb_read32(sdev, SSB_TMSLOW);
+       tmslow &= ~BCM43xx_TMSLOW_GMODE;
+       tmslow |= BCM43xx_TMSLOW_PHYRESET;
+       tmslow |= SSB_TMSLOW_FGC;
+       ssb_write32(sdev, SSB_TMSLOW, tmslow);
+       msleep(1);
+
+       tmslow = ssb_read32(sdev, SSB_TMSLOW);
+       tmslow &= ~SSB_TMSLOW_FGC;
+       tmslow |= BCM43xx_TMSLOW_PHYRESET;
+       ssb_write32(sdev, SSB_TMSLOW, tmslow);
+       msleep(1);
+}
+
+static int bcm43xx_switch_phymode(struct bcm43xx_wl *wl,
+                                 unsigned int new_mode)
+{
+       struct bcm43xx_wldev *up_dev;
+       struct bcm43xx_wldev *down_dev;
+       int err;
+       int gmode = -1;
+       int old_was_started = 0;
+       int old_was_inited = 0;
+
+       err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
+       if (err) {
+               printk(KERN_INFO PFX "Could not find a device for %s-PHY mode\n",
+                      phymode_to_string(new_mode));
+               return err;
+       }
+       assert(gmode == 0 || gmode == 1);
+       if ((up_dev == wl->current_dev) &&
+           (wl->current_dev->phy.gmode == gmode)) {
+               /* This device is already running. */
+               return 0;
+       }
+       dprintk(KERN_INFO PFX "Reconfiguring PHYmode to %s-PHY\n",
+               phymode_to_string(new_mode));
+       down_dev = wl->current_dev;
+
+       /* Shutdown the currently running core. */
+       if (down_dev->started) {
+               old_was_started = 1;
+               bcm43xx_wireless_core_stop(down_dev);
+       }
+       if (bcm43xx_status(down_dev) == BCM43xx_STAT_INITIALIZED) {
+               old_was_inited = 1;
+               bcm43xx_wireless_core_exit(down_dev);
+       }
+
+       if (down_dev != up_dev) {
+               /* We switch to a different core, so we put PHY into
+                * RESET on the old core. */
+               bcm43xx_put_phy_into_reset(down_dev);
+       }
+
+       /* Now start the new core. */
+       up_dev->phy.gmode = gmode;
+       if (old_was_inited) {
+               err = bcm43xx_wireless_core_init(up_dev);
+               if (err) {
+                       printk(KERN_INFO PFX "Fatal: Could not initialize device for "
+                              "new selected %s-PHY mode\n",
+                              phymode_to_string(new_mode));
+                       return err;
+               }
+       }
+       if (old_was_started) {
+               assert(old_was_inited);
+               err = bcm43xx_wireless_core_start(up_dev);
+               if (err) {
+                       printk(KERN_INFO PFX "Fatal: Coult not start device for "
+                              "new selected %s-PHY mode\n",
+                              phymode_to_string(new_mode));
+                       bcm43xx_wireless_core_exit(up_dev);
+                       return err;
+               }
+       }
+
+       wl->current_dev = up_dev;
+
+       return 0;
+}
+
+static int bcm43xx_antenna_from_ieee80211(u8 antenna)
+{
+       switch (antenna) {
+       case 0: /* default/diversity */
+               return BCM43xx_ANTENNA_DEFAULT;
+       case 1: /* Antenna 0 */
+               return BCM43xx_ANTENNA0;
+       case 2: /* Antenna 1 */
+               return BCM43xx_ANTENNA1;
+       default:
+               return BCM43xx_ANTENNA_DEFAULT;
+       }
+}
+
+static int bcm43xx_dev_config(struct ieee80211_hw *hw,
+                             struct ieee80211_conf *conf)
+{
+       struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
+       struct bcm43xx_wldev *dev;
+       struct bcm43xx_phy *phy;
+       unsigned long flags;
+       unsigned int new_phymode = 0xFFFF;
+       int antenna_tx;
+       int antenna_rx;
+       int err = 0;
+
+       antenna_tx = bcm43xx_antenna_from_ieee80211(conf->antenna_sel_tx);
+       antenna_rx = bcm43xx_antenna_from_ieee80211(conf->antenna_sel_rx);
+
+       mutex_lock(&wl->mutex);
+
+       /* Switch the PHY mode (if necessary). */
+       switch (conf->phymode) {
+       case MODE_IEEE80211A:
+               new_phymode = BCM43xx_PHYMODE_A;
+               break;
+       case MODE_IEEE80211B:
+               new_phymode = BCM43xx_PHYMODE_B;
+               break;
+       case MODE_IEEE80211G:
+               new_phymode = BCM43xx_PHYMODE_G;
+               break;
+       default:
+               assert(0);
+       }
+       err = bcm43xx_switch_phymode(wl, new_phymode);
+       if (err)
+               goto out_unlock_mutex;
+       dev = wl->current_dev;
+       phy = &dev->phy;
+
+       spin_lock_irqsave(&wl->irq_lock, flags);
+       if (bcm43xx_status(dev) != BCM43xx_STAT_INITIALIZED)
+               goto out_unlock;
+
+       /* Switch to the requested channel. */
+       if (conf->channel_val != phy->channel)
+               bcm43xx_radio_selectchannel(dev, conf->channel_val, 0);
+
+       /* Enable/Disable ShortSlot timing. */
+       if (!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) != dev->short_slot) {
+               assert(phy->type == BCM43xx_PHYTYPE_G);
+               if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
+                       bcm43xx_short_slot_timing_enable(dev);
+               else
+                       bcm43xx_short_slot_timing_disable(dev);
+       }
+
+       /* Adjust the desired TX power level. */
+       if (conf->power_level != 0) {
+               if (conf->power_level != phy->power_level) {
+                       phy->power_level = conf->power_level;
+                       bcm43xx_phy_xmitpower(dev);
+               }
+       }
+
+       /* Hide/Show the SSID (AP mode only). */
+       if (conf->flags & IEEE80211_CONF_SSID_HIDDEN) {
+               bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD,
+                               bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD)
+                               | BCM43xx_SBF_NO_SSID_BCAST);
+       } else {
+               bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD,
+                               bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD)
+                               & ~BCM43xx_SBF_NO_SSID_BCAST);
+       }
+
+       /* Antennas for RX and management frame TX. */
+       bcm43xx_mgmtframe_txantenna(dev, antenna_tx);
+       bcm43xx_set_rx_antenna(dev, antenna_rx);
+
+       /* Update templates for AP mode. */
+       if (bcm43xx_is_mode(wl, IEEE80211_IF_TYPE_AP))
+               bcm43xx_set_beacon_int(dev, conf->beacon_int);
+
+out_unlock:
+       spin_unlock_irqrestore(&wl->irq_lock, flags);
+out_unlock_mutex:
+       mutex_unlock(&wl->mutex);
+
+       return err;
+}
+
+static int bcm43xx_dev_set_key(struct ieee80211_hw *hw,
+                              set_key_cmd cmd,
+                              u8 *addr,
+                              struct ieee80211_key_conf *key,
+                              int aid)
+{
+       struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
+       struct bcm43xx_wldev *dev = wl->current_dev;
+       unsigned long flags;
+       u8 algorithm;
+       u8 index;
+       int err = -EINVAL;
+
+       if (!dev)
+               return -ENODEV;
+       switch (key->alg) {
+       case ALG_NONE:
+       case ALG_NULL:
+               algorithm = BCM43xx_SEC_ALGO_NONE;
+               break;
+       case ALG_WEP:
+               if (key->keylen == 5)
+                       algorithm = BCM43xx_SEC_ALGO_WEP40;
+               else
+                       algorithm = BCM43xx_SEC_ALGO_WEP104;
+               break;
+       case ALG_TKIP:
+               algorithm = BCM43xx_SEC_ALGO_TKIP;
+               break;
+       case ALG_CCMP:
+               algorithm = BCM43xx_SEC_ALGO_AES;
+               break;
+       default:
+               assert(0);
+               goto out;
+       }
+
+       index = (u8)(key->keyidx);
+       if (index > 3)
+               goto out;
+
+       mutex_lock(&wl->mutex);
+       spin_lock_irqsave(&wl->irq_lock, flags);
+
+       if (bcm43xx_status(dev) != BCM43xx_STAT_INITIALIZED) {
+               err = -ENODEV;
+               goto out_unlock;
+       }
+
+       switch (cmd) {
+       case SET_KEY:
+               key->flags &= ~IEEE80211_KEY_FORCE_SW_ENCRYPT;
+
+               if (algorithm == BCM43xx_SEC_ALGO_TKIP) {
+                       /* FIXME: No TKIP hardware encryption for now. */
+                       key->flags |= IEEE80211_KEY_FORCE_SW_ENCRYPT;
+               }
+
+               if (is_broadcast_ether_addr(addr)) {
+                       /* addr is FF:FF:FF:FF:FF:FF for default keys */
+                       err = bcm43xx_key_write(dev, index, algorithm,
+                                               key->key, key->keylen,
+                                               NULL, key);
+               } else {
+                       err = bcm43xx_key_write(dev, -1, algorithm,
+                                               key->key, key->keylen,
+                                               addr, key);
+               }
+               if (err) {
+                       key->flags |= IEEE80211_KEY_FORCE_SW_ENCRYPT;
+                       goto out_unlock;
+               }
+               dev->key[key->hw_key_idx].enabled = 1;
+
+               if (algorithm == BCM43xx_SEC_ALGO_WEP40 ||
+                   algorithm == BCM43xx_SEC_ALGO_WEP104) {
+                       bcm43xx_hf_write(dev,
+                                        bcm43xx_hf_read(dev) |
+                                        BCM43xx_HF_USEDEFKEYS);
+               } else {
+                       bcm43xx_hf_write(dev,
+                                        bcm43xx_hf_read(dev) &
+                                        ~BCM43xx_HF_USEDEFKEYS);
+               }
+               break;
+       case DISABLE_KEY: {
+               static const u8 zero[BCM43xx_SEC_KEYSIZE] = { 0 };
+
+               algorithm = BCM43xx_SEC_ALGO_NONE;
+               if (is_broadcast_ether_addr(addr)) {
+                       err = bcm43xx_key_write(dev, index, algorithm,
+                                               zero, BCM43xx_SEC_KEYSIZE,
+                                               NULL, key);
+               } else {
+                       err = bcm43xx_key_write(dev, -1, algorithm,
+                                               zero, BCM43xx_SEC_KEYSIZE,
+                                               addr, key);
+               }
+               dev->key[key->hw_key_idx].enabled = 0;
+               break;
+       }
+       case REMOVE_ALL_KEYS:
+               bcm43xx_clear_keys(dev);
+               err = 0;
+               break;
+       default:
+               assert(0);
+       }
+out_unlock:
+       spin_unlock_irqrestore(&wl->irq_lock, flags);
+       mutex_unlock(&wl->mutex);
+out:
+       if (!err) {
+               dprintk(KERN_DEBUG PFX "Using %s based encryption for keyidx: %d, "
+                       "mac: " MAC_FMT "\n",
+                       (key->flags & IEEE80211_KEY_FORCE_SW_ENCRYPT) ?
+                       "software" : "hardware",
+                       key->keyidx, MAC_ARG(addr));
+       }
+       return err;
+}
+
+static void bcm43xx_set_multicast_list(struct ieee80211_hw *hw,
+                                      unsigned short netflags,
+                                      int mc_count)
+{
+       struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
+       struct bcm43xx_wldev *dev = wl->current_dev;
+       unsigned long flags;
+
+       if (!dev)
+               return;
+       spin_lock_irqsave(&wl->irq_lock, flags);
+       if (wl->promisc != !!(netflags & IFF_PROMISC)) {
+               wl->promisc = !!(netflags & IFF_PROMISC);
+               if (bcm43xx_status(dev) == BCM43xx_STAT_INITIALIZED)
+                       bcm43xx_adjust_opmode(dev);
+       }
+       spin_unlock_irqrestore(&wl->irq_lock, flags);
+}
+
+static int bcm43xx_config_interface(struct ieee80211_hw *hw,
+                                   int if_id,
+                                   struct ieee80211_if_conf *conf)
+{
+       struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
+       struct bcm43xx_wldev *dev = wl->current_dev;
+       unsigned long flags;
+
+       if (!dev)
+               return -ENODEV;
+       mutex_lock(&wl->mutex);
+       spin_lock_irqsave(&wl->irq_lock, flags);
+       if (conf->type != IEEE80211_IF_TYPE_MNTR) {
+               assert(wl->if_id == if_id);
+               wl->bssid = conf->bssid;
+               if (bcm43xx_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
+                       assert(conf->type == IEEE80211_IF_TYPE_AP);
+                       bcm43xx_set_ssid(dev, conf->ssid, conf->ssid_len);
+                       if (conf->beacon)
+                               bcm43xx_refresh_templates(dev, conf->beacon);
+               }
+       }
+       spin_unlock_irqrestore(&wl->irq_lock, flags);
+       mutex_unlock(&wl->mutex);
+
+       return 0;
+}
+
+/* Locking: wl->mutex */
+static void bcm43xx_wireless_core_stop(struct bcm43xx_wldev *dev)
+{
+       struct bcm43xx_wl *wl = dev->wl;
+       unsigned long flags;
+
+       if (!dev->started)
+               return;
+
+       mutex_unlock(&wl->mutex);
+       bcm43xx_periodic_tasks_delete(dev);
+       flush_scheduled_work();
+       mutex_lock(&wl->mutex);
+
+       ieee80211_stop_queues(wl->hw);
+
+       /* Disable and sync interrupts. */
+       spin_lock_irqsave(&wl->irq_lock, flags);
+       dev->irq_savedstate = bcm43xx_interrupt_disable(dev, BCM43xx_IRQ_ALL);
+       bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_MASK); /* flush */
+       spin_unlock_irqrestore(&wl->irq_lock, flags);
+       bcm43xx_synchronize_irq(dev);
+
+       bcm43xx_mac_suspend(dev);
+       free_irq(dev->dev->irq, dev);
+       dev->started = 0;
+       dprintk(KERN_INFO PFX "Wireless interface stopped\n");
+}
+
+/* Locking: wl->mutex */
+static int bcm43xx_wireless_core_start(struct bcm43xx_wldev *dev)
+{
+       struct bcm43xx_wl *wl =