Merge xburst target.
authorLars-Peter Clausen <lars@metafoo.de>
Mon, 11 Jan 2010 04:44:45 +0000 (04:44 +0000)
committerLars-Peter Clausen <lars@metafoo.de>
Mon, 11 Jan 2010 04:44:45 +0000 (04:44 +0000)
SVN-Revision: 19098

84 files changed:
target/linux/xburst/Makefile [new file with mode: 0644]
target/linux/xburst/base-files/etc/config/fstab [new file with mode: 0644]
target/linux/xburst/base-files/etc/config/network [new file with mode: 0755]
target/linux/xburst/base-files/etc/config/system [new file with mode: 0644]
target/linux/xburst/config-2.6.32 [new file with mode: 0644]
target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/Makefile [new file with mode: 0644]
target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/dummy.c [new file with mode: 0644]
target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/head.S [new file with mode: 0644]
target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/ld.script [new file with mode: 0644]
target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/misc.c [new file with mode: 0644]
target/linux/xburst/files-2.6.32/arch/mips/boot/tools/entry [new file with mode: 0644]
target/linux/xburst/files-2.6.32/arch/mips/boot/tools/filesize [new file with mode: 0644]
target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/board-qi_lb60.h [new file with mode: 0644]
target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/clock.h [new file with mode: 0644]
target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/dma.h [new file with mode: 0644]
target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/gpio.h [new file with mode: 0644]
target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/irq.h [new file with mode: 0644]
target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/jz4740.h [new file with mode: 0644]
target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/platform.h [new file with mode: 0644]
target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/regs.h [new file with mode: 0644]
target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/serial.h [new file with mode: 0644]
target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/timer.h [new file with mode: 0644]
target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/war.h [new file with mode: 0644]
target/linux/xburst/files-2.6.32/arch/mips/jz4740/Kconfig [new file with mode: 0644]
target/linux/xburst/files-2.6.32/arch/mips/jz4740/Makefile [new file with mode: 0644]
target/linux/xburst/files-2.6.32/arch/mips/jz4740/board-n526.c [new file with mode: 0644]
target/linux/xburst/files-2.6.32/arch/mips/jz4740/board-qi_lb60.c [new file with mode: 0644]
target/linux/xburst/files-2.6.32/arch/mips/jz4740/clock.c [new file with mode: 0644]
target/linux/xburst/files-2.6.32/arch/mips/jz4740/dma.c [new file with mode: 0644]
target/linux/xburst/files-2.6.32/arch/mips/jz4740/gpio.c [new file with mode: 0644]
target/linux/xburst/files-2.6.32/arch/mips/jz4740/irq.c [new file with mode: 0644]
target/linux/xburst/files-2.6.32/arch/mips/jz4740/platform.c [new file with mode: 0644]
target/linux/xburst/files-2.6.32/arch/mips/jz4740/pm.c [new file with mode: 0644]
target/linux/xburst/files-2.6.32/arch/mips/jz4740/prom.c [new file with mode: 0644]
target/linux/xburst/files-2.6.32/arch/mips/jz4740/reset.c [new file with mode: 0644]
target/linux/xburst/files-2.6.32/arch/mips/jz4740/setup.c [new file with mode: 0644]
target/linux/xburst/files-2.6.32/arch/mips/jz4740/time.c [new file with mode: 0644]
target/linux/xburst/files-2.6.32/drivers/char/defkeymap.c [new file with mode: 0644]
target/linux/xburst/files-2.6.32/drivers/i2c/chips/n526-lpc.c [new file with mode: 0644]
target/linux/xburst/files-2.6.32/drivers/misc/jz4740-adc.c [new file with mode: 0644]
target/linux/xburst/files-2.6.32/drivers/mmc/host/jz_mmc.c [new file with mode: 0644]
target/linux/xburst/files-2.6.32/drivers/mtd/nand/jz4740_nand.c [new file with mode: 0644]
target/linux/xburst/files-2.6.32/drivers/power/jz4740-battery.c [new file with mode: 0644]
target/linux/xburst/files-2.6.32/drivers/rtc/rtc-jz4740.c [new file with mode: 0644]
target/linux/xburst/files-2.6.32/drivers/usb/gadget/jz4740_udc.c [new file with mode: 0644]
target/linux/xburst/files-2.6.32/drivers/usb/gadget/jz4740_udc.h [new file with mode: 0644]
target/linux/xburst/files-2.6.32/drivers/video/backlight/gpm940b0.c [new file with mode: 0644]
target/linux/xburst/files-2.6.32/drivers/video/jz4740_fb.c [new file with mode: 0644]
target/linux/xburst/files-2.6.32/include/linux/jz4740-adc.h [new file with mode: 0644]
target/linux/xburst/files-2.6.32/include/linux/jz4740_fb.h [new file with mode: 0644]
target/linux/xburst/files-2.6.32/include/linux/mmc/jz4740_mmc.h [new file with mode: 0644]
target/linux/xburst/files-2.6.32/include/linux/mtd/jz4740_nand.h [new file with mode: 0644]
target/linux/xburst/files-2.6.32/include/linux/power/jz4740-battery.h [new file with mode: 0644]
target/linux/xburst/files-2.6.32/sound/soc/codecs/jzcodec.c [new file with mode: 0644]
target/linux/xburst/files-2.6.32/sound/soc/codecs/jzcodec.h [new file with mode: 0644]
target/linux/xburst/files-2.6.32/sound/soc/jz4740/Kconfig [new file with mode: 0644]
target/linux/xburst/files-2.6.32/sound/soc/jz4740/Makefile [new file with mode: 0644]
target/linux/xburst/files-2.6.32/sound/soc/jz4740/jz4740-i2s.c [new file with mode: 0644]
target/linux/xburst/files-2.6.32/sound/soc/jz4740/jz4740-i2s.h [new file with mode: 0644]
target/linux/xburst/files-2.6.32/sound/soc/jz4740/jz4740-pcm.c [new file with mode: 0644]
target/linux/xburst/files-2.6.32/sound/soc/jz4740/jz4740-pcm.h [new file with mode: 0644]
target/linux/xburst/files-2.6.32/sound/soc/jz4740/n526.c [new file with mode: 0644]
target/linux/xburst/files-2.6.32/sound/soc/jz4740/qi_lb60.c [new file with mode: 0644]
target/linux/xburst/image/Makefile [new file with mode: 0644]
target/linux/xburst/image/ubinize.cfg [new file with mode: 0644]
target/linux/xburst/modules.mk [new file with mode: 0644]
target/linux/xburst/patches-2.6.32/001-core.patch [new file with mode: 0644]
target/linux/xburst/patches-2.6.32/050-nand.patch [new file with mode: 0644]
target/linux/xburst/patches-2.6.32/051-fb.patch [new file with mode: 0644]
target/linux/xburst/patches-2.6.32/052-rtc.patch [new file with mode: 0644]
target/linux/xburst/patches-2.6.32/053-adc.patch [new file with mode: 0644]
target/linux/xburst/patches-2.6.32/100-battery.patch [new file with mode: 0644]
target/linux/xburst/patches-2.6.32/101-mmc.patch [new file with mode: 0644]
target/linux/xburst/patches-2.6.32/103-lcm.patch [new file with mode: 0644]
target/linux/xburst/patches-2.6.32/103-serial.patch [new file with mode: 0644]
target/linux/xburst/patches-2.6.32/104-usb.patch [new file with mode: 0644]
target/linux/xburst/patches-2.6.32/105-sound.patch [new file with mode: 0644]
target/linux/xburst/patches-2.6.32/220-add-2gb-nand-support.patch [new file with mode: 0644]
target/linux/xburst/patches-2.6.32/300-jffs2-summery-vmalloc.patch [new file with mode: 0644]
target/linux/xburst/patches-2.6.32/400-spi-gpio-3wire.patch [new file with mode: 0644]
target/linux/xburst/patches-2.6.32/420-fb-notifier-pre-post.patch [new file with mode: 0644]
target/linux/xburst/patches-2.6.32/500-modifier-keys.patch [new file with mode: 0644]
target/linux/xburst/patches-2.6.32/800-n526-lpc.patch [new file with mode: 0644]
target/linux/xburst/patches-2.6.32/900-add-openwrt-logo.patch [new file with mode: 0644]

diff --git a/target/linux/xburst/Makefile b/target/linux/xburst/Makefile
new file mode 100644 (file)
index 0000000..7043be0
--- /dev/null
@@ -0,0 +1,28 @@
+#
+# Copyright (C) 2009-2010 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+include $(TOPDIR)/rules.mk
+
+ARCH:=mipsel
+BOARD:=xburst
+BOARDNAME:=XBurst JZ47x0
+FEATURES:=jffs2 tgz ubifs
+
+LINUX_VERSION:=2.6.32
+
+DEVICE_TYPE=other
+
+include $(INCLUDE_DIR)/target.mk
+
+KERNELNAME:=uImage
+
+DEFAULT_PACKAGES += gpioctl
+
+define Target/Description
+       Build firmware images for XBurst JZ47x0 based boards.
+endef
+
+$(eval $(call BuildTarget))
diff --git a/target/linux/xburst/base-files/etc/config/fstab b/target/linux/xburst/base-files/etc/config/fstab
new file mode 100644 (file)
index 0000000..5223561
--- /dev/null
@@ -0,0 +1,6 @@
+config mount
+       option target   /card
+       option device   /dev/mmcblk0p1
+       option fstype   auto
+       option options  rw,sync
+       option enabled  1
diff --git a/target/linux/xburst/base-files/etc/config/network b/target/linux/xburst/base-files/etc/config/network
new file mode 100755 (executable)
index 0000000..a086003
--- /dev/null
@@ -0,0 +1,13 @@
+# Copyright (C) 2006 OpenWrt.org
+
+config interface loopback
+       option ifname   lo
+       option proto    static
+       option ipaddr   127.0.0.1
+       option netmask  255.0.0.0
+
+config interface lan
+       option ifname   usb0
+       option proto    static
+       option ipaddr   192.168.1.1
+       option netmask  255.255.255.0
diff --git a/target/linux/xburst/base-files/etc/config/system b/target/linux/xburst/base-files/etc/config/system
new file mode 100644 (file)
index 0000000..e198966
--- /dev/null
@@ -0,0 +1,3 @@
+config system
+       option hostname BenNanoNote     
+       option timezone UTC
diff --git a/target/linux/xburst/config-2.6.32 b/target/linux/xburst/config-2.6.32
new file mode 100644 (file)
index 0000000..6b04207
--- /dev/null
@@ -0,0 +1,403 @@
+CONFIG_32BIT=y
+# CONFIG_64BIT is not set
+# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
+# CONFIG_AR7 is not set
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_ARPD is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_BATTERY_JZ4740=y
+# CONFIG_BCM47XX is not set
+# CONFIG_BCM63XX is not set
+CONFIG_BITREVERSE=y
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
+# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
+CONFIG_CFG80211_DEFAULT_PS_VALUE=0
+CONFIG_CONSOLE_TRANSLATIONS=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+# CONFIG_CPU_CAVIUM_OCTEON is not set
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+# CONFIG_CPU_LOONGSON2E is not set
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPS32_R1=y
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+CONFIG_CPU_MIPSR1=y
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R5500 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_VR41XX is not set
+CONFIG_CRC16=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_DEFAULT_TCP_CONG="cubic"
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_ELF_CORE=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+CONFIG_FAT_FS=y
+CONFIG_FB=y
+CONFIG_FB_JZ4740=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+# CONFIG_FIRMWARE_EDID is not set
+CONFIG_FONTS=y
+# CONFIG_FONT_10x18 is not set
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_8x16 is not set
+# CONFIG_FONT_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_SUN12x22 is not set
+CONFIG_FONT_SUN8x16=y
+CONFIG_FORCE_MAX_ZONEORDER=12
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FREEZER=y
+# CONFIG_FSNOTIFY is not set
+# CONFIG_FW_LOADER is not set
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_GPIOLIB=y
+# CONFIG_GPIO_MC33880 is not set
+# CONFIG_HAMRADIO is not set
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HIBERNATION is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_HW_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_GPIO_BUTTONS is not set
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_INPUT_YEALINK is not set
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_MULTICAST is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_RARP is not set
+CONFIG_IRQ_CPU=y
+# CONFIG_ISDN is not set
+CONFIG_JBD=y
+CONFIG_JZ4740_ADC=y
+# CONFIG_JZ4740_N526 is not set
+CONFIG_JZ4740_QI_LB60=y
+CONFIG_JZRISC=y
+CONFIG_JZSOC=y
+CONFIG_KALLSYMS=y
+CONFIG_KEYBOARD_ATKBD=y
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_LKKBD is not set
+CONFIG_KEYBOARD_MATRIX=y
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_LCD_GPM940B0=y
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_LMS283GF05 is not set
+# CONFIG_LCD_LTV350QV is not set
+# CONFIG_LCD_PLATFORM is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=2
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_CLUT224 is not set
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOGO_OPENWRT_CLUT224=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+# CONFIG_MACH_ALCHEMY is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+CONFIG_MACH_JZ=y
+# CONFIG_MACH_LOONGSON is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_MINI_FO is not set
+CONFIG_MIPS=y
+# CONFIG_MIPS_COBALT is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_MACHINE is not set
+# CONFIG_MIPS_MALTA is not set
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+# CONFIG_MIPS_SIM is not set
+CONFIG_MMC=y
+# CONFIG_MMC_AT91 is not set
+# CONFIG_MMC_ATMELMCI is not set
+CONFIG_MMC_BLOCK=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
+CONFIG_MMC_JZ=y
+CONFIG_MMC_UNSAFE_RESUME=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_JZ4740=y
+CONFIG_MTD_NAND_VERIFY_WRITE=y
+# CONFIG_MTD_SST25L is not set
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_DEBUG is not set
+# CONFIG_MTD_UBI_GLUEBI is not set
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+# CONFIG_NET_ETHERNET is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_NLS=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_CODEPAGE_1250=y
+CONFIG_NLS_CODEPAGE_1251=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=y
+CONFIG_NLS_CODEPAGE_775=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_855=y
+CONFIG_NLS_CODEPAGE_857=y
+CONFIG_NLS_CODEPAGE_860=y
+CONFIG_NLS_CODEPAGE_861=y
+CONFIG_NLS_CODEPAGE_862=y
+CONFIG_NLS_CODEPAGE_863=y
+CONFIG_NLS_CODEPAGE_864=y
+CONFIG_NLS_CODEPAGE_865=y
+CONFIG_NLS_CODEPAGE_866=y
+CONFIG_NLS_CODEPAGE_869=y
+CONFIG_NLS_CODEPAGE_874=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_949=y
+CONFIG_NLS_CODEPAGE_950=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_13=y
+CONFIG_NLS_ISO8859_14=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_3=y
+CONFIG_NLS_ISO8859_4=y
+CONFIG_NLS_ISO8859_5=y
+CONFIG_NLS_ISO8859_6=y
+CONFIG_NLS_ISO8859_7=y
+CONFIG_NLS_ISO8859_8=y
+CONFIG_NLS_ISO8859_9=y
+CONFIG_NLS_KOI8_R=y
+CONFIG_NLS_KOI8_U=y
+CONFIG_NLS_UTF8=y
+# CONFIG_NO_IOPORT is not set
+# CONFIG_NXP_STB220 is not set
+# CONFIG_NXP_STB225 is not set
+# CONFIG_PACKET_MMAP is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_PCSPKR_PLATFORM=y
+# CONFIG_PDA_POWER is not set
+CONFIG_PM=y
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_PM_DEBUG is not set
+# CONFIG_PM_RUNTIME is not set
+CONFIG_PM_SLEEP=y
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+CONFIG_PREEMPT=y
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PRINTK_TIME=y
+CONFIG_RELAY=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DRV_CMOS is not set
+CONFIG_RTC_DRV_JZ4740=y
+# CONFIG_RTC_DRV_PCF2123 is not set
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SDIO_UART is not set
+CONFIG_SECCOMP=y
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIO=y
+# CONFIG_SERIO_I8042 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_SWARM is not set
+CONFIG_SND=y
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_JACK=y
+CONFIG_SND_JZ4740_SOC=y
+CONFIG_SND_JZ4740_SOC_I2S=y
+CONFIG_SND_JZ4740_SOC_QI_LB60=y
+CONFIG_SND_MIXER_OSS=y
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+CONFIG_SND_PCM=y
+CONFIG_SND_PCM_OSS=y
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+CONFIG_SND_SOC=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_I2C_AND_SPI=y
+CONFIG_SND_SOC_JZCODEC=y
+CONFIG_SND_TIMER=y
+# CONFIG_SND_VERBOSE_PROCFS is not set
+CONFIG_SOC_JZ4740=y
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+# CONFIG_SOUND_OSS_CORE_PRECLAIM is not set
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_GPIO=y
+CONFIG_SPI_MASTER=y
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_STAGING is not set
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_SYN_COOKIES is not set
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_TRAD_SIGNALS=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+CONFIG_TREE_RCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
+# CONFIG_UBIFS_FS_DEBUG is not set
+CONFIG_UBIFS_FS_LZO=y
+# CONFIG_UBIFS_FS_XATTR is not set
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+CONFIG_USB_ETH=y
+# CONFIG_USB_ETH_EEM is not set
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_FILE_STORAGE is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_IMX is not set
+CONFIG_USB_GADGET_JZ4740=y
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+CONFIG_USB_GADGET_SELECTED=y
+CONFIG_USB_GADGET_VBUS_DRAW=2
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_G_SERIAL is not set
+CONFIG_USB_JZ4740=y
+# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_ZERO is not set
+CONFIG_VFAT_FS=y
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_VLAN_8021Q is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_WATCHDOG is not set
+# CONFIG_WLAN_80211 is not set
+CONFIG_ZONE_DMA_FLAG=0
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/Makefile b/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/Makefile
new file mode 100644 (file)
index 0000000..9b41329
--- /dev/null
@@ -0,0 +1,42 @@
+#\r
+# linux/arch/mips/boot/compressed/Makefile\r
+#\r
+# create a compressed zImage from the original vmlinux\r
+#\r
+\r
+targets                := zImage vmlinuz vmlinux.bin.gz head.o misc.o piggy.o dummy.o\r
+\r
+OBJS           := $(obj)/head.o $(obj)/misc.o\r
+\r
+LD_ARGS        := -T $(obj)/ld.script -Ttext 0x80600000 -Bstatic\r
+OBJCOPY_ARGS   := -O elf32-tradlittlemips\r
+\r
+ENTRY          := $(obj)/../tools/entry\r
+FILESIZE       := $(obj)/../tools/filesize\r
+\r
+drop-sections  = .reginfo .mdebug .comment .note .pdr .options .MIPS.options\r
+strip-flags    = $(addprefix --remove-section=,$(drop-sections))\r
+\r
+\r
+$(obj)/vmlinux.bin.gz: vmlinux\r
+       rm -f $(obj)/vmlinux.bin.gz\r
+       $(OBJCOPY) -O binary $(strip-flags) vmlinux $(obj)/vmlinux.bin\r
+       gzip -v9f $(obj)/vmlinux.bin\r
+\r
+$(obj)/head.o: $(obj)/head.S $(obj)/vmlinux.bin.gz vmlinux\r
+       $(CC) $(KBUILD_AFLAGS) \\r
+       -DIMAGESIZE=$(shell sh $(FILESIZE) $(obj)/vmlinux.bin.gz) \\r
+       -DKERNEL_ENTRY=$(shell sh $(ENTRY) $(NM) vmlinux ) \\r
+       -DLOADADDR=$(loadaddr) \\r
+       -c -o $(obj)/head.o $<\r
+\r
+$(obj)/vmlinuz: $(OBJS) $(obj)/ld.script $(obj)/vmlinux.bin.gz $(obj)/dummy.o\r
+       $(OBJCOPY) \\r
+               --add-section=.image=$(obj)/vmlinux.bin.gz \\r
+               --set-section-flags=.image=contents,alloc,load,readonly,data \\r
+               $(obj)/dummy.o $(obj)/piggy.o\r
+       $(LD) $(LD_ARGS) -o $@ $(OBJS) $(obj)/piggy.o\r
+       $(OBJCOPY) $(OBJCOPY_ARGS) $@ $@ -R .comment -R .stab -R .stabstr -R .initrd -R .sysmap\r
+\r
+zImage: $(obj)/vmlinuz\r
+       $(OBJCOPY) -O binary $(obj)/vmlinuz $(obj)/zImage       \r
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/dummy.c b/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/dummy.c
new file mode 100644 (file)
index 0000000..31dbf45
--- /dev/null
@@ -0,0 +1,4 @@
+int main(void)
+{
+       return 0;
+}
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/head.S b/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/head.S
new file mode 100644 (file)
index 0000000..d9700eb
--- /dev/null
@@ -0,0 +1,85 @@
+/*
+ *  linux/arch/mips/boot/compressed/head.S
+ *
+ *  Copyright (C) 2005-2008 Ingenic Semiconductor Inc.
+ */
+
+#include <asm/asm.h>
+#include <asm/cacheops.h>
+#include <asm/cachectl.h>
+#include <asm/regdef.h>
+
+#define IndexInvalidate_I       0x00
+#define IndexWriteBack_D        0x01
+
+       .set noreorder
+       LEAF(startup)
+startup:
+       move    s0, a0          /* Save the boot loader transfered args */
+       move    s1, a1
+       move    s2, a2
+       move    s3, a3
+
+       la      a0, _edata
+       la      a1, _end
+1:     sw      zero, 0(a0)     /* Clear BSS section */
+       bne     a1, a0, 1b
+       addu    a0, 4
+
+       la      sp, (.stack + 8192)
+
+       la      a0, __image_begin
+       la      a1, IMAGESIZE
+       la      a2, LOADADDR
+       la      ra, 1f
+       la      k0, decompress_kernel
+       jr      k0
+       nop
+1:
+
+       move    a0, s0
+       move    a1, s1
+       move    a2, s2
+       move    a3, s3
+       li      k0, KERNEL_ENTRY
+       jr      k0
+       nop
+2:
+       b 32
+       END(startup)
+
+
+       LEAF(flushcaches)
+       la      t0, 1f
+       la      t1, 0xa0000000
+       or      t0, t0, t1
+       jr      t0
+       nop
+1:
+       li      k0, 0x80000000  # start address
+       li      k1, 0x80004000  # end address (16KB I-Cache)
+       subu    k1, 128
+
+2:
+       .set mips3
+       cache   IndexWriteBack_D, 0(k0)
+       cache   IndexWriteBack_D, 32(k0)
+       cache   IndexWriteBack_D, 64(k0)
+       cache   IndexWriteBack_D, 96(k0)
+       cache   IndexInvalidate_I, 0(k0)
+       cache   IndexInvalidate_I, 32(k0)
+       cache   IndexInvalidate_I, 64(k0)
+       cache   IndexInvalidate_I, 96(k0)
+       .set mips0
+
+       bne     k0, k1, 2b
+       addu    k0, k0, 128
+       la      t0, 3f
+       jr      t0
+       nop
+3:
+       jr      ra
+       nop
+       END(flushcaches)
+
+       .comm .stack,4096*2,4
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/ld.script b/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/ld.script
new file mode 100644 (file)
index 0000000..fcf8ba0
--- /dev/null
@@ -0,0 +1,151 @@
+OUTPUT_ARCH(mips)
+ENTRY(startup)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+
+  .init          : { *(.init)          } =0
+  .text      :
+  {
+    _ftext = . ;
+    *(.text)
+    *(.rodata)
+    *(.rodata1)
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+  } =0
+  .kstrtab : { *(.kstrtab) }
+
+  . = ALIGN(16);               /* Exception table */
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  __start___dbe_table = .;     /* Exception table for data bus errors */
+  __dbe_table : { *(__dbe_table) }
+  __stop___dbe_table = .;
+
+  __start___ksymtab = .;       /* Kernel symbol table */
+  __ksymtab : { *(__ksymtab) }
+  __stop___ksymtab = .;
+
+  _etext = .;
+
+  . = ALIGN(8192);
+  .data.init_task : { *(.data.init_task) }
+
+  /* Startup code */
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(16);
+  __setup_start = .;
+  .setup.init : { *(.setup.init) }
+  __setup_end = .;
+  __initcall_start = .;
+  .initcall.init : { *(.initcall.init) }
+  __initcall_end = .;
+  . = ALIGN(4096);     /* Align double page for init_task_union */
+  __init_end = .;
+
+  . = ALIGN(4096);
+  .data.page_aligned : { *(.data.idt) }
+
+  . = ALIGN(32);
+  .data.cacheline_aligned : { *(.data.cacheline_aligned) }
+
+  .fini      : { *(.fini)    } =0
+  .reginfo : { *(.reginfo) }
+  /* Adjust the address for the data segment.  We want to adjust up to
+     the same address within the page on the next page up.  It would
+     be more correct to do this:
+       . = .;
+     The current expression does not correctly handle the case of a
+     text segment ending precisely at the end of a page; it causes the
+     data segment to skip a page.  The above expression does not have
+     this problem, but it will currently (2/95) cause BFD to allocate
+     a single segment, combining both text and data, for this case.
+     This will prevent the text segment from being shared among
+     multiple executions of the program; I think that is more
+     important than losing a page of the virtual address space (note
+     that no actual memory is lost; the page which is skipped can not
+     be referenced).  */
+  . = .;
+  .data    :
+  {
+    _fdata = . ;
+    *(.data)
+
+   /* Put the compressed image here, so bss is on the end. */
+   __image_begin = .;
+   *(.image)
+   __image_end = .;
+   /* Align the initial ramdisk image (INITRD) on page boundaries. */
+   . = ALIGN(4096);
+   __ramdisk_begin = .;
+   *(.initrd)
+   __ramdisk_end = .;
+   . = ALIGN(4096);
+
+    CONSTRUCTORS
+  }
+  .data1   : { *(.data1) }
+  _gp = . + 0x8000;
+  .lit8 : { *(.lit8) }
+  .lit4 : { *(.lit4) }
+  .ctors         : { *(.ctors)   }
+  .dtors         : { *(.dtors)   }
+  .got           : { *(.got.plt) *(.got) }
+  .dynamic       : { *(.dynamic) }
+  /* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .sdata     : { *(.sdata) }
+  . = ALIGN(4);
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __bss_start = .;
+  _fbss = .;
+  .sbss      : { *(.sbss) *(.scommon) }
+  .bss       :
+  {
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   .  = ALIGN(4);
+  _end = . ;
+  PROVIDE (end = .);
+  }
+
+  /* Sections to be discarded */
+  /DISCARD/ :
+  {
+        *(.text.exit)
+        *(.data.exit)
+        *(.exitcall.exit)
+  }
+
+  /* This is the MIPS specific mdebug section.  */
+  .mdebug : { *(.mdebug) }
+  /* These are needed for ELF backends which have not yet been
+     converted to the new style linker.  */
+  .stab 0 : { *(.stab) }
+  .stabstr 0 : { *(.stabstr) }
+  /* DWARF debug sections.
+     Symbols in the .debug DWARF section are relative to the beginning of the
+     section so we begin .debug at 0.  It's not clear yet what needs to happen
+     for the others.   */
+  .debug          0 : { *(.debug) }
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  .line           0 : { *(.line) }
+  /* These must appear regardless of  .  */
+  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
+  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
+  .comment : { *(.comment) }
+  .note : { *(.note) }
+}
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/misc.c b/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/misc.c
new file mode 100644 (file)
index 0000000..2309fee
--- /dev/null
@@ -0,0 +1,242 @@
+/*
+ * linux/arch/mips/boot/compressed/misc.c
+ *
+ * This is a collection of several routines from gzip-1.0.3
+ * adapted for Linux.
+ *
+ * malloc by Hannu Savolainen 1993 and Matthias Urlichs 1994
+ *
+ * Adapted for JZSOC by Peter Wei, 2008
+ *
+ */
+
+#define size_t int
+#define NULL 0
+
+/*
+ * gzip declarations
+ */
+
+#define OF(args)  args
+#define STATIC static
+
+#undef memset
+#undef memcpy
+#define memzero(s, n)     memset ((s), 0, (n))
+
+typedef unsigned char  uch;
+typedef unsigned short ush;
+typedef unsigned long  ulg;
+
+#define WSIZE 0x8000           /* Window size must be at least 32k, */
+                               /* and a power of two */
+
+static uch *inbuf;          /* input buffer */
+static uch window[WSIZE];    /* Sliding window buffer */
+
+static unsigned insize = 0;  /* valid bytes in inbuf */
+static unsigned inptr = 0;   /* index of next byte to be processed in inbuf */
+static unsigned outcnt = 0;  /* bytes in output buffer */
+
+/* gzip flag byte */
+#define ASCII_FLAG   0x01 /* bit 0 set: file probably ASCII text */
+#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part gzip file */
+#define EXTRA_FIELD  0x04 /* bit 2 set: extra field present */
+#define ORIG_NAME    0x08 /* bit 3 set: original file name present */
+#define COMMENT      0x10 /* bit 4 set: file comment present */
+#define ENCRYPTED    0x20 /* bit 5 set: file is encrypted */
+#define RESERVED     0xC0 /* bit 6,7:   reserved */
+
+#define get_byte()  (inptr < insize ? inbuf[inptr++] : fill_inbuf())
+               
+/* Diagnostic functions */
+#ifdef DEBUG
+#  define Assert(cond,msg) {if(!(cond)) error(msg);}
+#  define Trace(x) fprintf x
+#  define Tracev(x) {if (verbose) fprintf x ;}
+#  define Tracevv(x) {if (verbose>1) fprintf x ;}
+#  define Tracec(c,x) {if (verbose && (c)) fprintf x ;}
+#  define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;}
+#else
+#  define Assert(cond,msg)
+#  define Trace(x)
+#  define Tracev(x)
+#  define Tracevv(x)
+#  define Tracec(c,x)
+#  define Tracecv(c,x)
+#endif
+
+static int  fill_inbuf(void);
+static void flush_window(void);
+static void error(char *m);
+static void gzip_mark(void **);
+static void gzip_release(void **);
+
+void* memset(void* s, int c, size_t n);
+void* memcpy(void* __dest, __const void* __src, size_t __n);
+
+extern void flushcaches(void); /* defined in head.S */
+
+char *input_data;
+int input_len;
+
+static long bytes_out = 0;
+static uch *output_data;
+static unsigned long output_ptr = 0;
+
+static void *malloc(int size);
+static void free(void *where);
+static void error(char *m);
+static void gzip_mark(void **);
+static void gzip_release(void **);
+
+static void puts(const char *str)
+{
+}
+
+extern unsigned char _end[];
+static unsigned long free_mem_ptr;
+static unsigned long free_mem_end_ptr;
+#define HEAP_SIZE             0x10000
+
+#include "../../../../lib/inflate.c"
+
+static void *malloc(int size)
+{
+       void *p;
+
+       if (size <0) error("Malloc error\n");
+       if (free_mem_ptr == 0) error("Memory error\n");
+
+       free_mem_ptr = (free_mem_ptr + 3) & ~3; /* Align */
+
+       p = (void *)free_mem_ptr;
+       free_mem_ptr += size;
+
+       if (free_mem_ptr >= free_mem_end_ptr)
+               error("\nOut of memory\n");
+
+       return p;
+}
+
+static void free(void *where)
+{      /* Don't care */
+}
+
+static void gzip_mark(void **ptr)
+{
+       *ptr = (void *) free_mem_ptr;
+}
+
+static void gzip_release(void **ptr)
+{
+       free_mem_ptr = (long) *ptr;
+}
+
+void* memset(void* s, int c, size_t n)
+{
+       int i;
+       char *ss = (char*)s;
+
+       for (i=0;i<n;i++) ss[i] = c;
+       return s;
+}
+
+void* memcpy(void* __dest, __const void* __src, size_t __n)
+{
+       int i = 0;
+       unsigned char *d = (unsigned char *)__dest, *s = (unsigned char *)__src;
+
+       for (i = __n >> 3; i > 0; i--) {
+               *d++ = *s++;
+               *d++ = *s++;
+               *d++ = *s++;
+               *d++ = *s++;
+               *d++ = *s++;
+               *d++ = *s++;
+               *d++ = *s++;
+               *d++ = *s++;
+       }
+
+       if (__n & 1 << 2) {
+               *d++ = *s++;
+               *d++ = *s++;
+               *d++ = *s++;
+               *d++ = *s++;
+       }
+
+       if (__n & 1 << 1) {
+               *d++ = *s++;
+               *d++ = *s++;
+       }
+
+       if (__n & 1)
+               *d++ = *s++;
+
+       return __dest;
+}
+
+/* ===========================================================================
+ * Fill the input buffer. This is called only when the buffer is empty
+ * and at least one byte is really needed.
+ */
+static int fill_inbuf(void)
+{
+       if (insize != 0) {
+               error("ran out of input data\n");
+       }
+
+       inbuf = input_data;
+       insize = input_len;
+       inptr = 1;
+       return inbuf[0];
+}
+
+/* ===========================================================================
+ * Write the output window window[0..outcnt-1] and update crc and bytes_out.
+ * (Used for the decompressed data only.)
+ */
+static void flush_window(void)
+{
+    ulg c = crc;         /* temporary variable */
+    unsigned n;
+    uch *in, *out, ch;
+    
+    in = window;
+    out = &output_data[output_ptr]; 
+    for (n = 0; n < outcnt; n++) {
+           ch = *out++ = *in++;
+           c = crc_32_tab[((int)c ^ ch) & 0xff] ^ (c >> 8);
+    }
+    crc = c;
+    bytes_out += (ulg)outcnt;
+    output_ptr += (ulg)outcnt;
+    outcnt = 0;
+}
+
+static void error(char *x)
+{
+       puts("\n\n");
+       puts(x);
+       puts("\n\n -- System halted");
+
+       while(1);       /* Halt */
+}
+
+void decompress_kernel(unsigned int imageaddr, unsigned int imagesize, unsigned int loadaddr)
+{
+       input_data = (char *)imageaddr;
+       input_len = imagesize;
+       output_ptr = 0;
+       output_data = (uch *)loadaddr;
+       free_mem_ptr = (unsigned long)_end;
+       free_mem_end_ptr = free_mem_ptr + HEAP_SIZE;
+
+       makecrc();
+       puts("Uncompressing Linux...");
+       gunzip();
+       flushcaches();
+       puts("Ok, booting the kernel.");
+}
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/boot/tools/entry b/target/linux/xburst/files-2.6.32/arch/mips/boot/tools/entry
new file mode 100644 (file)
index 0000000..376e822
--- /dev/null
@@ -0,0 +1,12 @@
+#!/bin/sh
+
+# grab the kernel_entry address from the vmlinux elf image
+entry=`$1 $2  | grep kernel_entry`
+
+fs=`echo $entry | grep ffffffff`  # check toolchain output
+
+if [ -n "$fs" ]; then
+       echo "0x"`$1 $2  | grep kernel_entry | cut -c9- | awk '{print $1}'`
+else
+       echo "0x"`$1 $2  | grep kernel_entry | cut -c1- | awk '{print $1}'`
+fi
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/boot/tools/filesize b/target/linux/xburst/files-2.6.32/arch/mips/boot/tools/filesize
new file mode 100644 (file)
index 0000000..2142ad5
--- /dev/null
@@ -0,0 +1,7 @@
+#!/bin/sh
+HOSTNAME=`uname`
+if [ "$HOSTNAME" = "Linux" ]; then
+echo `ls -l $1 | awk '{print $5}'`
+else
+echo `ls -l $1 | awk '{print $6}'`
+fi
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/board-qi_lb60.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/board-qi_lb60.h
new file mode 100644 (file)
index 0000000..e5de9da
--- /dev/null
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2009 Qi Hardware Inc.,
+ * Author: Xiangfu Liu <xiangfu@qi-hardware.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ASM_JZ4740_QI_LB60_H__
+#define __ASM_JZ4740_QI_LB60_H__
+
+#include <linux/gpio.h>
+/*
+ * Frequencies of on-board oscillators
+ */
+#define JZ_EXTAL               12000000  /* Main extal freq: 12 MHz */
+#define JZ_EXTAL_RTC           32768     /* RTC extal freq: 32.768 KHz */
+
+/*
+ * GPIO
+ */
+#define GPIO_DC_DETE_N          JZ_GPIO_PORTC(26)
+#define GPIO_CHARG_STAT_N       JZ_GPIO_PORTC(27)
+#define GPIO_LED_EN             JZ_GPIO_PORTC(28)
+#define GPIO_LCD_CS             JZ_GPIO_PORTC(21)
+#define GPIO_DISP_OFF_N         JZ_GPIO_PORTD(21)
+#define GPIO_PWM                JZ_GPIO_PORTD(27)
+#define GPIO_WAKEUP_N           JZ_GPIO_PORTD(29)
+
+#define GPIO_AMP_EN             JZ_GPIO_PORTD(4)
+
+#define GPIO_SD_CD_N            JZ_GPIO_PORTD(0)
+#define GPIO_SD_VCC_EN_N        JZ_GPIO_PORTD(2)
+
+#define GPIO_USB_DETE           JZ_GPIO_PORTD(28)
+#define GPIO_BUZZ_PWM           JZ_GPIO_PORTD(27)
+#define GPIO_UDC_HOTPLUG        GPIO_USB_DETE
+
+#define GPIO_AUDIO_POP          JZ_GPIO_PORTB(29)
+#define GPIO_COB_TEST           JZ_GPIO_PORTB(30)
+
+#define GPIO_KEYOUT_BASE        JZ_GPIO_PORTC(10)
+#define GPIO_KEYIN_BASE         JZ_GPIO_PORTD(18)
+#define GPIO_KEYIN_8            JZ_GPIO_PORTD(26)
+
+#endif /* __ASM_JZ4740_QI_LB60_H__ */
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/clock.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/clock.h
new file mode 100644 (file)
index 0000000..4869b88
--- /dev/null
@@ -0,0 +1,298 @@
+/*
+ *  linux/include/asm-mips/mach-jz4740/clock.h
+ *
+ *  JZ4740 clocks definition.
+ *
+ *  Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
+ *
+ *  Author: <lhhuang@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_JZ4740_CLOCK_H__
+#define __ASM_JZ4740_CLOCK_H__
+
+#include <asm/mach-jz4740/regs.h>
+
+/***************************************************************************
+ * CPM
+ ***************************************************************************/
+#define __cpm_get_pllm() \
+       ((REG_CPM_CPPCR & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT)
+#define __cpm_get_plln() \
+       ((REG_CPM_CPPCR & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT)
+#define __cpm_get_pllod() \
+       ((REG_CPM_CPPCR & CPM_CPPCR_PLLOD_MASK) >> CPM_CPPCR_PLLOD_BIT)
+
+#define __cpm_get_cdiv() \
+       ((REG_CPM_CPCCR & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT)
+#define __cpm_get_hdiv() \
+       ((REG_CPM_CPCCR & CPM_CPCCR_HDIV_MASK) >> CPM_CPCCR_HDIV_BIT)
+#define __cpm_get_pdiv() \
+       ((REG_CPM_CPCCR & CPM_CPCCR_PDIV_MASK) >> CPM_CPCCR_PDIV_BIT)
+#define __cpm_get_mdiv() \
+       ((REG_CPM_CPCCR & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT)
+#define __cpm_get_ldiv() \
+       ((REG_CPM_CPCCR & CPM_CPCCR_LDIV_MASK) >> CPM_CPCCR_LDIV_BIT)
+#define __cpm_get_udiv() \
+       ((REG_CPM_CPCCR & CPM_CPCCR_UDIV_MASK) >> CPM_CPCCR_UDIV_BIT)
+#define __cpm_get_i2sdiv() \
+       ((REG_CPM_I2SCDR & CPM_I2SCDR_I2SDIV_MASK) >> CPM_I2SCDR_I2SDIV_BIT)
+#define __cpm_get_pixdiv() \
+       ((REG_CPM_LPCDR & CPM_LPCDR_PIXDIV_MASK) >> CPM_LPCDR_PIXDIV_BIT)
+#define __cpm_get_mscdiv() \
+       ((REG_CPM_MSCCDR & CPM_MSCCDR_MSCDIV_MASK) >> CPM_MSCCDR_MSCDIV_BIT)
+#define __cpm_get_uhcdiv() \
+       ((REG_CPM_UHCCDR & CPM_UHCCDR_UHCDIV_MASK) >> CPM_UHCCDR_UHCDIV_BIT)
+#define __cpm_get_ssidiv() \
+       ((REG_CPM_SSICCDR & CPM_SSICDR_SSICDIV_MASK) >> CPM_SSICDR_SSIDIV_BIT)
+
+#define __cpm_set_cdiv(v) \
+       (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_CDIV_MASK) | ((v) << (CPM_CPCCR_CDIV_BIT)))
+#define __cpm_set_hdiv(v) \
+       (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_HDIV_MASK) | ((v) << (CPM_CPCCR_HDIV_BIT)))
+#define __cpm_set_pdiv(v) \
+       (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_PDIV_MASK) | ((v) << (CPM_CPCCR_PDIV_BIT)))
+#define __cpm_set_mdiv(v) \
+       (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_MDIV_MASK) | ((v) << (CPM_CPCCR_MDIV_BIT)))
+#define __cpm_set_ldiv(v) \
+       (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_LDIV_MASK) | ((v) << (CPM_CPCCR_LDIV_BIT)))
+#define __cpm_set_udiv(v) \
+       (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_UDIV_MASK) | ((v) << (CPM_CPCCR_UDIV_BIT)))
+#define __cpm_set_i2sdiv(v) \
+       (REG_CPM_I2SCDR = (REG_CPM_I2SCDR & ~CPM_I2SCDR_I2SDIV_MASK) | ((v) << (CPM_I2SCDR_I2SDIV_BIT)))
+#define __cpm_set_pixdiv(v) \
+       (REG_CPM_LPCDR = (REG_CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | ((v) << (CPM_LPCDR_PIXDIV_BIT)))
+#define __cpm_set_mscdiv(v) \
+       (REG_CPM_MSCCDR = (REG_CPM_MSCCDR & ~CPM_MSCCDR_MSCDIV_MASK) | ((v) << (CPM_MSCCDR_MSCDIV_BIT)))
+#define __cpm_set_uhcdiv(v) \
+       (REG_CPM_UHCCDR = (REG_CPM_UHCCDR & ~CPM_UHCCDR_UHCDIV_MASK) | ((v) << (CPM_UHCCDR_UHCDIV_BIT)))
+#define __cpm_ssiclk_select_exclk() \
+       (REG_CPM_SSICDR &= ~CPM_SSICDR_SCS)
+#define __cpm_ssiclk_select_pllout() \
+       (REG_CPM_SSICDR |= CPM_SSICDR_SCS)
+#define __cpm_set_ssidiv(v) \
+       (REG_CPM_SSICDR = (REG_CPM_SSICDR & ~CPM_SSICDR_SSIDIV_MASK) | ((v) << (CPM_SSICDR_SSIDIV_BIT)))
+
+#define __cpm_select_i2sclk_exclk()    (REG_CPM_CPCCR &= ~CPM_CPCCR_I2CS)
+#define __cpm_select_i2sclk_pll()      (REG_CPM_CPCCR |= CPM_CPCCR_I2CS)
+#define __cpm_enable_cko()             (REG_CPM_CPCCR |= CPM_CPCCR_CLKOEN)
+#define __cpm_select_usbclk_exclk()    (REG_CPM_CPCCR &= ~CPM_CPCCR_UCS)
+#define __cpm_select_usbclk_pll()      (REG_CPM_CPCCR |= CPM_CPCCR_UCS)
+#define __cpm_enable_pll_change()      (REG_CPM_CPCCR |= CPM_CPCCR_CE)
+#define __cpm_pllout_direct()          (REG_CPM_CPCCR |= CPM_CPCCR_PCS)
+#define __cpm_pllout_div2()            (REG_CPM_CPCCR &= ~CPM_CPCCR_PCS)
+
+#define __cpm_pll_is_on()              (REG_CPM_CPPCR & CPM_CPPCR_PLLS)
+#define __cpm_pll_bypass()             (REG_CPM_CPPCR |= CPM_CPPCR_PLLBP)
+#define __cpm_pll_enable()             (REG_CPM_CPPCR |= CPM_CPPCR_PLLEN)
+
+#define __cpm_get_cclk_doze_duty() \
+       ((REG_CPM_LCR & CPM_LCR_DOZE_DUTY_MASK) >> CPM_LCR_DOZE_DUTY_BIT)
+#define __cpm_set_cclk_doze_duty(v) \
+       (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_DOZE_DUTY_MASK) | ((v) << (CPM_LCR_DOZE_DUTY_BIT)))
+
+#define __cpm_doze_mode()              (REG_CPM_LCR |= CPM_LCR_DOZE_ON)
+#define __cpm_idle_mode() \
+       (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_IDLE)
+#define __cpm_sleep_mode() \
+       (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_SLEEP)
+
+#define __cpm_stop_all()       (REG_CPM_CLKGR = 0x7fff)
+#define __cpm_stop_uart1()     (REG_CPM_CLKGR |= CPM_CLKGR_UART1)
+#define __cpm_stop_uhc()       (REG_CPM_CLKGR |= CPM_CLKGR_UHC)
+#define __cpm_stop_ipu()       (REG_CPM_CLKGR |= CPM_CLKGR_IPU)
+#define __cpm_stop_dmac()      (REG_CPM_CLKGR |= CPM_CLKGR_DMAC)
+#define __cpm_stop_udc()       (REG_CPM_CLKGR |= CPM_CLKGR_UDC)
+#define __cpm_stop_lcd()       (REG_CPM_CLKGR |= CPM_CLKGR_LCD)
+#define __cpm_stop_cim()       (REG_CPM_CLKGR |= CPM_CLKGR_CIM)
+#define __cpm_stop_sadc()      (REG_CPM_CLKGR |= CPM_CLKGR_SADC)
+#define __cpm_stop_msc()       (REG_CPM_CLKGR |= CPM_CLKGR_MSC)
+#define __cpm_stop_aic1()      (REG_CPM_CLKGR |= CPM_CLKGR_AIC1)
+#define __cpm_stop_aic2()      (REG_CPM_CLKGR |= CPM_CLKGR_AIC2)
+#define __cpm_stop_ssi()       (REG_CPM_CLKGR |= CPM_CLKGR_SSI)
+#define __cpm_stop_i2c()       (REG_CPM_CLKGR |= CPM_CLKGR_I2C)
+#define __cpm_stop_rtc()       (REG_CPM_CLKGR |= CPM_CLKGR_RTC)
+#define __cpm_stop_tcu()       (REG_CPM_CLKGR |= CPM_CLKGR_TCU)
+#define __cpm_stop_uart0()     (REG_CPM_CLKGR |= CPM_CLKGR_UART0)
+
+#define __cpm_start_all()      (REG_CPM_CLKGR = 0x0)
+#define __cpm_start_uart1()    (REG_CPM_CLKGR &= ~CPM_CLKGR_UART1)
+#define __cpm_start_uhc()      (REG_CPM_CLKGR &= ~CPM_CLKGR_UHC)
+#define __cpm_start_ipu()      (REG_CPM_CLKGR &= ~CPM_CLKGR_IPU)
+#define __cpm_start_dmac()     (REG_CPM_CLKGR &= ~CPM_CLKGR_DMAC)
+#define __cpm_start_udc()      (REG_CPM_CLKGR &= ~CPM_CLKGR_UDC)
+#define __cpm_start_lcd()      (REG_CPM_CLKGR &= ~CPM_CLKGR_LCD)
+#define __cpm_start_cim()      (REG_CPM_CLKGR &= ~CPM_CLKGR_CIM)
+#define __cpm_start_sadc()     (REG_CPM_CLKGR &= ~CPM_CLKGR_SADC)
+#define __cpm_start_msc()      (REG_CPM_CLKGR &= ~CPM_CLKGR_MSC)
+#define __cpm_start_aic1()     (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC1)
+#define __cpm_start_aic2()     (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC2)
+#define __cpm_start_ssi()      (REG_CPM_CLKGR &= ~CPM_CLKGR_SSI)
+#define __cpm_start_i2c()      (REG_CPM_CLKGR &= ~CPM_CLKGR_I2C)
+#define __cpm_start_rtc()      (REG_CPM_CLKGR &= ~CPM_CLKGR_RTC)
+#define __cpm_start_tcu()      (REG_CPM_CLKGR &= ~CPM_CLKGR_TCU)
+#define __cpm_start_uart0()    (REG_CPM_CLKGR &= ~CPM_CLKGR_UART0)
+
+#define __cpm_get_o1st() \
+       ((REG_CPM_SCR & CPM_SCR_O1ST_MASK) >> CPM_SCR_O1ST_BIT)
+#define __cpm_set_o1st(v) \
+       (REG_CPM_SCR = (REG_CPM_SCR & ~CPM_SCR_O1ST_MASK) | ((v) << (CPM_SCR_O1ST_BIT)))
+#define __cpm_suspend_usbphy()         (REG_CPM_SCR |= CPM_SCR_USBPHY_SUSPEND)
+#define __cpm_enable_osc_in_sleep()    (REG_CPM_SCR |= CPM_SCR_OSC_ENABLE)
+
+
+
+/*
+ * JZ4740 clocks structure
+ */
+typedef struct {
+       unsigned int cclk;      /* CPU clock */
+       unsigned int hclk;      /* System bus clock */
+       unsigned int pclk;      /* Peripheral bus clock */
+       unsigned int mclk;      /* Flash/SRAM/SDRAM clock */
+       unsigned int lcdclk;    /* LCDC module clock */
+       unsigned int pixclk;    /* LCD pixel clock */
+       unsigned int i2sclk;    /* AIC module clock */
+       unsigned int usbclk;    /* USB module clock */
+       unsigned int mscclk;    /* MSC module clock */
+       unsigned int extalclk;  /* EXTAL clock for UART,I2C,SSI,TCU,USB-PHY */
+       unsigned int rtcclk;    /* RTC clock for CPM,INTC,RTC,TCU,WDT */
+} jz_clocks_t;
+
+extern jz_clocks_t jz_clocks;
+
+
+/* PLL output frequency */
+static __inline__ unsigned int __cpm_get_pllout(void)
+{
+       unsigned long m, n, no, pllout;
+       unsigned long cppcr = REG_CPM_CPPCR;
+       unsigned long od[4] = {1, 2, 2, 4};
+       if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP)) {
+               m = __cpm_get_pllm() + 2;
+               n = __cpm_get_plln() + 2;
+               no = od[__cpm_get_pllod()];
+               pllout = ((JZ_EXTAL) / (n * no)) * m;
+       } else
+               pllout = JZ_EXTAL;
+       return pllout;
+}
+
+/* PLL output frequency for MSC/I2S/LCD/USB */
+static __inline__ unsigned int __cpm_get_pllout2(void)
+{
+       if (REG_CPM_CPCCR & CPM_CPCCR_PCS)
+               return __cpm_get_pllout();
+       else
+               return __cpm_get_pllout()/2;
+}
+
+/* CPU core clock */
+static __inline__ unsigned int __cpm_get_cclk(void)
+{
+       int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
+
+       return __cpm_get_pllout() / div[__cpm_get_cdiv()];
+}
+
+/* AHB system bus clock */
+static __inline__ unsigned int __cpm_get_hclk(void)
+{
+       int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
+
+       return __cpm_get_pllout() / div[__cpm_get_hdiv()];
+}
+
+/* Memory bus clock */
+static __inline__ unsigned int __cpm_get_mclk(void)
+{
+       int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
+
+       return __cpm_get_pllout() / div[__cpm_get_mdiv()];
+}
+
+/* APB peripheral bus clock */
+static __inline__ unsigned int __cpm_get_pclk(void)
+{
+       int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
+
+       return __cpm_get_pllout() / div[__cpm_get_pdiv()];
+}
+
+/* LCDC module clock */
+static __inline__ unsigned int __cpm_get_lcdclk(void)
+{
+       return __cpm_get_pllout2() / (__cpm_get_ldiv() + 1);
+}
+
+/* LCD pixel clock */
+static __inline__ unsigned int __cpm_get_pixclk(void)
+{
+       return __cpm_get_pllout2() / (__cpm_get_pixdiv() + 1);
+}
+
+/* I2S clock */
+static __inline__ unsigned int __cpm_get_i2sclk(void)
+{
+       if (REG_CPM_CPCCR & CPM_CPCCR_I2CS) {
+               return __cpm_get_pllout2() / (__cpm_get_i2sdiv() + 1);
+       }
+       else {
+               return JZ_EXTAL;
+       }
+}
+
+/* USB clock */
+static __inline__ unsigned int __cpm_get_usbclk(void)
+{
+       if (REG_CPM_CPCCR & CPM_CPCCR_UCS) {
+               return __cpm_get_pllout2() / (__cpm_get_udiv() + 1);
+       }
+       else {
+               return JZ_EXTAL;
+       }
+}
+
+/* MSC clock */
+static __inline__ unsigned int __cpm_get_mscclk(void)
+{
+       return __cpm_get_pllout2() / (__cpm_get_mscdiv() + 1);
+}
+
+/* EXTAL clock for UART,I2C,SSI,TCU,USB-PHY */
+static __inline__ unsigned int __cpm_get_extalclk(void)
+{
+       return JZ_EXTAL;
+}
+
+/* RTC clock for CPM,INTC,RTC,TCU,WDT */
+static __inline__ unsigned int __cpm_get_rtcclk(void)
+{
+       return JZ_EXTAL_RTC;
+}
+
+/*
+ * Output 24MHz for SD and 16MHz for MMC.
+ */
+static inline void __cpm_select_msc_clk(int sd)
+{
+       unsigned int pllout2 = __cpm_get_pllout2();
+       unsigned int div = 0;
+
+       if (sd) {
+               div = pllout2 / 24000000;
+       }
+       else {
+               div = pllout2 / 16000000;
+       }
+
+       REG_CPM_MSCCDR = div - 1;
+}
+
+int jz_init_clocks(unsigned long ext_rate);
+
+#endif /* __ASM_JZ4740_CLOCK_H__ */
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/dma.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/dma.h
new file mode 100644 (file)
index 0000000..e7f474e
--- /dev/null
@@ -0,0 +1,90 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *     JZ7420/JZ4740 DMA definitions
+ *
+ *  This program is free software; you can redistribute         it and/or modify it
+ *  under  the terms of         the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __ASM_MACH_JZ4740_DMA_H__
+#define __ASM_MACH_JZ4740_DMA_H__
+
+struct jz4740_dma_chan;
+
+enum jz4740_dma_request_type {
+       JZ4740_DMA_TYPE_AUTO_REQUEST =   8,
+       JZ4740_DMA_TYPE_UART_TRANSMIT = 20,
+       JZ4740_DMA_TYPE_UART_RECEIVE =  21,
+       JZ4740_DMA_TYPE_SPI_TRANSMIT =  22,
+       JZ4740_DMA_TYPE_SPI_RECEIVE =   23,
+       JZ4740_DMA_TYPE_AIC_TRANSMIT =  24,
+       JZ4740_DMA_TYPE_AIC_RECEIVE =   25,
+       JZ4740_DMA_TYPE_MMC_TRANSMIT =  26,
+       JZ4740_DMA_TYPE_MMC_RECEIVE =   27,
+       JZ4740_DMA_TYPE_TCU =           28,
+       JZ4740_DMA_TYPE_SADC =          29,
+       JZ4740_DMA_TYPE_SLCD =          30,
+};
+
+enum jz4740_dma_width {
+       JZ4740_DMA_WIDTH_8BIT,
+       JZ4740_DMA_WIDTH_16BIT,
+       JZ4740_DMA_WIDTH_32BIT,
+};
+
+enum jz4740_dma_transfer_size {
+       JZ4740_DMA_TRANSFER_SIZE_4BYTE  = 0,
+       JZ4740_DMA_TRANSFER_SIZE_1BYTE  = 1,
+       JZ4740_DMA_TRANSFER_SIZE_2BYTE  = 2,
+       JZ4740_DMA_TRANSFER_SIZE_16BYTE = 3,
+       JZ4740_DMA_TRANSFER_SIZE_32BYTE = 4,
+};
+
+enum jz4740_dma_flags {
+       JZ4740_DMA_SRC_AUTOINC = 0x2,
+       JZ4740_DMA_DST_AUTOINC = 0x1,
+};
+
+enum jz4740_dma_mode {
+       JZ4740_DMA_MODE_SINGLE = 0,
+       JZ4740_DMA_MODE_BLOCK = 1,
+};
+
+struct jz4740_dma_config {
+       enum jz4740_dma_width src_width;
+       enum jz4740_dma_width dst_width;
+       enum jz4740_dma_transfer_size transfer_size;
+       enum jz4740_dma_request_type request_type;
+       enum jz4740_dma_flags flags;
+       enum jz4740_dma_mode mode;
+};
+
+typedef void (*jz4740_dma_complete_callback_t)(struct jz4740_dma_chan *, int , void *);
+
+struct jz4740_dma_chan* jz4740_dma_request(void *dev, const char *name);
+void jz4740_dma_free(struct jz4740_dma_chan *dma);
+
+void jz4740_dma_configure(struct jz4740_dma_chan *dma, 
+                          const struct jz4740_dma_config *config);
+
+
+void jz4740_dma_enable(struct jz4740_dma_chan *dma);
+void jz4740_dma_disable(struct jz4740_dma_chan *dma);
+
+void jz4740_dma_set_src_addr(struct jz4740_dma_chan *dma, dma_addr_t src);
+void jz4740_dma_set_dst_addr(struct jz4740_dma_chan *dma, dma_addr_t dst);
+void jz4740_dma_set_transfer_count(struct jz4740_dma_chan *dma, uint32_t count);
+
+uint32_t jz4740_dma_get_residue(const struct jz4740_dma_chan *dma);
+
+void jz4740_dma_set_complete_cb(struct jz4740_dma_chan *dma,
+                                jz4740_dma_complete_callback_t cb);
+
+#endif  /* __ASM_JZ4740_DMA_H__ */
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/gpio.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/gpio.h
new file mode 100644 (file)
index 0000000..90d37dd
--- /dev/null
@@ -0,0 +1,393 @@
+/*
+ *  Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
+ *     JZ7420/JZ4740 GPIO pin definitions
+ *
+ *  This program is free software; you can redistribute         it and/or modify it
+ *  under  the terms of         the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef _JZ_GPIO_H
+#define _JZ_GPIO_H
+
+#include <linux/types.h>
+
+enum jz_gpio_function {
+    JZ_GPIO_FUNC_NONE,
+    JZ_GPIO_FUNC1,
+    JZ_GPIO_FUNC2,
+    JZ_GPIO_FUNC3,
+};
+
+
+/*
+ Usually a driver for a SoC component has to request several gpio pins and
+ configure them as funcion pins.
+ jz_gpio_bulk_request can be used to ease this process.
+ Usually one would do something like:
+
+ const static struct jz_gpio_bulk_request i2c_pins[] = {
+       JZ_GPIO_BULK_PIN(I2C_SDA),
+       JZ_GPIO_BULK_PIN(I2C_SCK),
+ };
+
+ inside the probe function:
+
+    ret = jz_gpio_bulk_request(i2c_pins, ARRAY_SIZE(i2c_pins));
+    if (ret) {
+       ...
+
+ inside the remove function:
+
+    jz_gpio_bulk_free(i2c_pins, ARRAY_SIZE(i2c_pins));
+
+
+*/
+struct jz_gpio_bulk_request {
+       int gpio;
+       const char *name;
+       enum jz_gpio_function function;
+};
+
+#define JZ_GPIO_BULK_PIN(pin) { \
+    .gpio = JZ_GPIO_ ## pin, \
+    .name = #pin, \
+    .function = JZ_GPIO_FUNC_ ## pin \
+}
+
+int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num);
+void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num);
+void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num);
+void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num);
+void jz_gpio_enable_pullup(unsigned gpio);
+void jz_gpio_disable_pullup(unsigned gpio);
+int jz_gpio_set_function(int gpio, enum jz_gpio_function function);
+
+int jz_gpio_port_direction_input(int port, uint32_t mask);
+int jz_gpio_port_direction_output(int port, uint32_t mask);
+void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask);
+uint32_t jz_gpio_port_get_value(int port, uint32_t mask);
+
+#include <asm/mach-generic/gpio.h>
+
+#define JZ_GPIO_PORTA(x) (x + 32 * 0)
+#define JZ_GPIO_PORTB(x) (x + 32 * 1)
+#define JZ_GPIO_PORTC(x) (x + 32 * 2)
+#define JZ_GPIO_PORTD(x) (x + 32 * 3)
+
+/* Port A function pins */
+#define JZ_GPIO_MEM_DATA0              JZ_GPIO_PORTA(0)
+#define JZ_GPIO_MEM_DATA1              JZ_GPIO_PORTA(1)
+#define JZ_GPIO_MEM_DATA2              JZ_GPIO_PORTA(2)
+#define JZ_GPIO_MEM_DATA3              JZ_GPIO_PORTA(3)
+#define JZ_GPIO_MEM_DATA4              JZ_GPIO_PORTA(4)
+#define JZ_GPIO_MEM_DATA5              JZ_GPIO_PORTA(5)
+#define JZ_GPIO_MEM_DATA6              JZ_GPIO_PORTA(6)
+#define JZ_GPIO_MEM_DATA7              JZ_GPIO_PORTA(7)
+#define JZ_GPIO_MEM_DATA8              JZ_GPIO_PORTA(8)
+#define JZ_GPIO_MEM_DATA9              JZ_GPIO_PORTA(9)
+#define JZ_GPIO_MEM_DATA10             JZ_GPIO_PORTA(10)
+#define JZ_GPIO_MEM_DATA11             JZ_GPIO_PORTA(11)
+#define JZ_GPIO_MEM_DATA12             JZ_GPIO_PORTA(12)
+#define JZ_GPIO_MEM_DATA13             JZ_GPIO_PORTA(13)
+#define JZ_GPIO_MEM_DATA14             JZ_GPIO_PORTA(14)
+#define JZ_GPIO_MEM_DATA15             JZ_GPIO_PORTA(15)
+#define JZ_GPIO_MEM_DATA16             JZ_GPIO_PORTA(16)
+#define JZ_GPIO_MEM_DATA17             JZ_GPIO_PORTA(17)
+#define JZ_GPIO_MEM_DATA18             JZ_GPIO_PORTA(18)
+#define JZ_GPIO_MEM_DATA19             JZ_GPIO_PORTA(19)
+#define JZ_GPIO_MEM_DATA20             JZ_GPIO_PORTA(20)
+#define JZ_GPIO_MEM_DATA21             JZ_GPIO_PORTA(21)
+#define JZ_GPIO_MEM_DATA22             JZ_GPIO_PORTA(22)
+#define JZ_GPIO_MEM_DATA23             JZ_GPIO_PORTA(23)
+#define JZ_GPIO_MEM_DATA24             JZ_GPIO_PORTA(24)
+#define JZ_GPIO_MEM_DATA25             JZ_GPIO_PORTA(25)
+#define JZ_GPIO_MEM_DATA26             JZ_GPIO_PORTA(26)
+#define JZ_GPIO_MEM_DATA27             JZ_GPIO_PORTA(27)
+#define JZ_GPIO_MEM_DATA28             JZ_GPIO_PORTA(28)
+#define JZ_GPIO_MEM_DATA29             JZ_GPIO_PORTA(29)
+#define JZ_GPIO_MEM_DATA30             JZ_GPIO_PORTA(30)
+#define JZ_GPIO_MEM_DATA31             JZ_GPIO_PORTA(31)
+
+#define JZ_GPIO_FUNC_MEM_DATA0         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA1         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA2         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA3         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA4         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA5         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA6         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA7         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA8         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA9         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA10                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA11                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA12                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA13                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA14                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA15                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA16                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA17                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA18                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA19                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA20                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA21                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA22                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA23                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA24                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA25                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA26                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA27                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA28                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA29                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA30                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA31                JZ_GPIO_FUNC1
+
+/* Port B function pins */
+#define JZ_GPIO_MEM_ADDR0              JZ_GPIO_PORTB(0)
+#define JZ_GPIO_MEM_ADDR1              JZ_GPIO_PORTB(1)
+#define JZ_GPIO_MEM_ADDR2              JZ_GPIO_PORTB(2)
+#define JZ_GPIO_MEM_ADDR3              JZ_GPIO_PORTB(3)
+#define JZ_GPIO_MEM_ADDR4              JZ_GPIO_PORTB(4)
+#define JZ_GPIO_MEM_ADDR5              JZ_GPIO_PORTB(5)
+#define JZ_GPIO_MEM_ADDR6              JZ_GPIO_PORTB(6)
+#define JZ_GPIO_MEM_ADDR7              JZ_GPIO_PORTB(7)
+#define JZ_GPIO_MEM_ADDR8              JZ_GPIO_PORTB(8)
+#define JZ_GPIO_MEM_ADDR9              JZ_GPIO_PORTB(9)
+#define JZ_GPIO_MEM_ADDR10             JZ_GPIO_PORTB(10)
+#define JZ_GPIO_MEM_ADDR11             JZ_GPIO_PORTB(11)
+#define JZ_GPIO_MEM_ADDR12             JZ_GPIO_PORTB(12)
+#define JZ_GPIO_MEM_ADDR13             JZ_GPIO_PORTB(13)
+#define JZ_GPIO_MEM_ADDR14             JZ_GPIO_PORTB(14)
+#define JZ_GPIO_MEM_ADDR15             JZ_GPIO_PORTB(15)
+#define JZ_GPIO_MEM_ADDR16             JZ_GPIO_PORTB(16)
+#define JZ_GPIO_MEM_CLS                        JZ_GPIO_PORTB(17)
+#define JZ_GPIO_MEM_SPL                        JZ_GPIO_PORTB(18)
+#define JZ_GPIO_MEM_DCS                        JZ_GPIO_PORTB(19)
+#define JZ_GPIO_MEM_RAS                        JZ_GPIO_PORTB(20)
+#define JZ_GPIO_MEM_CAS                        JZ_GPIO_PORTB(21)
+#define JZ_GPIO_MEM_SDWE               JZ_GPIO_PORTB(22)
+#define JZ_GPIO_MEM_CKE                        JZ_GPIO_PORTB(23)
+#define JZ_GPIO_MEM_CKO                        JZ_GPIO_PORTB(24)
+#define JZ_GPIO_MEM_CS0                        JZ_GPIO_PORTB(25)
+#define JZ_GPIO_MEM_CS1                        JZ_GPIO_PORTB(26)
+#define JZ_GPIO_MEM_CS2                        JZ_GPIO_PORTB(27)
+#define JZ_GPIO_MEM_CS3                        JZ_GPIO_PORTB(28)
+#define JZ_GPIO_MEM_RD                 JZ_GPIO_PORTB(29)
+#define JZ_GPIO_MEM_WR                 JZ_GPIO_PORTB(30)
+#define JZ_GPIO_MEM_WE0                        JZ_GPIO_PORTB(31)
+
+#define JZ_GPIO_FUNC_MEM_ADDR0         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR1         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR2         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR3         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR4         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR5         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR6         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR7         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR8         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR9         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR10                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR11                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR12                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR13                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR14                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR15                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR16                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_CLS           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_SPL           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DCS           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_RAS           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_CAS           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_SDWE          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_CKE           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_CKO           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_CS0           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_CS1           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_CS2           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_CS3           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_RD            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_WR            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_WE0           JZ_GPIO_FUNC1
+
+
+#define JZ_GPIO_MEM_ADDR21             JZ_GPIO_PORTB(17)
+#define JZ_GPIO_MEM_ADDR22             JZ_GPIO_PORTB(18)
+
+#define JZ_GPIO_FUNC_MEM_ADDR21                JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_MEM_ADDR22                JZ_GPIO_FUNC2
+
+/* Port C function pins */
+#define JZ_GPIO_LCD_DATA0              JZ_GPIO_PORTC(0)
+#define JZ_GPIO_LCD_DATA1              JZ_GPIO_PORTC(1)
+#define JZ_GPIO_LCD_DATA2              JZ_GPIO_PORTC(2)
+#define JZ_GPIO_LCD_DATA3              JZ_GPIO_PORTC(3)
+#define JZ_GPIO_LCD_DATA4              JZ_GPIO_PORTC(4)
+#define JZ_GPIO_LCD_DATA5              JZ_GPIO_PORTC(5)
+#define JZ_GPIO_LCD_DATA6              JZ_GPIO_PORTC(6)
+#define JZ_GPIO_LCD_DATA7              JZ_GPIO_PORTC(7)
+#define JZ_GPIO_LCD_DATA8              JZ_GPIO_PORTC(8)
+#define JZ_GPIO_LCD_DATA9              JZ_GPIO_PORTC(9)
+#define JZ_GPIO_LCD_DATA10             JZ_GPIO_PORTC(10)
+#define JZ_GPIO_LCD_DATA11             JZ_GPIO_PORTC(11)
+#define JZ_GPIO_LCD_DATA12             JZ_GPIO_PORTC(12)
+#define JZ_GPIO_LCD_DATA13             JZ_GPIO_PORTC(13)
+#define JZ_GPIO_LCD_DATA14             JZ_GPIO_PORTC(14)
+#define JZ_GPIO_LCD_DATA15             JZ_GPIO_PORTC(15)
+#define JZ_GPIO_LCD_DATA16             JZ_GPIO_PORTC(16)
+#define JZ_GPIO_LCD_DATA17             JZ_GPIO_PORTC(17)
+#define JZ_GPIO_LCD_PCLK               JZ_GPIO_PORTC(18)
+#define JZ_GPIO_LCD_HSYNC              JZ_GPIO_PORTC(19)
+#define JZ_GPIO_LCD_VSYNC              JZ_GPIO_PORTC(20)
+#define JZ_GPIO_LCD_DE                 JZ_GPIO_PORTC(21)
+#define JZ_GPIO_LCD_PS                 JZ_GPIO_PORTC(22)
+#define JZ_GPIO_LCD_REV                        JZ_GPIO_PORTC(23)
+#define JZ_GPIO_MEM_WE1                        JZ_GPIO_PORTC(24)
+#define JZ_GPIO_MEM_WE2                        JZ_GPIO_PORTC(25)
+#define JZ_GPIO_MEM_WE3                        JZ_GPIO_PORTC(26)
+#define JZ_GPIO_MEM_WAIT               JZ_GPIO_PORTC(27)
+#define JZ_GPIO_MEM_FRE                        JZ_GPIO_PORTC(28)
+#define JZ_GPIO_MEM_FWE                        JZ_GPIO_PORTC(29)
+
+#define JZ_GPIO_FUNC_LCD_DATA0         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA1         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA2         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA3         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA4         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA5         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA6         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA7         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA8         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA9         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA10                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA11                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA12                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA13                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA14                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA15                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA16                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA17                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_PCLK          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_VSYNC         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_HSYNC         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DE            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_PS            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_REV           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_WE1           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_WE2           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_WE3           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_WAIT          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_FRE           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_FWE           JZ_GPIO_FUNC1
+
+
+#define JZ_GPIO_MEM_ADDR19             JZ_GPIO_PORTB(22)
+#define JZ_GPIO_MEM_ADDR20             JZ_GPIO_PORTB(23)
+
+#define JZ_GPIO_FUNC_MEM_ADDR19                JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_MEM_ADDR20                JZ_GPIO_FUNC2
+
+/* Port D function pins */
+#define JZ_GPIO_CIM_DATA0              JZ_GPIO_PORTD(0)
+#define JZ_GPIO_CIM_DATA1              JZ_GPIO_PORTD(1)
+#define JZ_GPIO_CIM_DATA2              JZ_GPIO_PORTD(2)
+#define JZ_GPIO_CIM_DATA3              JZ_GPIO_PORTD(3)
+#define JZ_GPIO_CIM_DATA4              JZ_GPIO_PORTD(4)
+#define JZ_GPIO_CIM_DATA5              JZ_GPIO_PORTD(5)
+#define JZ_GPIO_CIM_DATA6              JZ_GPIO_PORTD(6)
+#define JZ_GPIO_CIM_DATA7              JZ_GPIO_PORTD(7)
+#define JZ_GPIO_MSC_CMD                        JZ_GPIO_PORTD(8)
+#define JZ_GPIO_MSC_CLK                        JZ_GPIO_PORTD(9)
+#define JZ_GPIO_MSC_DATA0              JZ_GPIO_PORTD(10)
+#define JZ_GPIO_MSC_DATA1              JZ_GPIO_PORTD(11)
+#define JZ_GPIO_MSC_DATA2              JZ_GPIO_PORTD(12)
+#define JZ_GPIO_MSC_DATA3              JZ_GPIO_PORTD(13)
+#define JZ_GPIO_CIM_MCLK               JZ_GPIO_PORTD(14)
+#define JZ_GPIO_CIM_PCLK               JZ_GPIO_PORTD(15)
+#define JZ_GPIO_CIM_VSYNC              JZ_GPIO_PORTD(16)
+#define JZ_GPIO_CIM_HSYNC              JZ_GPIO_PORTD(17)
+#define JZ_GPIO_SPI_CLK                        JZ_GPIO_PORTD(18)
+#define JZ_GPIO_SPI_CE0                        JZ_GPIO_PORTD(19)
+#define JZ_GPIO_SPI_DT                 JZ_GPIO_PORTD(20)
+#define JZ_GPIO_SPI_DR                 JZ_GPIO_PORTD(21)
+#define JZ_GPIO_SPI_CE1                        JZ_GPIO_PORTD(22)
+#define JZ_GPIO_PWM0                   JZ_GPIO_PORTD(23)
+#define JZ_GPIO_PWM1                   JZ_GPIO_PORTD(24)
+#define JZ_GPIO_PWM2                   JZ_GPIO_PORTD(25)
+#define JZ_GPIO_PWM3                   JZ_GPIO_PORTD(26)
+#define JZ_GPIO_PWM4                   JZ_GPIO_PORTD(27)
+#define JZ_GPIO_PWM5                   JZ_GPIO_PORTD(28)
+#define JZ_GPIO_PWM6                   JZ_GPIO_PORTD(30)
+#define JZ_GPIO_PWM7                   JZ_GPIO_PORTD(31)
+
+#define JZ_GPIO_FUNC_CIM_DATA0         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_CIM_DATA1         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_CIM_DATA2         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_CIM_DATA3         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_CIM_DATA4         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_CIM_DATA5         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_CIM_DATA6         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_CIM_DATA7         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MSC_CMD           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MSC_CLK           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MSC_DATA0         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MSC_DATA1         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MSC_DATA2         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MSC_DATA3         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_CIM_MCLK          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_CIM_PCLK          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_CIM_VSYNC         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_CIM_HSYNC         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_SPI_CLK           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_SPI_CE0           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_SPI_DT            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_SPI_DR            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_SPI_CE1           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_PWM0              JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_PWM1              JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_PWM2              JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_PWM3              JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_PWM4              JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_PWM5              JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_PWM6              JZ_GPIO_FUNC1
+
+#define JZ_GPIO_MEM_SCLK_RSTN          JZ_GPIO_PORTD(18)
+#define JZ_GPIO_MEM_BCLK               JZ_GPIO_PORTD(19)
+#define JZ_GPIO_MEM_SDATO              JZ_GPIO_PORTD(20)
+#define JZ_GPIO_MEM_SDATI              JZ_GPIO_PORTD(21)
+#define JZ_GPIO_MEM_SYNC               JZ_GPIO_PORTD(22)
+#define JZ_GPIO_I2C_SDA                        JZ_GPIO_PORTD(23)
+#define JZ_GPIO_I2C_SCK                        JZ_GPIO_PORTD(24)
+#define JZ_GPIO_UART0_TXD              JZ_GPIO_PORTD(25)
+#define JZ_GPIO_UART0_RXD              JZ_GPIO_PORTD(26)
+#define JZ_GPIO_MEM_ADDR17             JZ_GPIO_PORTD(27)
+#define JZ_GPIO_MEM_ADDR18             JZ_GPIO_PORTD(28)
+#define JZ_GPIO_UART0_CTS              JZ_GPIO_PORTD(30)
+#define JZ_GPIO_UART0_RTS              JZ_GPIO_PORTD(31)
+
+#define JZ_GPIO_FUNC_MEM_SCLK_RSTN     JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_MEM_BCLK          JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_MEM_SDATO         JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_MEM_SDATI         JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_MEM_SYNC          JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_I2C_SDA           JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_I2C_SCK           JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_UART0_TXD         JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_UART0_RXD         JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_MEM_ADDR17                JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_MEM_ADDR18                JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_UART0_CTS         JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_UART0_RTS         JZ_GPIO_FUNC2
+
+#define JZ_GPIO_UART1_RXD              JZ_GPIO_PORTD(30)
+#define JZ_GPIO_UART1_TXD              JZ_GPIO_PORTD(31)
+
+#define JZ_GPIO_FUNC_UART1_RXD         JZ_GPIO_FUNC3
+#define JZ_GPIO_FUNC_UART1_TXD         JZ_GPIO_FUNC3
+
+#endif
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/irq.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/irq.h
new file mode 100644 (file)
index 0000000..59f0ea5
--- /dev/null
@@ -0,0 +1,55 @@
+/*
+ *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
+ *     JZ7420/JZ4740 IRQ definitions
+ *
+ *  This program is free software; you can redistribute         it and/or modify it
+ *  under  the terms of         the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __ASM_MACH_JZ4740_IRQ_H__
+#define __ASM_MACH_JZ4740_IRQ_H__
+
+#define MIPS_CPU_IRQ_BASE 0
+#define JZ_IRQ_BASE 8
+
+/* 1st-level interrupts */
+#define JZ_IRQ(x)      (JZ_IRQ_BASE + (x))
+#define JZ_IRQ_I2C     JZ_IRQ(1)
+#define JZ_IRQ_UHC     JZ_IRQ(3)
+#define JZ_IRQ_UART1   JZ_IRQ(8)
+#define JZ_IRQ_UART0   JZ_IRQ(9)
+#define JZ_IRQ_SADC    JZ_IRQ(12)
+#define JZ_IRQ_MSC     JZ_IRQ(14)
+#define JZ_IRQ_RTC     JZ_IRQ(15)
+#define JZ_IRQ_SSI     JZ_IRQ(16)
+#define JZ_IRQ_CIM     JZ_IRQ(17)
+#define JZ_IRQ_AIC     JZ_IRQ(18)
+#define JZ_IRQ_ETH     JZ_IRQ(19)
+#define JZ_IRQ_DMAC    JZ_IRQ(20)
+#define JZ_IRQ_TCU2    JZ_IRQ(21)
+#define JZ_IRQ_TCU1    JZ_IRQ(22)
+#define JZ_IRQ_TCU0    JZ_IRQ(23)
+#define JZ_IRQ_UDC     JZ_IRQ(24)
+#define JZ_IRQ_GPIO3   JZ_IRQ(25)
+#define JZ_IRQ_GPIO2   JZ_IRQ(26)
+#define JZ_IRQ_GPIO1   JZ_IRQ(27)
+#define JZ_IRQ_GPIO0   JZ_IRQ(28)
+#define JZ_IRQ_IPU     JZ_IRQ(29)
+#define JZ_IRQ_LCD     JZ_IRQ(30)
+
+/* 2nd-level interrupts */
+#define JZ_IRQ_DMA(x)  ((x) + JZ_IRQ(32))  /* 32 to 37 for DMAC channel 0 to 5 */
+
+#define JZ_IRQ_INTC_GPIO(x)    (JZ_IRQ_GPIO0 - (x))
+#define JZ_IRQ_GPIO(x)         (JZ_IRQ(48) + (x))
+
+#define NR_IRQS (JZ_IRQ_GPIO(127) + 1)
+
+#endif
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/jz4740.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/jz4740.h
new file mode 100644 (file)
index 0000000..7f9293a
--- /dev/null
@@ -0,0 +1,38 @@
+/*
+ *  linux/include/asm-mips/mach-jz4740/jz4740.h
+ *
+ *  JZ4740 common definition.
+ *
+ *  Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
+ *
+ *  Author: <lhhuang@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_JZ4740_H__
+#define __ASM_JZ4740_H__
+
+#include <asm/mach-jz4740/regs.h>
+#include <asm/mach-jz4740/dma.h>
+
+/*------------------------------------------------------------------
+ * Platform definitions
+ */
+
+#ifdef CONFIG_JZ4740_QI_LB60
+#include <asm/mach-jz4740/board-qi_lb60.h>
+#endif
+
+/* Add other platform definition here ... */
+
+
+/*------------------------------------------------------------------
+ * Follows are related to platform definitions
+ */
+
+#include <asm/mach-jz4740/serial.h>
+
+#endif /* __ASM_JZ4740_H__ */
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/platform.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/platform.h
new file mode 100644 (file)
index 0000000..42de1c1
--- /dev/null
@@ -0,0 +1,34 @@
+/*
+ *  Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
+ *     JZ7420/JZ4740 platform device definitions
+ *
+ *  This program is free software; you can redistribute         it and/or modify it
+ *  under  the terms of         the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+
+#ifndef __JZ4740_PLATFORM_H
+#define __JZ4740_PLATFORM_H
+
+#include <linux/platform_device.h>
+
+extern struct platform_device jz4740_usb_ohci_device;
+extern struct platform_device jz4740_usb_gdt_device;
+extern struct platform_device jz4740_mmc_device;
+extern struct platform_device jz4740_rtc_device;
+extern struct platform_device jz4740_i2c_device;
+extern struct platform_device jz4740_nand_device;
+extern struct platform_device jz4740_framebuffer_device;
+extern struct platform_device jz4740_i2s_device;
+extern struct platform_device jz4740_codec_device;
+extern struct platform_device jz4740_adc_device;
+extern struct platform_device jz4740_battery_device;
+
+#endif
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/regs.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/regs.h
new file mode 100644 (file)
index 0000000..3046fee
--- /dev/null
@@ -0,0 +1,675 @@
+/*
+ *  linux/include/asm-mips/mach-jz4740/regs.h
+ *
+ *  Ingenic's JZ4740 common include.
+ *
+ *  Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
+ *
+ *  Author: <yliu@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __JZ4740_REGS_H__
+#define __JZ4740_REGS_H__
+
+#if defined(__ASSEMBLY__) || defined(__LANGUAGE_ASSEMBLY)
+#define REG8(addr)     (addr)
+#define REG16(addr)    (addr)
+#define REG32(addr)    (addr)
+#else
+#define REG8(addr)     *((volatile unsigned char *)(addr))
+#define REG16(addr)    *((volatile unsigned short *)(addr))
+#define REG32(addr)    *((volatile unsigned int *)(addr))
+#endif
+
+/*
+ * Define the module base addresses
+ */
+#define        CPM_BASE        0xB0000000
+#define        INTC_BASE       0xB0001000
+#define        TCU_BASE        0xB0002000
+#define        WDT_BASE        0xB0002000
+#define        RTC_BASE        0xB0003000
+#define        GPIO_BASE       0xB0010000
+#define        AIC_BASE        0xB0020000
+#define        ICDC_BASE       0xB0020000
+#define        MSC_BASE        0xB0021000
+#define        UART0_BASE      0xB0030000
+#define        UART1_BASE      0xB0031000
+#define        I2C_BASE        0xB0042000
+#define        SSI_BASE        0xB0043000
+#define        SADC_BASE       0xB0070000
+#define        EMC_BASE        0xB3010000
+#define        DMAC_BASE       0xB3020000
+#define        UHC_BASE        0xB3030000
+#define        UDC_BASE        0xB3040000
+#define        LCD_BASE        0xB3050000
+#define        SLCD_BASE       0xB3050000
+#define        CIM_BASE        0xB3060000
+#define IPU_BASE       0xB3080000
+#define        ETH_BASE        0xB3100000
+
+/*************************************************************************
+ * CPM (Clock reset and Power control Management)
+ *************************************************************************/
+#define CPM_CPCCR      (CPM_BASE+0x00)
+#define CPM_CPPCR      (CPM_BASE+0x10)
+#define CPM_I2SCDR     (CPM_BASE+0x60)
+#define CPM_LPCDR      (CPM_BASE+0x64)
+#define CPM_MSCCDR     (CPM_BASE+0x68)
+#define CPM_UHCCDR     (CPM_BASE+0x6C)
+#define CPM_SSICDR     (CPM_BASE+0x74)
+
+#define CPM_LCR                (CPM_BASE+0x04)
+#define CPM_CLKGR      (CPM_BASE+0x20)
+#define CPM_SCR                (CPM_BASE+0x24)
+
+#define CPM_HCR                (CPM_BASE+0x30)
+#define CPM_HWFCR      (CPM_BASE+0x34)
+#define CPM_HRCR       (CPM_BASE+0x38)
+#define CPM_HWCR       (CPM_BASE+0x3c)
+#define CPM_HWSR       (CPM_BASE+0x40)
+#define CPM_HSPR       (CPM_BASE+0x44)
+
+#define CPM_RSR                (CPM_BASE+0x08)
+
+#define REG_CPM_CPCCR  REG32(CPM_CPCCR)
+#define REG_CPM_CPPCR  REG32(CPM_CPPCR)
+#define REG_CPM_I2SCDR REG32(CPM_I2SCDR)
+#define REG_CPM_LPCDR  REG32(CPM_LPCDR)
+#define REG_CPM_MSCCDR REG32(CPM_MSCCDR)
+#define REG_CPM_UHCCDR REG32(CPM_UHCCDR)
+#define REG_CPM_SSICDR REG32(CPM_SSICDR)
+
+#define REG_CPM_LCR    REG32(CPM_LCR)
+#define REG_CPM_CLKGR  REG32(CPM_CLKGR)
+#define REG_CPM_SCR    REG32(CPM_SCR)
+#define REG_CPM_HCR    REG32(CPM_HCR)
+#define REG_CPM_HWFCR  REG32(CPM_HWFCR)
+#define REG_CPM_HRCR   REG32(CPM_HRCR)
+#define REG_CPM_HWCR   REG32(CPM_HWCR)
+#define REG_CPM_HWSR   REG32(CPM_HWSR)
+#define REG_CPM_HSPR   REG32(CPM_HSPR)
+
+#define REG_CPM_RSR    REG32(CPM_RSR)
+
+/* Clock Control Register */
+#define CPM_CPCCR_I2CS         (1 << 31)
+#define CPM_CPCCR_CLKOEN       (1 << 30)
+#define CPM_CPCCR_UCS          (1 << 29)
+#define CPM_CPCCR_UDIV_BIT     23
+#define CPM_CPCCR_UDIV_MASK    (0x3f << CPM_CPCCR_UDIV_BIT)
+#define CPM_CPCCR_CE           (1 << 22)
+#define CPM_CPCCR_PCS          (1 << 21)
+#define CPM_CPCCR_LDIV_BIT     16
+#define CPM_CPCCR_LDIV_MASK    (0x1f << CPM_CPCCR_LDIV_BIT)
+#define CPM_CPCCR_MDIV_BIT     12
+#define CPM_CPCCR_MDIV_MASK    (0x0f << CPM_CPCCR_MDIV_BIT)
+#define CPM_CPCCR_PDIV_BIT     8
+#define CPM_CPCCR_PDIV_MASK    (0x0f << CPM_CPCCR_PDIV_BIT)
+#define CPM_CPCCR_HDIV_BIT     4
+#define CPM_CPCCR_HDIV_MASK    (0x0f << CPM_CPCCR_HDIV_BIT)
+#define CPM_CPCCR_CDIV_BIT     0
+#define CPM_CPCCR_CDIV_MASK    (0x0f << CPM_CPCCR_CDIV_BIT)
+
+/* I2S Clock Divider Register */
+#define CPM_I2SCDR_I2SDIV_BIT  0
+#define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT)
+
+/* LCD Pixel Clock Divider Register */
+#define CPM_LPCDR_PIXDIV_BIT   0
+#define CPM_LPCDR_PIXDIV_MASK  (0x7ff << CPM_LPCDR_PIXDIV_BIT)
+
+/* MSC Clock Divider Register */
+#define CPM_MSCCDR_MSCDIV_BIT  0
+#define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT)
+
+/* UHC Clock Divider Register */
+#define CPM_UHCCDR_UHCDIV_BIT  0
+#define CPM_UHCCDR_UHCDIV_MASK (0xf << CPM_UHCCDR_UHCDIV_BIT)
+
+/* SSI Clock Divider Register */
+#define CPM_SSICDR_SCS         (1<<31) /* SSI clock source selection, 0:EXCLK, 1: PLL */
+#define CPM_SSICDR_SSIDIV_BIT  0
+#define CPM_SSICDR_SSIDIV_MASK (0xf << CPM_SSICDR_SSIDIV_BIT)
+
+/* PLL Control Register */
+#define CPM_CPPCR_PLLM_BIT     23
+#define CPM_CPPCR_PLLM_MASK    (0x1ff << CPM_CPPCR_PLLM_BIT)
+#define CPM_CPPCR_PLLN_BIT     18
+#define CPM_CPPCR_PLLN_MASK    (0x1f << CPM_CPPCR_PLLN_BIT)
+#define CPM_CPPCR_PLLOD_BIT    16
+#define CPM_CPPCR_PLLOD_MASK   (0x03 << CPM_CPPCR_PLLOD_BIT)
+#define CPM_CPPCR_PLLS         (1 << 10)
+#define CPM_CPPCR_PLLBP                (1 << 9)
+#define CPM_CPPCR_PLLEN                (1 << 8)
+#define CPM_CPPCR_PLLST_BIT    0
+#define CPM_CPPCR_PLLST_MASK   (0xff << CPM_CPPCR_PLLST_BIT)
+
+/* Low Power Control Register */
+#define CPM_LCR_DOZE_DUTY_BIT  3
+#define CPM_LCR_DOZE_DUTY_MASK         (0x1f << CPM_LCR_DOZE_DUTY_BIT)
+#define CPM_LCR_DOZE_ON                (1 << 2)
+#define CPM_LCR_LPM_BIT                0
+#define CPM_LCR_LPM_MASK       (0x3 << CPM_LCR_LPM_BIT)
+  #define CPM_LCR_LPM_IDLE     (0x0 << CPM_LCR_LPM_BIT)
+  #define CPM_LCR_LPM_SLEEP    (0x1 << CPM_LCR_LPM_BIT)
+
+/* Clock Gate Register */
+#define CPM_CLKGR_UART1                (1 << 15)
+#define CPM_CLKGR_UHC          (1 << 14)
+#define CPM_CLKGR_IPU          (1 << 13)
+#define CPM_CLKGR_DMAC         (1 << 12)
+#define CPM_CLKGR_UDC          (1 << 11)
+#define CPM_CLKGR_LCD          (1 << 10)
+#define CPM_CLKGR_CIM          (1 << 9)
+#define CPM_CLKGR_SADC         (1 << 8)
+#define CPM_CLKGR_MSC          (1 << 7)
+#define CPM_CLKGR_AIC1         (1 << 6)
+#define CPM_CLKGR_AIC2         (1 << 5)
+#define CPM_CLKGR_SSI          (1 << 4)
+#define CPM_CLKGR_I2C          (1 << 3)
+#define CPM_CLKGR_RTC          (1 << 2)
+#define CPM_CLKGR_TCU          (1 << 1)
+#define CPM_CLKGR_UART0                (1 << 0)
+
+/* Sleep Control Register */
+#define CPM_SCR_O1ST_BIT       8
+#define CPM_SCR_O1ST_MASK      (0xff << CPM_SCR_O1ST_BIT)
+#define CPM_SCR_USBPHY_ENABLE  (1 << 6)
+#define CPM_SCR_OSC_ENABLE     (1 << 4)
+
+/* Hibernate Control Register */
+#define CPM_HCR_PD             (1 << 0)
+
+/* Wakeup Filter Counter Register in Hibernate Mode */
+#define CPM_HWFCR_TIME_BIT     0
+#define CPM_HWFCR_TIME_MASK    (0x3ff << CPM_HWFCR_TIME_BIT)
+
+/* Reset Counter Register in Hibernate Mode */
+#define CPM_HRCR_TIME_BIT      0
+#define CPM_HRCR_TIME_MASK     (0x7f << CPM_HRCR_TIME_BIT)
+
+/* Wakeup Control Register in Hibernate Mode */
+#define CPM_HWCR_WLE_LOW       (0 << 2)
+#define CPM_HWCR_WLE_HIGH      (1 << 2)
+#define CPM_HWCR_PIN_WAKEUP    (1 << 1)
+#define CPM_HWCR_RTC_WAKEUP    (1 << 0)
+
+/* Wakeup Status Register in Hibernate Mode */
+#define CPM_HWSR_WSR_PIN       (1 << 1)
+#define CPM_HWSR_WSR_RTC       (1 << 0)
+
+/* Reset Status Register */
+#define CPM_RSR_HR             (1 << 2)
+#define CPM_RSR_WR             (1 << 1)
+#define CPM_RSR_PR             (1 << 0)
+
+/*************************************************************************
+ * UART
+ *************************************************************************/
+
+#define IRDA_BASE      UART0_BASE
+#define UART_BASE      UART0_BASE
+#define UART_OFF       0x1000
+
+/* Register Offset */
+#define OFF_RDR                (0x00)  /* R  8b H'xx */
+#define OFF_TDR                (0x00)  /* W  8b H'xx */
+#define OFF_DLLR       (0x00)  /* RW 8b H'00 */
+#define OFF_DLHR       (0x04)  /* RW 8b H'00 */
+#define OFF_IER                (0x04)  /* RW 8b H'00 */
+#define OFF_ISR                (0x08)  /* R  8b H'01 */
+#define OFF_FCR                (0x08)  /* W  8b H'00 */
+#define OFF_LCR                (0x0C)  /* RW 8b H'00 */
+#define OFF_MCR                (0x10)  /* RW 8b H'00 */
+#define OFF_LSR                (0x14)  /* R  8b H'00 */
+#define OFF_MSR                (0x18)  /* R  8b H'00 */
+#define OFF_SPR                (0x1C)  /* RW 8b H'00 */
+#define OFF_SIRCR      (0x20)  /* RW 8b H'00, UART0 */
+#define OFF_UMR                (0x24)  /* RW 8b H'00, UART M Register */
+#define OFF_UACR       (0x28)  /* RW 8b H'00, UART Add Cycle Register */
+
+/* Register Address */
+#define UART0_RDR      (UART0_BASE + OFF_RDR)
+#define UART0_TDR      (UART0_BASE + OFF_TDR)
+#define UART0_DLLR     (UART0_BASE + OFF_DLLR)
+#define UART0_DLHR     (UART0_BASE + OFF_DLHR)
+#define UART0_IER      (UART0_BASE + OFF_IER)
+#define UART0_ISR      (UART0_BASE + OFF_ISR)
+#define UART0_FCR      (UART0_BASE + OFF_FCR)
+#define UART0_LCR      (UART0_BASE + OFF_LCR)
+#define UART0_MCR      (UART0_BASE + OFF_MCR)
+#define UART0_LSR      (UART0_BASE + OFF_LSR)
+#define UART0_MSR      (UART0_BASE + OFF_MSR)
+#define UART0_SPR      (UART0_BASE + OFF_SPR)
+#define UART0_SIRCR    (UART0_BASE + OFF_SIRCR)
+#define UART0_UMR      (UART0_BASE + OFF_UMR)
+#define UART0_UACR     (UART0_BASE + OFF_UACR)
+
+/*
+ * Define macros for UARTIER
+ * UART Interrupt Enable Register
+ */
+#define UARTIER_RIE    (1 << 0)        /* 0: receive fifo full interrupt disable */
+#define UARTIER_TIE    (1 << 1)        /* 0: transmit fifo empty interrupt disable */
+#define UARTIER_RLIE   (1 << 2)        /* 0: receive line status interrupt disable */
+#define UARTIER_MIE    (1 << 3)        /* 0: modem status interrupt disable */
+#define UARTIER_RTIE   (1 << 4)        /* 0: receive timeout interrupt disable */
+
+/*
+ * Define macros for UARTISR
+ * UART Interrupt Status Register
+ */
+#define UARTISR_IP     (1 << 0)        /* 0: interrupt is pending  1: no interrupt */
+#define UARTISR_IID    (7 << 1)        /* Source of Interrupt */
+#define UARTISR_IID_MSI                (0 << 1)  /* Modem status interrupt */
+#define UARTISR_IID_THRI       (1 << 1)  /* Transmitter holding register empty */
+#define UARTISR_IID_RDI                (2 << 1)  /* Receiver data interrupt */
+#define UARTISR_IID_RLSI       (3 << 1)  /* Receiver line status interrupt */
+#define UARTISR_IID_RTO                (6 << 1)  /* Receive timeout */
+#define UARTISR_FFMS           (3 << 6)  /* FIFO mode select, set when UARTFCR.FE is set to 1 */
+#define UARTISR_FFMS_NO_FIFO   (0 << 6)
+#define UARTISR_FFMS_FIFO_MODE (3 << 6)
+
+/*
+ * Define macros for UARTFCR
+ * UART FIFO Control Register
+ */
+#define UARTFCR_FE     (1 << 0)        /* 0: non-FIFO mode  1: FIFO mode */
+#define UARTFCR_RFLS   (1 << 1)        /* write 1 to flush receive FIFO */
+#define UARTFCR_TFLS   (1 << 2)        /* write 1 to flush transmit FIFO */
+#define UARTFCR_DMS    (1 << 3)        /* 0: disable DMA mode */
+#define UARTFCR_UUE    (1 << 4)        /* 0: disable UART */
+#define UARTFCR_RTRG   (3 << 6)        /* Receive FIFO Data Trigger */
+#define UARTFCR_RTRG_1 (0 << 6)
+#define UARTFCR_RTRG_4 (1 << 6)
+#define UARTFCR_RTRG_8 (2 << 6)
+#define UARTFCR_RTRG_15        (3 << 6)
+
+/*
+ * Define macros for UARTLCR
+ * UART Line Control Register
+ */
+#define UARTLCR_WLEN   (3 << 0)        /* word length */
+#define UARTLCR_WLEN_5 (0 << 0)
+#define UARTLCR_WLEN_6 (1 << 0)
+#define UARTLCR_WLEN_7 (2 << 0)
+#define UARTLCR_WLEN_8 (3 << 0)
+#define UARTLCR_STOP   (1 << 2)        /* 0: 1 stop bit when word length is 5,6,7,8
+                                          1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
+#define UARTLCR_STOP1  (0 << 2)
+#define UARTLCR_STOP2  (1 << 2)
+#define UARTLCR_PE     (1 << 3)        /* 0: parity disable */
+#define UARTLCR_PROE   (1 << 4)        /* 0: even parity  1: odd parity */
+#define UARTLCR_SPAR   (1 << 5)        /* 0: sticky parity disable */
+#define UARTLCR_SBRK   (1 << 6)        /* write 0 normal, write 1 send break */
+#define UARTLCR_DLAB   (1 << 7)        /* 0: access UARTRDR/TDR/IER  1: access UARTDLLR/DLHR */
+
+/*
+ * Define macros for UARTLSR
+ * UART Line Status Register
+ */
+#define UARTLSR_DR     (1 << 0)        /* 0: receive FIFO is empty  1: receive data is ready */
+#define UARTLSR_ORER   (1 << 1)        /* 0: no overrun error */
+#define UARTLSR_PER    (1 << 2)        /* 0: no parity error */
+#define UARTLSR_FER    (1 << 3)        /* 0; no framing error */
+#define UARTLSR_BRK    (1 << 4)        /* 0: no break detected  1: receive a break signal */
+#define UARTLSR_TDRQ   (1 << 5)        /* 1: transmit FIFO half "empty" */
+#define UARTLSR_TEMT   (1 << 6)        /* 1: transmit FIFO and shift registers empty */
+#define UARTLSR_RFER   (1 << 7)        /* 0: no receive error  1: receive error in FIFO mode */
+
+/*
+ * Define macros for UARTMCR
+ * UART Modem Control Register
+ */
+#define UARTMCR_RTS    (1 << 1)        /* 0: RTS_ output high, 1: RTS_ output low */
+#define UARTMCR_LOOP   (1 << 4)        /* 0: normal  1: loopback mode */
+#define UARTMCR_MCE    (1 << 7)        /* 0: modem function is disable */
+
+/*
+ * Define macros for UARTMSR
+ * UART Modem Status Register
+ */
+#define UARTMSR_CCTS   (1 << 0)        /* 1: a change on CTS_ pin */
+#define UARTMSR_CTS    (1 << 4)        /* 0: CTS_ pin is high */
+
+/*
+ * Define macros for SIRCR
+ * Slow IrDA Control Register
+ */
+#define SIRCR_TSIRE    (1 << 0)  /* 0: transmitter is in UART mode  1: SIR mode */
+#define SIRCR_RSIRE    (1 << 1)  /* 0: receiver is in UART mode  1: SIR mode */
+#define SIRCR_TPWS     (1 << 2)  /* 0: transmit 0 pulse width is 3/16 of bit length
+                                          1: 0 pulse width is 1.6us for 115.2Kbps */
+#define SIRCR_TDPL     (1 << 3)  /* 0: encoder generates a positive pulse for 0 */
+#define SIRCR_RDPL     (1 << 4)  /* 0: decoder interprets positive pulse as 0 */
+
+
+/*************************************************************************
+ * EMC (External Memory Controller)
+ *************************************************************************/
+#define EMC_SMCR0      (EMC_BASE + 0x10)  /* Static Memory Control Register 0 */
+#define EMC_SMCR1      (EMC_BASE + 0x14)  /* Static Memory Control Register 1 */
+#define EMC_SMCR2      (EMC_BASE + 0x18)  /* Static Memory Control Register 2 */
+#define EMC_SMCR3      (EMC_BASE + 0x1c)  /* Static Memory Control Register 3 */
+#define EMC_SMCR4      (EMC_BASE + 0x20)  /* Static Memory Control Register 4 */
+#define EMC_SACR0      (EMC_BASE + 0x30)  /* Static Memory Bank 0 Addr Config Reg */
+#define EMC_SACR1      (EMC_BASE + 0x34)  /* Static Memory Bank 1 Addr Config Reg */
+#define EMC_SACR2      (EMC_BASE + 0x38)  /* Static Memory Bank 2 Addr Config Reg */
+#define EMC_SACR3      (EMC_BASE + 0x3c)  /* Static Memory Bank 3 Addr Config Reg */
+#define EMC_SACR4      (EMC_BASE + 0x40)  /* Static Memory Bank 4 Addr Config Reg */
+
+#define EMC_NFCSR      (EMC_BASE + 0x050) /* NAND Flash Control/Status Register */
+#define EMC_NFECR      (EMC_BASE + 0x100) /* NAND Flash ECC Control Register */
+#define EMC_NFECC      (EMC_BASE + 0x104) /* NAND Flash ECC Data Register */
+#define EMC_NFPAR0     (EMC_BASE + 0x108) /* NAND Flash RS Parity 0 Register */
+#define EMC_NFPAR1     (EMC_BASE + 0x10c) /* NAND Flash RS Parity 1 Register */
+#define EMC_NFPAR2     (EMC_BASE + 0x110) /* NAND Flash RS Parity 2 Register */
+#define EMC_NFINTS     (EMC_BASE + 0x114) /* NAND Flash Interrupt Status Register */
+#define EMC_NFINTE     (EMC_BASE + 0x118) /* NAND Flash Interrupt Enable Register */
+#define EMC_NFERR0     (EMC_BASE + 0x11c) /* NAND Flash RS Error Report 0 Register */
+#define EMC_NFERR1     (EMC_BASE + 0x120) /* NAND Flash RS Error Report 1 Register */
+#define EMC_NFERR2     (EMC_BASE + 0x124) /* NAND Flash RS Error Report 2 Register */
+#define EMC_NFERR3     (EMC_BASE + 0x128) /* NAND Flash RS Error Report 3 Register */
+
+#define EMC_DMCR       (EMC_BASE + 0x80)  /* DRAM Control Register */
+#define EMC_RTCSR      (EMC_BASE + 0x84)  /* Refresh Time Control/Status Register */
+#define EMC_RTCNT      (EMC_BASE + 0x88)  /* Refresh Timer Counter */
+#define EMC_RTCOR      (EMC_BASE + 0x8c)  /* Refresh Time Constant Register */
+#define EMC_DMAR0      (EMC_BASE + 0x90)  /* SDRAM Bank 0 Addr Config Register */
+#define EMC_SDMR0      (EMC_BASE + 0xa000) /* Mode Register of SDRAM bank 0 */
+
+
+#define REG_EMC_SMCR0  REG32(EMC_SMCR0)
+#define REG_EMC_SMCR1  REG32(EMC_SMCR1)
+#define REG_EMC_SMCR2  REG32(EMC_SMCR2)
+#define REG_EMC_SMCR3  REG32(EMC_SMCR3)
+#define REG_EMC_SMCR4  REG32(EMC_SMCR4)
+#define REG_EMC_SACR0  REG32(EMC_SACR0)
+#define REG_EMC_SACR1  REG32(EMC_SACR1)
+#define REG_EMC_SACR2  REG32(EMC_SACR2)
+#define REG_EMC_SACR3  REG32(EMC_SACR3)
+#define REG_EMC_SACR4  REG32(EMC_SACR4)
+
+#define REG_EMC_NFCSR  REG32(EMC_NFCSR)
+#define REG_EMC_NFECR  REG32(EMC_NFECR)
+#define REG_EMC_NFECC  REG32(EMC_NFECC)
+#define REG_EMC_NFPAR0 REG32(EMC_NFPAR0)
+#define REG_EMC_NFPAR1 REG32(EMC_NFPAR1)
+#define REG_EMC_NFPAR2 REG32(EMC_NFPAR2)
+#define REG_EMC_NFINTS REG32(EMC_NFINTS)
+#define REG_EMC_NFINTE REG32(EMC_NFINTE)
+#define REG_EMC_NFERR0 REG32(EMC_NFERR0)
+#define REG_EMC_NFERR1 REG32(EMC_NFERR1)
+#define REG_EMC_NFERR2 REG32(EMC_NFERR2)
+#define REG_EMC_NFERR3 REG32(EMC_NFERR3)
+
+#define REG_EMC_DMCR   REG32(EMC_DMCR)
+#define REG_EMC_RTCSR  REG16(EMC_RTCSR)
+#define REG_EMC_RTCNT  REG16(EMC_RTCNT)
+#define REG_EMC_RTCOR  REG16(EMC_RTCOR)
+#define REG_EMC_DMAR0  REG32(EMC_DMAR0)
+
+/* Static Memory Control Register */
+#define EMC_SMCR_STRV_BIT      24
+#define EMC_SMCR_STRV_MASK     (0x0f << EMC_SMCR_STRV_BIT)
+#define EMC_SMCR_TAW_BIT       20
+#define EMC_SMCR_TAW_MASK      (0x0f << EMC_SMCR_TAW_BIT)
+#define EMC_SMCR_TBP_BIT       16
+#define EMC_SMCR_TBP_MASK      (0x0f << EMC_SMCR_TBP_BIT)
+#define EMC_SMCR_TAH_BIT       12
+#define EMC_SMCR_TAH_MASK      (0x07 << EMC_SMCR_TAH_BIT)
+#define EMC_SMCR_TAS_BIT       8
+#define EMC_SMCR_TAS_MASK      (0x07 << EMC_SMCR_TAS_BIT)
+#define EMC_SMCR_BW_BIT                6
+#define EMC_SMCR_BW_MASK       (0x03 << EMC_SMCR_BW_BIT)
+  #define EMC_SMCR_BW_8BIT     (0 << EMC_SMCR_BW_BIT)
+  #define EMC_SMCR_BW_16BIT    (1 << EMC_SMCR_BW_BIT)
+  #define EMC_SMCR_BW_32BIT    (2 << EMC_SMCR_BW_BIT)
+#define EMC_SMCR_BCM           (1 << 3)
+#define EMC_SMCR_BL_BIT                1
+#define EMC_SMCR_BL_MASK       (0x03 << EMC_SMCR_BL_BIT)
+  #define EMC_SMCR_BL_4                (0 << EMC_SMCR_BL_BIT)
+  #define EMC_SMCR_BL_8                (1 << EMC_SMCR_BL_BIT)
+  #define EMC_SMCR_BL_16       (2 << EMC_SMCR_BL_BIT)
+  #define EMC_SMCR_BL_32       (3 << EMC_SMCR_BL_BIT)
+#define EMC_SMCR_SMT           (1 << 0)
+
+/* Static Memory Bank Addr Config Reg */
+#define EMC_SACR_BASE_BIT      8
+#define EMC_SACR_BASE_MASK     (0xff << EMC_SACR_BASE_BIT)
+#define EMC_SACR_MASK_BIT      0
+#define EMC_SACR_MASK_MASK     (0xff << EMC_SACR_MASK_BIT)
+
+/* NAND Flash Control/Status Register */
+#define EMC_NFCSR_NFCE4                (1 << 7) /* NAND Flash Enable */
+#define EMC_NFCSR_NFE4         (1 << 6) /* NAND Flash FCE# Assertion Enable */
+#define EMC_NFCSR_NFCE3                (1 << 5)
+#define EMC_NFCSR_NFE3         (1 << 4)
+#define EMC_NFCSR_NFCE2                (1 << 3)
+#define EMC_NFCSR_NFE2         (1 << 2)
+#define EMC_NFCSR_NFCE1                (1 << 1)
+#define EMC_NFCSR_NFE1         (1 << 0)
+
+/* NAND Flash ECC Control Register */
+#define EMC_NFECR_PRDY         (1 << 4) /* Parity Ready */
+#define EMC_NFECR_RS_DECODING  (0 << 3) /* RS is in decoding phase */
+#define EMC_NFECR_RS_ENCODING  (1 << 3) /* RS is in encoding phase */
+#define EMC_NFECR_HAMMING      (0 << 2) /* Select HAMMING Correction Algorithm */
+#define EMC_NFECR_RS           (1 << 2) /* Select RS Correction Algorithm */
+#define EMC_NFECR_ERST         (1 << 1) /* ECC Reset */
+#define EMC_NFECR_ECCE         (1 << 0) /* ECC Enable */
+
+/* NAND Flash ECC Data Register */
+#define EMC_NFECC_ECC2_BIT     16
+#define EMC_NFECC_ECC2_MASK    (0xff << EMC_NFECC_ECC2_BIT)
+#define EMC_NFECC_ECC1_BIT     8
+#define EMC_NFECC_ECC1_MASK    (0xff << EMC_NFECC_ECC1_BIT)
+#define EMC_NFECC_ECC0_BIT     0
+#define EMC_NFECC_ECC0_MASK    (0xff << EMC_NFECC_ECC0_BIT)
+
+/* NAND Flash Interrupt Status Register */
+#define EMC_NFINTS_ERRCNT_BIT  29       /* Error Count */
+#define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT)
+#define EMC_NFINTS_PADF                (1 << 4) /* Padding Finished */
+#define EMC_NFINTS_DECF                (1 << 3) /* Decoding Finished */
+#define EMC_NFINTS_ENCF                (1 << 2) /* Encoding Finished */
+#define EMC_NFINTS_UNCOR       (1 << 1) /* Uncorrectable Error Occurred */
+#define EMC_NFINTS_ERR         (1 << 0) /* Error Occurred */
+
+/* NAND Flash Interrupt Enable Register */
+#define EMC_NFINTE_PADFE       (1 << 4) /* Padding Finished Interrupt Enable */
+#define EMC_NFINTE_DECFE       (1 << 3) /* Decoding Finished Interrupt Enable */
+#define EMC_NFINTE_ENCFE       (1 << 2) /* Encoding Finished Interrupt Enable */
+#define EMC_NFINTE_UNCORE      (1 << 1) /* Uncorrectable Error Occurred Intr Enable */
+#define EMC_NFINTE_ERRE                (1 << 0) /* Error Occurred Interrupt */
+
+/* NAND Flash RS Error Report Register */
+#define EMC_NFERR_INDEX_BIT    16       /* Error Symbol Index */
+#define EMC_NFERR_INDEX_MASK   (0x1ff << EMC_NFERR_INDEX_BIT)
+#define EMC_NFERR_MASK_BIT     0        /* Error Symbol Value */
+#define EMC_NFERR_MASK_MASK    (0x1ff << EMC_NFERR_MASK_BIT)
+
+
+/* DRAM Control Register */
+#define EMC_DMCR_BW_BIT                31
+#define EMC_DMCR_BW            (1 << EMC_DMCR_BW_BIT)
+#define EMC_DMCR_CA_BIT                26
+#define EMC_DMCR_CA_MASK       (0x07 << EMC_DMCR_CA_BIT)
+  #define EMC_DMCR_CA_8                (0 << EMC_DMCR_CA_BIT)
+  #define EMC_DMCR_CA_9                (1 << EMC_DMCR_CA_BIT)
+  #define EMC_DMCR_CA_10       (2 << EMC_DMCR_CA_BIT)
+  #define EMC_DMCR_CA_11       (3 << EMC_DMCR_CA_BIT)
+  #define EMC_DMCR_CA_12       (4 << EMC_DMCR_CA_BIT)
+#define EMC_DMCR_RMODE         (1 << 25)
+#define EMC_DMCR_RFSH          (1 << 24)
+#define EMC_DMCR_MRSET         (1 << 23)
+#define EMC_DMCR_RA_BIT                20
+#define EMC_DMCR_RA_MASK       (0x03 << EMC_DMCR_RA_BIT)
+  #define EMC_DMCR_RA_11       (0 << EMC_DMCR_RA_BIT)
+  #define EMC_DMCR_RA_12       (1 << EMC_DMCR_RA_BIT)
+  #define EMC_DMCR_RA_13       (2 << EMC_DMCR_RA_BIT)
+#define EMC_DMCR_BA_BIT                19
+#define EMC_DMCR_BA            (1 << EMC_DMCR_BA_BIT)
+#define EMC_DMCR_PDM           (1 << 18)
+#define EMC_DMCR_EPIN          (1 << 17)
+#define EMC_DMCR_TRAS_BIT      13
+#define EMC_DMCR_TRAS_MASK     (0x07 << EMC_DMCR_TRAS_BIT)
+#define EMC_DMCR_RCD_BIT       11
+#define EMC_DMCR_RCD_MASK      (0x03 << EMC_DMCR_RCD_BIT)
+#define EMC_DMCR_TPC_BIT       8
+#define EMC_DMCR_TPC_MASK      (0x07 << EMC_DMCR_TPC_BIT)
+#define EMC_DMCR_TRWL_BIT      5
+#define EMC_DMCR_TRWL_MASK     (0x03 << EMC_DMCR_TRWL_BIT)
+#define EMC_DMCR_TRC_BIT       2
+#define EMC_DMCR_TRC_MASK      (0x07 << EMC_DMCR_TRC_BIT)
+#define EMC_DMCR_TCL_BIT       0
+#define EMC_DMCR_TCL_MASK      (0x03 << EMC_DMCR_TCL_BIT)
+
+/* Refresh Time Control/Status Register */
+#define EMC_RTCSR_CMF          (1 << 7)
+#define EMC_RTCSR_CKS_BIT      0
+#define EMC_RTCSR_CKS_MASK     (0x07 << EMC_RTCSR_CKS_BIT)
+  #define EMC_RTCSR_CKS_DISABLE        (0 << EMC_RTCSR_CKS_BIT)
+  #define EMC_RTCSR_CKS_4      (1 << EMC_RTCSR_CKS_BIT)
+  #define EMC_RTCSR_CKS_16     (2 << EMC_RTCSR_CKS_BIT)
+  #define EMC_RTCSR_CKS_64     (3 << EMC_RTCSR_CKS_BIT)
+  #define EMC_RTCSR_CKS_256    (4 << EMC_RTCSR_CKS_BIT)
+  #define EMC_RTCSR_CKS_1024   (5 << EMC_RTCSR_CKS_BIT)
+  #define EMC_RTCSR_CKS_2048   (6 << EMC_RTCSR_CKS_BIT)
+  #define EMC_RTCSR_CKS_4096   (7 << EMC_RTCSR_CKS_BIT)
+
+/* SDRAM Bank Address Configuration Register */
+#define EMC_DMAR_BASE_BIT      8
+#define EMC_DMAR_BASE_MASK     (0xff << EMC_DMAR_BASE_BIT)
+#define EMC_DMAR_MASK_BIT      0
+#define EMC_DMAR_MASK_MASK     (0xff << EMC_DMAR_MASK_BIT)
+
+/* Mode Register of SDRAM bank 0 */
+#define EMC_SDMR_BM            (1 << 9) /* Write Burst Mode */
+#define EMC_SDMR_OM_BIT                7        /* Operating Mode */
+#define EMC_SDMR_OM_MASK       (3 << EMC_SDMR_OM_BIT)
+  #define EMC_SDMR_OM_NORMAL   (0 << EMC_SDMR_OM_BIT)
+#define EMC_SDMR_CAS_BIT       4        /* CAS Latency */
+#define EMC_SDMR_CAS_MASK      (7 << EMC_SDMR_CAS_BIT)
+  #define EMC_SDMR_CAS_1       (1 << EMC_SDMR_CAS_BIT)
+  #define EMC_SDMR_CAS_2       (2 << EMC_SDMR_CAS_BIT)
+  #define EMC_SDMR_CAS_3       (3 << EMC_SDMR_CAS_BIT)
+#define EMC_SDMR_BT_BIT                3        /* Burst Type */
+#define EMC_SDMR_BT_MASK       (1 << EMC_SDMR_BT_BIT)
+  #define EMC_SDMR_BT_SEQ      (0 << EMC_SDMR_BT_BIT) /* Sequential */
+  #define EMC_SDMR_BT_INT      (1 << EMC_SDMR_BT_BIT) /* Interleave */
+#define EMC_SDMR_BL_BIT                0        /* Burst Length */
+#define EMC_SDMR_BL_MASK       (7 << EMC_SDMR_BL_BIT)
+  #define EMC_SDMR_BL_1                (0 << EMC_SDMR_BL_BIT)
+  #define EMC_SDMR_BL_2                (1 << EMC_SDMR_BL_BIT)
+  #define EMC_SDMR_BL_4                (2 << EMC_SDMR_BL_BIT)
+  #define EMC_SDMR_BL_8                (3 << EMC_SDMR_BL_BIT)
+
+#define EMC_SDMR_CAS2_16BIT \
+  (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
+#define EMC_SDMR_CAS2_32BIT \
+  (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
+#define EMC_SDMR_CAS3_16BIT \
+  (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
+#define EMC_SDMR_CAS3_32BIT \
+  (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
+
+/*************************************************************************
+ * WDT (WatchDog Timer)
+ *************************************************************************/
+#define WDT_TDR                (WDT_BASE + 0x00)
+#define WDT_TCER       (WDT_BASE + 0x04)
+#define WDT_TCNT       (WDT_BASE + 0x08)
+#define WDT_TCSR       (WDT_BASE + 0x0C)
+
+#define REG_WDT_TDR    REG16(WDT_TDR)
+#define REG_WDT_TCER   REG8(WDT_TCER)
+#define REG_WDT_TCNT   REG16(WDT_TCNT)
+#define REG_WDT_TCSR   REG16(WDT_TCSR)
+
+// Register definition
+#define WDT_TCSR_PRESCALE_BIT  3
+#define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT)
+  #define WDT_TCSR_PRESCALE1   (0x0 << WDT_TCSR_PRESCALE_BIT)
+  #define WDT_TCSR_PRESCALE4   (0x1 << WDT_TCSR_PRESCALE_BIT)
+  #define WDT_TCSR_PRESCALE16  (0x2 << WDT_TCSR_PRESCALE_BIT)
+  #define WDT_TCSR_PRESCALE64  (0x3 << WDT_TCSR_PRESCALE_BIT)
+  #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT)
+  #define WDT_TCSR_PRESCALE1024        (0x5 << WDT_TCSR_PRESCALE_BIT)
+#define WDT_TCSR_EXT_EN                (1 << 2)
+#define WDT_TCSR_RTC_EN                (1 << 1)
+#define WDT_TCSR_PCK_EN                (1 << 0)
+
+#define WDT_TCER_TCEN          (1 << 0)
+
+/*************************************************************************
+ * RTC
+ *************************************************************************/
+#define RTC_RCR                (RTC_BASE + 0x00) /* RTC Control Register */
+#define RTC_RSR                (RTC_BASE + 0x04) /* RTC Second Register */
+#define RTC_RSAR       (RTC_BASE + 0x08) /* RTC Second Alarm Register */
+#define RTC_RGR                (RTC_BASE + 0x0c) /* RTC Regulator Register */
+
+#define RTC_HCR                (RTC_BASE + 0x20) /* Hibernate Control Register */
+#define RTC_HWFCR      (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */
+#define RTC_HRCR       (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */
+#define RTC_HWCR       (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */
+#define RTC_HWRSR      (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */
+#define RTC_HSPR       (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */
+
+#define REG_RTC_RCR    REG32(RTC_RCR)
+#define REG_RTC_RSR    REG32(RTC_RSR)
+#define REG_RTC_RSAR   REG32(RTC_RSAR)
+#define REG_RTC_RGR    REG32(RTC_RGR)
+#define REG_RTC_HCR    REG32(RTC_HCR)
+#define REG_RTC_HWFCR  REG32(RTC_HWFCR)
+#define REG_RTC_HRCR   REG32(RTC_HRCR)
+#define REG_RTC_HWCR   REG32(RTC_HWCR)
+#define REG_RTC_HWRSR  REG32(RTC_HWRSR)
+#define REG_RTC_HSPR   REG32(RTC_HSPR)
+
+/* RTC Control Register */
+#define RTC_RCR_WRDY_BIT 7
+#define RTC_RCR_WRDY   (1 << 7)  /* Write Ready Flag */
+#define RTC_RCR_1HZ_BIT        6
+#define RTC_RCR_1HZ    (1 << RTC_RCR_1HZ_BIT)  /* 1Hz Flag */
+#define RTC_RCR_1HZIE  (1 << 5)  /* 1Hz Interrupt Enable */
+#define RTC_RCR_AF_BIT 4
+#define RTC_RCR_AF     (1 << RTC_RCR_AF_BIT)  /* Alarm Flag */
+#define RTC_RCR_AIE    (1 << 3)  /* Alarm Interrupt Enable */
+#define RTC_RCR_AE     (1 << 2)  /* Alarm Enable */
+#define RTC_RCR_RTCE   (1 << 0)  /* RTC Enable */
+
+/* RTC Regulator Register */
+#define RTC_RGR_LOCK           (1 << 31) /* Lock Bit */
+#define RTC_RGR_ADJC_BIT       16
+#define RTC_RGR_ADJC_MASK      (0x3ff << RTC_RGR_ADJC_BIT)
+#define RTC_RGR_NC1HZ_BIT      0
+#define RTC_RGR_NC1HZ_MASK     (0xffff << RTC_RGR_NC1HZ_BIT)
+
+/* Hibernate Control Register */
+#define RTC_HCR_PD             (1 << 0)  /* Power Down */
+
+/* Hibernate Wakeup Filter Counter Register */
+#define RTC_HWFCR_BIT          5
+#define RTC_HWFCR_MASK         (0x7ff << RTC_HWFCR_BIT)
+
+/* Hibernate Reset Counter Register */
+#define RTC_HRCR_BIT           5
+#define RTC_HRCR_MASK          (0x7f << RTC_HRCR_BIT)
+
+/* Hibernate Wakeup Control Register */
+#define RTC_HWCR_EALM          (1 << 0)  /* RTC alarm wakeup enable */
+
+/* Hibernate Wakeup Status Register */
+#define RTC_HWRSR_HR           (1 << 5)  /* Hibernate reset */
+#define RTC_HWRSR_PPR          (1 << 4)  /* PPR reset */
+#define RTC_HWRSR_PIN          (1 << 1)  /* Wakeup pin status bit */
+#define RTC_HWRSR_ALM          (1 << 0)  /* RTC alarm status bit */
+
+#endif /* __JZ4740_REGS_H__ */
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/serial.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/serial.h
new file mode 100644 (file)
index 0000000..c4819b9
--- /dev/null
@@ -0,0 +1,30 @@
+/*
+ *  linux/include/asm-mips/mach-jz4740/serial.h
+ *
+ *  Ingenic's JZ4740 common include.
+ *
+ *  Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
+ *
+ *  Author: <yliu@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_BOARD_SERIAL_H__
+#define __ASM_BOARD_SERIAL_H__
+
+#ifndef CONFIG_SERIAL_MANY_PORTS
+#undef RS_TABLE_SIZE
+#define RS_TABLE_SIZE  1
+#endif
+
+#define JZ_BASE_BAUD   (12000000/16)
+
+#define JZ_SERIAL_PORT_DEFNS \
+       { .baud_base = JZ_BASE_BAUD, .irq = IRQ_UART0, \
+         .flags = STD_COM_FLAGS, .iomem_base = (u8 *)UART0_BASE, \
+         .iomem_reg_shift = 2, .io_type = SERIAL_IO_MEM },
+
+#endif /* __ASM_BORAD_SERIAL_H__ */
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/timer.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/timer.h
new file mode 100644 (file)
index 0000000..3214f36
--- /dev/null
@@ -0,0 +1,22 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *     JZ4740 platform timer support
+ *
+ *  This program is free software; you can redistribute         it and/or modify it
+ *  under  the terms of         the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __ASM_MACH_JZ4740_TIMER
+#define __ASM_MACH_JZ4740_TIMER
+
+void jz4740_timer_enable_watchdog(void);
+void jz4740_timer_disable_watchdog(void);
+
+#endif
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/war.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/war.h
new file mode 100644 (file)
index 0000000..3a5bc17
--- /dev/null
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_JZ4740_WAR_H
+#define __ASM_MIPS_MACH_JZ4740_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR    0
+#define R4600_V1_HIT_CACHEOP_WAR       0
+#define R4600_V2_HIT_CACHEOP_WAR       0
+#define R5432_CP0_INTERRUPT_WAR                0
+#define BCM1250_M3_WAR                 0
+#define SIBYTE_1956_WAR                        0
+#define MIPS4K_ICACHE_REFILL_WAR       0
+#define MIPS_CACHE_SYNC_WAR            0
+#define TX49XX_ICACHE_INDEX_INV_WAR    0
+#define RM9000_CDEX_SMP_WAR            0
+#define ICACHE_REFILLS_WORKAROUND_WAR  0
+#define R10000_LLSC_WAR                        0
+#define MIPS34K_MISSED_ITLB_WAR                0
+
+#endif /* __ASM_MIPS_MACH_JZ4740_WAR_H */
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/Kconfig b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/Kconfig
new file mode 100644 (file)
index 0000000..015e056
--- /dev/null
@@ -0,0 +1,35 @@
+choice
+    prompt "Machine type"
+    depends on MACH_JZ
+    default JZ4740_QI_LB60
+
+config JZ4740_QI_LB60
+       bool "Qi Hardware Ben NanoNote"
+       select DMA_NONCOHERENT
+       select SOC_JZ4740
+
+config JZ4740_N526
+       bool "Hanvon n526 eBook reader"
+       select DMA_NONCOHERENT
+       select SOC_JZ4740
+
+
+endchoice
+
+config SOC_JZ4740
+       bool
+       select JZSOC
+       select GENERIC_GPIO
+       select ARCH_REQUIRE_GPIOLIB
+       select SYS_HAS_EARLY_PRINTK
+       select SYS_SUPPORTS_LITTLE_ENDIAN
+       select IRQ_CPU
+
+config JZSOC
+       bool
+       select JZRISC
+       select SYS_HAS_CPU_MIPS32_R1
+       select SYS_SUPPORTS_32BIT_KERNEL
+
+config JZRISC
+       bool
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/Makefile b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/Makefile
new file mode 100644 (file)
index 0000000..19fc95c
--- /dev/null
@@ -0,0 +1,18 @@
+#
+# Makefile for the Ingenic JZ4740.
+#
+
+# Object file lists.
+
+obj-y += prom.o irq.o time.o reset.o setup.o dma.o \
+       gpio.o clock.o platform.o
+
+# board specific support
+
+obj-$(CONFIG_JZ4740_QI_LB60)   += board-qi_lb60.o
+obj-$(CONFIG_JZ4740_N526)      += board-n526.o
+
+# PM support
+
+obj-$(CONFIG_PM)         +=pm.o
+
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/board-n526.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/board-n526.c
new file mode 100644 (file)
index 0000000..fa46278
--- /dev/null
@@ -0,0 +1,346 @@
+/*
+ *  Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
+ *     N526 eBook reader support
+ *
+ *  This program is free software; you can redistribute         it and/or modify it
+ *  under  the terms of         the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+
+#include <asm/mach-jz4740/platform.h>
+
+#include <linux/mtd/jz4740_nand.h>
+#include <linux/jz4740_fb.h>
+#include <linux/power_supply.h>
+#include <linux/power/jz4740-battery.h>
+#include <linux/mmc/jz4740_mmc.h>
+
+#include <video/broadsheetfb.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+
+/* NAND */
+static struct nand_ecclayout n526_ecclayout = {
+       .eccbytes = 36,
+       .eccpos = {
+               6,  7,  8,  9,  10, 11, 12, 13,
+               14, 15, 16, 17, 18, 19, 20, 21,
+               22, 23, 24, 25, 26, 27, 28, 29,
+               30, 31, 32, 33, 34, 35, 36, 37,
+               38, 39, 40, 41},
+       .oobfree = {
+               {.offset = 2,
+                .length = 4},
+               {.offset = 42,
+                .length = 22}}
+};
+
+static struct mtd_partition n526_partitions[] = {
+       { .name = "NAND BOOT partition",
+         .offset = 0 * 0x100000,
+         .size = 4 * 0x100000,
+       },
+       { .name = "NAND KERNEL partition",
+         .offset = 4 * 0x100000,
+         .size = 4 * 0x100000,
+       },
+       { .name = "NAND ROOTFS partition",
+         .offset = 16 * 0x100000,
+         .size = 498 * 0x100000,
+       },
+};
+
+static struct jz_nand_platform_data n526_nand_pdata = {
+       .ecc_layout = &n526_ecclayout,
+       .partitions = n526_partitions,
+       .num_partitions = ARRAY_SIZE(n526_partitions),
+       .busy_gpio = 94,
+};
+
+
+/* Battery */
+/*static struct jz_batt_info n526_battery_pdata = {
+       .dc_dect_gpio   = GPIO_DC_DETE_N,
+       .usb_dect_gpio  = GPIO_USB_DETE,
+       .charg_stat_gpio  = GPIO_CHARG_STAT_N,
+
+       .min_voltag     = 3600000,
+       .max_voltag     = 4200000,
+       .batt_tech      = POWER_SUPPLY_TECHNOLOGY_LIPO,
+};*/
+
+
+static struct jz4740_mmc_platform_data n526_mmc_pdata = {
+       .gpio_card_detect       = JZ_GPIO_PORTD(7),
+       .card_detect_active_low = 1,
+       .gpio_read_only         = -1,
+       .gpio_power             = JZ_GPIO_PORTD(17),
+       .power_active_low = 1,
+};
+
+static struct gpio_led n526_leds[] = {
+       {
+               .name = "n526:blue:power",
+               .gpio = JZ_GPIO_PORTD(28),
+               .default_state = LEDS_GPIO_DEFSTATE_ON,
+       }
+};
+
+static struct gpio_led_platform_data n526_leds_pdata = {
+       .leds = n526_leds,
+       .num_leds = ARRAY_SIZE(n526_leds),
+};
+
+static struct platform_device n526_leds_device = {
+       .name = "leds-gpio",
+       .id = -1,
+       .dev = {
+               .platform_data = &n526_leds_pdata,
+       },
+};
+
+static void __init board_gpio_setup(void)
+{
+       /* We only need to enable/disable pullup here for pins used in generic
+        * drivers. Everything else is done by the drivers themselfs. */
+       jz_gpio_disable_pullup(JZ_GPIO_PORTD(17));
+       jz_gpio_enable_pullup(JZ_GPIO_PORTD(7));
+       jz_gpio_disable_pullup(JZ_GPIO_PORTC(19));
+       jz_gpio_disable_pullup(JZ_GPIO_PORTC(20));
+       jz_gpio_disable_pullup(JZ_GPIO_PORTC(21));
+       jz_gpio_disable_pullup(JZ_GPIO_PORTC(23));
+}
+
+
+static const int n526_eink_ctrl_gpios[] = {
+       0,
+       JZ_GPIO_PORTC(23),
+       JZ_GPIO_PORTC(19),
+       JZ_GPIO_PORTC(20),
+};
+
+static void n526_eink_set_ctl(struct broadsheetfb_par * par, unsigned char ctrl, u8
+value)
+{
+       gpio_set_value(n526_eink_ctrl_gpios[ctrl], value);
+}
+
+
+static int n526_eink_wait(struct broadsheetfb_par *par)
+{
+       int i = 0;
+       wait_event(par->waitq, gpio_get_value(JZ_GPIO_PORTB(17)));
+
+       return 0;
+}
+
+static u16 n526_eink_get_hdb(struct broadsheetfb_par *par)
+{
+       u16 value = 0;
+       jz_gpio_port_direction_input(JZ_GPIO_PORTC(0), 0xffff);
+       gpio_set_value(JZ_GPIO_PORTC(21), 0);
+       mdelay(100);
+
+       value = jz_gpio_port_get_value(JZ_GPIO_PORTC(0), 0xffff);
+
+       gpio_set_value(JZ_GPIO_PORTC(21), 1);
+       jz_gpio_port_direction_output(JZ_GPIO_PORTC(0), 0xffff);
+       return value;
+}
+
+static void n526_eink_set_hdb(struct broadsheetfb_par *par, u16 value)
+{
+       jz_gpio_port_set_value(JZ_GPIO_PORTC(0), value, 0xffff);
+}
+
+static int n526_eink_init(struct broadsheetfb_par *par)
+{
+       int i = 0;
+
+       gpio_request(JZ_GPIO_PORTD(1), "display reset?");
+       gpio_direction_output(JZ_GPIO_PORTD(1), 1);
+       mdelay(10);
+       gpio_set_value(JZ_GPIO_PORTD(1), 0);
+
+       gpio_request(JZ_GPIO_PORTB(18), "foobar");
+       gpio_direction_output(JZ_GPIO_PORTB(18), 0);
+
+       gpio_request(JZ_GPIO_PORTB(29), "foobar");
+       gpio_direction_output(JZ_GPIO_PORTB(29), 1);
+
+
+       for(i = 1; i < ARRAY_SIZE(n526_eink_ctrl_gpios); ++i) {
+               gpio_request(n526_eink_ctrl_gpios[i], "foobar");
+               gpio_direction_output(n526_eink_ctrl_gpios[i], 0);
+       }
+
+       gpio_request(JZ_GPIO_PORTC(22), "foobar");
+       gpio_direction_input(JZ_GPIO_PORTC(22));
+       gpio_request(JZ_GPIO_PORTC(21), "foobar");
+       gpio_direction_output(JZ_GPIO_PORTC(21), 1);
+
+       for(i = 0; i < 16; ++i) {
+               gpio_request(JZ_GPIO_PORTC(i), "display data");
+       }
+       jz_gpio_port_direction_output(JZ_GPIO_PORTC(0), 0xffff);
+
+       gpio_direction_output(JZ_GPIO_PORTB(18), 1);
+
+       return 0;
+}
+
+static irqreturn_t n526_eink_busy_irq(int irq, void *devid)
+{
+       struct broadsheetfb_par *par = devid;
+       wake_up(&par->waitq);
+
+       return IRQ_HANDLED;
+}
+
+static int n526_eink_setup_irq(struct fb_info *info)
+{
+       int ret;
+       struct broadsheetfb_par *par = info->par;
+
+       gpio_request(JZ_GPIO_PORTB(17), "foobar");
+       gpio_direction_input(JZ_GPIO_PORTB(17));
+
+       ret = request_irq(gpio_to_irq(JZ_GPIO_PORTB(17)), n526_eink_busy_irq,
+                               IRQF_DISABLED | IRQF_TRIGGER_RISING,
+                               "eInk busyline", par);
+       if (ret)
+               printk("n526 display: Failed to request busyline irq: %d\n", ret);
+       return 0;
+}
+
+static void n526_eink_cleanup(struct broadsheetfb_par *par)
+{
+}
+
+static struct broadsheet_board broadsheet_pdata = {
+       .owner = THIS_MODULE,
+       .init = n526_eink_init,
+       .wait_for_rdy = n526_eink_wait,
+       .set_ctl = n526_eink_set_ctl,
+       .set_hdb = n526_eink_set_hdb,
+       .get_hdb = n526_eink_get_hdb,
+       .cleanup = n526_eink_cleanup,
+       .setup_irq = n526_eink_setup_irq,
+};
+
+static struct platform_device n526_broadsheet_device = {
+       .name = "broadsheetfb",
+       .id = -1,
+       .dev = {
+               .platform_data = &broadsheet_pdata,
+       },
+};
+
+static struct gpio_keys_button qi_lb60_gpio_keys_buttons[] = {
+       [0] = {
+               .code           = KEY_ENTER,
+               .gpio           = 0,
+               .active_low     = 1,
+               .desc           = "Power",
+       },
+};
+
+static struct gpio_keys_platform_data qi_lb60_gpio_keys_data = {
+       .nbuttons = ARRAY_SIZE(qi_lb60_gpio_keys_buttons),
+       .buttons = qi_lb60_gpio_keys_buttons,
+};
+
+static struct platform_device qi_lb60_gpio_keys = {
+       .name = "gpio-keys",
+       .id =   -1,
+       .dev = {
+               .platform_data = &qi_lb60_gpio_keys_data,
+       }
+};
+
+static struct i2c_gpio_platform_data n526_i2c_pdata = {
+       .sda_pin = JZ_GPIO_PORTD(23),
+       .scl_pin = JZ_GPIO_PORTD(24),
+       .udelay = 2,
+       .timeout = 3 * HZ,
+};
+
+static struct platform_device n526_i2c_device = {
+       .name = "i2c-gpio",
+       .id = -1,
+       .dev = {
+               .platform_data = &n526_i2c_pdata,
+       },
+};
+
+static struct i2c_board_info n526_i2c_board_info = {
+       .type = "n526-lpc",
+       .addr = 0x54,
+};
+
+
+static struct platform_device *jz_platform_devices[] __initdata = {
+       &jz4740_usb_ohci_device,
+       &jz4740_usb_gdt_device,
+       &jz4740_mmc_device,
+       &jz4740_nand_device,
+       &jz4740_i2s_device,
+       &jz4740_codec_device,
+       &jz4740_rtc_device,
+       &n526_leds_device,
+       &n526_broadsheet_device,
+       &qi_lb60_gpio_keys,
+       &n526_i2c_device,
+};
+
+
+static int __init n526_init_platform_devices(void)
+{
+
+       jz4740_nand_device.dev.platform_data = &n526_nand_pdata;
+/*     jz4740_battery_device.dev.platform_data = &n526_battery_pdata;*/
+       jz4740_mmc_device.dev.platform_data = &n526_mmc_pdata;
+
+       n526_i2c_board_info.irq = gpio_to_irq(JZ_GPIO_PORTD(14)),
+       i2c_register_board_info(0, &n526_i2c_board_info, 1);
+
+       return platform_add_devices(jz_platform_devices,
+                                       ARRAY_SIZE(jz_platform_devices));
+
+}
+
+
+extern int jz_gpiolib_init(void);
+extern int jz_init_clocks(unsigned long extal);
+
+static int __init n526_board_setup(void)
+{
+       if (jz_gpiolib_init())
+               panic("Failed to initalize jz gpio\n");
+       jz_init_clocks(12000000);
+
+       board_gpio_setup();
+
+       if (n526_init_platform_devices())
+               panic("Failed to initalize platform devices\n");
+
+       return 0;
+}
+
+arch_initcall(n526_board_setup);
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/board-qi_lb60.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/board-qi_lb60.c
new file mode 100644 (file)
index 0000000..5d22e20
--- /dev/null
@@ -0,0 +1,394 @@
+/*
+ * linux/arch/mips/jz4740/board-qi_lb60.c
+ *
+ * QI_LB60 setup routines.
+ *
+ * Copyright (c) 2009 Qi Hardware inc.,
+ * Author: Xiangfu Liu <xiangfu@qi-hardware.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 or later
+ * as published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+
+#include <asm/mach-jz4740/board-qi_lb60.h>
+#include <asm/mach-jz4740/platform.h>
+
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+#include <linux/mtd/jz4740_nand.h>
+#include <linux/jz4740_fb.h>
+#include <linux/input/matrix_keypad.h>
+#include <linux/mtd/jz4740_nand.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi_gpio.h>
+#include <linux/power_supply.h>
+#include <linux/power/jz4740-battery.h>
+#include <linux/mmc/jz4740_mmc.h>
+
+
+/* NAND */
+static struct nand_ecclayout qi_lb60_ecclayout_1gb = {
+       .eccbytes = 36,
+       .eccpos = {
+               6,  7,  8,  9,  10, 11, 12, 13,
+               14, 15, 16, 17, 18, 19, 20, 21,
+               22, 23, 24, 25, 26, 27, 28, 29,
+               30, 31, 32, 33, 34, 35, 36, 37,
+               38, 39, 40, 41},
+       .oobfree = {
+               {.offset = 2,
+                .length = 4},
+               {.offset = 42,
+                .length = 22}}
+};
+
+static struct mtd_partition qi_lb60_partitions_1gb[] = {
+       { .name = "NAND BOOT partition",
+         .offset = 0 * 0x100000,
+         .size = 4 * 0x100000,
+       },
+       { .name = "NAND KERNEL partition",
+         .offset = 4 * 0x100000,
+         .size = 4 * 0x100000,
+       },
+       { .name = "NAND ROOTFS partition",
+         .offset = 8 * 0x100000,
+         .size = (504 + 512) * 0x100000,
+       },
+};
+
+static struct nand_ecclayout qi_lb60_ecclayout_2gb = {
+       .eccbytes = 72,
+       .eccpos = {
+               12, 13, 14, 15, 16, 17, 18, 19,
+               20, 21, 22, 23, 24, 25, 26, 27, 
+               28, 29, 30, 31, 32, 33, 34, 35,
+               36, 37, 38, 39, 40, 41, 42, 43,
+               44, 45, 46, 47, 48, 49, 50, 51, 
+               52, 53, 54, 55, 56, 57, 58, 59, 
+               60, 61, 62, 63, 64, 65, 66, 67, 
+               68, 69, 70, 71, 72, 73, 74, 75, 
+               76, 77, 78, 79, 80, 81, 82, 83},
+       .oobfree = {
+               {.offset = 2,
+                .length = 10},
+               {.offset = 84,
+                .length = 44}}
+};
+
+static struct mtd_partition qi_lb60_partitions_2gb[] = {
+       { .name = "NAND BOOT partition",
+         .offset = 0 * 0x100000,
+         .size = 4 * 0x100000,
+       },
+       { .name = "NAND KERNEL partition",
+         .offset = 4 * 0x100000,
+         .size = 4 * 0x100000,
+       },
+       { .name = "NAND ROOTFS partition",
+         .offset = 8 * 0x100000,
+         .size = (504 + 512 + 1024) * 0x100000,
+       },
+};
+
+static void qi_lb60_nand_ident(struct platform_device *pdev,
+                               struct nand_chip *chip, 
+                               struct mtd_partition **partitions,
+                               int *num_partitions)
+{
+       if (chip->page_shift == 12) {
+               chip->ecc.layout = &qi_lb60_ecclayout_2gb;
+               *partitions = qi_lb60_partitions_2gb;
+               *num_partitions = ARRAY_SIZE(qi_lb60_partitions_2gb);
+       } else {
+               chip->ecc.layout = &qi_lb60_ecclayout_1gb;
+               *partitions = qi_lb60_partitions_1gb;
+               *num_partitions = ARRAY_SIZE(qi_lb60_partitions_1gb);
+       }
+}
+
+static struct jz_nand_platform_data qi_lb60_nand_pdata = {
+       .ident_callback = qi_lb60_nand_ident,
+       .busy_gpio = 94,
+};
+
+
+/* Keyboard*/
+
+/* #define KEEP_UART_ALIVE
+ * don't define this. the keyboard and keyboard both work
+ */
+
+#define KEY_QI_QI      KEY_F13
+#define KEY_QI_UPRED   KEY_RIGHTALT
+#define KEY_QI_VOLUP   KEY_VOLUMEUP
+#define KEY_QI_VOLDOWN KEY_VOLUMEDOWN
+#define KEY_QI_FN      KEY_LEFTCTRL
+
+static const uint32_t qi_lb60_keymap[] = {
+       KEY(0, 0, KEY_F1),      /* S2 */
+       KEY(0, 1, KEY_F2),      /* S3 */
+       KEY(0, 2, KEY_F3),      /* S4 */
+       KEY(0, 3, KEY_F4),      /* S5 */
+       KEY(0, 4, KEY_F5),      /* S6 */
+       KEY(0, 5, KEY_F6),      /* S7 */
+       KEY(0, 6, KEY_F7),      /* S8 */
+
+       KEY(1, 0, KEY_Q),       /* S10 */
+       KEY(1, 1, KEY_W),       /* S11 */
+       KEY(1, 2, KEY_E),       /* S12 */
+       KEY(1, 3, KEY_R),       /* S13 */
+       KEY(1, 4, KEY_T),       /* S14 */
+       KEY(1, 5, KEY_Y),       /* S15 */
+       KEY(1, 6, KEY_U),       /* S16 */
+       KEY(1, 7, KEY_I),       /* S17 */
+       KEY(2, 0, KEY_A),       /* S18 */
+       KEY(2, 1, KEY_S),       /* S19 */
+       KEY(2, 2, KEY_D),       /* S20 */
+       KEY(2, 3, KEY_F),       /* S21 */
+       KEY(2, 4, KEY_G),       /* S22 */
+       KEY(2, 5, KEY_H),       /* S23 */
+       KEY(2, 6, KEY_J),       /* S24 */
+       KEY(2, 7, KEY_K),       /* S25 */
+       KEY(3, 0, KEY_ESC),     /* S26 */
+       KEY(3, 1, KEY_Z),       /* S27 */
+       KEY(3, 2, KEY_X),       /* S28 */
+       KEY(3, 3, KEY_C),       /* S29 */
+       KEY(3, 4, KEY_V),       /* S30 */
+       KEY(3, 5, KEY_B),       /* S31 */
+       KEY(3, 6, KEY_N),       /* S32 */
+       KEY(3, 7, KEY_M),       /* S33 */
+       KEY(4, 0, KEY_TAB),     /* S34 */
+       KEY(4, 1, KEY_CAPSLOCK),        /* S35 */
+       KEY(4, 2, KEY_BACKSLASH),       /* S36 */
+       KEY(4, 3, KEY_APOSTROPHE),      /* S37 */
+       KEY(4, 4, KEY_COMMA),   /* S38 */
+       KEY(4, 5, KEY_DOT),     /* S39 */
+       KEY(4, 6, KEY_SLASH),   /* S40 */
+       KEY(4, 7, KEY_UP),      /* S41 */
+       KEY(5, 0, KEY_O),       /* S42 */
+       KEY(5, 1, KEY_L),       /* S43 */
+       KEY(5, 2, KEY_EQUAL),   /* S44 */
+       KEY(5, 3, KEY_QI_UPRED),        /* S45 */
+       KEY(5, 4, KEY_SPACE),   /* S46 */
+       KEY(5, 5, KEY_QI_QI),   /* S47 */
+       KEY(5, 6, KEY_RIGHTCTRL),       /* S48 */
+       KEY(5, 7, KEY_LEFT),    /* S49 */
+       KEY(6, 0, KEY_F8),      /* S50 */
+       KEY(6, 1, KEY_P),       /* S51 */
+       KEY(6, 2, KEY_BACKSPACE),/* S52 */
+       KEY(6, 3, KEY_ENTER),   /* S53 */
+       KEY(6, 4, KEY_QI_VOLUP),        /* S54 */
+       KEY(6, 5, KEY_QI_VOLDOWN),      /* S55 */
+       KEY(6, 6, KEY_DOWN),    /* S56 */
+       KEY(6, 7, KEY_RIGHT),   /* S57 */
+
+#ifndef KEEP_UART_ALIVE
+       KEY(7, 0, KEY_LEFTSHIFT),       /* S58 */
+       KEY(7, 1, KEY_LEFTALT), /* S59 */
+       KEY(7, 2, KEY_QI_FN),   /* S60 */
+#endif
+};
+
+static const struct matrix_keymap_data qi_lb60_keymap_data = {
+       .keymap         = qi_lb60_keymap,
+       .keymap_size    = ARRAY_SIZE(qi_lb60_keymap),
+};
+
+static const unsigned int qi_lb60_keypad_cols[] = {
+       74, 75, 76, 77, 78, 79, 80, 81,
+};
+
+static const unsigned int qi_lb60_keypad_rows[] = {
+       114, 115, 116, 117, 118, 119, 120,
+#ifndef KEEP_UART_ALIVE
+       122,
+#endif
+};
+
+static struct matrix_keypad_platform_data qi_lb60_pdata = {
+       .keymap_data = &qi_lb60_keymap_data,
+       .col_gpios      = qi_lb60_keypad_cols,
+       .row_gpios      = qi_lb60_keypad_rows,
+       .num_col_gpios  = ARRAY_SIZE(qi_lb60_keypad_cols),
+       .num_row_gpios  = ARRAY_SIZE(qi_lb60_keypad_rows),
+       .col_scan_delay_us      = 10,
+       .debounce_ms            = 10,
+       .wakeup                 = 1,
+       .active_low             = 1,
+};
+
+static struct platform_device qi_lb60_keypad = {
+       .name           = "matrix-keypad",
+       .id             = -1,
+       .dev            = {
+               .platform_data = &qi_lb60_pdata,
+       },
+};
+
+/* Display */
+static struct fb_videomode qi_lb60_video_modes[] = {
+       {
+               .name = "320x240",
+               .xres = 320,
+               .yres = 240,
+               .pixclock = 700000,
+               .left_margin = 140,
+               .right_margin = 273,
+               .upper_margin = 20,
+               .lower_margin = 2,
+               .hsync_len = 1,
+               .vsync_len = 1,
+               .sync = 0,
+               .vmode = FB_VMODE_NONINTERLACED,
+       },
+};
+
+static struct jz4740_fb_platform_data qi_lb60_fb_pdata = {
+       .width          = 60,
+       .height         = 45,
+       .num_modes      = ARRAY_SIZE(qi_lb60_video_modes),
+       .modes          = qi_lb60_video_modes,
+       .bpp            = 24,
+       .lcd_type       = JZ_LCD_TYPE_8BIT_SERIAL,
+};
+
+
+struct spi_gpio_platform_data spigpio_platform_data = {
+       .sck = JZ_GPIO_PORTC(23),
+       .mosi = JZ_GPIO_PORTC(22),
+       .miso = JZ_GPIO_PORTC(22),
+       .num_chipselect = 1,
+};
+
+static struct platform_device spigpio_device = {
+       .name = "spi_gpio",
+       .id   = 1,
+       .dev = {
+               .platform_data = &spigpio_platform_data,
+       },
+};
+
+static struct spi_board_info qi_lb60_spi_board_info[] = {
+       {
+               .modalias = "gpm940b0",
+               .controller_data = (void*)JZ_GPIO_PORTC(21),
+               .chip_select = 0,
+               .bus_num = 1,
+               .max_speed_hz = 30 * 1000,
+       },
+};
+
+/* Battery */
+static struct jz_batt_info qi_lb60_battery_pdata = {
+       .dc_dect_gpio   = GPIO_DC_DETE_N,
+       .usb_dect_gpio  = GPIO_USB_DETE,
+       .charg_stat_gpio  = GPIO_CHARG_STAT_N,
+
+       .min_voltag     = 3600000,
+       .max_voltag     = 4200000,
+       .batt_tech      = POWER_SUPPLY_TECHNOLOGY_LIPO,
+};
+
+/* GPIO Key: power */
+static struct gpio_keys_button qi_lb60_gpio_keys_buttons[] = {
+       [0] = {
+               .code           = KEY_POWER,
+               .gpio           = GPIO_WAKEUP_N,
+               .active_low     = 1,
+               .desc           = "Power",
+               .wakeup         = 1,
+       },
+};
+
+static struct gpio_keys_platform_data qi_lb60_gpio_keys_data = {
+       .nbuttons = ARRAY_SIZE(qi_lb60_gpio_keys_buttons),
+       .buttons = qi_lb60_gpio_keys_buttons,
+};
+
+static struct platform_device qi_lb60_gpio_keys = {
+       .name = "gpio-keys",
+       .id =   -1,
+       .dev = {
+               .platform_data = &qi_lb60_gpio_keys_data,
+       }
+};
+
+static struct jz4740_mmc_platform_data qi_lb60_mmc_pdata = {
+       .gpio_card_detect       = JZ_GPIO_PORTD(0),
+       .gpio_read_only         = -1,
+       .gpio_power             = JZ_GPIO_PORTD(2),
+       .power_active_low       = 1,
+};
+
+static struct platform_device *jz_platform_devices[] __initdata = {
+       &jz4740_usb_ohci_device,
+       &jz4740_usb_gdt_device,
+       &jz4740_mmc_device,
+       &jz4740_nand_device,
+       &qi_lb60_keypad,
+       &spigpio_device,
+       &jz4740_framebuffer_device,
+       &jz4740_i2s_device,
+       &jz4740_codec_device,
+       &jz4740_rtc_device,
+       &jz4740_adc_device,
+       &jz4740_battery_device,
+       &qi_lb60_gpio_keys,
+};
+
+static void __init board_gpio_setup(void)
+{
+       /* We only need to enable/disable pullup here for pins used in generic
+        * drivers. Everything else is done by the drivers themselfs. */
+       jz_gpio_disable_pullup(GPIO_SD_VCC_EN_N);
+       jz_gpio_disable_pullup(GPIO_SD_CD_N);
+}
+
+static int __init qi_lb60_init_platform_devices(void)
+{
+       jz4740_framebuffer_device.dev.platform_data = &qi_lb60_fb_pdata;
+       jz4740_nand_device.dev.platform_data = &qi_lb60_nand_pdata;
+       jz4740_battery_device.dev.platform_data = &qi_lb60_battery_pdata;
+       jz4740_mmc_device.dev.platform_data = &qi_lb60_mmc_pdata;
+
+       spi_register_board_info(qi_lb60_spi_board_info,
+                               ARRAY_SIZE(qi_lb60_spi_board_info));
+
+       return platform_add_devices(jz_platform_devices,
+                                       ARRAY_SIZE(jz_platform_devices));
+
+}
+extern int jz_gpiolib_init(void);
+extern int jz_init_clocks(unsigned long extal);
+
+static __init int board_avt2(char *str)
+{
+       qi_lb60_mmc_pdata.card_detect_active_low = 1;
+
+       return 1;
+}
+
+__setup("avt2", board_avt2);
+
+static int __init qi_lb60_board_setup(void)
+{
+       printk("Qi Hardware JZ4740 QI_LB60 setup\n");
+       if (jz_gpiolib_init())
+               panic("Failed to initalize jz gpio\n");
+       jz_init_clocks(12000000);
+
+       board_gpio_setup();
+
+       if (qi_lb60_init_platform_devices())
+               panic("Failed to initalize platform devices\n");
+
+       return 0;
+}
+
+arch_initcall(qi_lb60_board_setup);
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/clock.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/clock.c
new file mode 100644 (file)
index 0000000..853c6d8
--- /dev/null
@@ -0,0 +1,795 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *     JZ4740 SoC TCU support
+ *
+ *  This program is free software; you can redistribute         it and/or modify it
+ *  under  the terms of         the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/err.h>
+
+#define JZ_REG_CLOCK_CTRL      0x00
+#define JZ_REG_CLOCK_PLL       0x10
+#define JZ_REG_CLOCK_GATE      0x20
+#define JZ_REG_CLOCK_I2S       0x60
+#define JZ_REG_CLOCK_LCD       0x64
+#define JZ_REG_CLOCK_MMC       0x68
+#define JZ_REG_CLOCK_UHC       0x6C
+#define JZ_REG_CLOCK_SPI       0x74
+
+#define JZ_CLOCK_CTRL_I2S_SRC_PLL      BIT(31)
+#define JZ_CLOCK_CTRL_KO_ENABLE                BIT(30)
+#define JZ_CLOCK_CTRL_UDC_SRC_PLL      BIT(29)
+#define JZ_CLOCK_CTRL_UDIV_MASK                0x1f800000
+#define JZ_CLOCK_CTRL_CHANGE_ENABLE    BIT(22)
+#define JZ_CLOCK_CTRL_PLL_HALF         BIT(21)
+#define JZ_CLOCK_CTRL_LDIV_MASK                0x001f0000
+#define JZ_CLOCK_CTRL_UDIV_OFFSET      23
+#define JZ_CLOCK_CTRL_LDIV_OFFSET      16
+#define JZ_CLOCK_CTRL_MDIV_OFFSET      12
+#define JZ_CLOCK_CTRL_PDIV_OFFSET       8
+#define JZ_CLOCK_CTRL_HDIV_OFFSET       4
+#define JZ_CLOCK_CTRL_CDIV_OFFSET       0
+
+#define JZ_CLOCK_GATE_UART0    BIT(0)
+#define JZ_CLOCK_GATE_TCU      BIT(1)
+#define JZ_CLOCK_GATE_RTC      BIT(2)
+#define JZ_CLOCK_GATE_I2C      BIT(3)
+#define JZ_CLOCK_GATE_SPI      BIT(4)
+#define JZ_CLOCK_GATE_AIC_PCLK BIT(5)
+#define JZ_CLOCK_GATE_AIC      BIT(6)
+#define JZ_CLOCK_GATE_MMC      BIT(7)
+#define JZ_CLOCK_GATE_ADC      BIT(8)
+#define JZ_CLOCK_GATE_CIM      BIT(9)
+#define JZ_CLOCK_GATE_LCD      BIT(10)
+#define JZ_CLOCK_GATE_UDC      BIT(11)
+#define JZ_CLOCK_GATE_DMAC     BIT(12)
+#define JZ_CLOCK_GATE_IPU      BIT(13)
+#define JZ_CLOCK_GATE_UHC      BIT(14)
+#define JZ_CLOCK_GATE_UART1    BIT(15)
+
+#define JZ_CLOCK_I2S_DIV_MASK          0x01ff
+
+#define JZ_CLOCK_LCD_DIV_MASK          0x01ff
+
+#define JZ_CLOCK_MMC_DIV_MASK          0x001f
+
+#define JZ_CLOCK_UHC_DIV_MASK          0x000f
+
+#define JZ_CLOCK_SPI_SRC_PLL           BIT(31)
+#define JZ_CLOCK_SPI_DIV_MASK          0x000f
+
+#define JZ_CLOCK_PLL_M_MASK            0x01ff
+#define JZ_CLOCK_PLL_N_MASK            0x001f
+#define JZ_CLOCK_PLL_OD_MASK           0x0003
+#define JZ_CLOCK_PLL_STABLE            BIT(10)
+#define JZ_CLOCK_PLL_BYPASS            BIT(9)
+#define JZ_CLOCK_PLL_ENABLED           BIT(8)
+#define JZ_CLOCK_PLL_STABLIZE_MASK     0x000f
+#define JZ_CLOCK_PLL_M_OFFSET          23
+#define JZ_CLOCK_PLL_N_OFFSET          18
+#define JZ_CLOCK_PLL_OD_OFFSET         16
+
+static void __iomem *jz_clock_base;
+static spinlock_t jz_clock_lock;
+static LIST_HEAD(jz_clocks);
+
+struct clk {
+       const char *name;
+       struct clk* parent;
+
+       uint32_t gate_bit;
+
+       unsigned long (*get_rate)(struct clk* clk);
+       unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
+       int (*set_rate)(struct clk* clk, unsigned long rate);
+       int (*enable)(struct clk* clk);
+       int (*disable)(struct clk* clk);
+
+       int (*set_parent)(struct clk* clk, struct clk *parent);
+       struct list_head list;
+};
+
+struct main_clk {
+       struct clk clk;
+       uint32_t div_offset;
+};
+
+struct divided_clk {
+       struct clk clk;
+       uint32_t reg;
+       uint32_t mask;
+};
+
+struct static_clk {
+       struct clk clk;
+       unsigned long rate;
+};
+
+static uint32_t jz_clk_reg_read(int reg)
+{
+       return readl(jz_clock_base + reg);
+}
+
+static void jz_clk_reg_write_mask(int reg, uint32_t val, uint32_t mask)
+{
+       uint32_t val2;
+
+       spin_lock(&jz_clock_lock);
+       val2 = readl(jz_clock_base + reg);
+       val2 &= ~mask;
+       val2 |= val;
+       writel(val2, jz_clock_base + reg);
+       spin_unlock(&jz_clock_lock);
+}
+
+static void jz_clk_reg_set_bits(int reg, uint32_t mask)
+{
+       uint32_t val;
+
+       spin_lock(&jz_clock_lock);
+       val = readl(jz_clock_base + reg);
+       val |= mask;
+       writel(val, jz_clock_base + reg);
+       spin_unlock(&jz_clock_lock);
+}
+
+static void jz_clk_reg_clear_bits(int reg, uint32_t mask)
+{
+       uint32_t val;
+
+       spin_lock(&jz_clock_lock);
+       val = readl(jz_clock_base + reg);
+       val &= ~mask;
+       writel(val, jz_clock_base + reg);
+       spin_unlock(&jz_clock_lock);
+}
+
+static int jz_clk_enable_gating(struct clk *clk)
+{
+       jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, clk->gate_bit);
+       return 0;
+}
+
+static int jz_clk_disable_gating(struct clk *clk)
+{
+       jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, clk->gate_bit);
+       return 0;
+}
+
+static unsigned long jz_clk_static_get_rate(struct clk *clk)
+{
+       return ((struct static_clk*)clk)->rate;
+}
+
+static int jz_clk_ko_enable(struct clk* clk)
+{
+       jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_KO_ENABLE);
+       return 0;
+}
+
+static int jz_clk_ko_disable(struct clk* clk)
+{
+       jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_KO_ENABLE);
+       return 0;
+}
+
+
+static const int pllno[] = {1, 2, 2, 4};
+
+static unsigned long jz_clk_pll_get_rate(struct clk *clk)
+{
+       uint32_t val;
+       int m;
+       int n;
+       int od;
+
+       val = jz_clk_reg_read(JZ_REG_CLOCK_PLL);
+
+       if (val & JZ_CLOCK_PLL_BYPASS)
+               return clk_get_rate(clk->parent);
+
+       m = ((val >> 23) & 0x1ff) + 2;
+       n = ((val >> 18) & 0x1f) + 2;
+       od = (val >> 16) & 0x3;
+
+       return clk_get_rate(clk->parent) * (m / n) / pllno[od];
+}
+
+static unsigned long jz_clk_pll_half_get_rate(struct clk *clk)
+{
+       uint32_t reg;
+
+       reg = jz_clk_reg_read(JZ_REG_CLOCK_CTRL);
+       if (reg & JZ_CLOCK_CTRL_PLL_HALF)
+               return jz_clk_pll_get_rate(clk->parent);
+       return jz_clk_pll_get_rate(clk->parent) >> 1;
+}
+
+
+
+static const int jz_clk_main_divs[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
+
+static unsigned long jz_clk_main_round_rate(struct clk *clk, unsigned long rate)
+{
+       unsigned long parent_rate = jz_clk_pll_get_rate(clk->parent);
+       int div;
+
+       div = parent_rate / rate;
+       if (div > 32)
+               return parent_rate / 32;
+       else if (div < 1)
+               return parent_rate;
+
+       div &= (0x3 << (ffs(div) - 1));
+
+       return parent_rate / div;
+}
+
+static unsigned long jz_clk_main_get_rate(struct clk *clk) {
+       struct main_clk *mclk = (struct main_clk*)clk;
+       uint32_t div;
+
+       div = jz_clk_reg_read(JZ_REG_CLOCK_CTRL);
+
+       div >>= mclk->div_offset;
+       div &= 0xf;
+
+       if (div >= ARRAY_SIZE(jz_clk_main_divs))
+               div = ARRAY_SIZE(jz_clk_main_divs) - 1;
+
+       return jz_clk_pll_get_rate(clk->parent) / jz_clk_main_divs[div];
+}
+
+static int jz_clk_main_set_rate(struct clk *clk, unsigned long rate)
+{
+       struct main_clk *mclk = (struct main_clk*)clk;
+       int i;
+       int div;
+       unsigned long parent_rate = jz_clk_pll_get_rate(clk->parent);
+
+       rate = jz_clk_main_round_rate(clk, rate);
+
+       div = parent_rate / rate;
+
+       i = (ffs(div) - 1) << 1;
+       if (i > 0 && !(div & BIT(i-1)))
+               i -= 1;
+
+       jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, i << mclk->div_offset,
+                               0xf << mclk->div_offset);
+
+       return 0;
+}
+
+
+static struct static_clk jz_clk_ext = {
+       .clk = {
+               .name = "ext",
+               .get_rate = jz_clk_static_get_rate,
+       },
+};
+
+static struct clk jz_clk_pll = {
+       .name = "pll",
+       .parent = &jz_clk_ext.clk,
+       .get_rate = jz_clk_pll_get_rate,
+};
+
+static struct clk jz_clk_pll_half = {
+       .name = "pll half",
+       .parent = &jz_clk_pll,
+       .get_rate = jz_clk_pll_half_get_rate,
+};
+
+static struct main_clk jz_clk_cpu = {
+       .clk = {
+               .name = "cclk",
+               .parent = &jz_clk_pll,
+               .get_rate = jz_clk_main_get_rate,
+               .set_rate = jz_clk_main_set_rate,
+               .round_rate = jz_clk_main_round_rate,
+       },
+       .div_offset = JZ_CLOCK_CTRL_CDIV_OFFSET,
+};
+
+static struct main_clk jz_clk_memory = {
+       .clk = {
+               .name = "mclk",
+               .parent = &jz_clk_pll,
+               .get_rate = jz_clk_main_get_rate,
+               .set_rate = jz_clk_main_set_rate,
+               .round_rate = jz_clk_main_round_rate,
+       },
+       .div_offset = JZ_CLOCK_CTRL_MDIV_OFFSET,
+};
+
+static struct main_clk jz_clk_high_speed_peripheral = {
+       .clk = {
+               .name = "hclk",
+               .parent = &jz_clk_pll,
+               .get_rate = jz_clk_main_get_rate,
+               .set_rate = jz_clk_main_set_rate,
+               .round_rate = jz_clk_main_round_rate,
+       },
+       .div_offset = JZ_CLOCK_CTRL_HDIV_OFFSET,
+};
+
+
+static struct main_clk jz_clk_low_speed_peripheral = {
+       .clk = {
+               .name = "pclk",
+               .parent = &jz_clk_pll,
+               .get_rate = jz_clk_main_get_rate,
+               .set_rate = jz_clk_main_set_rate,
+       },
+       .div_offset = JZ_CLOCK_CTRL_PDIV_OFFSET,
+};
+
+static struct clk jz_clk_ko = {
+       .name = "cko",
+       .parent = &jz_clk_memory.clk,
+       .enable = jz_clk_ko_enable,
+       .disable = jz_clk_ko_disable,
+};
+
+static int jz_clk_spi_set_parent(struct clk *clk, struct clk *parent)
+{
+       if (parent == &jz_clk_pll)
+               jz_clk_reg_set_bits(JZ_CLOCK_SPI_SRC_PLL, JZ_REG_CLOCK_SPI);
+       else if(parent == &jz_clk_ext.clk)
+               jz_clk_reg_clear_bits(JZ_CLOCK_SPI_SRC_PLL, JZ_REG_CLOCK_SPI);
+       else
+               return -EINVAL;
+
+       clk->parent = parent;
+
+       return 0;
+}
+
+static int jz_clk_i2s_set_parent(struct clk *clk, struct clk *parent)
+{
+       if (parent == &jz_clk_pll_half)
+               jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_I2S_SRC_PLL);
+       else if(parent == &jz_clk_ext.clk)
+               jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_I2S_SRC_PLL);
+       else
+               return -EINVAL;
+
+       clk->parent = parent;
+
+       return 0;
+}
+
+static int jz_clk_udc_set_parent(struct clk *clk, struct clk *parent)
+{
+       if (parent == &jz_clk_pll_half)
+               jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_UDC_SRC_PLL);
+       else if(parent == &jz_clk_ext.clk)
+               jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_UDC_SRC_PLL);
+       else
+               return -EINVAL;
+
+       clk->parent = parent;
+
+       return 0;
+}
+
+static int jz_clk_udc_set_rate(struct clk *clk, unsigned long rate)
+{
+       int div;
+
+       if (clk->parent == &jz_clk_ext.clk)
+               return -EINVAL;
+
+       div = clk_get_rate(clk->parent) / rate - 1;
+
+       if (div < 0)
+               div = 0;
+       else if (div > 63)
+               div = 63;
+
+       jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, div << JZ_CLOCK_CTRL_UDIV_OFFSET,
+                               JZ_CLOCK_CTRL_UDIV_MASK);
+       return 0;
+}
+
+static unsigned long jz_clk_udc_get_rate(struct clk *clk)
+{
+       int div;
+
+       if (clk->parent == &jz_clk_ext.clk)
+               return clk_get_rate(clk->parent);
+
+       div = (jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_UDIV_MASK);
+       div >>= JZ_CLOCK_CTRL_UDIV_OFFSET;
+       div += 1;
+
+       return clk_get_rate(clk->parent) / div;
+}
+
+static unsigned long jz_clk_divided_get_rate(struct clk *clk)
+{
+       struct divided_clk *dclk = (struct divided_clk*)clk;
+       int div;
+
+       if (clk->parent == &jz_clk_ext.clk)
+               return clk_get_rate(clk->parent);
+
+       div = (jz_clk_reg_read(dclk->reg) & dclk->mask) + 1;
+
+       return clk_get_rate(clk->parent) / div;
+}
+
+static int jz_clk_divided_set_rate(struct clk *clk, unsigned long rate)
+{
+       struct divided_clk *dclk = (struct divided_clk*)clk;
+       int div;
+
+       if (clk->parent == &jz_clk_ext.clk)
+               return -EINVAL;
+
+       div = clk_get_rate(clk->parent) / rate - 1;
+
+       if (div < 0)
+               div = 0;
+       else if(div > dclk->mask)
+               div = dclk->mask;
+
+       jz_clk_reg_write_mask(dclk->reg, div, dclk->mask);
+
+       return 0;
+}
+
+static unsigned long jz_clk_ldclk_round_rate(struct clk *clk, unsigned long rate)
+{
+       int div;
+       unsigned long parent_rate = jz_clk_pll_half_get_rate(clk->parent);
+
+       if (rate > 150000000)
+               return 150000000;
+
+       div = parent_rate / rate;
+       if (div < 1)
+               div = 1;
+       else if(div > 32)
+               div = 32;
+
+       return parent_rate / div;
+}
+
+static int jz_clk_ldclk_set_rate(struct clk *clk, unsigned long rate)
+{
+       int div;
+
+       if (rate > 150000000)
+               return -EINVAL;
+
+       div = jz_clk_pll_half_get_rate(clk->parent) / rate - 1;
+       if (div < 0)
+               div = 0;
+       else if(div > 31)
+               div = 31;
+
+       jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, div << JZ_CLOCK_CTRL_LDIV_OFFSET,
+                               JZ_CLOCK_CTRL_LDIV_MASK);
+
+       return 0;
+}
+
+static unsigned long jz_clk_ldclk_get_rate(struct clk *clk)
+{
+       int div;
+
+       div = jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_LDIV_MASK;
+       div >>= JZ_CLOCK_CTRL_LDIV_OFFSET;
+
+       return jz_clk_pll_half_get_rate(clk->parent) / (div + 1);
+}
+
+static struct clk jz_clk_ld = {
+       .name = "lcd",
+       .parent = &jz_clk_pll_half,
+       .set_rate = jz_clk_ldclk_set_rate,
+       .get_rate = jz_clk_ldclk_get_rate,
+       .round_rate = jz_clk_ldclk_round_rate,
+};
+
+static struct divided_clk jz_clk_lp = {
+       .clk = {
+               .name = "lcd_pclk",
+               .parent = &jz_clk_pll_half,
+       },
+       .reg = JZ_REG_CLOCK_LCD,
+       .mask = JZ_CLOCK_LCD_DIV_MASK,
+};
+
+static struct clk jz_clk_cim_mclk = {
+       .name = "cim_mclk",
+       .parent = &jz_clk_high_speed_peripheral.clk,
+};
+
+static struct static_clk jz_clk_cim_pclk = {
+       .clk = {
+               .name = "cim_pclk",
+               .gate_bit = JZ_CLOCK_GATE_CIM,
+               .get_rate = jz_clk_static_get_rate,
+               .enable = jz_clk_enable_gating,
+               .disable = jz_clk_disable_gating,
+       },
+};
+
+static struct divided_clk jz_clk_i2s = {
+       .clk = {
+               .name = "i2s",
+               .parent = &jz_clk_ext.clk,
+               .gate_bit = JZ_CLOCK_GATE_AIC,
+               .set_rate = jz_clk_divided_set_rate,
+               .get_rate = jz_clk_divided_get_rate,
+               .enable = jz_clk_enable_gating,
+               .disable = jz_clk_disable_gating,
+               .set_parent = jz_clk_i2s_set_parent,
+       },
+       .reg = JZ_REG_CLOCK_I2S,
+       .mask = JZ_CLOCK_I2S_DIV_MASK,
+};
+
+static struct  divided_clk jz_clk_mmc = {
+       .clk = {
+               .name = "mmc",
+               .parent = &jz_clk_pll_half,
+               .gate_bit = JZ_CLOCK_GATE_MMC,
+               .set_rate = jz_clk_divided_set_rate,
+               .get_rate = jz_clk_divided_get_rate,
+               .enable = jz_clk_enable_gating,
+               .disable = jz_clk_disable_gating,
+       },
+       .reg = JZ_REG_CLOCK_MMC,
+       .mask = JZ_CLOCK_MMC_DIV_MASK,
+};
+
+static struct divided_clk jz_clk_uhc = {
+       .clk = {
+               .name = "uhc",
+               .parent = &jz_clk_pll_half,
+               .gate_bit = JZ_CLOCK_GATE_UHC,
+               .set_rate = jz_clk_divided_set_rate,
+               .get_rate = jz_clk_divided_get_rate,
+               .enable = jz_clk_enable_gating,
+               .disable = jz_clk_disable_gating,
+       },
+       .reg = JZ_REG_CLOCK_UHC,
+       .mask = JZ_CLOCK_UHC_DIV_MASK,
+};
+
+static struct clk jz_clk_udc = {
+       .name = "udc",
+       .parent = &jz_clk_ext.clk,
+       .set_parent = jz_clk_udc_set_parent,
+       .set_rate = jz_clk_udc_set_rate,
+       .get_rate = jz_clk_udc_get_rate,
+};
+
+static struct divided_clk jz_clk_spi = {
+       .clk = {
+               .name = "spi",
+               .parent = &jz_clk_ext.clk,
+               .gate_bit = JZ_CLOCK_GATE_SPI,
+               .set_rate = jz_clk_divided_set_rate,
+               .get_rate = jz_clk_divided_get_rate,
+               .enable = jz_clk_enable_gating,
+               .disable = jz_clk_disable_gating,
+               .set_parent = jz_clk_spi_set_parent,
+       },
+       .reg = JZ_REG_CLOCK_SPI,
+       .mask = JZ_CLOCK_SPI_DIV_MASK,
+};
+
+static struct clk jz_clk_uart0 = {
+       .name = "uart0",
+       .parent = &jz_clk_ext.clk,
+       .gate_bit = JZ_CLOCK_GATE_UART0,
+       .enable = jz_clk_enable_gating,
+       .disable = jz_clk_disable_gating,
+};
+
+static struct clk jz_clk_uart1 = {
+       .name = "uart1",
+       .parent = &jz_clk_ext.clk,
+       .gate_bit = JZ_CLOCK_GATE_UART1,
+       .enable = jz_clk_enable_gating,
+       .disable = jz_clk_disable_gating,
+};
+
+static struct clk jz_clk_dma = {
+       .name = "dma",
+       .parent = &jz_clk_high_speed_peripheral.clk,
+       .gate_bit = JZ_CLOCK_GATE_UART0,
+       .enable = jz_clk_enable_gating,
+       .disable = jz_clk_disable_gating,
+};
+
+static struct clk jz_clk_ipu = {
+       .name = "ipu",
+       .parent = &jz_clk_high_speed_peripheral.clk,
+       .gate_bit = JZ_CLOCK_GATE_IPU,
+       .enable = jz_clk_enable_gating,
+       .disable = jz_clk_disable_gating,
+};
+
+static struct clk jz_clk_adc = {
+       .name = "adc",
+       .parent = &jz_clk_ext.clk,
+       .gate_bit = JZ_CLOCK_GATE_ADC,
+       .enable = jz_clk_enable_gating,
+       .disable = jz_clk_disable_gating,
+};
+
+static struct clk jz_clk_i2c = {
+       .name = "i2c",
+       .parent = &jz_clk_ext.clk,
+       .gate_bit = JZ_CLOCK_GATE_I2C,
+       .enable = jz_clk_enable_gating,
+       .disable = jz_clk_disable_gating,
+};
+
+static struct static_clk jz_clk_rtc = {
+       .clk = {
+               .name = "rtc",
+               .gate_bit = JZ_CLOCK_GATE_RTC,
+               .enable = jz_clk_enable_gating,
+               .disable = jz_clk_disable_gating,
+       },
+       .rate = 32768,
+};
+
+int clk_enable(struct clk *clk)
+{
+       if (!clk->enable)
+               return -EINVAL;
+
+       return clk->enable(clk);
+}
+EXPORT_SYMBOL_GPL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+       if (clk->disable)
+               clk->disable(clk);
+}
+EXPORT_SYMBOL_GPL(clk_disable);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+       if (clk->get_rate)
+               return clk->get_rate(clk);
+       if (clk->parent)
+               return clk_get_rate(clk->parent);
+
+       return -EINVAL;
+}
+EXPORT_SYMBOL_GPL(clk_get_rate);
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+       if (!clk->set_rate)
+               return -EINVAL;
+       return clk->set_rate(clk, rate);
+}
+EXPORT_SYMBOL_GPL(clk_set_rate);
+
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+       if (clk->round_rate)
+               return clk->round_rate(clk, rate);
+
+       return -EINVAL;
+}
+EXPORT_SYMBOL_GPL(clk_round_rate);
+
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+       int ret;
+
+       if (!clk->set_parent)
+               return -EINVAL;
+
+       clk->disable(clk);
+       ret = clk->set_parent(clk, parent);
+       clk->enable(clk);
+
+       return ret;
+}
+EXPORT_SYMBOL_GPL(clk_set_parent);
+
+
+struct clk *clk_get(struct device *dev, const char *name)
+{
+       struct clk *clk;
+
+       list_for_each_entry(clk, &jz_clocks, list) {
+           if (strcmp(clk->name, name) == 0)
+                       return clk;
+       }
+       return ERR_PTR(-ENOENT);
+}
+EXPORT_SYMBOL_GPL(clk_get);
+
+void clk_put(struct clk *clk)
+{
+}
+EXPORT_SYMBOL_GPL(clk_put);
+
+inline static void clk_add(struct clk *clk)
+{
+    list_add_tail(&clk->list, &jz_clocks);
+}
+
+static void clk_register_clks(void)
+{
+    clk_add(&jz_clk_ext.clk);
+    clk_add(&jz_clk_pll);
+    clk_add(&jz_clk_pll_half);
+    clk_add(&jz_clk_cpu.clk);
+    clk_add(&jz_clk_high_speed_peripheral.clk);
+    clk_add(&jz_clk_low_speed_peripheral.clk);
+    clk_add(&jz_clk_ko);
+    clk_add(&jz_clk_ld);
+    clk_add(&jz_clk_lp.clk);
+    clk_add(&jz_clk_cim_mclk);
+    clk_add(&jz_clk_cim_pclk.clk);
+    clk_add(&jz_clk_i2s.clk);
+    clk_add(&jz_clk_mmc.clk);
+    clk_add(&jz_clk_uhc.clk);
+    clk_add(&jz_clk_udc);
+    clk_add(&jz_clk_uart0);
+    clk_add(&jz_clk_uart1);
+    clk_add(&jz_clk_dma);
+    clk_add(&jz_clk_ipu);
+    clk_add(&jz_clk_adc);
+    clk_add(&jz_clk_i2c);
+    clk_add(&jz_clk_rtc.clk);
+}
+
+int jz_init_clocks(unsigned long ext_rate)
+{
+       uint32_t val;
+
+       jz_clock_base = ioremap(0x10000000, 0x100);
+       if (!jz_clock_base)
+               return -EBUSY;
+
+       jz_clk_ext.rate = ext_rate;
+
+       val = jz_clk_reg_read(JZ_REG_CLOCK_SPI);
+
+       if (val & JZ_CLOCK_SPI_SRC_PLL)
+               jz_clk_spi.clk.parent = &jz_clk_pll_half;
+
+       val = jz_clk_reg_read(JZ_REG_CLOCK_CTRL);
+
+       if (val & JZ_CLOCK_CTRL_I2S_SRC_PLL)
+               jz_clk_i2s.clk.parent = &jz_clk_pll_half;
+
+       if (val & JZ_CLOCK_CTRL_UDC_SRC_PLL)
+               jz_clk_udc.parent = &jz_clk_pll_half;
+
+       clk_register_clks();
+
+       return 0;
+}
+EXPORT_SYMBOL_GPL(jz_init_clocks);
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/dma.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/dma.c
new file mode 100644 (file)
index 0000000..e43fb74
--- /dev/null
@@ -0,0 +1,338 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *     JZ4740 SoC DMA support
+ *
+ *  This program is free software; you can redistribute         it and/or modify it
+ *  under  the terms of         the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+
+#include <linux/dma-mapping.h>
+#include <asm/mach-jz4740/dma.h>
+#include <asm/mach-jz4740/regs.h>
+
+#define JZ_REG_DMA_SRC_ADDR(x)         (0x00 + (x) * 0x20)
+#define JZ_REG_DMA_DST_ADDR(x)         (0x04 + (x) * 0x20)
+#define JZ_REG_DMA_TRANSFER_COUNT(x)   (0x08 + (x) * 0x20)
+#define JZ_REG_DMA_REQ_TYPE(x)         (0x0C + (x) * 0x20)
+#define JZ_REG_DMA_STATUS_CTRL(x)      (0x10 + (x) * 0x20)
+#define JZ_REG_DMA_CMD(x)              (0x14 + (x) * 0x20)
+#define JZ_REG_DMA_DESC_ADDR(x)                (0x18 + (x) * 0x20)
+
+#define JZ_REG_DMA_CTRL                        0x300
+#define JZ_REG_DMA_IRQ                 0x304
+#define JZ_REG_DMA_DOORBELL            0x308
+#define JZ_REG_DMA_DOORBELL_SET                0x30C
+
+#define JZ_DMA_STATUS_CTRL_NO_DESC             BIT(31)
+#define JZ_DMA_STATUS_CTRL_DESC_INV            BIT(6)
+#define JZ_DMA_STATUS_CTRL_ADDR_ERR            BIT(4)
+#define JZ_DMA_STATUS_CTRL_TRANSFER_DONE       BIT(3)
+#define JZ_DMA_STATUS_CTRL_HALT                        BIT(2)
+#define JZ_DMA_STATUS_CTRL_COUNT_TERMINATE     BIT(1)
+#define JZ_DMA_STATUS_CTRL_ENABLE              BIT(0)
+
+#define JZ_DMA_CMD_SRC_INC                     BIT(23)
+#define JZ_DMA_CMD_DST_INC                     BIT(22)
+#define JZ_DMA_CMD_RDIL_MASK                   (0xf << 16)
+#define JZ_DMA_CMD_SRC_WIDTH_MASK              (0x3 << 14)
+#define JZ_DMA_CMD_DST_WIDTH_MASK              (0x3 << 12)
+#define JZ_DMA_CMD_INTERVAL_LENGTH_MASK                (0x7 << 8)
+#define JZ_DMA_CMD_BLOCK_MODE                  BIT(7)
+#define JZ_DMA_CMD_DESC_VALID                  BIT(4)
+#define JZ_DMA_CMD_DESC_VALID_MODE             BIT(3)
+#define JZ_DMA_CMD_VALID_IRQ_ENABLE            BIT(2)
+#define JZ_DMA_CMD_TRANSFER_IRQ_ENABLE         BIT(1)
+#define JZ_DMA_CMD_LINK_ENABLE                 BIT(0)
+
+#define JZ_DMA_CMD_FLAGS_OFFSET 22
+#define JZ_DMA_CMD_RDIL_OFFSET 16
+#define JZ_DMA_CMD_SRC_WIDTH_OFFSET 14
+#define JZ_DMA_CMD_DST_WIDTH_OFFSET 12
+#define JZ_DMA_CMD_TRANSFER_SIZE_OFFSET 8
+#define JZ_DMA_CMD_MODE_OFFSET 7
+
+#define JZ_DMA_CTRL_PRIORITY_MASK      (0x3 << 8)
+#define JZ_DMA_CTRL_HALT               BIT(3)
+#define JZ_DMA_CTRL_ADDRESS_ERROR      BIT(2)
+#define JZ_DMA_CTRL_ENABLE             BIT(0)
+
+
+static void __iomem *jz4740_dma_base;
+static spinlock_t jz4740_dma_lock;
+
+static inline uint32_t jz4740_dma_read(size_t reg)
+{
+       return readl(jz4740_dma_base + reg);
+}
+
+static inline void jz4740_dma_write(size_t reg, uint32_t val)
+{
+       writel(val, jz4740_dma_base + reg);
+}
+
+static inline void jz4740_dma_write_mask(size_t reg, uint32_t val, uint32_t mask)
+{
+       uint32_t val2;
+       val2 = jz4740_dma_read(reg);
+       val2 &= ~mask;
+       val2 |= val;
+       jz4740_dma_write(reg, val2);
+}
+
+struct jz4740_dma_chan {
+       unsigned int id;
+       void *dev;
+       const char *name;
+
+       enum jz4740_dma_flags flags;
+       uint32_t transfer_shift;
+
+       jz4740_dma_complete_callback_t complete_cb;
+       
+       unsigned used:1;
+};
+
+#define JZ4740_DMA_CHANNEL(_id) { .id = _id }
+
+struct jz4740_dma_chan jz4740_dma_channels[] = {
+       JZ4740_DMA_CHANNEL(0),
+       JZ4740_DMA_CHANNEL(1),
+       JZ4740_DMA_CHANNEL(2),
+       JZ4740_DMA_CHANNEL(3),
+       JZ4740_DMA_CHANNEL(4),
+       JZ4740_DMA_CHANNEL(5),
+};
+
+struct jz4740_dma_chan* jz4740_dma_request(void *dev, const char *name)
+{
+       unsigned int i;
+       struct jz4740_dma_chan *dma = NULL;
+
+       spin_lock(&jz4740_dma_lock);
+
+       for (i = 0; i < ARRAY_SIZE(jz4740_dma_channels); ++i) {
+               if (!jz4740_dma_channels[i].used) {
+                       dma = &jz4740_dma_channels[i];
+                       dma->used = 1;
+                       break;
+               }
+       }
+
+       spin_unlock(&jz4740_dma_lock);
+
+       if (!dma)
+               return NULL;
+
+       dma->dev = dev;
+       dma->name = name;
+
+       return dma;
+}
+
+void jz4740_dma_configure(struct jz4740_dma_chan *dma, 
+                          const struct jz4740_dma_config *config)
+{
+       uint32_t cmd;
+       uint32_t ctrl;
+
+       switch(config->transfer_size) {
+               case JZ4740_DMA_TRANSFER_SIZE_2BYTE:
+                       dma->transfer_shift = 1;
+                       break;
+               case JZ4740_DMA_TRANSFER_SIZE_4BYTE:
+                       dma->transfer_shift = 2;
+                       break;
+               case JZ4740_DMA_TRANSFER_SIZE_16BYTE:
+                       dma->transfer_shift = 4;
+                       break;
+               case JZ4740_DMA_TRANSFER_SIZE_32BYTE:
+                       dma->transfer_shift = 5;
+                       break;
+               default:
+                       dma->transfer_shift = 0;
+                       break;
+       }
+
+       cmd = config->flags << JZ_DMA_CMD_FLAGS_OFFSET;
+       cmd |= config->src_width << JZ_DMA_CMD_SRC_WIDTH_OFFSET;
+       cmd |= config->dst_width << JZ_DMA_CMD_DST_WIDTH_OFFSET;
+       cmd |= config->transfer_size << JZ_DMA_CMD_TRANSFER_SIZE_OFFSET;
+       cmd |= config->mode << JZ_DMA_CMD_MODE_OFFSET;
+       cmd |= JZ_DMA_CMD_TRANSFER_IRQ_ENABLE;
+
+       ctrl = JZ_DMA_STATUS_CTRL_NO_DESC;
+       ctrl |= JZ_DMA_STATUS_CTRL_HALT;
+
+       jz4740_dma_write(JZ_REG_DMA_CMD(dma->id), cmd);
+       jz4740_dma_write(JZ_REG_DMA_STATUS_CTRL(dma->id), ctrl);
+       jz4740_dma_write(JZ_REG_DMA_REQ_TYPE(dma->id), config->request_type);
+}
+EXPORT_SYMBOL_GPL(jz4740_dma_configure);
+
+void jz4740_dma_set_src_addr(struct jz4740_dma_chan *dma, dma_addr_t src)
+{
+       jz4740_dma_write(JZ_REG_DMA_SRC_ADDR(dma->id), src);
+}
+EXPORT_SYMBOL_GPL(jz4740_dma_set_src_addr);
+
+void jz4740_dma_set_dst_addr(struct jz4740_dma_chan *dma, dma_addr_t dst)
+{
+       jz4740_dma_write(JZ_REG_DMA_DST_ADDR(dma->id), dst);
+}
+EXPORT_SYMBOL_GPL(jz4740_dma_set_dst_addr);
+
+void jz4740_dma_set_transfer_count(struct jz4740_dma_chan *dma, uint32_t count)
+{
+       count >>= dma->transfer_shift;
+       jz4740_dma_write(JZ_REG_DMA_TRANSFER_COUNT(dma->id), count);
+}
+EXPORT_SYMBOL_GPL(jz4740_dma_set_transfer_count);
+
+void jz4740_dma_set_complete_cb(struct jz4740_dma_chan *dma,
+                                jz4740_dma_complete_callback_t cb)
+{
+       dma->complete_cb = cb;
+}
+EXPORT_SYMBOL_GPL(jz4740_dma_set_complete_cb);
+
+void jz4740_dma_free(struct jz4740_dma_chan *dma)
+{
+       dma->dev = NULL;
+       dma->complete_cb = NULL;
+       dma->used = 0;
+}
+EXPORT_SYMBOL_GPL(jz4740_dma_free);
+
+void jz4740_dma_enable(struct jz4740_dma_chan *dma)
+{
+       jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id),
+                       JZ_DMA_STATUS_CTRL_ENABLE,
+                       JZ_DMA_STATUS_CTRL_ENABLE | JZ_DMA_STATUS_CTRL_HALT);
+
+       jz4740_dma_write_mask(JZ_REG_DMA_CTRL,
+                       JZ_DMA_CTRL_ENABLE,
+                       JZ_DMA_CTRL_ENABLE | JZ_DMA_CTRL_HALT);
+}
+EXPORT_SYMBOL_GPL(jz4740_dma_enable);
+
+void jz4740_dma_disable(struct jz4740_dma_chan *dma)
+{
+       jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id), 0,
+                       JZ_DMA_STATUS_CTRL_ENABLE);
+}
+EXPORT_SYMBOL_GPL(jz4740_dma_disable);
+
+uint32_t jz4740_dma_get_residue(const struct jz4740_dma_chan *dma)
+{
+       uint32_t residue;
+       residue = jz4740_dma_read(JZ_REG_DMA_TRANSFER_COUNT(dma->id));
+       return residue << dma->transfer_shift;
+}
+EXPORT_SYMBOL_GPL(jz4740_dma_get_residue);
+
+static void jz4740_dma_chan_irq(struct jz4740_dma_chan *dma)
+{
+       uint32_t status;
+
+       status = jz4740_dma_read(JZ_REG_DMA_STATUS_CTRL(dma->id));
+
+       jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id), 0,
+               JZ_DMA_STATUS_CTRL_ENABLE | JZ_DMA_STATUS_CTRL_TRANSFER_DONE);
+
+       if (dma->complete_cb)
+               dma->complete_cb(dma, 0, dma->dev);
+}
+
+static irqreturn_t jz4740_dma_irq(int irq, void *dev_id)
+{
+       uint32_t irq_status;
+       unsigned int i;
+
+       irq_status = readl(jz4740_dma_base + JZ_REG_DMA_IRQ);
+
+       for (i = 0; i < 6; ++i) {
+               if (irq_status & (1 << i))
+                       jz4740_dma_chan_irq(&jz4740_dma_channels[i]);
+       }
+
+       return IRQ_HANDLED;
+}
+
+#if 0
+static struct jz4740_dma_config dma_test_config = {
+       .src_width = JZ4740_DMA_WIDTH_32BIT,
+       .dst_width = JZ4740_DMA_WIDTH_32BIT,
+       .transfer_size = JZ4740_DMA_TRANSFER_SIZE_4BYTE,
+       .request_type = JZ4740_DMA_TYPE_AUTO_REQUEST,
+       .flags = JZ4740_DMA_SRC_AUTOINC | JZ4740_DMA_DST_AUTOINC,
+       .mode = JZ4740_DMA_MODE_BLOCK,
+};
+
+static void jz4740_dma_test(void)
+{
+       uint32_t *buf1, *buf2;
+       dma_addr_t addr1, addr2;
+       struct jz4740_dma_chan *dma = jz4740_dma_request(NULL, "dma test");
+       int i;
+
+       printk("STARTING DMA TEST\n");
+
+       buf1 = dma_alloc_coherent(NULL,
+                                               0x1000,
+                                               &addr1, GFP_KERNEL);
+       buf2 = dma_alloc_coherent(NULL,
+                                               0x1000,
+                                               &addr2, GFP_KERNEL);
+
+       for (i = 0; i < 0x400; ++i)
+               buf1[i] = i;
+
+
+       jz4740_dma_configure(dma, &dma_test_config);
+       jz4740_dma_set_src_addr(dma, addr1);
+       jz4740_dma_set_dst_addr(dma, addr2);
+       jz4740_dma_set_transfer_count(dma, 0x1000);
+
+       jz4740_dma_enable(dma);
+       mdelay(2000);
+
+       for (i = 0; i < 0x400; ++i) {
+               if (buf2[i] != i)
+                       printk("OH MY GOD: %x %x\n", i, buf2[i]);
+       }
+
+       printk("DMA TEST DONE\n");
+}
+#endif
+
+static int jz4740_dma_init(void)
+{
+       unsigned int ret;
+
+       jz4740_dma_base = ioremap(CPHYSADDR(DMAC_BASE), 0x400);
+
+       if (!jz4740_dma_base)
+               return -EBUSY;
+
+       spin_lock_init(&jz4740_dma_lock);
+
+       ret = request_irq(JZ_IRQ_DMAC, jz4740_dma_irq, 0, "DMA", NULL);
+
+       if (ret)
+               printk("JZ4740 DMA: Failed to request irq: %d\n", ret);
+
+       return ret;
+}
+arch_initcall(jz4740_dma_init);
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/gpio.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/gpio.c
new file mode 100644 (file)
index 0000000..30f83fa
--- /dev/null
@@ -0,0 +1,490 @@
+/*
+ *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
+ *     JZ4740 platform GPIO support
+ *
+ *  This program is free software; you can redistribute         it and/or modify it
+ *  under  the terms of         the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include <linux/spinlock.h>
+#include <linux/sysdev.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/bitops.h>
+
+#define JZ_GPIO_BASE_A (32*0)
+#define JZ_GPIO_BASE_B (32*1)
+#define JZ_GPIO_BASE_C (32*2)
+#define JZ_GPIO_BASE_D (32*3)
+
+#define JZ_GPIO_NUM_A 32
+#define JZ_GPIO_NUM_B 32
+#define JZ_GPIO_NUM_C 31
+#define JZ_GPIO_NUM_D 32
+
+#define JZ_IRQ_GPIO_BASE_A (JZ_IRQ_GPIO(0) + JZ_GPIO_BASE_A)
+#define JZ_IRQ_GPIO_BASE_B (JZ_IRQ_GPIO(0) + JZ_GPIO_BASE_B)
+#define JZ_IRQ_GPIO_BASE_C (JZ_IRQ_GPIO(0) + JZ_GPIO_BASE_C)
+#define JZ_IRQ_GPIO_BASE_D (JZ_IRQ_GPIO(0) + JZ_GPIO_BASE_D)
+
+#define JZ_IRQ_GPIO_A(num) (JZ_IRQ_GPIO_BASE_A + num)
+#define JZ_IRQ_GPIO_B(num) (JZ_IRQ_GPIO_BASE_B + num)
+#define JZ_IRQ_GPIO_C(num) (JZ_IRQ_GPIO_BASE_C + num)
+#define JZ_IRQ_GPIO_D(num) (JZ_IRQ_GPIO_BASE_D + num)
+
+#define JZ_REG_GPIO_PIN                        0x00
+#define JZ_REG_GPIO_DATA               0x10
+#define JZ_REG_GPIO_DATA_SET           0x14
+#define JZ_REG_GPIO_DATA_CLEAR         0x18
+#define JZ_REG_GPIO_MASK               0x20
+#define JZ_REG_GPIO_MASK_SET           0x24
+#define JZ_REG_GPIO_MASK_CLEAR         0x28
+#define JZ_REG_GPIO_PULL               0x30
+#define JZ_REG_GPIO_PULL_SET           0x34
+#define JZ_REG_GPIO_PULL_CLEAR         0x38
+#define JZ_REG_GPIO_FUNC               0x40
+#define JZ_REG_GPIO_FUNC_SET           0x44
+#define JZ_REG_GPIO_FUNC_CLEAR         0x48
+#define JZ_REG_GPIO_SELECT             0x50
+#define JZ_REG_GPIO_SELECT_SET         0x54
+#define JZ_REG_GPIO_SELECT_CLEAR       0x58
+#define JZ_REG_GPIO_DIRECTION          0x60
+#define JZ_REG_GPIO_DIRECTION_SET      0x64
+#define JZ_REG_GPIO_DIRECTION_CLEAR    0x68
+#define JZ_REG_GPIO_TRIGGER            0x70
+#define JZ_REG_GPIO_TRIGGER_SET                0x74
+#define JZ_REG_GPIO_TRIGGER_CLEAR      0x78
+#define JZ_REG_GPIO_FLAG               0x80
+#define JZ_REG_GPIO_FLAG_CLEAR         0x14
+
+#define CHIP_TO_REG(chip, reg) (jz_gpio_base + (((chip)->base) << 3) + reg)
+
+#define GPIO_TO_BIT(gpio) BIT(gpio & 0x1f)
+#define GPIO_TO_REG(gpio, reg) (jz_gpio_base + ((gpio >> 5) << 8) + reg)
+
+static void __iomem *jz_gpio_base;
+
+struct jz_gpio_chip {
+       unsigned int irq;
+       unsigned int irq_base;
+       uint32_t wakeup;
+       uint32_t suspend_mask;
+       uint32_t edge_trigger_both;
+       spinlock_t lock;
+       struct gpio_chip gpio_chip;
+       struct irq_chip irq_chip;
+};
+
+static struct jz_gpio_chip *jz_irq_to_chip(unsigned int irq)
+{
+       return get_irq_chip_data(irq);
+}
+
+static inline void jz_gpio_write_bit(unsigned int gpio, unsigned int reg)
+{
+       writel(GPIO_TO_BIT(gpio), GPIO_TO_REG(gpio, reg));
+}
+
+int jz_gpio_set_function(int gpio, enum jz_gpio_function function)
+{
+       if (function == JZ_GPIO_FUNC_NONE) {
+               jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_CLEAR);
+               jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
+               jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
+       } else {
+               jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_SET);
+               switch (function) {
+               case JZ_GPIO_FUNC1:
+                       jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
+                       break;
+               case JZ_GPIO_FUNC3:
+                       jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_SET);
+               case JZ_GPIO_FUNC2: /* Falltrough */
+                       jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_SET);
+                       break;
+               default:
+                       BUG();
+                       break;
+               }
+       }
+
+       return 0;
+}
+EXPORT_SYMBOL_GPL(jz_gpio_set_function);
+
+int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num)
+{
+       size_t i;
+       int ret;
+
+       for (i = 0; i < num; ++i, ++request) {
+               ret = gpio_request(request->gpio, request->name);
+               if (ret)
+                       goto err;
+               jz_gpio_set_function(request->gpio, request->function);
+       }
+
+       return 0;
+err:
+       for (--request; i > 0; --i, --request)
+               gpio_free(request->gpio);
+
+       return ret;
+}
+EXPORT_SYMBOL_GPL(jz_gpio_bulk_request);
+
+void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num)
+{
+       size_t i;
+
+       for (i = 0; i < num; ++i, ++request) {
+               gpio_free(request->gpio);
+               jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
+       }
+
+}
+EXPORT_SYMBOL_GPL(jz_gpio_bulk_free);
+
+void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num)
+{
+       size_t i;
+
+       for (i = 0; i < num; ++i, ++request) {
+               jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
+               jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_DIRECTION_SET);
+       }
+}
+EXPORT_SYMBOL_GPL(jz_gpio_bulk_suspend);
+
+void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num)
+{
+       size_t i;
+
+       for (i = 0; i < num; ++i, ++request) {
+               jz_gpio_set_function(request->gpio, request->function);
+       }
+}
+EXPORT_SYMBOL_GPL(jz_gpio_bulk_resume);
+
+void jz_gpio_enable_pullup(unsigned gpio)
+{
+       jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_CLEAR);
+}
+EXPORT_SYMBOL_GPL(jz_gpio_enable_pullup);
+
+void jz_gpio_disable_pullup(unsigned gpio)
+{
+       jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_SET);
+}
+EXPORT_SYMBOL_GPL(jz_gpio_disable_pullup);
+
+static int jz_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
+{
+       return !!(readl(CHIP_TO_REG(chip, JZ_REG_GPIO_PIN)) & BIT(gpio));
+}
+
+static void jz_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
+{
+       uint32_t __iomem *reg = CHIP_TO_REG(chip, JZ_REG_GPIO_DATA_SET);
+       reg += !value;
+       writel(BIT(gpio), reg);
+}
+
+static int jz_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
+{
+       writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_SET));
+       jz_gpio_set_value(chip, gpio, value);
+
+       return 0;
+}
+
+static int jz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
+{
+       writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_CLEAR));
+
+       return 0;
+}
+
+int jz_gpio_port_direction_input(int port, uint32_t mask)
+{
+       writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_CLEAR));
+
+       return 0;
+}
+EXPORT_SYMBOL(jz_gpio_port_direction_input);
+
+int jz_gpio_port_direction_output(int port, uint32_t mask)
+{
+       writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_SET));
+
+       return 0;
+}
+EXPORT_SYMBOL(jz_gpio_port_direction_output);
+
+void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask)
+{
+       writel((~value) & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_CLEAR));
+       writel(value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_SET));
+}
+EXPORT_SYMBOL(jz_gpio_port_set_value);
+
+uint32_t jz_gpio_port_get_value(int port, uint32_t mask)
+{
+       uint32_t value = readl(GPIO_TO_REG(port, JZ_REG_GPIO_PIN));
+
+       return value & mask;
+}
+EXPORT_SYMBOL(jz_gpio_port_get_value);
+
+
+#define IRQ_TO_GPIO(irq) (irq - JZ_IRQ_GPIO(0))
+#define IRQ_TO_BIT(irq) BIT(IRQ_TO_GPIO(irq) & 0x1f)
+
+#define IRQ_TO_REG(irq, reg)  GPIO_TO_REG(IRQ_TO_GPIO(irq), reg)
+
+static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
+{
+       uint32_t flag;
+       unsigned int gpio_irq;
+       unsigned int gpio_bank;
+       struct jz_gpio_chip *chip = get_irq_desc_data(desc);
+
+       gpio_bank = JZ_IRQ_GPIO0 - irq;
+
+       flag = readl(jz_gpio_base + (gpio_bank << 8) + JZ_REG_GPIO_FLAG);
+
+       gpio_irq = ffs(flag) - 1;
+
+       if (chip->edge_trigger_both & BIT(gpio_irq)) {
+               uint32_t value = readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_PIN));
+               if (value & BIT(gpio_irq)) {
+                       writel(BIT(gpio_irq),
+                               CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_DIRECTION_CLEAR));
+               } else {
+                       writel(BIT(gpio_irq),
+                               CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_DIRECTION_SET));
+               }
+       }
+
+       gpio_irq += (gpio_bank << 5) + JZ_IRQ_GPIO(0);
+
+       generic_handle_irq(gpio_irq);
+};
+
+static inline void jz_gpio_set_irq_bit(unsigned int irq, unsigned int reg)
+{
+       writel(IRQ_TO_BIT(irq), IRQ_TO_REG(irq, reg));
+}
+
+static void jz_gpio_irq_mask(unsigned int irq)
+{
+       jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_SET);
+};
+
+static void jz_gpio_irq_unmask(unsigned int irq)
+{
+       jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_CLEAR);
+};
+
+/* TODO: Check if function is gpio */
+static unsigned int jz_gpio_irq_startup(unsigned int irq)
+{
+       struct irq_desc *desc = irq_to_desc(irq);
+
+       jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_SET);
+
+       jz_gpio_irq_unmask(irq);
+       desc->status &= ~IRQ_MASKED;
+
+       return 0;
+}
+
+static void jz_gpio_irq_shutdown(unsigned int irq)
+{
+       struct irq_desc *desc = irq_to_desc(irq);
+
+       jz_gpio_irq_mask(irq);
+       desc->status |= IRQ_MASKED;
+
+       /* Set direction to input */
+       jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
+       jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_CLEAR);
+}
+
+static void jz_gpio_irq_ack(unsigned int irq)
+{
+       jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_FLAG_CLEAR);
+};
+
+static int jz_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
+{
+       struct jz_gpio_chip *chip = jz_irq_to_chip(irq);
+       struct irq_desc *desc = irq_to_desc(irq);
+
+       jz_gpio_irq_mask(irq);
+
+       if (flow_type == IRQ_TYPE_EDGE_BOTH) {
+               uint32_t value = readl(IRQ_TO_REG(irq, JZ_REG_GPIO_PIN));
+               if (value & IRQ_TO_BIT(irq))
+                       flow_type = IRQ_TYPE_EDGE_FALLING;
+               else
+                       flow_type = IRQ_TYPE_EDGE_RISING;
+               chip->edge_trigger_both |= IRQ_TO_BIT(irq);
+       } else {
+               chip->edge_trigger_both &= ~IRQ_TO_BIT(irq);
+       }
+
+       switch(flow_type) {
+       case IRQ_TYPE_EDGE_RISING:
+               jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET);
+               jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET);
+               break;
+       case IRQ_TYPE_EDGE_FALLING:
+               jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
+               jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET);
+               break;
+       case IRQ_TYPE_LEVEL_HIGH:
+               jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET);
+               jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR);
+               break;
+       case IRQ_TYPE_LEVEL_LOW:
+               jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
+               jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR);
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       if (!(desc->status & IRQ_MASKED))
+               jz_gpio_irq_unmask(irq);
+
+       return 0;
+}
+
+static int jz_gpio_irq_set_wake(unsigned int irq, unsigned int on)
+{
+       struct jz_gpio_chip *chip = jz_irq_to_chip(irq);
+       spin_lock(&chip->lock);
+       if (on)
+               chip->wakeup |= IRQ_TO_BIT(irq);
+       else
+               chip->wakeup &= ~IRQ_TO_BIT(irq);
+       spin_unlock(&chip->lock);
+
+       set_irq_wake(chip->irq, !!(chip->wakeup));
+       return 0;
+}
+
+int gpio_to_irq(unsigned gpio)
+{
+       return JZ_IRQ_GPIO(0) + gpio;
+}
+EXPORT_SYMBOL_GPL(gpio_to_irq);
+
+int irq_to_gpio(unsigned gpio)
+{
+       return IRQ_TO_GPIO(gpio);
+}
+EXPORT_SYMBOL_GPL(irq_to_gpio);
+
+#define JZ_GPIO_CHIP(_bank) { \
+       .irq_base = JZ_IRQ_GPIO_BASE_ ## _bank, \
+       .gpio_chip = { \
+               .label = "Bank " # _bank, \
+               .owner = THIS_MODULE, \
+               .set = jz_gpio_set_value, \
+               .get = jz_gpio_get_value, \
+               .direction_output = jz_gpio_direction_output, \
+               .direction_input = jz_gpio_direction_input, \
+               .base = JZ_GPIO_BASE_ ## _bank, \
+               .ngpio = JZ_GPIO_NUM_ ## _bank, \
+       }, \
+       .irq_chip =  { \
+               .name = "GPIO Bank " # _bank, \
+               .mask = jz_gpio_irq_mask, \
+               .unmask = jz_gpio_irq_unmask, \
+               .ack = jz_gpio_irq_ack, \
+               .startup = jz_gpio_irq_startup, \
+               .shutdown = jz_gpio_irq_shutdown, \
+               .set_type = jz_gpio_irq_set_type, \
+               .set_wake = jz_gpio_irq_set_wake, \
+       }, \
+}
+
+static struct jz_gpio_chip jz_gpio_chips[] = {
+       JZ_GPIO_CHIP(A),
+       JZ_GPIO_CHIP(B),
+       JZ_GPIO_CHIP(C),
+       JZ_GPIO_CHIP(D),
+};
+
+static int jz_gpio_suspend(struct sys_device *dev, pm_message_t state)
+{
+       struct jz_gpio_chip *chip = jz_gpio_chips;
+       int i, gpio;
+       for (i = 0; i < ARRAY_SIZE(jz_gpio_chips); ++i, ++chip) {
+               gpio = chip->gpio_chip.base;
+               chip->suspend_mask = readl(GPIO_TO_REG(gpio, JZ_REG_GPIO_MASK));
+               writel(~(chip->wakeup), GPIO_TO_REG(gpio, JZ_REG_GPIO_MASK_SET));
+       }
+
+       return 0;
+}
+
+static int jz_gpio_resume(struct sys_device *dev)
+{
+       struct jz_gpio_chip *chip = jz_gpio_chips;
+       int i;
+       for (i = 0; i < ARRAY_SIZE(jz_gpio_chips); ++i, ++chip) {
+               writel(~(chip->suspend_mask), GPIO_TO_REG(chip->gpio_chip.base, JZ_REG_GPIO_MASK_CLEAR));
+       }
+
+       return 0;
+}
+
+static struct sysdev_class jz_gpio_sysdev = {
+       .name = "JZ4740 GPIO",
+       .suspend = jz_gpio_suspend,
+       .resume = jz_gpio_resume,
+};
+
+int __init jz_gpiolib_init(void)
+{
+       struct jz_gpio_chip *chip = jz_gpio_chips;
+       int i, irq;
+
+       jz_gpio_base = ioremap(0x10010000, 0x400);
+
+       for (i = 0; i < ARRAY_SIZE(jz_gpio_chips); ++i, ++chip) {
+               gpiochip_add(&chip->gpio_chip);
+               spin_lock_init(&chip->lock);
+               chip->irq = JZ_IRQ_INTC_GPIO(i);
+               set_irq_data(chip->irq, chip);
+               set_irq_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
+               for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) {
+                       set_irq_chip_and_handler(irq, &chip->irq_chip, handle_level_irq);
+                       set_irq_chip_data(irq, chip);
+               }
+       }
+
+       sysdev_class_register(&jz_gpio_sysdev);
+
+       printk("JZ GPIO initalized\n");
+
+       return 0;
+}
+
+
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/irq.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/irq.c
new file mode 100644 (file)
index 0000000..2167f2d
--- /dev/null
@@ -0,0 +1,130 @@
+/*
+ *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
+ *     JZ4740 platform IRQ support
+ *
+ *  This program is free software; you can redistribute         it and/or modify it
+ *  under  the terms of         the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/timex.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+
+#include <asm/io.h>
+#include <asm/mipsregs.h>
+#include <asm/irq_cpu.h>
+
+static void __iomem *jz_intc_base;
+static uint32_t jz_intc_wakeup;
+static uint32_t jz_intc_saved;
+
+#define JZ_REG_BASE_INTC 0x10001000
+
+#define JZ_REG_INTC_STATUS     0x00
+#define JZ_REG_INTC_MASK       0x04
+#define JZ_REG_INTC_SET_MASK   0x08
+#define JZ_REG_INTC_CLEAR_MASK 0x0c
+#define JZ_REG_INTC_PENDING    0x10
+
+#define IRQ_BIT(x) BIT((x) - JZ_IRQ_BASE)
+
+static void intc_irq_unmask(unsigned int irq)
+{
+       writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
+}
+
+static void intc_irq_mask(unsigned int irq)
+{
+       writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_SET_MASK);
+}
+
+static void intc_irq_ack(unsigned int irq)
+{
+       writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_PENDING);
+}
+
+static int intc_irq_set_wake(unsigned int irq, unsigned int on)
+{
+       if (on)
+               jz_intc_wakeup |= IRQ_BIT(irq);
+       else
+               jz_intc_wakeup &= ~IRQ_BIT(irq);
+
+       return 0;
+}
+
+static struct irq_chip intc_irq_type = {
+       .name =         "INTC",
+       .mask =         intc_irq_mask,
+       .unmask =       intc_irq_unmask,
+       .ack =          intc_irq_ack,
+       .set_wake =     intc_irq_set_wake,
+};
+
+static irqreturn_t jz4740_cascade(int irq, void *data)
+{
+       uint32_t irq_reg;
+       irq_reg = readl(jz_intc_base + JZ_REG_INTC_PENDING);
+
+       if (irq_reg) {
+               generic_handle_irq(ffs(irq_reg) - 1 + JZ_IRQ_BASE);
+               return IRQ_HANDLED;
+       }
+
+       return 0;
+}
+
+static struct irqaction jz4740_cascade_action = {
+       .handler = jz4740_cascade,
+       .name = "JZ4740 cascade interrupt"
+};
+
+void __init arch_init_irq(void)
+{
+       int i;
+       mips_cpu_irq_init();
+
+       jz_intc_base = ioremap(JZ_REG_BASE_INTC, 0x14);
+
+       for (i = JZ_IRQ_BASE; i < JZ_IRQ_BASE + 32; i++) {
+               intc_irq_mask(i);
+               set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);
+       }
+
+       setup_irq(2, &jz4740_cascade_action);
+}
+
+asmlinkage void plat_irq_dispatch(void)
+{
+       unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
+       if (pending & STATUSF_IP2)
+               jz4740_cascade(2, NULL);
+       else if(pending & STATUSF_IP3)
+               do_IRQ(3);
+       else
+               spurious_interrupt();
+}
+
+/* TODO: Use sysdev */
+void jz4740_intc_suspend(void)
+{
+       jz_intc_saved = readl(jz_intc_base + JZ_REG_INTC_MASK);
+       writel(~jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_SET_MASK);
+}
+
+void jz4740_intc_resume(void)
+{
+       writel(~jz_intc_saved, jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
+}
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/platform.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/platform.c
new file mode 100644 (file)
index 0000000..4e37929
--- /dev/null
@@ -0,0 +1,246 @@
+/*
+ *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
+ *     JZ4740 platform devices
+ *
+ *  This program is free software; you can redistribute         it and/or modify it
+ *  under  the terms of         the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/resource.h>
+
+#include <asm/mach-jz4740/platform.h>
+#include <asm/mach-jz4740/regs.h>
+#include <asm/mach-jz4740/irq.h>
+
+/* OHCI (USB full speed host controller) */
+static struct resource jz4740_usb_ohci_resources[] = {
+       [0] = {
+               .start  = CPHYSADDR(UHC_BASE),
+               .end    = CPHYSADDR(UHC_BASE) + 0x10000 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = JZ_IRQ_UHC,
+               .end    = JZ_IRQ_UHC,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+/* The dmamask must be set for OHCI to work */
+static u64 ohci_dmamask = ~(u32)0;
+
+struct platform_device jz4740_usb_ohci_device = {
+       .name           = "jz-ohci",
+       .id             = 0,
+       .dev = {
+               .dma_mask               = &ohci_dmamask,
+               .coherent_dma_mask      = 0xffffffff,
+       },
+       .num_resources  = ARRAY_SIZE(jz4740_usb_ohci_resources),
+       .resource       = jz4740_usb_ohci_resources,
+};
+
+/* UDC (USB gadget controller) */
+static struct resource jz4740_usb_gdt_resources[] = {
+       [0] = {
+               .start  = CPHYSADDR(UDC_BASE),
+               .end    = CPHYSADDR(UDC_BASE) + 0x10000 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = JZ_IRQ_UDC,
+               .end    = JZ_IRQ_UDC,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static u64 jz4740_udc_dmamask = ~(u32)0;
+
+struct platform_device jz4740_usb_gdt_device = {
+       .name           = "jz-udc",
+       .id             = -1,
+       .dev = {
+               .dma_mask               = &jz4740_udc_dmamask,
+               .coherent_dma_mask      = 0xffffffff,
+       },
+       .num_resources  = ARRAY_SIZE(jz4740_usb_gdt_resources),
+       .resource       = jz4740_usb_gdt_resources,
+};
+
+/** MMC/SD controller **/
+static struct resource jz4740_mmc_resources[] = {
+       [0] = {
+               .start  = CPHYSADDR(MSC_BASE),
+               .end    = CPHYSADDR(MSC_BASE) + 0x10000 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = JZ_IRQ_MSC,
+               .end    = JZ_IRQ_MSC,
+               .flags  = IORESOURCE_IRQ,
+       }
+};
+
+static u64 jz4740_mmc_dmamask =  ~(u32)0;
+
+struct platform_device jz4740_mmc_device = {
+       .name = "jz4740-mmc",
+       .id = 0,
+       .dev = {
+               .dma_mask               = &jz4740_mmc_dmamask,
+               .coherent_dma_mask      = 0xffffffff,
+       },
+       .num_resources  = ARRAY_SIZE(jz4740_mmc_resources),
+       .resource       = jz4740_mmc_resources,
+};
+
+static struct resource jz4740_rtc_resources[] = {
+       [0] = {
+               .start  = CPHYSADDR(RTC_BASE),
+               .end    = CPHYSADDR(RTC_BASE) + 0x10,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = JZ_IRQ_RTC,
+               .end    = JZ_IRQ_RTC,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+struct platform_device jz4740_rtc_device = {
+       .name   = "jz4740-rtc",
+       .id     = -1,
+       .num_resources  = ARRAY_SIZE(jz4740_rtc_resources),
+       .resource       = jz4740_rtc_resources,
+};
+
+/** I2C controller **/
+static struct resource jz4740_i2c_resources[] = {
+       [0] = {
+               .start  = CPHYSADDR(I2C_BASE),
+               .end    = CPHYSADDR(I2C_BASE) + 0x10000 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = JZ_IRQ_I2C,
+               .end    = JZ_IRQ_I2C,
+               .flags  = IORESOURCE_IRQ,
+       }
+};
+
+static u64 jz4740_i2c_dmamask =  ~(u32)0;
+
+struct platform_device jz4740_i2c_device = {
+       .name = "jz_i2c",
+       .id = 0,
+       .dev = {
+               .dma_mask               = &jz4740_i2c_dmamask,
+               .coherent_dma_mask      = 0xffffffff,
+       },
+       .num_resources  = ARRAY_SIZE(jz4740_i2c_resources),
+       .resource       = jz4740_i2c_resources,
+};
+
+static struct resource jz4740_nand_resources[] = {
+       [0] = {
+               .start  = CPHYSADDR(EMC_BASE),
+               .end    = CPHYSADDR(EMC_BASE) + 0x10000 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+struct platform_device jz4740_nand_device = {
+       .name = "jz4740-nand",
+       .num_resources = ARRAY_SIZE(jz4740_nand_resources),
+       .resource = jz4740_nand_resources,
+};
+
+static struct resource jz4740_framebuffer_resources[] = {
+       [0] = {
+               .start  = CPHYSADDR(LCD_BASE),
+               .end    = CPHYSADDR(LCD_BASE) + 0x10000 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static u64 jz4740_fb_dmamask = ~(u32)0;
+
+struct platform_device jz4740_framebuffer_device = {
+       .name = "jz4740-fb",
+       .id = -1,
+       .num_resources = ARRAY_SIZE(jz4740_framebuffer_resources),
+       .resource = jz4740_framebuffer_resources,
+       .dev = {
+               .dma_mask = &jz4740_fb_dmamask,
+               .coherent_dma_mask = 0xffffffff,
+       },
+};
+
+static struct resource jz4740_i2s_resources[] = {
+       [0] = {
+               .start  = CPHYSADDR(AIC_BASE),
+               .end    = CPHYSADDR(AIC_BASE) + 0x38 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+struct platform_device jz4740_i2s_device = {
+       .name = "jz4740-i2s",
+       .id = -1,
+       .num_resources = ARRAY_SIZE(jz4740_i2s_resources),
+       .resource = jz4740_i2s_resources,
+};
+
+static struct resource jz4740_codec_resources[] = {
+       [0] = {
+               .start  = CPHYSADDR(AIC_BASE) + 0x80,
+               .end    = CPHYSADDR(AIC_BASE) + 0x88 - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+struct platform_device jz4740_codec_device = {
+       .name           = "jz4740-codec",
+       .id             = -1,
+       .num_resources  = ARRAY_SIZE(jz4740_codec_resources),
+       .resource       = jz4740_codec_resources,
+};
+
+static struct resource jz4740_adc_resources[] = {
+       [0] = {
+               .start  = CPHYSADDR(SADC_BASE),
+               .end    = CPHYSADDR(SADC_BASE) + 0x30,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = JZ_IRQ_SADC,
+               .end    = JZ_IRQ_SADC,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+struct platform_device jz4740_adc_device = {
+       .name           = "jz4740-adc",
+       .id             = -1,
+       .num_resources  = ARRAY_SIZE(jz4740_adc_resources),
+       .resource       = jz4740_adc_resources,
+};
+
+struct platform_device jz4740_battery_device = {
+       .name = "jz4740-battery",
+       .id = -1,
+       .dev = {
+               .parent = &jz4740_adc_device.dev
+       },
+};
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/pm.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/pm.c
new file mode 100644 (file)
index 0000000..d19bb81
--- /dev/null
@@ -0,0 +1,77 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *     JZ4740 SoC power management support
+ *
+ *  This program is free software; you can redistribute         it and/or modify it
+ *  under  the terms of         the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/pm.h>
+#include <linux/delay.h>
+#include <linux/suspend.h>
+#include <asm/mach-jz4740/regs.h>
+
+extern void jz4740_intc_suspend(void);
+extern void jz4740_intc_resume(void);
+
+static int jz_pm_enter(suspend_state_t state)
+{
+       unsigned long nfcsr = REG_EMC_NFCSR;
+       uint32_t scr = REG_CPM_SCR;
+
+       /* Disable nand flash */
+       REG_EMC_NFCSR = ~0xff;
+
+       udelay(100);
+
+       /*stop udc and usb*/
+       REG_CPM_SCR &= ~( 1<<6 | 1<<7);
+       REG_CPM_SCR |= 0<<6 | 1<<7;
+
+       jz4740_intc_suspend();
+
+       /* Enter SLEEP mode */
+       REG_CPM_LCR &= ~CPM_LCR_LPM_MASK;
+       REG_CPM_LCR |= CPM_LCR_LPM_SLEEP;
+       __asm__(".set\tmips3\n\t"
+               "wait\n\t"
+               ".set\tmips0");
+
+       /* Restore to IDLE mode */
+       REG_CPM_LCR &= ~CPM_LCR_LPM_MASK;
+       REG_CPM_LCR |= CPM_LCR_LPM_IDLE;
+
+       /* Restore nand flash control register */
+       REG_EMC_NFCSR = nfcsr;
+
+       jz4740_intc_resume();
+
+       /* Restore sleep control register */
+       REG_CPM_SCR = scr;
+
+       return 0;
+}
+
+static struct platform_suspend_ops jz_pm_ops = {
+       .valid          = suspend_valid_only_mem,
+       .enter          = jz_pm_enter,
+};
+
+/*
+ * Initialize power interface
+ */
+int __init jz_pm_init(void)
+{
+       suspend_set_ops(&jz_pm_ops);
+       return 0;
+
+}
+late_initcall(jz_pm_init);
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/prom.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/prom.c
new file mode 100644 (file)
index 0000000..e28d815
--- /dev/null
@@ -0,0 +1,111 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *    PROM library initialisation code, supports YAMON and U-Boot.
+ *
+ * Copyright 2000, 2001, 2006 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *             ppopov@mvista.com or source@mvista.com
+ *
+ * This file was derived from Carsten Langgaard's
+ * arch/mips/mips-boards/xx files.
+ *
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/string.h>
+
+#include <asm/bootinfo.h>
+#include <asm/mach-jz4740/regs.h>
+
+/* #define DEBUG_CMDLINE */
+
+int prom_argc;
+char **prom_argv, **prom_envp;
+
+char *prom_getcmdline(void)
+{
+       return &(arcs_cmdline[0]);
+}
+
+void prom_init_cmdline(void)
+{
+       char *cp, *c;
+       size_t i = 1;
+
+       cp = &(arcs_cmdline[0]);
+       while(i < prom_argc) {
+               c = prom_argv[i];
+               while (*c) {
+                       *cp++ = *c++;
+               }
+               *cp++ = ' ';
+               i++;
+       }
+       if (i > 1) {
+               *(cp - 1) = '\0';
+       }
+
+}
+
+void __init prom_init(void)
+{
+       unsigned long memsize;
+
+       prom_argc = (int) fw_arg0;
+       prom_argv = (char **) fw_arg1;
+       prom_envp = (char **) fw_arg2;
+
+       mips_machtype = MACH_INGENIC_JZ4740;
+
+       prom_init_cmdline();
+       memsize = 0x04000000;
+       add_memory_region(0, memsize, BOOT_MEM_RAM);
+}
+
+void __init prom_free_prom_memory(void)
+{
+}
+
+/* used by early printk */
+void prom_putchar(char c)
+{
+       volatile u8 *uart_lsr = (volatile u8 *)(UART0_BASE + OFF_LSR);
+       volatile u8 *uart_tdr = (volatile u8 *)(UART0_BASE + OFF_TDR);
+
+       /* Wait for fifo to shift out some bytes */
+       while ( !((*uart_lsr & (UARTLSR_TDRQ | UARTLSR_TEMT)) == 0x60) );
+
+       *uart_tdr = (u8)c;
+}
+
+const char *get_system_type(void)
+{
+       return "JZ4740";
+}
+
+EXPORT_SYMBOL(prom_getcmdline);
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/reset.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/reset.c
new file mode 100644 (file)
index 0000000..a4b2292
--- /dev/null
@@ -0,0 +1,50 @@
+/*
+ * linux/arch/mips/jz4740/reset.c
+ *
+ * JZ4740 reset routines.
+ *
+ * Copyright (c) 2006-2007  Ingenic Semiconductor Inc.
+ * Author: <yliu@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <asm/io.h>
+#include <asm/pgtable.h>
+#include <asm/processor.h>
+#include <asm/reboot.h>
+#include <asm/system.h>
+#include <asm/mach-jz4740/regs.h>
+#include <asm/mach-jz4740/timer.h>
+#include <asm/mach-jz4740/jz4740.h>
+
+void jz_restart(char *command)
+{
+       printk(KERN_NOTICE "Restarting after 4 ms\n");
+       REG_WDT_TCSR = WDT_TCSR_PRESCALE4 | WDT_TCSR_EXT_EN;
+       REG_WDT_TCNT = 0;
+       REG_WDT_TDR = JZ_EXTAL/1000;   /* reset after 4ms */
+       jz4740_timer_enable_watchdog();
+       REG_WDT_TCER = WDT_TCER_TCEN;  /* wdt start */
+       while (1);
+}
+
+void jz_halt(void)
+{
+       /* Put CPU to power down mode */
+       while (!(REG_RTC_RCR & RTC_RCR_WRDY));
+       REG_RTC_HCR = RTC_HCR_PD;
+
+       while (1)
+               __asm__(".set\tmips3\n\t"
+                       "wait\n\t"
+                       ".set\tmips0");
+}
+
+void jz_power_off(void)
+{
+       jz_halt();
+}
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/setup.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/setup.c
new file mode 100644 (file)
index 0000000..3f12e2e
--- /dev/null
@@ -0,0 +1,108 @@
+/*
+ * linux/arch/mips/jz4740/common/setup.c
+ * 
+ * JZ4740 common setup routines.
+ * 
+ * Copyright (C) 2006 Ingenic Semiconductor Inc.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ */
+#include <linux/init.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/tty.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/serial_8250.h>
+
+#include <asm/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+#include <asm/mipsregs.h>
+#include <asm/reboot.h>
+#include <asm/pgtable.h>
+#include <asm/time.h>
+#include <asm/mach-jz4740/jz4740.h>
+#include <asm/mach-jz4740/regs.h>
+#include <asm/mach-jz4740/clock.h>
+#include <asm/mach-jz4740/serial.h>
+
+extern char *__init prom_getcmdline(void);
+extern void __init jz_board_setup(void);
+extern void jz_restart(char *);
+extern void jz_halt(void);
+extern void jz_power_off(void);
+extern void jz_time_init(void);
+
+static void __init soc_cpm_setup(void)
+{
+       /* Enable CKO to external memory */
+       __cpm_enable_cko();
+
+       /* CPU enters IDLE mode when executing 'wait' instruction */
+       __cpm_idle_mode();
+}
+
+
+static void __init jz_serial_setup(void)
+{
+#ifdef CONFIG_SERIAL_8250
+       struct uart_port s;
+       REG8(UART0_FCR) |= UARTFCR_UUE; /* enable UART module */
+       memset(&s, 0, sizeof(s));
+       s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
+       s.iotype = SERIAL_IO_MEM;
+       s.regshift = 2;
+       s.uartclk = JZ_EXTAL;
+
+       s.line = 0;
+       s.membase = (u8 *)UART0_BASE;
+       s.irq = JZ_IRQ_UART0;
+       if (early_serial_setup(&s) != 0) {
+               printk(KERN_ERR "Serial ttyS0 setup failed!\n");
+       }
+
+       s.line = 1;
+       s.membase = (u8 *)UART1_BASE;
+       s.irq = JZ_IRQ_UART1;
+       if (early_serial_setup(&s) != 0) {
+               printk(KERN_ERR "Serial ttyS1 setup failed!\n");
+       }
+#endif
+}
+
+void __init plat_mem_setup(void)
+{
+       char *argptr;
+
+       argptr = prom_getcmdline();
+
+       /* IO/MEM resources. Which will be the addtion value in `inX' and
+        * `outX' macros defined in asm/io.h */
+       set_io_port_base(0);
+       ioport_resource.start   = 0x00000000;
+       ioport_resource.end     = 0xffffffff;
+       iomem_resource.start    = 0x00000000;
+       iomem_resource.end      = 0xffffffff;
+
+       _machine_restart = jz_restart;
+       _machine_halt = jz_halt;
+       pm_power_off = jz_power_off;
+       soc_cpm_setup();
+       jz_serial_setup();
+}
+
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/time.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/time.c
new file mode 100644 (file)
index 0000000..b811fcd
--- /dev/null
@@ -0,0 +1,262 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *     JZ4740 platform timer support
+ *
+ *  This program is free software; you can redistribute         it and/or modify it
+ *  under  the terms of         the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/time.h>
+#include <linux/clockchips.h>
+#include <linux/clk.h>
+
+#include <asm/mach-jz4740/irq.h>
+#include <asm/mach-jz4740/jz4740.h>
+#include <asm/time.h>
+
+#define JZ_REG_TIMER_STOP              0x1C
+#define JZ_REG_TIMER_STOP_SET          0x2C
+#define JZ_REG_TIMER_STOP_CLEAR                0x3C
+#define JZ_REG_TIMER_ENABLE            0x10
+#define JZ_REG_TIMER_ENABLE_SET                0x14
+#define JZ_REG_TIMER_ENABLE_CLEAR      0x18
+#define JZ_REG_TIMER_FLAG              0x20
+#define JZ_REG_TIMER_FLAG_SET          0x24
+#define JZ_REG_TIMER_FLAG_CLEAR                0x28
+#define JZ_REG_TIMER_MASK              0x30
+#define JZ_REG_TIMER_MASK_SET          0x34
+#define JZ_REG_TIMER_MASK_CLEAR                0x38
+
+#define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x40)
+#define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x44)
+#define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x48)
+#define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x4C)
+
+#define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10)
+#define JZ_TIMER_IRQ_FULL(x) BIT(x)
+
+#define JZ_TIMER_CTRL_PWM_ACTIVE_LOW   BIT(8)
+#define JZ_TIMER_CTRL_PWM_ENABLE       BIT(7)
+#define JZ_TIMER_CTRL_PRESCALE_MASK    0x1c
+#define JZ_TIMER_CTRL_PRESCALE_OFFSET  0x3
+#define JZ_TIMER_CTRL_PRESCALE_1       (0 << 3)
+#define JZ_TIMER_CTRL_PRESCALE_4       (1 << 3)
+#define JZ_TIMER_CTRL_PRESCALE_16      (2 << 3)
+#define JZ_TIMER_CTRL_PRESCALE_64      (3 << 3)
+#define JZ_TIMER_CTRL_PRESCALE_256     (4 << 3)
+#define JZ_TIMER_CTRL_PRESCALE_1024    (5 << 3)
+
+#define JZ_TIMER_CTRL_SRC_EXT          BIT(2)
+#define JZ_TIMER_CTRL_SRC_RTC          BIT(1)
+#define JZ_TIMER_CTRL_SRC_PCLK         BIT(0)
+
+static void __iomem *jz4740_timer_base;
+static uint16_t jz4740_jiffies_per_tick;
+
+void jz4740_timer_enable_watchdog(void)
+{
+       writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
+}
+
+void jz4740_timer_disable_watchdog(void)
+{
+       writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
+}
+
+static inline void jz4740_timer_set_period(unsigned int timer, uint16_t period)
+{
+       writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer));
+}
+
+static inline void jz4740_timer_set_duty(unsigned int timer, uint16_t duty)
+{
+       writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer));
+}
+
+static void jz4740_init_timer(void)
+{
+       uint16_t val = 0;
+       val |= JZ_TIMER_CTRL_PRESCALE_16;
+       val |= JZ_TIMER_CTRL_SRC_EXT;
+
+       writew(val, jz4740_timer_base + JZ_REG_TIMER_CTRL(0));
+       writew(0xffff, jz4740_timer_base + JZ_REG_TIMER_DFR(0));
+       writew(val, jz4740_timer_base + JZ_REG_TIMER_CTRL(1));
+       writew(0xffff, jz4740_timer_base + JZ_REG_TIMER_DFR(1));
+}
+
+static void jz4740_timer_enable(unsigned int timer)
+{
+       writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
+       writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
+}
+
+static void jz4740_timer_disable(unsigned int timer)
+{
+       writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
+       writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
+}
+
+static void jz4740_timer_irq_full_enable(unsigned int timer)
+{
+       writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
+       writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
+}
+
+static int jz4740_timer_irq_full_is_enabled(unsigned int timer)
+{
+       return !(readl(jz4740_timer_base + JZ_REG_TIMER_MASK) &
+       JZ_TIMER_IRQ_FULL(timer));
+}
+
+static void jz4740_timer_irq_full_disable(unsigned int timer)
+{
+       writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
+}
+
+static void jz4740_timer_irq_half_enable(unsigned int timer)
+{
+       writel(JZ_TIMER_IRQ_HALF(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
+       writel(JZ_TIMER_IRQ_HALF(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
+}
+
+static void jz4740_timer_irq_half_disable(unsigned int timer)
+{
+       writel(JZ_TIMER_IRQ_HALF(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
+}
+
+static cycle_t jz4740_clocksource_read(struct clocksource *cs)
+{
+    uint16_t val;
+       val = readw(jz4740_timer_base + JZ_REG_TIMER_CNT(1));
+       return val;
+}
+
+static struct clocksource jz4740_clocksource = {
+       .name = "jz4740-timer",
+       .rating = 200,
+       .read = jz4740_clocksource_read,
+       .mask = CLOCKSOURCE_MASK(16),
+       .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static irqreturn_t jz4740_clockevent_irq(int irq, void *devid)
+{
+       struct clock_event_device *cd = devid;
+
+       writel(JZ_TIMER_IRQ_FULL(0), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
+
+       if (cd->mode != CLOCK_EVT_MODE_PERIODIC) {
+               jz4740_timer_disable(0);
+               cd->event_handler(cd);
+        } else {
+               cd->event_handler(cd);
+       }
+
+    return IRQ_HANDLED;
+}
+
+static void jz4740_clockevent_set_mode(enum clock_event_mode mode,
+                                      struct clock_event_device *cd)
+{
+       switch(mode) {
+       case CLOCK_EVT_MODE_PERIODIC:
+               writew(0x0, jz4740_timer_base + JZ_REG_TIMER_CNT(0));
+               writew(jz4740_jiffies_per_tick, jz4740_timer_base + JZ_REG_TIMER_DFR(0));
+       case CLOCK_EVT_MODE_RESUME:
+               jz4740_timer_irq_full_enable(0);
+               jz4740_timer_enable(0);
+               break;
+       case CLOCK_EVT_MODE_ONESHOT:
+       case CLOCK_EVT_MODE_SHUTDOWN:
+               jz4740_timer_disable(0);
+               break;
+       default:
+               break;
+       }
+}
+
+static int jz4740_clockevent_set_next(unsigned long evt, struct
+clock_event_device *cd)
+{
+       writew(0x0, jz4740_timer_base + JZ_REG_TIMER_CNT(0));
+       writew(evt, jz4740_timer_base + JZ_REG_TIMER_DFR(0));
+       jz4740_timer_enable(0);
+
+       return 0;
+}
+
+static struct clock_event_device jz4740_clockevent = {
+       .name = "jz4740-timer",
+       .features = CLOCK_EVT_FEAT_PERIODIC,
+       .set_next_event = jz4740_clockevent_set_next,
+       .set_mode = jz4740_clockevent_set_mode,
+       .rating = 200,
+    .irq = JZ_IRQ_TCU0,
+};
+
+static struct irqaction jz_irqaction = {
+       .handler        = jz4740_clockevent_irq,
+       .flags          = IRQF_PERCPU | IRQF_TIMER | IRQF_DISABLED,
+       .name           = "jz4740-timerirq",
+    .dev_id      = &jz4740_clockevent,
+};
+
+
+void __init plat_time_init(void)
+{
+    int ret;
+       uint32_t clk_rate;
+       struct clk *ext_clk;
+
+       jz4740_timer_base = ioremap(CPHYSADDR(TCU_BASE), 0x100);
+
+       if (!jz4740_timer_base) {
+           printk(KERN_ERR "Failed to ioremap timer registers");
+           return;
+       }
+
+       /*ext_clk = clk_get(NULL, "ext");
+       clk_rate = clk_get_rate(ext_clk) >> 4;
+       clk_put(ext_clk);*/
+
+
+       clk_rate = JZ_EXTAL >> 4;
+
+    jz4740_jiffies_per_tick = DIV_ROUND_CLOSEST(clk_rate, HZ);
+
+       clockevent_set_clock(&jz4740_clockevent, clk_rate);
+       jz4740_clockevent.min_delta_ns = clockevent_delta2ns(100, &jz4740_clockevent);
+       jz4740_clockevent.max_delta_ns = clockevent_delta2ns(0xffff, &jz4740_clockevent);
+       jz4740_clockevent.cpumask = cpumask_of(0);
+
+       clockevents_register_device(&jz4740_clockevent);
+
+       clocksource_set_clock(&jz4740_clocksource, clk_rate);
+       ret = clocksource_register(&jz4740_clocksource);
+
+       if (ret)
+           printk(KERN_ERR "Failed to register clocksource: %d\n", ret);
+
+       setup_irq(JZ_IRQ_TCU0, &jz_irqaction);
+
+       jz4740_init_timer();
+       writew(jz4740_jiffies_per_tick, jz4740_timer_base + JZ_REG_TIMER_DFR(0));
+    jz4740_timer_irq_half_disable(0);
+    jz4740_timer_irq_full_enable(0);
+       jz4740_timer_enable(0);
+
+    jz4740_timer_irq_half_disable(1);
+    jz4740_timer_irq_full_disable(1);
+
+       jz4740_timer_enable(1);
+}
diff --git a/target/linux/xburst/files-2.6.32/drivers/char/defkeymap.c b/target/linux/xburst/files-2.6.32/drivers/char/defkeymap.c
new file mode 100644 (file)
index 0000000..fca8d59
--- /dev/null
@@ -0,0 +1,422 @@
+/* Do not edit this file! It was automatically generated by   */
+/*    loadkeys --mktable defkeymap.map > defkeymap.c          */
+
+#include <linux/types.h>
+#include <linux/keyboard.h>
+#include <linux/kd.h>
+
+u_short plain_map[NR_KEYS] = {
+       0xf200, 0xf01b, 0xf031, 0xf032, 0xf033, 0xf034, 0xf035, 0xf036,
+       0xf037, 0xf038, 0xf039, 0xf030, 0xf02d, 0xf03d, 0xf07f, 0xf009,
+       0xfb71, 0xfb77, 0xfb65, 0xfb72, 0xfb74, 0xfb79, 0xfb75, 0xfb69,
+       0xfb6f, 0xfb70, 0xf05b, 0xf05d, 0xf201, 0xf706, 0xfb61, 0xfb73,
+       0xfb64, 0xfb66, 0xfb67, 0xfb68, 0xfb6a, 0xfb6b, 0xfb6c, 0xf03b,
+       0xf027, 0xf060, 0xf700, 0xf05c, 0xfb7a, 0xfb78, 0xfb63, 0xfb76,
+       0xfb62, 0xfb6e, 0xfb6d, 0xf02c, 0xf02e, 0xf02f, 0xf701, 0xf30c,
+       0xf703, 0xf020, 0xf207, 0xf100, 0xf101, 0xf102, 0xf103, 0xf104,
+       0xf105, 0xf106, 0xf107, 0xf108, 0xf109, 0xf208, 0xf209, 0xf307,
+       0xf308, 0xf309, 0xf30b, 0xf304, 0xf305, 0xf306, 0xf30a, 0xf301,
+       0xf302, 0xf303, 0xf300, 0xf310, 0xf206, 0xf200, 0xf03c, 0xf10a,
+       0xf10b, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf30e, 0xf702, 0xf30d, 0xf01c, 0xf701, 0xf205, 0xf114, 0xf603,
+       0xf118, 0xf601, 0xf602, 0xf117, 0xf600, 0xf119, 0xf115, 0xf116,
+       0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+};
+
+static u_short shift_map[NR_KEYS] = {
+       0xf200, 0xf01b, 0xf021, 0xf040, 0xf023, 0xf024, 0xf025, 0xf05e,
+       0xf026, 0xf02a, 0xf028, 0xf029, 0xf05f, 0xf02b, 0xf07f, 0xf009,
+       0xfb51, 0xfb57, 0xfb45, 0xfb52, 0xfb54, 0xfb59, 0xfb55, 0xfb49,
+       0xfb4f, 0xfb50, 0xf07b, 0xf07d, 0xf201, 0xf706, 0xfb41, 0xfb53,
+       0xfb44, 0xfb46, 0xfb47, 0xfb48, 0xfb4a, 0xfb4b, 0xfb4c, 0xf03a,
+       0xf022, 0xf07e, 0xf700, 0xf07c, 0xfb5a, 0xfb58, 0xfb43, 0xfb56,
+       0xfb42, 0xfb4e, 0xfb4d, 0xf03b, 0xf03a, 0xf03f, 0xf701, 0xf30c,
+       0xf703, 0xf020, 0xf207, 0xf10a, 0xf10b, 0xf10c, 0xf10d, 0xf10e,
+       0xf10f, 0xf110, 0xf111, 0xf112, 0xf113, 0xf213, 0xf203, 0xf307,
+       0xf308, 0xf309, 0xf30b, 0xf304, 0xf305, 0xf306, 0xf30a, 0xf301,
+       0xf302, 0xf303, 0xf300, 0xf310, 0xf206, 0xf200, 0xf03e, 0xf10a,
+       0xf10b, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf30e, 0xf702, 0xf30d, 0xf01c, 0xf701, 0xf205, 0xf114, 0xf603,
+       0xf20b, 0xf601, 0xf602, 0xf117, 0xf600, 0xf20a, 0xf115, 0xf116,
+       0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+};
+
+static u_short altgr_map[NR_KEYS] = {
+       0xf200, 0xf200, 0xf200, 0xf040, 0xf200, 0xf024, 0xf200, 0xf200,
+       0xf07b, 0xf05b, 0xf05d, 0xf07d, 0xf05c, 0xf07e, 0xf008, 0xf200,
+       0xf021, 0xf040, 0xf023, 0xf024, 0xf025, 0xf05e, 0xf026, 0xf02a,
+       0xf028, 0xf029, 0xf200, 0xf07e, 0xf201, 0xf706, 0xf0b0, 0xf0a8,
+       0xf0a4, 0xf02d, 0xf05f, 0xf07b, 0xf05b, 0xf05d, 0xf07d, 0xf200,
+       0xf200, 0xf200, 0xf700, 0xf200, 0xf039, 0xf030, 0xf916, 0xfb76,
+       0xf915, 0xf03c, 0xf03e, 0xf027, 0xf022, 0xf200, 0xf701, 0xf30c,
+       0xf703, 0xf200, 0xf207, 0xf031, 0xf032, 0xf033, 0xf034, 0xf035,
+       0xf036, 0xf037, 0xf038, 0xf514, 0xf515, 0xf208, 0xf202, 0xf911,
+       0xf912, 0xf913, 0xf30b, 0xf90e, 0xf90f, 0xf910, 0xf30a, 0xf90b,
+       0xf90c, 0xf90d, 0xf90a, 0xf310, 0xf206, 0xf200, 0xf07c, 0xf516,
+       0xf517, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf30e, 0xf702, 0xf30d, 0xf01c, 0xf701, 0xf205, 0xf114, 0xf603,
+       0xf118, 0xf601, 0xf602, 0xf117, 0xf600, 0xf119, 0xf115, 0xf116,
+       0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+};
+
+static u_short ctrl_map[NR_KEYS] = {
+       0xf200, 0xf200, 0xf200, 0xf000, 0xf01b, 0xf01c, 0xf01d, 0xf01e,
+       0xf01f, 0xf07f, 0xf200, 0xf200, 0xf01f, 0xf200, 0xf200, 0xf200,
+       0xf011, 0xf017, 0xf005, 0xf012, 0xf014, 0xf019, 0xf015, 0xf009,
+       0xf00f, 0xf010, 0xf01b, 0xf01d, 0xf201, 0xf706, 0xf001, 0xf013,
+       0xf004, 0xf006, 0xf007, 0xf008, 0xf00a, 0xf00b, 0xf00c, 0xf200,
+       0xf007, 0xf000, 0xf700, 0xf01c, 0xf01a, 0xf018, 0xf003, 0xf016,
+       0xf002, 0xf00e, 0xf00d, 0xf200, 0xf20e, 0xf07f, 0xf701, 0xf30c,
+       0xf703, 0xf000, 0xf207, 0xf100, 0xf101, 0xf102, 0xf103, 0xf104,
+       0xf105, 0xf106, 0xf107, 0xf108, 0xf109, 0xf208, 0xf204, 0xf307,
+       0xf308, 0xf309, 0xf30b, 0xf304, 0xf305, 0xf306, 0xf30a, 0xf301,
+       0xf302, 0xf303, 0xf300, 0xf310, 0xf206, 0xf200, 0xf200, 0xf10a,
+       0xf10b, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf30e, 0xf702, 0xf30d, 0xf01c, 0xf701, 0xf205, 0xf114, 0xf603,
+       0xf118, 0xf601, 0xf602, 0xf117, 0xf600, 0xf119, 0xf115, 0xf116,
+       0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+};
+
+static u_short shift_ctrl_map[NR_KEYS] = {
+       0xf200, 0xf200, 0xf200, 0xf000, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf01f, 0xf200, 0xf200, 0xf200,
+       0xf011, 0xf017, 0xf005, 0xf012, 0xf014, 0xf019, 0xf015, 0xf009,
+       0xf00f, 0xf010, 0xf200, 0xf200, 0xf201, 0xf706, 0xf001, 0xf013,
+       0xf004, 0xf006, 0xf007, 0xf008, 0xf00a, 0xf00b, 0xf00c, 0xf200,
+       0xf200, 0xf200, 0xf700, 0xf200, 0xf01a, 0xf018, 0xf003, 0xf016,
+       0xf002, 0xf00e, 0xf00d, 0xf200, 0xf200, 0xf200, 0xf701, 0xf30c,
+       0xf703, 0xf200, 0xf207, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf208, 0xf200, 0xf307,
+       0xf308, 0xf309, 0xf30b, 0xf304, 0xf305, 0xf306, 0xf30a, 0xf301,
+       0xf302, 0xf303, 0xf300, 0xf310, 0xf206, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf30e, 0xf702, 0xf30d, 0xf01c, 0xf701, 0xf205, 0xf114, 0xf603,
+       0xf118, 0xf601, 0xf602, 0xf117, 0xf600, 0xf119, 0xf115, 0xf116,
+       0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+};
+
+static u_short alt_map[NR_KEYS] = {
+       0xf200, 0xf81b, 0xf831, 0xf832, 0xf833, 0xf834, 0xf835, 0xf836,
+       0xf837, 0xf838, 0xf839, 0xf830, 0xf82d, 0xf83d, 0xf87f, 0xf809,
+       0xf871, 0xf877, 0xf865, 0xf872, 0xf874, 0xf879, 0xf875, 0xf869,
+       0xf86f, 0xf870, 0xf85b, 0xf85d, 0xf80d, 0xf706, 0xf861, 0xf873,
+       0xf864, 0xf866, 0xf867, 0xf868, 0xf86a, 0xf86b, 0xf86c, 0xf83b,
+       0xf827, 0xf860, 0xf700, 0xf85c, 0xf87a, 0xf878, 0xf863, 0xf876,
+       0xf862, 0xf86e, 0xf86d, 0xf200, 0xf200, 0xf82f, 0xf701, 0xf30c,
+       0xf703, 0xf820, 0xf207, 0xf500, 0xf501, 0xf502, 0xf503, 0xf504,
+       0xf505, 0xf506, 0xf507, 0xf508, 0xf509, 0xf208, 0xf209, 0xf907,
+       0xf908, 0xf909, 0xf30b, 0xf904, 0xf905, 0xf906, 0xf30a, 0xf901,
+       0xf902, 0xf903, 0xf900, 0xf310, 0xf206, 0xf200, 0xf83c, 0xf50a,
+       0xf50b, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf30e, 0xf702, 0xf30d, 0xf01c, 0xf701, 0xf205, 0xf114, 0xf603,
+       0xf118, 0xf210, 0xf211, 0xf117, 0xf600, 0xf119, 0xf115, 0xf116,
+       0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+};
+
+static u_short ctrl_alt_map[NR_KEYS] = {
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf811, 0xf817, 0xf805, 0xf812, 0xf814, 0xf819, 0xf815, 0xf809,
+       0xf80f, 0xf810, 0xf200, 0xf200, 0xf201, 0xf706, 0xf801, 0xf813,
+       0xf804, 0xf806, 0xf807, 0xf808, 0xf80a, 0xf80b, 0xf80c, 0xf200,
+       0xf200, 0xf200, 0xf700, 0xf200, 0xf81a, 0xf818, 0xf803, 0xf816,
+       0xf802, 0xf80e, 0xf80d, 0xf200, 0xf200, 0xf200, 0xf701, 0xf30c,
+       0xf703, 0xf200, 0xf207, 0xf500, 0xf501, 0xf502, 0xf503, 0xf504,
+       0xf505, 0xf506, 0xf507, 0xf508, 0xf509, 0xf208, 0xf200, 0xf307,
+       0xf308, 0xf309, 0xf30b, 0xf304, 0xf305, 0xf306, 0xf30a, 0xf301,
+       0xf302, 0xf303, 0xf300, 0xf20c, 0xf206, 0xf200, 0xf200, 0xf50a,
+       0xf50b, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf30e, 0xf702, 0xf30d, 0xf01c, 0xf701, 0xf205, 0xf114, 0xf603,
+       0xf118, 0xf601, 0xf602, 0xf117, 0xf600, 0xf119, 0xf115, 0xf20c,
+       0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+};
+
+static u_short ctl_map[NR_KEYS] = {
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf033, 0xf200, 0xf200,
+       0xfb71, 0xfb77, 0xfb65, 0xfb72, 0xfb74, 0xfb79, 0xf037, 0xf038,
+       0xf039, 0xfb70, 0xf200, 0xf200, 0xf201, 0xf706, 0xfb61, 0xfb73,
+       0xfb64, 0xfb66, 0xfb67, 0xfb68, 0xf034, 0xf035, 0xf036, 0xf200,
+       0xf200, 0xf200, 0xf700, 0xf200, 0xfb7a, 0xfb78, 0xfb63, 0xfb76,
+       0xfb62, 0xf031, 0xf032, 0xf200, 0xf200, 0xf030, 0xf701, 0xf30c,
+       0xf703, 0xf200, 0xf207, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf208, 0xf200, 0xf307,
+       0xf308, 0xf309, 0xf30b, 0xf304, 0xf305, 0xf306, 0xf30a, 0xf301,
+       0xf302, 0xf303, 0xf300, 0xf310, 0xf206, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf30e, 0xf702, 0xf30d, 0xf01c, 0xf701, 0xf205, 0xf114, 0xf603,
+       0xf118, 0xf601, 0xf602, 0xf117, 0xf600, 0xf119, 0xf115, 0xf116,
+       0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+       0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,
+};
+
+ushort *key_maps[MAX_NR_KEYMAPS] = {
+       plain_map, shift_map, altgr_map, 0,
+       ctrl_map, shift_ctrl_map, 0, 0,
+       alt_map, 0, 0, 0,
+       ctrl_alt_map, 0, 0, 0,
+       0, 0, 0, 0,
+       0, 0, 0, 0,
+       0, 0, 0, 0,
+       0, 0, 0, 0,
+       0, 0, 0, 0,
+       0, 0, 0, 0,
+       0, 0, 0, 0,
+       0, 0, 0, 0,
+       0, 0, 0, 0,
+       0, 0, 0, 0,
+       0, 0, 0, 0,
+       0, 0, 0, 0,
+       ctl_map,        0
+};
+
+unsigned int keymap_count = 8;
+
+/*
+ * Philosophy: most people do not define more strings, but they who do
+ * often want quite a lot of string space. So, we statically allocate
+ * the default and allocate dynamically in chunks of 512 bytes.
+ */
+
+char func_buf[] = {
+       '\033', '[', '[', 'A', 0, 
+       '\033', '[', '[', 'B', 0, 
+       '\033', '[', '[', 'C', 0, 
+       '\033', '[', '[', 'D', 0, 
+       '\033', '[', '[', 'E', 0, 
+       '\033', '[', '1', '7', '~', 0, 
+       '\033', '[', '1', '8', '~', 0, 
+       '\033', '[', '1', '9', '~', 0, 
+       '\033', '[', '2', '0', '~', 0, 
+       '\033', '[', '2', '1', '~', 0, 
+       '\033', '[', '2', '3', '~', 0, 
+       '\033', '[', '2', '4', '~', 0, 
+       '\033', '[', '2', '5', '~', 0, 
+       '\033', '[', '2', '6', '~', 0, 
+       '\033', '[', '2', '8', '~', 0, 
+       '\033', '[', '2', '9', '~', 0, 
+       '\033', '[', '3', '1', '~', 0, 
+       '\033', '[', '3', '2', '~', 0, 
+       '\033', '[', '3', '3', '~', 0, 
+       '\033', '[', '3', '4', '~', 0, 
+       '\033', '[', '1', '~', 0, 
+       '\033', '[', '2', '~', 0, 
+       '\033', '[', '3', '~', 0, 
+       '\033', '[', '4', '~', 0, 
+       '\033', '[', '5', '~', 0, 
+       '\033', '[', '6', '~', 0, 
+       '\033', '[', 'M', 0, 
+       '\033', '[', 'P', 0, 
+};
+
+char *funcbufptr = func_buf;
+int funcbufsize = sizeof(func_buf);
+int funcbufleft = 0;          /* space left */
+
+char *func_table[MAX_NR_FUNC] = {
+       func_buf + 0,
+       func_buf + 5,
+       func_buf + 10,
+       func_buf + 15,
+       func_buf + 20,
+       func_buf + 25,
+       func_buf + 31,
+       func_buf + 37,
+       func_buf + 43,
+       func_buf + 49,
+       func_buf + 55,
+       func_buf + 61,
+       func_buf + 67,
+       func_buf + 73,
+       func_buf + 79,
+       func_buf + 85,
+       func_buf + 91,
+       func_buf + 97,
+       func_buf + 103,
+       func_buf + 109,
+       func_buf + 115,
+       func_buf + 120,
+       func_buf + 125,
+       func_buf + 130,
+       func_buf + 135,
+       func_buf + 140,
+       func_buf + 145,
+       0,
+       0,
+       func_buf + 149,
+       0,
+};
+
+struct kbdiacr accent_table[MAX_DIACR] = {
+       {'`', 'A', '\300'},     {'`', 'a', '\340'},
+       {'\'', 'A', '\301'},    {'\'', 'a', '\341'},
+       {'^', 'A', '\302'},     {'^', 'a', '\342'},
+       {'~', 'A', '\303'},     {'~', 'a', '\343'},
+       {'"', 'A', '\304'},     {'"', 'a', '\344'},
+       {'O', 'A', '\305'},     {'o', 'a', '\345'},
+       {'0', 'A', '\305'},     {'0', 'a', '\345'},
+       {'A', 'A', '\305'},     {'a', 'a', '\345'},
+       {'A', 'E', '\306'},     {'a', 'e', '\346'},
+       {',', 'C', '\307'},     {',', 'c', '\347'},
+       {'`', 'E', '\310'},     {'`', 'e', '\350'},
+       {'\'', 'E', '\311'},    {'\'', 'e', '\351'},
+       {'^', 'E', '\312'},     {'^', 'e', '\352'},
+       {'"', 'E', '\313'},     {'"', 'e', '\353'},
+       {'`', 'I', '\314'},     {'`', 'i', '\354'},
+       {'\'', 'I', '\315'},    {'\'', 'i', '\355'},
+       {'^', 'I', '\316'},     {'^', 'i', '\356'},
+       {'"', 'I', '\317'},     {'"', 'i', '\357'},
+       {'-', 'D', '\320'},     {'-', 'd', '\360'},
+       {'~', 'N', '\321'},     {'~', 'n', '\361'},
+       {'`', 'O', '\322'},     {'`', 'o', '\362'},
+       {'\'', 'O', '\323'},    {'\'', 'o', '\363'},
+       {'^', 'O', '\324'},     {'^', 'o', '\364'},
+       {'~', 'O', '\325'},     {'~', 'o', '\365'},
+       {'"', 'O', '\326'},     {'"', 'o', '\366'},
+       {'/', 'O', '\330'},     {'/', 'o', '\370'},
+       {'`', 'U', '\331'},     {'`', 'u', '\371'},
+       {'\'', 'U', '\332'},    {'\'', 'u', '\372'},
+       {'^', 'U', '\333'},     {'^', 'u', '\373'},
+       {'"', 'U', '\334'},     {'"', 'u', '\374'},
+       {'\'', 'Y', '\335'},    {'\'', 'y', '\375'},
+       {'T', 'H', '\336'},     {'t', 'h', '\376'},
+       {'s', 's', '\337'},     {'"', 'y', '\377'},
+       {'s', 'z', '\337'},     {'i', 'j', '\377'},
+};
+
+unsigned int accent_table_size = 68;
diff --git a/target/linux/xburst/files-2.6.32/drivers/i2c/chips/n526-lpc.c b/target/linux/xburst/files-2.6.32/drivers/i2c/chips/n526-lpc.c
new file mode 100644 (file)
index 0000000..4ac5c79
--- /dev/null
@@ -0,0 +1,237 @@
+/*
+ * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/i2c.h>
+#include <linux/input.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+
+#include <linux/workqueue.h>
+
+#include <asm/mach-jz4740/irq.h>
+#include <asm/mach-jz4740/gpio.h>
+
+struct n526_lpc {
+       struct i2c_client *client;
+       struct input_dev *input;
+
+       struct work_struct work;
+};
+
+static const unsigned int n526_lpc_keymap[] = {
+       [0x01] = KEY_PAGEUP,
+       [0x02] = KEY_PAGEDOWN,
+       [0x03] = KEY_VOLUMEUP,
+       [0x04] = KEY_VOLUMEDOWN,
+       [0x06] = KEY_1,
+       [0x07] = KEY_Q,
+       [0x08] = KEY_A,
+       [0x09] = KEY_Z,
+       [0x0a] = KEY_LEFTSHIFT,
+       [0x0b] = KEY_2,
+       [0x0c] = KEY_W,
+       [0x0d] = KEY_S,
+       [0x0e] = KEY_X,
+       [0x0f] = KEY_REFRESH,
+       [0x10] = KEY_3,
+       [0x11] = KEY_E,
+       [0x12] = KEY_D,
+       [0x13] = KEY_C,
+       [0x14] = KEY_DOCUMENTS,
+       [0x15] = KEY_4,
+       [0x16] = KEY_R,
+       [0x17] = KEY_F,
+       [0x18] = KEY_V,
+       [0x19] = KEY_MUTE,
+       [0x1a] = KEY_5,
+       [0x1b] = KEY_T,
+       [0x1c] = KEY_G,
+       [0x1d] = KEY_B,
+       [0x1e] = KEY_DELETE,
+       [0x1f] = KEY_6,
+       [0x20] = KEY_Y,
+       [0x21] = KEY_H,
+       [0x22] = KEY_N,
+       [0x23] = KEY_SPACE,
+       [0x24] = KEY_7,
+       [0x25] = KEY_U,
+       [0x26] = KEY_J,
+       [0x27] = KEY_M,
+/*     [0x28] = KEY_SYM, */
+       [0x29] = KEY_8,
+       [0x2a] = KEY_I,
+       [0x2b] = KEY_K,
+       [0x2c] = KEY_MENU,
+       [0x2d] = KEY_LEFT,
+       [0x2e] = KEY_9,
+       [0x2f] = KEY_O,
+       [0x30] = KEY_L,
+       [0x31] = KEY_UP,
+       [0x32] = KEY_DOWN,
+       [0x33] = KEY_0,
+       [0x34] = KEY_P,
+       [0x35] = KEY_BACKSPACE,
+       [0x36] = KEY_ENTER,
+       [0x37] = KEY_RIGHT,
+};
+
+static void n526_lpc_irq_work(struct work_struct *work)
+{
+       int ret;
+       struct n526_lpc *n526_lpc = container_of(work, struct n526_lpc, work);
+       struct i2c_client *client = n526_lpc->client;
+       unsigned char raw_msg;
+       struct i2c_msg msg = {client->addr, client->flags | I2C_M_RD, 1, &raw_msg};
+       unsigned char keycode;
+
+
+       ret = i2c_transfer(client->adapter, &msg, 1);
+
+       if (ret != 1) {
+               dev_err(&client->dev, "Failed to read lpc status\n");
+       }
+
+       keycode = raw_msg & 0x7f;
+
+       if (keycode < ARRAY_SIZE(n526_lpc_keymap)) {
+               input_report_key(n526_lpc->input, n526_lpc_keymap[keycode],
+                                !(raw_msg & 0x80));
+               input_sync(n526_lpc->input);
+       }
+}
+
+static irqreturn_t n526_lpc_irq(int irq, void *dev_id)
+{
+       struct n526_lpc *n526_lpc = dev_id;
+
+       schedule_work(&n526_lpc->work);
+       return IRQ_HANDLED;
+}
+
+static int __devinit n526_lpc_probe(struct i2c_client *client,
+               const struct i2c_device_id *id)
+{
+       int ret;
+       size_t i;
+       struct n526_lpc *n526_lpc;
+       struct input_dev *input;
+
+       n526_lpc = kmalloc(sizeof(*n526_lpc), GFP_KERNEL);
+
+       if (!n526_lpc) {
+               dev_err(&client->dev, "Failed to allocate device structure\n");
+               return -ENOMEM;
+       }
+
+       input = input_allocate_device();
+       if (!input) {
+               dev_err(&client->dev, "Failed to allocate input device\n");
+               ret = -ENOMEM;
+               goto err_free;
+       }
+
+       input->name = "n526-keys";
+       input->phys = "n526-keys/input0";
+       input->dev.parent = &client->dev;
+       input->id.bustype = BUS_I2C;
+       input->id.vendor  = 0x0001;
+       input->id.product = 0x0001;
+       input->id.version = 0x0001;
+
+       __set_bit(EV_KEY, input->evbit);
+
+       for (i = 0; i < ARRAY_SIZE(n526_lpc_keymap); ++i) {
+               if (n526_lpc_keymap[i] != 0)
+                       __set_bit(n526_lpc_keymap[i], input->keybit);
+       }
+
+       ret = input_register_device(input);
+
+       if (ret) {
+               dev_err(&client->dev, "Failed to register input device: %d\n", ret);
+               goto err_free_input;
+       }
+
+       n526_lpc->client = client;
+       n526_lpc->input  = input;
+       INIT_WORK(&n526_lpc->work, n526_lpc_irq_work);
+
+       ret = request_irq(client->irq, n526_lpc_irq, IRQF_TRIGGER_FALLING,
+                         "n526-lpc", n526_lpc);
+       if (ret) {
+               dev_err(&client->dev, "Failed to request irq: %d\n", ret);
+               goto err_unregister_input;
+       }
+
+       i2c_set_clientdata(client, n526_lpc);
+
+       return 0;
+
+err_unregister_input:
+       input_unregister_device(input);
+err_free_input:
+       input_free_device(input);
+err_free:
+       kfree(n526_lpc);
+
+       return ret;
+}
+
+static int n526_lpc_remove(struct i2c_client *client)
+{
+       struct n526_lpc *n526_lpc = i2c_get_clientdata(client);
+
+       free_irq(client->irq, n526_lpc);
+
+       i2c_set_clientdata(client, NULL);
+       input_unregister_device(n526_lpc->input);
+       input_free_device(n526_lpc->input);
+       kfree(n526_lpc);
+
+ return 0;
+}
+
+static const struct i2c_device_id n526_lpc_id[] = {
+       { "n526-lpc", 0 },
+       { }
+};
+MODULE_DEVICE_TABLE(i2c, n526_lpc_id);
+
+static struct i2c_driver n526_lpc_driver = {
+       .driver = {
+               .name = "n526-lpc",
+               .owner = THIS_MODULE,
+       },
+       .probe = n526_lpc_probe,
+       .remove = n526_lpc_remove,
+       .id_table = n526_lpc_id,
+};
+
+static int __init n526_lpc_init(void)
+{
+       return i2c_add_driver(&n526_lpc_driver);
+}
+module_init(n526_lpc_init);
+
+static void __exit n526_lpc_exit(void)
+{
+       i2c_del_driver(&n526_lpc_driver);
+}
+module_exit(n526_lpc_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Lars-Peter Clausen");
+MODULE_DESCRIPTION("n526 keypad driver");
+MODULE_ALIAS("i2c:n526-keys");
diff --git a/target/linux/xburst/files-2.6.32/drivers/misc/jz4740-adc.c b/target/linux/xburst/files-2.6.32/drivers/misc/jz4740-adc.c
new file mode 100644 (file)
index 0000000..7da3bcc
--- /dev/null
@@ -0,0 +1,362 @@
+/*
+ * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
+ *             JZ4720/JZ4740 SoC ADC driver
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * This driver is meant to synchronize access to the adc core for the battery
+ * and touchscreen driver. Thus these drivers should use the adc driver as a
+ * parent.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/jz4740-adc.h>
+
+#define JZ_REG_ADC_ENABLE      0x00
+#define JZ_REG_ADC_CFG         0x04
+#define JZ_REG_ADC_CTRL                0x08
+#define JZ_REG_ADC_STATUS      0x0C
+#define JZ_REG_ADC_SAME                0x10
+#define JZ_REG_ADC_WAIT                0x14
+#define JZ_REG_ADC_TOUCH       0x18
+#define JZ_REG_ADC_BATTERY     0x1C
+#define JZ_REG_ADC_ADCIN       0x20
+
+#define JZ_ADC_ENABLE_TOUCH            BIT(2)
+#define JZ_ADC_ENABLE_BATTERY          BIT(1)
+#define JZ_ADC_ENABLE_ADCIN            BIT(0)
+
+#define JZ_ADC_CFG_SPZZ                        BIT(31)
+#define JZ_ADC_CFG_EX_IN               BIT(30)
+#define JZ_ADC_CFG_DNUM_MASK           (0x7 << 16)
+#define JZ_ADC_CFG_DMA_ENABLE          BIT(15)
+#define JZ_ADC_CFG_XYZ_MASK            (0x2 << 13)
+#define JZ_ADC_CFG_SAMPLE_NUM_MASK     (0x7 << 10)
+#define JZ_ADC_CFG_CLKDIV              (0xf << 5)
+#define JZ_ADC_CFG_BAT_MB              BIT(4)
+
+#define JZ_ADC_CFG_DNUM_OFFSET         16
+#define JZ_ADC_CFG_XYZ_OFFSET          13
+#define JZ_ADC_CFG_SAMPLE_NUM_OFFSET   10
+#define JZ_ADC_CFG_CLKDIV_OFFSET       5
+
+#define JZ_ADC_IRQ_PENDOWN             BIT(4)
+#define JZ_ADC_IRQ_PENUP               BIT(3)
+#define JZ_ADC_IRQ_TOUCH               BIT(2)
+#define JZ_ADC_IRQ_BATTERY             BIT(1)
+#define JZ_ADC_IRQ_ADCIN               BIT(0)
+
+#define JZ_ADC_TOUCH_TYPE1             BIT(31)
+#define JZ_ADC_TOUCH_DATA1_MASK                0xfff
+#define JZ_ADC_TOUCH_TYPE0             BIT(15)
+#define JZ_ADC_TOUCH_DATA0_MASK                0xfff
+
+#define JZ_ADC_BATTERY_MASK            0xfff
+
+#define JZ_ADC_ADCIN_MASK              0xfff
+
+struct jz4740_adc {
+       struct resource *mem;
+       void __iomem *base;
+
+       int irq;
+
+       struct completion bat_completion;
+       struct completion adc_completion;
+
+       spinlock_t lock;
+};
+
+static irqreturn_t jz4740_adc_irq(int irq, void *data)
+{
+       struct jz4740_adc *adc = data;
+       uint8_t status;
+
+       status = readb(adc->base + JZ_REG_ADC_STATUS);
+
+       if (status & JZ_ADC_IRQ_BATTERY)
+               complete(&adc->bat_completion);
+       if (status & JZ_ADC_IRQ_ADCIN)
+               complete(&adc->adc_completion);
+
+       writeb(0xff, adc->base + JZ_REG_ADC_STATUS);
+
+       return IRQ_HANDLED;
+}
+
+static void jz4740_adc_enable_irq(struct jz4740_adc *adc, int irq)
+{
+       unsigned long flags;
+       uint8_t val;
+
+       spin_lock_irqsave(&adc->lock, flags);
+
+       val = readb(adc->base + JZ_REG_ADC_CTRL);
+       val &= ~irq;
+       writeb(val, adc->base + JZ_REG_ADC_CTRL);
+
+       spin_unlock_irqrestore(&adc->lock, flags);
+}
+
+static void jz4740_adc_disable_irq(struct jz4740_adc *adc, int irq)
+{
+       unsigned long flags;
+       uint8_t val;
+
+       spin_lock_irqsave(&adc->lock, flags);
+
+       val = readb(adc->base + JZ_REG_ADC_CTRL);
+       val |= irq;
+       writeb(val, adc->base + JZ_REG_ADC_CTRL);
+
+       spin_unlock_irqrestore(&adc->lock, flags);
+}
+
+static void jz4740_adc_enable_adc(struct jz4740_adc *adc, int engine)
+{
+       unsigned long flags;
+       uint8_t val;
+
+       spin_lock_irqsave(&adc->lock, flags);
+
+       val = readb(adc->base + JZ_REG_ADC_ENABLE);
+       val |= engine;
+       writeb(val, adc->base + JZ_REG_ADC_ENABLE);
+
+       spin_unlock_irqrestore(&adc->lock, flags);
+}
+
+static void jz4740_adc_disable_adc(struct jz4740_adc *adc, int engine)
+{
+       unsigned long flags;
+       uint8_t val;
+
+       spin_lock_irqsave(&adc->lock, flags);
+
+       val = readb(adc->base + JZ_REG_ADC_ENABLE);
+       val &= ~engine;
+       writeb(val, adc->base + JZ_REG_ADC_ENABLE);
+
+       spin_unlock_irqrestore(&adc->lock, flags);
+}
+
+static inline void jz4740_adc_set_cfg(struct jz4740_adc *adc, uint32_t mask,
+uint32_t val)
+{
+       unsigned long flags;
+       uint32_t cfg;
+
+       spin_lock_irqsave(&adc->lock, flags);
+
+       cfg = readl(adc->base + JZ_REG_ADC_CFG);
+
+       cfg &= ~mask;
+       cfg |= val;
+
+       writel(cfg, adc->base + JZ_REG_ADC_CFG);
+
+       spin_unlock_irqrestore(&adc->lock, flags);
+}
+
+long jz4740_adc_read_battery_voltage(struct device *dev,
+                                               enum jz_adc_battery_scale scale)
+{
+       struct jz4740_adc *adc = dev_get_drvdata(dev);
+       unsigned long t;
+       long long voltage;
+       uint16_t val;
+
+       if (!adc)
+               return -ENODEV;
+
+       if (scale == JZ_ADC_BATTERY_SCALE_2V5)
+               jz4740_adc_set_cfg(adc, JZ_ADC_CFG_BAT_MB, JZ_ADC_CFG_BAT_MB);
+       else
+               jz4740_adc_set_cfg(adc, JZ_ADC_CFG_BAT_MB, 0);
+
+       jz4740_adc_enable_irq(adc, JZ_ADC_IRQ_BATTERY);
+       jz4740_adc_enable_adc(adc, JZ_ADC_ENABLE_BATTERY);
+
+       t = wait_for_completion_interruptible_timeout(&adc->bat_completion,
+                                                       HZ);
+
+       jz4740_adc_disable_irq(adc, JZ_ADC_IRQ_BATTERY);
+
+       if (t <= 0) {
+               jz4740_adc_disable_adc(adc, JZ_ADC_ENABLE_BATTERY);
+               return t ? t : -ETIMEDOUT;
+       }
+
+       val = readw(adc->base + JZ_REG_ADC_BATTERY);
+
+       if (scale == JZ_ADC_BATTERY_SCALE_2V5)
+               voltage = (((long long)val) * 2500000LL) >> 12LL;
+       else
+               voltage = ((((long long)val) * 7395000LL) >> 12LL) + 33000LL;
+
+       return voltage;
+}
+EXPORT_SYMBOL_GPL(jz4740_adc_read_battery_voltage);
+
+static ssize_t jz4740_adc_read_adcin(struct device *dev,
+                                       struct device_attribute *dev_attr,
+                                       char *buf)
+{
+       struct jz4740_adc *adc = dev_get_drvdata(dev);
+       unsigned long t;
+       uint16_t val;
+
+       jz4740_adc_enable_irq(adc, JZ_ADC_IRQ_ADCIN);
+       jz4740_adc_enable_adc(adc, JZ_ADC_ENABLE_ADCIN);
+
+       t = wait_for_completion_interruptible_timeout(&adc->adc_completion,
+                                                       HZ);
+
+       jz4740_adc_disable_irq(adc, JZ_ADC_IRQ_ADCIN);
+
+       if (t <= 0) {
+               jz4740_adc_disable_adc(adc, JZ_ADC_ENABLE_ADCIN);
+               return t ? t : -ETIMEDOUT;
+       }
+
+       val = readw(adc->base + JZ_REG_ADC_ADCIN);
+
+       return sprintf(buf, "%d\n", val);
+}
+
+static DEVICE_ATTR(adcin, S_IRUGO, jz4740_adc_read_adcin, NULL);
+
+static int __devinit jz4740_adc_probe(struct platform_device *pdev)
+{
+       int ret;
+       struct jz4740_adc *adc;
+
+       adc = kmalloc(sizeof(*adc), GFP_KERNEL);
+
+       adc->irq = platform_get_irq(pdev, 0);
+
+       if (adc->irq < 0) {
+               ret = adc->irq;
+               dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
+               goto err_free;
+       }
+
+       adc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+       if (!adc->mem) {
+               ret = -ENOENT;
+               dev_err(&pdev->dev, "Failed to get platform mmio resource\n");
+               goto err_free;
+       }
+
+       adc->mem = request_mem_region(adc->mem->start, resource_size(adc->mem),
+                                       pdev->name);
+
+       if (!adc->mem) {
+               ret = -EBUSY;
+               dev_err(&pdev->dev, "Failed to request mmio memory region\n");
+               goto err_free;
+       }
+
+       adc->base = ioremap_nocache(adc->mem->start, resource_size(adc->mem));
+
+       if (!adc->base) {
+               ret = -EBUSY;
+               dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
+               goto err_release_mem_region;
+       }
+
+
+       init_completion(&adc->bat_completion);
+       init_completion(&adc->adc_completion);
+
+       spin_lock_init(&adc->lock);
+
+       platform_set_drvdata(pdev, adc);
+
+       ret = request_irq(adc->irq, jz4740_adc_irq, 0, pdev->name, adc);
+
+       if (ret) {
+               dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
+               goto err_iounmap;
+       }
+
+       ret = device_create_file(&pdev->dev, &dev_attr_adcin);
+       if (ret) {
+               dev_err(&pdev->dev, "Failed to create sysfs file: %d\n", ret);
+               goto err_free_irq;
+       }
+
+       writeb(0x00, adc->base + JZ_REG_ADC_ENABLE);
+       writeb(0xff, adc->base + JZ_REG_ADC_CTRL);
+
+       return 0;
+
+err_free_irq:
+       free_irq(adc->irq, adc);
+err_iounmap:
+       platform_set_drvdata(pdev, NULL);
+       iounmap(adc->base);
+err_release_mem_region:
+       release_mem_region(adc->mem->start, resource_size(adc->mem));
+err_free:
+       kfree(adc);
+
+       return ret;
+}
+
+static int __devexit jz4740_adc_remove(struct platform_device *pdev)
+{
+       struct jz4740_adc *adc = platform_get_drvdata(pdev);
+
+       device_remove_file(&pdev->dev, &dev_attr_adcin);
+
+       free_irq(adc->irq, adc);
+
+       iounmap(adc->base);
+       release_mem_region(adc->mem->start, resource_size(adc->mem));
+
+       platform_set_drvdata(pdev, NULL);
+
+       kfree(adc);
+
+       return 0;
+}
+
+struct platform_driver jz4740_adc_driver = {
+       .probe  = jz4740_adc_probe,
+       .remove = jz4740_adc_remove,
+       .driver = {
+               .name = "jz4740-adc",
+               .owner = THIS_MODULE,
+       },
+};
+
+static int __init jz4740_adc_init(void)
+{
+       return platform_driver_register(&jz4740_adc_driver);
+}
+module_init(jz4740_adc_init);
+
+static void __exit jz4740_adc_exit(void)
+{
+       platform_driver_unregister(&jz4740_adc_driver);
+}
+module_exit(jz4740_adc_exit);
+
+MODULE_DESCRIPTION("JZ4720/JZ4740 SoC ADC driver");
+MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:jz4740-adc");
+MODULE_ALIAS("platform:jz4720-adc");
diff --git a/target/linux/xburst/files-2.6.32/drivers/mmc/host/jz_mmc.c b/target/linux/xburst/files-2.6.32/drivers/mmc/host/jz_mmc.c
new file mode 100644 (file)
index 0000000..e4bdde0
--- /dev/null
@@ -0,0 +1,955 @@
+/*
+ *  Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
+ *     JZ7420/JZ4740 GPIO SD/MMC controller driver
+ *
+ *  This program is free software; you can redistribute         it and/or modify it
+ *  under  the terms of         the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/mmc/host.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/scatterlist.h>
+#include <linux/clk.h>
+#include <linux/mmc/jz4740_mmc.h>
+
+#include <linux/gpio.h>
+#include <asm/mach-jz4740/gpio.h>
+#include <asm/cacheflush.h>
+#include <linux/dma-mapping.h>
+
+#define JZ_REG_MMC_STRPCL      0x00
+#define JZ_REG_MMC_STATUS      0x04
+#define JZ_REG_MMC_CLKRT       0x08
+#define JZ_REG_MMC_CMDAT       0x0C
+#define JZ_REG_MMC_RESTO       0x10
+#define JZ_REG_MMC_RDTO                0x14
+#define JZ_REG_MMC_BLKLEN      0x18
+#define JZ_REG_MMC_NOB         0x1C
+#define JZ_REG_MMC_SNOB                0x20
+#define JZ_REG_MMC_IMASK       0x24
+#define JZ_REG_MMC_IREG                0x28
+#define JZ_REG_MMC_CMD         0x2C
+#define JZ_REG_MMC_ARG         0x30
+#define JZ_REG_MMC_RESP_FIFO   0x34
+#define JZ_REG_MMC_RXFIFO      0x38
+#define JZ_REG_MMC_TXFIFO      0x3C
+
+#define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7)
+#define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6)
+#define JZ_MMC_STRPCL_START_READWAIT BIT(5)
+#define JZ_MMC_STRPCL_STOP_READWAIT BIT(4)
+#define JZ_MMC_STRPCL_RESET BIT(3)
+#define JZ_MMC_STRPCL_START_OP BIT(2)
+#define JZ_MMC_STRPCL_CLOCK_CONTROL BIT(1) | BIT(0)
+#define JZ_MMC_STRPCL_CLOCK_STOP BIT(0)
+#define JZ_MMC_STRPCL_CLOCK_START BIT(1)
+
+
+#define JZ_MMC_STATUS_IS_RESETTING BIT(15)
+#define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14)
+#define JZ_MMC_STATUS_PRG_DONE BIT(13)
+#define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12)
+#define JZ_MMC_STATUS_END_CMD_RES BIT(11)
+#define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10)
+#define JZ_MMC_STATUS_IS_READWAIT BIT(9)
+#define JZ_MMC_STATUS_CLK_EN BIT(8)
+#define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7)
+#define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6)
+#define JZ_MMC_STATUS_CRC_RES_ERR BIT(5)
+#define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4)
+#define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3)
+#define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2)
+#define JZ_MMC_STATUS_TIMEOUT_RES BIT(1)
+#define JZ_MMC_STATUS_TIMEOUT_READ BIT(0)
+
+#define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0))
+#define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2))
+
+
+#define JZ_MMC_CMDAT_IO_ABORT BIT(11)
+#define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10)
+#define JZ_MMC_CMDAT_DMA_EN BIT(8)
+#define JZ_MMC_CMDAT_INIT BIT(7)
+#define JZ_MMC_CMDAT_BUSY BIT(6)
+#define JZ_MMC_CMDAT_STREAM BIT(5)
+#define JZ_MMC_CMDAT_WRITE BIT(4)
+#define JZ_MMC_CMDAT_DATA_EN BIT(3)
+#define JZ_MMC_CMDAT_RESPONSE_FORMAT BIT(2) | BIT(1) | BIT(0)
+#define JZ_MMC_CMDAT_RSP_R1 1
+#define JZ_MMC_CMDAT_RSP_R2 2
+#define JZ_MMC_CMDAT_RSP_R3 3
+
+#define JZ_MMC_IRQ_SDIO BIT(7)
+#define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6)
+#define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5)
+#define JZ_MMC_IRQ_END_CMD_RES BIT(2)
+#define JZ_MMC_IRQ_PRG_DONE BIT(1)
+#define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0)
+
+
+#define JZ_MMC_CLK_RATE 24000000
+
+struct jz4740_mmc_host {
+       struct mmc_host *mmc;
+       struct platform_device *pdev;
+       struct jz4740_mmc_platform_data *pdata;
+       struct clk *clk;
+
+       int irq;
+       int card_detect_irq;
+
+       struct resource *mem;
+       void __iomem *base;
+       struct mmc_request *req;
+       struct mmc_command *cmd;
+
+       int max_clock;
+       uint32_t cmdat;
+
+       uint16_t irq_mask;
+
+       spinlock_t lock;
+       struct timer_list clock_timer;
+       struct timer_list timeout_timer;
+       unsigned waiting:1;
+};
+
+static void jz4740_mmc_cmd_done(struct jz4740_mmc_host *host);
+
+static void jz4740_mmc_enable_irq(struct jz4740_mmc_host *host, unsigned int irq)
+{
+       unsigned long flags;
+       spin_lock_irqsave(&host->lock, flags);
+
+       host->irq_mask &= ~irq;
+       writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK);
+
+       spin_unlock_irqrestore(&host->lock, flags);
+}
+
+static void jz4740_mmc_disable_irq(struct jz4740_mmc_host *host, unsigned int irq)
+{
+       unsigned long flags;
+       spin_lock_irqsave(&host->lock, flags);
+
+       host->irq_mask |= irq;
+       writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK);
+
+       spin_unlock_irqrestore(&host->lock, flags);
+}
+
+static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host, bool start_transfer)
+{
+       uint16_t val = JZ_MMC_STRPCL_CLOCK_START;
+
+       if (start_transfer)
+               val |= JZ_MMC_STRPCL_START_OP;
+
+       writew(val, host->base + JZ_REG_MMC_STRPCL);
+}
+
+static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host)
+{
+       uint16_t status;
+       writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL);
+       do {
+               status = readl(host->base + JZ_REG_MMC_STATUS);
+       } while (status & JZ_MMC_STATUS_CLK_EN);
+
+}
+
+static void jz4740_mmc_reset(struct jz4740_mmc_host *host)
+{
+       writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL);
+       udelay(10);
+       while(readw(host->base + JZ_REG_MMC_STATUS) & JZ_MMC_STATUS_IS_RESETTING);
+}
+
+static void jz4740_mmc_request_done(struct jz4740_mmc_host *host)
+{
+       struct mmc_request *req;
+       unsigned long flags;
+
+       spin_lock_irqsave(&host->lock, flags);
+       req = host->req;
+       host->req = NULL;
+       host->waiting = 0;
+       spin_unlock_irqrestore(&host->lock, flags);
+
+       if (!unlikely(req))
+               return;
+
+/*     if (req->cmd->error != 0) {
+               printk("error\n");
+               jz4740_mmc_reset(host);
+       }*/
+
+       mmc_request_done(host->mmc, req);
+}
+
+static void jz4740_mmc_write_data(struct jz4740_mmc_host *host, struct mmc_data *data) {
+       struct scatterlist *sg;
+       uint32_t *sg_pointer;
+       int status;
+       size_t i, j;
+
+       for (sg = data->sg; sg; sg = sg_next(sg)) {
+               sg_pointer = sg_virt(sg);
+               i = sg->length / 4;
+               j = i >> 3;
+               i = i & 0x7;
+               while (j) {
+                       do {
+                               status = readw(host->base + JZ_REG_MMC_IREG);
+                       } while (!(status & JZ_MMC_IRQ_TXFIFO_WR_REQ));
+                       writew(JZ_MMC_IRQ_TXFIFO_WR_REQ, host->base + JZ_REG_MMC_IREG);
+
+                       writel(sg_pointer[0], host->base + JZ_REG_MMC_TXFIFO);
+                       writel(sg_pointer[1], host->base + JZ_REG_MMC_TXFIFO);
+                       writel(sg_pointer[2], host->base + JZ_REG_MMC_TXFIFO);
+                       writel(sg_pointer[3], host->base + JZ_REG_MMC_TXFIFO);
+                       writel(sg_pointer[4], host->base + JZ_REG_MMC_TXFIFO);
+                       writel(sg_pointer[5], host->base + JZ_REG_MMC_TXFIFO);
+                       writel(sg_pointer[6], host->base + JZ_REG_MMC_TXFIFO);
+                       writel(sg_pointer[7], host->base + JZ_REG_MMC_TXFIFO);
+                       sg_pointer += 8;
+                       --j;
+               }
+               if (i) {
+                       do {
+                               status = readw(host->base + JZ_REG_MMC_IREG);
+                       } while (!(status & JZ_MMC_IRQ_TXFIFO_WR_REQ));
+                       writew(JZ_MMC_IRQ_TXFIFO_WR_REQ, host->base + JZ_REG_MMC_IREG);
+
+                       while (i) {
+                               writel(*sg_pointer, host->base + JZ_REG_MMC_TXFIFO);
+                               ++sg_pointer;
+                               --i;
+                       }
+               }
+               data->bytes_xfered += sg->length;
+       }
+
+       status = readl(host->base + JZ_REG_MMC_STATUS);
+       if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK)
+               goto err;
+
+       writew(JZ_MMC_IRQ_TXFIFO_WR_REQ, host->base + JZ_REG_MMC_IREG);
+       do {
+               status = readl(host->base + JZ_REG_MMC_STATUS);
+       } while ((status & JZ_MMC_STATUS_DATA_TRAN_DONE) == 0);
+       writew(JZ_MMC_IRQ_DATA_TRAN_DONE, host->base + JZ_REG_MMC_IREG);
+
+       return;
+err:
+       if(status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) {
+               host->req->cmd->error = -ETIMEDOUT;
+               data->error = -ETIMEDOUT;
+       } else {
+               host->req->cmd->error = -EILSEQ;
+               data->error = -EILSEQ;
+       }
+}
+
+static void jz4740_mmc_timeout(unsigned long data)
+{
+       struct jz4740_mmc_host *host = (struct jz4740_mmc_host*)data;
+       unsigned long flags;
+
+       spin_lock_irqsave(&host->lock, flags);
+       if (!host->waiting) {
+               spin_unlock_irqrestore(&host->lock, flags);
+               return;
+       }
+
+       host->waiting = 0;
+
+       spin_unlock_irqrestore(&host->lock, flags);
+
+       host->req->cmd->error = -ETIMEDOUT;
+       jz4740_mmc_request_done(host);
+}
+
+static void jz4740_mmc_read_data(struct jz4740_mmc_host *host, struct mmc_data *data) {
+       struct scatterlist *sg;
+       uint32_t *sg_pointer;
+       uint32_t d;
+       uint16_t status = 0;
+       size_t i, j;
+
+       for (sg = data->sg; sg; sg = sg_next(sg)) {
+               sg_pointer = sg_virt(sg);
+               i = sg->length;
+               j = i >> 5;
+               i = i & 0x1f;
+               while (j) {
+                       do {
+                               status = readw(host->base + JZ_REG_MMC_IREG);
+                       } while (!(status & JZ_MMC_IRQ_RXFIFO_RD_REQ));
+                       writew(JZ_MMC_IRQ_RXFIFO_RD_REQ, host->base + JZ_REG_MMC_IREG);
+
+                       sg_pointer[0] = readl(host->base + JZ_REG_MMC_RXFIFO);
+                       sg_pointer[1] = readl(host->base + JZ_REG_MMC_RXFIFO);
+                       sg_pointer[2] = readl(host->base + JZ_REG_MMC_RXFIFO);
+                       sg_pointer[3] = readl(host->base + JZ_REG_MMC_RXFIFO);
+                       sg_pointer[4] = readl(host->base + JZ_REG_MMC_RXFIFO);
+                       sg_pointer[5] = readl(host->base + JZ_REG_MMC_RXFIFO);
+                       sg_pointer[6] = readl(host->base + JZ_REG_MMC_RXFIFO);
+                       sg_pointer[7] = readl(host->base + JZ_REG_MMC_RXFIFO);
+
+                       sg_pointer += 8;
+                       --j;
+               }
+
+               while (i >= 4) {
+                       do {
+                               status = readl(host->base + JZ_REG_MMC_STATUS);
+                       } while ((status & JZ_MMC_STATUS_DATA_FIFO_EMPTY));
+
+                       *sg_pointer = readl(host->base + JZ_REG_MMC_RXFIFO);
+                       ++sg_pointer;
+                       i -= 4;
+               }
+               if (i > 0) {
+                       d = readl(host->base + JZ_REG_MMC_RXFIFO);
+                       memcpy(sg_pointer, &d, i);
+               }
+               data->bytes_xfered += sg->length;
+
+               flush_dcache_page(sg_page(sg));
+       }
+
+       status = readl(host->base + JZ_REG_MMC_STATUS);
+       if (status & JZ_MMC_STATUS_READ_ERROR_MASK)
+               goto err;
+
+       /* For whatever reason there is sometime one word more in the fifo then
+        * requested */
+       while ((status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) == 0) {
+               d = readl(host->base + JZ_REG_MMC_RXFIFO);
+               status = readl(host->base + JZ_REG_MMC_STATUS);
+       }
+       return;
+
+err:
+       if(status & JZ_MMC_STATUS_TIMEOUT_READ) {
+               host->req->cmd->error = -ETIMEDOUT;
+               data->error = -ETIMEDOUT;
+       } else {
+               host->req->cmd->error = -EILSEQ;
+               data->error = -EILSEQ;
+       }
+}
+
+static irqreturn_t jz_mmc_irq_worker(int irq, void *devid)
+{
+       struct jz4740_mmc_host *host = (struct jz4740_mmc_host*)devid;
+
+       if (host->cmd->error)
+               jz4740_mmc_request_done(host);
+       else
+               jz4740_mmc_cmd_done(host);
+
+       return IRQ_HANDLED;
+}
+
+static irqreturn_t jz_mmc_irq(int irq, void *devid)
+{
+       struct jz4740_mmc_host *host = devid;
+       uint16_t irq_reg, status, tmp;
+       unsigned long flags;
+       irqreturn_t ret = IRQ_HANDLED;
+
+       irq_reg = readw(host->base + JZ_REG_MMC_IREG);
+
+       tmp = irq_reg;
+       spin_lock(&host->lock);
+       irq_reg &= ~host->irq_mask;
+       spin_unlock(&host->lock);
+
+       if (irq_reg & JZ_MMC_IRQ_SDIO) {
+               writew(JZ_MMC_IRQ_SDIO, host->base + JZ_REG_MMC_IREG);
+               mmc_signal_sdio_irq(host->mmc);
+       }
+
+       if (!host->req || !host->cmd) {
+               goto handled;
+       }
+
+
+       spin_lock_irqsave(&host->lock, flags);
+       if (!host->waiting) {
+               spin_unlock_irqrestore(&host->lock, flags);
+               goto handled;
+       }
+       host->waiting = 0;
+       spin_unlock_irqrestore(&host->lock, flags);
+
+       del_timer(&host->timeout_timer);
+
+       status = readl(host->base + JZ_REG_MMC_STATUS);
+
+       if (status & JZ_MMC_STATUS_TIMEOUT_RES) {
+               host->cmd->error = -ETIMEDOUT;
+       } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) {
+               host->cmd->error = -EIO;
+       } else if(status & (JZ_MMC_STATUS_CRC_READ_ERROR |
+                                               JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
+               host->cmd->data->error = -EIO;
+       } else if(status & (JZ_MMC_STATUS_CRC_READ_ERROR |
+                                               JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
+               host->cmd->data->error = -EIO;
+       }
+
+       if (irq_reg & JZ_MMC_IRQ_END_CMD_RES) {
+               jz4740_mmc_disable_irq(host, JZ_MMC_IRQ_END_CMD_RES);
+               writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG);
+               ret = IRQ_WAKE_THREAD;
+       }
+
+       return ret;
+handled:
+
+       writew(0xff, host->base + JZ_REG_MMC_IREG);
+       return IRQ_HANDLED;
+}
+
+static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate) {
+       int div = 0;
+       int real_rate = host->max_clock;
+       jz4740_mmc_clock_disable(host);
+
+       while ((real_rate >> 1) >= rate && div < 7) {
+               ++div;
+               real_rate >>= 1;
+       }
+       clk_set_rate(host->clk, JZ_MMC_CLK_RATE);
+
+       writew(div, host->base + JZ_REG_MMC_CLKRT);
+       return real_rate;
+}
+
+
+static void jz4740_mmc_read_response(struct jz4740_mmc_host *host, struct mmc_command *cmd)
+{
+       int i;
+       uint16_t tmp;
+       if (cmd->flags & MMC_RSP_136) {
+               tmp = readw(host->base + JZ_REG_MMC_RESP_FIFO);
+               for (i = 0; i < 4; ++i) {
+                       cmd->resp[i] = tmp << 24;
+                       cmd->resp[i] |= readw(host->base + JZ_REG_MMC_RESP_FIFO) << 8;
+                       tmp = readw(host->base + JZ_REG_MMC_RESP_FIFO);
+                       cmd->resp[i] |= tmp >> 8;
+               }
+       } else {
+               cmd->resp[0] = readw(host->base + JZ_REG_MMC_RESP_FIFO) << 24;
+               cmd->resp[0] |= readw(host->base + JZ_REG_MMC_RESP_FIFO) << 8;
+               cmd->resp[0] |= readw(host->base + JZ_REG_MMC_RESP_FIFO) & 0xff;
+       }
+}
+
+static void jz4740_mmc_send_command(struct jz4740_mmc_host *host, struct mmc_command *cmd)
+{
+       uint32_t cmdat = host->cmdat;
+
+       host->cmdat &= ~JZ_MMC_CMDAT_INIT;
+       jz4740_mmc_clock_disable(host);
+
+       host->cmd = cmd;
+
+       if (cmd->flags & MMC_RSP_BUSY)
+               cmdat |= JZ_MMC_CMDAT_BUSY;
+
+       switch (mmc_resp_type(cmd)) {
+       case MMC_RSP_R1B:
+       case MMC_RSP_R1:
+               cmdat |= JZ_MMC_CMDAT_RSP_R1;
+               break;
+       case MMC_RSP_R2:
+               cmdat |= JZ_MMC_CMDAT_RSP_R2;
+               break;
+       case MMC_RSP_R3:
+               cmdat |= JZ_MMC_CMDAT_RSP_R3;
+               break;
+       default:
+               break;
+       }
+
+       if (cmd->data) {
+               cmdat |= JZ_MMC_CMDAT_DATA_EN;
+               if (cmd->data->flags & MMC_DATA_WRITE)
+                       cmdat |= JZ_MMC_CMDAT_WRITE;
+               if (cmd->data->flags & MMC_DATA_STREAM)
+                       cmdat |= JZ_MMC_CMDAT_STREAM;
+
+               writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN);
+               writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB);
+       }
+
+       writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD);
+       writel(cmd->arg, host->base + JZ_REG_MMC_ARG);
+       writel(cmdat, host->base + JZ_REG_MMC_CMDAT);
+
+       host->waiting = 1;
+       jz4740_mmc_clock_enable(host, 1);
+       mod_timer(&host->timeout_timer, 4*HZ);
+}
+
+static void jz4740_mmc_cmd_done(struct jz4740_mmc_host *host)
+{
+       uint32_t status;
+       struct mmc_command *cmd = host->req->cmd;
+       struct mmc_request *req = host->req;
+       status = readl(host->base + JZ_REG_MMC_STATUS);
+
+       if (cmd->flags & MMC_RSP_PRESENT)
+               jz4740_mmc_read_response(host, cmd);
+
+       if (cmd->data) {
+               if (cmd->data->flags & MMC_DATA_READ)
+                       jz4740_mmc_read_data(host, cmd->data);
+               else
+                       jz4740_mmc_write_data(host, cmd->data);
+       }
+
+       if (req->stop) {
+               jz4740_mmc_send_command(host, req->stop);
+               do {
+                       status = readl(host->base + JZ_REG_MMC_STATUS);
+               } while ((status & JZ_MMC_STATUS_PRG_DONE) == 0);
+               writew(JZ_MMC_IRQ_PRG_DONE, host->base + JZ_REG_MMC_IREG);
+       }
+
+       jz4740_mmc_request_done(host);
+}
+
+static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
+{
+       struct jz4740_mmc_host *host = mmc_priv(mmc);
+
+       host->req = req;
+
+       writew(0xffff, host->base + JZ_REG_MMC_IREG);
+
+       writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG);
+       jz4740_mmc_enable_irq(host, JZ_MMC_IRQ_END_CMD_RES);
+       jz4740_mmc_send_command(host, req->cmd);
+}
+
+
+static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+       struct jz4740_mmc_host *host = mmc_priv(mmc);
+       if (ios->clock)
+               jz4740_mmc_set_clock_rate(host, ios->clock);
+
+       switch(ios->power_mode) {
+       case MMC_POWER_UP:
+               if (gpio_is_valid(host->pdata->gpio_power))
+                       gpio_set_value(host->pdata->gpio_power,
+                                       !host->pdata->power_active_low);
+               host->cmdat |= JZ_MMC_CMDAT_INIT;
+               clk_enable(host->clk);
+               break;
+       case MMC_POWER_ON:
+               break;
+       default:
+               if (gpio_is_valid(host->pdata->gpio_power))
+                       gpio_set_value(host->pdata->gpio_power,
+                                       host->pdata->power_active_low);
+               clk_disable(host->clk);
+               break;
+       }
+
+       switch(ios->bus_width) {
+       case MMC_BUS_WIDTH_1:
+               host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
+               break;
+       case MMC_BUS_WIDTH_4:
+               host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
+               break;
+       default:
+               dev_err(&host->pdev->dev, "Invalid bus width: %d\n", ios->bus_width);
+       }
+}
+
+static int jz4740_mmc_get_ro(struct mmc_host *mmc)
+{
+       struct jz4740_mmc_host *host = mmc_priv(mmc);
+       if (!gpio_is_valid(host->pdata->gpio_read_only))
+               return -ENOSYS;
+
+       return gpio_get_value(host->pdata->gpio_read_only) ^
+               host->pdata->read_only_active_low;
+}
+
+static int jz4740_mmc_get_cd(struct mmc_host *mmc)
+{
+       struct jz4740_mmc_host *host = mmc_priv(mmc);
+       if (!gpio_is_valid(host->pdata->gpio_card_detect))
+               return -ENOSYS;
+
+       return gpio_get_value(host->pdata->gpio_card_detect) ^
+                       host->pdata->card_detect_active_low;
+}
+
+static irqreturn_t jz4740_mmc_card_detect_irq(int irq, void *devid)
+{
+       struct jz4740_mmc_host *host = devid;
+
+       mmc_detect_change(host->mmc, HZ / 3);
+
+       return IRQ_HANDLED;
+}
+
+static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
+{
+       struct jz4740_mmc_host *host = mmc_priv(mmc);
+       if (enable)
+               jz4740_mmc_enable_irq(host, JZ_MMC_IRQ_SDIO);
+       else
+               jz4740_mmc_disable_irq(host, JZ_MMC_IRQ_SDIO);
+}
+
+static const struct mmc_host_ops jz4740_mmc_ops = {
+       .request        = jz4740_mmc_request,
+       .set_ios        = jz4740_mmc_set_ios,
+       .get_ro         = jz4740_mmc_get_ro,
+       .get_cd         = jz4740_mmc_get_cd,
+       .enable_sdio_irq = jz4740_mmc_enable_sdio_irq,
+};
+
+static const struct jz_gpio_bulk_request jz4740_mmc_pins[] = {
+       JZ_GPIO_BULK_PIN(MSC_CMD),
+       JZ_GPIO_BULK_PIN(MSC_CLK),
+       JZ_GPIO_BULK_PIN(MSC_DATA0),
+       JZ_GPIO_BULK_PIN(MSC_DATA1),
+       JZ_GPIO_BULK_PIN(MSC_DATA2),
+       JZ_GPIO_BULK_PIN(MSC_DATA3),
+};
+
+static int __devinit jz4740_mmc_request_gpios(struct platform_device *pdev)
+{
+       int ret;
+       struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
+
+       if (!pdata)
+               return 0;
+
+       if (gpio_is_valid(pdata->gpio_card_detect)) {
+               ret = gpio_request(pdata->gpio_card_detect, "MMC detect change");
+               if (ret) {
+                       dev_err(&pdev->dev, "Failed to request detect change gpio\n");
+                       goto err;
+               }
+               gpio_direction_input(pdata->gpio_card_detect);
+       }
+
+       if (gpio_is_valid(pdata->gpio_read_only)) {
+               ret = gpio_request(pdata->gpio_read_only, "MMC read only");
+               if (ret) {
+                       dev_err(&pdev->dev, "Failed to request read only gpio: %d\n", ret);
+                       goto err_free_gpio_card_detect;
+               }
+               gpio_direction_input(pdata->gpio_read_only);
+       }
+
+       if (gpio_is_valid(pdata->gpio_power)) {
+               ret = gpio_request(pdata->gpio_power, "MMC power");
+               if (ret) {
+                       dev_err(&pdev->dev, "Failed to request power gpio: %d\n", ret);
+                       goto err_free_gpio_read_only;
+               }
+               gpio_direction_output(pdata->gpio_power, pdata->power_active_low);
+       }
+
+       return 0;
+
+err_free_gpio_read_only:
+       if (gpio_is_valid(pdata->gpio_read_only))
+               gpio_free(pdata->gpio_read_only);
+err_free_gpio_card_detect:
+       if (gpio_is_valid(pdata->gpio_card_detect))
+               gpio_free(pdata->gpio_card_detect);
+err:
+       return ret;
+}
+
+static void jz4740_mmc_free_gpios(struct platform_device *pdev)
+{
+       struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
+
+       if (!pdata)
+               return;
+
+       if (gpio_is_valid(pdata->gpio_power))
+               gpio_free(pdata->gpio_power);
+       if (gpio_is_valid(pdata->gpio_read_only))
+               gpio_free(pdata->gpio_read_only);
+       if (gpio_is_valid(pdata->gpio_card_detect))
+               gpio_free(pdata->gpio_card_detect);
+}
+
+static int __devinit jz4740_mmc_probe(struct platform_device* pdev)
+{
+       int ret;
+       struct mmc_host *mmc;
+       struct jz4740_mmc_host *host;
+       struct jz4740_mmc_platform_data *pdata;
+
+       pdata = pdev->dev.platform_data;
+
+       mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev);
+
+       if (!mmc) {
+               dev_err(&pdev->dev, "Failed to alloc mmc host structure\n");
+               return -ENOMEM;
+       }
+
+       host = mmc_priv(mmc);
+
+       host->irq = platform_get_irq(pdev, 0);
+
+       if (host->irq < 0) {
+               ret = host->irq;
+               dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
+               goto err_free_host;
+       }
+
+       host->clk = clk_get(&pdev->dev, "mmc");
+       if (!host->clk) {
+               ret = -ENOENT;
+               dev_err(&pdev->dev, "Failed to get mmc clock\n");
+               goto err_free_host;
+       }
+
+       host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+       if (!host->mem) {
+               ret = -ENOENT;
+               dev_err(&pdev->dev, "Failed to get base platform memory\n");
+               goto err_clk_put;
+       }
+
+       host->mem = request_mem_region(host->mem->start, resource_size(host->mem),
+                                       pdev->name);
+
+       if (!host->mem) {
+               ret = -EBUSY;
+               dev_err(&pdev->dev, "Failed to request base memory region\n");
+               goto err_clk_put;
+       }
+
+       host->base = ioremap_nocache(host->mem->start, resource_size(host->mem));
+
+       if (!host->base) {
+               ret = -EBUSY;
+               dev_err(&pdev->dev, "Failed to ioremap base memory\n");
+               goto err_release_mem_region;
+       }
+
+       if (pdata && pdata->data_1bit)
+               ret = jz_gpio_bulk_request(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
+       else
+               ret = jz_gpio_bulk_request(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
+
+       if (ret) {
+               dev_err(&pdev->dev, "Failed to request function pins: %d\n", ret);
+               goto err_iounmap;
+       }
+
+       ret = jz4740_mmc_request_gpios(pdev);
+       if (ret)
+               goto err_gpio_bulk_free;
+
+       mmc->ops = &jz4740_mmc_ops;
+       mmc->f_min = JZ_MMC_CLK_RATE / 128;
+       mmc->f_max = JZ_MMC_CLK_RATE;
+       mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
+       mmc->caps = (pdata && pdata->data_1bit) ? 0 : MMC_CAP_4_BIT_DATA;
+       mmc->caps |= MMC_CAP_SDIO_IRQ;
+       mmc->max_seg_size = 4096;
+       mmc->max_phys_segs = 128;
+
+       mmc->max_blk_size = (1 << 10) - 1;
+       mmc->max_blk_count = (1 << 15) - 1;
+       mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
+
+       host->mmc = mmc;
+       host->pdev = pdev;
+       host->pdata = pdata;
+       host->max_clock = JZ_MMC_CLK_RATE;
+       spin_lock_init(&host->lock);
+       host->irq_mask = 0xffff;
+
+       host->card_detect_irq = gpio_to_irq(pdata->gpio_card_detect);
+
+       if (host->card_detect_irq < 0) {
+               dev_warn(&pdev->dev, "Failed to get irq for card detect gpio\n");
+       } else {
+               ret = request_irq(host->card_detect_irq,
+                               jz4740_mmc_card_detect_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "MMC/SD detect changed", host);
+
+               if (ret) {
+                       dev_err(&pdev->dev, "Failed to request card detect irq");
+                       goto err_free_gpios;
+               }
+       }
+
+       ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, IRQF_DISABLED, "MMC/SD", host);
+       if (ret) {
+               dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
+               goto err_free_card_detect_irq;
+       }
+
+       jz4740_mmc_reset(host);
+       jz4740_mmc_clock_disable(host);
+       setup_timer(&host->timeout_timer, jz4740_mmc_timeout, (unsigned long)host);
+
+       platform_set_drvdata(pdev, host);
+       ret = mmc_add_host(mmc);
+
+       if (ret) {
+               dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret);
+               goto err_free_irq;
+       }
+       printk("JZ SD/MMC card driver registered\n");
+
+       return 0;
+
+err_free_irq:
+       free_irq(host->irq, host);
+err_free_card_detect_irq:
+       if (host->card_detect_irq >= 0)
+               free_irq(host->card_detect_irq, host);
+err_free_gpios:
+       jz4740_mmc_free_gpios(pdev);
+err_gpio_bulk_free:
+       if (pdata && pdata->data_1bit)
+               jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
+       else
+               jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
+err_iounmap:
+       iounmap(host->base);
+err_release_mem_region:
+       release_mem_region(host->mem->start, resource_size(host->mem));
+err_clk_put:
+       clk_put(host->clk);
+err_free_host:
+       platform_set_drvdata(pdev, NULL);
+       mmc_free_host(mmc);
+
+       return ret;
+}
+
+static int jz4740_mmc_remove(struct platform_device *pdev)
+{
+       struct jz4740_mmc_host *host = platform_get_drvdata(pdev);
+       struct jz4740_mmc_platform_data *pdata = host->pdata;
+
+       del_timer_sync(&host->timeout_timer);
+       jz4740_mmc_disable_irq(host, 0xff);
+       jz4740_mmc_reset(host);
+
+       mmc_remove_host(host->mmc);
+
+       free_irq(host->irq, host);
+       if (host->card_detect_irq >= 0)
+               free_irq(host->card_detect_irq, host);
+
+       jz4740_mmc_free_gpios(pdev);
+       if (pdata && pdata->data_1bit)
+               jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
+       else
+               jz_gpio_bulk_free(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
+
+       iounmap(host->base);
+       release_mem_region(host->mem->start, resource_size(host->mem));
+
+       clk_put(host->clk);
+
+       platform_set_drvdata(pdev, NULL);
+       mmc_free_host(host->mmc);
+
+       return 0;
+}
+
+#ifdef CONFIG_PM
+static int jz4740_mmc_suspend(struct device *dev)
+{
+       struct jz4740_mmc_host *host = dev_get_drvdata(dev);
+       struct jz4740_mmc_platform_data *pdata = host->pdata;
+
+       mmc_suspend_host(host->mmc, PMSG_SUSPEND);
+
+       if (pdata && pdata->data_1bit)
+               jz_gpio_bulk_suspend(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
+       else
+               jz_gpio_bulk_suspend(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
+
+       return 0;
+}
+
+static int jz4740_mmc_resume(struct device *dev)
+{
+       struct jz4740_mmc_host *host = dev_get_drvdata(dev);
+       struct jz4740_mmc_platform_data *pdata = host->pdata;
+
+       if (pdata && pdata->data_1bit)
+               jz_gpio_bulk_resume(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins) - 3);
+       else
+               jz_gpio_bulk_resume(jz4740_mmc_pins, ARRAY_SIZE(jz4740_mmc_pins));
+
+       mmc_resume_host(host->mmc);
+
+       return 0;
+}
+
+struct dev_pm_ops jz4740_mmc_pm_ops = {
+       .suspend        = jz4740_mmc_suspend,
+       .resume         = jz4740_mmc_resume,
+       .poweroff       = jz4740_mmc_suspend,
+       .restore        = jz4740_mmc_resume,
+};
+
+#define jz4740_mmc_PM_OPS (&jz4740_mmc_pm_ops)
+#else
+#define jz4740_mmc_PM_OPS NULL
+#endif
+
+static struct platform_driver jz4740_mmc_driver = {
+       .probe = jz4740_mmc_probe,
+       .remove = jz4740_mmc_remove,
+       .driver = {
+               .name = "jz4740-mmc",
+               .owner = THIS_MODULE,
+               .pm = jz4740_mmc_PM_OPS,
+       },
+};
+
+static int __init jz4740_mmc_init(void) {
+       return platform_driver_register(&jz4740_mmc_driver);
+}
+module_init(jz4740_mmc_init);
+
+static void __exit jz4740_mmc_exit(void) {
+       platform_driver_unregister(&jz4740_mmc_driver);
+}
+module_exit(jz4740_mmc_exit);
+
+MODULE_DESCRIPTION("JZ4720/JZ4740 SD/MMC controller driver");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
diff --git a/target/linux/xburst/files-2.6.32/drivers/mtd/nand/jz4740_nand.c b/target/linux/xburst/files-2.6.32/drivers/mtd/nand/jz4740_nand.c
new file mode 100644 (file)
index 0000000..d1e3818
--- /dev/null
@@ -0,0 +1,418 @@
+/*
+ *  Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
+ *     JZ4720/JZ4740 SoC NAND controller driver
+ *
+ *  This program is free software; you can redistribute         it and/or modify it
+ *  under  the terms of         the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+
+#include <linux/mtd/jz4740_nand.h>
+#include <linux/gpio.h>
+
+#define JZ_REG_NAND_CTRL       0x50
+#define JZ_REG_NAND_ECC_CTRL   0x100
+#define JZ_REG_NAND_DATA       0x104
+#define JZ_REG_NAND_PAR0       0x108
+#define JZ_REG_NAND_PAR1       0x10C
+#define JZ_REG_NAND_PAR2       0x110
+#define JZ_REG_NAND_IRQ_STAT   0x114
+#define JZ_REG_NAND_IRQ_CTRL   0x118
+#define JZ_REG_NAND_ERR(x)     (0x11C + (x << 2))
+
+#define JZ_NAND_ECC_CTRL_PAR_READY     BIT(4)
+#define JZ_NAND_ECC_CTRL_ENCODING      BIT(3)
+#define JZ_NAND_ECC_CTRL_RS            BIT(2)
+#define JZ_NAND_ECC_CTRL_RESET         BIT(1)
+#define JZ_NAND_ECC_CTRL_ENABLE                BIT(0)
+
+#define JZ_NAND_STATUS_ERR_COUNT       (BIT(31) | BIT(30) | BIT(29))
+#define JZ_NAND_STATUS_PAD_FINISH      BIT(4)
+#define JZ_NAND_STATUS_DEC_FINISH      BIT(3)
+#define JZ_NAND_STATUS_ENC_FINISH      BIT(2)
+#define JZ_NAND_STATUS_UNCOR_ERROR     BIT(1)
+#define JZ_NAND_STATUS_ERROR           BIT(0)
+
+#define JZ_NAND_CTRL_ENABLE_CHIP(x) BIT(x << 1)
+#define JZ_NAND_CTRL_ASSERT_CHIP(x) BIT((x << 1) + 1)
+
+#define JZ_NAND_DATA_ADDR ((void __iomem *)0xB8000000)
+#define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
+#define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000)
+
+struct jz_nand {
+       struct mtd_info mtd;
+       struct nand_chip chip;
+       void __iomem *base;
+       struct resource *mem;
+
+       struct jz_nand_platform_data *pdata;
+};
+
+static inline struct jz_nand *mtd_to_jz_nand(struct mtd_info *mtd)
+{
+       return container_of(mtd, struct jz_nand, mtd);
+}
+
+static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
+{
+       struct jz_nand *nand = mtd_to_jz_nand(mtd);
+       struct nand_chip *chip = mtd->priv;
+       uint32_t reg;
+
+       if (ctrl & NAND_CTRL_CHANGE) {
+               BUG_ON((ctrl & NAND_ALE) && (ctrl & NAND_CLE));
+               if (ctrl & NAND_ALE)
+                       chip->IO_ADDR_W = JZ_NAND_ADDR_ADDR;
+               else if (ctrl & NAND_CLE)
+                       chip->IO_ADDR_W = JZ_NAND_CMD_ADDR;
+               else
+                       chip->IO_ADDR_W = JZ_NAND_DATA_ADDR;
+
+               reg = readl(nand->base + JZ_REG_NAND_CTRL);
+               if ( ctrl & NAND_NCE )
+                       reg |= JZ_NAND_CTRL_ASSERT_CHIP(0);
+               else
+                       reg &= ~JZ_NAND_CTRL_ASSERT_CHIP(0);
+               writel(reg, nand->base + JZ_REG_NAND_CTRL);
+       }
+       if (dat != NAND_CMD_NONE)
+               writeb(dat, chip->IO_ADDR_W);
+}
+
+static int jz_nand_dev_ready(struct mtd_info *mtd)
+{
+       struct jz_nand *nand = mtd_to_jz_nand(mtd);
+       return gpio_get_value_cansleep(nand->pdata->busy_gpio);
+}
+
+static void jz_nand_hwctl(struct mtd_info *mtd, int mode)
+{
+       struct jz_nand *nand = mtd_to_jz_nand(mtd);
+       uint32_t reg;
+
+
+       writel(0, nand->base + JZ_REG_NAND_IRQ_STAT);
+       reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
+
+       reg |= JZ_NAND_ECC_CTRL_RESET;
+       reg |= JZ_NAND_ECC_CTRL_ENABLE;
+       reg |= JZ_NAND_ECC_CTRL_RS;
+
+       switch(mode) {
+       case NAND_ECC_READ:
+               reg &= ~JZ_NAND_ECC_CTRL_ENCODING;
+               break;
+       case NAND_ECC_WRITE:
+               reg |= JZ_NAND_ECC_CTRL_ENCODING;
+               break;
+       default:
+               break;
+       }
+
+       writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
+}
+
+static int jz_nand_calculate_ecc_rs(struct mtd_info* mtd, const uint8_t* dat,
+                                       uint8_t *ecc_code)
+{
+       struct jz_nand *nand = mtd_to_jz_nand(mtd);
+       uint32_t reg, status;
+       int i;
+
+       do {
+               status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
+       } while(!(status & JZ_NAND_STATUS_ENC_FINISH));
+
+       reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
+       reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
+       writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
+
+       for (i = 0; i < 9; ++i) {
+               ecc_code[i] = readb(nand->base + JZ_REG_NAND_PAR0 + i);
+       }
+
+       return 0;
+}
+
+static void correct_data(uint8_t *dat, int index, int mask)
+{
+       int offset = index & 0x7;
+       uint16_t data;
+       printk("correct: ");
+
+       index += (index >> 3);
+
+       data = dat[index];
+       data |= dat[index+1] << 8;
+
+       printk("0x%x -> ", data);
+
+       mask ^= (data >> offset) & 0x1ff;
+       data &= ~(0x1ff << offset);
+       data |= (mask << offset);
+
+       printk("0x%x\n", data);
+
+       dat[index] = data & 0xff;
+       dat[index+1] = (data >> 8) & 0xff;
+}
+
+static int jz_nand_correct_ecc_rs(struct mtd_info* mtd, uint8_t *dat,
+                                 uint8_t *read_ecc, uint8_t *calc_ecc)
+{
+       struct jz_nand *nand = mtd_to_jz_nand(mtd);
+       int i, error_count, index;
+       uint32_t reg, status, error;
+
+       for(i = 0; i < 9; ++i) {
+               if (read_ecc[i] != 0xff)
+                       break;
+       }
+       if (i == 9) {
+               for (i = 0; i < nand->chip.ecc.size; ++i) {
+                       if (dat[i] != 0xff)
+                               break;
+               }
+               if (i == nand->chip.ecc.size)
+                       return 0;
+       }
+
+       for(i = 0; i < 9; ++i)
+               writeb(read_ecc[i], nand->base + JZ_REG_NAND_PAR0 + i);
+
+       reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
+       reg |= JZ_NAND_ECC_CTRL_PAR_READY;
+       writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
+
+       do {
+               status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
+       } while (!(status & JZ_NAND_STATUS_DEC_FINISH));
+
+       reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
+       reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
+       writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
+
+       if (status & JZ_NAND_STATUS_ERROR) {
+               if (status & JZ_NAND_STATUS_UNCOR_ERROR) {
+                       printk("uncorrectable ecc:");
+                       for(i = 0; i < 9; ++i)
+                               printk(" 0x%x", read_ecc[i]);
+                       printk("\n");
+                       printk("uncorrectable data:");
+                       for(i = 0; i < 32; ++i)
+                               printk(" 0x%x", dat[i]);
+                       printk("\n");
+                       return -1;
+               }
+
+               error_count = (status & JZ_NAND_STATUS_ERR_COUNT) >> 29;
+
+               printk("error_count: %d %x\n", error_count, status);
+
+               for(i = 0; i < error_count; ++i) {
+                       error = readl(nand->base + JZ_REG_NAND_ERR(i));
+                       index = ((error >> 16) & 0x1ff) - 1;
+                       if (index >= 0 && index < 512) {
+                               correct_data(dat, index, error & 0x1ff);
+                       }
+               }
+
+               return error_count;
+       }
+
+       return 0;
+}
+
+
+
+#ifdef CONFIG_MTD_CMDLINE_PARTS
+static const char *part_probes[] = {"cmdline", NULL};
+#endif
+
+static int __devinit jz_nand_probe(struct platform_device *pdev)
+{
+       int ret;
+       struct jz_nand *nand;
+       struct nand_chip *chip;
+       struct mtd_info *mtd;
+       struct jz_nand_platform_data *pdata = pdev->dev.platform_data;
+#ifdef CONFIG_MTD_PARTITIONS
+       struct mtd_partition *partition_info;
+       int num_partitions = 0;
+#endif
+
+       nand = kzalloc(sizeof(*nand), GFP_KERNEL);
+       if (!nand) {
+               dev_err(&pdev->dev, "Failed to allocate device structure.\n");
+               return -ENOMEM;
+       }
+
+       nand->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       if (!nand->mem) {
+               dev_err(&pdev->dev, "Failed to get platform mmio memory\n");
+               ret = -ENOENT;
+               goto err_free;
+       }
+
+       nand->mem = request_mem_region(nand->mem->start, resource_size(nand->mem),
+                                       pdev->name);
+
+       if (!nand->mem) {
+               dev_err(&pdev->dev, "Failed to request mmio memory region\n");
+               ret = -EBUSY;
+               goto err_free;
+       }
+
+       nand->base = ioremap(nand->mem->start, resource_size(nand->mem));
+
+       if (!nand->base) {
+               dev_err(&pdev->dev, "Faild to ioremap mmio memory region\n");
+               ret = -EBUSY;
+               goto err_release_mem;
+       }
+
+       if (pdata && gpio_is_valid(pdata->busy_gpio)) {
+               ret = gpio_request(pdata->busy_gpio, "jz nand busy line");
+               if (ret) {
+                       dev_err(&pdev->dev, "Failed to request busy gpio %d: %d\n",
+                                       pdata->busy_gpio, ret);
+                       goto err_iounmap;
+               }
+       }
+
+       mtd             = &nand->mtd;
+       chip            = &nand->chip;
+       mtd->priv       = chip;
+       mtd->owner      = THIS_MODULE;
+       mtd->name       = "jz4740-nand";
+
+       chip->ecc.hwctl         = jz_nand_hwctl;
+
+       chip->ecc.calculate     = jz_nand_calculate_ecc_rs;
+       chip->ecc.correct       = jz_nand_correct_ecc_rs;
+       chip->ecc.mode          = NAND_ECC_HW;
+       chip->ecc.size          = 512;
+       chip->ecc.bytes         = 9;
+       if (pdata)
+               chip->ecc.layout = pdata->ecc_layout;
+
+       chip->chip_delay = 50;
+       chip->cmd_ctrl = jz_nand_cmd_ctrl;
+
+       if (pdata && gpio_is_valid(pdata->busy_gpio))
+               chip->dev_ready = jz_nand_dev_ready;
+
+       chip->IO_ADDR_R = JZ_NAND_DATA_ADDR;
+       chip->IO_ADDR_W = JZ_NAND_DATA_ADDR;
+
+       nand->pdata = pdata;
+       platform_set_drvdata(pdev, nand);
+
+       ret = nand_scan_ident(mtd, 1);
+       if (ret) {
+               dev_err(&pdev->dev,  "Failed to scan nand\n");
+               goto err_gpio_free;
+       }
+
+       if (pdata && pdata->ident_callback) {
+               pdata->ident_callback(pdev, chip, &pdata->partitions, &pdata->num_partitions);
+       }
+
+       ret = nand_scan_tail(mtd);
+       if (ret) {
+               dev_err(&pdev->dev,  "Failed to scan nand\n");
+               goto err_gpio_free;
+       }
+
+#ifdef CONFIG_MTD_PARTITIONS
+#ifdef CONFIG_MTD_CMDLINE_PARTS
+       num_partitions = parse_mtd_partitions(mtd, part_probes,
+                                               &partition_info, 0);
+#endif
+       if (num_partitions <= 0 && pdata) {
+               num_partitions = pdata->num_partitions;
+               partition_info = pdata->partitions;
+       }
+
+       if (num_partitions > 0)
+               ret = add_mtd_partitions(mtd, partition_info, num_partitions);
+       else
+#endif
+       ret = add_mtd_device(mtd);
+
+       if (ret) {
+               dev_err(&pdev->dev, "Failed to add mtd device\n");
+               goto err_nand_release;
+       }
+
+       dev_info(&pdev->dev, "Successfully registered JZ4740 NAND driver\n");
+
+       return 0;
+err_nand_release:
+       nand_release(&nand->mtd);
+err_gpio_free:
+       platform_set_drvdata(pdev, NULL);
+       gpio_free(pdata->busy_gpio);
+err_iounmap:
+       iounmap(nand->base);
+err_release_mem:
+       release_mem_region(nand->mem->start, resource_size(nand->mem));
+err_free:
+       kfree(nand);
+       return ret;
+}
+
+static void __devexit jz_nand_remove(struct platform_device *pdev)
+{
+       struct jz_nand *nand = platform_get_drvdata(pdev);
+
+       nand_release(&nand->mtd);
+
+       iounmap(nand->base);
+
+       release_mem_region(nand->mem->start, resource_size(nand->mem));
+
+       platform_set_drvdata(pdev, NULL);
+       kfree(nand);
+}
+
+struct platform_driver jz_nand_driver = {
+       .probe = jz_nand_probe,
+       .remove = __devexit_p(jz_nand_probe),
+       .driver = {
+               .name = "jz4740-nand",
+               .owner = THIS_MODULE,
+       },
+};
+
+static int __init jz_nand_init(void)
+{
+       return platform_driver_register(&jz_nand_driver);
+}
+module_init(jz_nand_init);
+
+static void __exit jz_nand_exit(void)
+{
+       platform_driver_unregister(&jz_nand_driver);
+}
+module_exit(jz_nand_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
+MODULE_DESCRIPTION("NAND controller driver for JZ4720/JZ4740 SoC");
+MODULE_ALIAS("platform:jz4740-nand");
+MODULE_ALIAS("platform:jz4720-nand");
diff --git a/target/linux/xburst/files-2.6.32/drivers/power/jz4740-battery.c b/target/linux/xburst/files-2.6.32/drivers/power/jz4740-battery.c
new file mode 100644 (file)
index 0000000..fe03d80
--- /dev/null
@@ -0,0 +1,471 @@
+/*
+ * Battery measurement code for Ingenic JZ SOC.
+ *
+ * based on tosa_battery.c
+ *
+ * Copyright (C) 2008 Marek Vasut <marek.vasut@gmail.com>
+ * Copyright (C) 2009 Jiejing Zhang <kzjeef@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/power_supply.h>
+#include <linux/delay.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+
+#include <linux/power/jz4740-battery.h>
+#include <linux/jz4740-adc.h>
+
+struct jz_battery_info {
+       struct power_supply usb;
+       struct power_supply bat;
+       struct power_supply ac;
+       int bat_status;
+       struct jz_batt_info *pdata;
+       struct mutex work_lock;
+       struct workqueue_struct *monitor_wqueue;
+       struct delayed_work bat_work;
+};
+
+#define ps_to_jz_battery(x) container_of((x), struct jz_battery_info, bat);
+
+/*********************************************************************
+ *             Power
+ *********************************************************************/
+
+
+static int jz_get_power_prop(struct jz_battery_info *bat_info,
+                            struct power_supply *psy,
+                            enum power_supply_property psp,
+                            union power_supply_propval *val)
+{
+       int gpio;
+       
+       if (bat_info == 0 || bat_info->pdata == 0)
+               return -EINVAL;
+       gpio = (psy->type == POWER_SUPPLY_TYPE_MAINS) ?
+               bat_info->pdata->dc_dect_gpio :
+               bat_info->pdata->usb_dect_gpio;
+       if (!gpio_is_valid(gpio))
+               return -EINVAL;
+       switch (psp) {
+       case POWER_SUPPLY_PROP_ONLINE:
+               val->intval = !gpio_get_value(gpio);
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+static int jz_usb_get_power_prop(struct power_supply *psy,
+                                enum power_supply_property psp,
+                                union power_supply_propval *val)
+{
+       struct jz_battery_info *bat_info = container_of(psy, struct jz_battery_info, usb);
+       return jz_get_power_prop(bat_info, psy, psp, val);
+}
+
+static int jz_ac_get_power_prop(struct power_supply *psy,
+                                enum power_supply_property psp,
+                                union power_supply_propval *val)
+{
+       struct jz_battery_info *bat_info = container_of(psy, struct jz_battery_info, ac);
+       return jz_get_power_prop(bat_info, psy, psp, val);
+}
+
+
+static enum power_supply_property jz_power_props[] = {
+       POWER_SUPPLY_PROP_ONLINE,
+};
+
+static struct power_supply jz_ac = {
+       .name = "ac",
+       .type = POWER_SUPPLY_TYPE_MAINS,
+       .properties = jz_power_props,
+       .num_properties = ARRAY_SIZE(jz_power_props),
+       .get_property = jz_ac_get_power_prop,
+};
+
+static struct power_supply jz_usb = {
+       .name = "usb",
+       .type = POWER_SUPPLY_TYPE_USB,
+       .properties = jz_power_props,
+       .num_properties = ARRAY_SIZE(jz_power_props),
+       .get_property = jz_usb_get_power_prop,
+};
+
+
+/*********************************************************************
+ *             Battery properties
+ *********************************************************************/
+
+static long jz_read_bat(struct power_supply *psy)
+{
+       struct jz_battery_info *bat_info = ps_to_jz_battery(psy);
+       enum jz_adc_battery_scale scale;
+
+       if (bat_info->pdata->max_voltag > 2500000)
+               scale = JZ_ADC_BATTERY_SCALE_7V5;
+       else
+               scale = JZ_ADC_BATTERY_SCALE_2V5;
+
+       return jz4740_adc_read_battery_voltage(psy->dev->parent->parent, scale);
+}
+
+static int jz_bat_get_capacity(struct power_supply *psy)
+{
+       int ret;
+       struct jz_battery_info *bat_info = ps_to_jz_battery(psy);
+
+       ret = jz_read_bat(psy);
+
+       if (ret < 0)
+               return ret;
+
+       ret = (ret - bat_info->pdata->min_voltag) * 100
+               / (bat_info->pdata->max_voltag - bat_info->pdata->min_voltag);
+
+       if (ret > 100)
+               ret = 100;
+       else if (ret < 0)
+               ret = 0;
+
+       return ret;
+}
+
+static int jz_bat_get_property(struct power_supply *psy,
+                               enum power_supply_property psp,
+                               union power_supply_propval *val)
+{
+       struct jz_battery_info *bat_info = ps_to_jz_battery(psy)
+       
+       switch (psp) {
+       case POWER_SUPPLY_PROP_STATUS:
+               val->intval = bat_info->bat_status;
+               break;
+       case POWER_SUPPLY_PROP_TECHNOLOGY:
+               val->intval = bat_info->pdata->batt_tech;
+               break;
+       case POWER_SUPPLY_PROP_HEALTH:
+               if(jz_read_bat(psy) < bat_info->pdata->min_voltag) {
+                       dev_dbg(psy->dev, "%s: battery is dead,"
+                               "voltage too low!\n", __func__);
+                       val->intval = POWER_SUPPLY_HEALTH_DEAD;
+               } else {
+                       dev_dbg(psy->dev, "%s: battery is good,"
+                               "voltage normal.\n", __func__);
+                       val->intval = POWER_SUPPLY_HEALTH_GOOD;
+               }
+               break;
+       case POWER_SUPPLY_PROP_CAPACITY:
+               val->intval = jz_bat_get_capacity(psy);
+               dev_dbg(psy->dev, "%s: battery_capacity = %d\n",
+                       __func__, val->intval);
+               break;
+       case POWER_SUPPLY_PROP_VOLTAGE_NOW:
+               val->intval = jz_read_bat(psy);
+               if (val->intval < 0)
+                       return val->intval;
+               break;
+       case POWER_SUPPLY_PROP_VOLTAGE_MAX:
+       case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN:
+               val->intval = bat_info->pdata->max_voltag;
+               break;
+       case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN:
+               val->intval = bat_info->pdata->min_voltag;
+               break;
+       case POWER_SUPPLY_PROP_PRESENT:
+               val->intval = 1;
+               break;
+       default:
+               return -EINVAL;
+       }
+       return 0;
+}
+
+static void jz_bat_external_power_changed(struct power_supply *psy)
+{
+       struct jz_battery_info *bat_info = ps_to_jz_battery(psy);
+       
+       cancel_delayed_work(&bat_info->bat_work);
+       queue_delayed_work(bat_info->monitor_wqueue, &bat_info->bat_work, HZ / 8);
+}
+
+static char *status_text[] = {
+       [POWER_SUPPLY_STATUS_UNKNOWN] =         "Unknown",
+       [POWER_SUPPLY_STATUS_CHARGING] =        "Charging",
+       [POWER_SUPPLY_STATUS_DISCHARGING] =     "Discharging",
+       [POWER_SUPPLY_STATUS_NOT_CHARGING] =    "Not charging",
+};
+
+static void jz_bat_update(struct power_supply *psy)
+{
+       struct jz_battery_info *bat_info = ps_to_jz_battery(psy);
+               
+       int old_status = bat_info->bat_status;
+       static unsigned long old_batt_vol = 0;
+       unsigned long batt_vol = jz_read_bat(psy);
+       
+       mutex_lock(&bat_info->work_lock);
+
+       if (gpio_is_valid(bat_info->pdata->charg_stat_gpio)) {
+               if(!gpio_get_value(bat_info->pdata->charg_stat_gpio))
+                       bat_info->bat_status = POWER_SUPPLY_STATUS_CHARGING;
+               else
+                       bat_info->bat_status = POWER_SUPPLY_STATUS_NOT_CHARGING;
+               dev_dbg(psy->dev, "%s: battery status=%s\n",
+                       __func__, status_text[bat_info->bat_status]);
+               
+               if (old_status != bat_info->bat_status) {
+                       dev_dbg(psy->dev, "%s %s -> %s\n",
+                               psy->name,
+                               status_text[old_status],
+                               status_text[bat_info->bat_status]);
+
+                       power_supply_changed(psy);
+               }
+       }
+
+       if (old_batt_vol - batt_vol > 50000) {
+               dev_dbg(psy->dev, "voltage change : %ld -> %ld\n",
+                       old_batt_vol, batt_vol);
+               power_supply_changed(psy);
+               old_batt_vol = batt_vol;
+       }
+
+       mutex_unlock(&bat_info->work_lock);
+}
+
+static enum power_supply_property jz_bat_main_props[] = {
+       POWER_SUPPLY_PROP_STATUS,
+       POWER_SUPPLY_PROP_TECHNOLOGY,
+       POWER_SUPPLY_PROP_HEALTH,
+       POWER_SUPPLY_PROP_CAPACITY, /* in percents! */
+       POWER_SUPPLY_PROP_VOLTAGE_NOW,
+       POWER_SUPPLY_PROP_VOLTAGE_MAX,
+       POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN,
+       POWER_SUPPLY_PROP_PRESENT,
+};
+
+struct power_supply bat_ps = {
+       .name                   = "battery",
+       .type                   = POWER_SUPPLY_TYPE_BATTERY,
+       .properties             = jz_bat_main_props,
+       .num_properties         = ARRAY_SIZE(jz_bat_main_props),
+       .get_property           = jz_bat_get_property,
+       .external_power_changed = jz_bat_external_power_changed,
+       .use_for_apm            = 1,
+};
+
+static void jz_bat_work(struct work_struct *work)
+{
+       /* query interval too small will increase system workload*/
+       const int interval = HZ * 30;
+       struct jz_battery_info *bat_info = container_of(work,struct jz_battery_info, bat_work.work);
+
+       jz_bat_update(&bat_info->bat);
+       queue_delayed_work(bat_info->monitor_wqueue,
+                          &bat_info->bat_work, interval);
+}
+
+#ifdef CONFIG_PM
+static int jz_bat_suspend(struct platform_device *pdev, pm_message_t state)
+{
+       struct jz_battery_info *bat_info = platform_get_drvdata(pdev);
+       
+       bat_info->bat_status =  POWER_SUPPLY_STATUS_UNKNOWN;
+
+       return 0;
+}
+
+static int jz_bat_resume(struct platform_device *pdev)
+{
+       struct jz_battery_info *bat_info = platform_get_drvdata(pdev);
+
+       bat_info->bat_status =  POWER_SUPPLY_STATUS_UNKNOWN;
+
+       cancel_delayed_work(&bat_info->bat_work);
+       queue_delayed_work(bat_info->monitor_wqueue, &bat_info->bat_work, HZ/10);
+
+       return 0;
+}
+#else
+#define jz_bat_suspend NULL
+#define jz_bat_resume NULL
+#endif
+
+static int jz_bat_probe(struct platform_device *pdev)
+{
+       int ret = 0;
+       struct jz_battery_info *bat_info;
+       
+       bat_info = kzalloc(sizeof(struct jz_battery_info), GFP_KERNEL);
+
+       if (!bat_info) {
+               return -ENOMEM;
+       }
+
+       if (!pdev->dev.platform_data) {
+               dev_err(&pdev->dev, "Please set battery info\n");
+               ret = -EINVAL;
+               goto err_platform_data;
+       }
+       platform_set_drvdata(pdev, bat_info);
+       bat_info->pdata = pdev->dev.platform_data;
+       bat_info->bat = bat_ps;
+       bat_info->usb = jz_usb;
+       bat_info->ac =  jz_ac;
+       mutex_init(&bat_info->work_lock);
+       INIT_DELAYED_WORK(&bat_info->bat_work, jz_bat_work);
+
+       if (gpio_is_valid(bat_info->pdata->dc_dect_gpio)) {
+               ret = gpio_request(bat_info->pdata->dc_dect_gpio, "AC/DC DECT");
+               if (ret) {
+                       dev_err(&pdev->dev, "ac/dc dect gpio request failed.\n");
+
+                       goto err_dc_gpio_request;
+               }
+               ret = gpio_direction_input(bat_info->pdata->dc_dect_gpio);
+               if (ret) {
+                       dev_err(&pdev->dev, "ac/dc dect gpio direction failed.\n");
+
+                       goto err_dc_gpio_direction;
+               }
+       }
+
+       if (gpio_is_valid(bat_info->pdata->usb_dect_gpio)) {
+               ret = gpio_request(bat_info->pdata->usb_dect_gpio, "USB DECT");
+               if (ret) {
+                       dev_err(&pdev->dev, "usb dect gpio request failed.\n");
+
+                       goto err_usb_gpio_request;
+               }
+               ret = gpio_direction_input(bat_info->pdata->usb_dect_gpio);
+               if (ret) {
+                       dev_err(&pdev->dev, "usb dect gpio set direction failed.\n");
+                       goto err_usb_gpio_direction;
+               }
+
+               jz_gpio_disable_pullup(bat_info->pdata->usb_dect_gpio);
+               /* TODO: Use generic gpio is better */
+       }
+
+       if (gpio_is_valid(bat_info->pdata->charg_stat_gpio)) {
+               ret = gpio_request(bat_info->pdata->charg_stat_gpio, "CHARG STAT");
+               if (ret) {
+                       dev_err(&pdev->dev, "charger state gpio request failed.\n");
+                       goto err_charg_gpio_request;
+               }
+               ret = gpio_direction_input(bat_info->pdata->charg_stat_gpio);
+               if (ret) {
+                       dev_err(&pdev->dev, "charger state gpio set direction failed.\n");
+                       goto err_charg_gpio_direction;
+               }
+       }
+       
+       if (gpio_is_valid(bat_info->pdata->dc_dect_gpio)) {
+               ret = power_supply_register(&pdev->dev, &bat_info->ac);
+               if (ret) {
+                       dev_err(&pdev->dev, "power supply ac/dc register failed.\n");
+                       goto err_power_register_ac;
+               }
+       }
+
+       if (gpio_is_valid(bat_info->pdata->usb_dect_gpio)) {
+               ret = power_supply_register(&pdev->dev, &bat_info->usb);
+               if (ret) {
+                       dev_err(&pdev->dev, "power supply usb register failed.\n");
+                       goto err_power_register_usb;
+               }
+       }
+
+       if (gpio_is_valid(bat_info->pdata->charg_stat_gpio)) {
+               ret = power_supply_register(&pdev->dev, &bat_info->bat);
+               if (ret) {
+                       dev_err(&pdev->dev, "power supply battery register failed.\n");
+                       goto err_power_register_bat;
+               } else {
+                       bat_info->monitor_wqueue = create_singlethread_workqueue("jz_battery");
+                       if (!bat_info->monitor_wqueue) {
+                               return -ESRCH;
+                       }
+                       queue_delayed_work(bat_info->monitor_wqueue, &bat_info->bat_work, HZ * 1);
+               }
+       }
+       printk(KERN_INFO "jz_bat init success.\n");
+       return ret;
+
+err_power_register_bat:
+       power_supply_unregister(&bat_info->usb);
+err_power_register_usb:
+       power_supply_unregister(&bat_info->ac);
+err_power_register_ac:
+err_charg_gpio_direction:
+       gpio_free(bat_info->pdata->charg_stat_gpio);
+err_charg_gpio_request:
+err_usb_gpio_direction:
+       gpio_free(bat_info->pdata->usb_dect_gpio);
+err_usb_gpio_request:
+err_dc_gpio_direction:
+       gpio_free(bat_info->pdata->dc_dect_gpio);
+err_dc_gpio_request:
+err_platform_data:
+       kfree(bat_info);
+       return ret;
+}
+
+static int jz_bat_remove(struct platform_device *pdev)
+{
+       struct jz_battery_info *bat_info = platform_get_drvdata(pdev);
+               
+       if (bat_info->pdata) {
+               if (gpio_is_valid(bat_info->pdata->dc_dect_gpio))
+                       gpio_free(bat_info->pdata->dc_dect_gpio);
+               if (gpio_is_valid(bat_info->pdata->usb_dect_gpio))
+                       gpio_free(bat_info->pdata->usb_dect_gpio);
+               if (gpio_is_valid(bat_info->pdata->charg_stat_gpio))
+                       gpio_free(bat_info->pdata->charg_stat_gpio);
+       }
+
+       power_supply_unregister(&bat_ps);
+       power_supply_unregister(&jz_ac);
+       power_supply_unregister(&jz_usb);
+
+       return 0;
+}
+
+static struct platform_driver jz_bat_driver = {
+       .probe          = jz_bat_probe,
+       .remove         = __devexit_p(jz_bat_remove),
+       .suspend        = jz_bat_suspend,
+       .resume