From 5f559d033941bc4ea2fb1270a49e5702cd819b6d Mon Sep 17 00:00:00 2001
From: Florian Fainelli <florian@openwrt.org>
Date: Sat, 27 Jun 2009 20:32:43 +0000
Subject: [PATCH 1/1] [brcm63xx] more fixes for bcm6338, no need not to prevent
 reads from MPI registers now that we have it defined correctly

SVN-Revision: 16589
---
 .../arch/mips/bcm63xx/boards/board_bcm963xx.c    | 16 ++++++++++------
 .../include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h  |  8 ++++----
 .../include/asm-mips/mach-bcm63xx/bcm63xx_regs.h |  7 ++++++-
 3 files changed, 20 insertions(+), 11 deletions(-)

diff --git a/target/linux/brcm63xx/files/arch/mips/bcm63xx/boards/board_bcm963xx.c b/target/linux/brcm63xx/files/arch/mips/bcm63xx/boards/board_bcm963xx.c
index c41951b988..e27264dfdf 100644
--- a/target/linux/brcm63xx/files/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/target/linux/brcm63xx/files/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -45,11 +45,11 @@ static struct board_info board;
 static struct board_info __initdata board_96338gw = {
 	.name				= "96338GW",
 	.expected_cpu_id		= 0x6338,
-
+	
 	.has_enet0			= 1,
 	.enet0 = {
-		.has_phy		= 1,
-		.use_internal_phy	= 1,
+		.force_speed_100	= 1,
+		.force_duplex_full	= 1,
 	},
 
 	.has_ohci0			= 1,
@@ -58,8 +58,12 @@ static struct board_info __initdata board_96338gw = {
 static struct board_info __initdata board_96338w = {
 	.name				= "96338W",
 	.expected_cpu_id		= 0x6338,
-
+	
 	.has_enet0			= 1,
+	.enet0 = {
+		.force_speed_100	= 1,
+		.force_duplex_full	= 1,
+	}
 };
 #endif
 
@@ -326,7 +330,7 @@ void __init board_prom_init(void)
 	/* read base address of boot chip select (0) 
 	 * 6338/6345 does not have MPI but boots from standard
 	 * MIPS Flash address */
-	if (BCMCPU_IS_6338() || BCMCPU_IS_6345())
+	if (BCMCPU_IS_6345())
 		val = 0x1fc00000;
 	else {
 		val = bcm_mpi_readl(MPI_CSBASE_REG(0));
@@ -554,7 +558,7 @@ int __init board_register_devices(void)
 #endif
 
 	/* read base address of boot chip select (0) */
-	if (BCMCPU_IS_6338() || BCMCPU_IS_6345())
+	if (BCMCPU_IS_6345())
 		val = 0x1fc0000;
 	else {
 		val = bcm_mpi_readl(MPI_CSBASE_REG(0));
diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
index 6209f47bcc..58ed2705ba 100644
--- a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
+++ b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
@@ -123,7 +123,7 @@ enum bcm63xx_regs_set {
 
 #define BCM_6338_DSL_LMEM_BASE		(0xfff00000)
 #define BCM_6338_PERF_BASE		(0xfffe0000)
-#define BCM_6338_BB_BASE		(0xdeadbeef)
+#define BCM_6338_BB_BASE		(0xfffe0100)
 #define BCM_6338_TIMER_BASE		(0xfffe0200)
 #define BCM_6338_WDT_BASE		(0xfffe021c)
 #define BCM_6338_UART0_BASE		(0xfffe0300)
@@ -132,9 +132,9 @@ enum bcm63xx_regs_set {
 #define BCM_6338_UDC0_BASE		(0xdeadbeef)
 #define BCM_6338_USBDMA_BASE		(0xfffe2400)
 #define BCM_6338_OHCI0_BASE		(0xdeadbeef)
-#define BCM_6338_OHCI_PRIV_BASE		(0xdeadbeef)
+#define BCM_6338_OHCI_PRIV_BASE		(0xfffe3000)
 #define BCM_6338_USBH_PRIV_BASE		(0xdeadbeef)
-#define BCM_6338_MPI_BASE		(0xdeadbeef)
+#define BCM_6338_MPI_BASE		(0xfffe3160)
 #define BCM_6338_PCMCIA_BASE		(0xdeadbeef)
 #define BCM_6338_SDRAM_REGS_BASE	(0xfffe3100)
 #define BCM_6338_DSL_BASE		(0xfffe1000)
@@ -142,7 +142,7 @@ enum bcm63xx_regs_set {
 #define BCM_6338_UBUS_BASE		(0xdeadbeef)
 #define BCM_6338_ENET0_BASE		(0xfffe2800)
 #define BCM_6338_ENET1_BASE		(0xdeadbeef)
-#define BCM_6338_ENETDMA_BASE		(0xfffe3800)
+#define BCM_6338_ENETDMA_BASE		(0xfffe2400)
 #define BCM_6338_EHCI0_BASE		(0xdeadbeef)
 #define BCM_6338_SDRAM_BASE		(0xfffe3100)
 #define BCM_6338_MEMC_BASE		(0xdeadbeef)
diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h
index 0b150db870..7e215a55ec 100644
--- a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h
+++ b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h
@@ -15,12 +15,17 @@
 /* Clock Control register */
 #define PERF_CKCTL_REG			0x4
 
+#define CKCTL_6338_ADSLPHY_EN		(1 << 0)
+#define CKCTL_6338_MPI_EN		(1 << 1)
+#define CKCTL_6338_DRAM_EN		(1 << 2)
 #define CKCTL_6338_ENET_EN		(1 << 4)
 #define CKCTL_6338_USBS_EN		(1 << 4)
 #define CKCTL_6338_SAR_EN		(1 << 5)
 #define CKCTL_6338_SPI_EN		(1 << 9)
 
-#define CKCTL_6338_ALL_SAFE_EN		(CKCTL_6338_ENET_EN |		\
+#define CKCTL_6338_ALL_SAFE_EN		(CKCTL_6338_ADSLPHY_EN |	\
+					CKCTL_6338_MPI_EN |		\
+					CKCTL_6338_ENET_EN |		\
 					CKCTL_6338_SAR_EN |		\
 					CKCTL_6338_SPI_EN)
 
-- 
2.30.2