diff options
| author | Markus Stockhausen | 2024-09-09 07:13:06 +0000 |
|---|---|---|
| committer | Sander Vanheule | 2024-09-14 17:58:55 +0000 |
| commit | a8bf6c25bfc5654f34271e0ef808fdeffdb845a3 (patch) | |
| tree | baa9d4e01e0bc8ebd4024b128989f2129db7ded9 | |
| parent | f86c166e0ff2f8557794cac3a71664fb41b6d48e (diff) | |
| download | openwrt-a8bf6c25bfc5654f34271e0ef808fdeffdb845a3.tar.gz | |
realtek: 6.6: copy patch drivers-net-phy-eee-support-for-rtl838x
Copy the patch file to 6.6. Reorder it in the 7xx range.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
| -rw-r--r-- | target/linux/realtek/patches-6.6/708-drivers-net-phy-eee-support-for-rtl838x.patch | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/target/linux/realtek/patches-6.6/708-drivers-net-phy-eee-support-for-rtl838x.patch b/target/linux/realtek/patches-6.6/708-drivers-net-phy-eee-support-for-rtl838x.patch new file mode 100644 index 0000000000..bf6e517cfb --- /dev/null +++ b/target/linux/realtek/patches-6.6/708-drivers-net-phy-eee-support-for-rtl838x.patch @@ -0,0 +1,61 @@ +From 2b88563ee5aafd9571d965b7f2093a0f58d98a31 Mon Sep 17 00:00:00 2001 +From: John Crispin <john@phrozen.org> +Date: Thu, 26 Nov 2020 12:02:21 +0100 +Subject: net: phy: EEE support for rtl838x + +* rename the target to realtek +* add refactored DSA driver +* add latest gpio driver +* lots of arch cleanups +* new irq driver +* additional boards + +Submitted-by: Bert Vermeulen <bert@biot.com> +Submitted-by: Birger Koblitz <mail@birger-koblitz.de> +Submitted-by: Sander Vanheule <sander@svanheule.net> +Submitted-by: Bjørn Mork <bjorn@mork.no> +Submitted-by: John Crispin <john@phrozen.org> +--- + drivers/net/phy/phylink. | 14 +++++++++++-- + 1 file changed, 12 insertions(+), 2 deletions(-) + +--- a/drivers/net/phy/phylink.c ++++ b/drivers/net/phy/phylink.c +@@ -1994,6 +1994,11 @@ int phylink_ethtool_ksettings_set(struct + * the presence of a PHY, this should not be changed as that + * should be determined from the media side advertisement. + */ ++ if (pl->phydev->drv->get_port && pl->phydev->drv->set_port) { ++ if(pl->phydev->drv->get_port(pl->phydev) != kset->base.port) { ++ pl->phydev->drv->set_port(pl->phydev, kset->base.port); ++ } ++ } + return phy_ethtool_ksettings_set(pl->phydev, kset); + } + +@@ -2297,8 +2302,11 @@ int phylink_ethtool_get_eee(struct phyli + + ASSERT_RTNL(); + +- if (pl->phydev) ++ if (pl->phydev) { ++ if (pl->phydev->drv->get_eee) ++ return pl->phydev->drv->get_eee(pl->phydev, eee); + ret = phy_ethtool_get_eee(pl->phydev, eee); ++ } + + return ret; + } +@@ -2315,8 +2323,11 @@ int phylink_ethtool_set_eee(struct phyli + + ASSERT_RTNL(); + +- if (pl->phydev) ++ if (pl->phydev) { ++ if (pl->phydev->drv->set_eee) ++ return pl->phydev->drv->set_eee(pl->phydev, eee); + ret = phy_ethtool_set_eee(pl->phydev, eee); ++ } + + return ret; + } |