realtek: rtl930x: sgmii support

This makes sgmii work for 1000Base-T SFPs by stupidly adding the sgmii mode
wherever 1000base-x is accepted.  No intelligence has been used in the
process.  But it "works for me".

There is an obvious need for refactoring this code to make it more obvious
how and why we configure the mac/phy link like we do for different modes.

Signed-off-by: Bjørn Mork <bjorn@mork.no>
Link: https://github.com/openwrt/openwrt/pull/17950
Signed-off-by: Sander Vanheule <sander@svanheule.net>

2 files changed, 21 insertions, 6 deletions

diff --git a/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/dsa.c b/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/dsa.c
index 69151b2f6b..cdfe0fe3dc 100644
--- a/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/dsa.c
+++ b/target/linux/realtek/files-6.6/drivers/net/dsa/rtl83xx/dsa.c
@@ -814,6 +814,7 @@ static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,
 	pr_info("%s SDS is %d\n", __func__, sds_num);
 	if (sds_num >= 0 &&
 	    (state->interface == PHY_INTERFACE_MODE_1000BASEX ||
+	     state->interface == PHY_INTERFACE_MODE_SGMII ||
 	     state->interface == PHY_INTERFACE_MODE_10GBASER))
 		rtl9300_serdes_setup(port, sds_num, state->interface);
 
diff --git a/target/linux/realtek/files-6.6/drivers/net/phy/rtl83xx-phy.c b/target/linux/realtek/files-6.6/drivers/net/phy/rtl83xx-phy.c
index 53a7e184f5..9bab139e6d 100644
--- a/target/linux/realtek/files-6.6/drivers/net/phy/rtl83xx-phy.c
+++ b/target/linux/realtek/files-6.6/drivers/net/phy/rtl83xx-phy.c
@@ -1921,6 +1921,7 @@ void rtl9300_sds_tx_config(int sds, phy_interface_t phy_if)
 
 	switch(phy_if) {
 	case PHY_INTERFACE_MODE_1000BASEX:
+	case PHY_INTERFACE_MODE_SGMII:
 		pre_amp = 0x1;
 		main_amp = 0x9;
 		post_amp = 0x1;
@@ -2475,7 +2476,9 @@ void rtl9300_do_rx_calibration_1(int sds, phy_interface_t phy_mode)
 
 	/* TODO: make this work for DAC cables of different lengths */
 	/* For a 10GBit serdes wit Fibre, SDS 8 or 9 */
-	if (phy_mode == PHY_INTERFACE_MODE_10GBASER || PHY_INTERFACE_MODE_1000BASEX)
+	if (phy_mode == PHY_INTERFACE_MODE_10GBASER ||
+	    phy_mode == PHY_INTERFACE_MODE_1000BASEX ||
+	    phy_mode == PHY_INTERFACE_MODE_SGMII)
 		rtl9300_sds_field_w(sds, 0x2e, 0x16,  3,  2, 0x02);
 	else
 		pr_err("%s not PHY-based or SerDes, implement DAC!\n", __func__);
@@ -2573,7 +2576,9 @@ void rtl9300_sds_rxcal_3_1(int sds_num, phy_interface_t phy_mode)
 	pr_info("start_1.3.1");
 
 	/* ##1.3.1 */
-	if (phy_mode != PHY_INTERFACE_MODE_10GBASER && phy_mode != PHY_INTERFACE_MODE_1000BASEX)
+	if (phy_mode != PHY_INTERFACE_MODE_10GBASER &&
+	    phy_mode != PHY_INTERFACE_MODE_1000BASEX &&
+	    phy_mode != PHY_INTERFACE_MODE_SGMII)
 		rtl9300_sds_field_w(sds_num, 0x2e, 0xc, 8, 8, 0);
 
 	rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x0);
@@ -2589,7 +2594,9 @@ void rtl9300_sds_rxcal_3_2(int sds_num, phy_interface_t phy_mode)
 	bool eq_hold_enabled;
 	int i;
 
-	if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX) {
+	if (phy_mode == PHY_INTERFACE_MODE_10GBASER ||
+	    phy_mode == PHY_INTERFACE_MODE_1000BASEX ||
+	    phy_mode == PHY_INTERFACE_MODE_SGMII) {
 		/* rtl9300_rxCaliConf_serdes_myParam */
 		dac_long_cable_offset = 3;
 		eq_hold_enabled = true;
@@ -2599,7 +2606,7 @@ void rtl9300_sds_rxcal_3_2(int sds_num, phy_interface_t phy_mode)
 		eq_hold_enabled = false;
 	}
 
-	if (phy_mode == PHY_INTERFACE_MODE_1000BASEX)
+	if (phy_mode != PHY_INTERFACE_MODE_10GBASER)
 		pr_warn("%s: LEQ only valid for 10GR!\n", __func__);
 
 	pr_info("start_1.3.2");
@@ -2614,7 +2621,9 @@ void rtl9300_sds_rxcal_3_2(int sds_num, phy_interface_t phy_mode)
 
 	pr_info("sum10:%u, avg10:%u, int10:%u", sum10, avg10, int10);
 
-	if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX) {
+	if (phy_mode == PHY_INTERFACE_MODE_10GBASER ||
+	    phy_mode == PHY_INTERFACE_MODE_1000BASEX ||
+	    phy_mode == PHY_INTERFACE_MODE_SGMII) {
 		if (dac_long_cable_offset) {
 			rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, dac_long_cable_offset);
 			rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, eq_hold_enabled);
@@ -2644,7 +2653,9 @@ void rtl9300_do_rx_calibration_3(int sds_num, phy_interface_t phy_mode)
 {
 	rtl9300_sds_rxcal_3_1(sds_num, phy_mode);
 
-	if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX)
+	if (phy_mode == PHY_INTERFACE_MODE_10GBASER ||
+	    phy_mode == PHY_INTERFACE_MODE_1000BASEX ||
+	    phy_mode == PHY_INTERFACE_MODE_SGMII)
 		rtl9300_sds_rxcal_3_2(sds_num, phy_mode);
 }
 
@@ -2765,6 +2776,7 @@ int rtl9300_sds_sym_err_reset(int sds_num, phy_interface_t phy_mode)
 		break;
 
 	case PHY_INTERFACE_MODE_1000BASEX:
+	case PHY_INTERFACE_MODE_SGMII:
 		rtl9300_sds_field_w(sds_num, 0x1, 24, 2, 0, 0);
 		rtl9300_sds_field_w(sds_num, 0x1, 3, 15, 8, 0);
 		rtl9300_sds_field_w(sds_num, 0x1, 2, 15, 0, 0);
@@ -2787,6 +2799,7 @@ u32 rtl9300_sds_sym_err_get(int sds_num, phy_interface_t phy_mode)
 		break;
 
 	case PHY_INTERFACE_MODE_1000BASEX:
+	case PHY_INTERFACE_MODE_SGMII:
 	case PHY_INTERFACE_MODE_10GBASER:
 		v = rtl930x_read_sds_phy(sds_num, 5, 1);
 		return v & 0xff;
@@ -2812,6 +2825,7 @@ int rtl9300_sds_check_calibration(int sds_num, phy_interface_t phy_mode)
 
 	switch (phy_mode) {
 	case PHY_INTERFACE_MODE_1000BASEX:
+	case PHY_INTERFACE_MODE_SGMII:
 	case PHY_INTERFACE_MODE_XGMII:
 		if ((errors2 - errors1 > 100) ||
 		    (errors1 >= 0xffff00) || (errors2 >= 0xffff00)) {