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<title>staging/stintel/target, branch master</title>
<subtitle>Staging tree of Stijn Tintel</subtitle>
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<updated>2026-09-19T15:58:33Z</updated>
<entry>
<title>realtek: vlan: protect the entire VLAN MSTI update</title>
<updated>2026-09-19T15:58:33Z</updated>
<author>
<name>Markus Stockhausen</name>
</author>
<published>2026-09-19T06:31:59Z</published>
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<id>urn:sha1:c1111ed5d69678613b7a47aa76f8e6209f0da56d</id>
<content type='text'>
rtldsa_vlan_msti_set() holds reg_mutex only while replacing the MST
slot. The VLAN table read and write remain unprotected, allowing
concurrent updates to overwrite VLAN data or leave the VLAN FID
inconsistent with MST slot bookkeeping.

Use scoped_guard() to hold reg_mutex across the VLAN table read,
MST slot replacement and VLAN table write. This also releases the
mutex automatically if the slot replacement fails.

Assisted-by: ChatGPT (OpenAI GPT-6 Astra)
Link: https://github.com/openwrt/openwrt/pull/25258
Signed-off-by: Markus Stockhausen &lt;markus.stockhausen@gmx.de&gt;
</content>
</entry>
<entry>
<title>realtek: vlan: fix RTL931x VLAN interface and tunnel IDs</title>
<updated>2026-09-19T15:58:33Z</updated>
<author>
<name>Markus Stockhausen</name>
</author>
<published>2026-09-18T21:24:22Z</published>
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<id>urn:sha1:0e274d425dd46750a9ea951b3eeccadec04428fa</id>
<content type='text'>
The RTL931x VLAN entry stores L3_INTF_ID in bits 61:52, corresponding
to bits 29:20 of the third table word. The writer currently shifts the
mask before applying it to if_id because shifts take precedence over
bitwise AND. As a result, valid 10-bit interface IDs are written as zero.
Mask the ID before shifting it into place, using an unsigned operand.

L2_TNL_LST_IDX occupies bits 30:18 of the last word, with its valid bit
at bit 31. The reader shifts the word without masking the result, so
a valid entry includes the valid bit as bit 13 of the decoded index.
Mask the decoded index to 13 bits while retaining the existing -1
sentinel for entries whose valid bit is clear.

Assisted-by: ChatGPT (OpenAI GPT-6 Astra)
Link: https://github.com/openwrt/openwrt/pull/25258
Signed-off-by: Markus Stockhausen &lt;markus.stockhausen@gmx.de&gt;
</content>
</entry>
<entry>
<title>realtek: vlan: preserve valid untagged VLAN memberships</title>
<updated>2026-09-19T15:58:33Z</updated>
<author>
<name>Markus Stockhausen</name>
</author>
<published>2026-09-18T21:14:07Z</published>
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<id>urn:sha1:b50ae1221b6ee40a0ea7b5659c176773f146d669</id>
<content type='text'>
rtldsa_vlan_add() clears the entire untagged port mask if any untagged
bit lies outside the current member mask. This also clears untagged
settings for existing member ports. Adding or updating one port can
therefore change the egress tagging of unrelated ports in the VLAN.

Intersect the untagged mask with the member mask instead. This retains
untagged settings for existing members while keeping the driver's
existing policy of removing non-member bits before updating the
requested port.

This does not impose a new hardware requirement: the Longan SDK handles
member and untagged masks separately and does not enforce this subset
relationship in its VLAN port setter.

Assisted-by: ChatGPT (OpenAI GPT-6 Astra)
Link: https://github.com/openwrt/openwrt/pull/25258
Signed-off-by: Markus Stockhausen &lt;markus.stockhausen@gmx.de&gt;
</content>
</entry>
<entry>
<title>realtek: vlan: fix RTL839x VLAN hash key decoding</title>
<updated>2026-09-19T15:58:33Z</updated>
<author>
<name>Markus Stockhausen</name>
</author>
<published>2026-09-18T21:02:34Z</published>
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<id>urn:sha1:02afa9daf007f68648e96f4b446ac4807e55bef8</id>
<content type='text'>
rtl839x_vlan_tables_read() reads the multicast and unicast hash key
selectors from bits 2 and 3 of the last VLAN table word. The Cypress
SDK table definition places these fields at bits 33 and 34 of the
96-bit entry, corresponding to bits 1 and 2 of the middle word.

Read both selectors from the correct word and bit positions, matching
rtl839x_vlan_set_tagged(). This prevents subsequent read-modify-write
updates from replacing the configured hash key selectors with values
read from unrelated bits.

Assisted-by: ChatGPT (OpenAI GPT-6 Astra)
Link: https://github.com/openwrt/openwrt/pull/25258
Signed-off-by: Markus Stockhausen &lt;markus.stockhausen@gmx.de&gt;
</content>
</entry>
<entry>
<title>realtek: vlan: remove unrelated VLAN 1 rewrite on VLAN add</title>
<updated>2026-09-19T15:58:33Z</updated>
<author>
<name>Markus Stockhausen</name>
</author>
<published>2026-09-18T20:52:29Z</published>
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<id>urn:sha1:8065b6a8f094262d33dc5c8dd7242466256bbfd1</id>
<content type='text'>
rtldsa_vlan_prepare() ignores the requested port and VLAN. It reads
VLANs 0 and 1 for debug output, then rewrites VLAN 1 from the decoded
fields before rtldsa_vlan_add() acquires reg_mutex. It performs no
validation and always returns success.

This rewrite can change VLAN 1 even when adding a different VLAN. On
RTL930x, the SDK table definition places VLAN_GROUP_MASK in bits 23:16
of the VLAN entry. rtl930x_vlan_tables_read() does not decode this field,
and rtl930x_vlan_set_tagged() clears it when rebuilding the entry. Thus,
adding a port to another VLAN can clear a nonzero group mask in VLAN 1.

Remove the helper, its call and the unused error variable. The VID
checks and the locked read-modify-write of the requested VLAN remain
in rtldsa_vlan_add(), including when the requested VID is 1.

Preserving the RTL930x group mask during updates to the requested VLAN
is a separate issue and is not addressed here.

Assisted-by: ChatGPT (OpenAI GPT-6 Astra)
Link: https://github.com/openwrt/openwrt/pull/25258
Signed-off-by: Markus Stockhausen &lt;markus.stockhausen@gmx.de&gt;
</content>
</entry>
<entry>
<title>mpc85xx: remove last 6.12 patch</title>
<updated>2026-09-19T09:38:12Z</updated>
<author>
<name>Rosen Penev</name>
</author>
<published>2026-09-19T00:03:33Z</published>
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<id>urn:sha1:cd6e27418adc613e1c95923d2e5df5a8c2420abd</id>
<content type='text'>
It seems this remained because of a mistake when merging.

Signed-off-by: Rosen Penev &lt;rosenp@gmail.com&gt;
Link: https://github.com/openwrt/openwrt/pull/25262
Signed-off-by: Robert Marko &lt;robimarko@gmail.com&gt;
</content>
</entry>
<entry>
<title>realtek: phy: fix RTL8218E XSGMII initialization</title>
<updated>2026-09-18T20:31:21Z</updated>
<author>
<name>Jonas Jelonek</name>
</author>
<published>2026-09-18T13:16:47Z</published>
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<id>urn:sha1:b6ba4e9142b7e926dd3822beffdae26de34da98e</id>
<content type='text'>
Commit c8c187f0f08a ("realtek: add support for RTL8218E") added the
PHY identifier and reused the generic RTL821x callbacks. This is enough
when the bootloader has already configured the package, but it leaves the
MAC-side SerDes uninitialized without that setup. As a result, the XSGMII
link is not established after a cold boot and/or without any
pre-established PHY setup.

Add package-level initialization on the base PHY address and gate it on
the strapped XSGMII mode. Apply the minimal required subset of the vendor
configuration, reset the active SerDes block, and force XSGMII mode by
disabling SerDes autonegotiation. QSGMII remains unsupported.

This completes RTL8218E support without relying on bootloader PHY setup
while avoiding the large, mostly unnecessary vendor register table. This
minimal sequence has been established through various testing iterations
on two devices.

Fixes: c8c187f0f08a ("realtek: add support for RTL8218E")
Assisted-by: ChatGPT (OpenAI GPT-5.6 Sol)
Link: https://github.com/openwrt/openwrt/pull/25255
Signed-off-by: Jonas Jelonek &lt;jonas@jonasjelonek.de&gt;
</content>
</entry>
<entry>
<title>realtek: dsa: move L2 code into dedicated module</title>
<updated>2026-09-18T20:15:00Z</updated>
<author>
<name>Markus Stockhausen</name>
</author>
<published>2026-09-18T11:14:49Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/openwrt/staging/stintel/commit/?id=a7c5436a32d2a717c3346321be24b6f460fcbb26'/>
<id>urn:sha1:a7c5436a32d2a717c3346321be24b6f460fcbb26</id>
<content type='text'>
Move the family-specific L2 implementations from rtl838x.c, rtl839x.c,
rtl930x.c and rtl931x.c into a new l2.c module.

This collects the FDB entry encoding, hashing, CAM access, learning,
flooding, multicast port masks and ageing operations in one place.
Declare the operations in l2.h and add l2.o to the driver Makefile.

No functional changes intended.

Assisted-by: ChatGPT (OpenAI GPT-5.6 Sol)
Link: https://github.com/openwrt/openwrt/pull/25250
Signed-off-by: Markus Stockhausen &lt;markus.stockhausen@gmx.de&gt;
</content>
</entry>
<entry>
<title>uml: remove obsolete 6.12 kernel config and patches</title>
<updated>2026-09-18T16:25:41Z</updated>
<author>
<name>Christian Lamparter</name>
</author>
<published>2026-08-01T15:38:28Z</published>
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<id>urn:sha1:0d165124bc0b25703dd404bab825d13795be97b7</id>
<content type='text'>
With 6.12 no longer selectable for UML drop the ballast.

Signed-off-by: Christian Lamparter &lt;chunkeey@gmail.com&gt;
</content>
</entry>
<entry>
<title>uml: switch target to 6.18 kernel</title>
<updated>2026-09-18T16:24:28Z</updated>
<author>
<name>Christian Lamparter</name>
</author>
<published>2026-08-01T15:35:19Z</published>
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<id>urn:sha1:056f9ff14d82ca61ec2387ef956f86ea0ded01bf</id>
<content type='text'>
Makes 6.18 the default kernel.

Signed-off-by: Christian Lamparter &lt;chunkeey@gmail.com&gt;
</content>
</entry>
</feed>
