bcm63xx/atf/bl1/aarch32, branch master

Refactor SPSR initialisation code

2019-07-24T11:49:54Z

Change-Id: Ic3b30de13e314efca30fc71370227d3e76f1148b Signed-off-by: John Tsichritzis

bl1-smc-handler: Ensure the lower-order 16 bits of SPSR are programmed

2019-03-13T10:08:50Z

A bug recently fixed in bl2/aarch32/bl2_el3_entrypoint.S relates to programming the lower-order 16 bits of the SPSR to populate into the CPSR on eret. The BL1 smc-handler code is identical and has the same shortfall in programming the SPSR from the platform defined struct entry_point_info->spsr. msr spsr, r1 will only update bits f->[31:24] and c->[7:0] respectively. In order to ensure the 16 lower-order processor mode bits x->[15:8] and c->[7:0] this patch changes msr spsr, r1 to msr spsr_xc, r1. This change ensures we capture the x field, which we are interested in and not the f field which we are not. Fixes: f3b4914be3b4 ('AArch32: Add generic changes in BL1') Signed-off-by: Bryan O'Donoghue

BL1: Enable pointer authentication support

2019-02-27T11:58:09Z

The size increase after enabling options related to ARMv8.3-PAuth is: +----------------------------+-------+-------+-------+--------+ | | text | bss | data | rodata | +----------------------------+-------+-------+-------+--------+ | CTX_INCLUDE_PAUTH_REGS = 1 | +108 | +192 | +0 | +0 | | | 0.5% | 0.8% | | | +----------------------------+-------+-------+-------+--------+ | ENABLE_PAUTH = 1 | +748 | +192 | +16 | +0 | | | 3.7% | 0.8% | 7.0% | | +----------------------------+-------+-------+-------+--------+ Results calculated with the following build configuration: make PLAT=fvp SPD=tspd DEBUG=1 \ SDEI_SUPPORT=1 \ EL3_EXCEPTION_HANDLING=1 \ TSP_NS_INTR_ASYNC_PREEMPT=1 \ CTX_INCLUDE_PAUTH_REGS=1 \ ENABLE_PAUTH=1 Change-Id: I3a7d02feb6a6d212be32a01432b0c7c1a261f567 Signed-off-by: Antonio Nino Diaz

Sanitise includes across codebase

2019-01-04T10:43:17Z

Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3a282 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca33988b9 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz

xlat v2: Support the EL2 translation regime

2018-08-10T12:47:11Z

The translation library is useful elsewhere. Even though this repository doesn't exercise the EL2 support of the library, it is better to have it here as well to make it easier to maintain. enable_mmu_secure() and enable_mmu_direct() have been deprecated. The functions are still present, but they are behind ERROR_DEPRECATED and they call the new functions enable_mmu_svc_mon() and enable_mmu_direct_svc_mon(). Change-Id: I13ad10cd048d9cc2d55e0fff9a5133671b67dcba Signed-off-by: Antonio Nino Diaz

Rename 'smcc' to 'smccc'

2018-03-21T10:49:27Z

When the source code says 'SMCC' it is talking about the SMC Calling Convention. The correct acronym is SMCCC. This affects a few definitions and file names. Some files have been renamed (smcc.h, smcc_helpers.h and smcc_macros.S) but the old files have been kept for compatibility, they include the new ones with an ERROR_DEPRECATED guard. Change-Id: I78f94052a502436fdd97ca32c0fe86bd58173f2f Signed-off-by: Antonio Nino Diaz

aarch32: use lr as bl32 boot argument on aarch32 only systems

2018-02-02T12:16:18Z

Add 'lr_svc' as a boot parameter in AArch32 bl1. This is used by Optee and Trusty to get the non-secure entry point on AArch32 platforms. This change is not ported in AArch64 mode where the BL31, not BL32, is in charge of booting the non secure image (BL33). Signed-off-by: Etienne Carriere

Merge pull request #978 from etienne-lms/minor-build

2017-06-28T12:46:19Z

Minor build fixes

bl1: include bl1_private.h in aarch* files

2017-06-23T07:38:06Z

This change avoids warnings when setting -Wmissing-prototypes or when using sparse tool. Signed-off-by: Yann Gautier Signed-off-by: Etienne Carriere

bl: security_state should be of type unsigned int

2017-06-23T07:26:44Z

security_state is either 0 or 1. Prevent sign conversion potential error (setting -Werror=sign-conversion results in a build error). Signed-off-by: Yann Gautier Signed-off-by: Etienne Carriere