bcm63xx/atf/drivers/arm/gic, branch master

Merge "GICv3 driver: Fix support for full SPI range" into integration

2019-09-27T09:49:05Z

GICv3: Enable multi socket GIC redistributor frame discovery

2019-09-26T03:01:28Z

This patch provides declaration and definition of new GICv3 driver API: gicv3_rdistif_probe().This function delegates the responsibility of discovering the corresponding Redistributor base frame to each CPU itself. It is a modified version of gicv3_rdistif_base_addrs_probe() and is executed by each CPU in the platform unlike the previous approach in which only the Primary CPU did the discovery of all the Redistributor frames for every CPU. The flush operations as part of gicv3_driver_init() function are made necessary even for platforms with WARMBOOT_ENABLE_DCACHE_EARLY because the GICv3 driver data structure contents are accessed by CPU with D-Cache turned off during power down operations. Change-Id: I1833e81d3974b32a3e4a3df4766a33d070982268 Signed-off-by: Madhukar Pappireddy

GICv3 driver: Fix support for full SPI range

2019-09-13T14:47:13Z

This patch fixes GICv3 driver bug which causes assertion when full range of SPI INTIDs 32-1019 is supported in GICv3 implementation. Change-Id: Ib6da4b6eea868cff271cb32c7c7570bf5547ab47 Signed-off-by: Alexei Fedorov

Switch AARCH32/AARCH64 to aarch64

2019-08-01T20:45:03Z

NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__. All common C compilers pre-define the same macros to signal which architecture the code is being compiled for: __arm__ for AArch32 (or earlier versions) and __aarch64__ for AArch64. There's no need for TF-A to define its own custom macros for this. In order to unify code with the export headers (which use __aarch64__ to avoid another dependency), let's deprecate the AARCH32 and AARCH64 macros and switch the code base over to the pre-defined standard macro. (Since it is somewhat unintuitive that __arm__ only means AArch32, let's standardize on only using __aarch64__.) Change-Id: Ic77de4b052297d77f38fc95f95f65a8ee70cf200 Signed-off-by: Julius Werner

Prevent pending G1S interrupt become G0 interrupt

2019-06-05T03:05:05Z

According to Arm GIC spec(IHI0069E, section 4.6.1), when GICD_CTLR.DS == 0, Secure Group 1 interrupts are treated as Group 0 by a CPU interface if: - The PE does not implement EL3. - ICC_SRE_EL1(S).SRE == 0 When a cpu enter suspend or deep idle, it might be powered off. When the cpu resume, according to the GIC spec(IHI0069E, section 9.2.15, 9.2.16 and 9.2.22) the ICC_SRE_EL1.SRE reset value is 0 (if write is allowed) and G0/G1S/G1NS interrupt of the GIC cpu interface are all disabled. If a G1S SPI interrupt occurred and the target cpu of the SPI is assigned to a specific cpu which is in suspend and is powered off, when the cpu resume and start to initial the GIC cpu interface, the initial sequence might affect the interrupt group type of the pending interrupt on the cpu interface. Current initial sequence on the cpu interface is: 1. Enable G0 interrupt 2. Enable G1S interrupt 3. Enable ICC_SRE_EL1(S).SRE It is possible to treat the pending G1S interrupt as G0 interrupt on the cpu interface if the G1S SPI interrupt occurred between step2 and step3. To prevent the above situation happend, the initial sequence should be changed as follows: 1. Enable ICC_SRE_EL1(S).SRE 2. Enable G0 interrupt 3. Enable G1S interrupt Change-Id: Ie34f6e0b32eb9a1677ff72571fd4bfdb5cae25b0 Signed-off-by: James Kung

Minor changes to documentation and comments

2019-02-28T13:35:21Z

Fix some typos and clarify some sentences. Change-Id: Id276d1ced9a991b4eddc5c47ad9a825e6b29ef74 Signed-off-by: Antonio Nino Diaz

GICv3: Allow probe for fewer GICR interfaces than exposed by the frame

2019-02-04T15:42:36Z

Previously the GICv3 redistributor probe function (gicv3_rdistif_base_addrs_probe()) asserted that the number of per-CPU redistributor interfaces expected to be probed by the platform is equal to the number exported by the redistributor frame. This is a problem in case the number of CPUs in the platform is less than the number of redistributor interfaces in the frame. Hence this patch removes the assertion check and allows probe for fewer redistributor interfaces as required by the platform. Change-Id: I3449763a3ad70817224442cbe184d001030c9874 Signed-off-by: Soby Mathew

Sanitise includes across codebase

2019-01-04T10:43:17Z

Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3a282 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca33988b9 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz

Standardise header guards across codebase

2018-11-08T10:20:19Z

All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz

Mark GICV3, CCI and CCN boot time code as init

2018-10-03T10:48:15Z

Mark the GICv3, CCI and CCN code only used in Bl31 initialization with __init to be reclaimed once no longer needed. Change-Id: I3d77f36758450d9d1d87ecc60bc1c63fe4082667 Signed-off-by: Daniel Boulby