bcm63xx/atf/drivers/arm, branch master

Correct UART PL011 initialization calculation

2019-10-08T12:58:25Z

Currently for Armv7 plaforms the quotient calculated in pl011 uart init code is moved to register r1. This patch moves the quotient to register r2 as done for other platforms in the udiv instruction. Value of register r2 is then used to calculate the values for IBRD and FBRD register Change-Id: Ie6622f9f0e6d634378b471df5d02823b492c8a24 Signed-off-by: Avinash Mehta

Merge "GICv3 driver: Fix support for full SPI range" into integration

2019-09-27T09:49:05Z

GICv3: Enable multi socket GIC redistributor frame discovery

2019-09-26T03:01:28Z

This patch provides declaration and definition of new GICv3 driver API: gicv3_rdistif_probe().This function delegates the responsibility of discovering the corresponding Redistributor base frame to each CPU itself. It is a modified version of gicv3_rdistif_base_addrs_probe() and is executed by each CPU in the platform unlike the previous approach in which only the Primary CPU did the discovery of all the Redistributor frames for every CPU. The flush operations as part of gicv3_driver_init() function are made necessary even for platforms with WARMBOOT_ENABLE_DCACHE_EARLY because the GICv3 driver data structure contents are accessed by CPU with D-Cache turned off during power down operations. Change-Id: I1833e81d3974b32a3e4a3df4766a33d070982268 Signed-off-by: Madhukar Pappireddy

GICv3 driver: Fix support for full SPI range

2019-09-13T14:47:13Z

This patch fixes GICv3 driver bug which causes assertion when full range of SPI INTIDs 32-1019 is supported in GICv3 implementation. Change-Id: Ib6da4b6eea868cff271cb32c7c7570bf5547ab47 Signed-off-by: Alexei Fedorov

Switch AARCH32/AARCH64 to aarch64

2019-08-01T20:45:03Z

NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__. All common C compilers pre-define the same macros to signal which architecture the code is being compiled for: __arm__ for AArch32 (or earlier versions) and __aarch64__ for AArch64. There's no need for TF-A to define its own custom macros for this. In order to unify code with the export headers (which use __aarch64__ to avoid another dependency), let's deprecate the AARCH32 and AARCH64 macros and switch the code base over to the pre-defined standard macro. (Since it is somewhat unintuitive that __arm__ only means AArch32, let's standardize on only using __aarch64__.) Change-Id: Ic77de4b052297d77f38fc95f95f65a8ee70cf200 Signed-off-by: Julius Werner

Replace ASSEMBLY with compiler-builtin ASSEMBLER

2019-08-01T20:14:12Z

NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__. All common C compilers predefine a macro called __ASSEMBLER__ when preprocessing a .S file. There is no reason for TF-A to define it's own __ASSEMBLY__ macro for this purpose instead. To unify code with the export headers (which use __ASSEMBLER__ to avoid one extra dependency), let's deprecate __ASSEMBLY__ and switch the code base over to the predefined standard. Change-Id: Id7d0ec8cf330195da80499c68562b65cb5ab7417 Signed-off-by: Julius Werner

Remove MULTI_CONSOLE_API flag and references to it

2019-06-28T09:52:48Z

The new API becomes the default one. Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec Signed-off-by: Ambroise Vincent

Console: removed legacy console API

2019-06-26T09:52:23Z

This interface has been deprecated in favour of MULTI_CONSOLE_API. Change-Id: I6170c1c8c74a890e5bd6d05396743fe62024a08a Signed-off-by: Ambroise Vincent

Prevent pending G1S interrupt become G0 interrupt

2019-06-05T03:05:05Z

According to Arm GIC spec(IHI0069E, section 4.6.1), when GICD_CTLR.DS == 0, Secure Group 1 interrupts are treated as Group 0 by a CPU interface if: - The PE does not implement EL3. - ICC_SRE_EL1(S).SRE == 0 When a cpu enter suspend or deep idle, it might be powered off. When the cpu resume, according to the GIC spec(IHI0069E, section 9.2.15, 9.2.16 and 9.2.22) the ICC_SRE_EL1.SRE reset value is 0 (if write is allowed) and G0/G1S/G1NS interrupt of the GIC cpu interface are all disabled. If a G1S SPI interrupt occurred and the target cpu of the SPI is assigned to a specific cpu which is in suspend and is powered off, when the cpu resume and start to initial the GIC cpu interface, the initial sequence might affect the interrupt group type of the pending interrupt on the cpu interface. Current initial sequence on the cpu interface is: 1. Enable G0 interrupt 2. Enable G1S interrupt 3. Enable ICC_SRE_EL1(S).SRE It is possible to treat the pending G1S interrupt as G0 interrupt on the cpu interface if the G1S SPI interrupt occurred between step2 and step3. To prevent the above situation happend, the initial sequence should be changed as follows: 1. Enable ICC_SRE_EL1(S).SRE 2. Enable G0 interrupt 3. Enable G1S interrupt Change-Id: Ie34f6e0b32eb9a1677ff72571fd4bfdb5cae25b0 Signed-off-by: James Kung

drivers: scmi: scmi_sq: Modify wrong payload length

2019-05-23T05:41:35Z

Payload length of the get dram mapping information message is 0. The mbx_mem->len parameter should be 4, it only contains message header. Fixes: b67d202 ("plat/synquacer: enable SCMI support") Signed-off-by: Masahisa Kojima Change-Id: If1cd4c855da2dc5dc4b6da3bea152b8441971de7