<feed xmlns='http://www.w3.org/2005/Atom'>
<title>bcm63xx/atf/drivers/st/clk, branch master</title>
<subtitle>Broadcom-s Trusted Firmware A</subtitle>
<id>https://git.openwrt.org/project/bcm63xx/atf/atom?h=master</id>
<link rel='self' href='https://git.openwrt.org/project/bcm63xx/atf/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/atf/'/>
<updated>2019-09-02T15:51:57Z</updated>
<entry>
<title>stm32mp1: use a common function to check spinlock is available</title>
<updated>2019-09-02T15:51:57Z</updated>
<author>
<name>Yann Gautier</name>
</author>
<published>2019-05-22T17:13:51Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/atf/commit/?id=e463d3f43e0115fbafd7a17f7ba550fc8e9a2ae0'/>
<id>urn:sha1:e463d3f43e0115fbafd7a17f7ba550fc8e9a2ae0</id>
<content type='text'>
To use spinlocks, MMU should be enabled, as well as data cache.
A common function is created (moved from clock file).
It is then used whenever a spinlock has to be taken, in BSEC and clock
drivers.

Change-Id: I94baed0114a2061ad71bd5287a91bf7f1c6821f6
Signed-off-by: Yann Gautier &lt;yann.gautier@st.com&gt;
</content>
</entry>
<entry>
<title>clk: stm32mp: enable RTCAPB clock for dual-core chips</title>
<updated>2019-09-02T15:51:30Z</updated>
<author>
<name>Yann Gautier</name>
</author>
<published>2019-05-20T12:39:26Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/atf/commit/?id=6cb45f8984af596fc5460204e9be1d85de79cf5e'/>
<id>urn:sha1:6cb45f8984af596fc5460204e9be1d85de79cf5e</id>
<content type='text'>
In order to correctly manage the bring-up of non boot CPUs, the RTCAPB
clock needs to be enabled.
It controls the access to backup registers, where the CPU entrypoint
will be stored.

Change-Id: Ifeeceb4faf64bc9e0778030444f437cc0bb27272
Signed-off-by: Yann Gautier &lt;yann.gautier@st.com&gt;
Signed-off-by: Etienne Carriere &lt;etienne.carriere@st.com&gt;
Signed-off-by: Nicolas Le Bayon &lt;nicolas.le.bayon@st.com&gt;
</content>
</entry>
<entry>
<title>stm32mp1: add general SYSCFG management</title>
<updated>2019-06-17T12:03:51Z</updated>
<author>
<name>Yann Gautier</name>
</author>
<published>2019-05-20T17:17:08Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/atf/commit/?id=f33b2433f5a6ae0a89ec7c1234deb7ac64362367'/>
<id>urn:sha1:f33b2433f5a6ae0a89ec7c1234deb7ac64362367</id>
<content type='text'>
The system configuration controller is mainly used to manage
the compensation cell and other IOs and system related settings.

The SYSCFG driver is in charge of configuring masters on the interconnect,
IO compensation, low voltage boards, or pull-ups for boot pins.
All other configurations should be handled in Linux drivers requiring it.

Device tree files are also updated to manage vdd-supply regulator.

Change-Id: I10fb513761a7d1f2b7afedca9c723ad9d1bccf42
Signed-off-by: Nicolas Le Bayon &lt;nicolas.le.bayon@st.com&gt;
Signed-off-by: Yann Gautier &lt;yann.gautier@st.com&gt;
</content>
</entry>
<entry>
<title>clk: stm32mp1: correctly handle Clock Spreading Generator</title>
<updated>2019-06-17T12:03:51Z</updated>
<author>
<name>Yann Gautier</name>
</author>
<published>2019-06-04T13:55:37Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/atf/commit/?id=dd98aec87ca83054c9bc7502d018e46b02536eb1'/>
<id>urn:sha1:dd98aec87ca83054c9bc7502d018e46b02536eb1</id>
<content type='text'>
To activate the CSG option, the driver needs to set the bit2
of PLLNCR register = SSCG_CTRL: Spread Spectrum Clock Generator.
This bit should not be cleared when starting the PLL.

Change-Id: Ie5c720ff03655f27a7e7e9e7ccf8295dd046112f
Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
Signed-off-by: Yann Gautier &lt;yann.gautier@st.com&gt;
</content>
</entry>
<entry>
<title>clk: stm32mp1: use defines for mask values in stm32mp1_clk_sel array</title>
<updated>2019-06-17T12:03:51Z</updated>
<author>
<name>Yann Gautier</name>
</author>
<published>2019-05-07T16:49:33Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/atf/commit/?id=d4151d2ff99cba5a1703b647f84db8882a05eab7'/>
<id>urn:sha1:d4151d2ff99cba5a1703b647f84db8882a05eab7</id>
<content type='text'>
Rework the macro that eases the table definition: the src and msk fields
are now using MASK and SHIFT defines of each source register.
Some macros had then to be modified: _USART1_SEL, _ASS_SEL and _MSS_SEL to
_UART1_SEL, _AXIS_SEL, and _MCUS_SEL to match register fields.

Note: the mask for RCC_ASSCKSELR_AXISSRC is changed from 0x3 to 0x7
to reflect the size of the register field, even if there are only
3 possible clock sources.

The mask value is also corrected for QSPI and FMC clock selection.

Change-Id: I44114e3c1dd37b9fa1be1ba519611abd9a07764c
Signed-off-by: Yann Gautier &lt;yann.gautier@st.com&gt;
Signed-off-by: Etienne Carriere &lt;etienne.carriere@st.com&gt;
</content>
</entry>
<entry>
<title>clk: stm32mp1: move oscillator functions to generic file</title>
<updated>2019-06-17T12:03:51Z</updated>
<author>
<name>Yann Gautier</name>
</author>
<published>2019-05-17T13:57:56Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/atf/commit/?id=f66358afeeea6b78912b1c59b0e87f9b96451d5f'/>
<id>urn:sha1:f66358afeeea6b78912b1c59b0e87f9b96451d5f</id>
<content type='text'>
Those functions are generic for parsing nodes from device tree
hence could be located in generic source file.

The oscillators description structure is also moved to STM32MP1 clock
driver, as it is no more used in stm32mp1_clkfunc and cannot be in a
generic file.

Change-Id: I93ba74f4eea916440fef9b160d306af1b39f17c6
Signed-off-by: Yann Gautier &lt;yann.gautier@st.com&gt;
</content>
</entry>
<entry>
<title>arch: add some defines for generic timer registers</title>
<updated>2019-06-17T12:03:16Z</updated>
<author>
<name>Yann Gautier</name>
</author>
<published>2019-04-17T11:47:07Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/atf/commit/?id=e1abd5600b0ddc3f821b0c8c3fae45d530583a85'/>
<id>urn:sha1:e1abd5600b0ddc3f821b0c8c3fae45d530583a85</id>
<content type='text'>
Those defines are used in STM32MP1 clock driver.
It is better to put them altogether with already defined registers.

Change-Id: I6f8ad8c2477b947af6f76283a4ef5c40212d0027
Signed-off-by: Yann Gautier &lt;yann.gautier@st.com&gt;
</content>
</entry>
<entry>
<title>stm32mp1: add minimal support for co-processor Cortex-M4</title>
<updated>2019-02-20T16:34:21Z</updated>
<author>
<name>Yann Gautier</name>
</author>
<published>2019-02-15T16:33:27Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/atf/commit/?id=b053a22e8a538d3ee6114c0ce7f25fa49f0302d8'/>
<id>urn:sha1:b053a22e8a538d3ee6114c0ce7f25fa49f0302d8</id>
<content type='text'>
STM32MP1 chip embeds a dual Cortex-A7 and a Cortex-M4.
The support for Cortex-M4 clocks is added when configuring the clock tree.
Some minimal security features to allow communications between A7 and M4
are also added.

Change-Id: I60417e244a476f60a2758f4969700b2684056665
Signed-off-by: Yann Gautier &lt;yann.gautier@st.com&gt;
</content>
</entry>
<entry>
<title>stm32mp1: update clock driver</title>
<updated>2019-02-14T10:20:23Z</updated>
<author>
<name>Yann Gautier</name>
</author>
<published>2019-02-14T09:53:33Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/atf/commit/?id=0d21680c35f328f1b793f0765760e994d883ff12'/>
<id>urn:sha1:0d21680c35f328f1b793f0765760e994d883ff12</id>
<content type='text'>
Remove useless private structure in function prototypes.
Add a reference counter on clocks.
Prepare for future secured/shared/non-secured clocks.

Change-Id: I3dbed81721da5ceff5e10b2c4155b1e340c036ee
Signed-off-by: Yann Gautier &lt;yann.gautier@st.com&gt;
Signed-off-by: Etienne Carriere &lt;etienne.carriere@st.com&gt;
Signed-off-by: Lionel Debieve &lt;lionel.debieve@st.com&gt;
Signed-off-by: Nicolas LE BAYON &lt;nicolas.le.bayon@st.com&gt;
</content>
</entry>
<entry>
<title>stm32mp1: split clkfunc code</title>
<updated>2019-02-14T10:20:23Z</updated>
<author>
<name>Yann Gautier</name>
</author>
<published>2019-02-14T10:15:20Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/atf/commit/?id=447b2b137d7286a1ef451336c6e73fb7fd8999a1'/>
<id>urn:sha1:447b2b137d7286a1ef451336c6e73fb7fd8999a1</id>
<content type='text'>
Create a new file stm32mp_clkfunc.c to put functions that could be common
between several platforms.

Change-Id: Ica915c796b162b2345056b33328acc05035a242c
Signed-off-by: Yann Gautier &lt;yann.gautier@st.com&gt;
</content>
</entry>
</feed>
