bcm63xx/atf/include/arch/aarch32, branch master

Add Broadcom's code for bcm63xx support

2021-12-24T12:15:12Z

This includes all bcm63xx families (some of them don't follow that naming schema - like BCM4908). All that code has been extracted from the RAXE500_RAXE450-V1.0.8.70_GPL_release.zip . Signed-off-by: Rafał Miłecki

Add missing support for BL2_AT_EL3 in XIP memory

2019-10-02T07:06:39Z

Add the missing flag for aarch32 XIP memory mode. It was previously added in aarch64 only. Minor: Correct the aarch64 missing flag. Signed-off-by: Lionel Debieve Change-Id: Iac0a7581a1fd580aececa75f97deb894858f776f

AArch32: Disable Secure Cycle Counter

2019-09-26T15:36:02Z

This patch changes implementation for disabling Secure Cycle Counter. For ARMv8.5 the counter gets disabled by setting SDCR.SCCD bit on CPU cold/warm boot. For the earlier architectures PMCR register is saved/restored on secure world entry/exit from/to Non-secure state, and cycle counting gets disabled by setting PMCR.DP bit. In 'include\aarch32\arch.h' header file new ARMv8.5-PMU related definitions were added. Change-Id: Ia8845db2ebe8de940d66dff479225a5b879316f8 Signed-off-by: Alexei Fedorov

Replace ASSEMBLY with compiler-builtin ASSEMBLER

2019-08-01T20:14:12Z

NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__. All common C compilers predefine a macro called __ASSEMBLER__ when preprocessing a .S file. There is no reason for TF-A to define it's own __ASSEMBLY__ macro for this purpose instead. To unify code with the export headers (which use __ASSEMBLER__ to avoid one extra dependency), let's deprecate __ASSEMBLY__ and switch the code base over to the predefined standard. Change-Id: Id7d0ec8cf330195da80499c68562b65cb5ab7417 Signed-off-by: Julius Werner

SSBS: init SPSR register with default SSBS value

2019-07-24T11:49:53Z

This patch introduces an additional precautionary step to further enhance protection against variant 4. During the context initialisation before we enter the various BL stages, the SPSR.SSBS bit is explicitly set to zero. As such, speculative loads/stores are by default disabled for all BL stages when they start executing. Subsequently, each BL stage, can choose to enable speculative loads/stores or keep them disabled. This change doesn't affect the initial execution context of BL33 which is totally platform dependent and, thus, it is intentionally left up to each platform to initialise. For Arm platforms, SPSR.SSBS is set to zero for BL33 too. This means that, for Arm platforms, all BL stages start with speculative loads/stores disabled. Change-Id: Ie47d39c391d3f20fc2852fc59dbd336f8cacdd6c Signed-off-by: John Tsichritzis

console: update skeleton

2019-07-16T13:01:02Z

Update the skeleton implementation of the console interface. The 32 bit version was outdated and has been copied from the 64 bit version. Change-Id: Ib3e4eb09402ffccb1a30c703a53829a7bf064dfe Signed-off-by: Ambroise Vincent

arch: add some defines for generic timer registers

2019-06-17T12:03:16Z

Those defines are used in STM32MP1 clock driver. It is better to put them altogether with already defined registers. Change-Id: I6f8ad8c2477b947af6f76283a4ef5c40212d0027 Signed-off-by: Yann Gautier

aarch32: Allow compiling with soft-float toolchain

2019-04-05T10:37:19Z

ARMv7 and Cortex-A32(ARMv8/aarch32) uses "arm-linux-gnueabi" toolchain which has both soft-float and hard-float variants and so there could be scenarios where soft-float toolchain is used.Even though TF-A documentation recommends to use hard-float toolchain for aarch32 but there are external projects where we cannot mandate the selection of toolchain and for those projects at least the build should not fail. Current TF-A source fails to build with soft-float toolchain because assembler does not recognizes "vmsr" instruction which is required to enable floating point unit. To avoid this piece of code being compiled with soft-float toolchain add predefined macro guard " __SOFTFP__" exposed by soft-float toolchain. Change-Id: I76ba40906a8d622dcd476dd36ab4d277a925996c Signed-off-by: Manish Pandey

Console: remove deprecated finish_console_register

2019-04-03T13:55:18Z

The old version of the macro is deprecated. Commit cc5859ca19ff ("Multi-console: Deprecate the `finish_console_register` macro") provides more details. Change-Id: I3d1cdf6496db7d8e6cfbb5804f508ff46ae7e67e Signed-off-by: Ambroise Vincent

Cortex-A53: Workarounds for 819472, 824069 and 827319

2019-02-28T09:56:58Z

The workarounds for these errata are so closely related that it is better to only have one patch to make it easier to understand. Change-Id: I0287fa69aefa8b72f884833f6ed0e7775ca834e9 Signed-off-by: Ambroise Vincent