Broadcom-s Trusted Firmware A https://git.openwrt.org/project/bcm63xx/atf/atom?h=master 2019-08-15T14:23:27Z 2019-08-15T14:23:27Z Alexei Fedorov 2019-07-29T12:34:07Z urn:sha1:6c6a470fc1c2e1a516214f1f6dbe00ef045d1d0f This patch modifies crash reporting for AArch64 to provide aligned output of register dump and GIC registers. Change-Id: I8743bf1d2d6d56086e735df43785ef28051c5fc3 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> 2019-08-01T20:45:03Z Julius Werner 2019-07-09T21:02:43Z urn:sha1:402b3cf8766fe2cb4ae462f7ee7761d08a1ba56c NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__. All common C compilers pre-define the same macros to signal which architecture the code is being compiled for: __arm__ for AArch32 (or earlier versions) and __aarch64__ for AArch64. There's no need for TF-A to define its own custom macros for this. In order to unify code with the export headers (which use __aarch64__ to avoid another dependency), let's deprecate the AARCH32 and AARCH64 macros and switch the code base over to the pre-defined standard macro. (Since it is somewhat unintuitive that __arm__ only means AArch32, let's standardize on only using __aarch64__.) Change-Id: Ic77de4b052297d77f38fc95f95f65a8ee70cf200 Signed-off-by: Julius Werner <jwerner@chromium.org> 2019-07-23T09:41:41Z Ambroise Vincent 2019-07-04T13:58:45Z urn:sha1:37b70031e027c76fdebe3c2d2edb2da173bcf150 The watchdog is configured with a default value of 256 seconds in order to implement the Trusted Board Boot Requirements. For the FVP and Juno platforms, the FWU process relies on a watchdog reset. In order to automate the test of FWU, the length of this process needs to be as short as possible. Instead of waiting for those 4 minutes to have a reset by the watchdog, tell it to reset immediately. There are no side effects as the value of the watchdog's load register resets to 0xFFFFFFFF. Tested on Juno. Change-Id: Ib1aea80ceddc18ff1e0813a5b98dd141ba8a3ff2 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> 2019-06-26T13:07:51Z Manoj Kumar 2019-06-21T16:07:13Z urn:sha1:de8bc83ee9401acdab20fd8ae1f9cb9bf7ef7829 N1SDP platform supports RDIMMs with ECC capability. To use the ECC capability, the entire DDR memory space has to be zeroed out before enabling the ECC bits in DMC620. Zeroing out several gigabytes of memory from SCP is quite time consuming so functions are added that zeros out the DDR memory from application processor which is much faster compared to SCP. BL33 binary cannot be copied to DDR memory before enabling ECC so this is also done by TF-A from IOFPGA-DDR3 memory to main DDR4 memory after ECC is enabled. Original PLAT_PHY_ADDR_SPACE_SIZE was limited to 36-bits with which the entire DDR space cannot be accessed as DRAM2 starts in base 0x8080000000. So these macros are redefined for all ARM platforms. Change-Id: If09524fb65b421b7a368b1b9fc52c49f2ddb7846 Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com> 2019-05-15T10:42:39Z Sami Mujawar 2019-05-09T12:35:02Z urn:sha1:6bb6015f915dbc6a1208358024387a76530d45da The default DRAM2 base address for Arm platforms is 0x880000000. However, on some platforms the firmware may want to move the start address to a different value. To support this introduce PLAT_ARM_DRAM2_BASE that defaults to 0x880000000; but can be overridden by a platform (e.g. in platform_def.h). Change-Id: I0d81195e06070bc98f376444b48ada2db1666e28 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> 2019-04-17T13:12:48Z Aditya Angadi 2019-04-16T05:59:14Z urn:sha1:b0c97dafe00f5da71361b53fcbf5e4c12b174ec2 The BL1 stage setup code for ARM platforms sets up the SP805 watchdog controller as the secure watchdog. But not all ARM platforms use SP805 as the secure watchdog controller. So introduce two new ARM platform code specific wrapper functions to start and stop the secure watchdog. These functions then replace the calls to SP805 driver in common BL1 setup code. All the ARM platforms implement these wrapper functions by either calling into SP805 driver or the SBSA watchdog driver. Change-Id: I1a9a11b124cf3fac2a84f22ca40acd440a441257 Signed-off-by: Aditya Angadi <aditya.angadi@arm.com> 2019-04-01T09:43:42Z Ambroise Vincent 2019-02-13T15:58:00Z urn:sha1:609e053caabf0807a71243eec11f49120eaaab61 Improved support for W=1 compilation flag by solving missing-prototypes and old-style-definition warnings. The libraries are compiling with warnings (which turn into errors with the Werror flag). Outside of libraries, some warnings cannot be fixed without heavy structural changes. Change-Id: I1668cf99123ac4195c2a6a1d48945f7a64c67f16 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> 2019-01-23T16:01:19Z Sathees Balya 2018-11-15T14:22:30Z urn:sha1:5b8d50e40701ebb6a7ba548ccaa96ba879587fb9 On ARM platforms, the BL2 memory can be overlaid by BL31/BL32. The memory descriptors describing the list of executable images are created in BL2 R/W memory, which could be possibly corrupted later on by BL31/BL32 due to overlay. This patch creates a reserved location in SRAM for these descriptors and are copied over by BL2 before handing over to next BL image. Also this patch increases the PLAT_ARM_MAX_BL2_SIZE for juno when TBBR is enabled. Fixes ARM-Software/tf-issues#626 Change-Id: I755735706fa702024b4032f51ed4895b3687377f Signed-off-by: Sathees Balya <sathees.balya@arm.com> 2019-01-22T09:20:59Z Antonio Nino Diaz 2019-01-21T11:53:29Z urn:sha1:8855e52ec5ba8764280ad6d9a2681f5df2930d23 The SPM implementation based on MM is going to be kept for the foreseeable future. Change-Id: I11e96778a4f52a1aa803e7e048d9a7cb24a53954 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Acked-by: Sumit Garg <sumit.garg@linaro.org> 2019-01-16T16:01:42Z Soby Mathew 2019-01-16T16:01:42Z urn:sha1:cd1f39b48ab4a0596ace57cc920e4d4ba6e92784 synquacer: add SPM support