bcm63xx/atf/lib/cpus/aarch64, branch master

Add Broadcom's code for bcm63xx support

2021-12-24T12:15:12Z

This includes all bcm63xx families (some of them don't follow that naming schema - like BCM4908). All that code has been extracted from the RAXE500_RAXE450-V1.0.8.70_GPL_release.zip . Signed-off-by: Rafał Miłecki

Merge "Neoverse N1 Errata Workaround 1542419" into integration

2019-10-07T12:05:26Z

Neoverse N1 Errata Workaround 1542419

2019-10-04T16:31:24Z

Coherent I-cache is causing a prefetch violation where when the core executes an instruction that has recently been modified, the core might fetch a stale instruction which violates the ordering of instruction fetches. The workaround includes an instruction sequence to implementation defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap handler to execute a TLB inner-shareable invalidation to an arbitrary address followed by a DSB. Signed-off-by: Lauren Wehrmeister Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6

Introducing support for Cortex-A65AE

2019-10-03T13:38:31Z

Change-Id: I1ea2bf088f1e001cdbd377cbfb7c6a2866af0422 Signed-off-by: Imre Kis

Introducing support for Cortex-A65

2019-10-02T16:12:28Z

Change-Id: I645442d52a295706948e2cac88c36c1a3cb0bc47 Signed-off-by: Imre Kis

Cortex_hercules: Add support for Hercules-AE

2019-09-30T11:55:31Z

Not tested on FVP Model. Change-Id: Iedebc5c1fbc7ea577e94142b7feafa5546f1f4f9 Signed-off-by: Artsem Artsemenka

Zeus: apply the MSR SSBS instruction

2019-09-11T13:37:42Z

Zeus supports the SSBS mechanism and also the new MSR instruction to immediately apply the mitigation. Hence, the new instruction is utilised in the Zeus-specific reset function. Change-Id: I962747c28afe85a15207a0eba4146f9a115b27e7 Signed-off-by: John Tsichritzis

Merge "Fix for N1 1043202 Errata Workaround" into integration

2019-08-20T09:31:16Z

Fix for N1 1043202 Errata Workaround

2019-08-19T16:06:18Z

ISB instruction was removed from the N1 1043202 Errata Workaround [1], this fix is adding the ISB instruction back in. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Signed-off-by: Lauren Wehrmeister Change-Id: I74eac7f6ad38991c36d423ad6aa44558033ad388

FVP_Base_AEMv8A platform: Fix cache maintenance operations

2019-08-16T11:30:37Z

This patch fixes FVP_Base_AEMv8A model hang issue with ARMv8.4+ with cache modelling enabled configuration. Incorrect L1 cache flush operation to PoU, using CLIDR_EL1 LoUIS field, which is required by the architecture to be zero for ARMv8.4-A with ARMv8.4-S2FWB feature is replaced with L1 to L2 and L2 to L3 (if L3 is present) cache flushes. FVP_Base_AEMv8A model can be configured with L3 enabled by setting `cluster0.l3cache-size` and `cluster1.l3cache-size` to non-zero values, and presence of L3 is checked in `aem_generic_core_pwr_dwn` function by reading CLIDR_EL1.Ctype3 field value. Change-Id: If3de3d4eb5ed409e5b4ccdbc2fe6d5a01894a9af Signed-off-by: Alexei Fedorov