bcm63xx/atf/lib/locks/exclusive/aarch32, branch master Broadcom-s Trusted Firmware A https://git.openwrt.org/project/bcm63xx/atf/atom?h=master 2017-11-08T12:49:29Z ARMv7 does not support STL instruction 2017-11-08T12:49:29Z Etienne Carriere 2017-11-05T21:55:47Z urn:sha1:0147bef523e27e26c0240fef4b47deca6720566c Also need to add a SEV instruction in ARMv7 spin_unlock which is implicit in ARMv8. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Use SPDX license identifiers 2017-05-03T08:39:28Z dp-arm 2017-05-03T08:38:09Z urn:sha1:82cb2c1ad9897473743f08437d0a3995bed561b9 To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file. NOTE: Files that have been imported by FreeBSD have not been modified. [0]: https://spdx.org/ Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a Signed-off-by: dp-arm <dimitris.papastamos@arm.com> AArch32: Add support in TF libraries 2016-08-10T11:35:46Z Soby Mathew 2016-05-05T13:10:46Z urn:sha1:e33b78a658bd54a815c780e17c2d0073db6f59db This patch adds AArch32 support to cpu ops, context management, per-cpu data and spinlock libraries. The `entrypoint_info` structure is modified to add support for AArch32 register arguments. The CPU operations for AEM generic cpu in AArch32 mode is also added. Change-Id: I1e52e79f498661d8f31f1e7b3a29e222bc7a4483