bcm63xx/atf/lib/xlat_tables/aarch32/xlat_tables.c, branch master

lib/xlat_tables: Add support for ARMv8.4-TTST

2019-01-30T11:17:38Z

ARMv8.4-TTST (Small Translation tables) relaxes the lower limit on the size of translation tables by increasing the maximum permitted value of the T1SZ and T0SZ fields in TCR_EL1, TCR_EL2, TCR_EL3, VTCR_EL2 and VSTCR_EL2. This feature is supported in AArch64 state only. This patch adds support for this feature to both versions of the translation tables library. It also removes the static build time checks for virtual address space size checks to runtime assertions. Change-Id: I4e8cebc197ec1c2092dc7d307486616786e6c093 Signed-off-by: Sathees Balya

Sanitise includes across codebase

2019-01-04T10:43:17Z

Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3a282 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca33988b9 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz

xlat: Remove deprecated interfaces

2018-09-28T14:31:53Z

Change-Id: I83de2ae3e0795e6fec3c1e5b37c441b64b0c9cb6 Signed-off-by: Antonio Nino Diaz

xlat v2: Support the EL2 translation regime

2018-08-10T12:47:11Z

The translation library is useful elsewhere. Even though this repository doesn't exercise the EL2 support of the library, it is better to have it here as well to make it easier to maintain. enable_mmu_secure() and enable_mmu_direct() have been deprecated. The functions are still present, but they are behind ERROR_DEPRECATED and they call the new functions enable_mmu_svc_mon() and enable_mmu_direct_svc_mon(). Change-Id: I13ad10cd048d9cc2d55e0fff9a5133671b67dcba Signed-off-by: Antonio Nino Diaz

xlat: Fix MISRA defects

2018-07-30T08:30:15Z

Fix defects of MISRA C-2012 rules 8.13, 10.1, 10.3, 10.4, 10.8, 11.6, 14.4, 15.7, 17.8, 20.10, 20.12, 21.1 and Directive 4.9. Change-Id: I7ff61e71733908596dbafe2e99d99b4fce9765bd Signed-off-by: Antonio Nino Diaz

xlat v1: Provide direct MMU-enabling stubs

2018-06-27T10:31:30Z

An earlier patch split MMU-enabling function for translation library v2. Although we don't intend to introduce the exact same functionality for xlat v1, this patch introduces stubs for directly enabling MMU to maintain API-compatibility. Change-Id: Id7d56e124c80af71de999fcda10f1734b50bca97 Signed-off-by: Jeenu Viswambharan

ARMv7 may not support large page addressing

2017-11-08T12:53:47Z

ARCH_SUPPORTS_LARGE_PAGE_ADDRESSING allows build environment to handle specific case when target ARMv7 core only supports 32bit MMU descriptor mode. If ARMv7 based platform does not set ARM_CORTEX_Ax=yes, platform shall define ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING to enable large page addressing support. Signed-off-by: Etienne Carriere

xlat lib: Fix some types

2017-07-26T08:28:23Z

Fix the type length and signedness of some of the constants and variables used in the translation table library. This patch supersedes Pull Request #1018: https://github.com/ARM-software/arm-trusted-firmware/pull/1018 Change-Id: Ibd45faf7a4fb428a0bf71c752551d35800212fb2 Signed-off-by: Sandrine Bailleux

xlat lib: Reorganize architectural defs

2017-07-25T12:09:00Z

Move the header files that provide translation tables architectural definitions from the library v2 source files to the library include directory. This allows to share these definitions between both versions (v1 and v2) of the library. Create a new header file that includes the AArch32 or AArch64 definitions based on the AARCH32 build flag, so that the library user doesn't have to worry about handling it on their side. Also repurpose some of the definitions the header files provide to concentrate on the things that differ between AArch32 and AArch64. As a result they now contain the following information: - the first table level that allows block descriptors; - the architectural limits of the virtual address space; - the initial lookup level to cover the entire address space. Additionally, move the XLAT_TABLE_LEVEL_MIN macro from xlat_tables_defs.h to the AArch32/AArch64 architectural definitions. This new organisation eliminates duplicated information in the AArch32 and AArch64 versions. It also decouples these architectural files from any platform-specific information. Previously, they were dependent on the address space size, which is platform-specific. Finally, for the v2 of the library, move the compatibility code for ADDR_SPACE_SIZE into a C file as it is not needed outside of this file. For v1, this code hasn't been changed and stays in a header file because it's needed by several files. Change-Id: If746c684acd80eebf918abd3ab6e8481d004ac68 Signed-off-by: Sandrine Bailleux

aarch32: Apply workaround for errata 813419 of Cortex-A57

2017-06-22T15:42:23Z

TLBI instructions for monitor mode won't have the desired effect under specific circumstances in Cortex-A57 r0p0. The workaround is to execute DSB and TLBI twice each time. Even though this errata is only needed in r0p0, the current errata framework is not prepared to apply run-time workarounds. The current one is always applied if compiled in, regardless of the CPU or its revision. The `DSB` instruction used when initializing the translation tables has been changed to `DSB ISH` as an optimization and to be consistent with the barriers used for the workaround. NOTE: This workaround is present in AArch64 TF and already enabled by default on Juno. Change-Id: I10b0baa304ed64b13b7b26ea766e61461e759dfa Signed-off-by: Dimitris Papastamos