bcm63xx/atf/lib, branch master

Add Broadcom's code for bcm63xx support

2021-12-24T12:15:12Z

This includes all bcm63xx families (some of them don't follow that naming schema - like BCM4908). All that code has been extracted from the RAXE500_RAXE450-V1.0.8.70_GPL_release.zip . Signed-off-by: Rafał Miłecki

xlat_table_v2: Fix enable WARMBOOT_ENABLE_DCACHE_EARLY config

2019-10-18T09:26:34Z

The WARMBOOT_ENABLE_DCACHE_EARLY allows caches to be turned on early during the boot. But the xlat_change_mem_attributes_ctx() API did not do the required cache maintenance after the mmap tables are modified if WARMBOOT_ENABLE_DCACHE_EARLY is enabled. This meant that when the caches are turned off during power down, the tables in memory are accessed as part of cache maintenance for power down, and the tables are not correct at this point which results in a data abort. This patch removes the optimization within xlat_change_mem_attributes_ctx() when WARMBOOT_ENABLE_DCACHE_EARLY is enabled. Signed-off-by: Artsem Artsemenka Change-Id: I82de3decba87dd13e9856b5f3620a1c8571c8d87

Merge "Neoverse N1 Errata Workaround 1542419" into integration

2019-10-07T12:05:26Z

Merge "Fix the CAS spinlock implementation" into integration

2019-10-07T11:43:32Z

Neoverse N1 Errata Workaround 1542419

2019-10-04T16:31:24Z

Coherent I-cache is causing a prefetch violation where when the core executes an instruction that has recently been modified, the core might fetch a stale instruction which violates the ordering of instruction fetches. The workaround includes an instruction sequence to implementation defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap handler to execute a TLB inner-shareable invalidation to an arbitrary address followed by a DSB. Signed-off-by: Lauren Wehrmeister Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6

Fix the CAS spinlock implementation

2019-10-04T08:19:35Z

Make the spinlock implementation use ARMv8.1-LSE CAS instruction based on a platform build option. The CAS-based implementation used to be unconditionally selected for all ARM8.1+ platforms. The previous CAS spinlock implementation had a bug wherein the spin_unlock() implementation had an `sev` after `stlr` which is not sufficient. A dsb is needed to ensure that the stlr completes prior to the sev. Having a dsb is heavyweight and a better solution would be to use load exclusive semantics to monitor the lock and wake up from wfe when a store happens to the lock. The patch implements the same. Change-Id: I5283ce4a889376e4cc01d1b9d09afa8229a2e522 Signed-off-by: Soby Mathew Signed-off-by: Olivier Deprez

Merge "TF-A: Add support for ARMv8.3-PAuth in BL1 SMC calls and BL2U" into integration

2019-10-03T16:22:41Z

TF-A: Add support for ARMv8.3-PAuth in BL1 SMC calls and BL2U

2019-10-03T13:43:55Z

This patch adds support for ARMv8.3-PAuth in BL1 SMC calls and BL2U image for firmware updates by programming APIAKey_EL1 registers and enabling Pointer Authentication in EL3 and EL1 respectively. Change-Id: I875d952aba8242caf74fb5f4f2d2af6f0c768c08 Signed-off-by: Alexei Fedorov

Introducing support for Cortex-A65AE

2019-10-03T13:38:31Z

Change-Id: I1ea2bf088f1e001cdbd377cbfb7c6a2866af0422 Signed-off-by: Imre Kis

Introducing support for Cortex-A65

2019-10-02T16:12:28Z

Change-Id: I645442d52a295706948e2cac88c36c1a3cb0bc47 Signed-off-by: Imre Kis