bcm63xx/atf/plat/arm/common, branch master

Migrate ARM platforms to use the new GICv3 API

2019-09-26T03:06:49Z

This patch invokes the new function gicv3_rdistif_probe() in the ARM platform specific gicv3 driver. Since this API modifies the shared GIC related data structure, it must be invoked coherently by using the platform specific pwr_domain_on_finish_late hook. Change-Id: I6efb17d5da61545a1c5a6641b8f58472b31e62a8 Signed-off-by: Madhukar Pappireddy

Refactor ARMv8.3 Pointer Authentication support code

2019-09-13T13:11:59Z

This patch provides the following features and makes modifications listed below: - Individual APIAKey key generation for each CPU. - New key generation on every BL31 warm boot and TSP CPU On event. - Per-CPU storage of APIAKey added in percpu_data[] of cpu_data structure. - `plat_init_apiakey()` function replaced with `plat_init_apkey()` which returns 128-bit value and uses Generic timer physical counter value to increase the randomness of the generated key. The new function can be used for generation of all ARMv8.3-PAuth keys - ARMv8.3-PAuth specific code placed in `lib\extensions\pauth`. - New `pauth_init_enable_el1()` and `pauth_init_enable_el3()` functions generate, program and enable APIAKey_EL1 for EL1 and EL3 respectively; pauth_disable_el1()` and `pauth_disable_el3()` functions disable PAuth for EL1 and EL3 respectively; `pauth_load_bl31_apiakey()` loads saved per-CPU APIAKey_EL1 from cpu-data structure. - Combined `save_gp_pauth_registers()` function replaces calls to `save_gp_registers()` and `pauth_context_save()`; `restore_gp_pauth_registers()` replaces `pauth_context_restore()` and `restore_gp_registers()` calls. - `restore_gp_registers_eret()` function removed with corresponding code placed in `el3_exit()`. - Fixed the issue when `pauth_t pauth_ctx` structure allocated space for 12 uint64_t PAuth registers instead of 10 by removal of macro CTX_PACGAKEY_END from `include/lib/el3_runtime/aarch64/context.h` and assigning its value to CTX_PAUTH_REGS_END. - Use of MODE_SP_ELX and MODE_SP_EL0 macro definitions in `msr spsel` instruction instead of hard-coded values. - Changes in documentation related to ARMv8.3-PAuth and ARMv8.5-BTI. Change-Id: Id18b81cc46f52a783a7e6a09b9f149b6ce803211 Signed-off-by: Alexei Fedorov

Switch AARCH32/AARCH64 to aarch64

2019-08-01T20:45:03Z

NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__. All common C compilers pre-define the same macros to signal which architecture the code is being compiled for: __arm__ for AArch32 (or earlier versions) and __aarch64__ for AArch64. There's no need for TF-A to define its own custom macros for this. In order to unify code with the export headers (which use __aarch64__ to avoid another dependency), let's deprecate the AARCH32 and AARCH64 macros and switch the code base over to the pre-defined standard macro. (Since it is somewhat unintuitive that __arm__ only means AArch32, let's standardize on only using __aarch64__.) Change-Id: Ic77de4b052297d77f38fc95f95f65a8ee70cf200 Signed-off-by: Julius Werner

arm: Shorten the Firmware Update (FWU) process

2019-07-23T09:41:41Z

The watchdog is configured with a default value of 256 seconds in order to implement the Trusted Board Boot Requirements. For the FVP and Juno platforms, the FWU process relies on a watchdog reset. In order to automate the test of FWU, the length of this process needs to be as short as possible. Instead of waiting for those 4 minutes to have a reset by the watchdog, tell it to reset immediately. There are no side effects as the value of the watchdog's load register resets to 0xFFFFFFFF. Tested on Juno. Change-Id: Ib1aea80ceddc18ff1e0813a5b98dd141ba8a3ff2 Signed-off-by: Ambroise Vincent

Remove MULTI_CONSOLE_API flag and references to it

2019-06-28T09:52:48Z

The new API becomes the default one. Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec Signed-off-by: Ambroise Vincent

plat/arm: Skip BL2U if RESET_TO_SP_MIN flag is set

2019-06-11T10:42:07Z

BL2U should not build when RESET_TO_SP_MIN flag is set, like BL1 and BL2. Change-Id: Iac516121f98611ca1f58d2b5efdec6525b06ce4e Signed-off-by: Louis Mayencourt

Merge changes from topic "sami/550_fix_n1sdp_issues_v1" into integration

2019-05-16T08:33:56Z

* changes: N1SDP: Initialise CNTFRQ in Non Secure CNTBaseN N1SDP: Fix DRAM2 start address Add option for defining platform DRAM2 base Disable speculative loads only if SSBS is supported

N1SDP: Initialise CNTFRQ in Non Secure CNTBaseN

2019-05-15T10:43:20Z

N1SDP exhibits the behavior similar to Juno wherein CNTBaseN.CNTFRQ can be written but does not reflect the value of the CNTFRQ register in CNTCTLBase frame. This doesn't follow ARM ARM in that the value updated in CNTCTLBase.CNTFRQ is not reflected in CNTBaseN.CNTFRQ. Hence enable the workaround (applied to Juno) for N1SDP that updates the CNTFRQ register in the Non Secure CNTBaseN frame. Change-Id: Id89ee1bca0f25c9d62f8f794f2c4f4e618cdf092 Signed-off-by: Sami Mujawar

SMMUv3: Abort DMA transactions

2019-05-10T15:09:19Z

For security DMA should be blocked at the SMMU by default unless explicitly enabled for a device. SMMU is disabled after reset with all streams bypassing the SMMU, and abortion of all incoming transactions implements a default deny policy on reset. This patch also moves "bl1_platform_setup()" function from arm_bl1_setup.c to FVP platforms' fvp_bl1_setup.c and fvp_ve_bl1_setup.c files. Change-Id: Ie0ffedc10219b1b884eb8af625bd4b6753749b1a Signed-off-by: Alexei Fedorov

Console: Remove Arm console unregister on suspend

2019-04-24T09:50:16Z

Change-Id: Ie649b3c367a93db057eeaee7e83fa3e43f8c2607 Signed-off-by: Ambroise Vincent