bcm63xx/atf/plat/intel/soc/agilex/include, branch master

intel: agilex: Clear PLL lostlock bypass mode

2019-08-19T02:56:31Z

To provide glitchless clock to downstream logic even if clock toggles Signed-off-by: Hadi Asyrafi Change-Id: I728d64d0ba3b4492125bea5b0737fc83180356f1

Merge "intel: agilex: Fix memory controller driver" into integration

2019-08-15T15:30:51Z

intel: agilex: Fix memory controller driver

2019-08-15T01:28:06Z

Increase calibration delay, fix ddrio control config & nonsecure region limit Signed-off-by: Hadi Asyrafi Change-Id: Ibca3c247a3ad5104176ca9057d29755599f13c9b

intel: agilex: Fix reliance on hard coded clock information

2019-08-14T11:06:35Z

Extract clock information for UART, MMC & Watchdog from the clock manager Signed-off-by: Hadi Asyrafi Change-Id: I42d3d4ceeaf45788d457472f6ddcd3fe099f0133

intel: Platform common code refactor

2019-08-07T12:19:11Z

Pull out common code from aarch64 and include Signed-off-by: Hadi Asyrafi Change-Id: I4d0f5e1bb01bcdacbedf8e6c359de594239b645f

intel: agilex: Fix build error

2019-07-24T10:53:52Z

"result of '1 << 31' requires 33 bits to represent, but 'int' only has 32 bits [-Werror=shift-overflow=]" This is treated as an error since commit 93c690eba8ca ("Enable -Wshift-overflow=2 to check for undefined shift behavior") Change-Id: I141827a6711ab7759bfd6357e4ed9c1176da7c7b Signed-off-by: Ambroise Vincent

intel: Adds support for Agilex platform

2019-07-17T11:06:49Z

Signed-off-by: Hadi Asyrafi Change-Id: Ib2ad2068abdf0b204c5cb021ea919581adaca4ef