bcm63xx/atf/plat/intel/soc/stratix10/include, branch master

intel: stratix10: Fix reliance on hard coded clock information

2019-08-13T10:20:53Z

Extract clock information for UART, MMC & Watchdog from the platform rather than hard code it Signed-off-by: Hadi Asyrafi Change-Id: I2582bd34a6da97bd75d5ccba5f93840e65f26b03

intel: Platform common code refactor

2019-08-07T12:19:11Z

Pull out common code from aarch64 and include Signed-off-by: Hadi Asyrafi Change-Id: I4d0f5e1bb01bcdacbedf8e6c359de594239b645f

Merge changes from topic "jc/shift-overflow" into integration

2019-07-16T10:11:27Z

* changes: Enable -Wshift-overflow=2 to check for undefined shift behavior Update base code to not rely on undefined overflow behaviour Update hisilicon drivers to not rely on undefined overflow behaviour Update synopsys drivers to not rely on undefined overflow behaviour Update imx platform to not rely on undefined overflow behaviour Update mediatek platform to not rely on undefined overflow behaviour Update layerscape platform to not rely on undefined overflow behaviour Update intel platform to not rely on undefined overflow behaviour Update rockchip platform to not rely on undefined overflow behaviour Update renesas platform to not rely on undefined overflow behaviour Update meson platform to not rely on undefined overflow behaviour Update marvell platform to not rely on undefined overflow behaviour

Update intel platform to not rely on undefined overflow behaviour

2019-07-11T11:10:58Z

This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: I4c7a315cb18b3bbe623e7a7a998d2dac869638a7 Signed-off-by: Justin Chadwell

plat/intel: Fix SMPLSEL for MMC

2019-07-10T03:39:03Z

MMC sample select needs to be set properly so that DWMMC clock can be driven to 50Mhz Signed-off-by: Tien Hock, Loh Change-Id: I4a1dde4f6a1e78a36940c57a7a5b162be0bd443a

intel: Enable watchdog timer on Intel S10 platform

2019-03-21T02:35:24Z

Watchdog driver support & enablement during platform setup Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim

plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform

2019-02-26T01:25:14Z

This adds BL31 support to Intel Stratix10 SoCFPGA platform. BL31 in TF-A supports: - PSCI calls to enable 4 CPU cores - PSCI mailbox calls for FPGA reconfiguration Signed-off-by: Loh Tien Hock

plat: intel: Fix faulty DDR calibration value

2019-02-13T06:39:31Z

A DDR calibration value is missing write mask, causing ECC DDR calibration to fail. This patch addresses the issue. ECC should also be scrubbed before MMU initializes, thus the scrubbing is moved to ddr intialization phase. Signed-off-by: Loh Tien Hock

plat: intel: Add BL2 support for Stratix 10 SoC

2019-02-04T08:17:24Z

This adds BL2 support for Intel Stratix 10 SoC FPGA. Functionality includes: - Release and setup peripherals from reset - Calibrate DDR - ECC DDR Scrubbing - Load FIP (bl31 and bl33) Signed-off-by: Loh Tien Hock