bcm63xx/atf/plat/intel/soc, branch masterBroadcom-s Trusted Firmware Ahttps://git.openwrt.org/project/bcm63xx/atf/atom?h=master2019-09-12T12:36:31ZInvalidate dcache build option for bl2 entry at EL32019-09-12T12:36:31ZHadi Asyrafi2019-08-20T07:33:27Zurn:sha1:b90f207a1d386ec391bd3ea9eb403c4ad7b7551b
Some of the platform (ie. Agilex) make use of CCU IPs which will only be
initialized during bl2_el3_early_platform_setup. Any operation to the
cache beforehand will crash the platform. Hence, this will provide an
option to skip the data cache invalidation upon bl2 entry at EL3
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I2c924ed0589a72d0034714c31be8fe57237d1f06
intel: agilex: Fix psci power domain off2019-09-12T07:20:04ZHadi Asyrafi2019-09-12T07:14:01Zurn:sha1:afac9681ff28d9a402b6622af94935300b42fbdf
Disable gic cpu interface for powered down cpu. This patch also removes
core reset during power off as core reset will be done during power on
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I2ca96d876b6e71e56d24a9a7e184b6d6226b8673
Merge "intel: stratix10: Fix reliance on hard coded clock information" into integration2019-09-05T09:11:31ZSandrine Bailleux2019-09-05T09:11:31Zurn:sha1:5dbdf8e4eac1d5999f07976f9f430894b0784907Merge "intel: agilex: Clear PLL lostlock bypass mode" into integration2019-08-28T13:05:51ZPaul Beesley2019-08-28T13:05:51Zurn:sha1:3441952f61a62948ccf84c2e3eada9b340c3560dintel: agilex: HMC driver calculate DDR size2019-08-19T10:19:04ZHadi Asyrafi2019-08-16T09:07:42Zurn:sha1:24d16a2e40dc6b38bd89faed20e7a1651d834871
Driver will calculate DDR size instead of using hardcoded value
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I642cf2180929965ef12bd5ae4393b2f3d0dcddde
intel: agilex: Clear PLL lostlock bypass mode2019-08-19T02:56:31ZHadi Asyrafi2019-08-16T03:08:14Zurn:sha1:960a12b3fb4699cad83973c853fb5064ed6a75d0
To provide glitchless clock to downstream logic even if clock toggles
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I728d64d0ba3b4492125bea5b0737fc83180356f1
Merge "intel: agilex: Fix memory controller driver" into integration2019-08-15T15:30:51ZPaul Beesley2019-08-15T15:30:51Zurn:sha1:d1b6013d8485094d948e6b6039b8d119a907ecf8intel: agilex: Fix memory controller driver2019-08-15T01:28:06ZHadi Asyrafi2019-08-08T10:52:31Zurn:sha1:b266d821480d7ddc101e4f736c7bb73bcb75830f
Increase calibration delay, fix ddrio control config & nonsecure region
limit
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ibca3c247a3ad5104176ca9057d29755599f13c9b
intel: agilex: Fix reliance on hard coded clock information2019-08-14T11:06:35ZHadi Asyrafi2019-08-14T05:49:00Zurn:sha1:4e865bd2900dbb67cf1e27511818498720ea94d9
Extract clock information for UART, MMC & Watchdog from the clock manager
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I42d3d4ceeaf45788d457472f6ddcd3fe099f0133
intel: stratix10: Fix reliance on hard coded clock information2019-08-13T10:20:53ZHadi Asyrafi2019-07-30T14:18:17Zurn:sha1:fea24b88e40e899bb7d0e15362c46a7154b76b71
Extract clock information for UART, MMC & Watchdog from the platform
rather than hard code it
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I2582bd34a6da97bd75d5ccba5f93840e65f26b03