bcm63xx/atf/plat/nvidia/tegra/common/drivers/memctrl, branch master

Tegra: memctrl_v2: fix "overflow before widen" coverity issue

2019-09-05T15:40:38Z

This patch fixes a coding error, where the size of the protected memory area was truncated due to an incorrect typecast. This defect was found by coverity and reported as CID 336781. Change-Id: I41878b0a9a5e5cd78ef3393fdc7b9ea7f7403ed3 Signed-off-by: Varun Wadekar

Tegra: memctrl_v2: remove usage of ENABLE_SMMU_DEVICE config

2019-01-23T18:33:11Z

This patch removes the usage of this platform config, as it is always enabled by all the supported platforms. Change-Id: Ie7adb641adeb3604b177b6960b797722d60addfa Signed-off-by: Varun Wadekar

Tegra: memctrl_v2: platform handler for TZDRAM setup

2019-01-23T18:32:57Z

The Tegra memctrl driver sets up the TZDRAM fence during boot and system suspend exit. This patch provides individual platforms with handlers to perform custom steps during TZDRAM setup. Change-Id: Iee094d6ca189c6dd24f1147003c33c99ff3a953b Signed-off-by: Steven Kao

Tegra: memctrl_v2: platform handler for TZDRAM settings

2019-01-23T18:32:46Z

The Tegra memctrl driver sets up the TZDRAM fence during boot and system suspend exit. This patch provides individual platforms with handlers to perform platform specific steps, e.g. enable encryption, save base/size to secure scratch registers. Change-Id: Ifaa2e0eac20b50f77ec734256544c36dd511bd63 Signed-off-by: Varun Wadekar

Tegra: memctrl_v2: allow CPU accesses to TZRAM

2019-01-23T18:31:25Z

This patch enables CPU access configuration register to allow accesses to the TZRAM aperture on chips after Tegra186. Change-Id: I0898582f8bd6fd35360ecf8ca5cee21fe35f7aab Signed-off-by: Steven Kao

Tegra: memctrl_v2: pack TZDRAM base to RSVD55_SCRATCH

2019-01-23T18:31:19Z

This patch saves the TZDRAM_BASE value to secure RSVD55 scratch register. The warmboot code uses this register to restore the settings on exiting System Suspend. Change-Id: Id76175c2a7d931227589468511365599e2908411 Signed-off-by: Harvey Hsieh

Tegra: memctrl_v2: platform handlers to program MSS

2019-01-23T18:30:54Z

Introduce platform handlers to program the MSS settings. This allows the current driver to scale to future chips. Change-Id: I40a27648a1a3c73b1ce38dafddc1babb6f0b0d9b Signed-off-by: Puneet Saxena Signed-off-by: Krishna Reddy

Tegra: memctrl: clean MC INT status before exit to bootloader

2019-01-18T17:21:51Z

This patch cleans the Memory controller's interrupt status register, before exiting to the non-secure world during cold boot. This is required as we observed that the MC's arbitration bit is set before exiting the secure world. Change-Id: Iacd01994d03b3b9cbd7b8a57fe7ab5b04e607a9f Signed-off-by: Harvey Hsieh

Tegra: memctrl_v2: pack TZDRAM base into SCRATCH54_LO

2019-01-18T17:21:51Z

This patch moves the TZDRAM base address to SCRATCH55_LO due to security concerns. The HI and LO address bits are packed into SCRATCH55_LO for the warmboot firmware to restore. SCRATCH54_HI is still being used for backward compatibility, but would be removed eventually. The scratch registers are populated as: * RSV55_0 = CFG1[12:0] | CFG0[31:20] * RSV55_1 = CFG3[1:0] * RSV54_1 = CFG1[12:0] Change-Id: Idc20d165d8117488010fcc8dfd946f7ad475da58 Signed-off-by: Harvey Hsieh

Tegra: memctrl: assert if dynamic memmap fails

2019-01-18T17:21:51Z

This patch adds an assert in case the dynamic memmap routine fails. Change-Id: Idd20debbb8944340f5928c6f2cfea973a63a7b1c Signed-off-by: Varun Wadekar