bcm63xx/atf/plat/nvidia/tegra/include/drivers, branch master

Replace ASSEMBLY with compiler-builtin ASSEMBLER

2019-08-01T20:14:12Z

NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__. All common C compilers predefine a macro called __ASSEMBLER__ when preprocessing a .S file. There is no reason for TF-A to define it's own __ASSEMBLY__ macro for this purpose instead. To unify code with the export headers (which use __ASSEMBLER__ to avoid one extra dependency), let's deprecate __ASSEMBLY__ and switch the code base over to the predefined standard. Change-Id: Id7d0ec8cf330195da80499c68562b65cb5ab7417 Signed-off-by: Julius Werner

Makefile: remove extra include paths in INCLUDES

2019-04-03T14:30:46Z

Now it is needed to use the full path of the common header files. Commit 09d40e0e0828 ("Sanitise includes across codebase") provides more information. Change-Id: Ifedc79d9f664d208ba565f5736612a3edd94c647 Signed-off-by: Ambroise Vincent

Tegra: bpmp: mark device "not present" on boot timeout

2019-01-31T16:50:31Z

This patch updates the state machine to "not present" if the bpmp firmware is not found in the system during boot. The suspend handler also checks now if the interface exists, before updating the internal state machine. Reported by: Kalyani Chidambaram Vaidyanathan Change-Id: If8fd7f8e412bb603944555c24826855226e7f48c Signed-off-by: Varun Wadekar

Tegra210: clear PMC_DPD registers on resume

2019-01-31T16:50:13Z

This patch clears the PMC's DPD registers on resuming from System Suspend, for all Tegra210 platforms that support the sc7entry-fw. Change-Id: I7881ef0a5f609ed28b158bc2f4016abea3c7f305 Signed-off-by: kalyani chidambaram

Tegra: bpmp: suspend/resume handlers

2019-01-31T16:49:50Z

This patch adds suspend and resume handlers for the BPMP interface. Mark the interface as "suspended" before entering System Suspend and verify that BPMP is alive on exit. Change-Id: I74ccbc86125079b46d06360fc4c7e8a5acfbdfb2 Signed-off-by: Varun Wadekar

Tegra210: SiP handlers to allow PMC access

2019-01-31T16:49:05Z

This patch adds SiP handler for Tegra210 platforms to service read/write requests for PMC block. None of the secure registers are accessible to the NS world though. Change-Id: I7dc1f10c6a6ee6efc642ddcfb1170fb36d3accff Signed-off-by: kalyani chidambaram

Tegra: support for System Suspend using sc7entry-fw binary

2019-01-31T16:48:36Z

This patch adds support to enter System Suspend on Tegra210 platforms without the traditional BPMP firmware. The BPMP firmware will no longer be supported on Tegra210 platforms and its functionality will be divided across the CPU and sc7entry-fw. The sc7entry-fw takes care of performing the hardware sequence required to enter System Suspend (SC7 power state) from the COP. The CPU is required to load this firmware to the internal RAM of the COP and start the sequence. The CPU also make sure that the COP is off after cold boot and is only powered on when we want to start the actual System Suspend sequence. The previous bootloader loads the firmware to TZDRAM and passes its base and size as part of the boot parameters. The EL3 layer is supposed to sanitize the parameters before touching the firmware blob. To assist the warmboot code with the PMIC discovery, EL3 is also supposed to program PMC's scratch register #210, with appropriate values. Without these settings the warmboot code wont be able to get the device out of System Suspend. Change-Id: I5a7b868512dbfd6cfefd55acf3978a1fd7ebf1e2 Signed-off-by: Varun Wadekar

Tegra: pmc: helper function to find last ON CPU

2019-01-31T16:48:00Z

This patch adds a helper function to find the last standing CPU in a cluster. Change-Id: Id018f1958f458c772c7b0c52af8ddf7532b1cec5 Signed-off-by: Varun Wadekar

Tegra: flowctrl: helper functions to assist with cluster power states

2019-01-31T16:47:15Z

This patch adds helper functions to help platforms with cluster state entry and exit decisions. * tegra_fc_ccplex_pgexit_lock(): lock CPU power ungate * tegra_fc_ccplex_pgexit_unlock(): unlock CPU power ungate * tegra_fc_is_ccx_allowed(): CCx state entry allowed on this CPU? Change-Id: I6490d34bf380dc03ae203eb3028f61984f06931c Signed-off-by: Varun Wadekar

Tegra: flowctrl: support to enable/disable WDT's legacy FIQ routing

2019-01-31T16:46:25Z

On earlier Tegra platforms, e.g. Tegra210, the watchdog timer's FIQ interrupt is not direclty wired to the GICD. It goes to the flow controller instead, for power state management. But the flow controller can route the FIQ to the GICD, as a PPI, which can then get routed to the target CPU. This patch adds routines to enable/disable routing the legacy FIQ used by the watchdog timers, to the GICD. Change-Id: Idd07c88c8d730b5f0e93e3a6e4fdc59bdcb2161b Signed-off-by: Varun Wadekar