bcm63xx/atf/plat/nvidia/tegra/include/t210, branch master

Tegra: restrict non-secure PMC accesses

2019-01-31T16:50:52Z

Platforms that do not support bpmp firmware, do not need access to the PMC block from outside of the CPU complex. The agents running on the CPU can always access the PMC through the EL3 exception space. This patch restricts non-secure world access to the PMC block on such platforms. Change-Id: I2c4318dc07ddf6407c1700595e0f4aac377ba258 Signed-off-by: Varun Wadekar

Tegra210: skip past sc7entry-fw signature header

2019-01-31T16:49:28Z

This patch skips past the signature header added to the sc7entry-fw binary by the previous level bootloader. Currently, the size of the header is 1KB, so adjust the start address and the binary size at the time of copy. Change-Id: Id0494548009749035846d54df417a960c640c8f9 Signed-off-by: Varun Wadekar

Tegra210: SiP handlers to allow PMC access

2019-01-31T16:49:05Z

This patch adds SiP handler for Tegra210 platforms to service read/write requests for PMC block. None of the secure registers are accessible to the NS world though. Change-Id: I7dc1f10c6a6ee6efc642ddcfb1170fb36d3accff Signed-off-by: kalyani chidambaram

Tegra210: power off all DMA masters before System Suspend entry

2019-01-31T16:48:56Z

This patch puts all the DMA masters in reset before starting the System Suspend sequence. This helps us make sure that there are no rogue agents in the system trying to over-write the SC7 Entry Firmware with their own. Change-Id: I7eb39999d229951e612fbfeb9f86c4efb8f98b5a Signed-off-by: Varun Wadekar

Tegra: support for System Suspend using sc7entry-fw binary

2019-01-31T16:48:36Z

This patch adds support to enter System Suspend on Tegra210 platforms without the traditional BPMP firmware. The BPMP firmware will no longer be supported on Tegra210 platforms and its functionality will be divided across the CPU and sc7entry-fw. The sc7entry-fw takes care of performing the hardware sequence required to enter System Suspend (SC7 power state) from the COP. The CPU is required to load this firmware to the internal RAM of the COP and start the sequence. The CPU also make sure that the COP is off after cold boot and is only powered on when we want to start the actual System Suspend sequence. The previous bootloader loads the firmware to TZDRAM and passes its base and size as part of the boot parameters. The EL3 layer is supposed to sanitize the parameters before touching the firmware blob. To assist the warmboot code with the PMIC discovery, EL3 is also supposed to program PMC's scratch register #210, with appropriate values. Without these settings the warmboot code wont be able to get the device out of System Suspend. Change-Id: I5a7b868512dbfd6cfefd55acf3978a1fd7ebf1e2 Signed-off-by: Varun Wadekar

Tegra210: remove support for cluster power down

2019-01-31T16:48:24Z

This patch removes support for powering down a CPU cluster on Tegra210 platforms as none of them actually use it. Change-Id: I9665634cf2b5b7b8a1b5a2700cae152dc9165fe3 Signed-off-by: Varun Wadekar

Tegra210: support for cluster idle from the CPU

2019-01-31T16:48:09Z

This patch adds support to enter/exit to/from cluster idle power state on Tegra210 platforms that do not load BPMP firmware. The CPU initates the cluster idle sequence on the last standing CPU, by following these steps: Entry ----- * stop other CPUs from waking up * program the PWM pinmux to tristate for OVR PMIC * program the flow controller to enter CC6 state * skip L1 $ flush during cluster power down, as L2 $ is inclusive of L1 $ on Cortex-A57 CPUs Exit ---- * program the PWM pinmux to un-tristate for OVR PMIC * allow other CPUs to wake up This patch also makes sure that cluster idle state entry is not enabled until CL-DVFS is ready. Change-Id: I54cf31bf72b4a09d9bf9d2baaed6ee5a963c7808 Signed-off-by: Varun Wadekar

Tegra: platform dependent address space sizes

2019-01-31T16:47:51Z

This patch moves the PLAT_PHY_ADDR_SPACE_SIZE & PLAT_VIRT_ADDR_SPACE macros to tegra_def.h, to define the virtual/physical address space size on the platform. Change-Id: I1c5d264c7ffc1af0e7b14cc16ae2c0416efc76f6 Signed-off-by: Steven Kao

Tegra210: Enable WDT_CPU interrupt for FIQ Debugger

2019-01-31T16:47:29Z

This patch enables the watchdog timer's interrupt as an FIQ interrupt to the CPU. The interrupt generated by the watchdog is connected to the flow controller for power management reasons, and needs to be routed to the GICD for it to reach the CPU. Change-Id: I9437b516da2c5d763eca72694ed7f3c7389b3d9e Signed-off-by: Varun Wadekar

Tegra: SiP: set GPU in reset after vpr resize

2019-01-31T16:46:15Z

Whenever the VPR memory is resized, the GPU is put into reset first and then the new VPR parameters are programmed to the memory controller block. There exists a scenario, where the GPU might be out before we program the new VPR parameters. This means, the GPU would still be using older settings and leak secrets. This patch puts the GPU back into reset, if it is out of reset after resizing VPR, to mitigate this hole. Change-Id: I38a1000e3803f80909efcb02e27da4bd46909931 Signed-off-by: Jeetesh Burman