bcm63xx/atf/plat/nvidia/tegra/soc, branch master

Makefile: remove extra include paths in INCLUDES

2019-04-03T14:30:46Z

Now it is needed to use the full path of the common header files. Commit 09d40e0e0828 ("Sanitise includes across codebase") provides more information. Change-Id: Ifedc79d9f664d208ba565f5736612a3edd94c647 Signed-off-by: Ambroise Vincent

Tegra186: trampoline: include bl_common.h

2019-02-07T16:47:51Z

This patch includes bl_common.h from plat_trampoline.S to link with the __BL31_END__ symbol. Change-Id: Ie66c5009018472607db668583c9a0b3553f0ae73 Signed-off-by: Varun Wadekar

Tegra186: use common 'BL31_BASE' variable

2019-02-07T16:47:42Z

This patch modfies the 'tegra_soc_pwr_domain_power_down_wfi' handler to use BL31_BASE variable, provided by bl_common.h Change-Id: I9747228d0193c1ae6999284458b9f866955a61a2 Signed-off-by: Varun Wadekar

Tegra186: remove ENABLE_AFI_DEVICE macro usage

2019-02-05T16:27:43Z

This patch removes this macro and its usage as it is used only within the Tegra186 files and all derived platforms keep the macro enabled. Change-Id: Ib831b3c002ba4dedc3d5fafbb7d321daa28fa9ea Signed-off-by: Varun Wadekar

spd: trusty: memmap trusty's code memory before peeking

2019-02-05T16:27:43Z

This patch dynamically maps the first page of trusty's code memory, before accessing it to find out if we are running a 32-bit or 64-bit image. On Tegra platforms, this means we have to increase the mappings to accomodate the new memmap entry. Change-Id: If370d1e6cfcccd69b260134c1b462d8d17bee03d Signed-off-by: Varun Wadekar

Tegra: initialise per-CPU GIC interface(s)

2019-02-05T16:27:43Z

This patch initilises the per-CPU GIC bits during cold boot and secondary CPU power up. Commit 80c50ee accidentally left out this part. Change-Id: I73ce59dbc83580a84b827cab89fe7e1f65f9f130 Signed-off-by: Varun Wadekar

Tegra: restrict non-secure PMC accesses

2019-01-31T16:50:52Z

Platforms that do not support bpmp firmware, do not need access to the PMC block from outside of the CPU complex. The agents running on the CPU can always access the PMC through the EL3 exception space. This patch restricts non-secure world access to the PMC block on such platforms. Change-Id: I2c4318dc07ddf6407c1700595e0f4aac377ba258 Signed-off-by: Varun Wadekar

Tegra186: memctrl: disable stream id writes for MC clients

2019-01-31T16:50:43Z

As per the latest recommendations from the hardware team, write access needs to be disabled for APE, BPMP, NvDec and SCE clients. This patch disables stream id register writes for these MC clients to implement those recommendations. Change-Id: I8887c0f2cc5bc3fc5bba42074810ba5c1d3f121f Signed-off-by: Krishna Reddy

Tegra210: toggle ring oscillator across cluster idle

2019-01-31T16:50:22Z

This patch toggles the ring oscillator state across cluster idle as DFLL loses its state. We dont want garbage values being written to the pmic when we enter cluster idle state, so enable "open loop" when we enter CC6 and restore the state to "closed loop" on exit. Change-Id: I56f4649f57bcc651d6c415a6dcdc978e9444c97b Signed-off-by: Varun Wadekar

Tegra210: clear PMC_DPD registers on resume

2019-01-31T16:50:13Z

This patch clears the PMC's DPD registers on resuming from System Suspend, for all Tegra210 platforms that support the sc7entry-fw. Change-Id: I7881ef0a5f609ed28b158bc2f4016abea3c7f305 Signed-off-by: kalyani chidambaram