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<title>bcm63xx/atf/plat/rockchip/px30/include, branch master</title>
<subtitle>Broadcom-s Trusted Firmware A</subtitle>
<id>https://git.openwrt.org/project/bcm63xx/atf/atom?h=master</id>
<link rel='self' href='https://git.openwrt.org/project/bcm63xx/atf/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/atf/'/>
<updated>2019-09-20T00:42:53Z</updated>
<entry>
<title>rockchip: Update BL31_BASE to 0x40000</title>
<updated>2019-09-20T00:42:53Z</updated>
<author>
<name>Kever Yang</name>
</author>
<published>2019-09-19T02:37:36Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/atf/commit/?id=0aad563c74807195cc7fe2208d17e2d889157f1e'/>
<id>urn:sha1:0aad563c74807195cc7fe2208d17e2d889157f1e</id>
<content type='text'>
Rockchip platform is using the first 1MB of DRAM as secure ram space,
and there is a vendor loader who loads and runs the BL31/BL32/BL33,
this loader is usually load by SoC BootRom to the start addres of DRAM,
we need to reserve enough space for this loader so that it doesn't need
to do the relocate when loading the BL31. eg.
We use U-Boot SPL to load ATF BL31 and U-Boot proper as BL33, the SPL
TEXT BASE is offset 0 of DRAM which is decide by Bootrom; if we update
the BL31_BASE to offset 0x40000(256KB), then the 0~0x40000 should be
enough for SPL and no need to do the relocate while the space size
0x10000(64KB) may not enough for SPL.
After this update, the BL31 can use the rest 768KB of the first 1MB,
which is also enough, and the loader who is using BL31 elf file can
support this update without any change.

Change-Id: I66dc685594d77f10f9a49c3be015fd6729250ece
Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>rockchip: Fix typo for TF content text</title>
<updated>2019-09-20T00:42:32Z</updated>
<author>
<name>Kever Yang</name>
</author>
<published>2019-09-20T00:40:54Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/atf/commit/?id=382ddb3dd46ada0d7439d2d95bb0de3b3abb6d9d'/>
<id>urn:sha1:382ddb3dd46ada0d7439d2d95bb0de3b3abb6d9d</id>
<content type='text'>
The 'txet' should be 'text'.

Change-Id: I2217a1adf50c3b86f3087b83c77d9291b280627c
Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>rockchip: px30: support px30</title>
<updated>2019-07-09T09:07:13Z</updated>
<author>
<name>XiaoDong Huang</name>
</author>
<published>2019-06-13T02:55:50Z</published>
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<id>urn:sha1:010d6ae3388ef63f2a2afcd408c1dc461fb43583</id>
<content type='text'>
px30 is a Quad-core soc and Cortex-a53 inside.
This patch supports the following functions:
1. basic platform setup
2. power up/off cpus
3. suspend/resume cpus
4. suspend/resume system
5. reset system
6. power off system

Change-Id: I73d55aa978096c078242be921abe0ddca9e8f67e
Signed-off-by: XiaoDong Huang &lt;derrick.huang@rock-chips.com&gt;
</content>
</entry>
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