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<title>bcm63xx/atf/plat/rockchip/rk3368, branch master</title>
<subtitle>Broadcom-s Trusted Firmware A</subtitle>
<id>https://git.openwrt.org/project/bcm63xx/atf/atom?h=master</id>
<link rel='self' href='https://git.openwrt.org/project/bcm63xx/atf/atom?h=master'/>
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<updated>2019-09-20T00:42:53Z</updated>
<entry>
<title>rockchip: Update BL31_BASE to 0x40000</title>
<updated>2019-09-20T00:42:53Z</updated>
<author>
<name>Kever Yang</name>
</author>
<published>2019-09-19T02:37:36Z</published>
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<id>urn:sha1:0aad563c74807195cc7fe2208d17e2d889157f1e</id>
<content type='text'>
Rockchip platform is using the first 1MB of DRAM as secure ram space,
and there is a vendor loader who loads and runs the BL31/BL32/BL33,
this loader is usually load by SoC BootRom to the start addres of DRAM,
we need to reserve enough space for this loader so that it doesn't need
to do the relocate when loading the BL31. eg.
We use U-Boot SPL to load ATF BL31 and U-Boot proper as BL33, the SPL
TEXT BASE is offset 0 of DRAM which is decide by Bootrom; if we update
the BL31_BASE to offset 0x40000(256KB), then the 0~0x40000 should be
enough for SPL and no need to do the relocate while the space size
0x10000(64KB) may not enough for SPL.
After this update, the BL31 can use the rest 768KB of the first 1MB,
which is also enough, and the loader who is using BL31 elf file can
support this update without any change.

Change-Id: I66dc685594d77f10f9a49c3be015fd6729250ece
Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>rockchip: Fix typo for TF content text</title>
<updated>2019-09-20T00:42:32Z</updated>
<author>
<name>Kever Yang</name>
</author>
<published>2019-09-20T00:40:54Z</published>
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<id>urn:sha1:382ddb3dd46ada0d7439d2d95bb0de3b3abb6d9d</id>
<content type='text'>
The 'txet' should be 'text'.

Change-Id: I2217a1adf50c3b86f3087b83c77d9291b280627c
Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>plat/rockchip: Use new bl31_params_parse_helper()</title>
<updated>2019-07-24T18:04:03Z</updated>
<author>
<name>Julius Werner</name>
</author>
<published>2019-05-30T23:57:15Z</published>
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<id>urn:sha1:3e02c7436cf40fb7f7eb4d3038b7fc1ed1eeaa5f</id>
<content type='text'>
The Rockchip platform is a prime candidate for switching to the new
bl31_params_parse_helper(), so switch it over. This will allow BL2
implementations on this platform to transparently switch over to the
version 2 parameter structure.

Change-Id: I540741d2425c93f66c8697ce749a351eb2b3a7e8
Signed-off-by: Julius Werner &lt;jwerner@chromium.org&gt;
</content>
</entry>
<entry>
<title>plat/rockchip: Switch to use new common BL aux parameter library</title>
<updated>2019-07-24T03:25:30Z</updated>
<author>
<name>Julius Werner</name>
</author>
<published>2019-05-25T03:37:58Z</published>
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<id>urn:sha1:c1185ffde17cf2fdf50aac172a0be9e2d7669fd0</id>
<content type='text'>
This patch changes all Rockchip platforms to use the new common BL aux
parameter helpers. Since the parameter space is now cleanly split in
generic and vendor-specific parameters and the COREBOOT_TABLE
parameter is now generic, the parameter type number for that parameter
has to change. Since it only affects coreboot which always builds TF as
a submodule and includes its headers directly to get these constants,
this should not cause any issues. In general, after this point, we
should avoid changing already assigned parameter type numbers whenever
possible.

Change-Id: Ic99ddd1e91ff5e5fe212fa30c793a0b8394c9dad
Signed-off-by: Julius Werner &lt;jwerner@chromium.org&gt;
</content>
</entry>
<entry>
<title>Update rockchip platform to not rely on undefined overflow behaviour</title>
<updated>2019-07-11T11:10:58Z</updated>
<author>
<name>Justin Chadwell</name>
</author>
<published>2019-07-03T13:11:28Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/atf/commit/?id=79ca7807cc00fb262b3c9e202f19dbbcb618f228'/>
<id>urn:sha1:79ca7807cc00fb262b3c9e202f19dbbcb618f228</id>
<content type='text'>
This consists of ensuring that the left operand of each shift is
unsigned when the operation might overflow into the sign bit.

Change-Id: Ib7fc54e4141cc4f1952a18241bc18671b36e2168
Signed-off-by: Justin Chadwell &lt;justin.chadwell@arm.com&gt;
</content>
</entry>
<entry>
<title>Remove MULTI_CONSOLE_API flag and references to it</title>
<updated>2019-06-28T09:52:48Z</updated>
<author>
<name>Ambroise Vincent</name>
</author>
<published>2019-04-04T08:13:28Z</published>
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<id>urn:sha1:5b6ebeec9c99f8d6a539d3b15e5dfb827891174a</id>
<content type='text'>
The new API becomes the default one.

Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec
Signed-off-by: Ambroise Vincent &lt;ambroise.vincent@arm.com&gt;
</content>
</entry>
<entry>
<title>rockchip: Disable binary generation for all SoCs.</title>
<updated>2019-05-02T10:27:19Z</updated>
<author>
<name>Christoph Müllner</name>
</author>
<published>2019-04-24T07:52:54Z</published>
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<id>urn:sha1:33218d2a8143ef54684db529f1a8a5182e5a52f7</id>
<content type='text'>
All supported Rockchip SoCs (RK3288, RK3328, RK3368 and RK3399)
have non-continuous memory areas in the linker script with a huge
gap between them. This results in extremely padded binary images
with a size of about 4 GiB.

E.g. on the RK3399 we have the following memory areas (and base addresses):
RAM (0x1000), SRAM (0xFF8C0000), and PMUSRAM (0xFF3B0000).

Consumers of the TF-A project (e.g. coreboot or U-Boot) therefore
use the ELF image instead, which has a size of a few hundred kBs.

In order to prevent the generation of a huge and useless file,
this patch disables the binary generation for all affected Rockchip
SoCs.

Signed-off-by: Christoph Müllner &lt;christophm30@gmail.com&gt;
Change-Id: I4ac65bdf1e598c3e1a59507897d183aee9a36916
</content>
</entry>
<entry>
<title>rockchip: Streamline and complete UARTn_BASE macros.</title>
<updated>2019-05-01T00:15:43Z</updated>
<author>
<name>Christoph Müllner</name>
</author>
<published>2019-04-30T23:37:58Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/atf/commit/?id=0957b9b2717d314fc669b22542e8329d48f178ef'/>
<id>urn:sha1:0957b9b2717d314fc669b22542e8329d48f178ef</id>
<content type='text'>
In order to set the UART base during bootup in common code of
plat/rockchip, we need to streamline the way the UART base addresses
are defined and add the missing definitions and mappings.

This patch does so by following the pattern UARTn_BASE, which is
already in use on RK3399 and RK3328. The numbering itself is derived
from the upstream Linux DTS files of the individual SoCs.

Signed-off-by: Christoph Müllner &lt;christophm30@gmail.com&gt;
Change-Id: I341a1996f4ceed5f82a2f6687d4dead9d7cc5c1f
</content>
</entry>
<entry>
<title>rockchip: only include libfdt in non-coreboot cases</title>
<updated>2019-04-26T21:36:17Z</updated>
<author>
<name>Heiko Stuebner</name>
</author>
<published>2019-04-24T18:26:51Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/atf/commit/?id=4200e5aae7c70c728bc9c2e1d8d45223a3f7c614'/>
<id>urn:sha1:4200e5aae7c70c728bc9c2e1d8d45223a3f7c614</id>
<content type='text'>
While mainline u-boot always expects to submit the devicetree
as platform param, coreboot always uses the existing parameter
structure. As libfdt is somewhat big, it makes sense to limit
its inclusion to where necessary and thus only to non-coreboot
builds.

libfdt itself will get build in all cases, but only the non-
coreboot build will actually reference and thus include it.

Signed-off-by: Heiko Stuebner &lt;heiko@sntech.de&gt;
Change-Id: I4c5bc28405a14e6070917e48a526bfe77bab2fb7
</content>
</entry>
<entry>
<title>rockchip: move pmusram assembler code to a aarch64 subdir</title>
<updated>2019-04-25T11:37:56Z</updated>
<author>
<name>Heiko Stuebner</name>
</author>
<published>2019-03-05T12:46:41Z</published>
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<id>urn:sha1:c3aaabaf7e66e56323167d282fd6848b7ade8ae2</id>
<content type='text'>
The current code doing power-management from sram is highly
arm64-specific so should live in a corresponding subdirectory
and not in the common area.

Signed-off-by: Heiko Stuebner &lt;heiko@sntech.de&gt;
Change-Id: I3b79ac26f70fd189d4d930faa6251439a644c5d9
</content>
</entry>
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