bcm63xx/atf/plat/ti, branch master

ti: k3: common: Trap all asynchronous bus errors to EL3

2019-07-04T16:14:46Z

These errors are asynchronous and cannot be directly correlated with the exact current running software, so handling them in the same EL is not critical. Handling them in TF-A allows for more platform specific decoding of the implementation defined exception registers Signed-off-by: Andrew F. Davis Change-Id: Iee7a38c9fc9c698fa0ad42dafa598bcbed6a4fda

Remove MULTI_CONSOLE_API flag and references to it

2019-06-28T09:52:48Z

The new API becomes the default one. Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec Signed-off-by: Ambroise Vincent

ti: k3: common: Remove coherency workaround for AM65x

2019-06-06T10:20:26Z

We previously left our caches on during power-down to prevent any non-caching accesses to memory that is cached by other cores. Now with the last accessed areas all being marked as non-cached by USE_COHERENT_MEM we can rely on that to workaround our interconnect issues. Remove the old workaround. Change-Id: Idadb7696d1449499d1edff4f6f62ab3b99d1efb7 Signed-off-by: Andrew F. Davis

ti: k3: common: Use coherent memory for shared data

2019-06-06T10:20:21Z

HW_ASSISTED_COHERENCY implies something stronger than just hardware coherent interconnect, specifically a DynamIQ capable ARM core. For K3, lets use WARMBOOT_ENABLE_DCACHE_EARLY to enable caches early and then let the caches get shut off on powerdown, to prevent data corruption we also need to USE_COHERENT_MEM so that any accesses to shared memory after this point is only to memory that is set as non-cached for all cores. Change-Id: Ib9337f012df0e0388237942607c501b6f3e2a949 Signed-off-by: Andrew F. Davis

ti: k3: common: Set L2 latency on A72 cores

2019-05-22T17:07:52Z

The Cortex-A72 based cores on K3 platforms can be clocked fast enough that an extra latency cycle is needed to ensure correct L2 access. Set the latency here for all A72 cores. Signed-off-by: Andrew F. Davis Change-Id: Id534316dec1c1f326908efbfd964f219cda7386a

ti: k3: common: Add support for J721E

2019-05-22T17:07:52Z

Enable Cortex-A72 support for J721E. Change-Id: I5bea5fb6ec45d1a9f8f2192d42da2cc03ae0f7ec Signed-off-by: Nishanth Menon Signed-off-by: Andrew F. Davis

ti: k3: common: Remove MSMC port definitions

2019-04-30T13:41:06Z

The MSMC port defines were added to help in the case when some ports are not connected and have no cores attached. We can get the same functionality by defined the number of cores on that port to zero. This simplifies several code paths, do this here. Signed-off-by: Andrew F. Davis Change-Id: I3247fe37af7b86c3227e647b4f617fab70c8ee8a

ti: k3: common: Mark sections for AM65x coherency workaround

2019-04-26T15:52:25Z

These sections of code are only needed for the coherency workaround used for AM65x, if this workaround is not needed then this code is not either. Mark it off to keep it separated from the rest of the PSCI implementation. Signed-off-by: Andrew F. Davis Change-Id: I113ca6a2a1f7881814ab0a64e5bac57139bc03ef

ti: k3: common: Allow USE_COHERENT_MEM for K3

2019-04-26T15:50:13Z

To make the USE_COHERENT_MEM option work we need to add an entry for the area to our memory map table. Also fixup the alignment here. Signed-off-by: Andrew F. Davis Change-Id: I1c05477a97646ac73846a711bc38d3746628d847

ti: k3: common: Fix RO data area size calculation

2019-04-26T15:45:50Z

The size of the RO data area was calculated by subtracting the area end address from itself and not the base address due to a typo. Fix this here. Note, this was noticed at a glance thanks to the new aligned formating of this table. Signed-off-by: Andrew F. Davis Change-Id: I994022ac9fc95dc5e37a420714da76081c61cce7