bcm63xx/u-boot/arch/arc/lib, branch master

CONFIG_SPL_SYS_[DI]CACHE_OFF: add

2019-05-18T12:15:35Z

While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin Signed-off-by: Trevor Woerner [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini

ARC: Fix iteration in arc_xx_version()

2019-01-25T05:40:53Z

"i" gets incremented before we're entering loop body and effectively we iterate from 1 to 8 instead of 0 to 7. This way we: a) Skip the first line of struct hs_versions b) Go over it and access memory beyond the structure Signed-off-by: Alexey Brodkin

ARC: Improve identification of ARC cores

2018-12-03T11:26:18Z

1. Try to guess a ARC core template that was used i.e. not just name a core family but something more menaingful like "ARC HS38", "ARC EM11D" etc. We do it checking availability of the key differentiation features like: - Caches (we actually only check for L1 I$ fpr simplicity) - XY-memory - DSP extensions etc. 2. Identify ARC subsystems 3. Print core clock frequency Signed-off-by: Alexey Brodkin

ARC: make generic print_cpuinfo() weak

2018-10-12T12:14:40Z

This allows board to override print_cpuinfo() because they might know better which ARChitect template was used. This way we may not only derive base architecture type and version but more meaningful things like "ARC EM7D" instead of simple "ARC EM", "ARC HS36" instead of "ARC HS". Signed-off-by: Alexey Brodkin

ARC: Implement print_cpuinfo()

2018-10-05T13:55:42Z

Once we enable DISPLAY_CPUINFO for ARC we'll see ARC core family and version printed on boot. Signed-off-by: Alexey Brodkin

ARC: Enable unaligned access in hardware if compiler uses it

2018-07-31T04:49:47Z

Even if ARC core might handle unaligned access to data this hardware feature by default is disabled. But GCC starting from 8.1.0 unconditionally uses it for ARC HS cores. Which leads to quite strange and fatal run-time failures like the one below if HW is not configured properly: | hsdk# sf probe | Misaligned data access exception @ 0xbff794d4 | ECR: 0x000d0000 | RET: 0xbff794d4 | BLINK: 0xbff79644 | STAT32: 0x00000800 | GP: 0x1003e000 r25: 0xbfd58f08 | BTA: 0xbff794a4 SP: 0xbfd58cd4 FP: 0xbfd58ef0 | LPS: 0xbff90240 LPE: 0xbff90244 LPC: 0x00000000 | r00: 0x00000000 r01: 0x00000003 r02: 0x000026bf | r03: 0x00000000 r04: 0x00000100 r05: 0x00000000 | r06: 0x00000001 r07: 0x00000000 r08: 0x1dcd6500 | r09: 0x00000000 r10: 0x00200000 r11: 0x00000000 | r12: 0x1b3d4440 r13: 0xbff9eca4 r14: 0xbfd59d68 | r15: 0xbfd60cd0 r16: 0x00000000 r17: 0x00000000 | r18: 0xbff9ed14 r19: 0xbfd59c78 r20: 0xbfd58d40 | r21: 0xbfd58d44 r22: 0x00000000 r23: 0x00000000 | r24: 0xbfd59ba8 | Resetting CPU ... Now we're checking for __ARC_UNALIGNED__ define emitted by the compiler if it's going to use unaligned access and then we force-enable it in hardware too. Signed-off-by: Alexey Brodkin

ARC: Reset: Implement weak reset_cpu()

2018-05-31T17:13:29Z

This will allow for board-specific implementation of reset. Default version will just stop execution with help of BRK instruction. Signed-off-by: Alexey Brodkin

ARC: Reset: Use __builtin_arc_brk() instead of open-coded ASM

2018-05-31T17:13:29Z

For quite some time we have a GCC's built-in which inserts BRK instruction so let's use it instead of simple insertion of in-line assembly. Signed-off-by: Alexey Brodkin

ARC: Improve relocation fix-ups

2018-05-31T17:13:29Z

We used to have the one and only linker script for all ARC boards and so we relied on a particular order of symbols there. Because of that we used __ivt_end as the marker of the end of all the code which won't be true any longer if we move .ivt section to any other place. That said we'd better check for each section separately. A couple of other improvements: 1. There's no point to include the marker of section end in interested range because its address is beyond the section, i.e. we should compare with "<" but not "<=". 2. .ivt section for ARCv2 cores is just an array of 32-bit ints and they are not swapped even on little-endia cores while in case of ARCompact cores .ivt contains valid code so swapping is required. 3. Just in case add check for ARC600 which is also ARCompact and its .ivt is normal code. Signed-off-by: Alexey Brodkin

ARC: Cache: Don't compare I$ and D$ line lengths

2018-05-31T17:13:29Z

We don't care much about I$ line length really as there're no per-line ops on I$ instead we only do full invalidation of it on occasion of relocation and right before jumping to the OS. Also as compared to Linux kernel where we don't support different lengths of I$ and D$ lines in U-Boot we have to deal with such an exotic configs if the target board is not supposed to run Linux kernel. Signed-off-by: Alexey Brodkin