bcm63xx/u-boot/arch/arm/cpu, branch master

armv8: fix typo in LINUX_KERNEL_IMAGE_HEADER check

2019-06-20T14:57:08Z

Fixes: 8163faf952 ARMv8: add optional Linux kernel image header Signed-off-by: Mian Yousaf Kaukab Reviewed-by: Stephen Warren Tested-by: Andreas Färber

armv8: ls1046afrwy: Add support for LS1046AFRWY platform

2019-06-19T07:24:57Z

LS1046AFRWY board supports LS1046A family SoCs. This patch add base support for this board. Board support's 4GB ddr memory, i2c, micro-click module,microSD card, serial console,qspi nor flash,ifc nand flash,qsgmii network interface, usb 3.0 and serdes interface to support two x1gen3 pcie interface. Signed-off-by: Camelia Groza Signed-off-by: Madalin Bucur Signed-off-by: Pankit Garg Signed-off-by: Pramod Kumar Signed-off-by: Rajesh Bhagat Signed-off-by: Vabhav Sharma Reviewed-by: Prabhakar Kushwaha

armv8: fsl-lsch2: add clock support for the second eSDHC

2019-06-19T07:24:57Z

Layerscape began to use two eSDHC controllers, for example, LS1012A. They are same IP block with same reference clock. This patch is to add clock support for the second eSDHC. Signed-off-by: Yinbo Zhu Reviewed-by: Prabhakar Kushwaha

arm: fsl-layerscape: add 0x3040 serdes1 settings for LS1046A

2019-06-19T07:24:57Z

Signed-off-by: Maciej Pijanowski Cc: piotr.krol@3mdeb.com Reviewed-by: Prabhakar Kushwaha

arm: fsl-layerscape: fix 0x3363 serdes1 settings for ls1046a

2019-06-19T07:24:57Z

As per LS1046A hardware manual, SGMII.9 and SGMII.10 present on lane D and lane C respectively for 0x3363 protocol. So fix serdes1 settings for ls1046a. Signed-off-by: Maciej Pijanowski Reviewed-by: Prabhakar Kushwaha

armv8: fsl-layerscape: fix config dependency for layerscape pci code

2019-06-19T07:24:57Z

Fixes a link error on layerscape platform, linking fails with CONFIG_PCI set and CONFIG_PCI_LAYERSCAPE unset. Signed-off-by: Alex Marginean Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha

armv8: fsl-layerscape: Change bootcmd update logic

2019-06-19T07:24:57Z

Change bootcmd update logic when CONFIG_ENV_ADDR is not defined Signed-off-by: Pankit Garg Reviewed-by: Prabhakar Kushwaha

armv8: fsl-layerscape: Update qspi clk cfg

2019-06-19T07:24:57Z

Update qspi clock configuration in TFABOOT in case of all boot sources except qspi boot source. Signed-off-by: Pankit Garg Reviewed-by: Prabhakar Kushwaha

armv8/fsl-layerscape: Add loop to check L3 dcache status

2019-06-19T07:24:57Z

Flushing L3 cache may need variable time depending upon cache line allocation. Coming up with a proper timeout value would be best handled by simulations under multiple scenarios in your actual system. >From the purely HN-F point of view, the flush would take ~15 cycles for a clean line, and ~22 cycles for a dirty line. For the dirty line case, there are many variables outside the HN-F that will increase the duration per line. For example, a *DBIDResp from the SN-F/SBSX, memory controller latency, SN-F/SBSX RetryAck responses, CCN ring congestion, CCN ring hops, etc, etc. The worst-case timeout would have to factor in all of these variables plus the HN-F cycles for every line in the L3, and assuming all lines are dirty In case if L3 is not flushed properly, system behaviour will be erratic, so remove timeout and add loop to check status of L3 cache. System will stuck in while loop if there is some issue in L3 cache flushing. Signed-off-by: Udit Kumar Signed-off-by: Meenakshi Aggarwal Reviewed-by: Prabhakar Kushwaha

armv8: fsl-lsch3: add clock support for the second eSDHC

2019-06-19T07:24:56Z

Layerscape began to use two eSDHC controllers, for example, LS1028A. They are same IP block with same reference clock. This patch is to add clock support for the second eSDHC. Signed-off-by: Yangbo Lu Signed-off-by: Yinbo Zhu Reviewed-by: Prabhakar Kushwaha