bcm63xx/u-boot/arch/arm/include/asm/arch-meson, branch masterBroadcom-s U-Boothttps://git.openwrt.org/project/bcm63xx/u-boot/atom?h=master2019-05-09T08:38:32Zmach-meson: g12a: add DWC2 peripheral mode support2019-05-09T08:38:32ZNeil Armstrong2019-02-19T13:21:04Zurn:sha1:92d911b2eedec8fee1f494ab961585e253351d4f
Adds support for Amlogic G12A USB Device mode.
The DWC2 Controller behind the Glue can be connected to an OTG
capable PHY. The Glue setups the PHY mode.
This patch implements Device mode support by adding a board_usb_init/cleanup
setting up the DWC2 controller and switch the OTG capable port to Device
before starting the DWC2 controller in Device mode.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
ARM: meson: add G12a support2019-04-23T09:19:09ZJerome Brunet2019-02-08T15:23:20Zurn:sha1:17b7efe25bef6286e949ebdd7fc416a011485dfb
Add support for the Amlogic G12A SoC, which is a mix between the
new physical memory mapping of AXG and the functionnalities of
the previous Amlogic GXL/GXM SoCs.
To handle the internal ethernet PHY, the Amlogic G12A SoCs now
embeds a dedicated PLL to feed the internal PHY.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
clk: meson: add g12a support2019-04-23T09:19:09ZJerome Brunet2019-02-11T15:45:01Zurn:sha1:912af8423f3ee02497f98b1373b6291fcf611e0d
Add basic support for the Amlogic G12A clock controller based on
the AXG driver.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
video: Add Meson Video Processing Unit Driver2019-01-31T08:35:01ZNeil Armstrong2018-07-24T15:45:28Zurn:sha1:3bed42209404f91f3e0efaf7f9b3c9a989beb922
This adds video output support for Amlogic GXBB/GXL/GXM chips.
The supported ports are CVBS and HDMI (based on DW_HDMI).
When using HDMI, only DMT modes are supported.
There is support for simple-framebuffer (CONFIG_VIDEO_DT_SIMPLEFB)
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jorge Ramire-Ortiz <jramirez@baylibre.com>
Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
[narmstrong: fixed defines alignment in meson_canvas.c]
Reviewed-by: Anatolij Gustschin <agust@denx.de>
ARM: meson: Add boot device discovery2018-11-26T13:40:52ZNeil Armstrong2018-07-27T12:10:00Zurn:sha1:d96a782d09dbdc4a28ece3d18dc17a572e39d4f2
The Amlogic Meson SoCs ROM supports a boot over USB with a custom protocol.
When no other boot medium are available (or by forcing the USB mode), the
ROM sets the primary USB port as device mode and waits for a Host to
enumerate.
When enumerated, a custom protocol described at [1] permits writing to
memory and execute some specific FIP init code to run the loaded
Arm Trusted Firmware BL2 and BL3 stages before running the BL33 stage.
In this mode, we can load different binaries that can be used by U-boot
like a script image file.
This adds support for a custom USB boot stage only available when the
boot mode is USB and the script file at a pre-defined address is valid.
This support was heavily copied from the Sunxi Allwinner FEL U-Boot support.
The tool pyamlboot described at [2], permits using this boot mode on boards
exposing the first USB port, either as OTG or Host port.
[1] https://github.com/superna9999/pyamlboot/blob/master/PROTOCOL.md
[2] https://github.com/superna9999/pyamlboot/blob/master/README.md
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
clk: Add clock driver for AXG2018-11-26T13:40:52ZNeil Armstrong2018-09-07T15:25:13Zurn:sha1:f6eb68b978fdb9b109ece3c71e2cc19d041103c5
This patch adds a minimal clock driver for the Amlogic AXG SoC to handle
the basic gates and PLLs.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
ARM: meson: Add support for AXG family2018-11-26T13:40:52ZNeil Armstrong2018-09-05T13:56:12Zurn:sha1:485bba395e00a3a9a250ae1d02abb9cff314e8e7
This patch adds support for the Amlogic AXG SoC, which is very close from
the Amlogic GXL SoCs with :
- Same 4xCortex-A53 CPUs but clocked at 1.2GHZ max
- DDR Interface limited to DDR4 16bit
- The whole physical register address space has been moved to 0xfxxxxxxx
- The pinctrl setup has changed
- The clock tree is different enough to use a different driver
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
ARM: meson: rework soc arch file to prepare for new SoC2018-11-26T13:40:52ZJerome Brunet2018-10-05T15:00:37Zurn:sha1:33e3378091391c90a110d93f4c89044b4461fb99
We are about to add support for the Amlogic AXG SoC. While very close to
the Gx SoC family, we will need to handle a few thing which are different
in this SoC. Rework the meson arch directory to prepare for this.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
meson: use the clock driver2018-06-19T11:31:47ZBeniamino Galvani2018-06-14T11:43:40Zurn:sha1:2e668af5531815dc6a6190cf6490b866da71ffaa
Use the clk framework to initialize clocks from drivers that need them
instead of having hardcoded frequencies and initializations from board
code.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
clk: add Amlogic meson clock driver2018-06-19T11:31:47ZBeniamino Galvani2018-06-14T11:43:39Zurn:sha1:c0fc1e215c6117b159bb9ca736d3e3338bbc028b
Introduce a basic clock driver for Amlogic Meson SoCs which supports
enabling/disabling clock gates and getting their frequency.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>