bcm63xx/u-boot/arch/arm/include/asm/arch-sunxi, branch master

arm: sunxi: h6: fix reset using r_wdog

2019-05-20T16:54:47Z

Some H6 boards have a watchdog which didn't make the SoC reboot properly. Reason is still unknown but several people have test it. Chen-Yu Tsai : Pine H64 = H6 V200-AWIN H6448BA 7782 => OK OrangePi Lite 2 = H6 V200-AWIN H8068BA 61C2 => KO Martin Ayotte : Pine H64 = H8069BA 6892 => OK OrangePi 3 = HA047BA 69W2 => KO OrangePi One Plus = H7310BA 6842 => KO OrangePi Lite2 = H6448BA 6662 => KO Clément Péron: Beelink GS1 = H6 V200-AWIN H7309BA 6842 => KO After the series of result, Icenowy try to reach Allwinner about this issue but they seems not interested to investigate it. As we don't have the ARIS coproc to do power management and watchdogis the only solution to reset the board. So, Change from watchdog to R_watchdog to allow a reboot on all H6 boards. Signed-off-by: Clément Péron Reviewed-by: Jagan Teki

sunxi: Allow booting from 128KB SD/eMMC offset

2019-04-10T10:04:32Z

On modern Allwinner SoCs (tested: H2+, A64, H5, H6) the BootROM can actually load the SPL also from sector 256 (128KB) of an SD card or eMMC chip. For more details, see [1]. In this case the boot source indicator (written at offset 0x28 of SRAM A1) has bit 4 set, so it's 0x10 for SD card and 0x12 for eMMC. Add those new values to the existing boot source check to allow booting the SPL from those "high" disk offsets as well. For this to work, the value of CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR needs to be adjusted, for instance to 0x140 (right after the high SPL). Doing this dynamically sounds desirable, but looks nasty to implement. [1] https://groups.google.com/forum/#!topic/linux-sunxi/MaiijyaAFjk Signed-off-by: Andre Przywara Acked-by: Maxime Ripard

reset: Add Allwinner RESET driver

2019-01-18T16:49:08Z

Add common reset driver for all Allwinner SoC's. Since CLK and RESET share common DT compatible, it is CLK driver job is to bind the reset driver. So add CLK bind call on respective SoC driver by passing ccu map descriptor so-that reset deassert, deassert operations held based on ccu reset table defined from CLK driver. Select DM_RESET via CLK_SUNXI, this make hidden section of RESET since CLK and RESET share common DT compatible and code. Signed-off-by: Jagan Teki Acked-by: Maxime Ripard

clk: Add Allwinner A64 CLK driver

2019-01-18T16:49:08Z

Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki Acked-by: Maxime Ripard

sunxi: board: Add i2c initialization for sun50i

2019-01-18T16:49:08Z

To use TWI0/1/2 the user can select CONFIG_I2C#_ENABLE. However even the controller is enabled, the mux for the pins are not set. This patch follows the existing mux method. Since the pads are different, separate check is added for each i2c. Tested with A64-SOM204 board. Signed-off-by: Stefan Mavrodiev Acked-by: Maxime Ripard Reviewed-by: Jagan Teki

sun50i: A64: add support for R_I2C controller

2018-11-13T16:39:10Z

Allwinner A64 has a I2C controller, which is in the R_ MMIO zone and has two groups of pinmuxes on PL bank, so it's called R_I2C. Add support for this I2C controller and the pinmux which doesn't conflict with RSB. Signed-off-by: Vasily Khoruzhick Acked-by: Maxime Ripard Tested-by: Maxime Ripard Cc: Vagrant Cascadian Acked-by: Jagan Teki

mmc: sunxi: add support for automatic delay calibration

2018-11-13T16:37:39Z

A64 and H6 support automatic delay calibration and Linux driver uses it instead of hardcoded delays. Add support for it to u-boot driver. Fixes eMMC instability on Pinebook Signed-off-by: Vasily Khoruzhick Acked-by: Maxime Ripard Tested-by: Maxime Ripard Reviewed-by: Andre Przywara Cc: Vagrant Cascadian Reviewed-by: Jagan Teki

sunxi: store DRAM size in SPL header

2018-10-29T15:11:15Z

At the moment we rely on the infamous get_ram_size() function to learn the actual DRAM size in U-Boot proper. This function has two issues: 1) It only works if the DRAM size is a power of two. We start to see boards which have 3GB of (usable) DRAM, so this does not fit anymore. 2) As U-Boot has no notion of reserved memory so far, it will happily ride through the DRAM, possibly stepping on secure-only memory. This could be a region of DRAM reserved for OP-TEE or some other secure payload, for instance. It will most likely crash in that case. As the SPL DRAM init routine has very accurate knowledge of the actual DRAM size, lets propagate this wisdom to U-Boot proper. We re-purpose a currently reserved word in our SPL header for that. The SPL itself stores the detected DRAM size there, and bumps the SPL header version number in that case. U-Boot proper checks for a valid SPL header and a high enough version number, then uses the DRAM size from there. If the SPL header field is not sufficient, we fall back to the old DRAM scanning routine. Part of the DRAM might be present and probed by SPL, but not accessible by the CPU. They're restricted in the main U-Boot binary, when accessing the DRAM size from SPL header. Signed-off-by: Andre Przywara Signed-off-by: Icenowy Zheng Acked-by: Maxime Ripard Reviewed-by: Jagan Teki

sunxi: Extend SPL header versioning

2018-10-29T15:11:15Z

On Allwinner SoCs we use some free bytes at the beginning of the SPL image to store various information. We have a version byte to allow updates, but changing this always requires all tools to be updated as well. Introduce the concept of semantic versioning [1] to the SPL header: The major part of the version number only changes on incompatible updates, a minor number bump indicates backward compatibility. This patch just documents the major/minor split, adds some comments to the header file and uses the versioning information for the existing users. [1] https://semver.org Signed-off-by: Andre Przywara Signed-off-by: Icenowy Zheng Acked-by: Maxime Ripard Acked-by: Jagan Teki

sunxi: fix sid base address macro name for H6

2018-08-20T11:52:59Z

In the current H6 CPU memory space code, the SUNXI in the macro name of the SID address base is wrongly spelled as SNUXI, which leads to SID readout not working. Fix this macro name. Fixes: 55f6b1c351c9 ("sunxi: add basic memory map definitions of H6 SoC") Signed-off-by: Icenowy Zheng Reviewed-by: Jagan Teki